├── bench └── verilog │ ├── test_bench_top.v │ ├── tests.v │ ├── wb_mast_model.v │ ├── wb_model_defines.v │ └── wb_slv_model.v ├── doc ├── README.txt ├── STATUS.txt └── dma_doc.pdf ├── rtl └── verilog │ ├── wb_dma_ch_arb.v │ ├── wb_dma_ch_pri_enc.v │ ├── wb_dma_ch_rf.v │ ├── wb_dma_ch_sel.v │ ├── wb_dma_de.v │ ├── wb_dma_defines.v │ ├── wb_dma_inc30r.v │ ├── wb_dma_pri_enc_sub.v │ ├── wb_dma_rf.v │ ├── wb_dma_top.v │ ├── wb_dma_wb_if.v │ ├── wb_dma_wb_mast.v │ └── wb_dma_wb_slv.v ├── sim └── rtl_sim │ └── bin │ └── Makefile └── syn └── bin ├── comp.dc ├── design_spec.dc ├── lib_spec.dc └── read.dc /bench/verilog/test_bench_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/wb_dma/HEAD/bench/verilog/test_bench_top.v -------------------------------------------------------------------------------- /bench/verilog/tests.v: -------------------------------------------------------------------------------- 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