├── README.TXT ├── doc ├── drawings.odg ├── xge_mac_spec.odt └── xge_mac_spec.pdf ├── rtl ├── auto_verilog.sh ├── custom.el ├── include │ ├── CRC32_D64.v │ ├── CRC32_D8.v │ ├── defines.v │ ├── timescale.v │ └── utils.v └── verilog │ ├── fault_sm.v │ ├── generic_fifo.v │ ├── generic_fifo_ctrl.v │ ├── generic_mem_medium.v │ ├── generic_mem_small.v │ ├── meta_sync.v │ ├── meta_sync_single.v │ ├── rx_data_fifo.v │ ├── rx_dequeue.v │ ├── rx_enqueue.v │ ├── rx_hold_fifo.v │ ├── sync_clk_core.v │ ├── sync_clk_wb.v │ ├── sync_clk_xgmii_tx.v │ ├── tx_data_fifo.v │ ├── tx_dequeue.v │ ├── tx_enqueue.v │ ├── tx_hold_fifo.v │ ├── wishbone_if.v │ └── xge_mac.v ├── sim ├── systemc │ ├── compile.sh │ ├── run.sh │ ├── sc.mk │ └── verilator.cmd └── verilog │ └── sim.do └── tbench ├── systemc ├── crc.cpp ├── crc.h ├── sc_cpu_if.cpp ├── sc_cpu_if.h ├── sc_main.cpp ├── sc_packet.cpp ├── sc_packet.h ├── sc_pkt_generator.cpp ├── sc_pkt_generator.h ├── sc_pkt_if.cpp ├── sc_pkt_if.h ├── sc_scoreboard.cpp ├── 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