├── stm32f10x_lib ├── CMSIS │ ├── License.doc │ ├── CMSIS debug support.htm │ ├── Documentation │ │ └── CMSIS_Core.htm │ ├── CM3 │ │ └── DeviceSupport │ │ │ └── ST │ │ │ └── STM32F10x │ │ │ ├── stm32f10x.h │ │ │ ├── system_stm32f10x.h │ │ │ └── startup │ │ │ └── gcc_ride7 │ │ │ ├── startup_stm32f10x_ld.s │ │ │ ├── startup_stm32f10x_md.s │ │ │ ├── startup_stm32f10x_ld_vl.s │ │ │ └── startup_stm32f10x_md_vl.s │ └── CMSIS_changes.htm └── STM32F10x_StdPeriph_Driver │ ├── src │ ├── stm32f10x_flash.c │ ├── stm32f10x_i2c.c │ ├── stm32f10x_usart.c │ ├── stm32f10x_crc.c │ ├── stm32f10x_iwdg.c │ ├── stm32f10x_dbgmcu.c │ ├── stm32f10x_wwdg.c │ ├── misc.c │ ├── stm32f10x_exti.c │ ├── stm32f10x_bkp.c │ ├── stm32f10x_pwr.c │ ├── stm32f10x_rtc.c │ └── stm32f10x_cec.c │ ├── inc │ ├── stm32f10x_crc.h │ ├── stm32f10x_wwdg.h │ ├── stm32f10x_dbgmcu.h │ ├── stm32f10x_iwdg.h │ ├── stm32f10x_rtc.h │ ├── stm32f10x_pwr.h │ ├── stm32f10x_cec.h │ ├── stm32f10x_exti.h │ ├── stm32f10x_bkp.h │ └── misc.h │ └── stm32f10x_conf.h ├── .travis.yml ├── user ├── uart_log.h ├── main.c └── uart_log.c ├── .gitignore ├── LICENSE ├── makefile_std_lib.mk ├── README.md ├── Makefile └── stm32_flash.ld /stm32f10x_lib/CMSIS/License.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/CMSIS/License.doc -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CMSIS debug support.htm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/CMSIS/CMSIS debug support.htm -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/Documentation/CMSIS_Core.htm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/CMSIS/Documentation/CMSIS_Core.htm -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freelamb/stm32f10x_makefile_template/master/stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | language: c 2 | dist: trusty 3 | 4 | sudo: required 5 | 6 | before_install: 7 | - sudo apt-get -qq update 8 | - sudo apt-get install -y gcc-arm-none-eabi 9 | 10 | compiler: 11 | - arm-none-eabi-gcc 12 | 13 | script: 14 | - make 15 | 16 | notifications: 17 | email: true -------------------------------------------------------------------------------- /user/uart_log.h: -------------------------------------------------------------------------------- 1 | // 2 | // Created by YangYongbao on 2017/3/18. 3 | // 4 | 5 | #ifndef STM32F10X_MAKEFILE_TEMPLATE_UART_LOG_H 6 | #define STM32F10X_MAKEFILE_TEMPLATE_UART_LOG_H 7 | 8 | void uart_log_init(void); 9 | 10 | void debug(const char *format, ...); 11 | 12 | #endif //STM32F10X_MAKEFILE_TEMPLATE_UART_LOG_H 13 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.o 3 | *.ko 4 | *.obj 5 | *.elf 6 | *.lst 7 | 8 | # Precompiled Headers 9 | *.gch 10 | *.pch 11 | 12 | # Libraries 13 | *.lib 14 | *.a 15 | *.la 16 | *.lo 17 | 18 | # Shared objects (inc. Windows DLLs) 19 | *.dll 20 | *.so 21 | *.so.* 22 | *.dylib 23 | 24 | # Executables 25 | *.exe 26 | *.out 27 | *.app 28 | *.i*86 29 | *.x86_64 30 | *.hex 31 | 32 | # Debug files 33 | *.dSYM/ 34 | *.su 35 | .idea/ 36 | CMakeLists.txt 37 | bin/main.bin 38 | bin/main.map 39 | cmake-build-debug/ 40 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 Runmec 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /makefile_std_lib.mk: -------------------------------------------------------------------------------- 1 | 2 | # STD Defines 3 | DDEFS += -DSTM32F10X_MD_VL -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 4 | 5 | # source director 6 | STM32F1_STD_LIB = $(STM32F10x_LIB_DIR)/STM32F10x_StdPeriph_Driver 7 | STM32F1_CORE_DIR = $(STM32F10x_LIB_DIR)/CMSIS/CM3/CoreSupport 8 | STM32F1_DEVICE_DIR = $(STM32F10x_LIB_DIR)/CMSIS/CM3/DeviceSupport/ST/STM32F10x 9 | STM32F1_SRC_DIR = $(STM32F1_STD_LIB)/src 10 | STM32F1_INC_DIR = $(STM32F1_STD_LIB)/inc 11 | 12 | # startup 13 | ASM_SRC += $(STM32F1_DEVICE_DIR)/startup/gcc_ride7/startup_stm32f10x_md_vl.s 14 | 15 | # CMSIS 16 | STM32F10X_LIB_SRC += $(STM32F1_DEVICE_DIR)/system_stm32f10x.c 17 | STM32F10X_LIB_SRC += $(STM32F1_CORE_DIR)/core_cm3.c 18 | 19 | # use libraries, please add or remove when you use or remove it. 20 | STM32F10X_LIB_SRC += $(STM32F1_SRC_DIR)/stm32f10x_rcc.c 21 | STM32F10X_LIB_SRC += $(STM32F1_SRC_DIR)/stm32f10x_gpio.c 22 | STM32F10X_LIB_SRC += $(STM32F1_SRC_DIR)/stm32f10x_exti.c 23 | STM32F10X_LIB_SRC += $(STM32F1_SRC_DIR)/stm32f10x_usart.c 24 | STM32F10X_LIB_SRC += $(STM32F1_SRC_DIR)/misc.c 25 | 26 | # include directories 27 | INCLUDE_DIRS += $(STM32F1_CORE_DIR) 28 | INCLUDE_DIRS += $(STM32F1_DEVICE_DIR) 29 | INCLUDE_DIRS += $(STM32F1_INC_DIR) 30 | INCLUDE_DIRS += $(STM32F1_STD_LIB) 31 | 32 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32 Makefile Template 2 | 3 | [![Build Status](https://travis-ci.org/freelamb/stm32f10x_makefile_template.svg?branch=master)](https://travis-ci.org/freelamb/stm32f10x_makefile_template) 4 | 5 | ## Requirement 6 | 7 | Working GNU ARM GCC (https://launchpad.net/gcc-arm-embedded) 8 | 9 | Texane stlink to flash the STM32F10x (https://github.com/texane/stlink) 10 | 11 | 12 | ## Usage 13 | 14 | ### build project 15 | 16 | ``` 17 | $ make 18 | ``` 19 | 20 | ### clean project 21 | 22 | ``` 23 | $ make clean 24 | ``` 25 | 26 | ### download to mcu by stlink 27 | ``` 28 | $ make flash 29 | ``` 30 | 31 | ### erase flash 32 | ``` 33 | $ make erase 34 | ``` 35 | 36 | ### download main.bin to mcu 37 | ``` 38 | $ ./build.sh 39 | ``` 40 | 41 | ## Debug base on st-link 42 | 43 | start debug 44 | ``` 45 | $ st-util 46 | ``` 47 | 48 | open shell in project root dir 49 | ``` 50 | $ arm-none-eabi-gdb *.elf 51 | 52 | GNU gdb (GNU Tools for ARM Embedded Processors) 7.10.1.20160923-cvs 53 | Copyright (C) 2015 Free Software Foundation, Inc. 54 | License GPLv3+: GNU GPL version 3 or later 55 | This is free software: you are free to change and redistribute it. 56 | There is NO WARRANTY, to the extent permitted by law. Type "show copying" 57 | and "show warranty" for details. 58 | This GDB was configured as "--host=x86_64-apple-darwin10 --target=arm-none-eabi". 59 | Type "show configuration" for configuration details. 60 | For bug reporting instructions, please see: 61 | . 62 | Find the GDB manual and other documentation resources online at: 63 | . 64 | For help, type "help". 65 | Type "apropos word" to search for commands related to "word"... 66 | Reading symbols from z2_cmcc_b_app.elf...done. 67 | ... 68 | (gdb) target extended-remote :4242 69 | ... 70 | ``` 71 | 72 | Clion configure debug reference 73 | 74 | https://www.yuque.com/freelamb/iot_tech/aezu7s 75 | 76 | ## Example 77 | 78 | mcu: STM32F103C8T6 79 | 80 | GPIOB6--Led 81 | 82 | -------------------------------------------------------------------------------- /user/main.c: -------------------------------------------------------------------------------- 1 | // 2 | // Created by YangYongbao on 2017/3/16. 3 | // 4 | 5 | #include "stm32f10x.h" 6 | #include "stm32f10x_conf.h" 7 | #include "uart_log.h" 8 | 9 | void Delay(__IO uint32_t nCount) 10 | { 11 | for(; nCount != 0; nCount--); 12 | } 13 | 14 | void RCC_Configuration(void) 15 | { 16 | ErrorStatus HSEStartUpStatus; 17 | 18 | /* RCC system reset(for debug purpose) */ 19 | RCC_DeInit(); 20 | /* Enable HSE */ 21 | RCC_HSEConfig(RCC_HSE_ON); 22 | /* Wait till HSE is ready */ 23 | HSEStartUpStatus = RCC_WaitForHSEStartUp(); 24 | if (HSEStartUpStatus == SUCCESS) { 25 | /* HCLK = SYSCLK */ 26 | RCC_HCLKConfig(RCC_SYSCLK_Div1); 27 | /* PCLK2 = HCLK */ 28 | RCC_PCLK2Config(RCC_HCLK_Div1); 29 | /* PCLK1 = HCLK/2 */ 30 | RCC_PCLK1Config(RCC_HCLK_Div2); 31 | /* Enable PLL */ 32 | RCC_PLLCmd(ENABLE); 33 | /* Wait till PLL is ready */ 34 | while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); 35 | /* Select PLL as system clock source */ 36 | RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); 37 | /* Wait till PLL is used as system clock source */ 38 | while (RCC_GetSYSCLKSource() != 0x08); 39 | } 40 | } 41 | 42 | void GPIO_Configuration(void) 43 | { 44 | GPIO_InitTypeDef GPIO_InitStructure; 45 | 46 | /* GPIOB clock enable */ 47 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 48 | 49 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; 50 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 51 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 52 | GPIO_Init(GPIOB, &GPIO_InitStructure); 53 | } 54 | 55 | int main() { 56 | 57 | RCC_Configuration(); 58 | GPIO_Configuration(); 59 | 60 | // uart log init 61 | uart_log_init(); 62 | 63 | debug("start main"); 64 | 65 | while(1) { 66 | GPIO_ResetBits(GPIOB, GPIO_Pin_6); 67 | debug("open"); 68 | Delay(1000000); 69 | GPIO_SetBits(GPIOB, GPIO_Pin_6); 70 | debug("close"); 71 | Delay(1000000); 72 | } 73 | 74 | return 0; 75 | } -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /** @addtogroup CMSIS 23 | * @{ 24 | */ 25 | 26 | /** @addtogroup stm32f10x_system 27 | * @{ 28 | */ 29 | 30 | /** 31 | * @brief Define to prevent recursive inclusion 32 | */ 33 | #ifndef __SYSTEM_STM32F10X_H 34 | #define __SYSTEM_STM32F10X_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** @addtogroup STM32F10x_System_Includes 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | 49 | /** @addtogroup STM32F10x_System_Exported_types 50 | * @{ 51 | */ 52 | 53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_CRC_H 25 | #define __STM32F10x_CRC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup CRC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup CRC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup CRC_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup CRC_Exported_Macros 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup CRC_Exported_Functions 67 | * @{ 68 | */ 69 | 70 | void CRC_ResetDR(void); 71 | uint32_t CRC_CalcCRC(uint32_t Data); 72 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 73 | uint32_t CRC_GetCRC(void); 74 | void CRC_SetIDRegister(uint8_t IDValue); 75 | uint8_t CRC_GetIDRegister(void); 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | #endif /* __STM32F10x_CRC_H */ 82 | /** 83 | * @} 84 | */ 85 | 86 | /** 87 | * @} 88 | */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 95 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | 2 | # toolchain 3 | TOOLCHAIN = arm-none-eabi- 4 | CC = $(TOOLCHAIN)gcc 5 | CP = $(TOOLCHAIN)objcopy 6 | AS = $(TOOLCHAIN)gcc -x assembler-with-cpp 7 | HEX = $(CP) -O ihex 8 | BIN = $(CP) -O binary -S 9 | 10 | # define mcu, specify the target processor 11 | MCU = cortex-m3 12 | 13 | # all the files will be generated with this name (main.elf, main.bin, main.hex, etc) 14 | PROJECT_NAME=stm32f10x_makefile_template 15 | 16 | # specify define 17 | DDEFS = 18 | 19 | # define root dir 20 | ROOT_DIR = . 21 | 22 | # define include dir 23 | INCLUDE_DIRS = . 24 | 25 | # define stm32f10x lib dir 26 | STM32F10x_LIB_DIR = $(ROOT_DIR)/stm32f10x_lib 27 | 28 | # define user dir 29 | USER_DIR = $(ROOT_DIR)/user 30 | 31 | # link file 32 | LINK_SCRIPT = $(ROOT_DIR)/stm32_flash.ld 33 | 34 | # stm32f10x lib src 35 | STM32F10X_LIB_SRC = 36 | 37 | # user specific 38 | SRC = 39 | SRC += $(USER_DIR)/main.c 40 | SRC += $(USER_DIR)/uart_log.c 41 | 42 | ASM_SRC = 43 | 44 | # user include 45 | INCLUDE_DIRS += $(USER_DIR) 46 | 47 | # include sub makefiles 48 | include makefile_std_lib.mk # STM32 Standard Peripheral Library 49 | 50 | INC_DIR = $(patsubst %, -I%, $(INCLUDE_DIRS)) 51 | 52 | # run from Flash 53 | DEFS = $(DDEFS) -DRUN_FROM_FLASH=1 54 | 55 | OBJECTS = $(ASM_SRC:.s=.o) $(SRC:.c=.o) $(STM32F10X_LIB_SRC:.c=.o) 56 | 57 | # Define optimisation level here 58 | OPT = -Os 59 | 60 | MC_FLAGS = -mcpu=$(MCU) 61 | 62 | AS_FLAGS = $(MC_FLAGS) -g -gdwarf-2 -mthumb -Wa,-amhls=$(<:.s=.lst) 63 | CP_FLAGS = $(MC_FLAGS) $(OPT) -g -gdwarf-2 -mthumb -fomit-frame-pointer -Wall -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) 64 | LD_FLAGS = $(MC_FLAGS) -g -gdwarf-2 -mthumb -nostartfiles -Xlinker --gc-sections -T$(LINK_SCRIPT) -Wl,-Map=$(PROJECT_NAME).map,--cref,--no-warn-mismatch 65 | 66 | # 67 | # makefile rules 68 | # 69 | all: $(OBJECTS) $(PROJECT_NAME).elf $(PROJECT_NAME).hex $(PROJECT_NAME).bin 70 | $(TOOLCHAIN)size $(PROJECT_NAME).elf 71 | 72 | %o: %c 73 | $(CC) -c $(CP_FLAGS) -I . $(INC_DIR) $< -o $@ 74 | 75 | %o: %s 76 | $(AS) -c $(AS_FLAGS) $< -o $@ 77 | 78 | %elf: $(OBJECTS) 79 | $(CC) $(OBJECTS) $(LD_FLAGS) -o $@ 80 | 81 | %hex: %elf 82 | $(HEX) $< $@ 83 | 84 | %bin: %elf 85 | $(BIN) $< $@ 86 | 87 | flash: $(PROJECT_NAME).bin 88 | st-flash write $(PROJECT_NAME).bin 0x8000000 89 | 90 | erase: 91 | st-flash erase 92 | 93 | clean: 94 | -rm -rf $(OBJECTS) 95 | -rm -rf $(PROJECT_NAME).elf 96 | -rm -rf $(PROJECT_NAME).map 97 | -rm -rf $(PROJECT_NAME).hex 98 | -rm -rf $(PROJECT_NAME).bin 99 | -rm -rf $(SRC:.c=.lst) 100 | -rm -rf $(ASM_SRC:.s=.lst) 101 | 102 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the WWDG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_WWDG_H 25 | #define __STM32F10x_WWDG_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup WWDG 39 | * @{ 40 | */ 41 | 42 | /** @defgroup WWDG_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup WWDG_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup WWDG_Prescaler 55 | * @{ 56 | */ 57 | 58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 63 | ((PRESCALER) == WWDG_Prescaler_2) || \ 64 | ((PRESCALER) == WWDG_Prescaler_4) || \ 65 | ((PRESCALER) == WWDG_Prescaler_8)) 66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup WWDG_Exported_Macros 78 | * @{ 79 | */ 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @defgroup WWDG_Exported_Functions 85 | * @{ 86 | */ 87 | 88 | void WWDG_DeInit(void); 89 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 90 | void WWDG_SetWindowValue(uint8_t WindowValue); 91 | void WWDG_EnableIT(void); 92 | void WWDG_SetCounter(uint8_t Counter); 93 | void WWDG_Enable(uint8_t Counter); 94 | FlagStatus WWDG_GetFlagStatus(void); 95 | void WWDG_ClearFlag(void); 96 | 97 | #ifdef __cplusplus 98 | } 99 | #endif 100 | 101 | #endif /* __STM32F10x_WWDG_H */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** 112 | * @} 113 | */ 114 | 115 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 116 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 08-April-2011 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CONF_H 24 | #define __STM32F10x_CONF_H 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ 28 | #include "stm32f10x_adc.h" 29 | #include "stm32f10x_bkp.h" 30 | #include "stm32f10x_can.h" 31 | #include "stm32f10x_cec.h" 32 | #include "stm32f10x_crc.h" 33 | #include "stm32f10x_dac.h" 34 | #include "stm32f10x_dbgmcu.h" 35 | #include "stm32f10x_dma.h" 36 | #include "stm32f10x_exti.h" 37 | #include "stm32f10x_flash.h" 38 | #include "stm32f10x_fsmc.h" 39 | #include "stm32f10x_gpio.h" 40 | #include "stm32f10x_i2c.h" 41 | #include "stm32f10x_iwdg.h" 42 | #include "stm32f10x_pwr.h" 43 | #include "stm32f10x_rcc.h" 44 | #include "stm32f10x_rtc.h" 45 | #include "stm32f10x_sdio.h" 46 | #include "stm32f10x_spi.h" 47 | #include "stm32f10x_tim.h" 48 | #include "stm32f10x_usart.h" 49 | #include "stm32f10x_wwdg.h" 50 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 51 | 52 | /* Exported types ------------------------------------------------------------*/ 53 | /* Exported constants --------------------------------------------------------*/ 54 | /* Uncomment the line below to expanse the "assert_param" macro in the 55 | Standard Peripheral Library drivers code */ 56 | /* #define USE_FULL_ASSERT 1 */ 57 | 58 | /* Exported macro ------------------------------------------------------------*/ 59 | #ifdef USE_FULL_ASSERT 60 | 61 | /** 62 | * @brief The assert_param macro is used for function's parameters check. 63 | * @param expr: If expr is false, it calls assert_failed function which reports 64 | * the name of the source file and the source line number of the call 65 | * that failed. If expr is true, it returns no value. 66 | * @retval None 67 | */ 68 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 69 | /* Exported functions ------------------------------------------------------- */ 70 | void assert_failed(uint8_t* file, uint32_t line); 71 | #else 72 | #define assert_param(expr) ((void)0) 73 | #endif /* USE_FULL_ASSERT */ 74 | 75 | #endif /* __STM32F10x_CONF_H */ 76 | 77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 78 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the CRC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_crc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup CRC 30 | * @brief CRC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup CRC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup CRC_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup CRC_Private_Macros 51 | * @{ 52 | */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup CRC_Private_Variables 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup CRC_Private_FunctionPrototypes 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup CRC_Private_Functions 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @brief Resets the CRC Data register (DR). 80 | * @param None 81 | * @retval None 82 | */ 83 | void CRC_ResetDR(void) 84 | { 85 | /* Reset CRC generator */ 86 | CRC->CR = CRC_CR_RESET; 87 | } 88 | 89 | /** 90 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 91 | * @param Data: data word(32-bit) to compute its CRC 92 | * @retval 32-bit CRC 93 | */ 94 | uint32_t CRC_CalcCRC(uint32_t Data) 95 | { 96 | CRC->DR = Data; 97 | 98 | return (CRC->DR); 99 | } 100 | 101 | /** 102 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 103 | * @param pBuffer: pointer to the buffer containing the data to be computed 104 | * @param BufferLength: length of the buffer to be computed 105 | * @retval 32-bit CRC 106 | */ 107 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 108 | { 109 | uint32_t index = 0; 110 | 111 | for(index = 0; index < BufferLength; index++) 112 | { 113 | CRC->DR = pBuffer[index]; 114 | } 115 | return (CRC->DR); 116 | } 117 | 118 | /** 119 | * @brief Returns the current CRC value. 120 | * @param None 121 | * @retval 32-bit CRC 122 | */ 123 | uint32_t CRC_GetCRC(void) 124 | { 125 | return (CRC->DR); 126 | } 127 | 128 | /** 129 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 130 | * @param IDValue: 8-bit value to be stored in the ID register 131 | * @retval None 132 | */ 133 | void CRC_SetIDRegister(uint8_t IDValue) 134 | { 135 | CRC->IDR = IDValue; 136 | } 137 | 138 | /** 139 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 140 | * @param None 141 | * @retval 8-bit value of the ID register 142 | */ 143 | uint8_t CRC_GetIDRegister(void) 144 | { 145 | return (CRC->IDR); 146 | } 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 161 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the DBGMCU 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_DBGMCU_H 25 | #define __STM32F10x_DBGMCU_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup DBGMCU 39 | * @{ 40 | */ 41 | 42 | /** @defgroup DBGMCU_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup DBGMCU_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 55 | #define DBGMCU_STOP ((uint32_t)0x00000002) 56 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 57 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 58 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 59 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) 60 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) 61 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) 62 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) 63 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) 64 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 65 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 66 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) 67 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) 68 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) 69 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) 70 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 71 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) 72 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) 73 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) 74 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) 75 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) 76 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) 77 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) 78 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) 79 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) 80 | 81 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup DBGMCU_Exported_Macros 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup DBGMCU_Exported_Functions 95 | * @{ 96 | */ 97 | 98 | uint32_t DBGMCU_GetREVID(void); 99 | uint32_t DBGMCU_GetDEVID(void); 100 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 101 | 102 | #ifdef __cplusplus 103 | } 104 | #endif 105 | 106 | #endif /* __STM32F10x_DBGMCU_H */ 107 | /** 108 | * @} 109 | */ 110 | 111 | /** 112 | * @} 113 | */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 120 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_IWDG_H 25 | #define __STM32F10x_IWDG_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup IWDG 39 | * @{ 40 | */ 41 | 42 | /** @defgroup IWDG_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup IWDG_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup IWDG_WriteAccess 55 | * @{ 56 | */ 57 | 58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 61 | ((ACCESS) == IWDG_WriteAccess_Disable)) 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup IWDG_prescaler 67 | * @{ 68 | */ 69 | 70 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 71 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 72 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 73 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 74 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 75 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 76 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 77 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 78 | ((PRESCALER) == IWDG_Prescaler_8) || \ 79 | ((PRESCALER) == IWDG_Prescaler_16) || \ 80 | ((PRESCALER) == IWDG_Prescaler_32) || \ 81 | ((PRESCALER) == IWDG_Prescaler_64) || \ 82 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 83 | ((PRESCALER) == IWDG_Prescaler_256)) 84 | /** 85 | * @} 86 | */ 87 | 88 | /** @defgroup IWDG_Flag 89 | * @{ 90 | */ 91 | 92 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 93 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 94 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 95 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 96 | /** 97 | * @} 98 | */ 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** @defgroup IWDG_Exported_Macros 105 | * @{ 106 | */ 107 | 108 | /** 109 | * @} 110 | */ 111 | 112 | /** @defgroup IWDG_Exported_Functions 113 | * @{ 114 | */ 115 | 116 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 117 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 118 | void IWDG_SetReload(uint16_t Reload); 119 | void IWDG_ReloadCounter(void); 120 | void IWDG_Enable(void); 121 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 122 | 123 | #ifdef __cplusplus 124 | } 125 | #endif 126 | 127 | #endif /* __STM32F10x_IWDG_H */ 128 | /** 129 | * @} 130 | */ 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 141 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the RTC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_RTC_H 25 | #define __STM32F10x_RTC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup RTC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup RTC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup RTC_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup RTC_interrupts_define 55 | * @{ 56 | */ 57 | 58 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ 59 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ 60 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ 61 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) 62 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ 63 | ((IT) == RTC_IT_SEC)) 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup RTC_interrupts_flags 69 | * @{ 70 | */ 71 | 72 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ 73 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ 74 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ 75 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ 76 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ 77 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) 78 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ 79 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ 80 | ((FLAG) == RTC_FLAG_SEC)) 81 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @defgroup RTC_Exported_Macros 92 | * @{ 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @defgroup RTC_Exported_Functions 100 | * @{ 101 | */ 102 | 103 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 104 | void RTC_EnterConfigMode(void); 105 | void RTC_ExitConfigMode(void); 106 | uint32_t RTC_GetCounter(void); 107 | void RTC_SetCounter(uint32_t CounterValue); 108 | void RTC_SetPrescaler(uint32_t PrescalerValue); 109 | void RTC_SetAlarm(uint32_t AlarmValue); 110 | uint32_t RTC_GetDivider(void); 111 | void RTC_WaitForLastTask(void); 112 | void RTC_WaitForSynchro(void); 113 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 114 | void RTC_ClearFlag(uint16_t RTC_FLAG); 115 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 116 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 117 | 118 | #ifdef __cplusplus 119 | } 120 | #endif 121 | 122 | #endif /* __STM32F10x_RTC_H */ 123 | /** 124 | * @} 125 | */ 126 | 127 | /** 128 | * @} 129 | */ 130 | 131 | /** 132 | * @} 133 | */ 134 | 135 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 136 | -------------------------------------------------------------------------------- /stm32_flash.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * GCC linker script for STM32 microcontrollers (ARM Cortex-M). 3 | * 4 | * It exports the symbols needed for the CMSIS assembler startup script for GCC 5 | * ARM toolchains (_sidata, _sdata, _edata, _sbss, _ebss) and sets the entry 6 | * point to Reset_Handler. 7 | * 8 | * Adapt FLASH/RAM size for your particular device below. 9 | * 10 | * @author Bjørn Forsman 11 | */ 12 | 13 | MEMORY 14 | { 15 | flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K 16 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K 17 | } 18 | 19 | ENTRY(Reset_Handler) 20 | 21 | /* 22 | * Reserve memory for heap and stack. The linker will issue an error if there 23 | * is not enough memory. 24 | * 25 | * NOTE: The reserved heap and stack will be added to the bss column of the 26 | * binutils size command. 27 | */ 28 | _heap_size = 0; /* required amount of heap */ 29 | _stack_size = 0; /* required amount of stack */ 30 | 31 | /* 32 | * The stack starts at the end of RAM and grows downwards. Full-descending 33 | * stack; decrement first, then store. 34 | */ 35 | _estack = ORIGIN(ram) + LENGTH(ram); 36 | 37 | SECTIONS 38 | { 39 | /* Reset and ISR vectors */ 40 | .isr_vector : 41 | { 42 | __isr_vector_start__ = .; 43 | KEEP(*(.isr_vector)) /* without 'KEEP' the garbage collector discards this section */ 44 | ASSERT(. != __isr_vector_start__, "The .isr_vector section is empty"); 45 | } >flash 46 | 47 | 48 | /* Text section (code and read-only data) */ 49 | .text : 50 | { 51 | . = ALIGN(4); 52 | _stext = .; 53 | *(.text*) /* code */ 54 | *(.rodata*) /* read only data */ 55 | 56 | /* 57 | * NOTE: .glue_7 and .glue_7t sections are not needed because Cortex-M 58 | * only supports Thumb instructions, no ARM/Thumb interworking. 59 | */ 60 | 61 | /* Static constructors and destructors */ 62 | KEEP(*(.init)) 63 | KEEP(*(.fini)) 64 | 65 | . = ALIGN(4); 66 | _etext = .; 67 | } >flash 68 | 69 | 70 | /* 71 | * Stack unwinding and exception handling sections. 72 | * 73 | * ARM compilers emit object files with .ARM.extab and .ARM.exidx sections 74 | * when using C++ exceptions. Also, at least GCC emits those sections when 75 | * dividing large numbers (64-bit) in C. So we have to handle them. 76 | * 77 | * (ARM uses .ARM.extab and .ARM.exidx instead of the .eh_frame section 78 | * used on x86.) 79 | */ 80 | .ARM.extab : /* exception unwinding information */ 81 | { 82 | *(.ARM.extab*) 83 | } >flash 84 | .ARM.exidx : /* index entries for section unwinding */ 85 | { 86 | *(.ARM.exidx*) 87 | } >flash 88 | 89 | 90 | /* 91 | * Newlib and Eglibc (at least) need these for C++ support. 92 | * 93 | * (Copied from Sourcery CodeBench Lite: arm-none-eabi-gcc -V) 94 | */ 95 | .preinit_array : 96 | { 97 | PROVIDE_HIDDEN(__preinit_array_start = .); 98 | KEEP(*(.preinit_array*)) 99 | PROVIDE_HIDDEN(__preinit_array_end = .); 100 | } >flash 101 | .init_array : 102 | { 103 | PROVIDE_HIDDEN(__init_array_start = .); 104 | KEEP(*(SORT(.init_array.*))) 105 | KEEP(*(.init_array*)) 106 | PROVIDE_HIDDEN(__init_array_end = .); 107 | } >flash 108 | .fini_array : 109 | { 110 | PROVIDE_HIDDEN(__fini_array_start = .); 111 | KEEP(*(SORT(.fini_array.*))) 112 | KEEP(*(.fini_array*)) 113 | PROVIDE_HIDDEN(__fini_array_end = .); 114 | } >flash 115 | 116 | 117 | /* 118 | * Initialized data section. This section is programmed into FLASH (LMA 119 | * address) and copied to RAM (VMA address) in startup code. 120 | */ 121 | _sidata = .; 122 | .data : AT(_sidata) /* LMA address is _sidata (in FLASH) */ 123 | { 124 | . = ALIGN(4); 125 | _sdata = .; /* data section VMA address */ 126 | *(.data*) 127 | . = ALIGN(4); 128 | _edata = .; 129 | } >ram 130 | 131 | 132 | /* Uninitialized data section (zeroed out by startup code) */ 133 | .bss : 134 | { 135 | . = ALIGN(4); 136 | _sbss = .; 137 | *(.bss*) 138 | *(COMMON) 139 | . = ALIGN(4); 140 | _ebss = .; 141 | } >ram 142 | 143 | 144 | /* 145 | * Reserve memory for heap and stack. The linker will issue an error if 146 | * there is not enough memory. 147 | */ 148 | ._heap : 149 | { 150 | . = ALIGN(4); 151 | . = . + _heap_size; 152 | . = ALIGN(4); 153 | } >ram 154 | ._stack : 155 | { 156 | . = ALIGN(4); 157 | . = . + _stack_size; 158 | . = ALIGN(4); 159 | } >ram 160 | } 161 | 162 | /* Nice to have */ 163 | __isr_vector_size__ = SIZEOF(.isr_vector); 164 | __text_size__ = SIZEOF(.text); 165 | __data_size__ = SIZEOF(.data); 166 | __bss_size__ = SIZEOF(.bss); 167 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_PWR_H 25 | #define __STM32F10x_PWR_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup PWR 39 | * @{ 40 | */ 41 | 42 | /** @defgroup PWR_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup PWR_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup PVD_detection_level 55 | * @{ 56 | */ 57 | 58 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 59 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 60 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 61 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 62 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 63 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 64 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 65 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ 67 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ 68 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ 69 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup Regulator_state_is_STOP_mode 75 | * @{ 76 | */ 77 | 78 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 79 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 81 | ((REGULATOR) == PWR_Regulator_LowPower)) 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup STOP_mode_entry 87 | * @{ 88 | */ 89 | 90 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 91 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @defgroup PWR_Flag 99 | * @{ 100 | */ 101 | 102 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 103 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 104 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 106 | ((FLAG) == PWR_FLAG_PVDO)) 107 | 108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** @defgroup PWR_Exported_Macros 118 | * @{ 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @defgroup PWR_Exported_Functions 126 | * @{ 127 | */ 128 | 129 | void PWR_DeInit(void); 130 | void PWR_BackupAccessCmd(FunctionalState NewState); 131 | void PWR_PVDCmd(FunctionalState NewState); 132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 133 | void PWR_WakeUpPinCmd(FunctionalState NewState); 134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 135 | void PWR_EnterSTANDBYMode(void); 136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 137 | void PWR_ClearFlag(uint32_t PWR_FLAG); 138 | 139 | #ifdef __cplusplus 140 | } 141 | #endif 142 | 143 | #endif /* __STM32F10x_PWR_H */ 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 157 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the IWDG firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_iwdg.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup IWDG 30 | * @brief IWDG driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup IWDG_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup IWDG_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 47 | 48 | /* KR register bit mask */ 49 | #define KR_KEY_Reload ((uint16_t)0xAAAA) 50 | #define KR_KEY_Enable ((uint16_t)0xCCCC) 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup IWDG_Private_Macros 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @} 62 | */ 63 | 64 | /** @defgroup IWDG_Private_Variables 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @defgroup IWDG_Private_FunctionPrototypes 73 | * @{ 74 | */ 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | /** @defgroup IWDG_Private_Functions 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 86 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 87 | * This parameter can be one of the following values: 88 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 89 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 90 | * @retval None 91 | */ 92 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 93 | { 94 | /* Check the parameters */ 95 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 96 | IWDG->KR = IWDG_WriteAccess; 97 | } 98 | 99 | /** 100 | * @brief Sets IWDG Prescaler value. 101 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 102 | * This parameter can be one of the following values: 103 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 104 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 105 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 106 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 107 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 108 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 109 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 110 | * @retval None 111 | */ 112 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 113 | { 114 | /* Check the parameters */ 115 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 116 | IWDG->PR = IWDG_Prescaler; 117 | } 118 | 119 | /** 120 | * @brief Sets IWDG Reload value. 121 | * @param Reload: specifies the IWDG Reload value. 122 | * This parameter must be a number between 0 and 0x0FFF. 123 | * @retval None 124 | */ 125 | void IWDG_SetReload(uint16_t Reload) 126 | { 127 | /* Check the parameters */ 128 | assert_param(IS_IWDG_RELOAD(Reload)); 129 | IWDG->RLR = Reload; 130 | } 131 | 132 | /** 133 | * @brief Reloads IWDG counter with value defined in the reload register 134 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 135 | * @param None 136 | * @retval None 137 | */ 138 | void IWDG_ReloadCounter(void) 139 | { 140 | IWDG->KR = KR_KEY_Reload; 141 | } 142 | 143 | /** 144 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 145 | * @param None 146 | * @retval None 147 | */ 148 | void IWDG_Enable(void) 149 | { 150 | IWDG->KR = KR_KEY_Enable; 151 | } 152 | 153 | /** 154 | * @brief Checks whether the specified IWDG flag is set or not. 155 | * @param IWDG_FLAG: specifies the flag to check. 156 | * This parameter can be one of the following values: 157 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 158 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 159 | * @retval The new state of IWDG_FLAG (SET or RESET). 160 | */ 161 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 162 | { 163 | FlagStatus bitstatus = RESET; 164 | /* Check the parameters */ 165 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 166 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 167 | { 168 | bitstatus = SET; 169 | } 170 | else 171 | { 172 | bitstatus = RESET; 173 | } 174 | /* Return the flag status */ 175 | return bitstatus; 176 | } 177 | 178 | /** 179 | * @} 180 | */ 181 | 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 191 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the DBGMCU firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_dbgmcu.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup DBGMCU 30 | * @brief DBGMCU driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup DBGMCU_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup DBGMCU_Private_Defines 43 | * @{ 44 | */ 45 | 46 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 47 | /** 48 | * @} 49 | */ 50 | 51 | /** @defgroup DBGMCU_Private_Macros 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @defgroup DBGMCU_Private_Variables 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup DBGMCU_Private_FunctionPrototypes 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup DBGMCU_Private_Functions 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @brief Returns the device revision identifier. 81 | * @param None 82 | * @retval Device revision identifier 83 | */ 84 | uint32_t DBGMCU_GetREVID(void) 85 | { 86 | return(DBGMCU->IDCODE >> 16); 87 | } 88 | 89 | /** 90 | * @brief Returns the device identifier. 91 | * @param None 92 | * @retval Device identifier 93 | */ 94 | uint32_t DBGMCU_GetDEVID(void) 95 | { 96 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 97 | } 98 | 99 | /** 100 | * @brief Configures the specified peripheral and low power mode behavior 101 | * when the MCU under Debug mode. 102 | * @param DBGMCU_Periph: specifies the peripheral and low power mode. 103 | * This parameter can be any combination of the following values: 104 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode 105 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 106 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 107 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 108 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 109 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 110 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted 111 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 112 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted 113 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted 114 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted 115 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted 116 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted 117 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 118 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted 119 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted 120 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 121 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 122 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 123 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 124 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted 125 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted 126 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted 127 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted 128 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted 129 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 130 | * @param NewState: new state of the specified peripheral in Debug mode. 131 | * This parameter can be: ENABLE or DISABLE. 132 | * @retval None 133 | */ 134 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 135 | { 136 | /* Check the parameters */ 137 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 138 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 139 | 140 | if (NewState != DISABLE) 141 | { 142 | DBGMCU->CR |= DBGMCU_Periph; 143 | } 144 | else 145 | { 146 | DBGMCU->CR &= ~DBGMCU_Periph; 147 | } 148 | } 149 | 150 | /** 151 | * @} 152 | */ 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 163 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the WWDG firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_wwdg.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup WWDG 31 | * @brief WWDG driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup WWDG_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup WWDG_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* ----------- WWDG registers bit address in the alias region ----------- */ 48 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) 49 | 50 | /* Alias word address of EWI bit */ 51 | #define CFR_OFFSET (WWDG_OFFSET + 0x04) 52 | #define EWI_BitNumber 0x09 53 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) 54 | 55 | /* --------------------- WWDG registers bit mask ------------------------ */ 56 | 57 | /* CR register bit mask */ 58 | #define CR_WDGA_Set ((uint32_t)0x00000080) 59 | 60 | /* CFR register bit mask */ 61 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 62 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80) 63 | #define BIT_Mask ((uint8_t)0x7F) 64 | 65 | /** 66 | * @} 67 | */ 68 | 69 | /** @defgroup WWDG_Private_Macros 70 | * @{ 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup WWDG_Private_Variables 78 | * @{ 79 | */ 80 | 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup WWDG_Private_FunctionPrototypes 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup WWDG_Private_Functions 94 | * @{ 95 | */ 96 | 97 | /** 98 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 99 | * @param None 100 | * @retval None 101 | */ 102 | void WWDG_DeInit(void) 103 | { 104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 106 | } 107 | 108 | /** 109 | * @brief Sets the WWDG Prescaler. 110 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 111 | * This parameter can be one of the following values: 112 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 113 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 114 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 115 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 116 | * @retval None 117 | */ 118 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 119 | { 120 | uint32_t tmpreg = 0; 121 | /* Check the parameters */ 122 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 123 | /* Clear WDGTB[1:0] bits */ 124 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask; 125 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 126 | tmpreg |= WWDG_Prescaler; 127 | /* Store the new value */ 128 | WWDG->CFR = tmpreg; 129 | } 130 | 131 | /** 132 | * @brief Sets the WWDG window value. 133 | * @param WindowValue: specifies the window value to be compared to the downcounter. 134 | * This parameter value must be lower than 0x80. 135 | * @retval None 136 | */ 137 | void WWDG_SetWindowValue(uint8_t WindowValue) 138 | { 139 | __IO uint32_t tmpreg = 0; 140 | 141 | /* Check the parameters */ 142 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 143 | /* Clear W[6:0] bits */ 144 | 145 | tmpreg = WWDG->CFR & CFR_W_Mask; 146 | 147 | /* Set W[6:0] bits according to WindowValue value */ 148 | tmpreg |= WindowValue & (uint32_t) BIT_Mask; 149 | 150 | /* Store the new value */ 151 | WWDG->CFR = tmpreg; 152 | } 153 | 154 | /** 155 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 156 | * @param None 157 | * @retval None 158 | */ 159 | void WWDG_EnableIT(void) 160 | { 161 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; 162 | } 163 | 164 | /** 165 | * @brief Sets the WWDG counter value. 166 | * @param Counter: specifies the watchdog counter value. 167 | * This parameter must be a number between 0x40 and 0x7F. 168 | * @retval None 169 | */ 170 | void WWDG_SetCounter(uint8_t Counter) 171 | { 172 | /* Check the parameters */ 173 | assert_param(IS_WWDG_COUNTER(Counter)); 174 | /* Write to T[6:0] bits to configure the counter value, no need to do 175 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 176 | WWDG->CR = Counter & BIT_Mask; 177 | } 178 | 179 | /** 180 | * @brief Enables WWDG and load the counter value. 181 | * @param Counter: specifies the watchdog counter value. 182 | * This parameter must be a number between 0x40 and 0x7F. 183 | * @retval None 184 | */ 185 | void WWDG_Enable(uint8_t Counter) 186 | { 187 | /* Check the parameters */ 188 | assert_param(IS_WWDG_COUNTER(Counter)); 189 | WWDG->CR = CR_WDGA_Set | Counter; 190 | } 191 | 192 | /** 193 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 194 | * @param None 195 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) 196 | */ 197 | FlagStatus WWDG_GetFlagStatus(void) 198 | { 199 | return (FlagStatus)(WWDG->SR); 200 | } 201 | 202 | /** 203 | * @brief Clears Early Wakeup interrupt flag. 204 | * @param None 205 | * @retval None 206 | */ 207 | void WWDG_ClearFlag(void) 208 | { 209 | WWDG->SR = (uint32_t)RESET; 210 | } 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /** 217 | * @} 218 | */ 219 | 220 | /** 221 | * @} 222 | */ 223 | 224 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 225 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_CEC_H 25 | #define __STM32F10x_CEC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup CEC 39 | * @{ 40 | */ 41 | 42 | 43 | /** @defgroup CEC_Exported_Types 44 | * @{ 45 | */ 46 | 47 | /** 48 | * @brief CEC Init structure definition 49 | */ 50 | typedef struct 51 | { 52 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 53 | This parameter can be a value of @ref CEC_BitTiming_Mode */ 54 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 55 | This parameter can be a value of @ref CEC_BitPeriod_Mode */ 56 | }CEC_InitTypeDef; 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /** @defgroup CEC_Exported_Constants 63 | * @{ 64 | */ 65 | 66 | /** @defgroup CEC_BitTiming_Mode 67 | * @{ 68 | */ 69 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ 70 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ 71 | 72 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ 73 | ((MODE) == CEC_BitTimingErrFreeMode)) 74 | /** 75 | * @} 76 | */ 77 | 78 | /** @defgroup CEC_BitPeriod_Mode 79 | * @{ 80 | */ 81 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ 82 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ 83 | 84 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ 85 | ((MODE) == CEC_BitPeriodFlexibleMode)) 86 | /** 87 | * @} 88 | */ 89 | 90 | 91 | /** @defgroup CEC_interrupts_definition 92 | * @{ 93 | */ 94 | #define CEC_IT_TERR CEC_CSR_TERR 95 | #define CEC_IT_TBTRF CEC_CSR_TBTRF 96 | #define CEC_IT_RERR CEC_CSR_RERR 97 | #define CEC_IT_RBTF CEC_CSR_RBTF 98 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ 99 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) 100 | /** 101 | * @} 102 | */ 103 | 104 | 105 | /** @defgroup CEC_Own_Address 106 | * @{ 107 | */ 108 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup CEC_Prescaler 114 | * @{ 115 | */ 116 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup CEC_flags_definition 123 | * @{ 124 | */ 125 | 126 | /** 127 | * @brief ESR register flags 128 | */ 129 | #define CEC_FLAG_BTE ((uint32_t)0x10010000) 130 | #define CEC_FLAG_BPE ((uint32_t)0x10020000) 131 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) 132 | #define CEC_FLAG_SBE ((uint32_t)0x10080000) 133 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000) 134 | #define CEC_FLAG_LINE ((uint32_t)0x10200000) 135 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) 136 | 137 | /** 138 | * @brief CSR register flags 139 | */ 140 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002) 141 | #define CEC_FLAG_TERR ((uint32_t)0x00000004) 142 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) 143 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010) 144 | #define CEC_FLAG_REOM ((uint32_t)0x00000020) 145 | #define CEC_FLAG_RERR ((uint32_t)0x00000040) 146 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080) 147 | 148 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) 149 | 150 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ 151 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ 152 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ 153 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ 154 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ 155 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ 156 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /** 163 | * @} 164 | */ 165 | 166 | /** @defgroup CEC_Exported_Macros 167 | * @{ 168 | */ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @defgroup CEC_Exported_Functions 175 | * @{ 176 | */ 177 | void CEC_DeInit(void); 178 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 179 | void CEC_Cmd(FunctionalState NewState); 180 | void CEC_ITConfig(FunctionalState NewState); 181 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 182 | void CEC_SetPrescaler(uint16_t CEC_Prescaler); 183 | void CEC_SendDataByte(uint8_t Data); 184 | uint8_t CEC_ReceiveDataByte(void); 185 | void CEC_StartOfMessage(void); 186 | void CEC_EndOfMessageCmd(FunctionalState NewState); 187 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); 188 | void CEC_ClearFlag(uint32_t CEC_FLAG); 189 | ITStatus CEC_GetITStatus(uint8_t CEC_IT); 190 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 191 | 192 | #ifdef __cplusplus 193 | } 194 | #endif 195 | 196 | #endif /* __STM32F10x_CEC_H */ 197 | 198 | /** 199 | * @} 200 | */ 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 211 | -------------------------------------------------------------------------------- /user/uart_log.c: -------------------------------------------------------------------------------- 1 | // 2 | // Created by YangYongbao on 2017/3/18. 3 | // 4 | 5 | #include "uart_log.h" 6 | #include 7 | #include "stm32f10x.h" 8 | #include "stm32f10x_conf.h" 9 | 10 | 11 | void uart_log_init(void) 12 | { 13 | GPIO_InitTypeDef GPIO_InitStructure; 14 | USART_InitTypeDef USART_InitStructure; 15 | 16 | RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA, ENABLE); 17 | RCC_APB1PeriphClockCmd( RCC_APB1Periph_USART2, ENABLE); 18 | 19 | /* USART2 GPIO config */ 20 | /* Configure USART2 Tx (PA2) as alternate function push-pull */ 21 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 22 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 23 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 24 | GPIO_Init(GPIOA, &GPIO_InitStructure); 25 | 26 | /* Configure USART2 Rx (PA3) as input floating */ 27 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; 28 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; 29 | GPIO_Init(GPIOA, &GPIO_InitStructure); 30 | 31 | /* USART2 mode config */ 32 | USART_InitStructure.USART_BaudRate = 9600; 33 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 34 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 35 | USART_InitStructure.USART_Parity = USART_Parity_No ; 36 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 37 | USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 38 | USART_Init(USART2, &USART_InitStructure); 39 | USART_ITConfig(USART2, USART_IT_RXNE, ENABLE); 40 | 41 | USART_Cmd(USART2, ENABLE); 42 | } 43 | 44 | 45 | void printchar(char **str, unsigned int c) 46 | { 47 | while (USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); 48 | USART_SendData(USART2, (uint8_t)c); 49 | } 50 | 51 | #define PAD_RIGHT 1 52 | #define PAD_ZERO 2 53 | 54 | static int prints(char **out, const char *string, int width, int pad) 55 | { 56 | register int pc = 0, padchar = ' '; 57 | 58 | if (width > 0) { 59 | register int len = 0; 60 | register const char *ptr; 61 | for (ptr = string; *ptr; ++ptr) ++len; 62 | if (len >= width) width = 0; 63 | else width -= len; 64 | if (pad & PAD_ZERO) padchar = '0'; 65 | } 66 | if (!(pad & PAD_RIGHT)) { 67 | for ( ; width > 0; --width) { 68 | printchar (out, padchar); 69 | ++pc; 70 | } 71 | } 72 | for ( ; *string ; ++string) { 73 | printchar (out, *string); 74 | ++pc; 75 | } 76 | for ( ; width > 0; --width) { 77 | printchar (out, padchar); 78 | ++pc; 79 | } 80 | 81 | return pc; 82 | } 83 | 84 | /* the following should be enough for 32 bit int */ 85 | #define PRINT_BUF_LEN 12 86 | 87 | static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) 88 | { 89 | char print_buf[PRINT_BUF_LEN]; 90 | register char *s; 91 | register int t, neg = 0, pc = 0; 92 | register unsigned int u = i; 93 | 94 | if (i == 0) { 95 | print_buf[0] = '0'; 96 | print_buf[1] = '\0'; 97 | return prints (out, print_buf, width, pad); 98 | } 99 | 100 | if (sg && b == 10 && i < 0) { 101 | neg = 1; 102 | u = -i; 103 | } 104 | 105 | s = print_buf + PRINT_BUF_LEN-1; 106 | *s = '\0'; 107 | 108 | while (u) { 109 | t = u % b; 110 | if( t >= 10 ) 111 | t += letbase - '0' - 10; 112 | *--s = t + '0'; 113 | u /= b; 114 | } 115 | 116 | if (neg) { 117 | if( width && (pad & PAD_ZERO) ) { 118 | printchar (out, '-'); 119 | ++pc; 120 | --width; 121 | } 122 | else { 123 | *--s = '-'; 124 | } 125 | } 126 | 127 | return pc + prints (out, s, width, pad); 128 | } 129 | 130 | static int print( char **out, const char *format, va_list args ) 131 | { 132 | register int width, pad; 133 | register int pc = 0; 134 | char scr[2]; 135 | 136 | for (; *format != 0; ++format) { 137 | if (*format == '%') { 138 | ++format; 139 | width = pad = 0; 140 | if (*format == '\0') break; 141 | if (*format == '%') goto out; 142 | if (*format == '-') { 143 | ++format; 144 | pad = PAD_RIGHT; 145 | } 146 | while (*format == '0') { 147 | ++format; 148 | pad |= PAD_ZERO; 149 | } 150 | for ( ; *format >= '0' && *format <= '9'; ++format) { 151 | width *= 10; 152 | width += *format - '0'; 153 | } 154 | if( *format == 's' ) { 155 | register char *s = (char *)va_arg( args, int ); 156 | pc += prints (out, s?s:"(null)", width, pad); 157 | continue; 158 | } 159 | if( *format == 'd' ) { 160 | pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); 161 | continue; 162 | } 163 | if( *format == 'x' ) { 164 | pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); 165 | continue; 166 | } 167 | if( *format == 'X' ) { 168 | pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); 169 | continue; 170 | } 171 | if( *format == 'u' ) { 172 | pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); 173 | continue; 174 | } 175 | if( *format == 'c' ) { 176 | /* char are converted to int then pushed on the stack */ 177 | scr[0] = (char)va_arg( args, int ); 178 | scr[1] = '\0'; 179 | pc += prints (out, scr, width, pad); 180 | continue; 181 | } 182 | } 183 | else { 184 | out: 185 | printchar (out, *format); 186 | ++pc; 187 | } 188 | } 189 | if (out) **out = '\0'; 190 | va_end( args ); 191 | return pc; 192 | } 193 | 194 | int printf(const char *format, ...) 195 | { 196 | va_list args; 197 | 198 | va_start( args, format ); 199 | return print( 0, format, args ); 200 | } 201 | 202 | void debug(const char *format, ...) 203 | { 204 | va_list args; 205 | 206 | va_start( args, format ); 207 | print( 0, format, args ); 208 | print( 0, "\n", args); 209 | } 210 | 211 | int sprintf(char *out, const char *format, ...) 212 | { 213 | va_list args; 214 | 215 | va_start( args, format ); 216 | return print( &out, format, args ); 217 | } 218 | 219 | int snprintf( char *buf, unsigned int count, const char *format, ... ) 220 | { 221 | va_list args; 222 | 223 | ( void ) count; 224 | 225 | va_start( args, format ); 226 | return print( &buf, format, args ); 227 | } 228 | 229 | 230 | // UART2 interrupt 231 | void USART2_IRQHandler(void) 232 | { 233 | uint8_t data; 234 | if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET) 235 | { 236 | data = USART_ReceiveData(USART2); 237 | /* add debug uart receive here */ 238 | // uart_receive_input(data); 239 | 240 | USART_ClearFlag(USART2, USART_FLAG_RXNE); 241 | USART_ClearITPendingBit(USART2, USART_IT_RXNE); 242 | } 243 | } 244 | 245 | 246 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the EXTI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_EXTI_H 25 | #define __STM32F10x_EXTI_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup EXTI 39 | * @{ 40 | */ 41 | 42 | /** @defgroup EXTI_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief EXTI mode enumeration 48 | */ 49 | 50 | typedef enum 51 | { 52 | EXTI_Mode_Interrupt = 0x00, 53 | EXTI_Mode_Event = 0x04 54 | }EXTIMode_TypeDef; 55 | 56 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 57 | 58 | /** 59 | * @brief EXTI Trigger enumeration 60 | */ 61 | 62 | typedef enum 63 | { 64 | EXTI_Trigger_Rising = 0x08, 65 | EXTI_Trigger_Falling = 0x0C, 66 | EXTI_Trigger_Rising_Falling = 0x10 67 | }EXTITrigger_TypeDef; 68 | 69 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 70 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 71 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 72 | /** 73 | * @brief EXTI Init Structure definition 74 | */ 75 | 76 | typedef struct 77 | { 78 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 79 | This parameter can be any combination of @ref EXTI_Lines */ 80 | 81 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 82 | This parameter can be a value of @ref EXTIMode_TypeDef */ 83 | 84 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 85 | This parameter can be a value of @ref EXTIMode_TypeDef */ 86 | 87 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 88 | This parameter can be set either to ENABLE or DISABLE */ 89 | }EXTI_InitTypeDef; 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup EXTI_Exported_Constants 96 | * @{ 97 | */ 98 | 99 | /** @defgroup EXTI_Lines 100 | * @{ 101 | */ 102 | 103 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ 104 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ 105 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ 106 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ 107 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ 108 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ 109 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ 110 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ 111 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ 112 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ 113 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ 114 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ 115 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ 116 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ 117 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ 118 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ 119 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ 120 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 121 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS 122 | Wakeup from suspend event */ 123 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 124 | 125 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) 126 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 127 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 128 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 129 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 130 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 131 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 132 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 133 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 134 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 135 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) 136 | 137 | 138 | /** 139 | * @} 140 | */ 141 | 142 | /** 143 | * @} 144 | */ 145 | 146 | /** @defgroup EXTI_Exported_Macros 147 | * @{ 148 | */ 149 | 150 | /** 151 | * @} 152 | */ 153 | 154 | /** @defgroup EXTI_Exported_Functions 155 | * @{ 156 | */ 157 | 158 | void EXTI_DeInit(void); 159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 162 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 163 | void EXTI_ClearFlag(uint32_t EXTI_Line); 164 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 165 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 166 | 167 | #ifdef __cplusplus 168 | } 169 | #endif 170 | 171 | #endif /* __STM32F10x_EXTI_H */ 172 | /** 173 | * @} 174 | */ 175 | 176 | /** 177 | * @} 178 | */ 179 | 180 | /** 181 | * @} 182 | */ 183 | 184 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 185 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes ------------------------------------------------------------------*/ 24 | #include "misc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup MISC 31 | * @brief MISC driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup MISC_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup MISC_Private_Defines 44 | * @{ 45 | */ 46 | 47 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 48 | /** 49 | * @} 50 | */ 51 | 52 | /** @defgroup MISC_Private_Macros 53 | * @{ 54 | */ 55 | 56 | /** 57 | * @} 58 | */ 59 | 60 | /** @defgroup MISC_Private_Variables 61 | * @{ 62 | */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup MISC_Private_FunctionPrototypes 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup MISC_Private_Functions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @brief Configures the priority grouping: pre-emption priority and subpriority. 82 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 83 | * This parameter can be one of the following values: 84 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority 85 | * 4 bits for subpriority 86 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority 87 | * 3 bits for subpriority 88 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority 89 | * 2 bits for subpriority 90 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority 91 | * 1 bits for subpriority 92 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority 93 | * 0 bits for subpriority 94 | * @retval None 95 | */ 96 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 97 | { 98 | /* Check the parameters */ 99 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 100 | 101 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 102 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 103 | } 104 | 105 | /** 106 | * @brief Initializes the NVIC peripheral according to the specified 107 | * parameters in the NVIC_InitStruct. 108 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 109 | * the configuration information for the specified NVIC peripheral. 110 | * @retval None 111 | */ 112 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 113 | { 114 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 115 | 116 | /* Check the parameters */ 117 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 118 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 119 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 120 | 121 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 122 | { 123 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 124 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 125 | tmppre = (0x4 - tmppriority); 126 | tmpsub = tmpsub >> tmppriority; 127 | 128 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 129 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 130 | tmppriority = tmppriority << 0x04; 131 | 132 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 133 | 134 | /* Enable the Selected IRQ Channels --------------------------------------*/ 135 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 136 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 137 | } 138 | else 139 | { 140 | /* Disable the Selected IRQ Channels -------------------------------------*/ 141 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 143 | } 144 | } 145 | 146 | /** 147 | * @brief Sets the vector table location and Offset. 148 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 149 | * This parameter can be one of the following values: 150 | * @arg NVIC_VectTab_RAM 151 | * @arg NVIC_VectTab_FLASH 152 | * @param Offset: Vector Table base offset field. This value must be a multiple 153 | * of 0x200. 154 | * @retval None 155 | */ 156 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 157 | { 158 | /* Check the parameters */ 159 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 160 | assert_param(IS_NVIC_OFFSET(Offset)); 161 | 162 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 163 | } 164 | 165 | /** 166 | * @brief Selects the condition for the system to enter low power mode. 167 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 168 | * This parameter can be one of the following values: 169 | * @arg NVIC_LP_SEVONPEND 170 | * @arg NVIC_LP_SLEEPDEEP 171 | * @arg NVIC_LP_SLEEPONEXIT 172 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 173 | * @retval None 174 | */ 175 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 176 | { 177 | /* Check the parameters */ 178 | assert_param(IS_NVIC_LP(LowPowerMode)); 179 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 180 | 181 | if (NewState != DISABLE) 182 | { 183 | SCB->SCR |= LowPowerMode; 184 | } 185 | else 186 | { 187 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 188 | } 189 | } 190 | 191 | /** 192 | * @brief Configures the SysTick clock source. 193 | * @param SysTick_CLKSource: specifies the SysTick clock source. 194 | * This parameter can be one of the following values: 195 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 196 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 197 | * @retval None 198 | */ 199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 200 | { 201 | /* Check the parameters */ 202 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 203 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 204 | { 205 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 206 | } 207 | else 208 | { 209 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 210 | } 211 | } 212 | 213 | /** 214 | * @} 215 | */ 216 | 217 | /** 218 | * @} 219 | */ 220 | 221 | /** 222 | * @} 223 | */ 224 | 225 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 226 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the EXTI firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_exti.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup EXTI 30 | * @brief EXTI driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup EXTI_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup EXTI_Private_Defines 43 | * @{ 44 | */ 45 | 46 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ 47 | 48 | /** 49 | * @} 50 | */ 51 | 52 | /** @defgroup EXTI_Private_Macros 53 | * @{ 54 | */ 55 | 56 | /** 57 | * @} 58 | */ 59 | 60 | /** @defgroup EXTI_Private_Variables 61 | * @{ 62 | */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup EXTI_Private_FunctionPrototypes 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup EXTI_Private_Functions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @brief Deinitializes the EXTI peripheral registers to their default reset values. 82 | * @param None 83 | * @retval None 84 | */ 85 | void EXTI_DeInit(void) 86 | { 87 | EXTI->IMR = 0x00000000; 88 | EXTI->EMR = 0x00000000; 89 | EXTI->RTSR = 0x00000000; 90 | EXTI->FTSR = 0x00000000; 91 | EXTI->PR = 0x000FFFFF; 92 | } 93 | 94 | /** 95 | * @brief Initializes the EXTI peripheral according to the specified 96 | * parameters in the EXTI_InitStruct. 97 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure 98 | * that contains the configuration information for the EXTI peripheral. 99 | * @retval None 100 | */ 101 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) 102 | { 103 | uint32_t tmp = 0; 104 | 105 | /* Check the parameters */ 106 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); 107 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); 108 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); 109 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); 110 | 111 | tmp = (uint32_t)EXTI_BASE; 112 | 113 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 114 | { 115 | /* Clear EXTI line configuration */ 116 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 117 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 118 | 119 | tmp += EXTI_InitStruct->EXTI_Mode; 120 | 121 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 122 | 123 | /* Clear Rising Falling edge configuration */ 124 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 125 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 126 | 127 | /* Select the trigger for the selected external interrupts */ 128 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 129 | { 130 | /* Rising Falling edge */ 131 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 132 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 133 | } 134 | else 135 | { 136 | tmp = (uint32_t)EXTI_BASE; 137 | tmp += EXTI_InitStruct->EXTI_Trigger; 138 | 139 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 140 | } 141 | } 142 | else 143 | { 144 | tmp += EXTI_InitStruct->EXTI_Mode; 145 | 146 | /* Disable the selected external lines */ 147 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 148 | } 149 | } 150 | 151 | /** 152 | * @brief Fills each EXTI_InitStruct member with its reset value. 153 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will 154 | * be initialized. 155 | * @retval None 156 | */ 157 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) 158 | { 159 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 160 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 161 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 162 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 163 | } 164 | 165 | /** 166 | * @brief Generates a Software interrupt. 167 | * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. 168 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 169 | * @retval None 170 | */ 171 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 172 | { 173 | /* Check the parameters */ 174 | assert_param(IS_EXTI_LINE(EXTI_Line)); 175 | 176 | EXTI->SWIER |= EXTI_Line; 177 | } 178 | 179 | /** 180 | * @brief Checks whether the specified EXTI line flag is set or not. 181 | * @param EXTI_Line: specifies the EXTI line flag to check. 182 | * This parameter can be: 183 | * @arg EXTI_Linex: External interrupt line x where x(0..19) 184 | * @retval The new state of EXTI_Line (SET or RESET). 185 | */ 186 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 187 | { 188 | FlagStatus bitstatus = RESET; 189 | /* Check the parameters */ 190 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 191 | 192 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 193 | { 194 | bitstatus = SET; 195 | } 196 | else 197 | { 198 | bitstatus = RESET; 199 | } 200 | return bitstatus; 201 | } 202 | 203 | /** 204 | * @brief Clears the EXTI's line pending flags. 205 | * @param EXTI_Line: specifies the EXTI lines flags to clear. 206 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 207 | * @retval None 208 | */ 209 | void EXTI_ClearFlag(uint32_t EXTI_Line) 210 | { 211 | /* Check the parameters */ 212 | assert_param(IS_EXTI_LINE(EXTI_Line)); 213 | 214 | EXTI->PR = EXTI_Line; 215 | } 216 | 217 | /** 218 | * @brief Checks whether the specified EXTI line is asserted or not. 219 | * @param EXTI_Line: specifies the EXTI line to check. 220 | * This parameter can be: 221 | * @arg EXTI_Linex: External interrupt line x where x(0..19) 222 | * @retval The new state of EXTI_Line (SET or RESET). 223 | */ 224 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 225 | { 226 | ITStatus bitstatus = RESET; 227 | uint32_t enablestatus = 0; 228 | /* Check the parameters */ 229 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 230 | 231 | enablestatus = EXTI->IMR & EXTI_Line; 232 | if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 233 | { 234 | bitstatus = SET; 235 | } 236 | else 237 | { 238 | bitstatus = RESET; 239 | } 240 | return bitstatus; 241 | } 242 | 243 | /** 244 | * @brief Clears the EXTI's line pending bits. 245 | * @param EXTI_Line: specifies the EXTI lines to clear. 246 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 247 | * @retval None 248 | */ 249 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 250 | { 251 | /* Check the parameters */ 252 | assert_param(IS_EXTI_LINE(EXTI_Line)); 253 | 254 | EXTI->PR = EXTI_Line; 255 | } 256 | 257 | /** 258 | * @} 259 | */ 260 | 261 | /** 262 | * @} 263 | */ 264 | 265 | /** 266 | * @} 267 | */ 268 | 269 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 270 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the BKP firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_BKP_H 25 | #define __STM32F10x_BKP_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup BKP 39 | * @{ 40 | */ 41 | 42 | /** @defgroup BKP_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup BKP_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup Tamper_Pin_active_level 55 | * @{ 56 | */ 57 | 58 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 59 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 60 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ 61 | ((LEVEL) == BKP_TamperPinLevel_Low)) 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 67 | * @{ 68 | */ 69 | 70 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 71 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 72 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 73 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 74 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ 75 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ 76 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ 77 | ((SOURCE) == BKP_RTCOutputSource_Second)) 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @defgroup Data_Backup_Register 83 | * @{ 84 | */ 85 | 86 | #define BKP_DR1 ((uint16_t)0x0004) 87 | #define BKP_DR2 ((uint16_t)0x0008) 88 | #define BKP_DR3 ((uint16_t)0x000C) 89 | #define BKP_DR4 ((uint16_t)0x0010) 90 | #define BKP_DR5 ((uint16_t)0x0014) 91 | #define BKP_DR6 ((uint16_t)0x0018) 92 | #define BKP_DR7 ((uint16_t)0x001C) 93 | #define BKP_DR8 ((uint16_t)0x0020) 94 | #define BKP_DR9 ((uint16_t)0x0024) 95 | #define BKP_DR10 ((uint16_t)0x0028) 96 | #define BKP_DR11 ((uint16_t)0x0040) 97 | #define BKP_DR12 ((uint16_t)0x0044) 98 | #define BKP_DR13 ((uint16_t)0x0048) 99 | #define BKP_DR14 ((uint16_t)0x004C) 100 | #define BKP_DR15 ((uint16_t)0x0050) 101 | #define BKP_DR16 ((uint16_t)0x0054) 102 | #define BKP_DR17 ((uint16_t)0x0058) 103 | #define BKP_DR18 ((uint16_t)0x005C) 104 | #define BKP_DR19 ((uint16_t)0x0060) 105 | #define BKP_DR20 ((uint16_t)0x0064) 106 | #define BKP_DR21 ((uint16_t)0x0068) 107 | #define BKP_DR22 ((uint16_t)0x006C) 108 | #define BKP_DR23 ((uint16_t)0x0070) 109 | #define BKP_DR24 ((uint16_t)0x0074) 110 | #define BKP_DR25 ((uint16_t)0x0078) 111 | #define BKP_DR26 ((uint16_t)0x007C) 112 | #define BKP_DR27 ((uint16_t)0x0080) 113 | #define BKP_DR28 ((uint16_t)0x0084) 114 | #define BKP_DR29 ((uint16_t)0x0088) 115 | #define BKP_DR30 ((uint16_t)0x008C) 116 | #define BKP_DR31 ((uint16_t)0x0090) 117 | #define BKP_DR32 ((uint16_t)0x0094) 118 | #define BKP_DR33 ((uint16_t)0x0098) 119 | #define BKP_DR34 ((uint16_t)0x009C) 120 | #define BKP_DR35 ((uint16_t)0x00A0) 121 | #define BKP_DR36 ((uint16_t)0x00A4) 122 | #define BKP_DR37 ((uint16_t)0x00A8) 123 | #define BKP_DR38 ((uint16_t)0x00AC) 124 | #define BKP_DR39 ((uint16_t)0x00B0) 125 | #define BKP_DR40 ((uint16_t)0x00B4) 126 | #define BKP_DR41 ((uint16_t)0x00B8) 127 | #define BKP_DR42 ((uint16_t)0x00BC) 128 | 129 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ 130 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ 131 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ 132 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ 133 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ 134 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ 135 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ 136 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ 137 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ 138 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ 139 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ 140 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ 141 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ 142 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) 143 | 144 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 145 | /** 146 | * @} 147 | */ 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @defgroup BKP_Exported_Macros 154 | * @{ 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /** @defgroup BKP_Exported_Functions 162 | * @{ 163 | */ 164 | 165 | void BKP_DeInit(void); 166 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 167 | void BKP_TamperPinCmd(FunctionalState NewState); 168 | void BKP_ITConfig(FunctionalState NewState); 169 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 170 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 171 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 172 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 173 | FlagStatus BKP_GetFlagStatus(void); 174 | void BKP_ClearFlag(void); 175 | ITStatus BKP_GetITStatus(void); 176 | void BKP_ClearITPendingBit(void); 177 | 178 | #ifdef __cplusplus 179 | } 180 | #endif 181 | 182 | #endif /* __STM32F10x_BKP_H */ 183 | /** 184 | * @} 185 | */ 186 | 187 | /** 188 | * @} 189 | */ 190 | 191 | /** 192 | * @} 193 | */ 194 | 195 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 196 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the BKP firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_bkp.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup BKP 31 | * @brief BKP driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup BKP_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup BKP_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* ------------ BKP registers bit address in the alias region --------------- */ 48 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE) 49 | 50 | /* --- CR Register ----*/ 51 | 52 | /* Alias word address of TPAL bit */ 53 | #define CR_OFFSET (BKP_OFFSET + 0x30) 54 | #define TPAL_BitNumber 0x01 55 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 56 | 57 | /* Alias word address of TPE bit */ 58 | #define TPE_BitNumber 0x00 59 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of TPIE bit */ 64 | #define CSR_OFFSET (BKP_OFFSET + 0x34) 65 | #define TPIE_BitNumber 0x02 66 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) 67 | 68 | /* Alias word address of TIF bit */ 69 | #define TIF_BitNumber 0x09 70 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) 71 | 72 | /* Alias word address of TEF bit */ 73 | #define TEF_BitNumber 0x08 74 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) 75 | 76 | /* ---------------------- BKP registers bit mask ------------------------ */ 77 | 78 | /* RTCCR register bit mask */ 79 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80) 80 | #define RTCCR_MASK ((uint16_t)0xFC7F) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | 87 | /** @defgroup BKP_Private_Macros 88 | * @{ 89 | */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup BKP_Private_Variables 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup BKP_Private_FunctionPrototypes 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup BKP_Private_Functions 112 | * @{ 113 | */ 114 | 115 | /** 116 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 117 | * @param None 118 | * @retval None 119 | */ 120 | void BKP_DeInit(void) 121 | { 122 | RCC_BackupResetCmd(ENABLE); 123 | RCC_BackupResetCmd(DISABLE); 124 | } 125 | 126 | /** 127 | * @brief Configures the Tamper Pin active level. 128 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 129 | * This parameter can be one of the following values: 130 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level 131 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level 132 | * @retval None 133 | */ 134 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 135 | { 136 | /* Check the parameters */ 137 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); 138 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; 139 | } 140 | 141 | /** 142 | * @brief Enables or disables the Tamper Pin activation. 143 | * @param NewState: new state of the Tamper Pin activation. 144 | * This parameter can be: ENABLE or DISABLE. 145 | * @retval None 146 | */ 147 | void BKP_TamperPinCmd(FunctionalState NewState) 148 | { 149 | /* Check the parameters */ 150 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 151 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; 152 | } 153 | 154 | /** 155 | * @brief Enables or disables the Tamper Pin Interrupt. 156 | * @param NewState: new state of the Tamper Pin Interrupt. 157 | * This parameter can be: ENABLE or DISABLE. 158 | * @retval None 159 | */ 160 | void BKP_ITConfig(FunctionalState NewState) 161 | { 162 | /* Check the parameters */ 163 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 164 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; 165 | } 166 | 167 | /** 168 | * @brief Select the RTC output source to output on the Tamper pin. 169 | * @param BKP_RTCOutputSource: specifies the RTC output source. 170 | * This parameter can be one of the following values: 171 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. 172 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency 173 | * divided by 64 on the Tamper pin. 174 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on 175 | * the Tamper pin. 176 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on 177 | * the Tamper pin. 178 | * @retval None 179 | */ 180 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 181 | { 182 | uint16_t tmpreg = 0; 183 | /* Check the parameters */ 184 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); 185 | tmpreg = BKP->RTCCR; 186 | /* Clear CCO, ASOE and ASOS bits */ 187 | tmpreg &= RTCCR_MASK; 188 | 189 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ 190 | tmpreg |= BKP_RTCOutputSource; 191 | /* Store the new value */ 192 | BKP->RTCCR = tmpreg; 193 | } 194 | 195 | /** 196 | * @brief Sets RTC Clock Calibration value. 197 | * @param CalibrationValue: specifies the RTC Clock Calibration value. 198 | * This parameter must be a number between 0 and 0x7F. 199 | * @retval None 200 | */ 201 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 202 | { 203 | uint16_t tmpreg = 0; 204 | /* Check the parameters */ 205 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); 206 | tmpreg = BKP->RTCCR; 207 | /* Clear CAL[6:0] bits */ 208 | tmpreg &= RTCCR_CAL_MASK; 209 | /* Set CAL[6:0] bits according to CalibrationValue value */ 210 | tmpreg |= CalibrationValue; 211 | /* Store the new value */ 212 | BKP->RTCCR = tmpreg; 213 | } 214 | 215 | /** 216 | * @brief Writes user data to the specified Data Backup Register. 217 | * @param BKP_DR: specifies the Data Backup Register. 218 | * This parameter can be BKP_DRx where x:[1, 42] 219 | * @param Data: data to write 220 | * @retval None 221 | */ 222 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 223 | { 224 | __IO uint32_t tmp = 0; 225 | 226 | /* Check the parameters */ 227 | assert_param(IS_BKP_DR(BKP_DR)); 228 | 229 | tmp = (uint32_t)BKP_BASE; 230 | tmp += BKP_DR; 231 | 232 | *(__IO uint32_t *) tmp = Data; 233 | } 234 | 235 | /** 236 | * @brief Reads data from the specified Data Backup Register. 237 | * @param BKP_DR: specifies the Data Backup Register. 238 | * This parameter can be BKP_DRx where x:[1, 42] 239 | * @retval The content of the specified Data Backup Register 240 | */ 241 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 242 | { 243 | __IO uint32_t tmp = 0; 244 | 245 | /* Check the parameters */ 246 | assert_param(IS_BKP_DR(BKP_DR)); 247 | 248 | tmp = (uint32_t)BKP_BASE; 249 | tmp += BKP_DR; 250 | 251 | return (*(__IO uint16_t *) tmp); 252 | } 253 | 254 | /** 255 | * @brief Checks whether the Tamper Pin Event flag is set or not. 256 | * @param None 257 | * @retval The new state of the Tamper Pin Event flag (SET or RESET). 258 | */ 259 | FlagStatus BKP_GetFlagStatus(void) 260 | { 261 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); 262 | } 263 | 264 | /** 265 | * @brief Clears Tamper Pin Event pending flag. 266 | * @param None 267 | * @retval None 268 | */ 269 | void BKP_ClearFlag(void) 270 | { 271 | /* Set CTE bit to clear Tamper Pin Event flag */ 272 | BKP->CSR |= BKP_CSR_CTE; 273 | } 274 | 275 | /** 276 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 277 | * @param None 278 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET). 279 | */ 280 | ITStatus BKP_GetITStatus(void) 281 | { 282 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); 283 | } 284 | 285 | /** 286 | * @brief Clears Tamper Pin Interrupt pending bit. 287 | * @param None 288 | * @retval None 289 | */ 290 | void BKP_ClearITPendingBit(void) 291 | { 292 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ 293 | BKP->CSR |= BKP_CSR_CTI; 294 | } 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /** 301 | * @} 302 | */ 303 | 304 | /** 305 | * @} 306 | */ 307 | 308 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 309 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/inc/misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __MISC_H 25 | #define __MISC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup MISC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup MISC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief NVIC Init Structure definition 48 | */ 49 | 50 | typedef struct 51 | { 52 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 53 | This parameter can be a value of @ref IRQn_Type 54 | (For the complete STM32 Devices IRQ Channels list, please 55 | refer to stm32f10x.h file) */ 56 | 57 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 58 | specified in NVIC_IRQChannel. This parameter can be a value 59 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 60 | 61 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 62 | in NVIC_IRQChannel. This parameter can be a value 63 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 64 | 65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 66 | will be enabled or disabled. 67 | This parameter can be set either to ENABLE or DISABLE */ 68 | } NVIC_InitTypeDef; 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup NVIC_Priority_Table 75 | * @{ 76 | */ 77 | 78 | /** 79 | @code 80 | The table below gives the allowed values of the pre-emption priority and subpriority according 81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function 82 | ============================================================================================================================ 83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 84 | ============================================================================================================================ 85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority 86 | | | | 4 bits for subpriority 87 | ---------------------------------------------------------------------------------------------------------------------------- 88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority 89 | | | | 3 bits for subpriority 90 | ---------------------------------------------------------------------------------------------------------------------------- 91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 92 | | | | 2 bits for subpriority 93 | ---------------------------------------------------------------------------------------------------------------------------- 94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 95 | | | | 1 bits for subpriority 96 | ---------------------------------------------------------------------------------------------------------------------------- 97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority 98 | | | | 0 bits for subpriority 99 | ============================================================================================================================ 100 | @endcode 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** @defgroup MISC_Exported_Constants 108 | * @{ 109 | */ 110 | 111 | /** @defgroup Vector_Table_Base 112 | * @{ 113 | */ 114 | 115 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 116 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 117 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 118 | ((VECTTAB) == NVIC_VectTab_FLASH)) 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup System_Low_Power 124 | * @{ 125 | */ 126 | 127 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 128 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 129 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 130 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 131 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 132 | ((LP) == NVIC_LP_SLEEPONEXIT)) 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup Preemption_Priority_Group 138 | * @{ 139 | */ 140 | 141 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 142 | 4 bits for subpriority */ 143 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 144 | 3 bits for subpriority */ 145 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 146 | 2 bits for subpriority */ 147 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 148 | 1 bits for subpriority */ 149 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 150 | 0 bits for subpriority */ 151 | 152 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 153 | ((GROUP) == NVIC_PriorityGroup_1) || \ 154 | ((GROUP) == NVIC_PriorityGroup_2) || \ 155 | ((GROUP) == NVIC_PriorityGroup_3) || \ 156 | ((GROUP) == NVIC_PriorityGroup_4)) 157 | 158 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 159 | 160 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 161 | 162 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /** @defgroup SysTick_clock_source 169 | * @{ 170 | */ 171 | 172 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 173 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 174 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 175 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 176 | /** 177 | * @} 178 | */ 179 | 180 | /** 181 | * @} 182 | */ 183 | 184 | /** @defgroup MISC_Exported_Macros 185 | * @{ 186 | */ 187 | 188 | /** 189 | * @} 190 | */ 191 | 192 | /** @defgroup MISC_Exported_Functions 193 | * @{ 194 | */ 195 | 196 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 197 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 198 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 200 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 201 | 202 | #ifdef __cplusplus 203 | } 204 | #endif 205 | 206 | #endif /* __MISC_H */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /** 217 | * @} 218 | */ 219 | 220 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 221 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the PWR firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_pwr.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup PWR 31 | * @brief PWR driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup PWR_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup PWR_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* --------- PWR registers bit address in the alias region ---------- */ 48 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 49 | 50 | /* --- CR Register ---*/ 51 | 52 | /* Alias word address of DBP bit */ 53 | #define CR_OFFSET (PWR_OFFSET + 0x00) 54 | #define DBP_BitNumber 0x08 55 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 56 | 57 | /* Alias word address of PVDE bit */ 58 | #define PVDE_BitNumber 0x04 59 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of EWUP bit */ 64 | #define CSR_OFFSET (PWR_OFFSET + 0x04) 65 | #define EWUP_BitNumber 0x08 66 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 67 | 68 | /* ------------------ PWR registers bit mask ------------------------ */ 69 | 70 | /* CR register bit mask */ 71 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) 72 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) 73 | 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @defgroup PWR_Private_Macros 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @defgroup PWR_Private_Variables 88 | * @{ 89 | */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup PWR_Private_FunctionPrototypes 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup PWR_Private_Functions 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @brief Deinitializes the PWR peripheral registers to their default reset values. 109 | * @param None 110 | * @retval None 111 | */ 112 | void PWR_DeInit(void) 113 | { 114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 115 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 116 | } 117 | 118 | /** 119 | * @brief Enables or disables access to the RTC and backup registers. 120 | * @param NewState: new state of the access to the RTC and backup registers. 121 | * This parameter can be: ENABLE or DISABLE. 122 | * @retval None 123 | */ 124 | void PWR_BackupAccessCmd(FunctionalState NewState) 125 | { 126 | /* Check the parameters */ 127 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 128 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 129 | } 130 | 131 | /** 132 | * @brief Enables or disables the Power Voltage Detector(PVD). 133 | * @param NewState: new state of the PVD. 134 | * This parameter can be: ENABLE or DISABLE. 135 | * @retval None 136 | */ 137 | void PWR_PVDCmd(FunctionalState NewState) 138 | { 139 | /* Check the parameters */ 140 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 141 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 142 | } 143 | 144 | /** 145 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 146 | * @param PWR_PVDLevel: specifies the PVD detection level 147 | * This parameter can be one of the following values: 148 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 149 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 150 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 151 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 152 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 153 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 154 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 155 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 156 | * @retval None 157 | */ 158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 159 | { 160 | uint32_t tmpreg = 0; 161 | /* Check the parameters */ 162 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 163 | tmpreg = PWR->CR; 164 | /* Clear PLS[7:5] bits */ 165 | tmpreg &= CR_PLS_MASK; 166 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 167 | tmpreg |= PWR_PVDLevel; 168 | /* Store the new value */ 169 | PWR->CR = tmpreg; 170 | } 171 | 172 | /** 173 | * @brief Enables or disables the WakeUp Pin functionality. 174 | * @param NewState: new state of the WakeUp Pin functionality. 175 | * This parameter can be: ENABLE or DISABLE. 176 | * @retval None 177 | */ 178 | void PWR_WakeUpPinCmd(FunctionalState NewState) 179 | { 180 | /* Check the parameters */ 181 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 182 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 183 | } 184 | 185 | /** 186 | * @brief Enters STOP mode. 187 | * @param PWR_Regulator: specifies the regulator state in STOP mode. 188 | * This parameter can be one of the following values: 189 | * @arg PWR_Regulator_ON: STOP mode with regulator ON 190 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 191 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 192 | * This parameter can be one of the following values: 193 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 194 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 195 | * @retval None 196 | */ 197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 198 | { 199 | uint32_t tmpreg = 0; 200 | /* Check the parameters */ 201 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 202 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 203 | 204 | /* Select the regulator state in STOP mode ---------------------------------*/ 205 | tmpreg = PWR->CR; 206 | /* Clear PDDS and LPDS bits */ 207 | tmpreg &= CR_DS_MASK; 208 | /* Set LPDS bit according to PWR_Regulator value */ 209 | tmpreg |= PWR_Regulator; 210 | /* Store the new value */ 211 | PWR->CR = tmpreg; 212 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 213 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 214 | 215 | /* Select STOP mode entry --------------------------------------------------*/ 216 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 217 | { 218 | /* Request Wait For Interrupt */ 219 | __WFI(); 220 | } 221 | else 222 | { 223 | /* Request Wait For Event */ 224 | __WFE(); 225 | } 226 | 227 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ 228 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 229 | } 230 | 231 | /** 232 | * @brief Enters STANDBY mode. 233 | * @param None 234 | * @retval None 235 | */ 236 | void PWR_EnterSTANDBYMode(void) 237 | { 238 | /* Clear Wake-up flag */ 239 | PWR->CR |= PWR_CR_CWUF; 240 | /* Select STANDBY mode */ 241 | PWR->CR |= PWR_CR_PDDS; 242 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 243 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 244 | /* This option is used to ensure that store operations are completed */ 245 | #if defined ( __CC_ARM ) 246 | __force_stores(); 247 | #endif 248 | /* Request Wait For Interrupt */ 249 | __WFI(); 250 | } 251 | 252 | /** 253 | * @brief Checks whether the specified PWR flag is set or not. 254 | * @param PWR_FLAG: specifies the flag to check. 255 | * This parameter can be one of the following values: 256 | * @arg PWR_FLAG_WU: Wake Up flag 257 | * @arg PWR_FLAG_SB: StandBy flag 258 | * @arg PWR_FLAG_PVDO: PVD Output 259 | * @retval The new state of PWR_FLAG (SET or RESET). 260 | */ 261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 262 | { 263 | FlagStatus bitstatus = RESET; 264 | /* Check the parameters */ 265 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 266 | 267 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 268 | { 269 | bitstatus = SET; 270 | } 271 | else 272 | { 273 | bitstatus = RESET; 274 | } 275 | /* Return the flag status */ 276 | return bitstatus; 277 | } 278 | 279 | /** 280 | * @brief Clears the PWR's pending flags. 281 | * @param PWR_FLAG: specifies the flag to clear. 282 | * This parameter can be one of the following values: 283 | * @arg PWR_FLAG_WU: Wake Up flag 284 | * @arg PWR_FLAG_SB: StandBy flag 285 | * @retval None 286 | */ 287 | void PWR_ClearFlag(uint32_t PWR_FLAG) 288 | { 289 | /* Check the parameters */ 290 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 291 | 292 | PWR->CR |= PWR_FLAG << 2; 293 | } 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 308 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the RTC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_rtc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup RTC 30 | * @brief RTC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup RTC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup RTC_Private_Defines 42 | * @{ 43 | */ 44 | #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ 45 | #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ 46 | 47 | /** 48 | * @} 49 | */ 50 | 51 | /** @defgroup RTC_Private_Macros 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @defgroup RTC_Private_Variables 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup RTC_Private_FunctionPrototypes 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup RTC_Private_Functions 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @brief Enables or disables the specified RTC interrupts. 81 | * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. 82 | * This parameter can be any combination of the following values: 83 | * @arg RTC_IT_OW: Overflow interrupt 84 | * @arg RTC_IT_ALR: Alarm interrupt 85 | * @arg RTC_IT_SEC: Second interrupt 86 | * @param NewState: new state of the specified RTC interrupts. 87 | * This parameter can be: ENABLE or DISABLE. 88 | * @retval None 89 | */ 90 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) 91 | { 92 | /* Check the parameters */ 93 | assert_param(IS_RTC_IT(RTC_IT)); 94 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 95 | 96 | if (NewState != DISABLE) 97 | { 98 | RTC->CRH |= RTC_IT; 99 | } 100 | else 101 | { 102 | RTC->CRH &= (uint16_t)~RTC_IT; 103 | } 104 | } 105 | 106 | /** 107 | * @brief Enters the RTC configuration mode. 108 | * @param None 109 | * @retval None 110 | */ 111 | void RTC_EnterConfigMode(void) 112 | { 113 | /* Set the CNF flag to enter in the Configuration Mode */ 114 | RTC->CRL |= RTC_CRL_CNF; 115 | } 116 | 117 | /** 118 | * @brief Exits from the RTC configuration mode. 119 | * @param None 120 | * @retval None 121 | */ 122 | void RTC_ExitConfigMode(void) 123 | { 124 | /* Reset the CNF flag to exit from the Configuration Mode */ 125 | RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 126 | } 127 | 128 | /** 129 | * @brief Gets the RTC counter value. 130 | * @param None 131 | * @retval RTC counter value. 132 | */ 133 | uint32_t RTC_GetCounter(void) 134 | { 135 | uint16_t tmp = 0; 136 | tmp = RTC->CNTL; 137 | return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; 138 | } 139 | 140 | /** 141 | * @brief Sets the RTC counter value. 142 | * @param CounterValue: RTC counter new value. 143 | * @retval None 144 | */ 145 | void RTC_SetCounter(uint32_t CounterValue) 146 | { 147 | RTC_EnterConfigMode(); 148 | /* Set RTC COUNTER MSB word */ 149 | RTC->CNTH = CounterValue >> 16; 150 | /* Set RTC COUNTER LSB word */ 151 | RTC->CNTL = (CounterValue & RTC_LSB_MASK); 152 | RTC_ExitConfigMode(); 153 | } 154 | 155 | /** 156 | * @brief Sets the RTC prescaler value. 157 | * @param PrescalerValue: RTC prescaler new value. 158 | * @retval None 159 | */ 160 | void RTC_SetPrescaler(uint32_t PrescalerValue) 161 | { 162 | /* Check the parameters */ 163 | assert_param(IS_RTC_PRESCALER(PrescalerValue)); 164 | 165 | RTC_EnterConfigMode(); 166 | /* Set RTC PRESCALER MSB word */ 167 | RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; 168 | /* Set RTC PRESCALER LSB word */ 169 | RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); 170 | RTC_ExitConfigMode(); 171 | } 172 | 173 | /** 174 | * @brief Sets the RTC alarm value. 175 | * @param AlarmValue: RTC alarm new value. 176 | * @retval None 177 | */ 178 | void RTC_SetAlarm(uint32_t AlarmValue) 179 | { 180 | RTC_EnterConfigMode(); 181 | /* Set the ALARM MSB word */ 182 | RTC->ALRH = AlarmValue >> 16; 183 | /* Set the ALARM LSB word */ 184 | RTC->ALRL = (AlarmValue & RTC_LSB_MASK); 185 | RTC_ExitConfigMode(); 186 | } 187 | 188 | /** 189 | * @brief Gets the RTC divider value. 190 | * @param None 191 | * @retval RTC Divider value. 192 | */ 193 | uint32_t RTC_GetDivider(void) 194 | { 195 | uint32_t tmp = 0x00; 196 | tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; 197 | tmp |= RTC->DIVL; 198 | return tmp; 199 | } 200 | 201 | /** 202 | * @brief Waits until last write operation on RTC registers has finished. 203 | * @note This function must be called before any write to RTC registers. 204 | * @param None 205 | * @retval None 206 | */ 207 | void RTC_WaitForLastTask(void) 208 | { 209 | /* Loop until RTOFF flag is set */ 210 | while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) 211 | { 212 | } 213 | } 214 | 215 | /** 216 | * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) 217 | * are synchronized with RTC APB clock. 218 | * @note This function must be called before any read operation after an APB reset 219 | * or an APB clock stop. 220 | * @param None 221 | * @retval None 222 | */ 223 | void RTC_WaitForSynchro(void) 224 | { 225 | /* Clear RSF flag */ 226 | RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; 227 | /* Loop until RSF flag is set */ 228 | while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) 229 | { 230 | } 231 | } 232 | 233 | /** 234 | * @brief Checks whether the specified RTC flag is set or not. 235 | * @param RTC_FLAG: specifies the flag to check. 236 | * This parameter can be one the following values: 237 | * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag 238 | * @arg RTC_FLAG_RSF: Registers Synchronized flag 239 | * @arg RTC_FLAG_OW: Overflow flag 240 | * @arg RTC_FLAG_ALR: Alarm flag 241 | * @arg RTC_FLAG_SEC: Second flag 242 | * @retval The new state of RTC_FLAG (SET or RESET). 243 | */ 244 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) 245 | { 246 | FlagStatus bitstatus = RESET; 247 | 248 | /* Check the parameters */ 249 | assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 250 | 251 | if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) 252 | { 253 | bitstatus = SET; 254 | } 255 | else 256 | { 257 | bitstatus = RESET; 258 | } 259 | return bitstatus; 260 | } 261 | 262 | /** 263 | * @brief Clears the RTC's pending flags. 264 | * @param RTC_FLAG: specifies the flag to clear. 265 | * This parameter can be any combination of the following values: 266 | * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after 267 | * an APB reset or an APB Clock stop. 268 | * @arg RTC_FLAG_OW: Overflow flag 269 | * @arg RTC_FLAG_ALR: Alarm flag 270 | * @arg RTC_FLAG_SEC: Second flag 271 | * @retval None 272 | */ 273 | void RTC_ClearFlag(uint16_t RTC_FLAG) 274 | { 275 | /* Check the parameters */ 276 | assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 277 | 278 | /* Clear the corresponding RTC flag */ 279 | RTC->CRL &= (uint16_t)~RTC_FLAG; 280 | } 281 | 282 | /** 283 | * @brief Checks whether the specified RTC interrupt has occurred or not. 284 | * @param RTC_IT: specifies the RTC interrupts sources to check. 285 | * This parameter can be one of the following values: 286 | * @arg RTC_IT_OW: Overflow interrupt 287 | * @arg RTC_IT_ALR: Alarm interrupt 288 | * @arg RTC_IT_SEC: Second interrupt 289 | * @retval The new state of the RTC_IT (SET or RESET). 290 | */ 291 | ITStatus RTC_GetITStatus(uint16_t RTC_IT) 292 | { 293 | ITStatus bitstatus = RESET; 294 | /* Check the parameters */ 295 | assert_param(IS_RTC_GET_IT(RTC_IT)); 296 | 297 | bitstatus = (ITStatus)(RTC->CRL & RTC_IT); 298 | if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) 299 | { 300 | bitstatus = SET; 301 | } 302 | else 303 | { 304 | bitstatus = RESET; 305 | } 306 | return bitstatus; 307 | } 308 | 309 | /** 310 | * @brief Clears the RTC's interrupt pending bits. 311 | * @param RTC_IT: specifies the interrupt pending bit to clear. 312 | * This parameter can be any combination of the following values: 313 | * @arg RTC_IT_OW: Overflow interrupt 314 | * @arg RTC_IT_ALR: Alarm interrupt 315 | * @arg RTC_IT_SEC: Second interrupt 316 | * @retval None 317 | */ 318 | void RTC_ClearITPendingBit(uint16_t RTC_IT) 319 | { 320 | /* Check the parameters */ 321 | assert_param(IS_RTC_IT(RTC_IT)); 322 | 323 | /* Clear the corresponding RTC pending bit */ 324 | RTC->CRL &= (uint16_t)~RTC_IT; 325 | } 326 | 327 | /** 328 | * @} 329 | */ 330 | 331 | /** 332 | * @} 333 | */ 334 | 335 | /** 336 | * @} 337 | */ 338 | 339 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 340 | -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_ld.s 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 26 | * 27 | *

© COPYRIGHT 2011 STMicroelectronics

28 | ****************************************************************************** 29 | */ 30 | 31 | .syntax unified 32 | .cpu cortex-m3 33 | .fpu softvfp 34 | .thumb 35 | 36 | .global g_pfnVectors 37 | .global Default_Handler 38 | 39 | /* start address for the initialization values of the .data section. 40 | defined in linker script */ 41 | .word _sidata 42 | /* start address for the .data section. defined in linker script */ 43 | .word _sdata 44 | /* end address for the .data section. defined in linker script */ 45 | .word _edata 46 | /* start address for the .bss section. defined in linker script */ 47 | .word _sbss 48 | /* end address for the .bss section. defined in linker script */ 49 | .word _ebss 50 | 51 | .equ BootRAM, 0xF108F85F 52 | /** 53 | * @brief This is the code that gets called when the processor first 54 | * starts execution following a reset event. Only the absolutely 55 | * necessary set is performed, after which the application 56 | * supplied main() routine is called. 57 | * @param None 58 | * @retval : None 59 | */ 60 | 61 | .section .text.Reset_Handler 62 | .weak Reset_Handler 63 | .type Reset_Handler, %function 64 | Reset_Handler: 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | movs r1, #0 68 | b LoopCopyDataInit 69 | 70 | CopyDataInit: 71 | ldr r3, =_sidata 72 | ldr r3, [r3, r1] 73 | str r3, [r0, r1] 74 | adds r1, r1, #4 75 | 76 | LoopCopyDataInit: 77 | ldr r0, =_sdata 78 | ldr r3, =_edata 79 | adds r2, r0, r1 80 | cmp r2, r3 81 | bcc CopyDataInit 82 | ldr r2, =_sbss 83 | b LoopFillZerobss 84 | /* Zero fill the bss segment. */ 85 | FillZerobss: 86 | movs r3, #0 87 | str r3, [r2], #4 88 | 89 | LoopFillZerobss: 90 | ldr r3, = _ebss 91 | cmp r2, r3 92 | bcc FillZerobss 93 | /* Call the clock system intitialization function.*/ 94 | bl SystemInit 95 | /* Call the application's entry point.*/ 96 | bl main 97 | bx lr 98 | .size Reset_Handler, .-Reset_Handler 99 | 100 | /** 101 | * @brief This is the code that gets called when the processor receives an 102 | * unexpected interrupt. This simply enters an infinite loop, preserving 103 | * the system state for examination by a debugger. 104 | * @param None 105 | * @retval None 106 | */ 107 | .section .text.Default_Handler,"ax",%progbits 108 | Default_Handler: 109 | Infinite_Loop: 110 | b Infinite_Loop 111 | .size Default_Handler, .-Default_Handler 112 | /****************************************************************************** 113 | * 114 | * The minimal vector table for a Cortex M3. Note that the proper constructs 115 | * must be placed on this to ensure that it ends up at physical address 116 | * 0x0000.0000. 117 | * 118 | ******************************************************************************/ 119 | .section .isr_vector,"a",%progbits 120 | .type g_pfnVectors, %object 121 | .size g_pfnVectors, .-g_pfnVectors 122 | 123 | 124 | g_pfnVectors: 125 | .word _estack 126 | .word Reset_Handler 127 | .word NMI_Handler 128 | .word HardFault_Handler 129 | .word MemManage_Handler 130 | .word BusFault_Handler 131 | .word UsageFault_Handler 132 | .word 0 133 | .word 0 134 | .word 0 135 | .word 0 136 | .word SVC_Handler 137 | .word DebugMon_Handler 138 | .word 0 139 | .word PendSV_Handler 140 | .word SysTick_Handler 141 | .word WWDG_IRQHandler 142 | .word PVD_IRQHandler 143 | .word TAMPER_IRQHandler 144 | .word RTC_IRQHandler 145 | .word FLASH_IRQHandler 146 | .word RCC_IRQHandler 147 | .word EXTI0_IRQHandler 148 | .word EXTI1_IRQHandler 149 | .word EXTI2_IRQHandler 150 | .word EXTI3_IRQHandler 151 | .word EXTI4_IRQHandler 152 | .word DMA1_Channel1_IRQHandler 153 | .word DMA1_Channel2_IRQHandler 154 | .word DMA1_Channel3_IRQHandler 155 | .word DMA1_Channel4_IRQHandler 156 | .word DMA1_Channel5_IRQHandler 157 | .word DMA1_Channel6_IRQHandler 158 | .word DMA1_Channel7_IRQHandler 159 | .word ADC1_2_IRQHandler 160 | .word USB_HP_CAN1_TX_IRQHandler 161 | .word USB_LP_CAN1_RX0_IRQHandler 162 | .word CAN1_RX1_IRQHandler 163 | .word CAN1_SCE_IRQHandler 164 | .word EXTI9_5_IRQHandler 165 | .word TIM1_BRK_IRQHandler 166 | .word TIM1_UP_IRQHandler 167 | .word TIM1_TRG_COM_IRQHandler 168 | .word TIM1_CC_IRQHandler 169 | .word TIM2_IRQHandler 170 | .word TIM3_IRQHandler 171 | .word 0 172 | .word I2C1_EV_IRQHandler 173 | .word I2C1_ER_IRQHandler 174 | .word 0 175 | .word 0 176 | .word SPI1_IRQHandler 177 | .word 0 178 | .word USART1_IRQHandler 179 | .word USART2_IRQHandler 180 | .word 0 181 | .word EXTI15_10_IRQHandler 182 | .word RTCAlarm_IRQHandler 183 | .word USBWakeUp_IRQHandler 184 | .word 0 185 | .word 0 186 | .word 0 187 | .word 0 188 | .word 0 189 | .word 0 190 | .word 0 191 | .word BootRAM /* @0x108. This is for boot in RAM mode for 192 | STM32F10x Low Density devices.*/ 193 | 194 | /******************************************************************************* 195 | * 196 | * Provide weak aliases for each Exception handler to the Default_Handler. 197 | * As they are weak aliases, any function with the same name will override 198 | * this definition. 199 | * 200 | *******************************************************************************/ 201 | 202 | .weak NMI_Handler 203 | .thumb_set NMI_Handler,Default_Handler 204 | 205 | .weak HardFault_Handler 206 | .thumb_set HardFault_Handler,Default_Handler 207 | 208 | .weak MemManage_Handler 209 | .thumb_set MemManage_Handler,Default_Handler 210 | 211 | .weak BusFault_Handler 212 | .thumb_set BusFault_Handler,Default_Handler 213 | 214 | .weak UsageFault_Handler 215 | .thumb_set UsageFault_Handler,Default_Handler 216 | 217 | .weak SVC_Handler 218 | .thumb_set SVC_Handler,Default_Handler 219 | 220 | .weak DebugMon_Handler 221 | .thumb_set DebugMon_Handler,Default_Handler 222 | 223 | .weak PendSV_Handler 224 | .thumb_set PendSV_Handler,Default_Handler 225 | 226 | .weak SysTick_Handler 227 | .thumb_set SysTick_Handler,Default_Handler 228 | 229 | .weak WWDG_IRQHandler 230 | .thumb_set WWDG_IRQHandler,Default_Handler 231 | 232 | .weak PVD_IRQHandler 233 | .thumb_set PVD_IRQHandler,Default_Handler 234 | 235 | .weak TAMPER_IRQHandler 236 | .thumb_set TAMPER_IRQHandler,Default_Handler 237 | 238 | .weak RTC_IRQHandler 239 | .thumb_set RTC_IRQHandler,Default_Handler 240 | 241 | .weak FLASH_IRQHandler 242 | .thumb_set FLASH_IRQHandler,Default_Handler 243 | 244 | .weak RCC_IRQHandler 245 | .thumb_set RCC_IRQHandler,Default_Handler 246 | 247 | .weak EXTI0_IRQHandler 248 | .thumb_set EXTI0_IRQHandler,Default_Handler 249 | 250 | .weak EXTI1_IRQHandler 251 | .thumb_set EXTI1_IRQHandler,Default_Handler 252 | 253 | .weak EXTI2_IRQHandler 254 | .thumb_set EXTI2_IRQHandler,Default_Handler 255 | 256 | .weak EXTI3_IRQHandler 257 | .thumb_set EXTI3_IRQHandler,Default_Handler 258 | 259 | .weak EXTI4_IRQHandler 260 | .thumb_set EXTI4_IRQHandler,Default_Handler 261 | 262 | .weak DMA1_Channel1_IRQHandler 263 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 264 | 265 | .weak DMA1_Channel2_IRQHandler 266 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel3_IRQHandler 269 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel4_IRQHandler 272 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel5_IRQHandler 275 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel6_IRQHandler 278 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel7_IRQHandler 281 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 282 | 283 | .weak ADC1_2_IRQHandler 284 | .thumb_set ADC1_2_IRQHandler,Default_Handler 285 | 286 | .weak USB_HP_CAN1_TX_IRQHandler 287 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 288 | 289 | .weak USB_LP_CAN1_RX0_IRQHandler 290 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 291 | 292 | .weak CAN1_RX1_IRQHandler 293 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 294 | 295 | .weak CAN1_SCE_IRQHandler 296 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 297 | 298 | .weak EXTI9_5_IRQHandler 299 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 300 | 301 | .weak TIM1_BRK_IRQHandler 302 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 303 | 304 | .weak TIM1_UP_IRQHandler 305 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_TRG_COM_IRQHandler 308 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_CC_IRQHandler 311 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 312 | 313 | .weak TIM2_IRQHandler 314 | .thumb_set TIM2_IRQHandler,Default_Handler 315 | 316 | .weak TIM3_IRQHandler 317 | .thumb_set TIM3_IRQHandler,Default_Handler 318 | 319 | .weak I2C1_EV_IRQHandler 320 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 321 | 322 | .weak I2C1_ER_IRQHandler 323 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 324 | 325 | .weak SPI1_IRQHandler 326 | .thumb_set SPI1_IRQHandler,Default_Handler 327 | 328 | .weak USART1_IRQHandler 329 | .thumb_set USART1_IRQHandler,Default_Handler 330 | 331 | .weak USART2_IRQHandler 332 | .thumb_set USART2_IRQHandler,Default_Handler 333 | 334 | .weak EXTI15_10_IRQHandler 335 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 336 | 337 | .weak RTCAlarm_IRQHandler 338 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 339 | 340 | .weak USBWakeUp_IRQHandler 341 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 342 | 343 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 344 | -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_md.s 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 26 | * 27 | *

© COPYRIGHT 2011 STMicroelectronics

28 | ****************************************************************************** 29 | */ 30 | 31 | .syntax unified 32 | .cpu cortex-m3 33 | .fpu softvfp 34 | .thumb 35 | 36 | .global g_pfnVectors 37 | .global Default_Handler 38 | 39 | /* start address for the initialization values of the .data section. 40 | defined in linker script */ 41 | .word _sidata 42 | /* start address for the .data section. defined in linker script */ 43 | .word _sdata 44 | /* end address for the .data section. defined in linker script */ 45 | .word _edata 46 | /* start address for the .bss section. defined in linker script */ 47 | .word _sbss 48 | /* end address for the .bss section. defined in linker script */ 49 | .word _ebss 50 | 51 | .equ BootRAM, 0xF108F85F 52 | /** 53 | * @brief This is the code that gets called when the processor first 54 | * starts execution following a reset event. Only the absolutely 55 | * necessary set is performed, after which the application 56 | * supplied main() routine is called. 57 | * @param None 58 | * @retval : None 59 | */ 60 | 61 | .section .text.Reset_Handler 62 | .weak Reset_Handler 63 | .type Reset_Handler, %function 64 | Reset_Handler: 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | movs r1, #0 68 | b LoopCopyDataInit 69 | 70 | CopyDataInit: 71 | ldr r3, =_sidata 72 | ldr r3, [r3, r1] 73 | str r3, [r0, r1] 74 | adds r1, r1, #4 75 | 76 | LoopCopyDataInit: 77 | ldr r0, =_sdata 78 | ldr r3, =_edata 79 | adds r2, r0, r1 80 | cmp r2, r3 81 | bcc CopyDataInit 82 | ldr r2, =_sbss 83 | b LoopFillZerobss 84 | /* Zero fill the bss segment. */ 85 | FillZerobss: 86 | movs r3, #0 87 | str r3, [r2], #4 88 | 89 | LoopFillZerobss: 90 | ldr r3, = _ebss 91 | cmp r2, r3 92 | bcc FillZerobss 93 | /* Call the clock system intitialization function.*/ 94 | bl SystemInit 95 | /* Call the application's entry point.*/ 96 | bl main 97 | bx lr 98 | .size Reset_Handler, .-Reset_Handler 99 | 100 | /** 101 | * @brief This is the code that gets called when the processor receives an 102 | * unexpected interrupt. This simply enters an infinite loop, preserving 103 | * the system state for examination by a debugger. 104 | * @param None 105 | * @retval None 106 | */ 107 | .section .text.Default_Handler,"ax",%progbits 108 | Default_Handler: 109 | Infinite_Loop: 110 | b Infinite_Loop 111 | .size Default_Handler, .-Default_Handler 112 | /****************************************************************************** 113 | * 114 | * The minimal vector table for a Cortex M3. Note that the proper constructs 115 | * must be placed on this to ensure that it ends up at physical address 116 | * 0x0000.0000. 117 | * 118 | ******************************************************************************/ 119 | .section .isr_vector,"a",%progbits 120 | .type g_pfnVectors, %object 121 | .size g_pfnVectors, .-g_pfnVectors 122 | 123 | 124 | g_pfnVectors: 125 | .word _estack 126 | .word Reset_Handler 127 | .word NMI_Handler 128 | .word HardFault_Handler 129 | .word MemManage_Handler 130 | .word BusFault_Handler 131 | .word UsageFault_Handler 132 | .word 0 133 | .word 0 134 | .word 0 135 | .word 0 136 | .word SVC_Handler 137 | .word DebugMon_Handler 138 | .word 0 139 | .word PendSV_Handler 140 | .word SysTick_Handler 141 | .word WWDG_IRQHandler 142 | .word PVD_IRQHandler 143 | .word TAMPER_IRQHandler 144 | .word RTC_IRQHandler 145 | .word FLASH_IRQHandler 146 | .word RCC_IRQHandler 147 | .word EXTI0_IRQHandler 148 | .word EXTI1_IRQHandler 149 | .word EXTI2_IRQHandler 150 | .word EXTI3_IRQHandler 151 | .word EXTI4_IRQHandler 152 | .word DMA1_Channel1_IRQHandler 153 | .word DMA1_Channel2_IRQHandler 154 | .word DMA1_Channel3_IRQHandler 155 | .word DMA1_Channel4_IRQHandler 156 | .word DMA1_Channel5_IRQHandler 157 | .word DMA1_Channel6_IRQHandler 158 | .word DMA1_Channel7_IRQHandler 159 | .word ADC1_2_IRQHandler 160 | .word USB_HP_CAN1_TX_IRQHandler 161 | .word USB_LP_CAN1_RX0_IRQHandler 162 | .word CAN1_RX1_IRQHandler 163 | .word CAN1_SCE_IRQHandler 164 | .word EXTI9_5_IRQHandler 165 | .word TIM1_BRK_IRQHandler 166 | .word TIM1_UP_IRQHandler 167 | .word TIM1_TRG_COM_IRQHandler 168 | .word TIM1_CC_IRQHandler 169 | .word TIM2_IRQHandler 170 | .word TIM3_IRQHandler 171 | .word TIM4_IRQHandler 172 | .word I2C1_EV_IRQHandler 173 | .word I2C1_ER_IRQHandler 174 | .word I2C2_EV_IRQHandler 175 | .word I2C2_ER_IRQHandler 176 | .word SPI1_IRQHandler 177 | .word SPI2_IRQHandler 178 | .word USART1_IRQHandler 179 | .word USART2_IRQHandler 180 | .word USART3_IRQHandler 181 | .word EXTI15_10_IRQHandler 182 | .word RTCAlarm_IRQHandler 183 | .word USBWakeUp_IRQHandler 184 | .word 0 185 | .word 0 186 | .word 0 187 | .word 0 188 | .word 0 189 | .word 0 190 | .word 0 191 | .word BootRAM /* @0x108. This is for boot in RAM mode for 192 | STM32F10x Medium Density devices. */ 193 | 194 | /******************************************************************************* 195 | * 196 | * Provide weak aliases for each Exception handler to the Default_Handler. 197 | * As they are weak aliases, any function with the same name will override 198 | * this definition. 199 | * 200 | *******************************************************************************/ 201 | 202 | .weak NMI_Handler 203 | .thumb_set NMI_Handler,Default_Handler 204 | 205 | .weak HardFault_Handler 206 | .thumb_set HardFault_Handler,Default_Handler 207 | 208 | .weak MemManage_Handler 209 | .thumb_set MemManage_Handler,Default_Handler 210 | 211 | .weak BusFault_Handler 212 | .thumb_set BusFault_Handler,Default_Handler 213 | 214 | .weak UsageFault_Handler 215 | .thumb_set UsageFault_Handler,Default_Handler 216 | 217 | .weak SVC_Handler 218 | .thumb_set SVC_Handler,Default_Handler 219 | 220 | .weak DebugMon_Handler 221 | .thumb_set DebugMon_Handler,Default_Handler 222 | 223 | .weak PendSV_Handler 224 | .thumb_set PendSV_Handler,Default_Handler 225 | 226 | .weak SysTick_Handler 227 | .thumb_set SysTick_Handler,Default_Handler 228 | 229 | .weak WWDG_IRQHandler 230 | .thumb_set WWDG_IRQHandler,Default_Handler 231 | 232 | .weak PVD_IRQHandler 233 | .thumb_set PVD_IRQHandler,Default_Handler 234 | 235 | .weak TAMPER_IRQHandler 236 | .thumb_set TAMPER_IRQHandler,Default_Handler 237 | 238 | .weak RTC_IRQHandler 239 | .thumb_set RTC_IRQHandler,Default_Handler 240 | 241 | .weak FLASH_IRQHandler 242 | .thumb_set FLASH_IRQHandler,Default_Handler 243 | 244 | .weak RCC_IRQHandler 245 | .thumb_set RCC_IRQHandler,Default_Handler 246 | 247 | .weak EXTI0_IRQHandler 248 | .thumb_set EXTI0_IRQHandler,Default_Handler 249 | 250 | .weak EXTI1_IRQHandler 251 | .thumb_set EXTI1_IRQHandler,Default_Handler 252 | 253 | .weak EXTI2_IRQHandler 254 | .thumb_set EXTI2_IRQHandler,Default_Handler 255 | 256 | .weak EXTI3_IRQHandler 257 | .thumb_set EXTI3_IRQHandler,Default_Handler 258 | 259 | .weak EXTI4_IRQHandler 260 | .thumb_set EXTI4_IRQHandler,Default_Handler 261 | 262 | .weak DMA1_Channel1_IRQHandler 263 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 264 | 265 | .weak DMA1_Channel2_IRQHandler 266 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel3_IRQHandler 269 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel4_IRQHandler 272 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel5_IRQHandler 275 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel6_IRQHandler 278 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel7_IRQHandler 281 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 282 | 283 | .weak ADC1_2_IRQHandler 284 | .thumb_set ADC1_2_IRQHandler,Default_Handler 285 | 286 | .weak USB_HP_CAN1_TX_IRQHandler 287 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 288 | 289 | .weak USB_LP_CAN1_RX0_IRQHandler 290 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 291 | 292 | .weak CAN1_RX1_IRQHandler 293 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 294 | 295 | .weak CAN1_SCE_IRQHandler 296 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 297 | 298 | .weak EXTI9_5_IRQHandler 299 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 300 | 301 | .weak TIM1_BRK_IRQHandler 302 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 303 | 304 | .weak TIM1_UP_IRQHandler 305 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_TRG_COM_IRQHandler 308 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_CC_IRQHandler 311 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 312 | 313 | .weak TIM2_IRQHandler 314 | .thumb_set TIM2_IRQHandler,Default_Handler 315 | 316 | .weak TIM3_IRQHandler 317 | .thumb_set TIM3_IRQHandler,Default_Handler 318 | 319 | .weak TIM4_IRQHandler 320 | .thumb_set TIM4_IRQHandler,Default_Handler 321 | 322 | .weak I2C1_EV_IRQHandler 323 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 324 | 325 | .weak I2C1_ER_IRQHandler 326 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 327 | 328 | .weak I2C2_EV_IRQHandler 329 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 330 | 331 | .weak I2C2_ER_IRQHandler 332 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 333 | 334 | .weak SPI1_IRQHandler 335 | .thumb_set SPI1_IRQHandler,Default_Handler 336 | 337 | .weak SPI2_IRQHandler 338 | .thumb_set SPI2_IRQHandler,Default_Handler 339 | 340 | .weak USART1_IRQHandler 341 | .thumb_set USART1_IRQHandler,Default_Handler 342 | 343 | .weak USART2_IRQHandler 344 | .thumb_set USART2_IRQHandler,Default_Handler 345 | 346 | .weak USART3_IRQHandler 347 | .thumb_set USART3_IRQHandler,Default_Handler 348 | 349 | .weak EXTI15_10_IRQHandler 350 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 351 | 352 | .weak RTCAlarm_IRQHandler 353 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 354 | 355 | .weak USBWakeUp_IRQHandler 356 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 357 | 358 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 359 | -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_ld_vl.s 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 8 | * toolchain. 9 | * This module performs: 10 | * - Set the initial SP 11 | * - Set the initial PC == Reset_Handler, 12 | * - Set the vector table entries with the exceptions ISR address 13 | * - Configure the clock system 14 | * - Branches to main in the C library (which eventually 15 | * calls main()). 16 | * After Reset the Cortex-M3 processor is in Thread mode, 17 | * priority is Privileged, and the Stack is set to Main. 18 | ****************************************************************************** 19 | * @attention 20 | * 21 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 22 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 23 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 24 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 25 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 26 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 27 | * 28 | *

© COPYRIGHT 2011 STMicroelectronics

29 | ****************************************************************************** 30 | */ 31 | 32 | .syntax unified 33 | .cpu cortex-m3 34 | .fpu softvfp 35 | .thumb 36 | 37 | .global g_pfnVectors 38 | .global Default_Handler 39 | 40 | /* start address for the initialization values of the .data section. 41 | defined in linker script */ 42 | .word _sidata 43 | /* start address for the .data section. defined in linker script */ 44 | .word _sdata 45 | /* end address for the .data section. defined in linker script */ 46 | .word _edata 47 | /* start address for the .bss section. defined in linker script */ 48 | .word _sbss 49 | /* end address for the .bss section. defined in linker script */ 50 | .word _ebss 51 | 52 | .equ BootRAM, 0xF108F85F 53 | /** 54 | * @brief This is the code that gets called when the processor first 55 | * starts execution following a reset event. Only the absolutely 56 | * necessary set is performed, after which the application 57 | * supplied main() routine is called. 58 | * @param None 59 | * @retval None 60 | */ 61 | 62 | .section .text.Reset_Handler 63 | .weak Reset_Handler 64 | .type Reset_Handler, %function 65 | Reset_Handler: 66 | 67 | /* Copy the data segment initializers from flash to SRAM */ 68 | movs r1, #0 69 | b LoopCopyDataInit 70 | 71 | CopyDataInit: 72 | ldr r3, =_sidata 73 | ldr r3, [r3, r1] 74 | str r3, [r0, r1] 75 | adds r1, r1, #4 76 | 77 | LoopCopyDataInit: 78 | ldr r0, =_sdata 79 | ldr r3, =_edata 80 | adds r2, r0, r1 81 | cmp r2, r3 82 | bcc CopyDataInit 83 | ldr r2, =_sbss 84 | b LoopFillZerobss 85 | /* Zero fill the bss segment. */ 86 | FillZerobss: 87 | movs r3, #0 88 | str r3, [r2], #4 89 | 90 | LoopFillZerobss: 91 | ldr r3, = _ebss 92 | cmp r2, r3 93 | bcc FillZerobss 94 | /* Call the clock system intitialization function.*/ 95 | bl SystemInit 96 | /* Call the application's entry point.*/ 97 | bl main 98 | bx lr 99 | .size Reset_Handler, .-Reset_Handler 100 | 101 | /** 102 | * @brief This is the code that gets called when the processor receives an 103 | * unexpected interrupt. This simply enters an infinite loop, preserving 104 | * the system state for examination by a debugger. 105 | * @param None 106 | * @retval None 107 | */ 108 | .section .text.Default_Handler,"ax",%progbits 109 | Default_Handler: 110 | Infinite_Loop: 111 | b Infinite_Loop 112 | .size Default_Handler, .-Default_Handler 113 | /****************************************************************************** 114 | * The minimal vector table for a Cortex M3. Note that the proper constructs 115 | * must be placed on this to ensure that it ends up at physical address 116 | * 0x0000.0000. 117 | * 118 | ******************************************************************************/ 119 | .section .isr_vector,"a",%progbits 120 | .type g_pfnVectors, %object 121 | .size g_pfnVectors, .-g_pfnVectors 122 | 123 | g_pfnVectors: 124 | .word _estack 125 | .word Reset_Handler 126 | .word NMI_Handler 127 | .word HardFault_Handler 128 | .word MemManage_Handler 129 | .word BusFault_Handler 130 | .word UsageFault_Handler 131 | .word 0 132 | .word 0 133 | .word 0 134 | .word 0 135 | .word SVC_Handler 136 | .word DebugMon_Handler 137 | .word 0 138 | .word PendSV_Handler 139 | .word SysTick_Handler 140 | .word WWDG_IRQHandler 141 | .word PVD_IRQHandler 142 | .word TAMPER_IRQHandler 143 | .word RTC_IRQHandler 144 | .word FLASH_IRQHandler 145 | .word RCC_IRQHandler 146 | .word EXTI0_IRQHandler 147 | .word EXTI1_IRQHandler 148 | .word EXTI2_IRQHandler 149 | .word EXTI3_IRQHandler 150 | .word EXTI4_IRQHandler 151 | .word DMA1_Channel1_IRQHandler 152 | .word DMA1_Channel2_IRQHandler 153 | .word DMA1_Channel3_IRQHandler 154 | .word DMA1_Channel4_IRQHandler 155 | .word DMA1_Channel5_IRQHandler 156 | .word DMA1_Channel6_IRQHandler 157 | .word DMA1_Channel7_IRQHandler 158 | .word ADC1_IRQHandler 159 | .word 0 160 | .word 0 161 | .word 0 162 | .word 0 163 | .word EXTI9_5_IRQHandler 164 | .word TIM1_BRK_TIM15_IRQHandler 165 | .word TIM1_UP_TIM16_IRQHandler 166 | .word TIM1_TRG_COM_TIM17_IRQHandler 167 | .word TIM1_CC_IRQHandler 168 | .word TIM2_IRQHandler 169 | .word TIM3_IRQHandler 170 | .word 0 171 | .word I2C1_EV_IRQHandler 172 | .word I2C1_ER_IRQHandler 173 | .word 0 174 | .word 0 175 | .word SPI1_IRQHandler 176 | .word 0 177 | .word USART1_IRQHandler 178 | .word USART2_IRQHandler 179 | .word 0 180 | .word EXTI15_10_IRQHandler 181 | .word RTCAlarm_IRQHandler 182 | .word CEC_IRQHandler 183 | .word 0 184 | .word 0 185 | .word 0 186 | .word 0 187 | .word 0 188 | .word 0 189 | .word 0 190 | .word 0 191 | .word 0 192 | .word 0 193 | .word 0 194 | .word TIM6_DAC_IRQHandler 195 | .word TIM7_IRQHandler 196 | .word 0 197 | .word 0 198 | .word 0 199 | .word 0 200 | .word 0 201 | .word 0 202 | .word 0 203 | .word 0 204 | .word 0 205 | .word 0 206 | .word 0 207 | .word 0 208 | .word 0 209 | .word 0 210 | .word 0 211 | .word 0 212 | .word 0 213 | .word 0 214 | .word 0 215 | .word 0 216 | .word 0 217 | .word 0 218 | .word 0 219 | .word 0 220 | .word 0 221 | .word 0 222 | .word 0 223 | .word 0 224 | .word 0 225 | .word 0 226 | .word 0 227 | .word 0 228 | .word 0 229 | .word 0 230 | .word 0 231 | .word 0 232 | .word 0 233 | .word 0 234 | .word 0 235 | .word 0 236 | .word 0 237 | .word 0 238 | .word 0 239 | .word BootRAM /* @0x01CC. This is for boot in RAM mode for 240 | STM32F10x Low Density Value Line devices. */ 241 | 242 | /******************************************************************************* 243 | * Provide weak aliases for each Exception handler to the Default_Handler. 244 | * As they are weak aliases, any function with the same name will override 245 | * this definition. 246 | *******************************************************************************/ 247 | 248 | .weak NMI_Handler 249 | .thumb_set NMI_Handler,Default_Handler 250 | 251 | .weak HardFault_Handler 252 | .thumb_set HardFault_Handler,Default_Handler 253 | 254 | .weak MemManage_Handler 255 | .thumb_set MemManage_Handler,Default_Handler 256 | 257 | .weak BusFault_Handler 258 | .thumb_set BusFault_Handler,Default_Handler 259 | 260 | .weak UsageFault_Handler 261 | .thumb_set UsageFault_Handler,Default_Handler 262 | 263 | .weak SVC_Handler 264 | .thumb_set SVC_Handler,Default_Handler 265 | 266 | .weak DebugMon_Handler 267 | .thumb_set DebugMon_Handler,Default_Handler 268 | 269 | .weak PendSV_Handler 270 | .thumb_set PendSV_Handler,Default_Handler 271 | 272 | .weak SysTick_Handler 273 | .thumb_set SysTick_Handler,Default_Handler 274 | 275 | .weak WWDG_IRQHandler 276 | .thumb_set WWDG_IRQHandler,Default_Handler 277 | 278 | .weak PVD_IRQHandler 279 | .thumb_set PVD_IRQHandler,Default_Handler 280 | 281 | .weak TAMPER_IRQHandler 282 | .thumb_set TAMPER_IRQHandler,Default_Handler 283 | 284 | .weak RTC_IRQHandler 285 | .thumb_set RTC_IRQHandler,Default_Handler 286 | 287 | .weak FLASH_IRQHandler 288 | .thumb_set FLASH_IRQHandler,Default_Handler 289 | 290 | .weak RCC_IRQHandler 291 | .thumb_set RCC_IRQHandler,Default_Handler 292 | 293 | .weak EXTI0_IRQHandler 294 | .thumb_set EXTI0_IRQHandler,Default_Handler 295 | 296 | .weak EXTI1_IRQHandler 297 | .thumb_set EXTI1_IRQHandler,Default_Handler 298 | 299 | .weak EXTI2_IRQHandler 300 | .thumb_set EXTI2_IRQHandler,Default_Handler 301 | 302 | .weak EXTI3_IRQHandler 303 | .thumb_set EXTI3_IRQHandler,Default_Handler 304 | 305 | .weak EXTI4_IRQHandler 306 | .thumb_set EXTI4_IRQHandler,Default_Handler 307 | 308 | .weak DMA1_Channel1_IRQHandler 309 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 310 | 311 | .weak DMA1_Channel2_IRQHandler 312 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 313 | 314 | .weak DMA1_Channel3_IRQHandler 315 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 316 | 317 | .weak DMA1_Channel4_IRQHandler 318 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 319 | 320 | .weak DMA1_Channel5_IRQHandler 321 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 322 | 323 | .weak DMA1_Channel6_IRQHandler 324 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 325 | 326 | .weak DMA1_Channel7_IRQHandler 327 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 328 | 329 | .weak ADC1_IRQHandler 330 | .thumb_set ADC1_IRQHandler,Default_Handler 331 | 332 | .weak EXTI9_5_IRQHandler 333 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 334 | 335 | .weak TIM1_BRK_TIM15_IRQHandler 336 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler 337 | 338 | .weak TIM1_UP_TIM16_IRQHandler 339 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler 340 | 341 | .weak TIM1_TRG_COM_TIM17_IRQHandler 342 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler 343 | 344 | .weak TIM1_CC_IRQHandler 345 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 346 | 347 | .weak TIM2_IRQHandler 348 | .thumb_set TIM2_IRQHandler,Default_Handler 349 | 350 | .weak TIM3_IRQHandler 351 | .thumb_set TIM3_IRQHandler,Default_Handler 352 | 353 | .weak I2C1_EV_IRQHandler 354 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 355 | 356 | .weak I2C1_ER_IRQHandler 357 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 358 | 359 | .weak SPI1_IRQHandler 360 | .thumb_set SPI1_IRQHandler,Default_Handler 361 | 362 | .weak USART1_IRQHandler 363 | .thumb_set USART1_IRQHandler,Default_Handler 364 | 365 | .weak USART2_IRQHandler 366 | .thumb_set USART2_IRQHandler,Default_Handler 367 | 368 | .weak EXTI15_10_IRQHandler 369 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 370 | 371 | .weak RTCAlarm_IRQHandler 372 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 373 | 374 | .weak CEC_IRQHandler 375 | .thumb_set CEC_IRQHandler,Default_Handler 376 | 377 | .weak TIM6_DAC_IRQHandler 378 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 379 | 380 | .weak TIM7_IRQHandler 381 | .thumb_set TIM7_IRQHandler,Default_Handler 382 | 383 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 384 | -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_md_vl.s 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 8 | * toolchain. 9 | * This module performs: 10 | * - Set the initial SP 11 | * - Set the initial PC == Reset_Handler, 12 | * - Set the vector table entries with the exceptions ISR address 13 | * - Configure the clock system 14 | * - Branches to main in the C library (which eventually 15 | * calls main()). 16 | * After Reset the Cortex-M3 processor is in Thread mode, 17 | * priority is Privileged, and the Stack is set to Main. 18 | ****************************************************************************** 19 | * @attention 20 | * 21 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 22 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 23 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 24 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 25 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 26 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 27 | * 28 | *

© COPYRIGHT 2011 STMicroelectronics

29 | ****************************************************************************** 30 | */ 31 | 32 | .syntax unified 33 | .cpu cortex-m3 34 | .fpu softvfp 35 | .thumb 36 | 37 | .global g_pfnVectors 38 | .global Default_Handler 39 | 40 | /* start address for the initialization values of the .data section. 41 | defined in linker script */ 42 | .word _sidata 43 | /* start address for the .data section. defined in linker script */ 44 | .word _sdata 45 | /* end address for the .data section. defined in linker script */ 46 | .word _edata 47 | /* start address for the .bss section. defined in linker script */ 48 | .word _sbss 49 | /* end address for the .bss section. defined in linker script */ 50 | .word _ebss 51 | 52 | .equ BootRAM, 0xF108F85F 53 | /** 54 | * @brief This is the code that gets called when the processor first 55 | * starts execution following a reset event. Only the absolutely 56 | * necessary set is performed, after which the application 57 | * supplied main() routine is called. 58 | * @param None 59 | * @retval None 60 | */ 61 | 62 | .section .text.Reset_Handler 63 | .weak Reset_Handler 64 | .type Reset_Handler, %function 65 | Reset_Handler: 66 | 67 | /* Copy the data segment initializers from flash to SRAM */ 68 | movs r1, #0 69 | b LoopCopyDataInit 70 | 71 | CopyDataInit: 72 | ldr r3, =_sidata 73 | ldr r3, [r3, r1] 74 | str r3, [r0, r1] 75 | adds r1, r1, #4 76 | 77 | LoopCopyDataInit: 78 | ldr r0, =_sdata 79 | ldr r3, =_edata 80 | adds r2, r0, r1 81 | cmp r2, r3 82 | bcc CopyDataInit 83 | ldr r2, =_sbss 84 | b LoopFillZerobss 85 | /* Zero fill the bss segment. */ 86 | FillZerobss: 87 | movs r3, #0 88 | str r3, [r2], #4 89 | 90 | LoopFillZerobss: 91 | ldr r3, = _ebss 92 | cmp r2, r3 93 | bcc FillZerobss 94 | /* Call the clock system intitialization function.*/ 95 | bl SystemInit 96 | /* Call the application's entry point.*/ 97 | bl main 98 | bx lr 99 | .size Reset_Handler, .-Reset_Handler 100 | 101 | /** 102 | * @brief This is the code that gets called when the processor receives an 103 | * unexpected interrupt. This simply enters an infinite loop, preserving 104 | * the system state for examination by a debugger. 105 | * @param None 106 | * @retval None 107 | */ 108 | .section .text.Default_Handler,"ax",%progbits 109 | Default_Handler: 110 | Infinite_Loop: 111 | b Infinite_Loop 112 | .size Default_Handler, .-Default_Handler 113 | /****************************************************************************** 114 | * 115 | * The minimal vector table for a Cortex M3. Note that the proper constructs 116 | * must be placed on this to ensure that it ends up at physical address 117 | * 0x0000.0000. 118 | * 119 | ******************************************************************************/ 120 | .section .isr_vector,"a",%progbits 121 | .type g_pfnVectors, %object 122 | .size g_pfnVectors, .-g_pfnVectors 123 | 124 | g_pfnVectors: 125 | .word _estack 126 | .word Reset_Handler 127 | .word NMI_Handler 128 | .word HardFault_Handler 129 | .word MemManage_Handler 130 | .word BusFault_Handler 131 | .word UsageFault_Handler 132 | .word 0 133 | .word 0 134 | .word 0 135 | .word 0 136 | .word SVC_Handler 137 | .word DebugMon_Handler 138 | .word 0 139 | .word PendSV_Handler 140 | .word SysTick_Handler 141 | .word WWDG_IRQHandler 142 | .word PVD_IRQHandler 143 | .word TAMPER_IRQHandler 144 | .word RTC_IRQHandler 145 | .word FLASH_IRQHandler 146 | .word RCC_IRQHandler 147 | .word EXTI0_IRQHandler 148 | .word EXTI1_IRQHandler 149 | .word EXTI2_IRQHandler 150 | .word EXTI3_IRQHandler 151 | .word EXTI4_IRQHandler 152 | .word DMA1_Channel1_IRQHandler 153 | .word DMA1_Channel2_IRQHandler 154 | .word DMA1_Channel3_IRQHandler 155 | .word DMA1_Channel4_IRQHandler 156 | .word DMA1_Channel5_IRQHandler 157 | .word DMA1_Channel6_IRQHandler 158 | .word DMA1_Channel7_IRQHandler 159 | .word ADC1_IRQHandler 160 | .word 0 161 | .word 0 162 | .word 0 163 | .word 0 164 | .word EXTI9_5_IRQHandler 165 | .word TIM1_BRK_TIM15_IRQHandler 166 | .word TIM1_UP_TIM16_IRQHandler 167 | .word TIM1_TRG_COM_TIM17_IRQHandler 168 | .word TIM1_CC_IRQHandler 169 | .word TIM2_IRQHandler 170 | .word TIM3_IRQHandler 171 | .word TIM4_IRQHandler 172 | .word I2C1_EV_IRQHandler 173 | .word I2C1_ER_IRQHandler 174 | .word I2C2_EV_IRQHandler 175 | .word I2C2_ER_IRQHandler 176 | .word SPI1_IRQHandler 177 | .word SPI2_IRQHandler 178 | .word USART1_IRQHandler 179 | .word USART2_IRQHandler 180 | .word USART3_IRQHandler 181 | .word EXTI15_10_IRQHandler 182 | .word RTCAlarm_IRQHandler 183 | .word CEC_IRQHandler 184 | .word 0 185 | .word 0 186 | .word 0 187 | .word 0 188 | .word 0 189 | .word 0 190 | .word 0 191 | .word 0 192 | .word 0 193 | .word 0 194 | .word 0 195 | .word TIM6_DAC_IRQHandler 196 | .word TIM7_IRQHandler 197 | .word 0 198 | .word 0 199 | .word 0 200 | .word 0 201 | .word 0 202 | .word 0 203 | .word 0 204 | .word 0 205 | .word 0 206 | .word 0 207 | .word 0 208 | .word 0 209 | .word 0 210 | .word 0 211 | .word 0 212 | .word 0 213 | .word 0 214 | .word 0 215 | .word 0 216 | .word 0 217 | .word 0 218 | .word 0 219 | .word 0 220 | .word 0 221 | .word 0 222 | .word 0 223 | .word 0 224 | .word 0 225 | .word 0 226 | .word 0 227 | .word 0 228 | .word 0 229 | .word 0 230 | .word 0 231 | .word 0 232 | .word 0 233 | .word 0 234 | .word 0 235 | .word 0 236 | .word 0 237 | .word 0 238 | .word 0 239 | .word 0 240 | .word BootRAM /* @0x01CC. This is for boot in RAM mode for 241 | STM32F10x Medium Value Line Density devices. */ 242 | 243 | /******************************************************************************* 244 | * Provide weak aliases for each Exception handler to the Default_Handler. 245 | * As they are weak aliases, any function with the same name will override 246 | * this definition. 247 | *******************************************************************************/ 248 | 249 | .weak NMI_Handler 250 | .thumb_set NMI_Handler,Default_Handler 251 | 252 | .weak HardFault_Handler 253 | .thumb_set HardFault_Handler,Default_Handler 254 | 255 | .weak MemManage_Handler 256 | .thumb_set MemManage_Handler,Default_Handler 257 | 258 | .weak BusFault_Handler 259 | .thumb_set BusFault_Handler,Default_Handler 260 | 261 | .weak UsageFault_Handler 262 | .thumb_set UsageFault_Handler,Default_Handler 263 | 264 | .weak SVC_Handler 265 | .thumb_set SVC_Handler,Default_Handler 266 | 267 | .weak DebugMon_Handler 268 | .thumb_set DebugMon_Handler,Default_Handler 269 | 270 | .weak PendSV_Handler 271 | .thumb_set PendSV_Handler,Default_Handler 272 | 273 | .weak SysTick_Handler 274 | .thumb_set SysTick_Handler,Default_Handler 275 | 276 | .weak WWDG_IRQHandler 277 | .thumb_set WWDG_IRQHandler,Default_Handler 278 | 279 | .weak PVD_IRQHandler 280 | .thumb_set PVD_IRQHandler,Default_Handler 281 | 282 | .weak TAMPER_IRQHandler 283 | .thumb_set TAMPER_IRQHandler,Default_Handler 284 | 285 | .weak RTC_IRQHandler 286 | .thumb_set RTC_IRQHandler,Default_Handler 287 | 288 | .weak FLASH_IRQHandler 289 | .thumb_set FLASH_IRQHandler,Default_Handler 290 | 291 | .weak RCC_IRQHandler 292 | .thumb_set RCC_IRQHandler,Default_Handler 293 | 294 | .weak EXTI0_IRQHandler 295 | .thumb_set EXTI0_IRQHandler,Default_Handler 296 | 297 | .weak EXTI1_IRQHandler 298 | .thumb_set EXTI1_IRQHandler,Default_Handler 299 | 300 | .weak EXTI2_IRQHandler 301 | .thumb_set EXTI2_IRQHandler,Default_Handler 302 | 303 | .weak EXTI3_IRQHandler 304 | .thumb_set EXTI3_IRQHandler,Default_Handler 305 | 306 | .weak EXTI4_IRQHandler 307 | .thumb_set EXTI4_IRQHandler,Default_Handler 308 | 309 | .weak DMA1_Channel1_IRQHandler 310 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 311 | 312 | .weak DMA1_Channel2_IRQHandler 313 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 314 | 315 | .weak DMA1_Channel3_IRQHandler 316 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 317 | 318 | .weak DMA1_Channel4_IRQHandler 319 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 320 | 321 | .weak DMA1_Channel5_IRQHandler 322 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 323 | 324 | .weak DMA1_Channel6_IRQHandler 325 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 326 | 327 | .weak DMA1_Channel7_IRQHandler 328 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 329 | 330 | .weak ADC1_IRQHandler 331 | .thumb_set ADC1_IRQHandler,Default_Handler 332 | 333 | .weak EXTI9_5_IRQHandler 334 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 335 | 336 | .weak TIM1_BRK_TIM15_IRQHandler 337 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler 338 | 339 | .weak TIM1_UP_TIM16_IRQHandler 340 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler 341 | 342 | .weak TIM1_TRG_COM_TIM17_IRQHandler 343 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler 344 | 345 | .weak TIM1_CC_IRQHandler 346 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 347 | 348 | .weak TIM2_IRQHandler 349 | .thumb_set TIM2_IRQHandler,Default_Handler 350 | 351 | .weak TIM3_IRQHandler 352 | .thumb_set TIM3_IRQHandler,Default_Handler 353 | 354 | .weak TIM4_IRQHandler 355 | .thumb_set TIM4_IRQHandler,Default_Handler 356 | 357 | .weak I2C1_EV_IRQHandler 358 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 359 | 360 | .weak I2C1_ER_IRQHandler 361 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 362 | 363 | .weak I2C2_EV_IRQHandler 364 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 365 | 366 | .weak I2C2_ER_IRQHandler 367 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 368 | 369 | .weak SPI1_IRQHandler 370 | .thumb_set SPI1_IRQHandler,Default_Handler 371 | 372 | .weak SPI2_IRQHandler 373 | .thumb_set SPI2_IRQHandler,Default_Handler 374 | 375 | .weak USART1_IRQHandler 376 | .thumb_set USART1_IRQHandler,Default_Handler 377 | 378 | .weak USART2_IRQHandler 379 | .thumb_set USART2_IRQHandler,Default_Handler 380 | 381 | .weak USART3_IRQHandler 382 | .thumb_set USART3_IRQHandler,Default_Handler 383 | 384 | .weak EXTI15_10_IRQHandler 385 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 386 | 387 | .weak RTCAlarm_IRQHandler 388 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 389 | 390 | .weak CEC_IRQHandler 391 | .thumb_set CEC_IRQHandler,Default_Handler 392 | 393 | .weak TIM6_DAC_IRQHandler 394 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 395 | 396 | .weak TIM7_IRQHandler 397 | .thumb_set TIM7_IRQHandler,Default_Handler 398 | 399 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 400 | -------------------------------------------------------------------------------- /stm32f10x_lib/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the CEC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_cec.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup CEC 31 | * @brief CEC driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup CEC_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | 44 | /** @defgroup CEC_Private_Defines 45 | * @{ 46 | */ 47 | 48 | /* ------------ CEC registers bit address in the alias region ----------- */ 49 | #define CEC_OFFSET (CEC_BASE - PERIPH_BASE) 50 | 51 | /* --- CFGR Register ---*/ 52 | 53 | /* Alias word address of PE bit */ 54 | #define CFGR_OFFSET (CEC_OFFSET + 0x00) 55 | #define PE_BitNumber 0x00 56 | #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) 57 | 58 | /* Alias word address of IE bit */ 59 | #define IE_BitNumber 0x01 60 | #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) 61 | 62 | /* --- CSR Register ---*/ 63 | 64 | /* Alias word address of TSOM bit */ 65 | #define CSR_OFFSET (CEC_OFFSET + 0x10) 66 | #define TSOM_BitNumber 0x00 67 | #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) 68 | 69 | /* Alias word address of TEOM bit */ 70 | #define TEOM_BitNumber 0x01 71 | #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) 72 | 73 | #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ 74 | #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | 81 | /** @defgroup CEC_Private_Macros 82 | * @{ 83 | */ 84 | 85 | /** 86 | * @} 87 | */ 88 | 89 | 90 | /** @defgroup CEC_Private_Variables 91 | * @{ 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | 99 | /** @defgroup CEC_Private_FunctionPrototypes 100 | * @{ 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | 108 | /** @defgroup CEC_Private_Functions 109 | * @{ 110 | */ 111 | 112 | /** 113 | * @brief Deinitializes the CEC peripheral registers to their default reset 114 | * values. 115 | * @param None 116 | * @retval None 117 | */ 118 | void CEC_DeInit(void) 119 | { 120 | /* Enable CEC reset state */ 121 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); 122 | /* Release CEC from reset state */ 123 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 124 | } 125 | 126 | 127 | /** 128 | * @brief Initializes the CEC peripheral according to the specified 129 | * parameters in the CEC_InitStruct. 130 | * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that 131 | * contains the configuration information for the specified 132 | * CEC peripheral. 133 | * @retval None 134 | */ 135 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) 136 | { 137 | uint16_t tmpreg = 0; 138 | 139 | /* Check the parameters */ 140 | assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 141 | assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); 142 | 143 | /*---------------------------- CEC CFGR Configuration -----------------*/ 144 | /* Get the CEC CFGR value */ 145 | tmpreg = CEC->CFGR; 146 | 147 | /* Clear BTEM and BPEM bits */ 148 | tmpreg &= CFGR_CLEAR_Mask; 149 | 150 | /* Configure CEC: Bit Timing Error and Bit Period Error */ 151 | tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); 152 | 153 | /* Write to CEC CFGR register*/ 154 | CEC->CFGR = tmpreg; 155 | 156 | } 157 | 158 | /** 159 | * @brief Enables or disables the specified CEC peripheral. 160 | * @param NewState: new state of the CEC peripheral. 161 | * This parameter can be: ENABLE or DISABLE. 162 | * @retval None 163 | */ 164 | void CEC_Cmd(FunctionalState NewState) 165 | { 166 | /* Check the parameters */ 167 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 168 | 169 | *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; 170 | 171 | if(NewState == DISABLE) 172 | { 173 | /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ 174 | while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) 175 | { 176 | } 177 | } 178 | } 179 | 180 | /** 181 | * @brief Enables or disables the CEC interrupt. 182 | * @param NewState: new state of the CEC interrupt. 183 | * This parameter can be: ENABLE or DISABLE. 184 | * @retval None 185 | */ 186 | void CEC_ITConfig(FunctionalState NewState) 187 | { 188 | /* Check the parameters */ 189 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 190 | 191 | *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; 192 | } 193 | 194 | /** 195 | * @brief Defines the Own Address of the CEC device. 196 | * @param CEC_OwnAddress: The CEC own address 197 | * @retval None 198 | */ 199 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) 200 | { 201 | /* Check the parameters */ 202 | assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); 203 | 204 | /* Set the CEC own address */ 205 | CEC->OAR = CEC_OwnAddress; 206 | } 207 | 208 | /** 209 | * @brief Sets the CEC prescaler value. 210 | * @param CEC_Prescaler: CEC prescaler new value 211 | * @retval None 212 | */ 213 | void CEC_SetPrescaler(uint16_t CEC_Prescaler) 214 | { 215 | /* Check the parameters */ 216 | assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); 217 | 218 | /* Set the Prescaler value*/ 219 | CEC->PRES = CEC_Prescaler; 220 | } 221 | 222 | /** 223 | * @brief Transmits single data through the CEC peripheral. 224 | * @param Data: the data to transmit. 225 | * @retval None 226 | */ 227 | void CEC_SendDataByte(uint8_t Data) 228 | { 229 | /* Transmit Data */ 230 | CEC->TXD = Data ; 231 | } 232 | 233 | 234 | /** 235 | * @brief Returns the most recent received data by the CEC peripheral. 236 | * @param None 237 | * @retval The received data. 238 | */ 239 | uint8_t CEC_ReceiveDataByte(void) 240 | { 241 | /* Receive Data */ 242 | return (uint8_t)(CEC->RXD); 243 | } 244 | 245 | /** 246 | * @brief Starts a new message. 247 | * @param None 248 | * @retval None 249 | */ 250 | void CEC_StartOfMessage(void) 251 | { 252 | /* Starts of new message */ 253 | *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; 254 | } 255 | 256 | /** 257 | * @brief Transmits message with or without an EOM bit. 258 | * @param NewState: new state of the CEC Tx End Of Message. 259 | * This parameter can be: ENABLE or DISABLE. 260 | * @retval None 261 | */ 262 | void CEC_EndOfMessageCmd(FunctionalState NewState) 263 | { 264 | /* Check the parameters */ 265 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 266 | 267 | /* The data byte will be transmitted with or without an EOM bit*/ 268 | *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; 269 | } 270 | 271 | /** 272 | * @brief Gets the CEC flag status 273 | * @param CEC_FLAG: specifies the CEC flag to check. 274 | * This parameter can be one of the following values: 275 | * @arg CEC_FLAG_BTE: Bit Timing Error 276 | * @arg CEC_FLAG_BPE: Bit Period Error 277 | * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error 278 | * @arg CEC_FLAG_SBE: Start Bit Error 279 | * @arg CEC_FLAG_ACKE: Block Acknowledge Error 280 | * @arg CEC_FLAG_LINE: Line Error 281 | * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error 282 | * @arg CEC_FLAG_TEOM: Tx End Of Message 283 | * @arg CEC_FLAG_TERR: Tx Error 284 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 285 | * @arg CEC_FLAG_RSOM: Rx Start Of Message 286 | * @arg CEC_FLAG_REOM: Rx End Of Message 287 | * @arg CEC_FLAG_RERR: Rx Error 288 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 289 | * @retval The new state of CEC_FLAG (SET or RESET) 290 | */ 291 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 292 | { 293 | FlagStatus bitstatus = RESET; 294 | uint32_t cecreg = 0, cecbase = 0; 295 | 296 | /* Check the parameters */ 297 | assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); 298 | 299 | /* Get the CEC peripheral base address */ 300 | cecbase = (uint32_t)(CEC_BASE); 301 | 302 | /* Read flag register index */ 303 | cecreg = CEC_FLAG >> 28; 304 | 305 | /* Get bit[23:0] of the flag */ 306 | CEC_FLAG &= FLAG_Mask; 307 | 308 | if(cecreg != 0) 309 | { 310 | /* Flag in CEC ESR Register */ 311 | CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); 312 | 313 | /* Get the CEC ESR register address */ 314 | cecbase += 0xC; 315 | } 316 | else 317 | { 318 | /* Get the CEC CSR register address */ 319 | cecbase += 0x10; 320 | } 321 | 322 | if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) 323 | { 324 | /* CEC_FLAG is set */ 325 | bitstatus = SET; 326 | } 327 | else 328 | { 329 | /* CEC_FLAG is reset */ 330 | bitstatus = RESET; 331 | } 332 | 333 | /* Return the CEC_FLAG status */ 334 | return bitstatus; 335 | } 336 | 337 | /** 338 | * @brief Clears the CEC's pending flags. 339 | * @param CEC_FLAG: specifies the flag to clear. 340 | * This parameter can be any combination of the following values: 341 | * @arg CEC_FLAG_TERR: Tx Error 342 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 343 | * @arg CEC_FLAG_RSOM: Rx Start Of Message 344 | * @arg CEC_FLAG_REOM: Rx End Of Message 345 | * @arg CEC_FLAG_RERR: Rx Error 346 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 347 | * @retval None 348 | */ 349 | void CEC_ClearFlag(uint32_t CEC_FLAG) 350 | { 351 | uint32_t tmp = 0x0; 352 | 353 | /* Check the parameters */ 354 | assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); 355 | 356 | tmp = CEC->CSR & 0x2; 357 | 358 | /* Clear the selected CEC flags */ 359 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); 360 | } 361 | 362 | /** 363 | * @brief Checks whether the specified CEC interrupt has occurred or not. 364 | * @param CEC_IT: specifies the CEC interrupt source to check. 365 | * This parameter can be one of the following values: 366 | * @arg CEC_IT_TERR: Tx Error 367 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished 368 | * @arg CEC_IT_RERR: Rx Error 369 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished 370 | * @retval The new state of CEC_IT (SET or RESET). 371 | */ 372 | ITStatus CEC_GetITStatus(uint8_t CEC_IT) 373 | { 374 | ITStatus bitstatus = RESET; 375 | uint32_t enablestatus = 0; 376 | 377 | /* Check the parameters */ 378 | assert_param(IS_CEC_GET_IT(CEC_IT)); 379 | 380 | /* Get the CEC IT enable bit status */ 381 | enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; 382 | 383 | /* Check the status of the specified CEC interrupt */ 384 | if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) 385 | { 386 | /* CEC_IT is set */ 387 | bitstatus = SET; 388 | } 389 | else 390 | { 391 | /* CEC_IT is reset */ 392 | bitstatus = RESET; 393 | } 394 | /* Return the CEC_IT status */ 395 | return bitstatus; 396 | } 397 | 398 | /** 399 | * @brief Clears the CEC's interrupt pending bits. 400 | * @param CEC_IT: specifies the CEC interrupt pending bit to clear. 401 | * This parameter can be any combination of the following values: 402 | * @arg CEC_IT_TERR: Tx Error 403 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished 404 | * @arg CEC_IT_RERR: Rx Error 405 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished 406 | * @retval None 407 | */ 408 | void CEC_ClearITPendingBit(uint16_t CEC_IT) 409 | { 410 | uint32_t tmp = 0x0; 411 | 412 | /* Check the parameters */ 413 | assert_param(IS_CEC_GET_IT(CEC_IT)); 414 | 415 | tmp = CEC->CSR & 0x2; 416 | 417 | /* Clear the selected CEC interrupt pending bits */ 418 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); 419 | } 420 | 421 | /** 422 | * @} 423 | */ 424 | 425 | /** 426 | * @} 427 | */ 428 | 429 | /** 430 | * @} 431 | */ 432 | 433 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 434 | -------------------------------------------------------------------------------- /stm32f10x_lib/CMSIS/CMSIS_changes.htm: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | CMSIS Changes 5 | 6 | 7 | 8 | 73 | 74 | 75 | 76 | 77 |

Changes to CMSIS version V1.20

78 | 79 |
80 | 81 |

1. Removed CMSIS Middelware packages

82 |

83 | CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. 84 |

85 | 86 |

2. SystemFrequency renamed to SystemCoreClock

87 |

88 | The variable name SystemCoreClock is more precise than SystemFrequency 89 | because the variable holds the clock value at which the core is running. 90 |

91 | 92 |

3. Changed startup concept

93 |

94 | The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit 95 | from main) has the weakness that it does not work for controllers which need a already 96 | configuerd clock system to configure the external memory controller. 97 |

98 | 99 |

Changed startup concept

100 |
    101 |
  • 102 | SystemInit() is called from startup file before premain. 103 |
    • 104 |
  • 105 | SystemInit() configures the clock system and also configures 106 | an existing external memory controller. 107 |
    • 108 |
  • 109 | SystemInit() must not use global variables. 110 |
    • 111 |
  • 112 | SystemCoreClock is initialized with a correct predefined value. 113 |
    • 114 |
  • 115 | Additional function void SystemCoreClockUpdate (void) is provided.
    116 | SystemCoreClockUpdate() updates the variable SystemCoreClock 117 | and must be called whenever the core clock is changed.
    118 | SystemCoreClockUpdate() evaluates the clock register settings and calculates 119 | the current core clock. 120 |
    • 121 |
122 | 123 | 124 |

4. Advanced Debug Functions

125 |

126 | ITM communication channel is only capable for OUT direction. To allow also communication for 127 | IN direction a simple concept is provided. 128 |

129 |
    130 |
  • 131 | Global variable volatile int ITM_RxBuffer used for IN data. 132 |
    • 133 |
  • 134 | Function int ITM_CheckChar (void) checks if a new character is available. 135 |
    • 136 |
  • 137 | Function int ITM_ReceiveChar (void) retrieves the new character. 138 |
    • 139 |
140 | 141 |

142 | For detailed explanation see file CMSIS debug support.htm. 143 |

144 | 145 | 146 |

5. Core Register Bit Definitions

147 |

148 | Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the 149 | defines correspond with the Cortex-M Technical Reference Manual. 150 |

151 |

152 | e.g. SysTick structure with bit definitions 153 |

154 | 
155 | /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
156 |   memory mapped structure for SysTick
157 |   @{
158 |  */
159 | typedef struct
160 | {
161 |   __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
162 |   __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
163 |   __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
164 |   __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
165 | } SysTick_Type;
166 | 
167 | /* SysTick Control / Status Register Definitions */
168 | #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
169 | #define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
170 | 
171 | #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
172 | #define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
173 | 
174 | #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
175 | #define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
176 | 
177 | #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
178 | #define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
179 | 
180 | /* SysTick Reload Register Definitions */
181 | #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
182 | #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
183 | 
184 | /* SysTick Current Register Definitions */
185 | #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
186 | #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
187 | 
188 | /* SysTick Calibration Register Definitions */
189 | #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
190 | #define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
191 | 
192 | #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
193 | #define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
194 | 
195 | #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
196 | #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
197 | /*@}*/ /* end of group CMSIS_CM3_SysTick */
198 | 199 |

7. DoxyGen Tags

200 |

201 | DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation 202 | using DoxyGen. 203 |

204 | 205 |

8. Folder Structure

206 |

207 | The folder structure is changed to differentiate the single support packages. 208 |

209 | 210 |
    211 |
  • CM0
    • 212 |
  • CM3 213 |
      214 |
    • CoreSupport
      • 215 |
    • DeviceSupport
      • 216 |
        217 |
      • Vendor 218 |
          219 |
        • Device 220 |
            221 |
          • Startup 222 |
              223 |
            • Toolchain
              • 224 |
            • Toolchain
              • 225 |
            • ...
              • 226 |
            227 |
            • 228 |
          229 |
          • 230 |
        • Device
          • 231 |
        • ...
          • 232 |
        233 |
        • 234 |
      • Vendor
        • 235 |
      • ...
        • 236 |
      237 | 238 |
    • Example 239 |
        240 |
      • Toolchain 241 |
          242 |
        • Device
          • 243 |
        • Device
          • 244 |
        • ...
          • 245 |
        246 |
        • 247 |
      • Toolchain
        • 248 |
      • ...
        • 249 |
      250 |
      • 251 |
    252 |
    • 253 | 254 |
  • Documentation
    • 255 |
256 | 257 |

9. Open Points

258 |

259 | Following points need to be clarified and solved: 260 |

261 |
    262 |
  • 263 |

    264 | Equivalent C and Assembler startup files. 265 |

    266 |

    267 | Is there a need for having C startup files although assembler startup files are 268 | very efficient and do not need to be changed? 269 |

    270 |

    • 271 |
  • 272 |

    273 | Placing of HEAP in external RAM. 274 |

    275 |

    276 | It must be possible to place HEAP in external RAM if the device supports an 277 | external memory controller. 278 |

    279 |
    • 280 |
  • 281 |

    282 | Placing of STACK /HEAP. 283 |

    284 |

    285 | STACK should always be placed at the end of internal RAM. 286 |

    287 |

    288 | If HEAP is placed in internal RAM than it should be placed after RW ZI section. 289 |

    290 |
    • 291 |
  • 292 |

    293 | Removing core_cm3.c and core_cm0.c. 294 |

    295 |

    296 | On a long term the functions in core_cm3.c and core_cm0.c must be replaced with 297 | appropriate compiler intrinsics. 298 |

    299 |
    • 300 |
301 | 302 | 303 |

10. Limitations

304 |

305 | The following limitations are not covered with the current CMSIS version: 306 |

307 |
    308 |
  • 309 | No C startup files for ARM toolchain are provided. 310 |
    • 311 |
  • 312 | No C startup files for GNU toolchain are provided. 313 |
    • 314 |
  • 315 | No C startup files for IAR toolchain are provided. 316 |
    • 317 |
  • 318 | No Tasking projects are provided yet. 319 |
    • 320 |
321 | --------------------------------------------------------------------------------