├── README.md ├── SD-card-controller ├── SD-card-controller-0-r2.core └── SD-card-controller-0-r3.core ├── ac97 └── ac97-1.2-r1.core ├── adv_debug_sys └── adv_debug_sys-3.1.0-r1.core ├── altera_virtual_jtag └── altera_virtual_jtag-1.0-r1.core ├── at25sf081 ├── at25sf081-1.6.core └── files │ └── 0001-Support-memory-initialization-from-plusarg.patch ├── bespoke-silicon-group ├── basejump_stl-hard.core ├── basejump_stl-nonsynth.core ├── basejump_stl.core └── bsg-external-hardfloat.core ├── cdc_utils └── cdc_utils-0.1-r1.core ├── chipsalliance.org └── swerv_el2.core ├── ethmac └── ethmac-0.core ├── fifo └── fifo-1.3-r1.core ├── fusesoc_utils ├── blinky-0.core ├── blinky-1.0.core ├── blinky-1.1.core ├── generators-0.1.3.core ├── generators-0.1.4.core ├── generators-0.1.5.core ├── generators-0.1.6.core └── generators-0.1.7.core ├── i2c ├── files │ └── 0001-add_vlog_tb_utils.patch ├── i2c-1.14-r1.core └── i2c-1.15.core ├── jtag_tap └── jtag_tap-1.13-r1.core ├── jtag_vpi ├── jtag_vpi-r3.core ├── jtag_vpi-r4.core └── jtag_vpi-r5.core ├── mor1kx ├── mor1kx-5.0-r2.core └── mor1kx-5.1.core ├── n25q128a11e ├── files │ ├── 0001-Increase-max-length-for-filenames.patch │ ├── 0002-Optionally-disable-mem-clear-on-startup.patch │ └── 0003-Add-workaround-for-Icarus-Verilog.patch └── n25q128a11e_vg12-1.2-r1.core ├── ompic └── ompic-1.0-r1.core ├── open-logic ├── 3.0.2 │ ├── olo_axi.core │ ├── olo_base.core │ ├── olo_intf.core │ ├── olo_quartus_tutorial.core │ └── olo_vivado_tutorial.core ├── 3.1.0 │ ├── olo_axi.core │ ├── olo_base.core │ ├── olo_intf.core │ ├── olo_quartus_tutorial.core │ └── olo_vivado_tutorial.core ├── 3.2.0 │ ├── olo_axi.core │ ├── olo_base.core │ ├── olo_intf.core │ ├── olo_quartus_tutorial.core │ └── olo_vivado_tutorial.core └── 3.3.0 │ ├── en_cl_fix.core │ ├── olo_axi.core │ ├── olo_base.core │ ├── olo_fix.core │ ├── olo_fix_tutorial.core │ ├── olo_intf.core │ ├── olo_quartus_tutorial.core │ └── olo_vivado_tutorial.core ├── or1k_bootloaders └── or1k_bootloaders-0.9.1-r1.core ├── pulp-platform.org ├── apb-0.1.0.core ├── apb_uart_sv-0.core ├── axi-0.23.0-r1.core ├── axi-0.25.0.core ├── axi-0.6.core ├── axi2apb-0.1.1-r3.core ├── axi_mem_if-0.2.0.core ├── axi_slice-1.1.3-r1.core ├── axi_slice_dc-1.1.1.core ├── common_cells-1.11.0.core ├── common_cells-1.16.4.core ├── common_cells-1.20.core └── include │ └── dummy ├── serv ├── serv-1.0.0-r1.core ├── serv-1.0.0.core ├── serv-1.0.2.core ├── serv-1.1.0.core ├── servant-1.0.0.core ├── servant-1.0.2-r1.core ├── servant-1.0.2.core ├── servant-1.1.0.core ├── serving-0.core ├── serving-1.0.2.core └── serving-1.1.0.core ├── simple_spi └── simple_spi-1.6.1.core ├── stream_utils └── stream_utils-1.3-r1.core ├── timer └── timer-1.0-r1.core ├── uart16550 └── uart16550-1.5.5-r1.core ├── verilator_tb_utils └── verilator_tb_utils-1.0.core ├── verilog-arbiter ├── verilog-arbiter-r2.core └── verilog-arbiter-r3.core ├── verilog-axis ├── verilog-axis-0-r1.core ├── verilog-axis-0-r2.core ├── verilog-axis-0-r3.core └── verilog-axis-0.core ├── vlog_tb_utils └── vlog_tb_utils-1.1-r1.core ├── wb_altera_ddr_wrapper └── wb_altera_ddr_wrapper-0-r1.core ├── wb_bfm └── wb_bfm-1.2.1-r1.core ├── wb_common └── wb_common-1.0.3.core ├── wb_intercon ├── wb_intercon-1.2.2-r1.core ├── wb_intercon-1.2.2.core └── wb_intercon-1.4.1.core ├── wb_ram └── wb_ram-1.1-r1.core ├── wb_sdram_ctrl ├── wb_sdram_ctrl-r3.core └── wb_sdram_ctrl-r4.core ├── wb_streamer └── wb_streamer-1.1-r1.core ├── wiredelay └── wiredelay-0-r1.core └── yosys_cells ├── ecp5-0.8.core └── ice40-0.7.core /README.md: -------------------------------------------------------------------------------- 1 | FuseSoC standard core library 2 | ============================= 3 | 4 | This is the standard core library to be used with [FuseSoC](https://github.com/olofk/fusesoc) 5 | 6 | ### Installation 7 | 8 | This library will be automatically cloned to `~/.local/share/fusesoc/fusesoc-cores` 9 | and added to `fusesoc.conf` when you run `fusesoc init`. 10 | 11 | If you have a existing FuseSoC setup and the above does not work for you, 12 | please consider this alternative installation method. Use git to clone 13 | this repository and add it to your `fusesoc.conf`. For example in 14 | `~/.config/fusesoc/fusesoc.conf`: 15 | 16 | ``` 17 | [main] 18 | cores_root = 19 | /home/joe/work/fusesoc-cores 20 | cache_root = /home/joe/work/fuse-cache 21 | build_root = /home/joe/work/fuse-builds 22 | ``` 23 | 24 | ### Contributing 25 | 26 | Cores for FuseSoC should follow the following guidelines. 27 | 28 | - **No Code** Please do not store code in `fusesoc-cores`. Please store 29 | your code in a separate repo or somewhere it can be fetched with the 30 | `url` provider. 31 | - If your core is really small please consider storing in the 32 | [tiny-cores](http://github.com/fusesoc/tiny-cores) repo. 33 | - **Stay Modern** Use the modern sections in your core file like `fileset` 34 | and `parameter`, please no obsolete `verilog` sections. For details on 35 | migrating old cores to the current standard please refer to the 36 | [FuseSoC migration guide](https://github.com/olofk/fusesoc/blob/master/doc/migrations.adoc). 37 | - **Versioning** Each core should be versioned with either 38 | - **Versioned** For cores where the upstream provider provides a release 39 | version, in git using tags is ideal, please use the corresponding 40 | release version. 41 | - **Pseudo-versioned** When an core's upstream provider is out of your 42 | control and does not use versions please use version `0` and point to 43 | a location which is unique for that revision (e.g. the sha for git 44 | repos or revision for svn repos instead of pointing to master, which 45 | might change over time). If you need to refer to a newer version of 46 | the upstream repo, still without a proper version, step the revision 47 | number (`0-r1`, `0-r2`..etc). 48 | -------------------------------------------------------------------------------- /SD-card-controller/SD-card-controller-0-r2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::SD-card-controller:0-r2 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/verilog/sd_data_xfer_trig.v 9 | - rtl/verilog/sd_crc_16.v 10 | - rtl/verilog/generic_fifo_dc_gray.v 11 | - rtl/verilog/sd_clock_divider.v 12 | - rtl/verilog/sd_cmd_master.v 13 | - rtl/verilog/sd_crc_7.v 14 | - rtl/verilog/sd_cmd_serial_host.v 15 | - rtl/verilog/generic_dpram.v 16 | - rtl/verilog/sdc_controller.v 17 | - rtl/verilog/monostable_domain_cross.v 18 | - rtl/verilog/sd_wb_sel_ctrl.v 19 | - rtl/verilog/sd_data_serial_host.v 20 | - rtl/verilog/sd_controller_wb.v 21 | - rtl/verilog/sd_data_master.v 22 | - rtl/verilog/bistable_domain_cross.v 23 | - rtl/verilog/sd_fifo_filler.v 24 | - rtl/verilog/byte_en_reg.v 25 | - rtl/verilog/edge_detect.v 26 | - rtl/verilog/sd_defines.h : {is_include_file : true} 27 | file_type: verilogSource 28 | 29 | tb: 30 | files: 31 | - bench/verilog/byte_en_reg_tb.sv 32 | - bench/verilog/sd_cmd_serial_host_tb.sv 33 | - bench/verilog/sdModel.v 34 | - bench/verilog/monostable_domain_cross_tb.sv 35 | - bench/verilog/sd_cmd_master_tb.sv 36 | - bench/verilog/sd_data_master_tb.sv 37 | - bench/verilog/wb_master32.v 38 | - bench/verilog/sd_fifo_filler_tb.sv 39 | - bench/verilog/bistable_domain_cross_tb.sv 40 | - bench/verilog/wb_master_behavioral.v : {file_type : verilogSource} 41 | - bench/verilog/sd_controller_wb_tb.sv 42 | - bench/verilog/wb_bus_mon.v 43 | - bench/verilog/sd_wb_sel_ctrl_tb.sv 44 | - bench/verilog/edge_detect_tb.sv 45 | - bench/verilog/wb_slave_behavioral.v 46 | - bench/verilog/sd_data_xfer_trig_tb.sv 47 | - bench/verilog/sd_data_serial_host_tb.sv 48 | - bench/verilog/sd_controller_top_tb.sv 49 | - bench/verilog/wb_model_defines.h : {is_include_file : true} 50 | - sim/rtl_sim/bin/ramdisk2.hex : {file_type : user, copyto: ramdisk2.hex} 51 | - sim/rtl_sim/bin/wb_memory.txt : {file_type : user, copyto : wb_memory.txt} 52 | file_type: systemVerilogSource 53 | 54 | targets: 55 | default: 56 | filesets : [rtl] 57 | tb: 58 | default_tool: modelsim 59 | filesets: [rtl, tb] 60 | parameters : [ramdisk, sd_model_log_file, wb_m_mon_log_file, wb_s_mon_log_file, wb_memory_file] 61 | toplevel : sd_controller_top_tb 62 | 63 | parameters: 64 | ramdisk: 65 | datatype : file 66 | default : ramdisk2.hex 67 | description : Initial simulated SD card contents (in Verilog hex format) 68 | paramtype : vlogparam 69 | 70 | sd_model_log_file: 71 | datatype : file 72 | default : sd_model.log 73 | description : Log file for SD card model 74 | paramtype : vlogparam 75 | 76 | wb_m_mon_log_file: 77 | datatype : file 78 | default : wb_m_mon.log 79 | description : Master monitor log file 80 | paramtype : vlogparam 81 | 82 | wb_s_mon_log_file: 83 | datatype : file 84 | default : wb_s_mon.log 85 | description : Slave monitor log file 86 | paramtype : vlogparam 87 | 88 | wb_memory_file: 89 | datatype : file 90 | default : wb_memory.txt 91 | description : Initial simulated Wishbone memory contents (in Verilog hex format) 92 | paramtype : vlogparam 93 | 94 | provider: 95 | name : github 96 | user : olofk 97 | repo : SD-card-controller 98 | version : c3b637c06e64d212f6d9121a36e07acb3b8d540f 99 | -------------------------------------------------------------------------------- /SD-card-controller/SD-card-controller-0-r3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::SD-card-controller:0-r3 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/verilog/sd_data_xfer_trig.v 9 | - rtl/verilog/sd_crc_16.v 10 | - rtl/verilog/generic_fifo_dc_gray.v 11 | - rtl/verilog/sd_clock_divider.v 12 | - rtl/verilog/sd_cmd_master.v 13 | - rtl/verilog/sd_crc_7.v 14 | - rtl/verilog/sd_cmd_serial_host.v 15 | - rtl/verilog/generic_dpram.v 16 | - rtl/verilog/sdc_controller.v 17 | - rtl/verilog/monostable_domain_cross.v 18 | - rtl/verilog/sd_wb_sel_ctrl.v 19 | - rtl/verilog/sd_data_serial_host.v 20 | - rtl/verilog/sd_controller_wb.v 21 | - rtl/verilog/sd_data_master.v 22 | - rtl/verilog/bistable_domain_cross.v 23 | - rtl/verilog/sd_fifo_filler.v 24 | - rtl/verilog/byte_en_reg.v 25 | - rtl/verilog/edge_detect.v 26 | - rtl/verilog/sd_defines.h : {is_include_file : true} 27 | file_type: verilogSource 28 | 29 | tb: 30 | files: 31 | - bench/verilog/byte_en_reg_tb.sv 32 | - bench/verilog/sd_cmd_serial_host_tb.sv 33 | - bench/verilog/sdModel.v 34 | - bench/verilog/monostable_domain_cross_tb.sv 35 | - bench/verilog/sd_cmd_master_tb.sv 36 | - bench/verilog/sd_data_master_tb.sv 37 | - bench/verilog/wb_master32.v 38 | - bench/verilog/sd_fifo_filler_tb.sv 39 | - bench/verilog/bistable_domain_cross_tb.sv 40 | - bench/verilog/wb_master_behavioral.v : {file_type : verilogSource} 41 | - bench/verilog/sd_controller_wb_tb.sv 42 | - bench/verilog/wb_bus_mon.v 43 | - bench/verilog/sd_wb_sel_ctrl_tb.sv 44 | - bench/verilog/edge_detect_tb.sv 45 | - bench/verilog/wb_slave_behavioral.v 46 | - bench/verilog/sd_data_xfer_trig_tb.sv 47 | - bench/verilog/sd_data_serial_host_tb.sv 48 | - bench/verilog/sd_controller_top_tb.sv 49 | - bench/verilog/wb_model_defines.h : {is_include_file : true} 50 | - sim/rtl_sim/bin/ramdisk2.hex : {file_type : user, copyto: ramdisk2.hex} 51 | - sim/rtl_sim/bin/wb_memory.txt : {file_type : user, copyto : wb_memory.txt} 52 | file_type: systemVerilogSource 53 | 54 | targets: 55 | default: 56 | filesets : [rtl] 57 | 58 | lint: 59 | default_tool: verilator 60 | filesets : [rtl] 61 | tools: 62 | verilator: 63 | mode : lint-only 64 | toplevel : sdc_controller 65 | 66 | tb: 67 | default_tool: modelsim 68 | filesets: [rtl, tb] 69 | parameters : [ramdisk, sd_model_log_file, wb_m_mon_log_file, wb_s_mon_log_file, wb_memory_file] 70 | toplevel : sd_controller_top_tb 71 | 72 | parameters: 73 | ramdisk: 74 | datatype : file 75 | default : ramdisk2.hex 76 | description : Initial simulated SD card contents (in Verilog hex format) 77 | paramtype : vlogparam 78 | 79 | sd_model_log_file: 80 | datatype : file 81 | default : sd_model.log 82 | description : Log file for SD card model 83 | paramtype : vlogparam 84 | 85 | wb_m_mon_log_file: 86 | datatype : file 87 | default : wb_m_mon.log 88 | description : Master monitor log file 89 | paramtype : vlogparam 90 | 91 | wb_s_mon_log_file: 92 | datatype : file 93 | default : wb_s_mon.log 94 | description : Slave monitor log file 95 | paramtype : vlogparam 96 | 97 | wb_memory_file: 98 | datatype : file 99 | default : wb_memory.txt 100 | description : Initial simulated Wishbone memory contents (in Verilog hex format) 101 | paramtype : vlogparam 102 | 103 | provider: 104 | name : github 105 | user : mczerski 106 | repo : SD-card-controller 107 | version : 2825b78e72abd059b15e60febc76fa3546583475 108 | -------------------------------------------------------------------------------- /ac97/ac97-1.2-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | description: OpenCores AC97 Controller core 3 | filesets: 4 | rtl_files: 5 | file_type: verilogSource 6 | files: 7 | - rtl/verilog/ac97_defines.v: 8 | is_include_file: true 9 | - rtl/verilog/ac97_cra.v 10 | - rtl/verilog/ac97_dma_if.v 11 | - rtl/verilog/ac97_dma_req.v 12 | - rtl/verilog/ac97_fifo_ctrl.v 13 | - rtl/verilog/ac97_in_fifo.v 14 | - rtl/verilog/ac97_int.v 15 | - rtl/verilog/ac97_out_fifo.v 16 | - rtl/verilog/ac97_prc.v 17 | - rtl/verilog/ac97_rf.v 18 | - rtl/verilog/ac97_rst.v 19 | - rtl/verilog/ac97_sin.v 20 | - rtl/verilog/ac97_soc.v 21 | - rtl/verilog/ac97_sout.v 22 | - rtl/verilog/ac97_top.v 23 | - rtl/verilog/ac97_wb_if.v 24 | tb_files: 25 | file_type: verilogSource 26 | files: 27 | - bench/verilog/ac97_codec_sin.v 28 | - bench/verilog/ac97_codec_sout.v 29 | - bench/verilog/ac97_codec_top.v 30 | - bench/verilog/test_bench_top.v 31 | - bench/verilog/tests.v: 32 | is_include_file: true 33 | - bench/verilog/wb_mast_model.v 34 | - bench/verilog/wb_model_defines.v: 35 | is_include_file: true 36 | name: ::ac97:1.2-r1 37 | provider: 38 | name: github 39 | patches: [] 40 | repo: ac97 41 | user: freecores 42 | version: a47e1fd5a2c5b9eb962b4790ab31873772b457e5 43 | targets: 44 | default: 45 | filesets: 46 | - rtl_files 47 | - tb_files 48 | sim: 49 | default_tool: icarus 50 | filesets: 51 | - rtl_files 52 | - tb_files 53 | toplevel: test 54 | synth: 55 | filesets: 56 | - rtl_files 57 | -------------------------------------------------------------------------------- /adv_debug_sys/adv_debug_sys-3.1.0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::adv_debug_sys:3.1.0-r1 4 | 5 | filesets: 6 | adv_dbg_if: 7 | files: 8 | - Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v: {is_include_file : true} 9 | - Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v: {is_include_file : true} 10 | - Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v 11 | - Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v 12 | - Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v 13 | - Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v 14 | - Hardware/adv_dbg_if/rtl/verilog/syncflop.v 15 | - Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v 16 | - Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_module.v 17 | - Hardware/adv_dbg_if/rtl/verilog/adbg_top.v 18 | - Hardware/adv_dbg_if/rtl/verilog/bytefifo.v 19 | - Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v 20 | - Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v 21 | - Hardware/adv_dbg_if/rtl/verilog/syncreg.v 22 | - Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v 23 | file_type : verilogSource 24 | 25 | jsp_tb: 26 | files: 27 | - Hardware/jtag/tap/rtl/verilog/tap_defines.v: {is_include_file : true} 28 | - Hardware/jtag/tap/rtl/verilog/tap_top.v 29 | - Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v 30 | file_type : verilogSource 31 | 32 | targets: 33 | default: 34 | filesets : [adv_dbg_if] 35 | jsp_tb: 36 | default_tool : icarus 37 | filesets : [adv_dbg_if, jsp_tb] 38 | toplevel : [adv_debug_tb] 39 | provider: 40 | name : github 41 | user : olofk 42 | repo : adv_debug_sys 43 | version : ADS_RELEASE_3_1_0 44 | -------------------------------------------------------------------------------- /altera_virtual_jtag/altera_virtual_jtag-1.0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: ::altera_virtual_jtag:1.0-r1 3 | description: Advanced Debug System wrapper for altera virtual jtag 4 | 5 | filesets: 6 | rtl_files: 7 | files: [altera_virtual_jtag.v : {file_type: verilogSource}] 8 | 9 | targets: 10 | default: 11 | filesets: [rtl_files] 12 | 13 | provider: 14 | name: url 15 | filetype: simple 16 | url: https://raw.githubusercontent.com/fusesoc/tiny-cores/2353a67ee0e51e3d458eb7bc71a8e1d06438a31c/altera_virtual_jtag/altera_virtual_jtag.v 17 | -------------------------------------------------------------------------------- /at25sf081/at25sf081-1.6.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::at25sf081:1.6 4 | 5 | filesets: 6 | model: 7 | files: 8 | - AT25SF081.v : {file_type : verilogSource} 9 | 10 | targets: 11 | default: 12 | filesets : [model] 13 | parameters : [spi_flash_file] 14 | 15 | parameters: 16 | spi_flash_file: 17 | datatype : file 18 | description : Initial SPI Flash contents (in Verilog hex format) 19 | paramtype : plusarg 20 | 21 | provider: 22 | name : url 23 | url : https://www.adestotech.com/sites/default/files/tools_download/Verilog_AT25SF081.zip 24 | filetype : zip 25 | user-agent: FuseSoC 26 | patches : [files/0001-Support-memory-initialization-from-plusarg.patch] 27 | -------------------------------------------------------------------------------- /at25sf081/files/0001-Support-memory-initialization-from-plusarg.patch: -------------------------------------------------------------------------------- 1 | From 7d3c05a954f8ee0d43da634e853c29de88bf6545 Mon Sep 17 00:00:00 2001 2 | From: Olof Kindgren 3 | Date: Fri, 17 Aug 2018 13:17:24 +0200 4 | Subject: [PATCH] Support memory initialization from plusarg 5 | 6 | --- 7 | AT25SF081.v | 3 +++ 8 | 1 file changed, 3 insertions(+) 9 | 10 | diff --git a/AT25SF081.v b/AT25SF081.v 11 | index 4eb520c..f0684d0 100644 12 | --- a/AT25SF081.v 13 | +++ b/AT25SF081.v 14 | @@ -435,12 +435,15 @@ module AT25SF081( SCLK, 15 | /*----------------------------------------------------------------------*/ 16 | /* initial flash data */ 17 | /*----------------------------------------------------------------------*/ 18 | + reg [1023:0] spi_flash_file; 19 | initial 20 | begin : memory_initialize 21 | for ( i = 0; i <= TOP_Add; i = i + 1 ) 22 | ARRAY[i] = 8'hff; 23 | if ( CELL_DATA != "empty" ) 24 | $readmemh("CELL_DATA",ARRAY) ; 25 | + else if( $value$plusargs("spi_flash_file=%s", spi_flash_file) ) 26 | + $readmemh(spi_flash_file, ARRAY); 27 | 28 | for( i = 0; i <= Secur_TOP_Add; i = i + 1 ) begin 29 | Secur_ARRAY[i]=8'hff; 30 | -- 31 | 2.16.4 32 | 33 | -------------------------------------------------------------------------------- /bespoke-silicon-group/basejump_stl-hard.core: -------------------------------------------------------------------------------- 1 | CAPI=2: '' 2 | ############################################################### 3 | # WARNING-AUTOGENERATED: DO NOT MODIFY # 4 | # Auto-generated by: # 5 | # https://github.com/dpetrisko/basejump_stl_cores # 6 | # # 7 | # Please submit issues / PRs to the generator repo instead! # 8 | ############################################################### 9 | name: bespoke-silicon-group:basejump_stl:hard:0.0.1 10 | description: 'BaseJump STL: A Standard Template Library for SystemVerilog (Hardened)' 11 | filesets: 12 | rtl: 13 | files: 14 | - hard/fakeram/bsg_mem_1rw_sync_macros.svh: 15 | is_include_file: true 16 | - hard/fakeram/bsg_mem_1rw_sync_mask_write_bit_macros.svh: 17 | is_include_file: true 18 | - hard/fakeram/bsg_mem_1rw_sync_mask_write_byte_macros.svh: 19 | is_include_file: true 20 | - hard/generic/bsg_mem/bsg_mem_1r1w_sync_macros.svh: 21 | is_include_file: true 22 | - hard/generic/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_macros.svh: 23 | is_include_file: true 24 | - hard/generic/bsg_mem/bsg_mem_1r1w_sync_mask_write_byte_macros.svh: 25 | is_include_file: true 26 | - hard/generic/bsg_mem/bsg_mem_1rw_sync_macros.svh: 27 | is_include_file: true 28 | - hard/generic/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_macros.svh: 29 | is_include_file: true 30 | - hard/generic/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_macros.svh: 31 | is_include_file: true 32 | - hard/generic/bsg_mem/bsg_mem_2r1w_sync_macros.svh: 33 | is_include_file: true 34 | - hard/generic/bsg_mem/bsg_mem_2rw_sync_macros.svh: 35 | is_include_file: true 36 | - hard/generic/bsg_mem/bsg_mem_2rw_sync_mask_write_bit_macros.svh: 37 | is_include_file: true 38 | - hard/generic/bsg_mem/bsg_mem_2rw_sync_mask_write_byte_macros.svh: 39 | is_include_file: true 40 | - hard/generic/bsg_mem/bsg_mem_3r1w_sync_macros.svh: 41 | is_include_file: true 42 | - hard/gf_14/bsg_mem/bsg_mem_1r1w_sync_macros.svh: 43 | is_include_file: true 44 | - hard/gf_14/bsg_mem/bsg_mem_1rw_sync_macros.svh: 45 | is_include_file: true 46 | - hard/gf_14/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_macros.svh: 47 | is_include_file: true 48 | - hard/gf_14/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_macros.svh: 49 | is_include_file: true 50 | - hard/gf_14/bsg_mem/bsg_mem_2r1w_sync_macros.svh: 51 | is_include_file: true 52 | - hard/gf_14/bsg_mem/bsg_mem_3r1w_sync_macros.svh: 53 | is_include_file: true 54 | - hard/tsmc_28/bsg_mem/bsg_mem_1r1w_sync_macros.svh: 55 | is_include_file: true 56 | - hard/tsmc_28/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_macros.svh: 57 | is_include_file: true 58 | - hard/tsmc_28/bsg_mem/bsg_mem_1r1w_sync_mask_write_byte_macros.svh: 59 | is_include_file: true 60 | - hard/tsmc_28/bsg_mem/bsg_mem_1rw_sync_macros.svh: 61 | is_include_file: true 62 | - hard/tsmc_28/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_macros.svh: 63 | is_include_file: true 64 | - hard/tsmc_28/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_macros.svh: 65 | is_include_file: true 66 | - hard/tsmc_28/bsg_mem/bsg_mem_2r1w_sync_macros.svh: 67 | is_include_file: true 68 | - hard/tsmc_28/bsg_mem/bsg_mem_2rw_sync_macros.svh: 69 | is_include_file: true 70 | - hard/tsmc_28/bsg_mem/bsg_mem_2rw_sync_mask_write_bit_macros.svh: 71 | is_include_file: true 72 | - hard/tsmc_28/bsg_mem/bsg_mem_2rw_sync_mask_write_byte_macros.svh: 73 | is_include_file: true 74 | - hard/tsmc_28/bsg_mem/bsg_mem_3r1w_sync_macros.svh: 75 | is_include_file: true 76 | - hard/gf_14/bsg_async/bsg_launch_sync_sync.sv 77 | - hard/gf_14/bsg_async/bsg_sync_sync.sv 78 | - hard/gf_14/bsg_clk_gen/bsg_clk_gen_osc.sv 79 | - hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.sv 80 | - hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.sv 81 | - hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.sv 82 | - hard/gf_14/bsg_link/bsg_link_isdr_phy.sv 83 | - hard/gf_14/bsg_link/bsg_link_osdr_phy.sv 84 | - hard/gf_14/bsg_misc/bsg_mux.sv 85 | - hard/gf_14/bsg_misc/bsg_tiehi.sv 86 | - hard/gf_14/bsg_misc/bsg_tielo.sv 87 | - hard/pickle_40/bsg_mem/bsg_mem_1rw_sync.sv 88 | - hard/pickle_40/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 89 | - hard/pickle_40/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 90 | - hard/pickle_40/bsg_mem/bsg_mem_2r1w_sync.sv 91 | - hard/saed_90/bsg_mem/bsg_mem_1r1w.sv 92 | - hard/saed_90/bsg_mem/bsg_mem_1r1w_sync.sv 93 | - hard/saed_90/bsg_mem/bsg_mem_1rw_sync.sv 94 | - hard/saed_90/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 95 | - hard/saed_90/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 96 | - hard/saed_90/bsg_misc/bsg_clkgate_optional.sv 97 | - hard/saed_90/bsg_misc/bsg_dff_gatestack.sv 98 | - hard/saed_90/bsg_misc/bsg_mux2_gatestack.sv 99 | - hard/saed_90/bsg_misc/bsg_muxi2_gatestack.sv 100 | - hard/tsmc_16/bsg_async/bsg_launch_sync_sync.sv 101 | - hard/tsmc_16/bsg_async/bsg_sync_sync.sv 102 | - hard/tsmc_16/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv 103 | - hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync.sv 104 | - hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 105 | - hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 106 | - hard/tsmc_16/bsg_mem/bsg_mem_2r1w_sync.sv 107 | - hard/tsmc_16/bsg_misc/bsg_level_shift_up_down_sink.sv 108 | - hard/tsmc_16/bsg_misc/bsg_level_shift_up_down_source.sv 109 | - hard/tsmc_16/bsg_misc/bsg_mux.sv 110 | - hard/tsmc_28/bsg_async/bsg_launch_sync_sync.sv 111 | - hard/tsmc_28/bsg_async/bsg_sync_sync.sv 112 | - hard/tsmc_28/bsg_async/bsg_sync_sync_async_reset_unit.sv 113 | - hard/tsmc_28/bsg_async/bsg_sync_sync_unit.sv 114 | - hard/tsmc_28/bsg_clk_gen/bsg_clk_gen_osc_v3.sv 115 | - hard/tsmc_28/bsg_clk_gen/bsg_rp_clk_gen_osc_unit_v3.sv 116 | - hard/tsmc_28/bsg_clk_gen/bsg_rp_clk_gen_osc_v3.sv 117 | - hard/tsmc_28/bsg_dmc/bsg_dmc_dly_line_v3.sv 118 | - hard/tsmc_28/bsg_dmc/bsg_rp_dly_line_v3.sv 119 | - hard/tsmc_28/bsg_link/bsg_link_isdr_phy.sv 120 | - hard/tsmc_28/bsg_link/bsg_link_osdr_phy.sv 121 | - hard/tsmc_28/bsg_misc/bsg_buf.sv 122 | - hard/tsmc_28/bsg_misc/bsg_dff.sv 123 | - hard/tsmc_28/bsg_misc/bsg_mux.sv 124 | - hard/tsmc_28/bsg_misc/bsg_nand.sv 125 | - hard/tsmc_28/bsg_misc/bsg_nor3.sv 126 | - hard/tsmc_28/bsg_misc/bsg_tiehi.sv 127 | - hard/tsmc_28/bsg_misc/bsg_tielo.sv 128 | - hard/tsmc_28/bsg_misc/bsg_xnor.sv 129 | - hard/tsmc_40/bsg_clk_gen/bsg_clk_gen_osc.sv 130 | - hard/tsmc_40/bsg_clk_gen/bsg_dly_line.sv 131 | - hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.sv 132 | - hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.sv 133 | - hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.sv 134 | - hard/tsmc_40/bsg_mem/bsg_mem_1r1w.sv 135 | - hard/tsmc_40/bsg_mem/bsg_mem_1r1w_sync.sv 136 | - hard/tsmc_40/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv 137 | - hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync.sv 138 | - hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 139 | - hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 140 | - hard/tsmc_40/bsg_mem/bsg_mem_2r1w.sv 141 | - hard/tsmc_40/bsg_mem/bsg_mem_2r1w_sync.sv 142 | - hard/tsmc_40/bsg_misc/bsg_and.sv 143 | - hard/tsmc_40/bsg_misc/bsg_buf.sv 144 | - hard/tsmc_40/bsg_misc/bsg_clkbuf.sv 145 | - hard/tsmc_40/bsg_misc/bsg_dff.sv 146 | - hard/tsmc_40/bsg_misc/bsg_dff_en.sv 147 | - hard/tsmc_40/bsg_misc/bsg_dff_reset.sv 148 | - hard/tsmc_40/bsg_misc/bsg_dff_reset_en.sv 149 | - hard/tsmc_40/bsg_misc/bsg_inv.sv 150 | - hard/tsmc_40/bsg_misc/bsg_mux.sv 151 | - hard/tsmc_40/bsg_misc/bsg_mux_bitwise.sv 152 | - hard/tsmc_40/bsg_misc/bsg_mux_one_hot.sv 153 | - hard/tsmc_40/bsg_misc/bsg_nand.sv 154 | - hard/tsmc_40/bsg_misc/bsg_nor3.sv 155 | - hard/tsmc_40/bsg_misc/bsg_reduce.sv 156 | - hard/tsmc_40/bsg_misc/bsg_tiehi.sv 157 | - hard/tsmc_40/bsg_misc/bsg_tielo.sv 158 | - hard/tsmc_40/bsg_misc/bsg_xnor.sv 159 | - hard/tsmc_40/bsg_misc/bsg_xor.sv 160 | - hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_and_csa_block_hard.sv 161 | - hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.sv 162 | - hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_comp42_rep.sv 163 | - hard/tsmc_180_250/bsg_clk_gen/bsg_clk_gen_osc.sv 164 | - hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.sv 165 | - hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.sv 166 | - hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.sv 167 | - hard/tsmc_180_250/bsg_dataflow/bsg_fifo_shift_datapath.sv 168 | - hard/tsmc_180_250/bsg_mem/bsg_mem_1r1w.sv 169 | - hard/tsmc_180_250/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv 170 | - hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync.sv 171 | - hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 172 | - hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 173 | - hard/tsmc_180_250/bsg_mem/bsg_mem_2r1w.sv 174 | - hard/tsmc_180_250/bsg_mem/bsg_mem_2r1w_sync.sv 175 | - hard/tsmc_180_250/bsg_misc/bsg_and.sv 176 | - hard/tsmc_180_250/bsg_misc/bsg_buf.sv 177 | - hard/tsmc_180_250/bsg_misc/bsg_clkbuf.sv 178 | - hard/tsmc_180_250/bsg_misc/bsg_dff.sv 179 | - hard/tsmc_180_250/bsg_misc/bsg_dff_en.sv 180 | - hard/tsmc_180_250/bsg_misc/bsg_dff_reset.sv 181 | - hard/tsmc_180_250/bsg_misc/bsg_dff_reset_en.sv 182 | - hard/tsmc_180_250/bsg_misc/bsg_inv.sv 183 | - hard/tsmc_180_250/bsg_misc/bsg_mux.sv 184 | - hard/tsmc_180_250/bsg_misc/bsg_mux_one_hot.sv 185 | - hard/tsmc_180_250/bsg_misc/bsg_nand.sv 186 | - hard/tsmc_180_250/bsg_misc/bsg_nor3.sv 187 | - hard/tsmc_180_250/bsg_misc/bsg_reduce.sv 188 | - hard/tsmc_180_250/bsg_misc/bsg_tiehi.sv 189 | - hard/tsmc_180_250/bsg_misc/bsg_tielo.sv 190 | - hard/tsmc_180_250/bsg_misc/bsg_xnor.sv 191 | - hard/tsmc_180_250/bsg_misc/bsg_xor.sv 192 | - hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_and_csa_block_hard.sv 193 | - hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.sv 194 | - hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_comp42_rep.sv 195 | - hard/ultrascale_plus/2019.1/bsg_mem_1r1w_sync_mask_write_byte.sv 196 | - hard/ultrascale_plus/2019.1/bsg_mem_1rw_sync_mask_write_bit.sv 197 | - hard/ultrascale_plus/2019.1/bsg_mem_1rw_sync_mask_write_byte.sv 198 | - hard/ultrascale_plus/bsg_async/bsg_launch_sync_sync.sv 199 | - hard/ultrascale_plus/bsg_link/bsg_link_ddr_upstream.sv 200 | - hard/ultrascale_plus/bsg_link/bsg_link_iddr_phy.sv 201 | - hard/ultrascale_plus/bsg_link/bsg_link_oddr_phy.sv 202 | - hard/ultrascale_plus/bsg_mem/bsg_mem_1r1w_sync.sv 203 | - hard/ultrascale_plus/bsg_mem/bsg_mem_1r1w_sync_mask_write_byte.sv 204 | - hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync.sv 205 | - hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 206 | - hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 207 | - hard/ultrascale_plus/bsg_misc/bsg_clkgate_optional.sv 208 | - hard/ultrascale_plus/bsg_misc/bsg_mul_add_unsigned.sv 209 | - hard/ultrascale_plus/bsg_misc/bsg_mux.sv 210 | file_type: systemVerilogSource 211 | nonsynth: {} 212 | provider: 213 | name: github 214 | user: bespoke-silicon-group 215 | repo: basejump_stl 216 | version: v0.0.1 217 | -------------------------------------------------------------------------------- /bespoke-silicon-group/basejump_stl-nonsynth.core: -------------------------------------------------------------------------------- 1 | CAPI=2: '' 2 | ############################################################### 3 | # WARNING-AUTOGENERATED: DO NOT MODIFY # 4 | # Auto-generated by: # 5 | # https://github.com/dpetrisko/basejump_stl_cores # 6 | # # 7 | # Please submit issues / PRs to the generator repo instead! # 8 | ############################################################### 9 | name: bespoke-silicon-group:basejump_stl:nonsynth:0.0.1 10 | description: 'BaseJump STL: A Standard Template Library for SystemVerilog (Nonsynthesizable)' 11 | filesets: 12 | rtl: 13 | files: 14 | - bsg_cache/bsg_nonsynth_cache_axe_tracer.sv 15 | - bsg_clk_gen/bsg_nonsynth_clk_watcher.sv 16 | - bsg_mem/bsg_nonsynth_mem_1r1w_sync_dma.sv 17 | - bsg_mem/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv 18 | - bsg_mem/bsg_nonsynth_mem_1rw_sync_assoc.sv 19 | - bsg_mem/bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc.sv 20 | - bsg_mem/bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv 21 | - bsg_test/bsg_nonsynth_ascii_writer.sv 22 | - bsg_test/bsg_nonsynth_axi_mem.sv 23 | - bsg_test/bsg_nonsynth_clock_gen.sv 24 | - bsg_test/bsg_nonsynth_clock_gen_plusarg.sv 25 | - bsg_test/bsg_nonsynth_delay_line.sv 26 | - bsg_test/bsg_nonsynth_dpi_clock_gen.sv 27 | - bsg_test/bsg_nonsynth_dpi_cycle_counter.sv 28 | - bsg_test/bsg_nonsynth_dpi_from_fifo.sv 29 | - bsg_test/bsg_nonsynth_dpi_gpio.sv 30 | - bsg_test/bsg_nonsynth_dpi_rom.sv 31 | - bsg_test/bsg_nonsynth_dpi_to_fifo.sv 32 | - bsg_test/bsg_nonsynth_dramsim3.sv 33 | - bsg_test/bsg_nonsynth_dramsim3_map.sv 34 | - bsg_test/bsg_nonsynth_dramsim3_unmap.sv 35 | - bsg_test/bsg_nonsynth_ramulator_hbm.sv 36 | - bsg_test/bsg_nonsynth_random_gen.sv 37 | - bsg_test/bsg_nonsynth_test_rom.sv 38 | - bsg_test/bsg_nonsynth_triwire.sv 39 | - bsg_test/bsg_nonsynth_val_watcher_1p.sv 40 | - bsg_test/bsg_nonsynth_profiler.sv 41 | - bsg_test/bsg_nonsynth_reset_gen.sv 42 | - bsg_test/bsg_nonsynth_sha256.sv 43 | file_type: systemVerilogSource 44 | nonsynth: 45 | files: 46 | - bsg_mem/bsg_mem_dma.cpp 47 | - bsg_test/bsg_dramsim3.cpp 48 | - bsg_test/bsg_nonsynth_dpi_clock_gen.cpp 49 | - bsg_test/bsg_ramulator_hbm.cpp 50 | file_type: cppSource 51 | provider: 52 | name: github 53 | user: bespoke-silicon-group 54 | repo: basejump_stl 55 | version: v0.0.1 56 | -------------------------------------------------------------------------------- /bespoke-silicon-group/basejump_stl.core: -------------------------------------------------------------------------------- 1 | CAPI=2: '' 2 | ############################################################### 3 | # WARNING-AUTOGENERATED: DO NOT MODIFY # 4 | # Auto-generated by: # 5 | # https://github.com/dpetrisko/basejump_stl_cores # 6 | # # 7 | # Please submit issues / PRs to the generator repo instead! # 8 | ############################################################### 9 | name: bespoke-silicon-group:basejump_stl:rtl:0.0.1 10 | description: 'BaseJump STL: A Standard Template Library for SystemVerilog' 11 | filesets: 12 | rtl: 13 | files: 14 | - bsg_cache/bsg_cache.svh: 15 | is_include_file: true 16 | - bsg_cache/bsg_cache_non_blocking.svh: 17 | is_include_file: true 18 | - bsg_clk_gen/bsg_clk_gen.svh: 19 | is_include_file: true 20 | - bsg_dmc/bsg_dmc.svh: 21 | is_include_file: true 22 | - bsg_noc/bsg_noc_links.svh: 23 | is_include_file: true 24 | - bsg_noc/bsg_wormhole_router.svh: 25 | is_include_file: true 26 | - bsg_tag/bsg_tag.svh: 27 | is_include_file: true 28 | - bsg_axi/bsg_axi_pkg.sv 29 | - bsg_cache/bsg_cache_non_blocking_pkg.sv 30 | - bsg_cache/bsg_cache_pkg.sv 31 | - bsg_dmc/bsg_dmc_pkg.sv 32 | - bsg_link/bsg_link_pkg.sv 33 | - bsg_noc/bsg_mesh_router_pkg.sv 34 | - bsg_noc/bsg_noc_pkg.sv 35 | - bsg_noc/bsg_wormhole_router_pkg.sv 36 | - bsg_tag/bsg_tag_pkg.sv 37 | - bsg_async/bsg_async_credit_counter.sv 38 | - bsg_async/bsg_async_fifo.sv 39 | - bsg_async/bsg_async_ptr_gray.sv 40 | - bsg_async/bsg_launch_sync_sync.sv 41 | - bsg_async/bsg_sync_sync.sv 42 | - bsg_cache/bsg_cache.sv 43 | - bsg_cache/bsg_cache_buffer_queue.sv 44 | - bsg_cache/bsg_cache_decode.sv 45 | - bsg_cache/bsg_cache_dma.sv 46 | - bsg_cache/bsg_cache_dma_to_wormhole.sv 47 | - bsg_cache/bsg_cache_miss.sv 48 | - bsg_cache/bsg_cache_non_blocking.sv 49 | - bsg_cache/bsg_cache_non_blocking_data_mem.sv 50 | - bsg_cache/bsg_cache_non_blocking_decode.sv 51 | - bsg_cache/bsg_cache_non_blocking_dma.sv 52 | - bsg_cache/bsg_cache_non_blocking_mhu.sv 53 | - bsg_cache/bsg_cache_non_blocking_miss_fifo.sv 54 | - bsg_cache/bsg_cache_non_blocking_stat_mem.sv 55 | - bsg_cache/bsg_cache_non_blocking_tag_mem.sv 56 | - bsg_cache/bsg_cache_non_blocking_tl_stage.sv 57 | - bsg_cache/bsg_cache_sbuf.sv 58 | - bsg_cache/bsg_cache_tbuf.sv 59 | - bsg_cache/bsg_cache_to_axi.sv 60 | - bsg_cache/bsg_cache_to_axi_ordering.sv 61 | - bsg_cache/bsg_cache_to_axi_rx.sv 62 | - bsg_cache/bsg_cache_to_axi_tx.sv 63 | - bsg_cache/bsg_cache_to_dram_ctrl.sv 64 | - bsg_cache/bsg_cache_to_dram_ctrl_rx.sv 65 | - bsg_cache/bsg_cache_to_dram_ctrl_tx.sv 66 | - bsg_cache/bsg_cache_to_test_dram.sv 67 | - bsg_cache/bsg_cache_to_test_dram_rx.sv 68 | - bsg_cache/bsg_cache_to_test_dram_rx_reorder.sv 69 | - bsg_cache/bsg_cache_to_test_dram_tx.sv 70 | - bsg_cache/bsg_wormhole_to_cache_dma_fanout.sv 71 | - bsg_cache/bsg_wormhole_to_cache_dma_inorder.sv 72 | - bsg_clk_gen/bsg_clk_gen.sv 73 | - bsg_clk_gen/bsg_clk_gen_osc.sv 74 | - bsg_clk_gen/bsg_clk_gen_osc_v3.sv 75 | - bsg_clk_gen/bsg_clk_gen_v3.sv 76 | - bsg_clk_gen/bsg_dly_line.sv 77 | - bsg_clk_gen/bsg_dram_clk_gen.sv 78 | - bsg_clk_gen/bsg_edge_balanced_mux4.sv 79 | - bsg_dataflow/bsg_1_to_n_tagged.sv 80 | - bsg_dataflow/bsg_1_to_n_tagged_fifo.sv 81 | - bsg_dataflow/bsg_1_to_n_tagged_fifo_shared.sv 82 | - bsg_dataflow/bsg_8b10b_decode_comb.sv 83 | - bsg_dataflow/bsg_8b10b_encode_comb.sv 84 | - bsg_dataflow/bsg_8b10b_shift_decoder.sv 85 | - bsg_dataflow/bsg_channel_narrow.sv 86 | - bsg_dataflow/bsg_channel_tunnel.sv 87 | - bsg_dataflow/bsg_channel_tunnel_in.sv 88 | - bsg_dataflow/bsg_channel_tunnel_out.sv 89 | - bsg_dataflow/bsg_channel_tunnel_wormhole.sv 90 | - bsg_dataflow/bsg_compare_and_swap.sv 91 | - bsg_dataflow/bsg_credit_to_token.sv 92 | - bsg_dataflow/bsg_fifo_1r1w_narrowed.sv 93 | - bsg_dataflow/bsg_fifo_1r1w_pseudo_large.sv 94 | - bsg_dataflow/bsg_fifo_1r1w_small.sv 95 | - bsg_dataflow/bsg_fifo_1r1w_small_credit_on_input.sv 96 | - bsg_dataflow/bsg_fifo_1r1w_small_hardened.sv 97 | - bsg_dataflow/bsg_fifo_1r1w_small_unhardened.sv 98 | - bsg_dataflow/bsg_fifo_1rw_large.sv 99 | - bsg_dataflow/bsg_fifo_bypass.sv 100 | - bsg_dataflow/bsg_fifo_reorder.sv 101 | - bsg_dataflow/bsg_fifo_shift_datapath.sv 102 | - bsg_dataflow/bsg_fifo_tracker.sv 103 | - bsg_dataflow/bsg_flatten_2D_array.sv 104 | - bsg_dataflow/bsg_flow_convert.sv 105 | - bsg_dataflow/bsg_flow_counter.sv 106 | - bsg_dataflow/bsg_make_2D_array.sv 107 | - bsg_dataflow/bsg_one_fifo.sv 108 | - bsg_dataflow/bsg_parallel_in_serial_out.sv 109 | - bsg_dataflow/bsg_parallel_in_serial_out_dynamic.sv 110 | - bsg_dataflow/bsg_parallel_in_serial_out_passthrough.sv 111 | - bsg_dataflow/bsg_permute_box.sv 112 | - bsg_dataflow/bsg_ready_to_credit_flow_converter.sv 113 | - bsg_dataflow/bsg_relay_fifo.sv 114 | - bsg_dataflow/bsg_round_robin_2_to_2.sv 115 | - bsg_dataflow/bsg_round_robin_fifo_to_fifo.sv 116 | - bsg_dataflow/bsg_round_robin_n_to_1.sv 117 | - bsg_dataflow/bsg_sbox.sv 118 | - bsg_dataflow/bsg_scatter_gather.sv 119 | - bsg_dataflow/bsg_serial_in_parallel_out.sv 120 | - bsg_dataflow/bsg_serial_in_parallel_out_dynamic.sv 121 | - bsg_dataflow/bsg_serial_in_parallel_out_passthrough.sv 122 | - bsg_dataflow/bsg_shift_reg.sv 123 | - bsg_dataflow/bsg_sort_4.sv 124 | - bsg_dataflow/bsg_sort_stable.sv 125 | - bsg_dataflow/bsg_two_buncher.sv 126 | - bsg_dataflow/bsg_two_fifo.sv 127 | - bsg_dataflow/bsg_fifo_1r1w_large.sv 128 | - bsg_dataflow/bsg_fifo_1r1w_large_banked.sv 129 | - bsg_dataflow/bsg_round_robin_1_to_n.sv 130 | - bsg_dataflow/bsg_serial_in_parallel_out_full.sv 131 | - bsg_dmc/bsg_dmc.sv 132 | - bsg_dmc/bsg_dmc_clk_rst_gen.sv 133 | - bsg_dmc/bsg_dmc_controller.sv 134 | - bsg_dmc/bsg_dmc_dly_line_v3.sv 135 | - bsg_dmc/bsg_dmc_phy.sv 136 | - bsg_dmc/bsg_dmc_sys_cfg_gen.sv 137 | - bsg_dmc/bsg_dmc_xilinx_ui_trace_replay.sv 138 | - bsg_link/bsg_link_ddr_downstream.sv 139 | - bsg_link/bsg_link_ddr_upstream.sv 140 | - bsg_link/bsg_link_iddr_phy.sv 141 | - bsg_link/bsg_link_isdr_phy.sv 142 | - bsg_link/bsg_link_oddr_phy.sv 143 | - bsg_link/bsg_link_osdr_phy.sv 144 | - bsg_link/bsg_link_osdr_phy_phase_align.sv 145 | - bsg_link/bsg_link_sdr.sv 146 | - bsg_link/bsg_link_sdr_downstream.sv 147 | - bsg_link/bsg_link_sdr_upstream.sv 148 | - bsg_link/bsg_link_source_sync_downstream.sv 149 | - bsg_link/bsg_link_source_sync_upstream.sv 150 | - bsg_link/bsg_link_source_sync_upstream_sync.sv 151 | - bsg_mem/bsg_cam_1r1w.sv 152 | - bsg_mem/bsg_cam_1r1w_replacement.sv 153 | - bsg_mem/bsg_cam_1r1w_sync.sv 154 | - bsg_mem/bsg_cam_1r1w_sync_unmanaged.sv 155 | - bsg_mem/bsg_cam_1r1w_tag_array.sv 156 | - bsg_mem/bsg_cam_1r1w_unmanaged.sv 157 | - bsg_mem/bsg_mem_1r1w.sv 158 | - bsg_mem/bsg_mem_1r1w_one_hot.sv 159 | - bsg_mem/bsg_mem_1r1w_sync_banked.sv 160 | - bsg_mem/bsg_mem_1r1w_sync_from_1rw_sync.sv 161 | - bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv 162 | - bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_synth.sv 163 | - bsg_mem/bsg_mem_1r1w_sync_mask_write_byte.sv 164 | - bsg_mem/bsg_mem_1r1w_sync_mask_write_byte_synth.sv 165 | - bsg_mem/bsg_mem_1r1w_sync_mask_write_var.sv 166 | - bsg_mem/bsg_mem_1r1w_sync_synth.sv 167 | - bsg_mem/bsg_mem_1r1w_synth.sv 168 | - bsg_mem/bsg_mem_1rw_sync_banked.sv 169 | - bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv 170 | - bsg_mem/bsg_mem_1rw_sync_mask_write_bit_banked.sv 171 | - bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv 172 | - bsg_mem/bsg_mem_1rw_sync_mask_write_bit_segmented.sv 173 | - bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.sv 174 | - bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv 175 | - bsg_mem/bsg_mem_1rw_sync_mask_write_byte_banked.sv 176 | - bsg_mem/bsg_mem_1rw_sync_mask_write_byte_segmented.sv 177 | - bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.sv 178 | - bsg_mem/bsg_mem_1rw_sync_mask_write_var.sv 179 | - bsg_mem/bsg_mem_1rw_sync_segmented.sv 180 | - bsg_mem/bsg_mem_1rw_sync_synth.sv 181 | - bsg_mem/bsg_mem_2r1w.sv 182 | - bsg_mem/bsg_mem_2r1w_sync.sv 183 | - bsg_mem/bsg_mem_2r1w_sync_synth.sv 184 | - bsg_mem/bsg_mem_2r1w_synth.sv 185 | - bsg_mem/bsg_mem_2rw_sync.sv 186 | - bsg_mem/bsg_mem_2rw_sync_mask_write_bit.sv 187 | - bsg_mem/bsg_mem_2rw_sync_mask_write_bit_synth.sv 188 | - bsg_mem/bsg_mem_2rw_sync_mask_write_byte.sv 189 | - bsg_mem/bsg_mem_2rw_sync_mask_write_byte_synth.sv 190 | - bsg_mem/bsg_mem_2rw_sync_synth.sv 191 | - bsg_mem/bsg_mem_3r1w.sv 192 | - bsg_mem/bsg_mem_3r1w_sync.sv 193 | - bsg_mem/bsg_mem_3r1w_sync_synth.sv 194 | - bsg_mem/bsg_mem_3r1w_synth.sv 195 | - bsg_mem/bsg_mem_banked_crossbar.sv 196 | - bsg_mem/bsg_mem_multiport.sv 197 | - bsg_mem/bsg_mem_multiport_latch.sv 198 | - bsg_mem/bsg_mem_multiport_latch_write_banked_bypassing.sv 199 | - bsg_mem/bsg_mem_multiport_latch_write_banked_bypassing_sync.sv 200 | - bsg_mem/bsg_mem_1r1w_sync.sv 201 | - bsg_mem/bsg_mem_1rw_sync.sv 202 | - bsg_noc/bsg_barrier.sv 203 | - bsg_noc/bsg_mesh_router.sv 204 | - bsg_noc/bsg_mesh_router_buffered.sv 205 | - bsg_noc/bsg_mesh_router_decoder_dor.sv 206 | - bsg_noc/bsg_mesh_stitch.sv 207 | - bsg_noc/bsg_mesh_to_ring_stitch.sv 208 | - bsg_noc/bsg_noc_repeater_node.sv 209 | - bsg_noc/bsg_ready_and_link_async_to_wormhole.sv 210 | - bsg_noc/bsg_wormhole_concentrator_out.sv 211 | - bsg_noc/bsg_wormhole_router.sv 212 | - bsg_noc/bsg_wormhole_router_adapter_in.sv 213 | - bsg_noc/bsg_wormhole_router_adapter_out.sv 214 | - bsg_noc/bsg_wormhole_router_decoder_dor.sv 215 | - bsg_noc/bsg_wormhole_router_input_control.sv 216 | - bsg_noc/bsg_wormhole_router_output_control.sv 217 | - bsg_noc/bsg_router_crossbar_o_by_i.sv 218 | - bsg_noc/bsg_wormhole_concentrator.sv 219 | - bsg_noc/bsg_wormhole_concentrator_in.sv 220 | - bsg_noc/bsg_wormhole_router_packet_parser.sv 221 | - bsg_tag/bsg_tag_bitbang.sv 222 | - bsg_tag/bsg_tag_client.sv 223 | - bsg_tag/bsg_tag_client_unsync.sv 224 | - bsg_tag/bsg_tag_master.sv 225 | - bsg_tag/bsg_tag_master_decentralized.sv 226 | - bsg_tag/bsg_tag_trace_replay.sv 227 | file_type: systemVerilogSource 228 | nonsynth: {} 229 | provider: 230 | name: github 231 | user: bespoke-silicon-group 232 | repo: basejump_stl 233 | version: v0.0.1 234 | -------------------------------------------------------------------------------- /bespoke-silicon-group/bsg-external-hardfloat.core: -------------------------------------------------------------------------------- 1 | CAPI=2: '' 2 | name: bsg-external:hardfloat:0.0.1 3 | description: 'Berkeley Verilog HardFloat (mirror by University of Washington)' 4 | filesets: 5 | rtl: 6 | files: 7 | - source/HardFloat_consts.vi: 8 | is_include_file: true 9 | - source/HardFloat_localFuncs.vi: 10 | is_include_file: true 11 | - source/RISCV/HardFloat_specialize.vi: 12 | is_include_file: true 13 | - source/RISCV/HardFloat_specialize.v 14 | - source/bsg_hardfloat_pkg.sv 15 | - source/HardFloat_primitives.v 16 | - source/HardFloat_rawFN.v 17 | - source/addRecFN.v 18 | - source/compareRecFN.v 19 | - source/divSqrtFN.v 20 | - source/divSqrtRecFN.v 21 | - source/divSqrtRecFN_medium.v 22 | - source/divSqrtRecFN_small.v 23 | - source/fNToRecFN.v 24 | - source/iNToRecFN.v 25 | - source/isSigNaNRecFN.v 26 | - source/mulAddRecFN.v 27 | - source/mulRecFN.v 28 | - source/recFNToFN.v 29 | - source/recFNToIN.v 30 | - source/recFNToRecFN.v 31 | file_type: systemVerilogSource 32 | provider: 33 | name: github 34 | user: bsg-external 35 | repo: HardFloat 36 | version: v0.0.1 37 | -------------------------------------------------------------------------------- /cdc_utils/cdc_utils-0.1-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: ::cdc_utils:0.1-r1 3 | description: Verilog CDC implementations 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/verilog/sync2_pgen.v 9 | - rtl/verilog/cc561.v 10 | file_type: verilogSource 11 | sdc: 12 | files: [data/cdc_utils.sdc : {file_type : SDC}] 13 | 14 | targets: 15 | default: 16 | filesets: [rtl, "tool_quartus? (sdc)"] 17 | 18 | provider: 19 | name: github 20 | user: fusesoc 21 | repo: cdc_utils 22 | version: v0.1 23 | -------------------------------------------------------------------------------- /chipsalliance.org/swerv_el2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : chipsalliance.org:cores:SweRV_EL2:1.2 4 | description : SweRV EL2 RISC-V Core 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - design/include/el2_def.sv 10 | - design/lib/el2_lib.sv 11 | - design/lib/beh_lib.sv 12 | - design/el2_mem.sv 13 | - design/el2_pic_ctrl.sv 14 | - design/el2_dma_ctrl.sv 15 | - design/ifu/el2_ifu_aln_ctl.sv 16 | - design/ifu/el2_ifu_compress_ctl.sv 17 | - design/ifu/el2_ifu_ifc_ctl.sv 18 | - design/ifu/el2_ifu_bp_ctl.sv 19 | - design/ifu/el2_ifu_ic_mem.sv 20 | - design/ifu/el2_ifu_mem_ctl.sv 21 | - design/ifu/el2_ifu_iccm_mem.sv 22 | - design/ifu/el2_ifu.sv 23 | - design/dec/el2_dec_decode_ctl.sv 24 | - design/dec/el2_dec_gpr_ctl.sv 25 | - design/dec/el2_dec_ib_ctl.sv 26 | - design/dec/el2_dec_tlu_ctl.sv 27 | - design/dec/el2_dec_trigger.sv 28 | - design/dec/el2_dec.sv 29 | - design/exu/el2_exu_alu_ctl.sv 30 | - design/exu/el2_exu_mul_ctl.sv 31 | - design/exu/el2_exu_div_ctl.sv 32 | - design/exu/el2_exu.sv 33 | - design/lsu/el2_lsu.sv 34 | - design/lsu/el2_lsu_bus_buffer.sv 35 | - design/lsu/el2_lsu_clkdomain.sv 36 | - design/lsu/el2_lsu_addrcheck.sv 37 | - design/lsu/el2_lsu_lsc_ctl.sv 38 | - design/lsu/el2_lsu_stbuf.sv 39 | - design/lsu/el2_lsu_bus_intf.sv 40 | - design/lsu/el2_lsu_ecc.sv 41 | - design/lsu/el2_lsu_dccm_mem.sv 42 | - design/lsu/el2_lsu_dccm_ctl.sv 43 | - design/lsu/el2_lsu_trigger.sv 44 | - design/dbg/el2_dbg.sv 45 | - design/dmi/dmi_wrapper.v 46 | - design/dmi/dmi_jtag_to_core_sync.v 47 | - design/dmi/rvjtag_tap.v 48 | - design/lib/mem_lib.sv 49 | - design/el2_swerv.sv 50 | - design/el2_swerv_wrapper.sv 51 | file_type : systemVerilogSource 52 | 53 | vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]} 54 | 55 | targets: 56 | default: 57 | filesets : 58 | - rtl 59 | - "tool_vivado ? (vivado_tcl)" 60 | lint: 61 | default_tool: verilator 62 | filesets : [rtl] 63 | generate : [swerv_default_config] 64 | tools: 65 | verilator : 66 | mode : lint-only 67 | toplevel : el2_swerv_wrapper 68 | 69 | synth: 70 | default_tool : vivado 71 | filesets : [rtl, vivado_tcl] 72 | generate : [swerv_default_config] 73 | parameters : [RV_FPGA_OPTIMIZE] 74 | tools: 75 | vivado: 76 | part : xc7a100tcsg324-1 77 | pnr : none 78 | toplevel : el2_swerv_wrapper 79 | 80 | generate: 81 | swerv_default_config: 82 | generator: swerv_el2_config 83 | position : first 84 | parameters: 85 | args : [-unset=assert_on] 86 | 87 | generators: 88 | swerv_el2_config: 89 | interpreter: python3 90 | command: configs/swerv_config_gen.py 91 | description : Create a SweRV EL2 configuration. Note! Only supports the default config 92 | 93 | parameters: 94 | RV_FPGA_OPTIMIZE: 95 | datatype : bool 96 | default : true 97 | description : Minimize clock gating to map better to FPGAs 98 | paramtype : vlogdefine 99 | 100 | provider: 101 | name : github 102 | user : chipsalliance 103 | repo : Cores-SweRV-EL2 104 | version : 4c5674ca354056b27e88cb7821ab0aa36f4102e2 105 | -------------------------------------------------------------------------------- /ethmac/ethmac-0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::ethmac:0-r1 3 | 4 | filesets: 5 | rtl: 6 | files: 7 | - rtl/verilog/ethmac.v 8 | 9 | - rtl/verilog/eth_clockgen.v 10 | - rtl/verilog/eth_cop.v 11 | - rtl/verilog/eth_crc.v 12 | - rtl/verilog/eth_fifo.v 13 | - rtl/verilog/eth_maccontrol.v 14 | - rtl/verilog/eth_macstatus.v 15 | - rtl/verilog/eth_miim.v 16 | - rtl/verilog/eth_outputcontrol.v 17 | - rtl/verilog/eth_random.v 18 | - rtl/verilog/eth_receivecontrol.v 19 | - rtl/verilog/eth_registers.v 20 | - rtl/verilog/eth_rxaddrcheck.v 21 | - rtl/verilog/eth_rxcounters.v 22 | - rtl/verilog/eth_register.v 23 | - rtl/verilog/eth_rxethmac.v 24 | - rtl/verilog/eth_rxstatem.v 25 | - rtl/verilog/eth_spram_256x32.v 26 | - rtl/verilog/eth_shiftreg.v 27 | - rtl/verilog/eth_transmitcontrol.v 28 | - rtl/verilog/eth_txcounters.v 29 | - rtl/verilog/eth_txethmac.v 30 | - rtl/verilog/eth_txstatem.v 31 | - rtl/verilog/eth_wishbone.v 32 | 33 | file_type : verilogSource 34 | 35 | includes: 36 | files: 37 | - rtl/verilog/ethmac_defines.v : {is_include_file : true} 38 | - rtl/verilog/timescale.v : {is_include_file : true} 39 | file_type : VerilogSource 40 | 41 | targets: 42 | default: 43 | filesets : [includes, rtl] 44 | 45 | lint: 46 | default_tool : verilator 47 | filesets : [includes, rtl] 48 | tools: 49 | verilator : 50 | mode : lint-only 51 | toplevel : ethmac 52 | 53 | synth: 54 | default_tool : vivado 55 | filesets : [includes, rtl] 56 | tools: 57 | vivado: 58 | part : xc7a100tcsg324-1 59 | toplevel : ethmac 60 | 61 | provider: 62 | name : github 63 | user : freecores 64 | repo : ethmac 65 | version : dd26899086edf3b797d2775ef9502d204a9a8149 66 | -------------------------------------------------------------------------------- /fifo/fifo-1.3-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::fifo:1.3-r1 4 | description : Generic FIFO 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/simple_dpram_sclk.v 10 | - rtl/verilog/fifo.v 11 | - rtl/verilog/fifo_fwft_adapter.v 12 | - rtl/verilog/fifo_fwft.v 13 | - rtl/verilog/dual_clock_fifo.v 14 | file_type : verilogSource 15 | 16 | bfm: 17 | files: 18 | - bench/fifo_reader.v 19 | - bench/fifo_fwft_reader.v 20 | - bench/fifo_writer.v 21 | file_type : verilogSource 22 | 23 | tb: 24 | files: 25 | - bench/fifo_tester.v 26 | - bench/dual_clock_fifo_tb.v 27 | - bench/fifo_fwft_tb.v 28 | - bench/fifo_tb.v 29 | file_type : verilogSource 30 | depend : [">=::vlog_tb_utils:1.1"] 31 | 32 | constraints: 33 | files : 34 | - "tool_quartus? (data/fifo.sdc)" : {file_type : SDC} 35 | 36 | parameters: 37 | read_rate: 38 | datatype : str 39 | description : FIFO read rate 40 | paramtype : plusarg 41 | 42 | write_rate: 43 | datatype : str 44 | description : FIFO write rate 45 | paramtype : plusarg 46 | 47 | data_width: 48 | datatype : int 49 | description : FIFO data width 50 | paramtype : vlogparam 51 | 52 | depth_width: 53 | datatype : int 54 | description : 2**(FIFO depth) 55 | paramtype : vlogparam 56 | 57 | targets: 58 | default: 59 | filesets : 60 | - rtl 61 | - constraints 62 | - "tool_icarus? (bfm)" 63 | - "tool_isim? (bfm)" 64 | - "tool_modelsim? (bfm)" 65 | fifo_fwft_tb: &sim 66 | default_tool : icarus 67 | description : Testbench for First Word Fall Through FIFO 68 | filesets : [rtl, bfm, tb] 69 | parameters : [read_rate, write_rate, data_width, depth_width] 70 | toplevel : fifo_fwft_tb 71 | 72 | dual_clock_fifo_tb: 73 | << : *sim 74 | description : Testbench for dual clock FIFO 75 | toplevel : dual_clock_fifo_tb 76 | 77 | fifo_tb: 78 | << : *sim 79 | description : Testbench single clock FIFO 80 | toplevel : fifo_tb 81 | 82 | provider: 83 | name : github 84 | user : olofk 85 | repo : fifo 86 | version : v1.3 87 | -------------------------------------------------------------------------------- /fusesoc_utils/generators-0.1.3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : fusesoc:utils:generators:0.1.3 4 | 5 | generators: 6 | custom: 7 | interpreter: python 8 | command: custom.py 9 | description : Run custom command 10 | usage: | 11 | The custom generator allows the user to specify a custom command to run. 12 | As the custom generator doesn't know by itself what is produced by the 13 | command, the user is requrested to specify any created files and associated 14 | plusargs, defines etc in the output configuration parameter. 15 | 16 | Parameters: 17 | command (str): The command to run. Working directory for the command is 18 | determined by the copy_core and run_from_core parameters 19 | copy_core (bool): Copy the working directory to a temporary location and run 20 | the command from there 21 | run_from_core (bool): Runs command from the directory specified as files_root 22 | in the configuration file 23 | output (dict): A dictionary describing the expected output from the command. 24 | These are written to the generated .core file 25 | files (list): A list of files, specified in the same format as CAPI2 fileset 26 | files, which are expected to be generated by the command 27 | parameters (dict): A map of parameters, specified in the same format as 28 | CAPI2 parameters, which are used by the generated files 29 | 30 | gitversion: 31 | interpreter: python 32 | command: gitversion.py 33 | description: Parse version tags from git repo 34 | usage: | 35 | The gitversion generator runs git describe to look at the tags in the current 36 | directory (or in files_root if that is defined in the input configuration file) 37 | and creates verilog defines that can be used in a core to provide accurate 38 | version information. 39 | 40 | Tags are assumed to be on the format vx.y.z which produces the following defines 41 | VERSION_MAJOR = x 42 | VERSION_MINOR = y 43 | VERSION_PATCH = z 44 | 45 | In addition to the parsed tags, the gitversion generator will also set 46 | VERSION_REV to the number of commits since the last tag and VERSION_DIRTY if 47 | it detects that there are local modifications in the repository 48 | 49 | icepll: 50 | interpreter: python 51 | command: icepll.py 52 | description: Generate a parameterized verilog wrapper for an iCE40 PLL 53 | usage: | 54 | The icepll generator is a simple wrapper around the icepll command 55 | 56 | Parameters: 57 | freq_in (int): PLL Input Frequency (default: 12 MHz) 58 | freq_out (int) PLL Output Frequency (default: 60 MHz) 59 | filename (str): Output filename (default: pll.v) 60 | module (bool): If true, generate a verilog module which instantiates the PLL. 61 | Otherwise, the user is responsible for instantiating the PLL 62 | and the icepll generator will create a list of parameters that 63 | can be included in the parameter list of the user-instantiated 64 | component (default: false) 65 | 66 | provider: 67 | name : github 68 | user : fusesoc 69 | repo : fusesoc-generators 70 | version : v0.1.3 71 | 72 | -------------------------------------------------------------------------------- /fusesoc_utils/generators-0.1.4.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : fusesoc:utils:generators:0.1.4 4 | 5 | generators: 6 | custom: 7 | interpreter: python 8 | command: custom.py 9 | description : Run custom command 10 | usage: | 11 | The custom generator allows the user to specify a custom command to run. 12 | As the custom generator doesn't know by itself what is produced by the 13 | command, the user is requrested to specify any created files and associated 14 | plusargs, defines etc in the output configuration parameter. 15 | 16 | Parameters: 17 | command (str): The command to run. Working directory for the command is 18 | determined by the copy_core and run_from_core parameters 19 | copy_core (bool): Copy the working directory to a temporary location and run 20 | the command from there 21 | run_from_core (bool): Runs command from the directory specified as files_root 22 | in the configuration file 23 | output (dict): A dictionary describing the expected output from the command. 24 | These are written to the generated .core file 25 | files (list): A list of files, specified in the same format as CAPI2 fileset 26 | files, which are expected to be generated by the command 27 | parameters (dict): A map of parameters, specified in the same format as 28 | CAPI2 parameters, which are used by the generated files 29 | 30 | gitversion: 31 | interpreter: python 32 | command: gitversion.py 33 | description: Parse version tags from git repo 34 | usage: | 35 | The gitversion generator runs git describe to look at the tags in the current 36 | directory (or in files_root if that is defined in the input configuration file) 37 | and creates verilog defines that can be used in a core to provide accurate 38 | version information. 39 | 40 | Tags are assumed to be on the format vx.y.z which produces the following defines 41 | VERSION_MAJOR = x 42 | VERSION_MINOR = y 43 | VERSION_PATCH = z 44 | 45 | In addition to the parsed tags, the gitversion generator will also set 46 | VERSION_REV to the number of commits since the last tag and VERSION_DIRTY if 47 | it detects that there are local modifications in the repository 48 | 49 | icepll: 50 | interpreter: python 51 | command: icepll.py 52 | description: Generate a parameterized verilog wrapper for an iCE40 PLL 53 | usage: | 54 | The icepll generator is a simple wrapper around the icepll command 55 | 56 | Parameters: 57 | freq_in (int): PLL Input Frequency (default: 12 MHz) 58 | freq_out (int) PLL Output Frequency (default: 60 MHz) 59 | filename (str): Output filename (default: pll.v) 60 | module (bool): If true, generate a verilog module which instantiates the PLL. 61 | Otherwise, the user is responsible for instantiating the PLL 62 | and the icepll generator will create a list of parameters that 63 | can be included in the parameter list of the user-instantiated 64 | component (default: false) 65 | 66 | provider: 67 | name : github 68 | user : fusesoc 69 | repo : fusesoc-generators 70 | version : v0.1.4 71 | 72 | -------------------------------------------------------------------------------- /fusesoc_utils/generators-0.1.5.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : fusesoc:utils:generators:0.1.5 4 | 5 | generators: 6 | custom: 7 | interpreter: python3 8 | command: custom.py 9 | description : Run custom command 10 | usage: | 11 | The custom generator allows the user to specify a custom command to run. 12 | As the custom generator doesn't know by itself what is produced by the 13 | command, the user is requrested to specify any created files and associated 14 | plusargs, defines etc in the output configuration parameter. 15 | 16 | Parameters: 17 | command (str): The command to run. Working directory for the command is 18 | determined by the copy_core and run_from_core parameters 19 | copy_core (bool): Copy the working directory to a temporary location and run 20 | the command from there 21 | run_from_core (bool): Runs command from the directory specified as files_root 22 | in the configuration file 23 | output (dict): A dictionary describing the expected output from the command. 24 | These are written to the generated .core file 25 | files (list): A list of files, specified in the same format as CAPI2 fileset 26 | files, which are expected to be generated by the command 27 | parameters (dict): A map of parameters, specified in the same format as 28 | CAPI2 parameters, which are used by the generated files 29 | 30 | gitversion: 31 | interpreter: python3 32 | command: gitversion.py 33 | description: Parse version tags from git repo 34 | usage: | 35 | The gitversion generator runs git describe to look at the tags in the current 36 | directory (or in files_root if that is defined in the input configuration file) 37 | and creates verilog defines that can be used in a core to provide accurate 38 | version information. 39 | 40 | Tags are assumed to be on the format vx.y.z which produces the following defines 41 | VERSION_MAJOR = x 42 | VERSION_MINOR = y 43 | VERSION_PATCH = z 44 | 45 | In addition to the parsed tags, the gitversion generator will also set 46 | VERSION_REV to the number of commits since the last tag and VERSION_DIRTY if 47 | it detects that there are local modifications in the repository 48 | 49 | icepll: 50 | interpreter: python3 51 | command: icepll.py 52 | description: Generate a parameterized verilog wrapper for an iCE40 PLL 53 | usage: | 54 | The icepll generator is a simple wrapper around the icepll command 55 | 56 | Parameters: 57 | freq_in (int): PLL Input Frequency (default: 12 MHz) 58 | freq_out (int) PLL Output Frequency (default: 60 MHz) 59 | filename (str): Output filename (default: pll.v) 60 | module (bool): If true, generate a verilog module which instantiates the PLL. 61 | Otherwise, the user is responsible for instantiating the PLL 62 | and the icepll generator will create a list of parameters that 63 | can be included in the parameter list of the user-instantiated 64 | component (default: false) 65 | 66 | template: 67 | interpreter: python3 68 | command: template/template_generator.py 69 | description: Generate a file from a Jinja template 70 | usage: | 71 | The template generator uses the provided YAML description to populate 72 | a Jinja template. 73 | 74 | The generator requires the following parameters: 75 | 76 | output_file: 77 | 78 | name: The file name for the rendered template 79 | type: The file type of the rendered template (vhdlSource, verilogSource, etc.) 80 | 81 | template: The file name of the template 82 | 83 | template_path (optional): The directory containing the template. 84 | 85 | If this parameter isn't specified the default is to use the 86 | calling core's directory followed by the templates 87 | directory for this generator. 88 | 89 | Examples of template usage are in the examples directory. 90 | 91 | provider: 92 | name : github 93 | user : fusesoc 94 | repo : fusesoc-generators 95 | version : v0.1.5 96 | -------------------------------------------------------------------------------- /fusesoc_utils/generators-0.1.6.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: fusesoc:utils:generators:0.1.6 4 | 5 | generators: 6 | custom: 7 | interpreter: python3 8 | command: custom.py 9 | description: Run custom command 10 | usage: | 11 | The custom generator allows the user to specify a custom command to run. 12 | As the custom generator doesn't know by itself what is produced by the 13 | command, the user is requrested to specify any created files and associated 14 | plusargs, defines etc in the output configuration parameter. 15 | 16 | Parameters: 17 | command (str): The command to run. Working directory for the command is 18 | determined by the copy_core and run_from_core parameters 19 | copy_core (bool): Copy the working directory to a temporary location and run 20 | the command from there 21 | run_from_core (bool): Runs command from the directory specified as files_root 22 | in the configuration file 23 | output (dict): A dictionary describing the expected output from the command. 24 | These are written to the generated .core file 25 | files (list): A list of files, specified in the same format as CAPI2 fileset 26 | files, which are expected to be generated by the command 27 | parameters (dict): A map of parameters, specified in the same format as 28 | CAPI2 parameters, which are used by the generated files 29 | 30 | gitversion: 31 | interpreter: python3 32 | command: gitversion.py 33 | description: Parse version tags from git repo 34 | usage: | 35 | The gitversion generator runs git describe to look at the tags in the current 36 | directory (or in files_root if that is defined in the input configuration file) 37 | and creates verilog defines that can be used in a core to provide accurate 38 | version information. 39 | 40 | Tags are assumed to be on the format vx.y.z which produces the following defines 41 | VERSION_MAJOR = x 42 | VERSION_MINOR = y 43 | VERSION_PATCH = z 44 | 45 | In addition to the parsed tags, the gitversion generator will also set 46 | VERSION_REV to the number of commits since the last tag and VERSION_DIRTY if 47 | it detects that there are local modifications in the repository 48 | 49 | icepll: 50 | interpreter: python3 51 | command: icepll.py 52 | description: Generate a parameterized verilog wrapper for an iCE40 PLL 53 | usage: | 54 | The icepll generator is a simple wrapper around the icepll command 55 | 56 | Parameters: 57 | freq_in (int): PLL Input Frequency (default: 12 MHz) 58 | freq_out (int) PLL Output Frequency (default: 60 MHz) 59 | filename (str): Output filename (default: pll.v) 60 | module (bool): If true, generate a verilog module which instantiates the PLL. 61 | Otherwise, the user is responsible for instantiating the PLL 62 | and the icepll generator will create a list of parameters that 63 | can be included in the parameter list of the user-instantiated 64 | component (default: false) 65 | 66 | template: 67 | interpreter: python3 68 | command: template/template_generator.py 69 | description: Generate a file from a Jinja template 70 | usage: | 71 | The template generator uses the provided YAML description to populate 72 | a Jinja template. 73 | 74 | The generator requires the following parameters: 75 | 76 | output_file: 77 | 78 | name: The file name for the rendered template 79 | type: The file type of the rendered template (vhdlSource, verilogSource, etc.) 80 | 81 | template: The file name of the template 82 | 83 | template_path (optional): The directory containing the template. 84 | 85 | If this parameter isn't specified the default is to use the 86 | calling core's directory followed by the templates 87 | directory for this generator. 88 | 89 | Examples of template usage are in the examples directory. 90 | 91 | chisel: 92 | interpreter: python3 93 | command: chisel.py 94 | description: Build Chisel HDL 95 | usage: | 96 | This generator builds chisel HDL generating Verilog output. 97 | The generator depends on the Mill or SBT build configs and require the 98 | host to have all pre-reqs like a Java Virtual Machine to build Chisel/Scala 99 | applications. 100 | The user is required to specify any created files and associated 101 | arguments and parameters. 102 | 103 | Parameters: 104 | buildtool (str): The Scala build tool to be used (Mill or SBT). 105 | Requires respective "build.sc" or "build.sbt". 106 | env (str): Environment variables to be passed to the Chisel build tool. 107 | outputdir (str): Output directory to be passed to build tool for generated 108 | verilog files from Chisel sources. Must match path used in 109 | "output: files:" section. 110 | extraargs (str): Extra arguments to be passed to the build tool. 111 | chiselproject (str): Chisel project name to be passed to the build tool. 112 | copy_core (bool): Copy the working directory to a temporary location and run 113 | the command from there 114 | output (dict): A dictionary describing the expected output from the command. 115 | These are written to the generated .core file 116 | files (list): A list of files, specified in the same format as CAPI2 fileset 117 | files, which are expected to be generated by the command 118 | parameters (dict): A map of parameters, specified in the same format as 119 | CAPI2 parameters, which are used by the generated files 120 | 121 | provider: 122 | name : github 123 | user : fusesoc 124 | repo : fusesoc-generators 125 | version : v0.1.6 126 | -------------------------------------------------------------------------------- /fusesoc_utils/generators-0.1.7.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: fusesoc:utils:generators:0.1.7 4 | 5 | generators: 6 | custom: 7 | interpreter: python3 8 | command: custom.py 9 | description: Run custom command 10 | usage: | 11 | The custom generator allows the user to specify a custom command to run. 12 | As the custom generator doesn't know by itself what is produced by the 13 | command, the user is requrested to specify any created files and associated 14 | plusargs, defines etc in the output configuration parameter. 15 | 16 | Parameters: 17 | command (str): The command to run. Working directory for the command is 18 | determined by the copy_core and run_from_core parameters 19 | copy_core (bool): Copy the working directory to a temporary location and run 20 | the command from there 21 | run_from_core (bool): Runs command from the directory specified as files_root 22 | in the configuration file 23 | output (dict): A dictionary describing the expected output from the command. 24 | These are written to the generated .core file 25 | files (list): A list of files, specified in the same format as CAPI2 fileset 26 | files, which are expected to be generated by the command 27 | parameters (dict): A map of parameters, specified in the same format as 28 | CAPI2 parameters, which are used by the generated files 29 | 30 | gitversion: 31 | interpreter: python3 32 | command: gitversion.py 33 | description: Parse version tags from git repo 34 | usage: | 35 | The gitversion generator runs git describe to look at the tags in the current 36 | directory (or in files_root if that is defined in the input configuration file) 37 | and creates verilog defines that can be used in a core to provide accurate 38 | version information. 39 | 40 | Tags are assumed to be on the format vx.y.z which produces the following defines 41 | VERSION_MAJOR = x 42 | VERSION_MINOR = y 43 | VERSION_PATCH = z 44 | 45 | In addition to the parsed tags, the gitversion generator will also set 46 | VERSION_REV to the number of commits since the last tag and VERSION_DIRTY if 47 | it detects that there are local modifications in the repository 48 | 49 | icepll: 50 | interpreter: python3 51 | command: icepll.py 52 | description: Generate a parameterized verilog wrapper for an iCE40 PLL 53 | usage: | 54 | The icepll generator is a simple wrapper around the icepll command 55 | 56 | Parameters: 57 | freq_in (int): PLL Input Frequency (default: 12 MHz) 58 | freq_out (int) PLL Output Frequency (default: 60 MHz) 59 | filename (str): Output filename (default: pll.v) 60 | module (bool): If true, generate a verilog module which instantiates the PLL. 61 | Otherwise, the user is responsible for instantiating the PLL 62 | and the icepll generator will create a list of parameters that 63 | can be included in the parameter list of the user-instantiated 64 | component (default: false) 65 | 66 | template: 67 | interpreter: python3 68 | command: template/template_generator.py 69 | description: Generate a file from a Jinja template 70 | usage: | 71 | The template generator uses the provided YAML description to populate 72 | a Jinja template. 73 | 74 | The generator requires the following parameters: 75 | 76 | output_file: 77 | 78 | name: The file name for the rendered template 79 | type: The file type of the rendered template (vhdlSource, verilogSource, etc.) 80 | 81 | template: The file name of the template 82 | 83 | template_path (optional): The directory containing the template. 84 | 85 | If this parameter isn't specified the default is to use the 86 | calling core's directory followed by the templates 87 | directory for this generator. 88 | 89 | Examples of template usage are in the examples directory. 90 | 91 | chisel: 92 | interpreter: python3 93 | command: chisel.py 94 | description: Build Chisel HDL 95 | usage: | 96 | This generator builds chisel HDL generating Verilog output. 97 | The generator depends on the Mill or SBT build configs and require the 98 | host to have all pre-reqs like a Java Virtual Machine to build Chisel/Scala 99 | applications. 100 | The user is required to specify any created files and associated 101 | arguments and parameters. 102 | 103 | Parameters: 104 | buildtool (str): The Scala build tool to be used (Mill or SBT). 105 | Requires respective "build.sc" or "build.sbt". 106 | env (str): Environment variables to be passed to the Chisel build tool. 107 | outputdir (str): Output directory to be passed to build tool for generated 108 | verilog files from Chisel sources. Must match path used in 109 | "output: files:" section. 110 | extraargs (str): Extra arguments to be passed to the build tool. 111 | chiselproject (str): Chisel project name to be passed to the build tool. 112 | copy_core (bool): Copy the working directory to a temporary location and run 113 | the command from there 114 | output (dict): A dictionary describing the expected output from the command. 115 | These are written to the generated .core file 116 | files (list): A list of files, specified in the same format as CAPI2 fileset 117 | files, which are expected to be generated by the command 118 | parameters (dict): A map of parameters, specified in the same format as 119 | CAPI2 parameters, which are used by the generated files 120 | 121 | provider: 122 | name : github 123 | user : fusesoc 124 | repo : fusesoc-generators 125 | version : v0.1.7 126 | -------------------------------------------------------------------------------- /i2c/files/0001-add_vlog_tb_utils.patch: -------------------------------------------------------------------------------- 1 | diff --git a/bench/verilog/tst_bench_top.v b/bench/verilog/tst_bench_top.v 2 | index 36454ff..5604d5f 100644 3 | --- a/bench/verilog/tst_bench_top.v 4 | +++ b/bench/verilog/tst_bench_top.v 5 | @@ -67,6 +67,7 @@ 6 | // 7 | 8 | module tst_bench_top(); 9 | + vlog_tb_utils vtu(); 10 | 11 | // 12 | // wires && regs 13 | -------------------------------------------------------------------------------- /i2c/i2c-1.14-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::i2c:1.14-r1 3 | filesets: 4 | rtl_files: 5 | files: 6 | - rtl/verilog/i2c_master_bit_ctrl.v 7 | - rtl/verilog/i2c_master_byte_ctrl.v 8 | - rtl/verilog/i2c_master_defines.v: {is_include_file : true} 9 | - rtl/verilog/i2c_master_top.v 10 | file_type : verilogSource 11 | 12 | tb_files: 13 | depend: 14 | - ">=vlog_tb_utils-1.0" 15 | - wiredelay 16 | files: 17 | - bench/verilog/wb_master_model.v 18 | - bench/verilog/tst_bench_top.v 19 | - bench/verilog/i2c_slave_model.v 20 | file_type : verilogSource 21 | 22 | targets: 23 | default: 24 | filesets : [rtl_files] 25 | sim: 26 | default_tool : icarus 27 | filesets : [rtl_files, tb_files] 28 | toplevel : [tst_bench_top] 29 | 30 | provider: 31 | name : github 32 | user : olofk 33 | repo : i2c 34 | version : v1.14 35 | patches : [files/0001-add_vlog_tb_utils.patch] 36 | -------------------------------------------------------------------------------- /i2c/i2c-1.15.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::i2c:1.15 4 | description : WISHBONE revB.2 compliant I2C controller 5 | 6 | filesets: 7 | rtl_files: 8 | files: 9 | - rtl/verilog/i2c_master_bit_ctrl.v 10 | - rtl/verilog/i2c_master_byte_ctrl.v 11 | - rtl/verilog/i2c_master_defines.v: {is_include_file : true} 12 | - rtl/verilog/i2c_master_top.v 13 | - "tool_verilator? (data/verilator_waiver.vlt)" : {file_type : vlt} 14 | file_type : verilogSource 15 | 16 | tb_files: 17 | depend: 18 | - ">=vlog_tb_utils-1.0" 19 | - wiredelay 20 | files: 21 | - bench/verilog/wb_master_model.v 22 | - bench/verilog/tst_bench_top.v 23 | - bench/verilog/i2c_slave_model.v 24 | file_type : verilogSource 25 | 26 | openlane: {files : [data/openlane.tcl : {file_type : tclSource}]} 27 | 28 | targets: 29 | default: 30 | filesets : [rtl_files] 31 | lint: 32 | default_tool : verilator 33 | filesets : [rtl_files] 34 | tools: 35 | verilator: 36 | mode : lint-only 37 | toplevel : i2c_master_top 38 | sim: 39 | default_tool : icarus 40 | filesets : [rtl_files, tb_files] 41 | parameters : [WITH_VTU] 42 | toplevel : [tst_bench_top] 43 | 44 | sky130: 45 | default_tool: openlane 46 | filesets: [rtl_files, openlane] 47 | toplevel: i2c_master_top 48 | 49 | parameters: 50 | WITH_VTU: 51 | datatype : bool 52 | default : true 53 | description : "(Internal use: Enables vlog_tb_utils for tb control)" 54 | paramtype : vlogdefine 55 | 56 | provider: 57 | name : github 58 | user : freecores 59 | repo : i2c 60 | version : v1.15 61 | -------------------------------------------------------------------------------- /jtag_tap/jtag_tap-1.13-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::jtag_tap:1.13-r1 3 | description : JTAG Tap 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - tap/rtl/verilog/tap_top.v 9 | file_type: verilogSource 10 | 11 | targets: 12 | default: 13 | filesets: [rtl] 14 | 15 | provider: 16 | name : github 17 | user : olofk 18 | repo : jtag 19 | version : v1.13 20 | -------------------------------------------------------------------------------- /jtag_vpi/jtag_vpi-r3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::jtag_vpi:0-r3 4 | description : TCP/IP controlled VPI JTAG Interface 5 | 6 | filesets : 7 | common : 8 | files : [jtag_common.c, jtag_common.h : {is_include_file : true}] 9 | file_type : cSource 10 | 11 | vpi : 12 | files : 13 | - jtag_vpi.c : {file_type : cSource} 14 | - jtag_vpi.v : {file_type : verilogSource} 15 | 16 | verilator : 17 | files : 18 | - jtagServer.cpp 19 | - jtagServer.h : {is_include_file : true} 20 | file_type : cppSource 21 | 22 | vpi: 23 | jtag_vpi: {filesets : [common, vpi]} 24 | 25 | targets : 26 | default: 27 | filesets : 28 | - common 29 | - "tool_verilator? (verilator)" 30 | - "!tool_verilator? (vpi)" 31 | parameters: [jtag_vpi_enable] 32 | 33 | parameters: 34 | jtag_vpi_enable: 35 | datatype : bool 36 | description : Enable JTAG debug interface 37 | paramtype : plusarg 38 | 39 | provider: 40 | name : github 41 | user : fjullien 42 | repo : jtag_vpi 43 | version : 4155b223b2da7a9f835eb07c8adc6715680c3c51 44 | -------------------------------------------------------------------------------- /jtag_vpi/jtag_vpi-r4.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::jtag_vpi:0-r4 4 | description : TCP/IP controlled VPI JTAG Interface 5 | 6 | filesets : 7 | common : 8 | files : [jtag_common.c, jtag_common.h : {is_include_file : true}] 9 | file_type : cSource 10 | 11 | vpi : 12 | files : 13 | - jtag_vpi.c : {file_type : cSource} 14 | - jtag_vpi.v : {file_type : verilogSource} 15 | 16 | verilator : 17 | files : 18 | - jtagServer.cpp 19 | - jtagServer.h : {is_include_file : true} 20 | file_type : cppSource 21 | 22 | vpi: 23 | jtag_vpi: {filesets : [common, vpi]} 24 | 25 | targets : 26 | default: 27 | filesets : 28 | - common 29 | - "tool_verilator? (verilator)" 30 | - "!tool_verilator? (vpi)" 31 | parameters: [jtag_vpi_enable] 32 | vpi : [jtag_vpi] 33 | 34 | parameters: 35 | jtag_vpi_enable: 36 | datatype : bool 37 | description : Enable JTAG debug interface 38 | paramtype : plusarg 39 | 40 | provider: 41 | name : github 42 | user : fjullien 43 | repo : jtag_vpi 44 | version : 4155b223b2da7a9f835eb07c8adc6715680c3c51 45 | -------------------------------------------------------------------------------- /jtag_vpi/jtag_vpi-r5.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::jtag_vpi:0-r5 4 | description : TCP/IP controlled VPI JTAG Interface 5 | 6 | filesets : 7 | common : 8 | files : [jtag_common.c, jtag_common.h : {is_include_file : true}] 9 | file_type : cSource 10 | 11 | vpi : 12 | files : 13 | - jtag_vpi.c : {file_type : cSource} 14 | - jtag_vpi.v : {file_type : verilogSource} 15 | 16 | verilator : 17 | files : 18 | - jtagServer.cpp 19 | - jtagServer.h : {is_include_file : true} 20 | file_type : cppSource 21 | 22 | vpi: 23 | jtag_vpi: {filesets : [common, vpi]} 24 | 25 | targets : 26 | default: 27 | filesets : 28 | - common 29 | - "tool_verilator? (verilator)" 30 | - "!tool_verilator? (vpi)" 31 | parameters: [jtag_vpi_enable] 32 | vpi : [jtag_vpi] 33 | 34 | parameters: 35 | jtag_vpi_enable: 36 | datatype : bool 37 | description : Enable JTAG debug interface 38 | paramtype : plusarg 39 | 40 | provider: 41 | name : github 42 | user : fjullien 43 | repo : jtag_vpi 44 | version : 600e65bb85d92d67a932c3b153991a2b74f78a77 45 | -------------------------------------------------------------------------------- /mor1kx/mor1kx-5.0-r2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::mor1kx:5.0-r2 4 | #description : mor1kx - an OpenRISC processor IP core 5 | 6 | filesets: 7 | core: 8 | files: 9 | - rtl/verilog/mor1kx-defines.v : {is_include_file : true} 10 | - rtl/verilog/mor1kx-sprs.v : {is_include_file : true} 11 | - rtl/verilog/mor1kx_utils.vh : {is_include_file : true} 12 | - rtl/verilog/mor1kx_branch_predictor_gshare.v 13 | - rtl/verilog/mor1kx_branch_predictor_simple.v 14 | - rtl/verilog/mor1kx_branch_predictor_saturation_counter.v 15 | - rtl/verilog/mor1kx_branch_prediction.v 16 | - rtl/verilog/mor1kx_bus_if_wb32.v 17 | - rtl/verilog/mor1kx_cache_lru.v 18 | - rtl/verilog/mor1kx_cfgrs.v 19 | - rtl/verilog/mor1kx_cpu_cappuccino.v 20 | - rtl/verilog/mor1kx_cpu_espresso.v 21 | - rtl/verilog/mor1kx_cpu_prontoespresso.v 22 | - rtl/verilog/mor1kx_cpu.v 23 | - rtl/verilog/mor1kx_ctrl_cappuccino.v 24 | - rtl/verilog/mor1kx_ctrl_espresso.v 25 | - rtl/verilog/mor1kx_ctrl_prontoespresso.v 26 | - rtl/verilog/mor1kx_dcache.v 27 | - rtl/verilog/mor1kx_decode_execute_cappuccino.v 28 | - rtl/verilog/mor1kx_decode.v 29 | - rtl/verilog/mor1kx_dmmu.v 30 | - rtl/verilog/mor1kx_execute_alu.v 31 | - rtl/verilog/mor1kx_execute_ctrl_cappuccino.v 32 | - rtl/verilog/mor1kx_fetch_cappuccino.v 33 | - rtl/verilog/mor1kx_fetch_espresso.v 34 | - rtl/verilog/mor1kx_fetch_prontoespresso.v 35 | - rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v 36 | - rtl/verilog/mor1kx_icache.v 37 | - rtl/verilog/mor1kx_immu.v 38 | - rtl/verilog/mor1kx_lsu_cappuccino.v 39 | - rtl/verilog/mor1kx_lsu_espresso.v 40 | - rtl/verilog/mor1kx_pcu.v 41 | - rtl/verilog/mor1kx_pic.v 42 | - rtl/verilog/mor1kx_rf_cappuccino.v 43 | - rtl/verilog/mor1kx_rf_espresso.v 44 | - rtl/verilog/mor1kx_simple_dpram_sclk.v 45 | - rtl/verilog/mor1kx_store_buffer.v 46 | - rtl/verilog/mor1kx_ticktimer.v 47 | - rtl/verilog/mor1kx_true_dpram_sclk.v 48 | - rtl/verilog/mor1kx.v 49 | - rtl/verilog/mor1kx_wb_mux_cappuccino.v 50 | - rtl/verilog/mor1kx_wb_mux_espresso.v 51 | file_type : verilogSource 52 | 53 | fpu: 54 | files: 55 | - rtl/verilog/pfpu32/pfpu32_addsub.v 56 | - rtl/verilog/pfpu32/pfpu32_cmp.v 57 | - rtl/verilog/pfpu32/pfpu32_f2i.v 58 | - rtl/verilog/pfpu32/pfpu32_i2f.v 59 | - rtl/verilog/pfpu32/pfpu32_muldiv.v 60 | - rtl/verilog/pfpu32/pfpu32_rnd.v 61 | - rtl/verilog/pfpu32/pfpu32_top.v 62 | file_type : verilogSource 63 | 64 | monitor: 65 | files : [bench/verilog/mor1kx_monitor.v] 66 | file_type : verilogSource 67 | 68 | parameters: 69 | trace_enable: 70 | datatype : bool 71 | description : Enable mor1kx instruction trace 72 | paramtype : plusarg 73 | 74 | trace_to_screen: 75 | datatype : bool 76 | description : Output mor1kx instruction trace to screen 77 | paramtype : plusarg 78 | 79 | targets: 80 | default: 81 | filesets: 82 | - core 83 | - fpu 84 | - "tool_icarus? (monitor)" 85 | - "tool_isim? (monitor)" 86 | - "tool_modelsim? (monitor)" 87 | - "tool_rivierapro? (monitor)" 88 | - "tool_xsim? (monitor)" 89 | parameters: [trace_enable, trace_to_screen] 90 | 91 | provider: 92 | name : github 93 | user : openrisc 94 | repo : mor1kx 95 | version : a9a01c009ea2b24764973560fde4a9855f4ba95d 96 | -------------------------------------------------------------------------------- /mor1kx/mor1kx-5.1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::mor1kx:5.1 4 | #description : mor1kx - an OpenRISC processor IP core 5 | 6 | filesets: 7 | core: 8 | files: 9 | - rtl/verilog/mor1kx-defines.v : {is_include_file : true} 10 | - rtl/verilog/mor1kx-sprs.v : {is_include_file : true} 11 | - rtl/verilog/mor1kx_utils.vh : {is_include_file : true} 12 | - rtl/verilog/mor1kx_branch_predictor_gshare.v 13 | - rtl/verilog/mor1kx_branch_predictor_simple.v 14 | - rtl/verilog/mor1kx_branch_predictor_saturation_counter.v 15 | - rtl/verilog/mor1kx_branch_prediction.v 16 | - rtl/verilog/mor1kx_bus_if_wb32.v 17 | - rtl/verilog/mor1kx_cache_lru.v 18 | - rtl/verilog/mor1kx_cfgrs.v 19 | - rtl/verilog/mor1kx_cpu_cappuccino.v 20 | - rtl/verilog/mor1kx_cpu_espresso.v 21 | - rtl/verilog/mor1kx_cpu_prontoespresso.v 22 | - rtl/verilog/mor1kx_cpu.v 23 | - rtl/verilog/mor1kx_ctrl_cappuccino.v 24 | - rtl/verilog/mor1kx_ctrl_espresso.v 25 | - rtl/verilog/mor1kx_ctrl_prontoespresso.v 26 | - rtl/verilog/mor1kx_dcache.v 27 | - rtl/verilog/mor1kx_decode_execute_cappuccino.v 28 | - rtl/verilog/mor1kx_decode.v 29 | - rtl/verilog/mor1kx_dmmu.v 30 | - rtl/verilog/mor1kx_execute_alu.v 31 | - rtl/verilog/mor1kx_execute_ctrl_cappuccino.v 32 | - rtl/verilog/mor1kx_fetch_cappuccino.v 33 | - rtl/verilog/mor1kx_fetch_espresso.v 34 | - rtl/verilog/mor1kx_fetch_prontoespresso.v 35 | - rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v 36 | - rtl/verilog/mor1kx_icache.v 37 | - rtl/verilog/mor1kx_immu.v 38 | - rtl/verilog/mor1kx_lsu_cappuccino.v 39 | - rtl/verilog/mor1kx_lsu_espresso.v 40 | - rtl/verilog/mor1kx_pcu.v 41 | - rtl/verilog/mor1kx_pic.v 42 | - rtl/verilog/mor1kx_rf_cappuccino.v 43 | - rtl/verilog/mor1kx_rf_espresso.v 44 | - rtl/verilog/mor1kx_simple_dpram_sclk.v 45 | - rtl/verilog/mor1kx_store_buffer.v 46 | - rtl/verilog/mor1kx_ticktimer.v 47 | - rtl/verilog/mor1kx_true_dpram_sclk.v 48 | - rtl/verilog/mor1kx.v 49 | - rtl/verilog/mor1kx_wb_mux_cappuccino.v 50 | - rtl/verilog/mor1kx_wb_mux_espresso.v 51 | file_type : verilogSource 52 | 53 | fpu: 54 | files: 55 | - rtl/verilog/pfpu32/pfpu32_addsub.v 56 | - rtl/verilog/pfpu32/pfpu32_cmp.v 57 | - rtl/verilog/pfpu32/pfpu32_f2i.v 58 | - rtl/verilog/pfpu32/pfpu32_i2f.v 59 | - rtl/verilog/pfpu32/pfpu32_muldiv.v 60 | - rtl/verilog/pfpu32/pfpu32_rnd.v 61 | - rtl/verilog/pfpu32/pfpu32_top.v 62 | file_type : verilogSource 63 | 64 | monitor: 65 | files : [bench/verilog/mor1kx_monitor.v] 66 | file_type : verilogSource 67 | 68 | parameters: 69 | trace_enable: 70 | datatype : bool 71 | description : Enable mor1kx instruction trace 72 | paramtype : plusarg 73 | 74 | trace_to_screen: 75 | datatype : bool 76 | description : Output mor1kx instruction trace to screen 77 | paramtype : plusarg 78 | 79 | targets: 80 | default: 81 | filesets: 82 | - core 83 | - fpu 84 | - "tool_icarus? (monitor)" 85 | - "tool_isim? (monitor)" 86 | - "tool_modelsim? (monitor)" 87 | - "tool_rivierapro? (monitor)" 88 | - "tool_xsim? (monitor)" 89 | parameters: [trace_enable, trace_to_screen] 90 | 91 | synth: 92 | default_tool : icestorm 93 | filesets : [core , fpu] 94 | tools: 95 | icestorm: 96 | pnr: none 97 | toplevel : mor1kx 98 | 99 | provider: 100 | name : github 101 | user : openrisc 102 | repo : mor1kx 103 | version : v5.1 104 | -------------------------------------------------------------------------------- /n25q128a11e/files/0001-Increase-max-length-for-filenames.patch: -------------------------------------------------------------------------------- 1 | From 30a43cd1e3f0e11e556bdc67718a18ec4994d1a6 Mon Sep 17 00:00:00 2001 2 | From: Olof Kindgren 3 | Date: Mon, 28 Nov 2016 12:14:33 +0100 4 | Subject: [PATCH 1/3] Increase max length for filenames 5 | 6 | --- 7 | N25Q128A11E_VG12/code/N25Qxxx.v | 10 +++++----- 8 | 1 file changed, 5 insertions(+), 5 deletions(-) 9 | 10 | diff --git a/N25Q128A11E_VG12/code/N25Qxxx.v b/N25Q128A11E_VG12/code/N25Qxxx.v 11 | index bce45ae..062ba4d 100644 12 | --- a/N25Q128A11E_VG12/code/N25Qxxx.v 13 | +++ b/N25Q128A11E_VG12/code/N25Qxxx.v 14 | @@ -128,10 +128,10 @@ inout Vpp_W_DQ2; //input Vpp_W, inout DQ2 (VPPH not implemented) 15 | 16 | 17 | //parameter [40*8:1] memory_file = "mem_Q016.vmf"; 18 | -parameter [40*8:1] memory_file = `FILENAME_mem; 19 | +parameter [2048*8:1] memory_file = `FILENAME_mem; 20 | 21 | // parameter [2048*8:1] fdp_file = "sfdp.vmf"; 22 | -parameter [48*8:1] fdp_file = `FILENAME_sfdp; 23 | +parameter [2048*8:1] fdp_file = `FILENAME_sfdp; 24 | 25 | 26 | reg PollingAccessOn = 0; 27 | @@ -3703,7 +3703,7 @@ module Memory(mem_file); 28 | `include "include/DevParam.h" 29 | 30 | 31 | - input [40*8:1] mem_file; 32 | + input [2048*8:1] mem_file; 33 | 34 | //----------------------------- 35 | // data structures definition 36 | @@ -4338,7 +4338,7 @@ module UtilFunctions; 37 | 38 | task load_memory_file; 39 | 40 | - input [40*8:1] memory_file; 41 | + input [2048*8:1] memory_file; 42 | 43 | begin 44 | 45 | @@ -7428,7 +7428,7 @@ module FlashDiscoveryParameter(sfdp_file); 46 | 47 | 48 | //input [2048*8:1] sfdp_file ; 49 | - input [48*8:1] sfdp_file ; 50 | + input [2048*8:1] sfdp_file ; 51 | //----------------------------- 52 | // data structures definition 53 | //----------------------------- 54 | -- 55 | 2.7.3 56 | 57 | -------------------------------------------------------------------------------- /n25q128a11e/files/0002-Optionally-disable-mem-clear-on-startup.patch: -------------------------------------------------------------------------------- 1 | From 8aba8dd386130ea93de5ab2e382cc83d79b5bcb8 Mon Sep 17 00:00:00 2001 2 | From: Olof Kindgren 3 | Date: Mon, 28 Nov 2016 12:15:17 +0100 4 | Subject: [PATCH 2/3] Optionally disable mem clear on startup 5 | 6 | --- 7 | N25Q128A11E_VG12/code/N25Qxxx.v | 6 ++++-- 8 | 1 file changed, 4 insertions(+), 2 deletions(-) 9 | 10 | diff --git a/N25Q128A11E_VG12/code/N25Qxxx.v b/N25Q128A11E_VG12/code/N25Qxxx.v 11 | index 062ba4d..75aac3b 100644 12 | --- a/N25Q128A11E_VG12/code/N25Qxxx.v 13 | +++ b/N25Q128A11E_VG12/code/N25Qxxx.v 14 | @@ -133,6 +133,7 @@ parameter [2048*8:1] memory_file = `FILENAME_mem; 15 | // parameter [2048*8:1] fdp_file = "sfdp.vmf"; 16 | parameter [2048*8:1] fdp_file = `FILENAME_sfdp; 17 | 18 | +parameter no_clear = 0; //Set param to disable slow memory clear on startup 19 | 20 | reg PollingAccessOn = 0; 21 | reg ReadAccessOn = 0; 22 | @@ -346,7 +347,7 @@ assign W_int = Vpp_W_DQ2; 23 | // Modules instantiations 24 | //--------------------------- 25 | 26 | -Memory mem (memory_file); 27 | +Memory #(.no_clear(no_clear)) mem (memory_file); 28 | 29 | UtilFunctions f (); 30 | 31 | @@ -3703,6 +3704,7 @@ module Memory(mem_file); 32 | `include "include/DevParam.h" 33 | 34 | 35 | + parameter no_clear = 0; 36 | input [2048*8:1] mem_file; 37 | 38 | //----------------------------- 39 | @@ -3735,7 +3737,7 @@ module Memory(mem_file); 40 | 41 | initial begin 42 | 43 | - for (i=0; i<=memDim-1; i=i+1) 44 | + for (i=0; i<=(no_clear ? 0 : memDim-1); i=i+1) 45 | memory[i] = data_NP; 46 | #1; 47 | 48 | -- 49 | 2.7.3 50 | 51 | -------------------------------------------------------------------------------- /n25q128a11e/files/0003-Add-workaround-for-Icarus-Verilog.patch: -------------------------------------------------------------------------------- 1 | From ff38378c36c363c164ba54b1b39f22e882a921c4 Mon Sep 17 00:00:00 2001 2 | From: Olof Kindgren 3 | Date: Mon, 28 Nov 2016 12:15:42 +0100 4 | Subject: [PATCH 3/3] Add workaround for Icarus Verilog 5 | 6 | --- 7 | N25Q128A11E_VG12/code/N25Qxxx.v | 2 ++ 8 | 1 file changed, 2 insertions(+) 9 | 10 | diff --git a/N25Q128A11E_VG12/code/N25Qxxx.v b/N25Q128A11E_VG12/code/N25Qxxx.v 11 | index 75aac3b..c88c2c9 100644 12 | --- a/N25Q128A11E_VG12/code/N25Qxxx.v 13 | +++ b/N25Q128A11E_VG12/code/N25Qxxx.v 14 | @@ -2022,7 +2022,9 @@ always @(sendToBus) begin 15 | 16 | 17 | dtr_dout_started = 1'b1; 18 | +`ifndef __ICARUS__ 19 | force DQ1 = 1'bX; 20 | +`endif 21 | if(N25Qxxx.DoubleTransferRate == 1) force DQ0 = 1'bX; 22 | if((cmdRecName == "Read Fast") || 23 | (cmdRecName == "Dual Command Fast Read") || 24 | -- 25 | 2.7.3 26 | 27 | -------------------------------------------------------------------------------- /n25q128a11e/n25q128a11e_vg12-1.2-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::n25q128a11e:1.2-r1 4 | description : Micron Verilog model, N25Q 128A11E, 1.8V, v1.1 5 | 6 | filesets: 7 | model: 8 | files: 9 | - N25Q128A11E_VG12/code/N25Qxxx.v 10 | - N25Q128A11E_VG12/include/Decoders.h : {is_include_file : true} 11 | - N25Q128A11E_VG12/include/DevParam.h : {is_include_file : true} 12 | - N25Q128A11E_VG12/include/PLRSDetectors.h : {is_include_file : true} 13 | - N25Q128A11E_VG12/include/TimingData.h : {is_include_file : true} 14 | - N25Q128A11E_VG12/include/UserData.h : {is_include_file : true} 15 | - N25Q128A11E_VG12/sim/sfdp.vmf : {is_include_file : true} 16 | file_type : verilogSource 17 | 18 | targets: 19 | default: {filesets : [model]} 20 | 21 | provider: 22 | name : url 23 | filetype : tar 24 | url : "https://media-www.micron.com/-/media/client/global/documents/products/sim-model/nor-flash/serial/bfm/n25q/n25q128a_micronxip_hold_18v_vg11,-d-,tar.gz?rev=35e5083ffec64d70ba7d88bb47f55f89" 25 | patches: 26 | - files/0001-Increase-max-length-for-filenames.patch 27 | - files/0002-Optionally-disable-mem-clear-on-startup.patch 28 | - files/0003-Add-workaround-for-Icarus-Verilog.patch 29 | -------------------------------------------------------------------------------- /ompic/ompic-1.0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: ::ompic:1.0-r1 3 | description: Open Multi-Processor Interrupt Controller core 4 | 5 | filesets: 6 | rtl_files: 7 | files: [rtl/verilog/ipi.v : {file_type: verilogSource}] 8 | 9 | targets: 10 | default: 11 | filesets: [rtl_files] 12 | 13 | provider: 14 | name : github 15 | user : openrisc 16 | repo : ompic 17 | version: v1.0 18 | -------------------------------------------------------------------------------- /open-logic/3.0.2/olo_axi.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:axi:3.0.2 4 | description : official release (stable); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/axi/vhdl/olo_axi_master_simple.vhd 10 | - src/axi/vhdl/olo_axi_pl_stage.vhd 11 | - src/axi/vhdl/olo_axi_master_full.vhd 12 | - src/axi/vhdl/olo_axi_lite_slave.vhd 13 | - src/axi/vhdl/olo_axi_pkg_protocol.vhd 14 | file_type : vhdlSource 15 | logical_name : olo 16 | depend : 17 | - "^open-logic:open-logic:base:3.0.2" 18 | 19 | 20 | targets: 21 | default: 22 | filesets : 23 | - rtl 24 | 25 | provider: 26 | name : github 27 | user : open-logic 28 | repo : open-logic 29 | version : 3.0.2 30 | -------------------------------------------------------------------------------- /open-logic/3.0.2/olo_base.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:base:3.0.2 4 | description : official release (stable); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/base/vhdl/olo_base_cc_n2xn.vhd 10 | - src/base/vhdl/olo_base_arb_rr.vhd 11 | - src/base/vhdl/olo_base_cc_simple.vhd 12 | - src/base/vhdl/olo_base_ram_sdp.vhd 13 | - src/base/vhdl/olo_base_delay_cfg.vhd 14 | - src/base/vhdl/olo_base_decode_firstbit.vhd 15 | - src/base/vhdl/olo_base_ram_tdp.vhd 16 | - src/base/vhdl/olo_base_strobe_gen.vhd 17 | - src/base/vhdl/olo_base_wconv_n2xn.vhd 18 | - src/base/vhdl/olo_base_fifo_async.vhd 19 | - src/base/vhdl/olo_base_arb_prio.vhd 20 | - src/base/vhdl/olo_base_cc_reset.vhd 21 | - src/base/vhdl/olo_base_delay.vhd 22 | - src/base/vhdl/olo_base_prbs.vhd 23 | - src/base/vhdl/olo_base_tdm_mux.vhd 24 | - src/base/vhdl/olo_base_cc_handshake.vhd 25 | - src/base/vhdl/olo_base_pkg_array.vhd 26 | - src/base/vhdl/olo_base_flowctrl_handler.vhd 27 | - src/base/vhdl/olo_base_dyn_sft.vhd 28 | - src/base/vhdl/olo_base_strobe_div.vhd 29 | - src/base/vhdl/olo_base_ram_sp.vhd 30 | - src/base/vhdl/olo_base_fifo_sync.vhd 31 | - src/base/vhdl/olo_base_cc_pulse.vhd 32 | - src/base/vhdl/olo_base_pkg_logic.vhd 33 | - src/base/vhdl/olo_base_cam.vhd 34 | - src/base/vhdl/olo_base_cc_status.vhd 35 | - src/base/vhdl/olo_base_reset_gen.vhd 36 | - src/base/vhdl/olo_base_pkg_math.vhd 37 | - src/base/vhdl/olo_base_wconv_xn2n.vhd 38 | - src/base/vhdl/olo_base_fifo_packet.vhd 39 | - src/base/vhdl/olo_base_pl_stage.vhd 40 | - src/base/vhdl/olo_base_cc_bits.vhd 41 | - src/base/vhdl/olo_base_cc_xn2n.vhd 42 | file_type : vhdlSource 43 | logical_name : olo 44 | 45 | 46 | targets: 47 | default: 48 | filesets : 49 | - rtl 50 | 51 | provider: 52 | name : github 53 | user : open-logic 54 | repo : open-logic 55 | version : 3.0.2 56 | -------------------------------------------------------------------------------- /open-logic/3.0.2/olo_intf.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:intf:3.0.2 4 | description : official release (stable); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/intf/vhdl/olo_intf_spi_slave.vhd 10 | - src/intf/vhdl/olo_intf_i2c_master.vhd 11 | - src/intf/vhdl/olo_intf_debounce.vhd 12 | - src/intf/vhdl/olo_intf_clk_meas.vhd 13 | - src/intf/vhdl/olo_intf_spi_master.vhd 14 | - src/intf/vhdl/olo_intf_sync.vhd 15 | - src/intf/vhdl/olo_intf_uart.vhd 16 | file_type : vhdlSource 17 | logical_name : olo 18 | depend : 19 | - "^open-logic:open-logic:base:3.0.2" 20 | 21 | 22 | targets: 23 | default: 24 | filesets : 25 | - rtl 26 | 27 | provider: 28 | name : github 29 | user : open-logic 30 | repo : open-logic 31 | version : 3.0.2 32 | -------------------------------------------------------------------------------- /open-logic/3.0.2/olo_quartus_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:quartus_tutorial:3.0.2 3 | description : official release (stable); quartus tutorial for open-logic, targetting DE0-CV board 4 | 5 | filesets: 6 | 7 | de0_cv: 8 | files: 9 | - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} 10 | - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} 11 | 12 | rtl: 13 | files: [quartus_tutorial.vhd : {file_type : vhdlSource}] 14 | depend : 15 | - "open-logic:open-logic:base" 16 | - "open-logic:open-logic:intf" 17 | 18 | targets: 19 | default: &default 20 | filesets : [rtl] 21 | toplevel: ["is_toplevel? (quartus_tutorial)"] 22 | 23 | de0_cv: 24 | default_tool : quartus 25 | filesets : [rtl, de0_cv] 26 | tools: 27 | quartus: 28 | family : Cyclone V 29 | device : 5CEBA4F23C7 30 | board_device_index : 2 31 | toplevel: quartus_tutorial 32 | 33 | provider: 34 | name : github 35 | user : open-logic 36 | repo : open-logic 37 | version : 3.0.2 38 | -------------------------------------------------------------------------------- /open-logic/3.0.2/olo_vivado_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:vivado_tutorial:3.0.2 3 | description : official release (stable); vivado tutorial for open-logic, targetting Zybo Z7-10 board 4 | 5 | filesets: 6 | 7 | zybo_z7: 8 | files: 9 | - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource} 10 | - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} 11 | 12 | rtl: 13 | files: [vivado_tutorial.vhd : {file_type : vhdlSource}] 14 | depend : 15 | - "open-logic:open-logic:base" 16 | - "open-logic:open-logic:intf" 17 | 18 | targets: 19 | default: &default 20 | filesets : [rtl] 21 | toplevel: ["is_toplevel? (vivado_tutorial)"] 22 | 23 | zybo_z7: 24 | default_tool: vivado 25 | description : Digilent Zybo Z7-10 SoC Kit 26 | filesets : [rtl, zybo_z7] 27 | tools: 28 | vivado: 29 | part : xc7z010clg400-1 30 | toplevel : vivado_tutorial 31 | 32 | provider: 33 | name : github 34 | user : open-logic 35 | repo : open-logic 36 | version : 3.0.2 37 | -------------------------------------------------------------------------------- /open-logic/3.1.0/olo_axi.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:axi:3.1.0 4 | description : stable release (downloaded from GitHub); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/axi/vhdl/olo_axi_master_simple.vhd 10 | - src/axi/vhdl/olo_axi_pl_stage.vhd 11 | - src/axi/vhdl/olo_axi_master_full.vhd 12 | - src/axi/vhdl/olo_axi_lite_slave.vhd 13 | - src/axi/vhdl/olo_axi_pkg_protocol.vhd 14 | file_type : vhdlSource 15 | logical_name : olo 16 | depend : 17 | - "^open-logic:open-logic:base:3.1.0" 18 | 19 | 20 | targets: 21 | default: 22 | filesets : 23 | - rtl 24 | 25 | provider: 26 | name : github 27 | user : open-logic 28 | repo : open-logic 29 | version : 3.1.0 30 | -------------------------------------------------------------------------------- /open-logic/3.1.0/olo_base.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:base:3.1.0 4 | description : stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/base/vhdl/olo_base_crc.vhd 10 | - src/base/vhdl/olo_base_cc_n2xn.vhd 11 | - src/base/vhdl/olo_base_arb_rr.vhd 12 | - src/base/vhdl/olo_base_cc_simple.vhd 13 | - src/base/vhdl/olo_base_ram_sdp.vhd 14 | - src/base/vhdl/olo_base_delay_cfg.vhd 15 | - src/base/vhdl/olo_base_decode_firstbit.vhd 16 | - src/base/vhdl/olo_base_ram_tdp.vhd 17 | - src/base/vhdl/olo_base_strobe_gen.vhd 18 | - src/base/vhdl/olo_base_wconv_n2m.vhd 19 | - src/base/vhdl/olo_base_wconv_n2xn.vhd 20 | - src/base/vhdl/olo_base_fifo_async.vhd 21 | - src/base/vhdl/olo_base_arb_prio.vhd 22 | - src/base/vhdl/olo_base_cc_reset.vhd 23 | - src/base/vhdl/olo_base_delay.vhd 24 | - src/base/vhdl/olo_base_prbs.vhd 25 | - src/base/vhdl/olo_base_tdm_mux.vhd 26 | - src/base/vhdl/olo_base_cc_handshake.vhd 27 | - src/base/vhdl/olo_base_pkg_array.vhd 28 | - src/base/vhdl/olo_base_flowctrl_handler.vhd 29 | - src/base/vhdl/olo_base_dyn_sft.vhd 30 | - src/base/vhdl/olo_base_strobe_div.vhd 31 | - src/base/vhdl/olo_base_ram_sp.vhd 32 | - src/base/vhdl/olo_base_fifo_sync.vhd 33 | - src/base/vhdl/olo_base_cc_pulse.vhd 34 | - src/base/vhdl/olo_base_pkg_logic.vhd 35 | - src/base/vhdl/olo_base_cam.vhd 36 | - src/base/vhdl/olo_base_pkg_attribute.vhd 37 | - src/base/vhdl/olo_base_cc_status.vhd 38 | - src/base/vhdl/olo_base_reset_gen.vhd 39 | - src/base/vhdl/olo_base_pkg_math.vhd 40 | - src/base/vhdl/olo_base_wconv_xn2n.vhd 41 | - src/base/vhdl/olo_base_fifo_packet.vhd 42 | - src/base/vhdl/olo_base_pl_stage.vhd 43 | - src/base/vhdl/olo_base_cc_bits.vhd 44 | - src/base/vhdl/olo_base_cc_xn2n.vhd 45 | file_type : vhdlSource 46 | logical_name : olo 47 | 48 | 49 | targets: 50 | default: 51 | filesets : 52 | - rtl 53 | 54 | provider: 55 | name : github 56 | user : open-logic 57 | repo : open-logic 58 | version : 3.1.0 59 | -------------------------------------------------------------------------------- /open-logic/3.1.0/olo_intf.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:intf:3.1.0 4 | description : stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/intf/vhdl/olo_intf_spi_slave.vhd 10 | - src/intf/vhdl/olo_intf_i2c_master.vhd 11 | - src/intf/vhdl/olo_intf_debounce.vhd 12 | - src/intf/vhdl/olo_intf_clk_meas.vhd 13 | - src/intf/vhdl/olo_intf_spi_master.vhd 14 | - src/intf/vhdl/olo_intf_sync.vhd 15 | - src/intf/vhdl/olo_intf_uart.vhd 16 | file_type : vhdlSource 17 | logical_name : olo 18 | depend : 19 | - "^open-logic:open-logic:base:3.1.0" 20 | 21 | 22 | targets: 23 | default: 24 | filesets : 25 | - rtl 26 | 27 | provider: 28 | name : github 29 | user : open-logic 30 | repo : open-logic 31 | version : 3.1.0 32 | -------------------------------------------------------------------------------- /open-logic/3.1.0/olo_quartus_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:quartus_tutorial:3.1.0 3 | description : stable release (downloaded from GitHub); quartus tutorial for open-logic, targetting DE0-CV board 4 | 5 | filesets: 6 | 7 | de0_cv: 8 | files: 9 | - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} 10 | - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} 11 | 12 | rtl: 13 | files: 14 | - doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource} 15 | depend : 16 | - "open-logic:open-logic:base" 17 | - "open-logic:open-logic:intf" 18 | 19 | targets: 20 | default: &default 21 | filesets : [rtl] 22 | toplevel: ["is_toplevel? (quartus_tutorial)"] 23 | 24 | de0_cv: 25 | default_tool : quartus 26 | filesets : [rtl, de0_cv] 27 | tools: 28 | quartus: 29 | family : Cyclone V 30 | device : 5CEBA4F23C7 31 | board_device_index : 2 32 | toplevel: quartus_tutorial 33 | 34 | provider: 35 | name : github 36 | user : open-logic 37 | repo : open-logic 38 | version : 3.1.0 39 | -------------------------------------------------------------------------------- /open-logic/3.1.0/olo_vivado_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:vivado_tutorial:3.1.0 3 | description : stable release (downloaded from GitHub); vivado tutorial for open-logic, targetting Zybo Z7-10 board 4 | 5 | filesets: 6 | 7 | zybo_z7: 8 | files: 9 | - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} 10 | 11 | rtl: 12 | files: 13 | - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource} 14 | depend : 15 | - "open-logic:open-logic:base" 16 | - "open-logic:open-logic:intf" 17 | 18 | targets: 19 | default: &default 20 | filesets : [rtl] 21 | toplevel: ["is_toplevel? (vivado_tutorial)"] 22 | 23 | zybo_z7: 24 | default_tool: vivado 25 | description : Digilent Zybo Z7-10 SoC Kit 26 | filesets : [rtl, zybo_z7] 27 | tools: 28 | vivado: 29 | part : xc7z010clg400-1 30 | toplevel : vivado_tutorial 31 | 32 | provider: 33 | name : github 34 | user : open-logic 35 | repo : open-logic 36 | version : 3.1.0 37 | -------------------------------------------------------------------------------- /open-logic/3.2.0/olo_axi.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:axi:3.2.0 4 | description : stable release (downloaded from GitHub); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/axi/vhdl/olo_axi_master_simple.vhd 10 | - src/axi/vhdl/olo_axi_pl_stage.vhd 11 | - src/axi/vhdl/olo_axi_master_full.vhd 12 | - src/axi/vhdl/olo_axi_lite_slave.vhd 13 | - src/axi/vhdl/olo_axi_pkg_protocol.vhd 14 | file_type : vhdlSource 15 | logical_name : olo 16 | depend : 17 | - "^open-logic:open-logic:base:3.2.0" 18 | 19 | 20 | targets: 21 | default: 22 | filesets : 23 | - rtl 24 | 25 | provider: 26 | name : github 27 | user : open-logic 28 | repo : open-logic 29 | version : 3.2.0 30 | -------------------------------------------------------------------------------- /open-logic/3.2.0/olo_base.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:base:3.2.0 4 | description : stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/base/vhdl/olo_base_crc.vhd 10 | - src/base/vhdl/olo_base_cc_n2xn.vhd 11 | - src/base/vhdl/olo_base_arb_rr.vhd 12 | - src/base/vhdl/olo_base_cc_simple.vhd 13 | - src/base/vhdl/olo_base_ram_sdp.vhd 14 | - src/base/vhdl/olo_base_delay_cfg.vhd 15 | - src/base/vhdl/olo_base_decode_firstbit.vhd 16 | - src/base/vhdl/olo_base_ram_tdp.vhd 17 | - src/base/vhdl/olo_base_strobe_gen.vhd 18 | - src/base/vhdl/olo_base_wconv_n2m.vhd 19 | - src/base/vhdl/olo_base_wconv_n2xn.vhd 20 | - src/base/vhdl/olo_base_fifo_async.vhd 21 | - src/base/vhdl/olo_base_arb_prio.vhd 22 | - src/base/vhdl/olo_base_cc_reset.vhd 23 | - src/base/vhdl/olo_base_delay.vhd 24 | - src/base/vhdl/olo_base_prbs.vhd 25 | - src/base/vhdl/olo_base_tdm_mux.vhd 26 | - src/base/vhdl/olo_base_cc_handshake.vhd 27 | - src/base/vhdl/olo_base_pkg_string.vhd 28 | - src/base/vhdl/olo_base_pkg_array.vhd 29 | - src/base/vhdl/olo_base_flowctrl_handler.vhd 30 | - src/base/vhdl/olo_base_dyn_sft.vhd 31 | - src/base/vhdl/olo_base_strobe_div.vhd 32 | - src/base/vhdl/olo_base_ram_sp.vhd 33 | - src/base/vhdl/olo_base_fifo_sync.vhd 34 | - src/base/vhdl/olo_base_cc_pulse.vhd 35 | - src/base/vhdl/olo_base_pkg_logic.vhd 36 | - src/base/vhdl/olo_base_cam.vhd 37 | - src/base/vhdl/olo_base_pkg_attribute.vhd 38 | - src/base/vhdl/olo_base_cc_status.vhd 39 | - src/base/vhdl/olo_base_reset_gen.vhd 40 | - src/base/vhdl/olo_base_pkg_math.vhd 41 | - src/base/vhdl/olo_base_wconv_xn2n.vhd 42 | - src/base/vhdl/olo_base_fifo_packet.vhd 43 | - src/base/vhdl/olo_base_pl_stage.vhd 44 | - src/base/vhdl/olo_base_cc_bits.vhd 45 | - src/base/vhdl/olo_base_cc_xn2n.vhd 46 | file_type : vhdlSource 47 | logical_name : olo 48 | 49 | 50 | targets: 51 | default: 52 | filesets : 53 | - rtl 54 | 55 | provider: 56 | name : github 57 | user : open-logic 58 | repo : open-logic 59 | version : 3.2.0 60 | -------------------------------------------------------------------------------- /open-logic/3.2.0/olo_intf.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:intf:3.2.0 4 | description : stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/intf/vhdl/olo_intf_spi_slave.vhd 10 | - src/intf/vhdl/olo_intf_i2c_master.vhd 11 | - src/intf/vhdl/olo_intf_debounce.vhd 12 | - src/intf/vhdl/olo_intf_clk_meas.vhd 13 | - src/intf/vhdl/olo_intf_spi_master.vhd 14 | - src/intf/vhdl/olo_intf_sync.vhd 15 | - src/intf/vhdl/olo_intf_uart.vhd 16 | file_type : vhdlSource 17 | logical_name : olo 18 | depend : 19 | - "^open-logic:open-logic:base:3.2.0" 20 | 21 | 22 | targets: 23 | default: 24 | filesets : 25 | - rtl 26 | 27 | provider: 28 | name : github 29 | user : open-logic 30 | repo : open-logic 31 | version : 3.2.0 32 | -------------------------------------------------------------------------------- /open-logic/3.2.0/olo_quartus_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:quartus_tutorial:3.2.0 3 | description : stable release (downloaded from GitHub); quartus tutorial for open-logic, targetting DE0-CV board 4 | 5 | filesets: 6 | 7 | de0_cv: 8 | files: 9 | - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} 10 | - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} 11 | 12 | rtl: 13 | files: 14 | - doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource} 15 | depend : 16 | - "open-logic:open-logic:base" 17 | - "open-logic:open-logic:intf" 18 | 19 | targets: 20 | default: &default 21 | filesets : [rtl] 22 | toplevel: ["is_toplevel? (quartus_tutorial)"] 23 | 24 | de0_cv: 25 | default_tool : quartus 26 | filesets : [rtl, de0_cv] 27 | tools: 28 | quartus: 29 | family : Cyclone V 30 | device : 5CEBA4F23C7 31 | board_device_index : 2 32 | toplevel: quartus_tutorial 33 | 34 | provider: 35 | name : github 36 | user : open-logic 37 | repo : open-logic 38 | version : 3.2.0 39 | -------------------------------------------------------------------------------- /open-logic/3.2.0/olo_vivado_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:vivado_tutorial:3.2.0 3 | description : stable release (downloaded from GitHub); vivado tutorial for open-logic, targetting Zybo Z7-10 board 4 | 5 | filesets: 6 | 7 | zybo_z7: 8 | files: 9 | - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} 10 | 11 | rtl: 12 | files: 13 | - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource} 14 | depend : 15 | - "open-logic:open-logic:base" 16 | - "open-logic:open-logic:intf" 17 | 18 | targets: 19 | default: &default 20 | filesets : [rtl] 21 | toplevel: ["is_toplevel? (vivado_tutorial)"] 22 | 23 | zybo_z7: 24 | default_tool: vivado 25 | description : Digilent Zybo Z7-10 SoC Kit 26 | filesets : [rtl, zybo_z7] 27 | tools: 28 | vivado: 29 | part : xc7z010clg400-1 30 | toplevel : vivado_tutorial 31 | 32 | provider: 33 | name : github 34 | user : open-logic 35 | repo : open-logic 36 | version : 3.2.0 37 | -------------------------------------------------------------------------------- /open-logic/3.3.0/en_cl_fix.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:en_cl_fix:2.2.0 4 | description : stable release (downloaded from GitHub); see https://github.com/enclustra/en_cl_fix/blob/main/README.md 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - hdl/en_cl_fix_private_pkg.vhd 10 | - hdl/en_cl_fix_pkg.vhd 11 | file_type : vhdlSource 12 | logical_name : olo 13 | 14 | targets: 15 | default: 16 | filesets : 17 | - rtl 18 | 19 | provider: 20 | name : github 21 | user : open-logic 22 | repo : en_cl_fix 23 | version : open-logic-2.2.0 24 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_axi.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:axi:3.3.0 4 | description : stable release (downloaded from GitHub); AXI related modules see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#axi 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/axi/vhdl/olo_axi_master_simple.vhd 10 | - src/axi/vhdl/olo_axi_pl_stage.vhd 11 | - src/axi/vhdl/olo_axi_master_full.vhd 12 | - src/axi/vhdl/olo_axi_lite_slave.vhd 13 | - src/axi/vhdl/olo_axi_pkg_protocol.vhd 14 | file_type : vhdlSource 15 | logical_name : olo 16 | depend : 17 | - "^open-logic:open-logic:base:3.3.0" 18 | 19 | 20 | targets: 21 | default: 22 | filesets : 23 | - rtl 24 | 25 | provider: 26 | name : github 27 | user : open-logic 28 | repo : open-logic 29 | version : 3.3.0 30 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_base.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:base:3.3.0 4 | description : stable release (downloaded from GitHub); Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#base 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/base/vhdl/olo_base_crc.vhd 10 | - src/base/vhdl/olo_base_cc_n2xn.vhd 11 | - src/base/vhdl/olo_base_arb_rr.vhd 12 | - src/base/vhdl/olo_base_cc_simple.vhd 13 | - src/base/vhdl/olo_base_ram_sdp.vhd 14 | - src/base/vhdl/olo_base_delay_cfg.vhd 15 | - src/base/vhdl/olo_base_decode_firstbit.vhd 16 | - src/base/vhdl/olo_base_ram_tdp.vhd 17 | - src/base/vhdl/olo_base_strobe_gen.vhd 18 | - src/base/vhdl/olo_base_wconv_n2m.vhd 19 | - src/base/vhdl/olo_base_wconv_n2xn.vhd 20 | - src/base/vhdl/olo_base_fifo_async.vhd 21 | - src/base/vhdl/olo_base_arb_prio.vhd 22 | - src/base/vhdl/olo_base_cc_reset.vhd 23 | - src/base/vhdl/olo_base_delay.vhd 24 | - src/base/vhdl/olo_base_prbs.vhd 25 | - src/base/vhdl/olo_base_tdm_mux.vhd 26 | - src/base/vhdl/olo_base_cc_handshake.vhd 27 | - src/base/vhdl/olo_base_pkg_string.vhd 28 | - src/base/vhdl/olo_base_pkg_array.vhd 29 | - src/base/vhdl/olo_base_flowctrl_handler.vhd 30 | - src/base/vhdl/olo_base_dyn_sft.vhd 31 | - src/base/vhdl/olo_base_strobe_div.vhd 32 | - src/base/vhdl/olo_base_ram_sp.vhd 33 | - src/base/vhdl/olo_base_fifo_sync.vhd 34 | - src/base/vhdl/olo_base_cc_pulse.vhd 35 | - src/base/vhdl/olo_base_pkg_logic.vhd 36 | - src/base/vhdl/olo_base_cam.vhd 37 | - src/base/vhdl/olo_base_pkg_attribute.vhd 38 | - src/base/vhdl/olo_base_cc_status.vhd 39 | - src/base/vhdl/olo_base_reset_gen.vhd 40 | - src/base/vhdl/olo_base_pkg_math.vhd 41 | - src/base/vhdl/olo_base_wconv_xn2n.vhd 42 | - src/base/vhdl/olo_base_fifo_packet.vhd 43 | - src/base/vhdl/olo_base_pl_stage.vhd 44 | - src/base/vhdl/olo_base_cc_bits.vhd 45 | - src/base/vhdl/olo_base_cc_xn2n.vhd 46 | file_type : vhdlSource 47 | logical_name : olo 48 | 49 | 50 | targets: 51 | default: 52 | filesets : 53 | - rtl 54 | 55 | provider: 56 | name : github 57 | user : open-logic 58 | repo : open-logic 59 | version : 3.3.0 60 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_fix.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:fix:3.3.0 4 | description : stable release (downloaded from GitHub); Fixed point mathematics see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#fix 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/fix/vhdl/olo_fix_abs.vhd 10 | - src/fix/vhdl/olo_fix_round.vhd 11 | - src/fix/vhdl/olo_fix_limit.vhd 12 | - src/fix/vhdl/olo_fix_sim_stimuli.vhd 13 | - src/fix/vhdl/olo_fix_resize.vhd 14 | - src/fix/vhdl/olo_fix_to_real.vhd 15 | - src/fix/vhdl/olo_fix_pkg.vhd 16 | - src/fix/vhdl/olo_fix_add.vhd 17 | - src/fix/vhdl/olo_fix_private_optional_reg.vhd 18 | - src/fix/vhdl/olo_fix_compare.vhd 19 | - src/fix/vhdl/olo_fix_saturate.vhd 20 | - src/fix/vhdl/olo_fix_sub.vhd 21 | - src/fix/vhdl/olo_fix_mult.vhd 22 | - src/fix/vhdl/olo_fix_addsub.vhd 23 | - src/fix/vhdl/olo_fix_neg.vhd 24 | - src/fix/vhdl/olo_fix_from_real.vhd 25 | - src/fix/vhdl/olo_fix_sim_checker.vhd 26 | file_type : vhdlSource 27 | logical_name : olo 28 | depend : 29 | - "^open-logic:open-logic:base:3.3.0" 30 | - "^open-logic:open-logic:en_cl_fix:2.2.0" 31 | 32 | 33 | targets: 34 | default: 35 | filesets : 36 | - rtl 37 | 38 | provider: 39 | name : github 40 | user : open-logic 41 | repo : open-logic 42 | version : 3.3.0 43 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_fix_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:olo_fix_tutorial:3.3.0 3 | description : stable release (downloaded from GitHub); olo_fix tutorial for open-logic, targetting Zybo Z7-10 board 4 | 5 | filesets: 6 | 7 | zybo_z7: 8 | files: 9 | - doc/tutorials/OloFixTutorial/Files/timing.xdc : {file_type : xdc} 10 | 11 | rtl: 12 | files: 13 | - doc/tutorials/OloFixTutorial/Files/controller_olo_fix.vhd : {file_type : vhdlSource} 14 | - doc/tutorials/OloFixTutorial/Files/fix_formats_pkg.vhd : {file_type : vhdlSource} 15 | depend : 16 | - "open-logic:open-logic:fix" 17 | 18 | targets: 19 | default: &default 20 | filesets : [rtl] 21 | toplevel: ["is_toplevel? (olo_fix_tutorial_controller)"] 22 | 23 | zybo_z7: 24 | default_tool: vivado 25 | description : Digilent Zybo Z7-10 SoC Kit 26 | filesets : [rtl, zybo_z7] 27 | tools: 28 | vivado: 29 | part : xc7z010clg400-1 30 | toplevel : olo_fix_tutorial_controller 31 | 32 | provider: 33 | name : github 34 | user : open-logic 35 | repo : open-logic 36 | version : 3.3.0 37 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_intf.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : open-logic:open-logic:intf:3.3.0 4 | description : stable release (downloaded from GitHub); Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.com/open-logic/open-logic/blob/main/doc/EntityList.md#intf 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - src/intf/vhdl/olo_intf_spi_slave.vhd 10 | - src/intf/vhdl/olo_intf_i2c_master.vhd 11 | - src/intf/vhdl/olo_intf_debounce.vhd 12 | - src/intf/vhdl/olo_intf_clk_meas.vhd 13 | - src/intf/vhdl/olo_intf_spi_master.vhd 14 | - src/intf/vhdl/olo_intf_sync.vhd 15 | - src/intf/vhdl/olo_intf_uart.vhd 16 | file_type : vhdlSource 17 | logical_name : olo 18 | depend : 19 | - "^open-logic:open-logic:base:3.3.0" 20 | 21 | 22 | targets: 23 | default: 24 | filesets : 25 | - rtl 26 | 27 | provider: 28 | name : github 29 | user : open-logic 30 | repo : open-logic 31 | version : 3.3.0 32 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_quartus_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:quartus_tutorial:3.3.0 3 | description : stable release (downloaded from GitHub); quartus tutorial for open-logic, targetting DE0-CV board 4 | 5 | filesets: 6 | 7 | de0_cv: 8 | files: 9 | - doc/tutorials/QuartusTutorial/Files/timing.sdc : {file_type : SDC} 10 | - doc/tutorials/QuartusTutorial/Files/pinout.tcl : {file_type : tclSource} 11 | 12 | rtl: 13 | files: 14 | - doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource} 15 | depend : 16 | - "open-logic:open-logic:base" 17 | - "open-logic:open-logic:intf" 18 | 19 | targets: 20 | default: &default 21 | filesets : [rtl] 22 | toplevel: ["is_toplevel? (quartus_tutorial)"] 23 | 24 | de0_cv: 25 | default_tool : quartus 26 | filesets : [rtl, de0_cv] 27 | tools: 28 | quartus: 29 | family : Cyclone V 30 | device : 5CEBA4F23C7 31 | board_device_index : 2 32 | toplevel: quartus_tutorial 33 | 34 | provider: 35 | name : github 36 | user : open-logic 37 | repo : open-logic 38 | version : 3.3.0 39 | -------------------------------------------------------------------------------- /open-logic/3.3.0/olo_vivado_tutorial.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : open-logic:tutorials:vivado_tutorial:3.3.0 3 | description : stable release (downloaded from GitHub); vivado tutorial for open-logic, targetting Zybo Z7-10 board 4 | 5 | filesets: 6 | 7 | zybo_z7: 8 | files: 9 | - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc} 10 | 11 | rtl: 12 | files: 13 | - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource} 14 | depend : 15 | - "open-logic:open-logic:base" 16 | - "open-logic:open-logic:intf" 17 | 18 | targets: 19 | default: &default 20 | filesets : [rtl] 21 | toplevel: ["is_toplevel? (vivado_tutorial)"] 22 | 23 | zybo_z7: 24 | default_tool: vivado 25 | description : Digilent Zybo Z7-10 SoC Kit 26 | filesets : [rtl, zybo_z7] 27 | tools: 28 | vivado: 29 | part : xc7z010clg400-1 30 | toplevel : vivado_tutorial 31 | 32 | provider: 33 | name : github 34 | user : open-logic 35 | repo : open-logic 36 | version : 3.3.0 37 | -------------------------------------------------------------------------------- /or1k_bootloaders/or1k_bootloaders-0.9.1-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: ::or1k_bootloaders:0.9.1-r1 3 | description: Wishbone boot ROM component and a collection of basic boot loaders for OpenRISC 1000 4 | 5 | filesets: 6 | bootloaders: 7 | files: 8 | - boot_loop.vh: {is_include_file: true} 9 | - clear_r3_and_jump_to_0x100.vh: {is_include_file: true} 10 | - led_blink.vh: {is_include_file: true} 11 | - spi_uimage_loader.vh: {is_include_file: true} 12 | file_type: verilogSource 13 | 14 | bootrom: 15 | files: [wb_bootrom.v : {file_type: verilogSource}] 16 | 17 | targets: 18 | default: 19 | filesets: [bootrom, bootloaders] 20 | 21 | provider: 22 | name: github 23 | user: olofk 24 | repo: or1k_bootloaders 25 | version: v0.9.1 26 | -------------------------------------------------------------------------------- /pulp-platform.org/apb-0.1.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: pulp-platform.org::apb:0.1.0 3 | filesets : {rtl : {files : [src/apb_intf.sv : {file_type : systemVerilogSource}]}} 4 | targets : {default : {filesets : [rtl]}} 5 | 6 | provider: 7 | name : github 8 | user : pulp-platform 9 | repo : apb 10 | version : v0.1.0 11 | -------------------------------------------------------------------------------- /pulp-platform.org/apb_uart_sv-0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::apb_uart_sv:0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - apb_uart_sv.sv 9 | - uart_rx.sv 10 | - uart_tx.sv 11 | - io_generic_fifo.sv 12 | - uart_interrupt.sv 13 | file_type : systemVerilogSource 14 | 15 | targets: {default : {filesets : [rtl]}} 16 | 17 | provider: 18 | name : github 19 | user : olofk 20 | repo : apb_uart_sv 21 | version : 5309631455a5f41fed5793231ed11ac66ae31e17 22 | -------------------------------------------------------------------------------- /pulp-platform.org/axi-0.23.0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::axi:0.23.0-r1 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - include/dummy : {is_include_file : true} 9 | - include/axi/assign.svh : {file_type : user} 10 | - include/axi/typedef.svh : {file_type : user} 11 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this 12 | # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 13 | # levels 1 and 0, etc. Files within a level are ordered alphabetically. 14 | # Level 0 15 | - src/axi_pkg.sv 16 | # Level 1 17 | - src/axi_intf.sv 18 | # Level 2 19 | - src/axi_atop_filter.sv 20 | - src/axi_burst_splitter.sv 21 | - src/axi_cdc.sv 22 | - src/axi_cut.sv 23 | - src/axi_delayer.sv 24 | - src/axi_demux.sv 25 | - src/axi_dw_downsizer.sv 26 | - src/axi_dw_upsizer.sv 27 | - src/axi_id_prepend.sv 28 | - src/axi_isolate.sv 29 | - src/axi_join.sv 30 | - src/axi_lite_demux.sv 31 | - src/axi_lite_join.sv 32 | - src/axi_lite_mailbox.sv 33 | - src/axi_lite_mux.sv 34 | - src/axi_lite_regs.sv 35 | - src/axi_lite_to_apb.sv 36 | - src/axi_lite_to_axi.sv 37 | - src/axi_modify_address.sv 38 | - src/axi_mux.sv 39 | - src/axi_serializer.sv 40 | # Level 3 41 | - src/axi_err_slv.sv 42 | - src/axi_dw_converter.sv 43 | - src/axi_multicut.sv 44 | - src/axi_to_axi_lite.sv 45 | # Level 4 46 | - src/axi_lite_xbar.sv 47 | - src/axi_xbar.sv 48 | file_type : systemVerilogSource 49 | depend : 50 | - ">=pulp-platform.org::common_cells:1.16.4" 51 | 52 | generators: 53 | axi_intercon_gen: 54 | interpreter: python3 55 | command: scripts/axi_intercon_gen.py 56 | description: Generate a wrapper around PULP AXI xbar interconnect 57 | usage: | 58 | axi_intercon_gen wraps axi_xbar by expanding arrays of signals into 59 | human-readable buses. Memory map can be set with generator parameters. 60 | It will also generate a verilog include file containing the wire 61 | definitions and module instantiation which can be `included in the 62 | module where the interconnect wrapper is intended to be used. 63 | 64 | Parameters: 65 | masters: A dictionary where each key names a master interface connecting 66 | to the interconnect and the associated value contains 67 | configuration for that interface. 68 | 69 | id_width (int): Width of the id signals for the master 70 | 71 | slaves: A dictionary where each key names a slave interface connecting 72 | to the interconnect and the associated value contains 73 | configuration for that interface. The following configuration 74 | keys are defined 75 | 76 | offset (int): Base address for the slave 77 | size (int): Size of the allocated memory map for the slave 78 | 79 | Example usage: 80 | The following config will generate an interconnect wrapper to which two 81 | AXI4 master interfaces (dma and ibus) with different id widths are 82 | connected, and connects downstream to three AXI4 slaves (rom, gpio, ram) 83 | 84 | soc_intercon: 85 | generator: axi_intercon_gen 86 | parameters: 87 | masters: 88 | dma: 89 | id_width : 1 90 | ibus: 91 | id_width : 2 92 | slaves: 93 | ram: 94 | offset : 0 95 | size: 0x10000000 96 | gpio: 97 | offset: 0x91000000 98 | size: 0x1000 99 | rom: 100 | offset : 0xffff0000 101 | size : 32768 102 | 103 | targets: 104 | default: 105 | filesets : [rtl] 106 | 107 | provider: 108 | name : github 109 | user : pulp-platform 110 | repo : axi 111 | version : 4fa050beddb00da40c5144d1edd4699a082df744 112 | -------------------------------------------------------------------------------- /pulp-platform.org/axi-0.25.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::axi:0.25.0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - include/axi/assign.svh : {is_include_file : true, include_path : include} 9 | - include/axi/typedef.svh : {is_include_file : true, include_path : include} 10 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this 11 | # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 12 | # levels 1 and 0, etc. Files within a level are ordered alphabetically. 13 | # Level 0 14 | - src/axi_pkg.sv 15 | # Level 1 16 | - src/axi_intf.sv 17 | # Level 2 18 | - src/axi_atop_filter.sv 19 | - src/axi_burst_splitter.sv 20 | - src/axi_cdc.sv 21 | - src/axi_cut.sv 22 | - src/axi_delayer.sv 23 | - src/axi_demux.sv 24 | - src/axi_dw_downsizer.sv 25 | - src/axi_dw_upsizer.sv 26 | - src/axi_id_prepend.sv 27 | - src/axi_isolate.sv 28 | - src/axi_join.sv 29 | - src/axi_lite_demux.sv 30 | - src/axi_lite_join.sv 31 | - src/axi_lite_mailbox.sv 32 | - src/axi_lite_mux.sv 33 | - src/axi_lite_regs.sv 34 | - src/axi_lite_to_apb.sv 35 | - src/axi_lite_to_axi.sv 36 | - src/axi_modify_address.sv 37 | - src/axi_mux.sv 38 | - src/axi_serializer.sv 39 | # Level 3 40 | - src/axi_err_slv.sv 41 | - src/axi_dw_converter.sv 42 | - src/axi_multicut.sv 43 | - src/axi_to_axi_lite.sv 44 | # Level 4 45 | - src/axi_lite_xbar.sv 46 | - src/axi_xbar.sv 47 | file_type : systemVerilogSource 48 | depend : 49 | - ">=pulp-platform.org::common_cells:1.16.4" 50 | 51 | generators: 52 | axi_intercon_gen: 53 | interpreter: python3 54 | command: scripts/axi_intercon_gen.py 55 | description: Generate a wrapper around PULP AXI xbar interconnect 56 | usage: | 57 | axi_intercon_gen wraps axi_xbar by expanding arrays of signals into 58 | human-readable buses. Memory map can be set with generator parameters. 59 | It will also generate a verilog include file containing the wire 60 | definitions and module instantiation which can be `included in the 61 | module where the interconnect wrapper is intended to be used. 62 | 63 | Parameters: 64 | masters: A dictionary where each key names a master interface connecting 65 | to the interconnect and the associated value contains 66 | configuration for that interface. 67 | 68 | id_width (int): Width of the id signals for the master 69 | 70 | slaves: A dictionary where each key names a slave interface connecting 71 | to the interconnect and the associated value contains 72 | configuration for that interface. The following configuration 73 | keys are defined 74 | 75 | offset (int): Base address for the slave 76 | size (int): Size of the allocated memory map for the slave 77 | 78 | Example usage: 79 | The following config will generate an interconnect wrapper to which two 80 | AXI4 master interfaces (dma and ibus) with different id widths are 81 | connected, and connects downstream to three AXI4 slaves (rom, gpio, ram) 82 | 83 | soc_intercon: 84 | generator: axi_intercon_gen 85 | parameters: 86 | masters: 87 | dma: 88 | id_width : 1 89 | ibus: 90 | id_width : 2 91 | slaves: 92 | ram: 93 | offset : 0 94 | size: 0x10000000 95 | gpio: 96 | offset: 0x91000000 97 | size: 0x1000 98 | rom: 99 | offset : 0xffff0000 100 | size : 32768 101 | 102 | targets: 103 | default: 104 | filesets : [rtl] 105 | 106 | provider: 107 | name : github 108 | user : pulp-platform 109 | repo : axi 110 | version : v0.25.0 111 | 112 | -------------------------------------------------------------------------------- /pulp-platform.org/axi-0.6.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::axi:0.6 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - src/axi_pkg.sv 9 | - src/axi_join.sv 10 | - src/axi_lite_multicut.sv 11 | - src/axi_intf.sv 12 | - src/axi_lite_join.sv 13 | - src/axi_arbiter.sv 14 | - src/axi_delayer.sv 15 | - src/axi_lite_cut.sv 16 | - src/axi_lite_xbar.sv 17 | - src/axi_multicut.sv 18 | - src/axi_address_resolver.sv 19 | - src/axi_to_axi_lite.sv 20 | - src/axi_lite_to_axi.sv 21 | - src/axi_cut.sv 22 | - src/axi_modify_address.sv 23 | - src/axi_id_remap.sv 24 | file_type: systemVerilogSource 25 | depend : ["pulp-platform.org::common_cells"] 26 | 27 | tb: 28 | files: 29 | - src/axi_test.sv 30 | - test/tb_axi_lite_xbar.sv 31 | file_type : systemVerilogSource 32 | targets: 33 | default: 34 | filesets : [rtl] 35 | 36 | lint: 37 | default_tool : verilator 38 | filesets : [rtl] 39 | tools: 40 | verilator: 41 | mode: lint-only 42 | toplevel: axi_lite_xbar 43 | sim: 44 | default_tool : modelsim 45 | filesets: [rtl, tb] 46 | toplevel : tb_axi_lite_xbar 47 | 48 | provider: 49 | name : github 50 | user : pulp-platform 51 | repo : axi 52 | version : v0.6.0 53 | -------------------------------------------------------------------------------- /pulp-platform.org/axi2apb-0.1.1-r3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: pulp-platform.org::axi2apb:0.1.1-r3 3 | 4 | filesets: 5 | rtl: 6 | files: 7 | - src/axi2apb.sv 8 | - src/axi2apb_64_32.sv 9 | - src/axi2apb_wrap.sv 10 | file_type : systemVerilogSource 11 | depend: 12 | - ">=pulp-platform.org::apb:0.1.0" 13 | - ">=pulp-platform.org::axi:0.4.5" 14 | - pulp-platform.org::axi_slice 15 | 16 | targets : {default : {filesets : [rtl]}} 17 | 18 | provider: 19 | name : github 20 | user : pulp-platform 21 | repo : axi2apb 22 | version : be292ade4f3c027a065e63e85bd7c1927b4a676f 23 | -------------------------------------------------------------------------------- /pulp-platform.org/axi_mem_if-0.2.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : pulp-platform.org::axi_mem_if:0.2.0 3 | 4 | filesets: 5 | rtl: 6 | files: [src/axi2mem.sv : {file_type : systemVerilogSource}] 7 | depend : [">=pulp-platform.org::axi:0.4.3"] 8 | 9 | targets: 10 | default: 11 | filesets : [rtl] 12 | 13 | provider: 14 | name : github 15 | user : pulp-platform 16 | repo : axi_mem_if 17 | version : v0.2.0 18 | -------------------------------------------------------------------------------- /pulp-platform.org/axi_slice-1.1.3-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: pulp-platform.org::axi_slice:1.1.3-r1 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - src/axi_single_slice.sv 9 | - src/axi_ar_buffer.sv 10 | - src/axi_aw_buffer.sv 11 | - src/axi_b_buffer.sv 12 | - src/axi_r_buffer.sv 13 | - src/axi_slice.sv 14 | - src/axi_w_buffer.sv 15 | - src/axi_slice_wrap.sv 16 | file_type : systemVerilogSource 17 | depend : [">=pulp-platform.org::common_cells:1.7.4"] 18 | 19 | targets: 20 | default: 21 | filesets : [rtl] 22 | 23 | provider: 24 | name : github 25 | user : pulp-platform 26 | repo : axi_slice 27 | version : aae8ca49dcfbfa8e44e1938a2e4a768db83006cb 28 | -------------------------------------------------------------------------------- /pulp-platform.org/axi_slice_dc-1.1.1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: pulp-platform.org::axi_slice_dc:1.1.1 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - src/axi_slice_dc_master.sv 9 | - src/axi_slice_dc_slave.sv 10 | - src/dc_data_buffer.sv 11 | - src/dc_full_detector.v 12 | - src/dc_synchronizer.v 13 | - src/dc_token_ring_fifo_din.v 14 | - src/dc_token_ring_fifo_dout.v 15 | - src/dc_token_ring.v 16 | - src/axi_slice_dc_master_wrap.sv 17 | - src/axi_slice_dc_slave_wrap.sv 18 | - src/axi_cdc.sv 19 | file_type : systemVerilogSource 20 | depend : 21 | - ">=pulp-platform.org::axi:0.4.3" 22 | - ">=pulp-platform.org::axi_slice:1.1.3" 23 | 24 | targets: 25 | default: 26 | filesets : [rtl] 27 | 28 | provider: 29 | name : github 30 | user : pulp-platform 31 | repo : axi_slice_dc 32 | version : v1.1.1 33 | -------------------------------------------------------------------------------- /pulp-platform.org/common_cells-1.11.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::common_cells:1.11.0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - src/fifo_v1.sv 9 | - src/fifo_v2.sv 10 | - src/fifo_v3.sv 11 | - src/lfsr_8bit.sv 12 | - src/lfsr_16bit.sv 13 | - src/spill_register.sv 14 | - src/stream_register.sv 15 | - src/stream_mux.sv 16 | - src/stream_demux.sv 17 | - src/cdc_2phase.sv 18 | - src/cdc_fifo_2phase.sv 19 | - src/cdc_fifo_gray.sv 20 | - src/onehot_to_bin.sv 21 | - src/rstgen.sv 22 | - src/rstgen_bypass.sv 23 | - src/edge_propagator_tx.sv 24 | - src/edge_propagator_rx.sv 25 | - src/edge_propagator.sv 26 | - src/lzc.sv 27 | - src/rrarbiter.sv 28 | - src/stream_arbiter_flushable.sv 29 | - src/stream_arbiter.sv 30 | - src/sync_wedge.sv 31 | - src/sync.sv 32 | - src/graycode.sv 33 | - src/clk_div.sv 34 | - src/edge_detect.sv 35 | - src/serial_deglitch.sv 36 | - src/counter.sv 37 | - src/mv_filter.sv 38 | file_type : systemVerilogSource 39 | 40 | cdc_2phase_tb: 41 | files: [test/cdc_2phase_tb.sv : {file_type : verilogSource}] 42 | 43 | cdc_fifo_tb: 44 | files: [test/cdc_fifo_tb.sv : {file_type : verilogSource}] 45 | 46 | targets: 47 | default: 48 | filesets : [rtl] 49 | 50 | cdc_2phase_tb: 51 | default_tool: modelsim 52 | filesets: [rtl, cdc_2phase_tb] 53 | toplevel : cdc_2phase_tb 54 | 55 | cdc_fifo_tb: 56 | default_tool: modelsim 57 | filesets: [rtl, cdc_fifo_tb] 58 | toplevel : cdc_fifo_tb 59 | 60 | provider: 61 | name : github 62 | user : pulp-platform 63 | repo : common_cells 64 | version : v1.11.0 65 | -------------------------------------------------------------------------------- /pulp-platform.org/common_cells-1.16.4.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::common_cells:1.16.4 4 | 5 | filesets: 6 | includes: 7 | files: 8 | #Ugly workaround 9 | - include/dummy : {is_include_file : true} 10 | 11 | - include/common_cells/registers.svh : {file_type : user} 12 | file_type : systemVerilogSource 13 | 14 | rtl: 15 | files: 16 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this package. 17 | # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0, 18 | # etc. Files within a level are ordered alphabetically. 19 | # Level 0 20 | - src/addr_decode.sv 21 | - src/cdc_2phase.sv 22 | - src/cf_math_pkg.sv 23 | - src/clk_div.sv 24 | - src/delta_counter.sv 25 | - src/edge_propagator_tx.sv 26 | - src/exp_backoff.sv 27 | - src/fifo_v3.sv 28 | - src/graycode.sv 29 | - src/lfsr.sv 30 | - src/lfsr_16bit.sv 31 | - src/lfsr_8bit.sv 32 | - src/lzc.sv 33 | - src/mv_filter.sv 34 | - src/onehot_to_bin.sv 35 | - src/plru_tree.sv 36 | - src/popcount.sv 37 | - src/rr_arb_tree.sv 38 | - src/rstgen_bypass.sv 39 | - src/serial_deglitch.sv 40 | - src/shift_reg.sv 41 | - src/spill_register.sv 42 | - src/stream_demux.sv 43 | - src/stream_filter.sv 44 | - src/stream_fork.sv 45 | - src/stream_mux.sv 46 | - src/sub_per_hash.sv 47 | - src/sync.sv 48 | - src/sync_wedge.sv 49 | - src/unread.sv 50 | # Level 1 51 | - src/cb_filter.sv 52 | - src/cdc_fifo_2phase.sv 53 | - src/cdc_fifo_gray.sv 54 | - src/counter.sv 55 | - src/edge_detect.sv 56 | - src/id_queue.sv 57 | - src/max_counter.sv 58 | - src/rstgen.sv 59 | - src/stream_delay.sv 60 | # Level 2 61 | - src/fall_through_register.sv 62 | - src/stream_arbiter_flushable.sv 63 | - src/stream_register.sv 64 | # Level 3 65 | - src/stream_arbiter.sv 66 | file_type : systemVerilogSource 67 | 68 | deprecated: 69 | files: 70 | # Deprecated modules 71 | # Level 0 72 | - src/deprecated/clock_divider_counter.sv 73 | - src/deprecated/find_first_one.sv 74 | - src/deprecated/generic_LFSR_8bit.sv 75 | - src/deprecated/generic_fifo.sv 76 | - src/deprecated/prioarbiter.sv 77 | - src/deprecated/pulp_sync.sv 78 | - src/deprecated/pulp_sync_wedge.sv 79 | - src/deprecated/rrarbiter.sv 80 | # Level 1 81 | - src/deprecated/clock_divider.sv 82 | - src/deprecated/fifo_v2.sv 83 | # Level 2 84 | - src/deprecated/fifo_v1.sv 85 | 86 | # Depend on deprecated modules 87 | - src/edge_propagator.sv 88 | - src/edge_propagator_rx.sv 89 | file_type : systemVerilogSource 90 | 91 | targets: 92 | default: 93 | filesets : [includes, rtl, deprecated] 94 | 95 | provider: 96 | name : github 97 | user : pulp-platform 98 | repo : common_cells 99 | version : v1.16.4 100 | -------------------------------------------------------------------------------- /pulp-platform.org/common_cells-1.20.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : pulp-platform.org::common_cells:1.20.0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - include/common_cells/registers.svh : {is_include_file : true, include_path : include} 9 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this package. 10 | # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0, 11 | # etc. Files within a level are ordered alphabetically. 12 | # Level 0 13 | - src/binary_to_gray.sv 14 | - src/cb_filter_pkg.sv 15 | - src/cdc_2phase.sv 16 | - src/cf_math_pkg.sv 17 | - src/clk_div.sv 18 | - src/delta_counter.sv 19 | - src/ecc_pkg.sv 20 | - src/edge_propagator_tx.sv 21 | - src/exp_backoff.sv 22 | - src/fifo_v3.sv 23 | - src/gray_to_binary.sv 24 | - src/isochronous_spill_register.sv 25 | - src/lfsr.sv 26 | - src/lfsr_16bit.sv 27 | - src/lfsr_8bit.sv 28 | - src/mv_filter.sv 29 | - src/onehot_to_bin.sv 30 | - src/plru_tree.sv 31 | - src/popcount.sv 32 | - src/rr_arb_tree.sv 33 | - src/rstgen_bypass.sv 34 | - src/serial_deglitch.sv 35 | - src/shift_reg.sv 36 | - src/spill_register.sv 37 | - src/stream_demux.sv 38 | - src/stream_filter.sv 39 | - src/stream_fork.sv 40 | - src/stream_intf.sv 41 | - src/stream_join.sv 42 | - src/stream_mux.sv 43 | - src/sub_per_hash.sv 44 | - src/sync.sv 45 | - src/sync_wedge.sv 46 | - src/unread.sv 47 | # Level 1 48 | - src/addr_decode.sv 49 | - src/cb_filter.sv 50 | - src/cdc_fifo_2phase.sv 51 | - src/cdc_fifo_gray.sv 52 | - src/counter.sv 53 | - src/ecc_decode.sv 54 | - src/ecc_encode.sv 55 | - src/edge_detect.sv 56 | - src/lzc.sv 57 | - src/max_counter.sv 58 | - src/rstgen.sv 59 | - src/stream_delay.sv 60 | - src/stream_fifo.sv 61 | - src/stream_fork_dynamic.sv 62 | - src/stream_xbar.sv 63 | # Level 2 64 | - src/fall_through_register.sv 65 | - src/id_queue.sv 66 | - src/stream_to_mem.sv 67 | - src/stream_arbiter_flushable.sv 68 | - src/stream_omega_net.sv 69 | - src/stream_register.sv 70 | # Level 3 71 | - src/stream_arbiter.sv 72 | file_type : systemVerilogSource 73 | 74 | deprecated: 75 | files: 76 | # Deprecated modules 77 | # Level 0 78 | - src/deprecated/clock_divider_counter.sv 79 | - src/deprecated/find_first_one.sv 80 | - src/deprecated/generic_LFSR_8bit.sv 81 | - src/deprecated/generic_fifo.sv 82 | - src/deprecated/prioarbiter.sv 83 | - src/deprecated/pulp_sync.sv 84 | - src/deprecated/pulp_sync_wedge.sv 85 | - src/deprecated/rrarbiter.sv 86 | # Level 1 87 | - src/deprecated/clock_divider.sv 88 | - src/deprecated/fifo_v2.sv 89 | # Level 2 90 | - src/deprecated/fifo_v1.sv 91 | 92 | # Depend on deprecated modules 93 | - src/edge_propagator.sv 94 | - src/edge_propagator_rx.sv 95 | file_type : systemVerilogSource 96 | 97 | targets: 98 | default: 99 | filesets : [rtl, deprecated] 100 | 101 | provider: 102 | name : github 103 | user : pulp-platform 104 | repo : common_cells 105 | version : f5f9a9d0e68b95dce01374a7416758b039e8709e 106 | 107 | -------------------------------------------------------------------------------- /pulp-platform.org/include/dummy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/fusesoc-cores/78d69702c5358ea2b87381a1ec3c7099f27e514a/pulp-platform.org/include/dummy -------------------------------------------------------------------------------- /serv/serv-1.0.0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serv:1.0.0-r1 4 | 5 | filesets: 6 | core: 7 | files: 8 | - rtl/serv_params.vh : {is_include_file : true} 9 | - rtl/shift_reg.v 10 | - rtl/ser_shift.v 11 | - rtl/serv_bufreg.v 12 | - rtl/serv_alu.v 13 | - rtl/serv_csr.v 14 | - rtl/serv_ctrl.v 15 | - rtl/serv_decode.v 16 | - rtl/serv_mem_if.v 17 | - rtl/serv_rf_if.v 18 | - rtl/serv_rf_ram_if.v 19 | - rtl/serv_rf_ram.v 20 | - rtl/serv_state.v 21 | - rtl/serv_top.v 22 | - rtl/serv_rf_top.v 23 | file_type : verilogSource 24 | 25 | targets: 26 | default: 27 | filesets : [core] 28 | parameters : [RISCV_FORMAL, SERV_CLEAR_RAM] 29 | toplevel : ["is_toplevel? (serv_rf_top)"] 30 | 31 | lint: 32 | default_tool : verilator 33 | filesets : [core] 34 | tools: 35 | verilator: 36 | mode : lint-only 37 | toplevel : serv_rf_top 38 | 39 | parameters: 40 | RISCV_FORMAL: 41 | datatype : bool 42 | paramtype : vlogdefine 43 | 44 | SERV_CLEAR_RAM: 45 | datatype : bool 46 | paramtype : vlogdefine 47 | 48 | provider: 49 | name : github 50 | user : olofk 51 | repo : serv 52 | version : 4f855602fac18c21385925c88737493d493dbfb2 53 | -------------------------------------------------------------------------------- /serv/serv-1.0.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serv:1.0.0 4 | 5 | filesets: 6 | core: 7 | files: 8 | - rtl/serv_params.vh : {is_include_file : true} 9 | - rtl/shift_reg.v 10 | - rtl/ser_shift.v 11 | - rtl/serv_bufreg.v 12 | - rtl/serv_alu.v 13 | - rtl/serv_csr.v 14 | - rtl/serv_ctrl.v 15 | - rtl/serv_decode.v 16 | - rtl/serv_mem_if.v 17 | - rtl/serv_rf_if.v 18 | - rtl/serv_rf_ram_if.v 19 | - rtl/serv_rf_ram.v 20 | - rtl/serv_state.v 21 | - rtl/serv_top.v 22 | - rtl/serv_rf_top.v 23 | file_type : verilogSource 24 | 25 | targets: 26 | default: 27 | filesets : [core] 28 | parameters : [RISCV_FORMAL, SERV_CLEAR_RAM] 29 | toplevel : ["is_toplevel? (serv_rf_top)"] 30 | 31 | lint: 32 | default_tool : verilator 33 | filesets : [core] 34 | tools: 35 | verilator: 36 | mode : lint-only 37 | toplevel : serv_rf_top 38 | 39 | parameters: 40 | RISCV_FORMAL: 41 | datatype : bool 42 | paramtype : vlogdefine 43 | 44 | SERV_CLEAR_RAM: 45 | datatype : bool 46 | paramtype : vlogdefine 47 | 48 | provider: 49 | name : github 50 | user : olofk 51 | repo : serv 52 | version : 1.0.0 53 | -------------------------------------------------------------------------------- /serv/serv-1.0.2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serv:1.0.2 4 | 5 | filesets: 6 | core: 7 | files: 8 | - rtl/serv_params.vh : {is_include_file : true} 9 | - rtl/serv_shift.v 10 | - rtl/serv_bufreg.v 11 | - rtl/serv_alu.v 12 | - rtl/serv_csr.v 13 | - rtl/serv_ctrl.v 14 | - rtl/serv_decode.v 15 | - rtl/serv_mem_if.v 16 | - rtl/serv_rf_if.v 17 | - rtl/serv_rf_ram_if.v 18 | - rtl/serv_rf_ram.v 19 | - rtl/serv_state.v 20 | - rtl/serv_top.v 21 | - rtl/serv_rf_top.v 22 | file_type : verilogSource 23 | 24 | targets: 25 | default: 26 | filesets : [core] 27 | parameters : [RISCV_FORMAL, SERV_CLEAR_RAM] 28 | toplevel : ["is_toplevel? (serv_rf_top)"] 29 | 30 | lint: 31 | default_tool : verilator 32 | filesets : [core] 33 | tools: 34 | verilator: 35 | mode : lint-only 36 | toplevel : serv_rf_top 37 | 38 | parameters: 39 | RISCV_FORMAL: 40 | datatype : bool 41 | paramtype : vlogdefine 42 | 43 | SERV_CLEAR_RAM: 44 | datatype : bool 45 | paramtype : vlogdefine 46 | 47 | provider: 48 | name : github 49 | user : olofk 50 | repo : serv 51 | version : 1.0.2 52 | -------------------------------------------------------------------------------- /serv/serv-1.1.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serv:1.1.0 4 | 5 | filesets: 6 | core: 7 | files: 8 | - "tool_verilator? (data/verilator_waiver.vlt)" : {file_type: vlt} 9 | - rtl/serv_bufreg.v 10 | - rtl/serv_alu.v 11 | - rtl/serv_csr.v 12 | - rtl/serv_ctrl.v 13 | - rtl/serv_decode.v 14 | - rtl/serv_immdec.v 15 | - rtl/serv_mem_if.v 16 | - rtl/serv_rf_if.v 17 | - rtl/serv_rf_ram_if.v 18 | - rtl/serv_rf_ram.v 19 | - rtl/serv_state.v 20 | - rtl/serv_top.v 21 | - rtl/serv_rf_top.v 22 | file_type : verilogSource 23 | 24 | targets: 25 | default: 26 | filesets : [core] 27 | parameters : 28 | - "is_toplevel? (PRE_REGISTER)" 29 | - "is_toplevel? (RESET_STRATEGY)" 30 | - RISCV_FORMAL 31 | - SERV_CLEAR_RAM 32 | - "is_toplevel? (WITH_CSR)" 33 | toplevel : ["is_toplevel? (serv_rf_top)"] 34 | 35 | lint: 36 | default_tool : verilator 37 | filesets : [core] 38 | tools: 39 | verilator: 40 | mode : lint-only 41 | verilator_options: 42 | - "-Wall" 43 | toplevel : serv_rf_top 44 | 45 | parameters: 46 | PRE_REGISTER: 47 | datatype : int 48 | description : Register signals before or after the decoder 49 | paramtype : vlogparam 50 | 51 | RESET_STRATEGY: 52 | datatype : str 53 | paramtype : vlogparam 54 | 55 | RISCV_FORMAL: 56 | datatype : bool 57 | paramtype : vlogdefine 58 | 59 | SERV_CLEAR_RAM: 60 | datatype : bool 61 | paramtype : vlogdefine 62 | 63 | WITH_CSR: 64 | datatype : int 65 | paramtype : vlogparam 66 | 67 | provider: 68 | name : github 69 | user : olofk 70 | repo : serv 71 | version : 1.1.0 72 | -------------------------------------------------------------------------------- /serv/servant-1.0.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::servant:1.0.0 4 | 5 | filesets: 6 | service: 7 | files: [servant/ice40_pll.v, servant/service.v] 8 | file_type : verilogSource 9 | depend : ["fusesoc:utils:generators"] 10 | 11 | mem_files: 12 | files: 13 | - sw/blinky.hex : {copyto : blinky.hex} 14 | - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex} 15 | file_type : user 16 | 17 | servant_tb: 18 | files: 19 | - bench/servant_sim.v 20 | - "!tool_verilator? (bench/uart_decoder.v)" 21 | - "!tool_verilator? (bench/servant_tb.v)" 22 | - "tool_verilator? (bench/servant_tb.cpp)" : {file_type : cppSource} 23 | file_type : verilogSource 24 | depend : [vlog_tb_utils] 25 | 26 | soc: 27 | files: 28 | - servant/servant_clock_gen.v 29 | - servant/servant_timer.v 30 | - servant/servant_gpio.v 31 | - servant/servant_arbiter.v 32 | - servant/servant_mux.v 33 | - "tool_quartus? (servant/servant_ram_quartus.sv)" : {file_type : systemVerilogSource} 34 | - "!tool_quartus? (servant/servant_ram.v)" 35 | - servant/servant.v 36 | file_type : verilogSource 37 | depend : [serv] 38 | 39 | cyc1000: 40 | files: 41 | - data/cyc1000.sdc : {file_type : SDC} 42 | - data/cyc1000.tcl : {file_type : tclSource} 43 | - servant/servclone10_clock_gen.v : {file_type : verilogSource} 44 | - servant/servclone10.v : {file_type : verilogSource} 45 | 46 | tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]} 47 | icebreaker : {files: [data/icebreaker.pcf : {file_type : PCF}]} 48 | 49 | nexys_a7: 50 | files: 51 | - servant/servix_clock_gen.v : {file_type : verilogSource} 52 | - servant/servix.v : {file_type : verilogSource} 53 | - data/nexys_a7.xdc : {file_type : xdc} 54 | 55 | orangecrab: 56 | files: 57 | - servant/servcp5.v : {file_type : verilogSource} 58 | - data/orangecrab.pcf : {file_type : LPF} 59 | 60 | arty_a7_35t: 61 | files: 62 | - servant/servix_clock_gen.v : {file_type : verilogSource} 63 | - servant/servix.v : {file_type : verilogSource} 64 | - data/arty_a7_35t.xdc : {file_type : xdc} 65 | targets: 66 | default: 67 | filesets : [soc] 68 | 69 | cyc1000: 70 | default_tool: quartus 71 | description: cyc1000 FPGA board 72 | filesets : [mem_files, soc, cyc1000] 73 | parameters : [memfile, memsize=32768] 74 | tools: 75 | quartus: 76 | family : Cyclone 10 LP 77 | device : 10CL025YU256C8G 78 | toplevel : servclone10 79 | 80 | icebreaker: 81 | default_tool : icestorm 82 | filesets : [mem_files, soc, service, icebreaker] 83 | generate: [icebreaker_pll] 84 | parameters : [memfile, memsize, PLL=ICE40_PAD] 85 | tools: 86 | icestorm: 87 | nextpnr_options: [--up5k, --freq, 16] 88 | pnr: next 89 | toplevel : service 90 | 91 | tinyfpga_bx: 92 | default_tool : icestorm 93 | filesets : [mem_files, soc, service, tinyfpga_bx] 94 | generate: [tinyfpga_bx_pll] 95 | parameters : [memfile, memsize, PLL=ICE40_CORE] 96 | tools: 97 | icestorm: 98 | nextpnr_options : [--lp8k, --package, cm81, --freq, 32] 99 | pnr: next 100 | toplevel : service 101 | 102 | lint: 103 | default_tool : verilator 104 | filesets : [soc] 105 | tools: 106 | verilator: 107 | mode : lint-only 108 | toplevel : servant 109 | 110 | nexys_a7: 111 | default_tool: vivado 112 | filesets : [mem_files, soc, nexys_a7] 113 | parameters : [memfile, memsize, frequency=32] 114 | tools: 115 | vivado: {part : xc7a100tcsg324-1} 116 | toplevel : servix 117 | 118 | orangecrab: 119 | default_tool: trellis 120 | filesets : [mem_files, soc, orangecrab] 121 | parameters : [memfile, memsize] 122 | tools: 123 | trellis: 124 | nextpnr_options : [--25k, --package, CSFBGA285] 125 | toplevel: servcp5 126 | 127 | arty_a7_35t: 128 | default_tool: vivado 129 | filesets : [mem_files, soc, arty_a7_35t] 130 | parameters : [memfile, memsize, frequency=16] 131 | tools: 132 | vivado: {part : xc7a35ticsg324-1L} 133 | toplevel : servix 134 | 135 | sim: 136 | default_tool: icarus 137 | filesets : [soc, servant_tb] 138 | parameters : 139 | - RISCV_FORMAL 140 | - SERV_CLEAR_RAM=true 141 | - firmware 142 | - memsize 143 | toplevel : servant_tb 144 | 145 | verilator_tb: 146 | default_tool: verilator 147 | filesets : [soc, servant_tb] 148 | parameters : 149 | - RISCV_FORMAL 150 | - firmware 151 | - memsize 152 | - signature 153 | - timeout 154 | - uart_baudrate 155 | - vcd 156 | - vcd_start 157 | tools: 158 | verilator: 159 | verilator_options : [--trace] 160 | toplevel : servant_sim 161 | 162 | parameters: 163 | PLL: 164 | datatype : str 165 | description : PLL type to use for main clock generation 166 | paramtype : vlogparam 167 | 168 | RISCV_FORMAL: 169 | datatype : bool 170 | paramtype : vlogdefine 171 | 172 | SERV_CLEAR_RAM: 173 | datatype : bool 174 | paramtype : vlogdefine 175 | 176 | firmware: 177 | datatype : file 178 | description : Preload RAM with a hex file at runtime (overrides memfile) 179 | paramtype : plusarg 180 | 181 | frequency: 182 | datatype : int 183 | description : PLL output frequency 184 | paramtype : vlogparam 185 | 186 | memfile: 187 | datatype : file 188 | description : Preload RAM with a hex file at compile-time 189 | paramtype : vlogparam 190 | 191 | memsize: 192 | datatype : int 193 | default : 8192 194 | description : Memory size in bytes for RAM (default 8kiB) 195 | paramtype : vlogparam 196 | 197 | signature: 198 | datatype : file 199 | paramtype : plusarg 200 | uart_baudrate: 201 | datatype : int 202 | description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding) 203 | paramtype : plusarg 204 | 205 | timeout: 206 | datatype : int 207 | paramtype : plusarg 208 | 209 | vcd: 210 | datatype : bool 211 | paramtype : plusarg 212 | 213 | vcd_start: 214 | datatype : int 215 | description : Delay start of VCD dumping until the specified time 216 | paramtype : plusarg 217 | 218 | generate: 219 | icebreaker_pll: 220 | generator: icepll 221 | parameters: 222 | freq_out : 16 223 | 224 | tinyfpga_bx_pll: 225 | generator: icepll 226 | parameters: 227 | freq_in : 16 228 | freq_out : 32 229 | 230 | provider: 231 | name : github 232 | user : olofk 233 | repo : serv 234 | version : 1.0.0 235 | -------------------------------------------------------------------------------- /serv/servant-1.0.2-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::servant:1.0.2-r1 4 | 5 | filesets: 6 | service: 7 | files: [servant/ice40_pll.v, servant/service.v] 8 | file_type : verilogSource 9 | depend : ["fusesoc:utils:generators"] 10 | 11 | mem_files: 12 | files: 13 | - sw/blinky.hex : {copyto : blinky.hex} 14 | - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex} 15 | file_type : user 16 | 17 | servant_tb: 18 | files: 19 | - bench/servant_sim.v 20 | - "!tool_verilator? (bench/uart_decoder.v)" 21 | - "!tool_verilator? (bench/servant_tb.v)" 22 | - "tool_verilator? (bench/servant_tb.cpp)" : {file_type : cppSource} 23 | file_type : verilogSource 24 | depend : [vlog_tb_utils] 25 | 26 | soc: 27 | files: 28 | - servant/servant_clock_gen.v 29 | - servant/servant_timer.v 30 | - servant/servant_gpio.v 31 | - servant/servant_arbiter.v 32 | - servant/servant_mux.v 33 | - "tool_quartus? (servant/servant_ram_quartus.sv)" : {file_type : systemVerilogSource} 34 | - "!tool_quartus? (servant/servant_ram.v)" 35 | - servant/servant.v 36 | file_type : verilogSource 37 | depend : [serv] 38 | 39 | cyc1000: 40 | files: 41 | - data/cyc1000.sdc : {file_type : SDC} 42 | - data/cyc1000.tcl : {file_type : tclSource} 43 | - servant/servclone10_clock_gen.v : {file_type : verilogSource} 44 | - servant/servclone10.v : {file_type : verilogSource} 45 | 46 | tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]} 47 | icebreaker : {files: [data/icebreaker.pcf : {file_type : PCF}]} 48 | alhambra : {files: [data/alhambra.pcf : {file_type : PCF}]} 49 | 50 | lx9_microboard: 51 | files: 52 | - servant/servant_lx9_clock_gen.v : {file_type : verilogSource} 53 | - servant/servant_lx9.v : {file_type : verilogSource} 54 | - data/lx9_microboard.ucf : {file_type : UCF} 55 | 56 | nexys_a7: 57 | files: 58 | - servant/servix_clock_gen.v : {file_type : verilogSource} 59 | - servant/servix.v : {file_type : verilogSource} 60 | - data/nexys_a7.xdc : {file_type : xdc} 61 | arty_a7_35t: 62 | files: 63 | - servant/servix_clock_gen.v : {file_type : verilogSource} 64 | - servant/servix.v : {file_type : verilogSource} 65 | - data/arty_a7_35t.xdc : {file_type : xdc} 66 | 67 | pipistrello: 68 | files: 69 | - servant/servis_clock_gen.v : {file_type : verilogSource} 70 | - servant/servis.v : {file_type : verilogSource} 71 | - data/pipistrello.ucf : {file_type : UCF} 72 | 73 | ulx3s: 74 | files: 75 | - data/ulx3s.lpf : {file_type : LPF} 76 | - servant/ecppll.v : {file_type : verilogSource} 77 | - servant/servant_ecp5_clock_gen.v : {file_type : verilogSource} 78 | - servant/servant_ecp5.v : {file_type : verilogSource} 79 | 80 | upduino2: 81 | files: 82 | - servant/servant_upduino2.v : {file_type : verilogSource} 83 | - data/upduino2.pcf : {file_type : PCF} 84 | 85 | zcu106: 86 | files: 87 | - servant/servus_clock_gen.v : {file_type : verilogSource} 88 | - servant/servus.v : {file_type : verilogSource} 89 | - data/zcu106.xdc : {file_type : xdc} 90 | 91 | targets: 92 | default: 93 | filesets : [soc] 94 | 95 | cyc1000: 96 | default_tool: quartus 97 | description: cyc1000 FPGA board 98 | filesets : [mem_files, soc, cyc1000] 99 | parameters : [memfile, memsize=32768] 100 | tools: 101 | quartus: 102 | family : Cyclone 10 LP 103 | device : 10CL025YU256C8G 104 | toplevel : servclone10 105 | 106 | icebreaker: 107 | default_tool : icestorm 108 | filesets : [mem_files, soc, service, icebreaker] 109 | generate: [icebreaker_pll] 110 | parameters : [memfile, memsize, PLL=ICE40_PAD] 111 | tools: 112 | icestorm: 113 | nextpnr_options: [--up5k, --freq, 16] 114 | pnr: next 115 | toplevel : service 116 | 117 | lx9_microboard: 118 | default_tool: ise 119 | description : LX9 Microboard 120 | filesets : [mem_files, soc, lx9_microboard] 121 | parameters : [memfile, memsize] 122 | tools: 123 | ise: 124 | family : Spartan6 125 | device : xc6slx9 126 | package : csg324 127 | speed : -2 128 | toplevel : servant_lx9 129 | 130 | 131 | tinyfpga_bx: 132 | default_tool : icestorm 133 | filesets : [mem_files, soc, service, tinyfpga_bx] 134 | generate: [tinyfpga_bx_pll] 135 | parameters : [memfile, memsize, PLL=ICE40_CORE] 136 | tools: 137 | icestorm: 138 | nextpnr_options : [--lp8k, --package, cm81, --freq, 32] 139 | pnr: next 140 | toplevel : service 141 | 142 | alhambra: 143 | default_tool : icestorm 144 | description: Open-hardware iCE40HX4K FPGA board 145 | filesets : [mem_files, soc, service, alhambra] 146 | generate: [alhambra_pll] 147 | parameters : [memfile, memsize, PLL=ICE40_CORE] 148 | tools: 149 | icestorm: 150 | nextpnr_options : [--hx8k, --package, "tq144:4k", --freq, 32] 151 | pnr: next 152 | toplevel : service 153 | 154 | lint: 155 | default_tool : verilator 156 | filesets : [soc] 157 | tools: 158 | verilator: 159 | mode : lint-only 160 | toplevel : servant 161 | 162 | nexys_a7: 163 | default_tool: vivado 164 | filesets : [mem_files, soc, nexys_a7] 165 | parameters : [memfile, memsize, frequency=32] 166 | tools: 167 | vivado: {part : xc7a100tcsg324-1} 168 | toplevel : servix 169 | 170 | arty_a7_35t: 171 | default_tool: vivado 172 | filesets : [mem_files, soc, arty_a7_35t] 173 | parameters : [memfile, memsize, frequency=16] 174 | tools: 175 | vivado: {part : xc7a35ticsg324-1L} 176 | toplevel : servix 177 | 178 | pipistrello: 179 | default_tool: ise 180 | description : Saanlima pipistrello 181 | filesets : [mem_files, soc, pipistrello] 182 | parameters : [memfile, memsize] 183 | tools: 184 | ise: 185 | family : Spartan6 186 | device : xc6slx45 187 | package : csg324 188 | speed : -3 189 | toplevel : servis 190 | 191 | sim: 192 | default_tool: icarus 193 | filesets : [soc, servant_tb] 194 | parameters : 195 | - RISCV_FORMAL 196 | - SERV_CLEAR_RAM=true 197 | - firmware 198 | - memsize 199 | toplevel : servant_tb 200 | 201 | ulx3s_85: 202 | default_tool: diamond 203 | description : ULX3S 85k version 204 | filesets : [mem_files, soc, ulx3s] 205 | parameters : [memfile, memsize] 206 | tools: 207 | diamond: 208 | part : LFE5U-85F-6BG381C 209 | trellis: 210 | nextpnr_options : [--package, CABGA381, --85k] 211 | toplevel: servant_ecp5 212 | 213 | upduino2: 214 | default_tool : icestorm 215 | filesets : [mem_files, soc, upduino2] 216 | parameters : [memfile, memsize] 217 | tools: 218 | icestorm: 219 | nextpnr_options: [--package, sg48, --up5k, --freq, 24] 220 | pnr: next 221 | toplevel : servant_upduino2 222 | 223 | verilator_tb: 224 | default_tool: verilator 225 | filesets : [soc, servant_tb] 226 | parameters : 227 | - RISCV_FORMAL 228 | - firmware 229 | - memsize 230 | - signature 231 | - timeout 232 | - uart_baudrate 233 | - vcd 234 | - vcd_start 235 | tools: 236 | verilator: 237 | verilator_options : [--trace] 238 | toplevel : servant_sim 239 | 240 | zcu106: 241 | default_tool: vivado 242 | description : Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit 243 | filesets : [mem_files, soc, zcu106] 244 | parameters : [memfile, memsize] 245 | tools: 246 | vivado: {part : xczu7ev-ffvc1156-2-e} 247 | toplevel : servus 248 | 249 | parameters: 250 | PLL: 251 | datatype : str 252 | description : PLL type to use for main clock generation 253 | paramtype : vlogparam 254 | 255 | RISCV_FORMAL: 256 | datatype : bool 257 | paramtype : vlogdefine 258 | 259 | SERV_CLEAR_RAM: 260 | datatype : bool 261 | paramtype : vlogdefine 262 | 263 | firmware: 264 | datatype : file 265 | description : Preload RAM with a hex file at runtime (overrides memfile) 266 | paramtype : plusarg 267 | 268 | frequency: 269 | datatype : int 270 | description : PLL output frequency 271 | paramtype : vlogparam 272 | 273 | memfile: 274 | datatype : file 275 | description : Preload RAM with a hex file at compile-time 276 | paramtype : vlogparam 277 | 278 | memsize: 279 | datatype : int 280 | default : 8192 281 | description : Memory size in bytes for RAM (default 8kiB) 282 | paramtype : vlogparam 283 | 284 | signature: 285 | datatype : file 286 | paramtype : plusarg 287 | uart_baudrate: 288 | datatype : int 289 | description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding) 290 | paramtype : plusarg 291 | 292 | timeout: 293 | datatype : int 294 | paramtype : plusarg 295 | 296 | vcd: 297 | datatype : bool 298 | paramtype : plusarg 299 | 300 | vcd_start: 301 | datatype : int 302 | description : Delay start of VCD dumping until the specified time 303 | paramtype : plusarg 304 | 305 | generate: 306 | icebreaker_pll: 307 | generator: icepll 308 | parameters: 309 | freq_out : 16 310 | 311 | tinyfpga_bx_pll: 312 | generator: icepll 313 | parameters: 314 | freq_in : 16 315 | freq_out : 32 316 | 317 | alhambra_pll: 318 | generator: icepll 319 | parameters: 320 | freq_in : 12 321 | freq_out : 32 322 | 323 | provider: 324 | name : github 325 | user : olofk 326 | repo : serv 327 | version : 14cbe03a61c28959fd0d334c39ad7f65c1f2eee4 328 | -------------------------------------------------------------------------------- /serv/servant-1.0.2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::servant:1.0.2 4 | 5 | filesets: 6 | service: 7 | files: [servant/ice40_pll.v, servant/service.v] 8 | file_type : verilogSource 9 | depend : ["fusesoc:utils:generators"] 10 | 11 | mem_files: 12 | files: 13 | - sw/blinky.hex : {copyto : blinky.hex} 14 | - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex} 15 | file_type : user 16 | 17 | servant_tb: 18 | files: 19 | - bench/servant_sim.v 20 | - "!tool_verilator? (bench/uart_decoder.v)" 21 | - "!tool_verilator? (bench/servant_tb.v)" 22 | - "tool_verilator? (bench/servant_tb.cpp)" : {file_type : cppSource} 23 | file_type : verilogSource 24 | depend : [vlog_tb_utils] 25 | 26 | soc: 27 | files: 28 | - servant/servant_clock_gen.v 29 | - servant/servant_timer.v 30 | - servant/servant_gpio.v 31 | - servant/servant_arbiter.v 32 | - servant/servant_mux.v 33 | - "tool_quartus? (servant/servant_ram_quartus.sv)" : {file_type : systemVerilogSource} 34 | - "!tool_quartus? (servant/servant_ram.v)" 35 | - servant/servant.v 36 | file_type : verilogSource 37 | depend : [serv] 38 | 39 | cyc1000: 40 | files: 41 | - data/cyc1000.sdc : {file_type : SDC} 42 | - data/cyc1000.tcl : {file_type : tclSource} 43 | - servant/servclone10_clock_gen.v : {file_type : verilogSource} 44 | - servant/servclone10.v : {file_type : verilogSource} 45 | 46 | tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]} 47 | icebreaker : {files: [data/icebreaker.pcf : {file_type : PCF}]} 48 | alhambra : {files: [data/alhambra.pcf : {file_type : PCF}]} 49 | 50 | lx9_microboard: 51 | files: 52 | - servant/servant_lx9_clock_gen.v : {file_type : verilogSource} 53 | - servant/servant_lx9.v : {file_type : verilogSource} 54 | - data/lx9_microboard.ucf : {file_type : UCF} 55 | 56 | nexys_a7: 57 | files: 58 | - servant/servix_clock_gen.v : {file_type : verilogSource} 59 | - servant/servix.v : {file_type : verilogSource} 60 | - data/nexys_a7.xdc : {file_type : xdc} 61 | arty_a7_35t: 62 | files: 63 | - servant/servix_clock_gen.v : {file_type : verilogSource} 64 | - servant/servix.v : {file_type : verilogSource} 65 | - data/arty_a7_35t.xdc : {file_type : xdc} 66 | 67 | pipistrello: 68 | files: 69 | - servant/servis_clock_gen.v : {file_type : verilogSource} 70 | - servant/servis.v : {file_type : verilogSource} 71 | - data/pipistrello.ucf : {file_type : UCF} 72 | 73 | ulx3s: 74 | files: 75 | - data/ulx3s.lpf : {file_type : LPF} 76 | - servant/ecppll.v : {file_type : verilogSource} 77 | - servant/servant_ecp5_clock_gen.v : {file_type : verilogSource} 78 | - servant/servant_ecp5.v : {file_type : verilogSource} 79 | 80 | upduino2: 81 | files: 82 | - servant/servant_upduino2.v : {file_type : verilogSource} 83 | - data/upduino2.pcf : {file_type : PCF} 84 | 85 | zcu106: 86 | files: 87 | - servant/servus_clock_gen.v : {file_type : verilogSource} 88 | - servant/servus.v : {file_type : verilogSource} 89 | - data/zcu106.xdc : {file_type : xdc} 90 | 91 | targets: 92 | default: 93 | filesets : [soc] 94 | 95 | cyc1000: 96 | default_tool: quartus 97 | description: cyc1000 FPGA board 98 | filesets : [mem_files, soc, cyc1000] 99 | parameters : [memfile, memsize=32768] 100 | tools: 101 | quartus: 102 | family : Cyclone 10 LP 103 | device : 10CL025YU256C8G 104 | toplevel : servclone10 105 | 106 | icebreaker: 107 | default_tool : icestorm 108 | filesets : [mem_files, soc, service, icebreaker] 109 | generate: [icebreaker_pll] 110 | parameters : [memfile, memsize, PLL=ICE40_PAD] 111 | tools: 112 | icestorm: 113 | nextpnr_options: [--up5k, --freq, 16] 114 | pnr: next 115 | toplevel : service 116 | 117 | lx9_microboard: 118 | default_tool: ise 119 | description : LX9 Microboard 120 | filesets : [mem_files, soc, lx9_microboard] 121 | parameters : [memfile, memsize] 122 | tools: 123 | ise: 124 | family : Spartan6 125 | device : xc6slx9 126 | package : csg324 127 | speed : -2 128 | toplevel : servant_lx9 129 | 130 | 131 | tinyfpga_bx: 132 | default_tool : icestorm 133 | filesets : [mem_files, soc, service, tinyfpga_bx] 134 | generate: [tinyfpga_bx_pll] 135 | parameters : [memfile, memsize, PLL=ICE40_CORE] 136 | tools: 137 | icestorm: 138 | nextpnr_options : [--lp8k, --package, cm81, --freq, 32] 139 | pnr: next 140 | toplevel : service 141 | 142 | alhambra: 143 | default_tool : icestorm 144 | description: Open-hardware iCE40HX4K FPGA board 145 | filesets : [mem_files, soc, service, alhambra] 146 | generate: [alhambra_pll] 147 | parameters : [memfile, memsize, PLL=ICE40_CORE] 148 | tools: 149 | icestorm: 150 | nextpnr_options : [--hx8k, --package, "tq144:4k", --freq, 32] 151 | pnr: next 152 | toplevel : service 153 | 154 | lint: 155 | default_tool : verilator 156 | filesets : [soc] 157 | tools: 158 | verilator: 159 | mode : lint-only 160 | toplevel : servant 161 | 162 | nexys_a7: 163 | default_tool: vivado 164 | filesets : [mem_files, soc, nexys_a7] 165 | parameters : [memfile, memsize, frequency=32] 166 | tools: 167 | vivado: {part : xc7a100tcsg324-1} 168 | toplevel : servix 169 | 170 | arty_a7_35t: 171 | default_tool: vivado 172 | filesets : [mem_files, soc, arty_a7_35t] 173 | parameters : [memfile, memsize, frequency=16] 174 | tools: 175 | vivado: {part : xc7a35ticsg324-1L} 176 | toplevel : servix 177 | 178 | pipistrello: 179 | default_tool: ise 180 | description : Saanlima pipistrello 181 | filesets : [mem_files, soc, pipistrello] 182 | parameters : [memfile, memsize] 183 | tools: 184 | ise: 185 | family : Spartan6 186 | device : xc6slx45 187 | package : csg324 188 | speed : -3 189 | toplevel : servis 190 | 191 | sim: 192 | default_tool: icarus 193 | filesets : [soc, servant_tb] 194 | parameters : 195 | - RISCV_FORMAL 196 | - SERV_CLEAR_RAM=true 197 | - firmware 198 | - memsize 199 | toplevel : servant_tb 200 | 201 | ulx3s_85: 202 | default_tool: diamond 203 | description : ULX3S 85k version 204 | filesets : [mem_files, soc, ulx3s] 205 | parameters : [memfile, memsize] 206 | tools: 207 | diamond: 208 | part : LFE5U-85F-6BG381C 209 | trellis: 210 | nextpnr_options : [--package, CABGA381, --85k] 211 | toplevel: servant_ecp5 212 | 213 | upduino2: 214 | default_tool : icestorm 215 | filesets : [mem_files, soc, upduino2] 216 | parameters : [memfile, memsize] 217 | tools: 218 | icestorm: 219 | nextpnr_options: [--package, sg48, --up5k, --freq, 24] 220 | pnr: next 221 | toplevel : servant_upduino2 222 | 223 | verilator_tb: 224 | default_tool: verilator 225 | filesets : [soc, servant_tb] 226 | parameters : 227 | - RISCV_FORMAL 228 | - firmware 229 | - memsize 230 | - signature 231 | - timeout 232 | - uart_baudrate 233 | - vcd 234 | - vcd_start 235 | tools: 236 | verilator: 237 | verilator_options : [--trace] 238 | toplevel : servant_sim 239 | 240 | zcu106: 241 | default_tool: vivado 242 | description : Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit 243 | filesets : [mem_files, soc, zcu106] 244 | parameters : [memfile, memsize] 245 | tools: 246 | vivado: {part : xczu7ev-ffvc1156-2-e} 247 | toplevel : servus 248 | 249 | parameters: 250 | PLL: 251 | datatype : str 252 | description : PLL type to use for main clock generation 253 | paramtype : vlogparam 254 | 255 | RISCV_FORMAL: 256 | datatype : bool 257 | paramtype : vlogdefine 258 | 259 | SERV_CLEAR_RAM: 260 | datatype : bool 261 | paramtype : vlogdefine 262 | 263 | firmware: 264 | datatype : file 265 | description : Preload RAM with a hex file at runtime (overrides memfile) 266 | paramtype : plusarg 267 | 268 | frequency: 269 | datatype : int 270 | description : PLL output frequency 271 | paramtype : vlogparam 272 | 273 | memfile: 274 | datatype : file 275 | description : Preload RAM with a hex file at compile-time 276 | paramtype : vlogparam 277 | 278 | memsize: 279 | datatype : int 280 | default : 8192 281 | description : Memory size in bytes for RAM (default 8kiB) 282 | paramtype : vlogparam 283 | 284 | signature: 285 | datatype : file 286 | paramtype : plusarg 287 | uart_baudrate: 288 | datatype : int 289 | description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding) 290 | paramtype : plusarg 291 | 292 | timeout: 293 | datatype : int 294 | paramtype : plusarg 295 | 296 | vcd: 297 | datatype : bool 298 | paramtype : plusarg 299 | 300 | vcd_start: 301 | datatype : int 302 | description : Delay start of VCD dumping until the specified time 303 | paramtype : plusarg 304 | 305 | generate: 306 | icebreaker_pll: 307 | generator: icepll 308 | parameters: 309 | freq_out : 16 310 | 311 | tinyfpga_bx_pll: 312 | generator: icepll 313 | parameters: 314 | freq_in : 16 315 | freq_out : 32 316 | 317 | alhambra_pll: 318 | generator: icepll 319 | parameters: 320 | freq_in : 12 321 | freq_out : 32 322 | 323 | provider: 324 | name : github 325 | user : olofk 326 | repo : serv 327 | version : 1.0.2 328 | -------------------------------------------------------------------------------- /serv/serving-0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serving:0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - serving/serving_arbiter.v 9 | - serving/serving_mux.v 10 | - serving/serving_ram.v 11 | - serving/serving.v 12 | file_type : verilogSource 13 | depend : [serv] 14 | 15 | targets: 16 | default: 17 | filesets : [rtl] 18 | 19 | lint: 20 | default_tool : verilator 21 | filesets : [rtl] 22 | tools: 23 | verilator: 24 | mode : lint-only 25 | toplevel : serving 26 | 27 | provider: 28 | name : github 29 | user : olofk 30 | repo : serv 31 | version : 4f855602fac18c21385925c88737493d493dbfb2 32 | -------------------------------------------------------------------------------- /serv/serving-1.0.2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serving:1.0.2 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - serving/serving_arbiter.v 9 | - serving/serving_mux.v 10 | - serving/serving_ram.v 11 | - serving/serving.v 12 | file_type : verilogSource 13 | depend : [serv] 14 | 15 | targets: 16 | default: 17 | filesets : [rtl] 18 | 19 | lint: 20 | default_tool : verilator 21 | filesets : [rtl] 22 | tools: 23 | verilator: 24 | mode : lint-only 25 | toplevel : serving 26 | 27 | provider: 28 | name : github 29 | user : olofk 30 | repo : serv 31 | version : 1.0.2 32 | -------------------------------------------------------------------------------- /serv/serving-1.1.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::serving:1.1.0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - serving/serving_arbiter.v 9 | - serving/serving_mux.v 10 | - serving/serving_ram.v 11 | - serving/serving.v 12 | file_type : verilogSource 13 | depend : [serv] 14 | 15 | targets: 16 | default: 17 | filesets : [rtl] 18 | 19 | lint: 20 | default_tool : verilator 21 | filesets : [rtl] 22 | tools: 23 | verilator: 24 | mode : lint-only 25 | toplevel : serving 26 | 27 | provider: 28 | name : github 29 | user : olofk 30 | repo : serv 31 | version : 1.1.0 32 | -------------------------------------------------------------------------------- /simple_spi/simple_spi-1.6.1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::simple_spi:1.6.1 4 | description : OpenCores SPI Core 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/fifo4.v 10 | - rtl/verilog/simple_spi_top.v 11 | file_type : verilogSource 12 | 13 | tb: 14 | files: 15 | - bench/verilog/tst_bench_top.v 16 | - bench/verilog/spi_slave_model.v 17 | - bench/verilog/wb_master_model.v 18 | file_type : verilogSource 19 | depend: [vlog_tb_utils] 20 | 21 | targets: 22 | default: 23 | filesets: [rtl] 24 | 25 | lint: 26 | default_tool : verilator 27 | filesets : [rtl] 28 | tools: {verilator : {mode : lint-only}} 29 | toplevel : simple_spi 30 | 31 | sim: 32 | default_tool: icarus 33 | filesets: [rtl,tb] 34 | toplevel: tst_bench_top 35 | 36 | provider: 37 | name : github 38 | user : olofk 39 | repo : simple_spi 40 | version : v1.6.1 41 | -------------------------------------------------------------------------------- /stream_utils/stream_utils-1.3-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: ::stream_utils:1.3-r1 4 | description : FIFOs and size converters for data streams 5 | 6 | filesets: 7 | bfm: 8 | files: [bench/stream_writer.v, bench/stream_reader.v] 9 | file_type: verilogSource 10 | depend: ['>=::vlog_tb_utils:1.1'] 11 | 12 | constraints: 13 | files: [data/stream_utils.sdc : {file_type : SDC}] 14 | 15 | src_files: 16 | files: 17 | - rtl/verilog/stream_upsizer.v 18 | - rtl/verilog/stream_downsizer.v 19 | - rtl/verilog/stream_fifo_if.v 20 | - rtl/verilog/stream_fifo.v 21 | - rtl/verilog/stream_dual_clock_fifo.v 22 | - rtl/verilog/stream_mux.v 23 | file_type: verilogSource 24 | depend: ['>=::fifo:1.2'] 25 | 26 | tb_files: 27 | files: 28 | - bench/stream_upsizer_tb.v 29 | - bench/stream_downsizer_tb.v 30 | - bench/stream_fifo_tb.v 31 | - bench/stream_dual_clock_fifo_tb.v 32 | file_type: verilogSource 33 | depend: ['>=::vlog_tb_utils:1.1'] 34 | 35 | parameters: 36 | read_rate: 37 | datatype: str 38 | description: Stream read rate 39 | paramtype: plusarg 40 | scope: private 41 | write_rate: 42 | datatype: str 43 | description: Stream write rate 44 | paramtype: plusarg 45 | scope: private 46 | 47 | targets: 48 | default: 49 | filesets: 50 | - src_files 51 | - "stream_bfm? (bfm)" 52 | - "tool_quartus? (constraints)" 53 | 54 | stream_upsizer_tb: &tb 55 | default_tool: icarus 56 | description : Testbench for stream upsizer 57 | filesets: [src_files, bfm, tb_files] 58 | parameters: [read_rate, write_rate] 59 | toplevel: stream_upsizer_tb 60 | 61 | stream_downsizer_tb: 62 | <<: *tb 63 | description : Testbench for stream downsizer 64 | toplevel: stream_downsizer_tb 65 | 66 | stream_fifo_tb: 67 | <<: *tb 68 | description : Testbench for stream fifo 69 | toplevel: stream_fifo_tb 70 | 71 | stream_dual_clock_fifo_tb: 72 | <<: *tb 73 | description : Testbench for stream dual clock FIFO 74 | toplevel: stream_dual_clock_fifo_tb 75 | 76 | provider: 77 | name: github 78 | user: olofk 79 | repo: stream_utils 80 | version: v1.3 81 | -------------------------------------------------------------------------------- /timer/timer-1.0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::timer:1.0-r1 4 | description : Simple free-running timer with Wishbone interface 5 | 6 | filesets: 7 | rtl: 8 | files: [timer.v : {file_type : verilogSource}] 9 | 10 | targets: 11 | default : {filesets : [rtl]} 12 | 13 | provider: 14 | name : url 15 | url : https://raw.githubusercontent.com/fusesoc/tiny-cores/2353a67ee0e51e3d458eb7bc71a8e1d06438a31c/timer/rtl/verilog/timer.v 16 | filetype : simple 17 | -------------------------------------------------------------------------------- /uart16550/uart16550-1.5.5-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::uart16550:1.5.5-r1 3 | description : UART 16550 transceiver 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/verilog/uart_defines.v: {is_include_file: true} 9 | - rtl/verilog/raminfr.v 10 | - rtl/verilog/uart_receiver.v 11 | - rtl/verilog/uart_regs.v 12 | - rtl/verilog/uart_rfifo.v 13 | - rtl/verilog/uart_sync_flops.v 14 | - rtl/verilog/uart_tfifo.v 15 | - rtl/verilog/uart_top.v 16 | - rtl/verilog/uart_transmitter.v 17 | - rtl/verilog/uart_wb.v 18 | file_type: verilogSource 19 | 20 | targets: 21 | default: 22 | filesets: [rtl] 23 | 24 | provider: 25 | name : github 26 | user : olofk 27 | repo : uart16550 28 | version : v1.5.5 29 | -------------------------------------------------------------------------------- /verilator_tb_utils/verilator_tb_utils-1.0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: ::verilator_tb_utils:1.0 4 | description: "Verilator test bench utility class" 5 | 6 | filesets: 7 | verilator_tb: 8 | files: 9 | - verilator_tb_utils.cpp 10 | - verilator_tb_utils.h: {is_include_file: true} 11 | - jtagServer.cpp 12 | - jtagServer.h: {is_include_file: true} 13 | file_type: cppSource 14 | depend: [elf-loader] 15 | 16 | targets: 17 | default: 18 | filesets: [verilator_tb] 19 | parameters: [timeout, elf_load, bin_load, jtag_server, vcd, vcdstart, vcdstop] 20 | 21 | parameters: 22 | timeout: 23 | datatype: int 24 | description: Stop the simulator after VAL cycles 25 | paramtype: cmdlinearg 26 | 27 | elf_load: 28 | datatype: file 29 | description: ELF file to preload to memory 30 | paramtype: cmdlinearg 31 | 32 | bin_load: 33 | datatype: file 34 | description: Binary file to preload to memory (created from elf with objcopy) 35 | paramtype: cmdlinearg 36 | 37 | jtag_server: 38 | datatype: int 39 | description: Enable openocd JTAG server and define the TCP PORT to listen on 40 | paramtype: cmdlinearg 41 | 42 | vcd: 43 | datatype: file 44 | description: Enable and save VCD to FILE 45 | paramtype: cmdlinearg 46 | 47 | vcdstart: 48 | datatype: int 49 | description: Delay VCD generation until after VAL cycles 50 | paramtype: cmdlinearg 51 | 52 | vcdstop: 53 | datatype: int 54 | description: Terminate VCD generation at VAL cycles 55 | paramtype: cmdlinearg 56 | 57 | provider: 58 | name : github 59 | user : stffrdhrn 60 | repo : verilator_tb_utils 61 | version : v1.0 62 | -------------------------------------------------------------------------------- /verilog-arbiter/verilog-arbiter-r2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::verilog-arbiter:0-r2 3 | description : Verilog arbiter 4 | 5 | filesets: 6 | rtl: 7 | files: [src/arbiter.v] 8 | file_type : verilogSource 9 | 10 | targets: 11 | default: 12 | filesets: [rtl] 13 | 14 | provider: 15 | name : github 16 | user : bmartini 17 | repo : verilog-arbiter 18 | version : b79f89e17f0be3b70a513c1a0b456f734a79273a 19 | -------------------------------------------------------------------------------- /verilog-arbiter/verilog-arbiter-r3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::verilog-arbiter:0-r3 3 | description : Verilog arbiter 4 | 5 | filesets: 6 | rtl: 7 | files: [src/arbiter.v] 8 | file_type : verilogSource 9 | 10 | targets: 11 | default: 12 | filesets: [rtl] 13 | 14 | provider: 15 | name : github 16 | user : bmartini 17 | repo : verilog-arbiter 18 | version : 782bf8f34244cc6a3f279f2dbac8b5bf3f044132 19 | -------------------------------------------------------------------------------- /verilog-axis/verilog-axis-0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::verilog-axis:0-r1 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/arbiter.v 9 | - rtl/priority_encoder.v 10 | - rtl/axis_arb_mux.v 11 | - rtl/axis_async_fifo.v 12 | file_type : verilogSource 13 | 14 | targets: 15 | default: 16 | filesets : [rtl] 17 | 18 | generators: 19 | axis_arb_mux: 20 | interpreter: python 21 | command: rtl/axis_arb_mux_gen.py 22 | description : Generate a parametrized AXI Stream arbiter 23 | 24 | provider: 25 | name : github 26 | user : olofk 27 | repo : verilog-axis 28 | version : 22a418e91d60dd8c2015adef7da0bfed67f98217 29 | -------------------------------------------------------------------------------- /verilog-axis/verilog-axis-0-r2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::verilog-axis:0-r2 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/arbiter.v 9 | - rtl/priority_encoder.v 10 | - rtl/axis_arb_mux.v 11 | - rtl/axis_async_fifo.v 12 | file_type : verilogSource 13 | 14 | targets: 15 | default: 16 | filesets : [rtl] 17 | 18 | generators: 19 | axis_arb_mux: 20 | interpreter: python 21 | command: rtl/axis_arb_mux_gen.py 22 | description : Generate a parametrized AXI Stream arbiter 23 | 24 | provider: 25 | name : github 26 | user : olofk 27 | repo : verilog-axis 28 | version : d1f724b212d243572cea4cd4dd2ad336ff9d71ef 29 | -------------------------------------------------------------------------------- /verilog-axis/verilog-axis-0-r3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::verilog-axis:0-r3 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/arbiter.v 9 | - rtl/priority_encoder.v 10 | - rtl/axis_arb_mux.v 11 | - rtl/axis_async_fifo.v 12 | file_type : verilogSource 13 | 14 | targets: 15 | default: 16 | filesets : [rtl] 17 | 18 | generators: 19 | axis_arb_mux: 20 | interpreter: python3 21 | command: rtl/axis_arb_mux_gen.py 22 | description : Generate a parametrized AXI Stream arbiter 23 | 24 | provider: 25 | name : github 26 | user : olofk 27 | repo : verilog-axis 28 | version : d1f724b212d243572cea4cd4dd2ad336ff9d71ef 29 | -------------------------------------------------------------------------------- /verilog-axis/verilog-axis-0.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::verilog-axis:0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/arbiter.v 9 | - rtl/priority_encoder.v 10 | - rtl/axis_arb_mux.v 11 | file_type : verilogSource 12 | 13 | targets: 14 | default: 15 | filesets : [rtl] 16 | 17 | generators: 18 | axis_arb_mux: 19 | interpreter: python 20 | command: rtl/axis_arb_mux_gen.py 21 | description : Generate a parametrized AXI Stream arbiter 22 | 23 | provider: 24 | name : github 25 | user : olofk 26 | repo : verilog-axis 27 | version : 22a418e91d60dd8c2015adef7da0bfed67f98217 28 | -------------------------------------------------------------------------------- /vlog_tb_utils/vlog_tb_utils-1.1-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::vlog_tb_utils:1.1-r1 4 | description : Verilog test bench utilities 5 | 6 | filesets: 7 | tb_files: 8 | files: 9 | - vlog_functions.v 10 | - vlog_tap_generator.v 11 | - vlog_tb_utils.v 12 | file_type : verilogSource 13 | 14 | targets: 15 | default: 16 | filesets : [tb_files] 17 | parameters : [heartbeat, tapfile, testcase, timeout, vcd] 18 | 19 | parameters: 20 | heartbeat: 21 | datatype : int 22 | description : Display a heartbeat message every n*heartbeat time unit 23 | paramtype : plusarg 24 | 25 | tapfile: 26 | datatype : str 27 | description : Name of TAP file 28 | paramtype : plusarg 29 | 30 | testcase: 31 | datatype : str 32 | description : Name of testcase (Used for VCD filename) 33 | paramtype : plusarg 34 | 35 | timeout: 36 | datatype : int 37 | description : Abort test case after n cycles 38 | paramtype : plusarg 39 | 40 | vcd: 41 | datatype : bool 42 | description : Enable VCD logging 43 | paramtype : plusarg 44 | 45 | provider: 46 | name : github 47 | user : fusesoc 48 | repo : vlog_tb_utils 49 | version : v1.1 50 | -------------------------------------------------------------------------------- /wb_altera_ddr_wrapper/wb_altera_ddr_wrapper-0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::wb_altera_ddr_wrapper:0-r1 3 | 4 | filesets: 5 | rtl: 6 | files: 7 | - rtl/verilog/wb_port_arbiter.v 8 | - rtl/verilog/bufram.v 9 | - rtl/verilog/dpram_altera.v 10 | - rtl/verilog/wb_ddr_ctrl.v 11 | - rtl/verilog/wb_port.v 12 | - rtl/verilog/ddr_ctrl_wrapper.v 13 | file_type : verilogSource 14 | depend : [fifo] 15 | 16 | tb: 17 | files: 18 | - bench/ddr_ctrl_ip/alt_mem_ddrx_define.iv : {is_include_file : true} 19 | - bench/ddr_ctrl_ip/alt_mem_phy_defines.v : {is_include_file : true} 20 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_alt_mem_ddrx_controller_top.v 21 | - bench/ddr_ctrl_ip/alt_mem_ddrx_controller.v 22 | - bench/ddr_ctrl_ip/alt_mem_ddrx_addr_cmd.v 23 | - bench/ddr_ctrl_ip/alt_mem_ddrx_addr_cmd_wrap.v 24 | - bench/ddr_ctrl_ip/alt_mem_ddrx_controller_st_top.v 25 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ddr2_odt_gen.v 26 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ddr3_odt_gen.v 27 | - bench/ddr_ctrl_ip/alt_mem_ddrx_lpddr2_addr_cmd.v 28 | - bench/ddr_ctrl_ip/alt_mem_ddrx_odt_gen.v 29 | - bench/ddr_ctrl_ip/alt_mem_ddrx_rdwr_data_tmg.v 30 | - bench/ddr_ctrl_ip/alt_mem_ddrx_arbiter.v 31 | - bench/ddr_ctrl_ip/alt_mem_ddrx_burst_gen.v 32 | - bench/ddr_ctrl_ip/alt_mem_ddrx_cmd_gen.v 33 | - bench/ddr_ctrl_ip/alt_mem_ddrx_csr.v 34 | - bench/ddr_ctrl_ip/alt_mem_ddrx_buffer.v 35 | - bench/ddr_ctrl_ip/alt_mem_ddrx_buffer_manager.v 36 | - bench/ddr_ctrl_ip/alt_mem_ddrx_burst_tracking.v 37 | - bench/ddr_ctrl_ip/alt_mem_ddrx_dataid_manager.v 38 | - bench/ddr_ctrl_ip/alt_mem_ddrx_fifo.v 39 | - bench/ddr_ctrl_ip/alt_mem_ddrx_list.v 40 | - bench/ddr_ctrl_ip/alt_mem_ddrx_rdata_path.v 41 | - bench/ddr_ctrl_ip/alt_mem_ddrx_wdata_path.v 42 | - bench/ddr_ctrl_ip/alt_mem_ddrx_define.iv 43 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_decoder.v 44 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_decoder_32_syn.v 45 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_decoder_64_syn.v 46 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_encoder.v 47 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_encoder_32_syn.v 48 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_encoder_64_syn.v 49 | - bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v 50 | - bench/ddr_ctrl_ip/alt_mem_ddrx_input_if.v 51 | - bench/ddr_ctrl_ip/alt_mem_ddrx_mm_st_converter.v 52 | - bench/ddr_ctrl_ip/alt_mem_ddrx_rank_timer.v 53 | - bench/ddr_ctrl_ip/alt_mem_ddrx_sideband.v 54 | - bench/ddr_ctrl_ip/alt_mem_ddrx_tbp.v 55 | - bench/ddr_ctrl_ip/alt_mem_ddrx_timing_param.v 56 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_controller_phy.v 57 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_phy_alt_mem_phy.v 58 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_phy_alt_mem_phy_pll.v 59 | - bench/ddr_ctrl_ip/altera_primitives.v 60 | - bench/ddr_ctrl_ip/cycloneiii_atoms.v 61 | - bench/ddr_ctrl_ip/sgate.v 62 | - bench/ddr_ctrl_ip/altera_mf.v 63 | - bench/ddr_ctrl_ip/220model.v 64 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_phy_alt_mem_phy_seq_wrapper.vo 65 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_sim.v 66 | - bench/ddr_ctrl_ip/ddr_ctrl_ip_phy.v 67 | - bench/wb_ddr_ctrl_tb.v 68 | file_type : verilogSource 69 | depend: [mt46v16m16p, wb_bfm] 70 | 71 | targets: 72 | default: 73 | filesets: [rtl] 74 | sim: 75 | default_tool : modelsim 76 | filesets: [rtl,tb] 77 | tools: 78 | modelsim: 79 | vlog_options : [+define+sg5B, +define+x16, +define+FULL_MEM] 80 | vsim_options : [-t, 1ps, -suppress, 3009] 81 | toplevel: [wb_ddr_ctrl_tb] 82 | 83 | provider: 84 | name : github 85 | user : fusesoc 86 | repo : wb_altera_ddr_wrapper 87 | version : e01aa362ebab53dcc6e87e2859afb302b03536f9 88 | -------------------------------------------------------------------------------- /wb_bfm/wb_bfm-1.2.1-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wb_bfm:1.2.1-r1 4 | description : Wishbone BFM 5 | 6 | filesets: 7 | bfm: 8 | files: 9 | - wb_bfm_master.v 10 | - wb_bfm_slave.v 11 | - wb_bfm_memory.v 12 | - wb_bfm_transactor.v 13 | file_type : verilogSource 14 | depend : [wb_common] 15 | 16 | tb: 17 | files: [bench/wb_bfm_tb.v : {file_type : verilogSource}] 18 | depend : [">=::vlog_tb_utils:1.1"] 19 | 20 | targets: 21 | default: 22 | filesets : [bfm] 23 | 24 | sim: 25 | default_tool : icarus 26 | description : WB BFM testbench 27 | filesets : [bfm, tb] 28 | parameters : [transactions, subtransactions] 29 | tools: 30 | isim: 31 | isim_options : [-d, BROKEN_CLOG2] 32 | toplevel : wb_bfm_tb 33 | 34 | parameters: 35 | transactions: 36 | datatype : int 37 | description : Number of test bench transactions 38 | paramtype : plusarg 39 | 40 | subtransactions: 41 | datatype : int 42 | description : Number of test subtransactions to run 43 | paramtype : plusarg 44 | 45 | provider: 46 | name : github 47 | user : olofk 48 | repo : wb_bfm 49 | version : v1.2.1 50 | -------------------------------------------------------------------------------- /wb_common/wb_common-1.0.3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wb_common:1.0.3 4 | 5 | filesets: 6 | common: 7 | files: 8 | - wb_common_params.v : {is_include_file : true} 9 | - wb_common.v : {is_include_file : true} 10 | file_type : verilogSource 11 | 12 | targets: 13 | default: 14 | filesets : [common] 15 | 16 | provider: 17 | name : github 18 | user : fusesoc 19 | repo : wb_common 20 | version : v1.0.3 21 | -------------------------------------------------------------------------------- /wb_intercon/wb_intercon-1.2.2-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wb_intercon:1.2.2-r1 4 | description : Wishbone Bus Interconnect utilities 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/wb_cdc.v 10 | - rtl/verilog/wb_arbiter.v 11 | - rtl/verilog/wb_data_resize.v 12 | - rtl/verilog/wb_mux.v 13 | file_type : verilogSource 14 | depend: 15 | - ">=verilog-arbiter-0-r1" 16 | - cdc_utils 17 | - wb_common 18 | 19 | tb: 20 | files: 21 | - bench/wb_cdc_tb.v 22 | - bench/wb_mux_tb.v 23 | - bench/wb_arbiter_tb.v 24 | - bench/wb_intercon_tb.v 25 | file_type : verilogSource 26 | depend: [">=vlog_tb_utils-1.1", ">=wb_bfm-1.1"] 27 | 28 | constraints: 29 | files : [data/wb_intercon.sdc: {file_type : SDC}] 30 | 31 | generators: 32 | wb_intercon_gen: 33 | interpreter: python3 34 | command: sw/wb_intercon_gen2.py 35 | description : Create a wishbone crossbar interconnect from a memory map 36 | usage: | 37 | The Wishbone interconnect generator generates a verilog core from a 38 | description of master and connected slave ports. 39 | 40 | Parameters: 41 | masters (dict): A named list of master ports. Each master has a list of 42 | connected slave ports 43 | 44 | Example 45 | 46 | masters: 47 | cpu_ibus: 48 | slaves: [mem, bootrom] 49 | cpu_dbus: [mem, uart, spi1, spi2] 50 | slaves (dict): A named list of slave ports. Each slave defines the 51 | and space they occupy in the memory map 52 | 53 | Example 54 | 55 | slaves: 56 | bootrom: 57 | offset : 0xf0000000 58 | size : 512 59 | uart: 60 | offset : 0x90000000 61 | size : 16 62 | mem: 63 | offset : 0x00000000 64 | size : 0x100000 65 | 66 | targets: 67 | default: 68 | filesets: [rtl, "tool_quartus? (constraints)"] 69 | tools: 70 | isim: 71 | fuse_options: [-d, BROKEN_CLOG2] 72 | 73 | sim: 74 | filesets: [rtl, tb] 75 | parameters: [transactions] 76 | tools: 77 | isim: 78 | fuse_options: [-d, BROKEN_CLOG2] 79 | toplevel: wb_intercon_tb 80 | 81 | parameters: 82 | transactions: 83 | datatype : int 84 | description : Number of wishbone transactions to run in test bench 85 | paramtype : plusarg 86 | 87 | provider: 88 | name : github 89 | user : olofk 90 | repo : wb_intercon 91 | version : v1.2.2 92 | -------------------------------------------------------------------------------- /wb_intercon/wb_intercon-1.2.2.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wb_intercon:1.2.2 4 | description : Wishbone Bus Interconnect utilities 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/wb_cdc.v 10 | - rtl/verilog/wb_arbiter.v 11 | - rtl/verilog/wb_data_resize.v 12 | - rtl/verilog/wb_mux.v 13 | file_type : verilogSource 14 | depend: 15 | - ">=verilog-arbiter-0-r1" 16 | - cdc_utils 17 | - wb_common 18 | 19 | tb: 20 | files: 21 | - bench/wb_cdc_tb.v 22 | - bench/wb_mux_tb.v 23 | - bench/wb_arbiter_tb.v 24 | - bench/wb_intercon_tb.v 25 | file_type : verilogSource 26 | depend: [">=vlog_tb_utils-1.1", ">=wb_bfm-1.1"] 27 | 28 | constraints: 29 | files : [data/wb_intercon.sdc: {file_type : SDC}] 30 | 31 | generators: 32 | wb_intercon_gen: 33 | interpreter: python 34 | command: sw/wb_intercon_gen2.py 35 | description : Create a wishbone crossbar interconnect from a memory map 36 | usage: | 37 | The Wishbone interconnect generator generates a verilog core from a 38 | description of master and connected slave ports. 39 | 40 | Parameters: 41 | masters (dict): A named list of master ports. Each master has a list of 42 | connected slave ports 43 | 44 | Example 45 | 46 | masters: 47 | cpu_ibus: 48 | slaves: [mem, bootrom] 49 | cpu_dbus: [mem, uart, spi1, spi2] 50 | slaves (dict): A named list of slave ports. Each slave defines the 51 | and space they occupy in the memory map 52 | 53 | Example 54 | 55 | slaves: 56 | bootrom: 57 | offset : 0xf0000000 58 | size : 512 59 | uart: 60 | offset : 0x90000000 61 | size : 16 62 | mem: 63 | offset : 0x00000000 64 | size : 0x100000 65 | 66 | targets: 67 | default: 68 | filesets: [rtl, "tool_quartus? (constraints)"] 69 | tools: 70 | isim: 71 | fuse_options: [-d, BROKEN_CLOG2] 72 | 73 | sim: 74 | filesets: [rtl, tb] 75 | parameters: [transactions] 76 | tools: 77 | isim: 78 | fuse_options: [-d, BROKEN_CLOG2] 79 | toplevel: wb_intercon_tb 80 | 81 | parameters: 82 | transactions: 83 | datatype : int 84 | description : Number of wishbone transactions to run in test bench 85 | paramtype : plusarg 86 | 87 | provider: 88 | name : github 89 | user : olofk 90 | repo : wb_intercon 91 | version : v1.2.2 92 | -------------------------------------------------------------------------------- /wb_intercon/wb_intercon-1.4.1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wb_intercon:1.4.1 4 | description : Wishbone Bus Interconnect utilities 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/wb_cdc.v 10 | - rtl/verilog/wb_arbiter.v 11 | - rtl/verilog/wb_data_resize.v 12 | - rtl/verilog/wb_mux.v 13 | file_type : verilogSource 14 | depend: 15 | - ">=verilog-arbiter-0-r1" 16 | - cdc_utils 17 | - wb_common 18 | 19 | tb: 20 | files: 21 | - bench/wb_cdc_tb.v 22 | - bench/wb_mux_tb.v 23 | - bench/wb_arbiter_tb.v 24 | - bench/wb_intercon_tb.v 25 | file_type : verilogSource 26 | depend: [">=vlog_tb_utils-1.1", ">=wb_bfm-1.1"] 27 | 28 | constraints: 29 | files : [data/wb_intercon.sdc: {file_type : SDC}] 30 | 31 | generators: 32 | wb_intercon_gen: 33 | interpreter: python3 34 | command: sw/wb_intercon_gen2.py 35 | description : Create a wishbone crossbar interconnect from a memory map 36 | usage: | 37 | The Wishbone interconnect generator generates a verilog core from a 38 | description of host and connected device ports. 39 | 40 | Parameters: 41 | hosts (dict): A named list of host ports. Each host has a list of 42 | connected device ports 43 | 44 | Example 45 | 46 | hosts: 47 | cpu_ibus: 48 | devices: [mem, bootrom] 49 | cpu_dbus: [mem, uart, spi1, spi2] 50 | devices (dict): A named list of device ports. Each device defines the 51 | and space they occupy in the memory map 52 | 53 | Example 54 | 55 | devices: 56 | bootrom: 57 | offset : 0xf0000000 58 | size : 512 59 | uart: 60 | offset : 0x90000000 61 | size : 16 62 | mem: 63 | offset : 0x00000000 64 | size : 0x100000 65 | 66 | targets: 67 | default: 68 | filesets: [rtl, "tool_quartus? (constraints)"] 69 | tools: 70 | isim: 71 | fuse_options: [-d, BROKEN_CLOG2] 72 | 73 | sim: 74 | default_tool : icarus 75 | description : wb_intercon regression tests 76 | filesets: [rtl, tb] 77 | parameters: [transactions] 78 | tools: 79 | isim: 80 | fuse_options: [-d, BROKEN_CLOG2] 81 | toplevel: wb_intercon_tb 82 | 83 | parameters: 84 | transactions: 85 | datatype : int 86 | description : Number of wishbone transactions to run in test bench 87 | paramtype : plusarg 88 | 89 | provider: 90 | name : github 91 | user : olofk 92 | repo : wb_intercon 93 | version : v1.4.1 94 | -------------------------------------------------------------------------------- /wb_ram/wb_ram-1.1-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name: ::wb_ram:1.1-r1 4 | description: Wishbone RAM with selectable backends 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/wb_ram.v 10 | - rtl/verilog/wb_ram_generic.v 11 | file_type: verilogSource 12 | depend: ['>=::wb_common:0'] 13 | 14 | tb: 15 | files: [bench/wb_ram_tb.v : {file_type : verilogSource}] 16 | depend: ['>=::vlog_tb_utils:1.0', '>=::wb_bfm:1.0'] 17 | 18 | parameters: 19 | transactions: 20 | datatype: int 21 | description: Number of wishbone transactions to run in test bench 22 | paramtype: plusarg 23 | scope: private 24 | 25 | targets: 26 | default: 27 | filesets: [rtl] 28 | 29 | sim: 30 | default_tool: icarus 31 | description : WB RAM testbench 32 | filesets: [rtl, tb] 33 | parameters: [transactions] 34 | toplevel: wb_ram_tb 35 | 36 | provider: 37 | name: github 38 | user: fusesoc 39 | repo: wb_ram 40 | version: v1.1 41 | -------------------------------------------------------------------------------- /wb_sdram_ctrl/wb_sdram_ctrl-r3.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::wb_sdram_ctrl:0-r3 3 | filesets: 4 | rtl: 5 | files: 6 | - rtl/verilog/wb_port_arbiter.v 7 | - rtl/verilog/bufram.v 8 | - rtl/verilog/dpram_altera.v 9 | - rtl/verilog/dpram_generic.v 10 | - rtl/verilog/dual_clock_fifo.v 11 | - rtl/verilog/sdram_ctrl.v 12 | - rtl/verilog/wb_port.v 13 | - rtl/verilog/wb_sdram_ctrl.v 14 | file_type : verilogSource 15 | 16 | tb: 17 | files : [bench/wb_sdram_ctrl_tb.v] 18 | file_type : verilogSource 19 | depend: 20 | [mt48lc16m16a2, ">=vlog_tb_utils-1.0", ">=wb_bfm-1.0"] 21 | 22 | parameters: 23 | transactions: 24 | datatype : int 25 | description : Number of wishbone transactions to run in test bench 26 | paramtype : plusarg 27 | 28 | subtransactions: 29 | datatype : int 30 | description : Number of wishbone transactions to run in test bench 31 | paramtype : plusarg 32 | 33 | seed: 34 | datatype : int 35 | description : Initial random seed 36 | paramtype : plusarg 37 | scope : private 38 | 39 | targets: 40 | default: 41 | filesets: [rtl] 42 | sim: 43 | default_tool : icarus 44 | filesets : [rtl, tb] 45 | parameters : [transactions, subtransactions, seed] 46 | tools: 47 | modelsim: 48 | vlog_options : [-timescale=1ns/1ps] 49 | vsim_options : [-t, 1ps] 50 | toplevel : [wb_sdram_ctrl_tb] 51 | 52 | provider: 53 | name : github 54 | user : stffrdhrn 55 | repo : wb_sdram_ctrl 56 | version : ccc032255dfdda6282b24eb8a6814fe9860bec0d 57 | -------------------------------------------------------------------------------- /wb_sdram_ctrl/wb_sdram_ctrl-r4.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name : ::wb_sdram_ctrl:0-r4 3 | filesets: 4 | rtl: 5 | files: 6 | - rtl/verilog/wb_port_arbiter.v 7 | - rtl/verilog/bufram.v 8 | - rtl/verilog/dpram_altera.v 9 | - rtl/verilog/dpram_ecp5.v 10 | - rtl/verilog/dpram_generic.v 11 | - rtl/verilog/dual_clock_fifo.v 12 | - rtl/verilog/sdram_ctrl.v 13 | - rtl/verilog/wb_port.v 14 | - rtl/verilog/wb_sdram_ctrl.v 15 | file_type : verilogSource 16 | 17 | tb: 18 | files : [bench/wb_sdram_ctrl_tb.v] 19 | file_type : verilogSource 20 | depend: 21 | [mt48lc16m16a2, ">=vlog_tb_utils-1.0", ">=wb_bfm-1.0"] 22 | 23 | parameters: 24 | transactions: 25 | datatype : int 26 | description : Number of wishbone transactions to run in test bench 27 | paramtype : plusarg 28 | 29 | subtransactions: 30 | datatype : int 31 | description : Number of wishbone transactions to run in test bench 32 | paramtype : plusarg 33 | 34 | seed: 35 | datatype : int 36 | description : Initial random seed 37 | paramtype : plusarg 38 | 39 | technology: 40 | datatype : str 41 | description : Select DPRAM implementation. Legal values are ALTERA, ECP5 or GENERIC (default) 42 | paramtype : vlogparam 43 | 44 | USE_LATTICE_GSR_PUR: 45 | datatype: bool 46 | paramtype : vlogdefine 47 | targets: 48 | default: 49 | filesets: [rtl] 50 | sim: &sim 51 | default_tool : icarus 52 | filesets : [rtl, tb] 53 | parameters : [transactions, subtransactions, seed, technology] 54 | tools: 55 | modelsim: 56 | vlog_options : [-timescale=1ns/1ps] 57 | vsim_options : [-t, 1ps] 58 | toplevel : [wb_sdram_ctrl_tb] 59 | sim_altsyncram: 60 | <<: *sim 61 | parameters : [transactions, subtransactions, seed, technology=ALTERA] 62 | tools: 63 | icarus: 64 | iverilog_options : [-l, $(QUARTUS_ROOTDIR)/eda/sim_lib/altera_mf.v] 65 | modelsim: 66 | vlog_options : [-timescale=1ns/1ps] 67 | vsim_options : [-t, 1ps, -L, altera_mf_ver] 68 | sim_ecp5: 69 | <<: *sim 70 | parameters : [transactions, subtransactions, seed, technology=ECP5, USE_LATTICE_GSR_PUR=true] 71 | tools: 72 | icarus: 73 | iverilog_options : [-y, $(FOUNDRY)/verilog/data/ecp5u] 74 | 75 | 76 | provider: 77 | name : github 78 | user : olofk 79 | repo : wb_sdram_ctrl 80 | version : 26eb18d5e652333650cfe1d8fee469c8695f703a 81 | -------------------------------------------------------------------------------- /wb_streamer/wb_streamer-1.1-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wb_streamer:1.1-r1 4 | description : Wishbone read/write AXI streamer core 5 | 6 | filesets: 7 | rtl: 8 | files: 9 | - rtl/verilog/wb_stream_reader_cfg.v 10 | - rtl/verilog/wb_stream_reader_ctrl.v 11 | - rtl/verilog/wb_stream_writer_fifo.v 12 | - rtl/verilog/wb_stream_reader.v 13 | - rtl/verilog/wb_stream_writer_cfg.v 14 | - rtl/verilog/wb_stream_writer_ctrl.v 15 | - rtl/verilog/wb_stream_writer.v 16 | file_type : verilogSource 17 | depend: 18 | - ">=fifo-1.0" 19 | - ">=stream_utils-1.1" 20 | 21 | tb: 22 | files: 23 | - bench/wb_reader.v 24 | - bench/wb_stream_reader_tb.v 25 | - bench/wb_stream_writer_tb.v 26 | file_type : verilogSource 27 | depend : 28 | - ">=vlog_tb_utils-1.0" 29 | - ">=wb_bfm-1.0" 30 | 31 | parameters: 32 | transactions: 33 | datatype : int 34 | description : Number of test bench transactions 35 | paramtype : plusarg 36 | 37 | verbose: 38 | datatype : bool 39 | description : Enable debug printouts in test bench 40 | paramtype : plusarg 41 | 42 | targets: 43 | default: 44 | filesets : [rtl] 45 | sim_reader: &sim 46 | default_tool : icarus 47 | filesets : [rtl, tb] 48 | parameters : [transactions, verbose] 49 | toplevel : wb_stream_reader_tb 50 | sim_writer: 51 | <<: *sim 52 | toplevel : wb_stream_writer_tb 53 | 54 | provider: 55 | name : github 56 | user : olofk 57 | repo : wb_streamer 58 | version : v1.1 59 | -------------------------------------------------------------------------------- /wiredelay/wiredelay-0-r1.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::wiredelay:0-r1 4 | description : Wire delay Verilog model 5 | filesets : {f : {files: [wiredelay.v : {file_type : verilogSource}]}} 6 | targets: {default: {filesets : [f]}} 7 | 8 | provider: 9 | name : url 10 | url : https://raw.githubusercontent.com/fusesoc/tiny-cores/master/wiredelay/wiredelay.v 11 | filetype : simple 12 | -------------------------------------------------------------------------------- /yosys_cells/ecp5-0.8.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : yosys:techlibs:ecp5:0.8 4 | 5 | filesets: 6 | ecp5_cells: 7 | files: [cells_sim.v : {file_type : verilogSource}] 8 | 9 | targets: 10 | default: 11 | filesets : [ecp5_cells] 12 | 13 | provider: 14 | name : url 15 | filetype : simple 16 | url : https://raw.githubusercontent.com/YosysHQ/yosys/d29b517fef05973dda3c556a95fbfb478d6e7e50/techlibs/ecp5/cells_sim.v -------------------------------------------------------------------------------- /yosys_cells/ice40-0.7.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : yosys:techlibs:ice40:0.7 4 | 5 | filesets: 6 | ice40_cells: 7 | files: 8 | - cells_sim.v : {file_type : verilogSource} 9 | 10 | targets: 11 | default: 12 | filesets : [ice40_cells] 13 | 14 | provider: 15 | name : url 16 | filetype : simple 17 | url : https://raw.githubusercontent.com/YosysHQ/yosys/c3be94e967c904d4b7a0591fdaa2d86bc926ec41/techlibs/ice40/cells_sim.v 18 | --------------------------------------------------------------------------------