├── LICENSE ├── README.md ├── rtl └── verilog │ ├── common.v │ ├── sd_brams.v │ ├── sd_const.vh │ ├── sd_link.v │ ├── sd_mgr.v │ ├── sd_params.vh │ ├── sd_phy.v │ ├── sd_top.v │ └── sd_wishbone.v └── sd_device.core /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/README.md -------------------------------------------------------------------------------- /rtl/verilog/common.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/common.v -------------------------------------------------------------------------------- /rtl/verilog/sd_brams.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_brams.v -------------------------------------------------------------------------------- /rtl/verilog/sd_const.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_const.vh -------------------------------------------------------------------------------- /rtl/verilog/sd_link.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_link.v -------------------------------------------------------------------------------- /rtl/verilog/sd_mgr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_mgr.v -------------------------------------------------------------------------------- /rtl/verilog/sd_params.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_params.vh -------------------------------------------------------------------------------- /rtl/verilog/sd_phy.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_phy.v -------------------------------------------------------------------------------- /rtl/verilog/sd_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_top.v -------------------------------------------------------------------------------- /rtl/verilog/sd_wishbone.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/rtl/verilog/sd_wishbone.v -------------------------------------------------------------------------------- /sd_device.core: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fusesoc/sd_device/HEAD/sd_device.core --------------------------------------------------------------------------------