├── README.md ├── project_demo ├── project_demo.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── project_demo.hw │ └── project_demo.lpr ├── project_demo.ip_user_files │ └── README.txt ├── project_demo.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ └── vrs_config_3.xml │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── test_alu_ctr.dcp │ │ ├── test_alu_ctr.tcl │ │ ├── test_alu_ctr.vds │ │ ├── test_alu_ctr_utilization_synth.pb │ │ ├── test_alu_ctr_utilization_synth.rpt │ │ ├── vivado.jou │ │ └── vivado.pb ├── project_demo.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── cla_test.tcl │ │ ├── cla_test_behav.wdb │ │ ├── cla_test_vlog.prj │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── test.tcl │ │ ├── test_add32.tcl │ │ ├── test_add32_behav.wdb │ │ ├── test_add32_vlog.prj │ │ ├── test_alu.tcl │ │ ├── test_alu_behav.wdb │ │ ├── test_alu_ctr.tcl │ │ ├── test_alu_ctr_behav.wdb │ │ ├── test_alu_ctr_vlog.prj │ │ ├── test_alu_vlog.prj │ │ ├── test_behav.wdb │ │ ├── test_i_ins.tcl │ │ ├── test_i_ins_behav.wdb │ │ ├── test_i_ins_vlog.prj │ │ ├── test_ls_ins.tcl │ │ ├── test_ls_ins_behav.wdb │ │ ├── test_ls_ins_vlog.prj │ │ ├── test_mem_file.tcl │ │ ├── test_mem_file_behav.wdb │ │ ├── test_mem_file_vlog.prj │ │ ├── test_next_pc.tcl │ │ ├── test_next_pc_behav.wdb │ │ ├── test_next_pc_vlog.prj │ │ ├── test_reg_file.tcl │ │ ├── test_reg_file_behav.wdb │ │ ├── test_reg_file_vlog.prj │ │ ├── test_top_alu.tcl │ │ ├── test_top_alu_behav.wdb │ │ ├── test_top_alu_vlog.prj │ │ ├── test_u_ins.tcl │ │ ├── test_u_ins_behav.wdb │ │ ├── test_u_ins_vlog.prj │ │ ├── test_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_198068.backup.jou │ │ ├── webtalk_198068.backup.log │ │ ├── webtalk_199924.backup.jou │ │ ├── webtalk_199924.backup.log │ │ ├── webtalk_200584.backup.jou │ │ ├── webtalk_200584.backup.log │ │ ├── webtalk_206464.backup.jou │ │ ├── webtalk_206464.backup.log │ │ ├── webtalk_206660.backup.jou │ │ ├── webtalk_206660.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── cla_test_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── cla_test_behav_102780_1575016266.btree │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_add32_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_alu_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── test_alu_behav_102780_1575076968.btree │ │ │ ├── test_alu_behav_102780_1575077765.btree │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_alu_ctr_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_i_ins_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_ls_ins_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_mem_file_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_next_pc_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── test_next_pc_behav_206052_1575116756.btree │ │ │ ├── test_next_pc_behav_8352_1575119110.btree │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_reg_file_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_top_alu_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_u_ins_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── xil_defaultlib │ │ │ ├── @r@i@s@c@vtop.sdb │ │ │ ├── ex.sdb │ │ │ ├── ex_mem.sdb │ │ │ ├── glbl.sdb │ │ │ ├── id.sdb │ │ │ ├── id_ex.sdb │ │ │ ├── if_id.sdb │ │ │ ├── inst_rom.sdb │ │ │ ├── mem.sdb │ │ │ ├── mem_wb.sdb │ │ │ ├── pc_reg.sdb │ │ │ ├── regfile.sdb │ │ │ ├── riscv.sdb │ │ │ ├── test.sdb │ │ │ ├── test_32add.sdb │ │ │ ├── test_add32.sdb │ │ │ ├── test_i_ins.sdb │ │ │ ├── test_ls_ins.sdb │ │ │ ├── test_mem_file.sdb │ │ │ ├── test_next_pc.sdb │ │ │ ├── test_r_ins.sdb │ │ │ ├── test_u_ins.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xil_demolib │ │ │ ├── add_32.sdb │ │ │ ├── alu.sdb │ │ │ ├── alu_ctr.sdb │ │ │ ├── alu_top.sdb │ │ │ ├── bit_slice.sdb │ │ │ ├── cla.sdb │ │ │ ├── cla_32.sdb │ │ │ ├── cla_adder.sdb │ │ │ ├── cla_test.sdb │ │ │ ├── cla_top.sdb │ │ │ ├── data_rom.sdb │ │ │ ├── full_adder.sdb │ │ │ ├── glbl.sdb │ │ │ ├── ie.sdb │ │ │ ├── inst_mem.sdb │ │ │ ├── inst_rom.sdb │ │ │ ├── mem_file.sdb │ │ │ ├── next_pc.sdb │ │ │ ├── pc.sdb │ │ │ ├── pc_reg.sdb │ │ │ ├── pg.sdb │ │ │ ├── reg_file.sdb │ │ │ ├── regfile.sdb │ │ │ ├── sum.sdb │ │ │ ├── test_add32.sdb │ │ │ ├── test_alu.sdb │ │ │ ├── test_alu_ctr.sdb │ │ │ ├── test_reg_file.sdb │ │ │ ├── test_top_alu.sdb │ │ │ └── xil_demolib.rlx │ │ └── xsim.svtype │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb ├── project_demo.srcs │ ├── sim_1 │ │ └── new │ │ │ ├── test_add.v │ │ │ ├── test_i_ins.v │ │ │ ├── test_ls_ins.v │ │ │ ├── test_mem_file.v │ │ │ ├── test_next_pc.v │ │ │ ├── test_r_ins.v │ │ │ ├── test_u_ins.v │ │ │ └── test_u_ls_ins.v │ └── sources_1 │ │ ├── imports │ │ └── new │ │ │ ├── cla_test.v │ │ │ ├── test_32add.v │ │ │ ├── test_add32.v │ │ │ ├── test_alu.v │ │ │ ├── test_alu_ctr.v │ │ │ ├── test_reg_file.v │ │ │ └── test_top_alu.v │ │ └── new │ │ ├── add_32.v │ │ ├── alu.v │ │ ├── alu_ctr.v │ │ ├── alu_top.v │ │ ├── bit_slice.v │ │ ├── cla.v │ │ ├── cla_32.v │ │ ├── cla_adder.v │ │ ├── cla_top.v │ │ ├── data_rom.v │ │ ├── full_adder.v │ │ ├── ie.v │ │ ├── inst_mem.v │ │ ├── inst_rom.data │ │ ├── inst_rom.v │ │ ├── is.v │ │ ├── mem_file.v │ │ ├── n_bits.v │ │ ├── next_pc.v │ │ ├── pc.v │ │ ├── pg.v │ │ ├── reg.v │ │ ├── reg_file.v │ │ ├── regfile.v │ │ ├── sum.v │ │ └── test_alu.v └── project_demo.xpr └── project_single_cycle ├── project_single_cycle.cache └── wt │ ├── gui_handlers.wdf │ ├── java_command_handlers.wdf │ ├── project.wpc │ ├── synthesis.wdf │ ├── synthesis_details.wdf │ ├── webtalk_pa.xml │ └── xsim.wdf ├── project_single_cycle.hw └── project_single_cycle.lpr ├── project_single_cycle.ip_user_files └── README.txt ├── project_single_cycle.runs ├── .jobs │ └── vrs_config_1.xml └── synth_1 │ ├── .Vivado_Synthesis.queue.rst │ ├── .vivado.begin.rst │ ├── .vivado.end.rst │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── alu_top.dcp │ ├── alu_top.tcl │ ├── alu_top.vds │ ├── alu_top_utilization_synth.pb │ ├── alu_top_utilization_synth.rpt │ ├── gen_run.xml │ ├── htr.txt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── vivado.jou │ └── vivado.pb ├── project_single_cycle.sim └── sim_1 │ ├── behav │ └── xsim │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── test_b_inst.tcl │ │ ├── test_b_inst_behav.wdb │ │ ├── test_b_inst_vlog.prj │ │ ├── test_cpu_top.tcl │ │ ├── test_cpu_top_behav.wdb │ │ ├── test_cpu_top_vlog.prj │ │ ├── test_id.tcl │ │ ├── test_id_behav.wdb │ │ ├── test_id_vlog.prj │ │ ├── test_j_inst.tcl │ │ ├── test_j_inst_behav.wdb │ │ ├── test_j_inst_vlog.prj │ │ ├── test_pc.tcl │ │ ├── test_pc_behav.wdb │ │ ├── test_pc_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_13408.backup.jou │ │ ├── webtalk_13408.backup.log │ │ ├── webtalk_14560.backup.jou │ │ ├── webtalk_14560.backup.log │ │ ├── webtalk_20724.backup.jou │ │ ├── webtalk_20724.backup.log │ │ ├── webtalk_23784.backup.jou │ │ ├── webtalk_23784.backup.log │ │ ├── webtalk_24428.backup.jou │ │ ├── webtalk_24428.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── test_b_inst_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── test_b_inst_behav_8352_1575160871.btree │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_cpu_top_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── test_cpu_top_behav_10340_1576317961.btree │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_id_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_j_inst_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── test_j_inst_behav_8352_1575167085.btree │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── test_pc_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── test_pc_behav_8352_1575120668.btree │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── xil_defaultlib │ │ │ ├── alu.sdb │ │ │ ├── alu_ctr.sdb │ │ │ ├── alu_top.sdb │ │ │ ├── data_mem.sdb │ │ │ ├── glbl.sdb │ │ │ ├── id.sdb │ │ │ ├── ie.sdb │ │ │ ├── inst_rom.sdb │ │ │ ├── mux_alu_asrc.sdb │ │ │ ├── mux_alu_bsrc.sdb │ │ │ ├── next_pc.sdb │ │ │ ├── pc_reg.sdb │ │ │ ├── reg_file.sdb │ │ │ ├── test_b_inst.sdb │ │ │ ├── test_cpu_top.sdb │ │ │ ├── test_id.sdb │ │ │ ├── test_j_inst.sdb │ │ │ ├── test_pc.sdb │ │ │ └── xil_defaultlib.rlx │ │ └── xsim.svtype │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb │ └── synth │ └── func │ └── xsim │ ├── compile.bat │ ├── compile.log │ ├── elaborate.bat │ ├── elaborate.log │ ├── simulate.bat │ ├── simulate.log │ ├── test_cpu_top.tcl │ ├── test_cpu_top_func_synth.v │ ├── test_cpu_top_func_synth.wdb │ ├── test_cpu_top_vlog.prj │ ├── webtalk.jou │ ├── webtalk.log │ ├── xelab.pb │ ├── xsim.dir │ ├── test_cpu_top_func_synth │ │ ├── Compile_Options.txt │ │ ├── TempBreakPointFile.txt │ │ ├── obj │ │ │ ├── xsim_0.win64.obj │ │ │ ├── xsim_1.c │ │ │ └── xsim_1.win64.obj │ │ ├── test_cpu_top_func_synth_10340_1576319131.btree │ │ ├── webtalk │ │ │ ├── .xsim_webtallk.info │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ └── usage_statistics_ext_xsim.xml │ │ ├── xsim.dbg │ │ ├── xsim.mem │ │ ├── xsim.reloc │ │ ├── xsim.rlx │ │ ├── xsim.rtti │ │ ├── xsim.svtype │ │ ├── xsim.type │ │ ├── xsim.xdbg │ │ ├── xsimcrash.log │ │ ├── xsimk.exe │ │ └── xsimkernel.log │ ├── xil_defaultlib │ │ ├── alu.sdb │ │ ├── alu_ctr.sdb │ │ ├── alu_top.sdb │ │ ├── data_mem.sdb │ │ ├── glbl.sdb │ │ ├── id.sdb │ │ ├── ie.sdb │ │ ├── inst_rom.sdb │ │ ├── mux_alu_asrc.sdb │ │ ├── mux_alu_bsrc.sdb │ │ ├── next_pc.sdb │ │ ├── pc_reg.sdb │ │ ├── reg_file.sdb │ │ ├── test_cpu_top.sdb │ │ └── xil_defaultlib.rlx │ └── xsim.svtype │ ├── xsim.ini │ ├── xvlog.log │ └── xvlog.pb ├── project_single_cycle.srcs ├── sim_1 │ └── new │ │ ├── test_alu.v │ │ ├── test_alu_ctr.v │ │ ├── test_alu_top.v │ │ ├── test_b_inst.v │ │ ├── test_cpu_top.v │ │ ├── test_data_mem.v │ │ ├── test_i_inst.v │ │ ├── test_id.v │ │ ├── test_j_inst.v │ │ ├── test_ls_inst.v │ │ ├── test_pc.v │ │ ├── test_r_inst.v │ │ ├── test_reg_file.v │ │ └── test_u_inst.v └── sources_1 │ └── new │ ├── alu.v │ ├── alu_ctr.v │ ├── alu_top.v │ ├── cpu_top.v │ ├── data_mem.v │ ├── data_rom.data │ ├── id.v │ ├── ie.v │ ├── inst_rom.data │ ├── inst_rom.v │ ├── mux_alu_asrc.v │ ├── mux_alu_bsrc.v │ ├── next_pc.v │ ├── pc_reg.v │ └── reg_file.v └── project_single_cycle.xpr /README.md: -------------------------------------------------------------------------------- 1 | # 注： 2 | - 主文件为仿真文件 test_cpu_top.v ，运行该文件即可对整个 CPU 进行仿真； 3 | - 可以直接将该项目导入 Vivado（不需要手动拷贝），具体方法自行上网了解； 4 | - inst_rom.v 和 data_mem.v 中配置的 inst_rom.data 和 data_rom.data 的文件目录需要按照本机进行更改； 5 | 6 | -------------------------------------------------------------------------------- /project_demo/project_demo.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:28 3 | eof: 4 | -------------------------------------------------------------------------------- /project_demo/project_demo.cache/wt/synthesis_details.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 3 | eof:2511430288 4 | -------------------------------------------------------------------------------- /project_demo/project_demo.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /project_demo/project_demo.hw/project_demo.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /project_demo/project_demo.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log test_alu_ctr.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source test_alu_ctr.tcl 10 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/runme.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/runme.log -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/test_alu_ctr.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/test_alu_ctr.dcp -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/test_alu_ctr.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/test_alu_ctr.tcl -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/test_alu_ctr.vds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/test_alu_ctr.vds -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/test_alu_ctr_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/test_alu_ctr_utilization_synth.pb -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Sat Nov 30 20:40:05 2019 6 | # Process ID: 3744 7 | # Current directory: D:/vivado_project/project_demo/project_demo.runs/synth_1 8 | # Command line: vivado.exe -log test_alu_ctr.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source test_alu_ctr.tcl 9 | # Log file: D:/vivado_project/project_demo/project_demo.runs/synth_1/test_alu_ctr.vds 10 | # Journal file: D:/vivado_project/project_demo/project_demo.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source test_alu_ctr.tcl -notrace 13 | -------------------------------------------------------------------------------- /project_demo/project_demo.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/cla_test.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/cla_test_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/cla_test_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/cla_test_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/cla_test_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/compile.log -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2017.4 2 | Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. 3 | Running: D:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto 6ee22bdd2fea4a06943ea8c42f870d4e --incr --debug typical --relax --mt 2 -L xil_demolib -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_next_pc_behav xil_defaultlib.test_next_pc xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2017.4 2 | Time resolution is 1 ps 3 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_add32.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_add32_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_add32_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_add32_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_demolib \ 3 | "../../../../project_demo.srcs/sources_1/new/add_32.v" \ 4 | "../../../../project_demo.srcs/sources_1/imports/new/test_add32.v" \ 5 | 6 | # compile glbl module 7 | verilog xil_demolib "glbl.v" 8 | 9 | # Do not sort compile order 10 | nosort 11 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_alu.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_ctr.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_ctr_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_ctr_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_ctr_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_ctr_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_alu_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_i_ins.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_i_ins_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_i_ins_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_i_ins_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_i_ins_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_ls_ins.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_ls_ins_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_ls_ins_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_ls_ins_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_ls_ins_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_mem_file.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_mem_file_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_mem_file_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_mem_file_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_mem_file_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_next_pc.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_next_pc_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_next_pc_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_reg_file.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_reg_file_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_reg_file_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_reg_file_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_reg_file_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_top_alu.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_top_alu_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_top_alu_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_top_alu_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_top_alu_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_u_ins.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_u_ins_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_u_ins_behav.wdb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_u_ins_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_u_ins_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/test_vlog.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/test_vlog.prj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_demolib" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "cla_test_behav" "xil_demolib.cla_test" "xil_demolib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/cla_test_behav_102780_1575016266.btree: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/cla_test_behav_102780_1575016266.btree -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/obj/xsim_1.win64.obj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/webtalk/.xsim_webtallk.info: -------------------------------------------------------------------------------- 1 | 1575005189 2 | 1575005362 3 | 13 4 | 1 5 | 6ee22bdd2fea4a06943ea8c42f870d4e 6 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.dbg -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.mem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.mem -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.reloc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.reloc -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.xdbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsim.xdbg -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VERILOG_MODULE_SCOPE_FILTER=true 11 | VERILOG_PACKAGE_SCOPE_FILTER=false 12 | VERILOG_BLOCK_SCOPE_FILTER=false 13 | VERILOG_TASK_SCOPE_FILTER=false 14 | VERILOG_PROCESS_SCOPE_FILTER=false 15 | INPUT_OBJECT_FILTER=true 16 | OUTPUT_OBJECT_FILTER=true 17 | INOUT_OBJECT_FILTER=true 18 | INTERNAL_OBJECT_FILTER=true 19 | CONSTANT_OBJECT_FILTER=true 20 | VARIABLE_OBJECT_FILTER=true 21 | SCOPE_NAME_COLUMN_WIDTH=0 22 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0 23 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0 24 | OBJECT_NAME_COLUMN_WIDTH=120 25 | OBJECT_VALUE_COLUMN_WIDTH=80 26 | OBJECT_DATA_TYPE_COLUMN_WIDTH=60 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/cla_test_behav/xsimcrash.log: -------------------------------------------------------------------------------- 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Design successfully loaded 3 | Design Loading Memory Usage: 6216 KB (Peak: 6216 KB) 4 | Design Loading CPU Usage: 31 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6836 KB (Peak: 6836 KB) 7 | Simulation CPU Usage: 62 ms 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_demolib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_add32_behav" "xil_demolib.test_add32" "xil_demolib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/xsim.xdbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/xsim.xdbg -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VERILOG_MODULE_SCOPE_FILTER=true 11 | VERILOG_PACKAGE_SCOPE_FILTER=false 12 | VERILOG_BLOCK_SCOPE_FILTER=false 13 | VERILOG_TASK_SCOPE_FILTER=false 14 | VERILOG_PROCESS_SCOPE_FILTER=false 15 | INPUT_OBJECT_FILTER=true 16 | OUTPUT_OBJECT_FILTER=true 17 | INOUT_OBJECT_FILTER=true 18 | INTERNAL_OBJECT_FILTER=true 19 | CONSTANT_OBJECT_FILTER=true 20 | VARIABLE_OBJECT_FILTER=true 21 | SCOPE_NAME_COLUMN_WIDTH=0 22 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0 23 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0 24 | OBJECT_NAME_COLUMN_WIDTH=120 25 | OBJECT_VALUE_COLUMN_WIDTH=80 26 | OBJECT_DATA_TYPE_COLUMN_WIDTH=60 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_add32_behav/xsimcrash.log: -------------------------------------------------------------------------------- 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59798 2 | Design successfully loaded 3 | Design Loading Memory Usage: 6224 KB (Peak: 6224 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6848 KB (Peak: 6848 KB) 7 | Simulation CPU Usage: 15 ms 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_alu_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_demolib" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_alu_behav" "xil_demolib.test_alu" "xil_demolib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_alu_behav/TempBreakPointFile.txt: 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/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_alu_ctr_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VERILOG_MODULE_SCOPE_FILTER=true 11 | VERILOG_PACKAGE_SCOPE_FILTER=false 12 | VERILOG_BLOCK_SCOPE_FILTER=false 13 | VERILOG_TASK_SCOPE_FILTER=false 14 | VERILOG_PROCESS_SCOPE_FILTER=false 15 | INPUT_OBJECT_FILTER=true 16 | OUTPUT_OBJECT_FILTER=true 17 | INOUT_OBJECT_FILTER=true 18 | INTERNAL_OBJECT_FILTER=true 19 | CONSTANT_OBJECT_FILTER=true 20 | VARIABLE_OBJECT_FILTER=true 21 | SCOPE_NAME_COLUMN_WIDTH=0 22 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0 23 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0 24 | OBJECT_NAME_COLUMN_WIDTH=120 25 | OBJECT_VALUE_COLUMN_WIDTH=80 26 | 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-------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_alu_ctr_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/test_alu_ctr_behav/xsimk.exe -simmode gui -wdb test_alu_ctr_behav.wdb -simrunnum 0 -socket 59189 2 | Design successfully loaded 3 | Design Loading Memory Usage: 6852 KB (Peak: 6852 KB) 4 | Design Loading CPU Usage: 46 ms 5 | Simulation completed 6 | Simulation Memory Usage: 7504 KB (Peak: 7504 KB) 7 | Simulation CPU Usage: 77 ms 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_behav" "xil_defaultlib.test" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- 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\"xsim.dir/test_behav/obj/xsim_1.win64.obj\" \"D:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"D:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.rtti -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.svtype: -------------------------------------------------------------------------------- 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/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VERILOG_MODULE_SCOPE_FILTER=true 11 | VERILOG_PACKAGE_SCOPE_FILTER=false 12 | VERILOG_BLOCK_SCOPE_FILTER=false 13 | VERILOG_TASK_SCOPE_FILTER=false 14 | VERILOG_PROCESS_SCOPE_FILTER=false 15 | INPUT_OBJECT_FILTER=true 16 | OUTPUT_OBJECT_FILTER=true 17 | INOUT_OBJECT_FILTER=true 18 | INTERNAL_OBJECT_FILTER=true 19 | CONSTANT_OBJECT_FILTER=true 20 | VARIABLE_OBJECT_FILTER=true 21 | SCOPE_NAME_COLUMN_WIDTH=0 22 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0 23 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0 24 | OBJECT_NAME_COLUMN_WIDTH=120 25 | OBJECT_VALUE_COLUMN_WIDTH=80 26 | OBJECT_DATA_TYPE_COLUMN_WIDTH=60 27 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-------------------------------------------------------------------------------- 1 | Running: xsim.dir/test_next_pc_behav/xsimk.exe -simmode gui -wdb test_next_pc_behav.wdb -simrunnum 0 -socket 52627 2 | Design successfully loaded 3 | Design Loading Memory Usage: 6232 KB (Peak: 6232 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6488 KB (Peak: 6488 KB) 7 | Simulation CPU Usage: 30 ms 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_reg_file_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_demolib" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_reg_file_behav" "xil_demolib.test_reg_file" "xil_demolib.glbl" -log "elaborate.log" 2 | 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-------------------------------------------------------------------------------- 1 | Running: xsim.dir/test_reg_file_behav/xsimk.exe -simmode gui -wdb test_reg_file_behav.wdb -simrunnum 0 -socket 57286 2 | Design successfully loaded 3 | Design Loading Memory Usage: 6256 KB (Peak: 6256 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6924 KB (Peak: 6924 KB) 7 | Simulation CPU Usage: 15 ms 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_top_alu_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_demolib" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_top_alu_behav" "xil_demolib.test_top_alu" "xil_demolib.glbl" -log "elaborate.log" 2 | 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-------------------------------------------------------------------------------- 1 | Running: xsim.dir/test_top_alu_behav/xsimk.exe -simmode gui -wdb test_top_alu_behav.wdb -simrunnum 0 -socket 53220 2 | Design successfully loaded 3 | Design Loading Memory Usage: 6240 KB (Peak: 6240 KB) 4 | Design Loading CPU Usage: 62 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6880 KB (Peak: 6880 KB) 7 | Simulation CPU Usage: 62 ms 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xsim.dir/test_u_ins_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "6ee22bdd2fea4a06943ea8c42f870d4e" --incr --debug "typical" --relax --mt "2" -L "xil_demolib" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_u_ins_behav" "xil_defaultlib.test_u_ins" "xil_defaultlib.glbl" -log "elaborate.log" 2 | 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/project_demo/project_demo.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_demolib=xsim.dir/xil_demolib 2 | xil_defaultlib=xsim.dir/xil_defaultlib 3 | -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.sim/sim_1/behav/xsim/xvlog.log -------------------------------------------------------------------------------- /project_demo/project_demo.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- 1 | 2 |  3 | 4 | End Record -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sim_1/new/test_add.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/29 10:59:35 7 | // Design Name: 8 | // Module Name: test_add 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_add( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sim_1/new/test_i_ins.v: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sim_1/new/test_r_ins.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sim_1/new/test_r_ins.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sim_1/new/test_u_ins.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sim_1/new/test_u_ins.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sim_1/new/test_u_ls_ins.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/30 15:34:37 7 | // Design Name: 8 | // Module Name: test_u_ls_ins 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_u_ls_ins( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/imports/new/test_32add.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/29 11:34:46 7 | // Design Name: 8 | // Module Name: test_32add 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_32add( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/imports/new/test_alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/imports/new/test_alu.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/imports/new/test_reg_file.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/imports/new/test_reg_file.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/imports/new/test_top_alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/imports/new/test_top_alu.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/alu.v: -------------------------------------------------------------------------------- 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| -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/cla_adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/new/cla_adder.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/full_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/29 18:56:01 7 | // Design Name: 8 | // Module Name: full_adder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module full_adder(a,b,cin,sum,cout); 24 | 25 | output[31:0] sum; 26 | output cout; 27 | input[31:0] a,b; 28 | input cin; 29 | 30 | assign {cout, sum} = a+b+cin; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/inst_rom.data: -------------------------------------------------------------------------------- 1 | 00206093 2 | 00306113 3 | 00506193 4 | 00108213 5 | 002082b3 6 | 7 | 8 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/inst_rom.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/30 18:20:56 7 | // Design Name: 8 | // Module Name: inst_rom 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module inst_rom( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/is.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/new/is.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/mem_file.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/new/mem_file.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/n_bits.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/new/n_bits.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/pg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/29 12:48:55 7 | // Design Name: 8 | // Module Name: pg 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module pg(a,b,p,g); 23 | input [3:0] a,b; 24 | output [3:0] p,g; 25 | assign p = a|b; 26 | assign g=a&b; 27 | endmodule -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/30 14:07:30 7 | // Design Name: 8 | // Module Name: reg 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module reg( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/reg_file.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_demo/project_demo.srcs/sources_1/new/reg_file.v -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/regfile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/30 14:09:26 7 | // Design Name: 8 | // Module Name: regfile 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module regfile( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/sum.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/29 12:48:55 7 | // Design Name: 8 | // Module Name: sum 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module sum(a,b,c,s); 24 | input [3:0] a,b,c; 25 | output [3:0] s; 26 | wire [3:0] t = a ^ b; 27 | assign s = t ^ c; 28 | endmodule 29 | -------------------------------------------------------------------------------- /project_demo/project_demo.srcs/sources_1/new/test_alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2019/11/30 08:39:25 7 | // Design Name: 8 | // Module Name: test_alu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test_alu( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:38 3 | eof: 4 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.cache/wt/synthesis_details.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 3 | eof:2511430288 4 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:706f73742d73796e746865736973:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:66756e6374696f6e616c:00:00 4 | eof:1988640257 5 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.hw/project_single_cycle.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.runs/synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.runs/synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/alu_top.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.runs/synth_1/alu_top.dcp -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/alu_top_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.runs/synth_1/alu_top_utilization_synth.pb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log alu_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source alu_top.tcl 10 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Sun Dec 1 10:30:38 2019 6 | # Process ID: 4672 7 | # Current directory: D:/vivado_project/project_single_cycle/project_single_cycle.runs/synth_1 8 | # Command line: vivado.exe -log alu_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source alu_top.tcl 9 | # Log file: D:/vivado_project/project_single_cycle/project_single_cycle.runs/synth_1/alu_top.vds 10 | # Journal file: D:/vivado_project/project_single_cycle/project_single_cycle.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source alu_top.tcl -notrace 13 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2017.4 2 | Time resolution is 1 ps 3 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_b_inst.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_b_inst_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_b_inst_behav.wdb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_cpu_top.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_cpu_top_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_cpu_top_behav.wdb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_id.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_id_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_id_behav.wdb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_id_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../project_single_cycle.srcs/sources_1/new/id.v" \ 4 | "../../../../project_single_cycle.srcs/sim_1/new/test_id.v" \ 5 | 6 | # compile glbl module 7 | verilog xil_defaultlib "glbl.v" 8 | 9 | # Do not sort compile order 10 | nosort 11 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_j_inst.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_j_inst_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_j_inst_behav.wdb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_pc.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_pc_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_pc_behav.wdb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/test_pc_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../project_single_cycle.srcs/sources_1/new/inst_rom.v" \ 4 | "../../../../project_single_cycle.srcs/sources_1/new/next_pc.v" \ 5 | "../../../../project_single_cycle.srcs/sources_1/new/pc_reg.v" \ 6 | "../../../../project_single_cycle.srcs/sim_1/new/test_pc.v" \ 7 | 8 | # compile glbl module 9 | verilog xil_defaultlib "glbl.v" 10 | 11 | # Do not sort compile order 12 | nosort 13 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/xsim.dir/test_b_inst_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "d5bb435768d240a9b6e9ce3d6779f8f0" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_b_inst_behav" "xil_defaultlib.test_b_inst" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/xsim.dir/test_b_inst_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/behav/xsim/xsim.dir/test_b_inst_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- 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Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/synth/func/xsim/test_cpu_top_func_synth.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.sim/sim_1/synth/func/xsim/test_cpu_top_func_synth.wdb -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.sim/sim_1/synth/func/xsim/xelab.pb: -------------------------------------------------------------------------------- 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input jump, 9 | 10 | output reg[31:0] next_pc 11 | ); 12 | 13 | always @ (*) begin 14 | 15 | if(~ce) 16 | next_pc <= 0; 17 | else 18 | if(branch & zero || jump) 19 | next_pc <= pc + imm; 20 | else 21 | next_pc <= pc + 4'h4; 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /project_single_cycle/project_single_cycle.srcs/sources_1/new/reg_file.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fuzhidai/CPU-Design-Based-on-RISC-V/4189b82bb7b325f6eba4b029f2791be20c02bf0b/project_single_cycle/project_single_cycle.srcs/sources_1/new/reg_file.v --------------------------------------------------------------------------------