├── .gitignore ├── include ├── pd_rx.h ├── pd.h ├── pd_config.h ├── crc32.h ├── pd_tx.h ├── README ├── pd_coding.h ├── pd_types.h └── pd_proto.h ├── src ├── CMakeLists.txt ├── main.c ├── crc32.c ├── cmd.c ├── pd_rx.c ├── pd_tx.c ├── pd_proto.c └── pd.c ├── CMakeLists.txt ├── platformio.ini ├── lib └── README ├── README.md └── sdkconfig.lolin_c3_mini /.gitignore: -------------------------------------------------------------------------------- 1 | .pio 2 | .vscode/.browse.c_cpp.db* 3 | .vscode/c_cpp_properties.json 4 | .vscode/launch.json 5 | .vscode/ipch 6 | -------------------------------------------------------------------------------- /include/pd_rx.h: -------------------------------------------------------------------------------- 1 | 2 | #pragma once 3 | 4 | #include 5 | #include "pd_types.h" 6 | 7 | 8 | void pd_rx_start(); 9 | void pd_rx_init(); 10 | void pd_rx_loop(); 11 | bool pd_rx_ongoing(); 12 | -------------------------------------------------------------------------------- /src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # This file was automatically generated for projects 2 | # without default 'CMakeLists.txt' file. 3 | 4 | FILE(GLOB_RECURSE app_sources ${CMAKE_SOURCE_DIR}/src/*.*) 5 | 6 | idf_component_register(SRCS ${app_sources}) 7 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.16.0) 2 | include($ENV{IDF_PATH}/tools/cmake/project.cmake) 3 | project(ESP32C3_PD) 4 | 5 | 6 | # Add extra component directories 7 | set(EXTRA_COMPONENT_DIRS 8 | ${IDF_PATH}/examples/system/console/advanced/components/cmd_system 9 | ${IDF_PATH}/examples/system/console/advanced/components/cmd_nvs 10 | ${IDF_PATH}/examples/system/console/advanced/components/cmd_wifi 11 | ) 12 | -------------------------------------------------------------------------------- /include/pd.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include "pd_types.h" 4 | 5 | #define PD_REQUEST_REFRESH_MS 2000 6 | 7 | void pd_mode(pd_mode_t mode); 8 | void pd_init(); 9 | void pd_state_reset(); 10 | 11 | void pd_request_timer(); 12 | void pd_refresh_request(bool immediate); 13 | void pd_request(uint8_t object, uint32_t current_ma, bool immediate); 14 | void pd_request_pps(uint8_t object, uint32_t voltage_mv, uint32_t current_ma, bool immediate); 15 | void pd_send_control(pd_message_type_t message_id); 16 | 17 | -------------------------------------------------------------------------------- /include/pd_config.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include "pd_types.h" 5 | 6 | 7 | // #define GPIO_CC1 3 8 | #define GPIO_PD 4 9 | #define GPIO_TX 3 10 | #define GPIO_CC1_IN 0 11 | 12 | #define PD_BUFFER_COUNT 64 13 | 14 | #define PD_RX_ACK_TASK_PRIO (configMAX_PRIORITIES - 1) 15 | #define PD_PROTOCOL_TASK_PRIO (configMAX_PRIORITIES - 2) 16 | #define PD_TX_TASK_PRIO (configMAX_PRIORITIES - 2) 17 | #define PD_LOG_TASK_PRIO (tskIDLE_PRIORITY + 1) 18 | 19 | 20 | //#define PD_TEST_EMARKER_CABLE 21 | #define PD_LOG_TX_PACKETS 22 | -------------------------------------------------------------------------------- /include/crc32.h: -------------------------------------------------------------------------------- 1 | /* -*- Mode: C; tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*- */ 2 | /* 3 | * Copyright 2011-Present Couchbase, Inc. 4 | * 5 | * Use of this software is governed by the Business Source License included 6 | * in the file licenses/BSL-Couchbase.txt. As of the Change Date specified 7 | * in that file, in accordance with the Business Source License, use of this 8 | * software will be governed by the Apache License, Version 2.0, included in 9 | * the file licenses/APL2.txt. 10 | */ 11 | #pragma once 12 | 13 | #include 14 | #include 15 | 16 | uint32_t crc32buf(const uint8_t* buf, size_t len); 17 | -------------------------------------------------------------------------------- /platformio.ini: -------------------------------------------------------------------------------- 1 | ; PlatformIO Project Configuration File 2 | ; 3 | ; Build options: build flags, source filter 4 | ; Upload options: custom upload port, speed and extra flags 5 | ; Library options: dependencies, extra library storages 6 | ; Advanced options: extra scripting 7 | ; 8 | ; Please visit documentation for the other options and examples 9 | ; https://docs.platformio.org/page/projectconf.html 10 | 11 | [env:lolin_c3_mini] 12 | platform = espressif32 13 | board = lolin_c3_mini 14 | framework = espidf 15 | upload_port = COM19 16 | upload_protocol = esptool 17 | upload_flags = 18 | --before 19 | default_reset 20 | --after 21 | hard_reset 22 | -------------------------------------------------------------------------------- /include/pd_tx.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include "pd_types.h" 5 | #include "pd_proto.h" 6 | 7 | void pd_tx_init(); 8 | 9 | /* check if a transmission is ongoing */ 10 | bool pd_tx_ongoing(); 11 | 12 | /* ToDo: Change the TX routines such that the checksum is automatically calculated 13 | _OR_ create functions to build various packets and payloads which finally calc the CRC. 14 | Right now the caller needs to calculate checksums on its own. 15 | also: take care about retransmission when missing GoodCRC 16 | */ 17 | 18 | /* send a raw message on the CC line after checking it is idle */ 19 | void pd_tx(const uint8_t *data, size_t length); 20 | 21 | /* enqueue an message for tx */ 22 | void pd_tx_enqueue(pd_msg *msg); 23 | 24 | /* send a message on the CC line directly. assume it is free. used for rx confirmation */ 25 | void pd_tx_start(const uint8_t *data, size_t length); 26 | 27 | 28 | void pd_tx_ack_received(uint32_t msg_id); 29 | 30 | /* helper to build a header. need a proper packet factory. */ 31 | uint16_t pd_tx_header( 32 | uint8_t extended, 33 | uint8_t num_data_objects, 34 | uint8_t message_id, 35 | uint8_t power_role, 36 | uint8_t spec_revision, 37 | uint8_t data_role, 38 | uint8_t message_type); 39 | 40 | -------------------------------------------------------------------------------- /lib/README: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for project specific (private) libraries. 3 | PlatformIO will compile them to static libraries and link into executable file. 4 | 5 | The source code of each library should be placed in an own separate directory 6 | ("lib/your_library_name/[here are source files]"). 7 | 8 | For example, see a structure of the following two libraries `Foo` and `Bar`: 9 | 10 | |--lib 11 | | | 12 | | |--Bar 13 | | | |--docs 14 | | | |--examples 15 | | | |--src 16 | | | |- Bar.c 17 | | | |- Bar.h 18 | | | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html 19 | | | 20 | | |--Foo 21 | | | |- Foo.c 22 | | | |- Foo.h 23 | | | 24 | | |- README --> THIS FILE 25 | | 26 | |- platformio.ini 27 | |--src 28 | |- main.c 29 | 30 | and a contents of `src/main.c`: 31 | ``` 32 | #include 33 | #include 34 | 35 | int main (void) 36 | { 37 | ... 38 | } 39 | 40 | ``` 41 | 42 | PlatformIO Library Dependency Finder will find automatically dependent 43 | libraries scanning project source files. 44 | 45 | More information about PlatformIO Library Dependency Finder 46 | - https://docs.platformio.org/page/librarymanager/ldf.html 47 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | 2 | #include "esp_system.h" 3 | #include "esp_console.h" 4 | #include "esp_flash.h" 5 | #include "esp_rom_gpio.h" 6 | #include "esp_timer.h" 7 | #include "esp_chip_info.h" 8 | #include "esp_efuse.h" 9 | #include "esp_log.h" 10 | #include "esp_mac.h" 11 | #include "esp_random.h" 12 | #include "nvs.h" 13 | #include "nvs_flash.h" 14 | #include "driver/gpio.h" 15 | #include "driver/ledc.h" 16 | #include "freertos/FreeRTOS.h" 17 | #include "freertos/task.h" 18 | 19 | #include "pd_config.h" 20 | #include "pd_rx.h" 21 | #include "pd_tx.h" 22 | #include "pd.h" 23 | 24 | #define TAG "ESP32-PD" 25 | 26 | void cmd_init(void); 27 | void cmd_main(void); 28 | 29 | static void initialize_nvs(void) 30 | { 31 | esp_err_t err = nvs_flash_init(); 32 | if (err == ESP_ERR_NVS_NO_FREE_PAGES || err == ESP_ERR_NVS_NEW_VERSION_FOUND) 33 | { 34 | ESP_ERROR_CHECK(nvs_flash_erase()); 35 | err = nvs_flash_init(); 36 | } 37 | ESP_ERROR_CHECK(err); 38 | } 39 | 40 | void app_main() 41 | { 42 | vTaskDelay(1000 / portTICK_PERIOD_MS); 43 | ESP_LOGI(TAG, "Starting up"); 44 | 45 | ESP_LOGI(TAG, " * Initialize IDLE"); 46 | 47 | /* my test setup has the 5k1 PD connected to a GPIO so i can toggle connect/disconnect */ 48 | pd_mode(PD_MODE_IDLE); 49 | vTaskDelay(1000 / portTICK_PERIOD_MS); 50 | 51 | pd_init(); 52 | 53 | ESP_LOGI(TAG, " * Main loop"); 54 | 55 | cmd_init(); 56 | 57 | cmd_main(); 58 | while (true) 59 | { 60 | vTaskDelay(100 / portTICK_PERIOD_MS); 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /include/README: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for project header files. 3 | 4 | A header file is a file containing C declarations and macro definitions 5 | to be shared between several project source files. You request the use of a 6 | header file in your project source file (C, C++, etc) located in `src` folder 7 | by including it, with the C preprocessing directive `#include'. 8 | 9 | ```src/main.c 10 | 11 | #include "header.h" 12 | 13 | int main (void) 14 | { 15 | ... 16 | } 17 | ``` 18 | 19 | Including a header file produces the same results as copying the header file 20 | into each source file that needs it. Such copying would be time-consuming 21 | and error-prone. With a header file, the related declarations appear 22 | in only one place. If they need to be changed, they can be changed in one 23 | place, and programs that include the header file will automatically use the 24 | new version when next recompiled. The header file eliminates the labor of 25 | finding and changing all the copies as well as the risk that a failure to 26 | find one copy will result in inconsistencies within a program. 27 | 28 | In C, the usual convention is to give header files names that end with `.h'. 29 | It is most portable to use only letters, digits, dashes, and underscores in 30 | header file names, and at most one dot. 31 | 32 | Read more about using header files in official GCC documentation: 33 | 34 | * Include Syntax 35 | * Include Operation 36 | * Once-Only Headers 37 | * Computed Includes 38 | 39 | https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html 40 | -------------------------------------------------------------------------------- /include/pd_coding.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include "pd_types.h" 5 | 6 | 7 | /* Array mapping 5b symbols to corresponding 4b values or special symbols */ 8 | static IRAM_ATTR const line_code_symbol_t line_code_decode[32] = { 9 | ERROR, /* 00000 Shall Not be used */ 10 | ERROR, /* 00001 Shall Not be used */ 11 | ERROR, /* 00010 Shall Not be used */ 12 | ERROR, /* 00011 Shall Not be used */ 13 | ERROR, /* 00100 Shall Not be used */ 14 | ERROR, /* 00101 Shall Not be used */ 15 | SYNC_3, /* 00110 Startsynch #3 */ 16 | RST_1, /* 00111 Hard Reset #1 */ 17 | ERROR, /* 01000 Shall Not be used */ 18 | HEX_1, /* 01001 hex data 1 */ 19 | HEX_4, /* 01010 hex data 4 */ 20 | HEX_5, /* 01011 hex data 5 */ 21 | ERROR, /* 01100 Shall Not be used */ 22 | EOP, /* 01101 EOP End of Packet */ 23 | HEX_6, /* 01110 hex data 6 */ 24 | HEX_7, /* 01111 hex data 7 */ 25 | ERROR, /* 10000 Shall Not be used */ 26 | SYNC_2, /* 10001 Startsynch #2 */ 27 | HEX_8, /* 10010 hex data 8 */ 28 | HEX_9, /* 10011 hex data 9 */ 29 | HEX_2, /* 10100 hex data 2 */ 30 | HEX_3, /* 10101 hex data 3 */ 31 | HEX_A, /* 10110 hex data A */ 32 | HEX_B, /* 10111 hex data B */ 33 | SYNC_1, /* 11000 Startsynch #1 */ 34 | RST_2, /* 11001 Hard Reset #2 */ 35 | HEX_C, /* 11010 hex data C */ 36 | HEX_D, /* 11011 hex data D */ 37 | HEX_E, /* 11100 hex data E */ 38 | HEX_F, /* 11101 hex data F */ 39 | HEX_0, /* 11110 hex data 0 */ 40 | ERROR, /* 11111 Shall Not be used */ 41 | }; 42 | 43 | /* Array mapping 5b symbols to corresponding 4b values or special symbols */ 44 | static IRAM_ATTR const line_code_symbol_t line_code_encode[] = { 45 | 0b11110, 46 | 0b01001, 47 | 0b10100, 48 | 0b10101, 49 | 0b01010, 50 | 0b01011, 51 | 0b01110, 52 | 0b01111, 53 | 0b10010, 54 | 0b10011, 55 | 0b10110, 56 | 0b10111, 57 | 0b11010, 58 | 0b11011, 59 | 0b11100, 60 | 0b11101, 61 | 0b11000, /* SYNC_1 */ 62 | 0b10001, /* SYNC_2 */ 63 | 0b00111, /* RST_1 */ 64 | 0b11001, /* RST_2 */ 65 | 0b01101, /* EOP */ 66 | 0b00110 /* SYNC_3 */ 67 | }; 68 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | # ESP32-C3 USB PD Hacky Stack 3 | 4 | A lightweight and experimental USB Power Delivery (PD) stack for the ESP32-C3. This project enables the ESP32-C3 to request voltages from a power supply, sniff and log PD communication, and inject commands for experimentation with Vendor Defined Messages (VDM). 5 | 6 | ## Why This Project? 7 | 8 | Typical USB PD solutions require external ICs like the CH224K, which can be as large as the ESP32 itself. This implementation replaces such ICs with a minimalistic approach using **MUN5233 NPN transistors with a monolithic bias resistor network** ([datasheet](https://www.farnell.com/datasheets/1672232.pdf)) for voltage level conversion. 9 | 10 | - **RX Path:** Converts the 0-1.2V CC signal to 3.3V using a MUN5233 transistor and the IO in weak mode as a pull up. 11 | - **TX Path:** Either directly drives with 3.3V (very hacky) or uses two outputs driving against each other, reducing voltage to approximately 1.7V - still outside protocol spec but works with all tested devices. 12 | 13 | Just good enough for your casual DIY project, saving you another huge component on your design. 14 | 15 | ## Features 16 | 17 | - **USB PD Communication:** Successfully requests user-defined voltage and maximum current from a USB PD power supply. 18 | - **Sniffing & Logging:** Monitor and log USB PD communication on the CC line. 19 | - **Command Injection:** Send messages to experiment with PD communication, including Vendor Defined Messages (VDM). 20 | - **Minimal Hardware Footprint:** Removes the need for bulky PD controllers by leveraging simple transistor-based level shifting. 21 | - **Exploits** the GPIOs capabilities by intentionally using them as weak outputs being driven to GND by the transistor or the CC-line. It's all still inside the specs, yet nothing one would really use for a reliable field design. 22 | - Uses one GPIO for receiving and one GPIO (far beyond PD spec) or two GPIOs (closer to PD spec) for driving one CC line with 3.3V/1.7V, whilst both variants seem to work reliable. 23 | 24 | ## Current State 25 | 26 | The implementation is capable of successfully requesting a user-defined voltage and maximum current from a USB PD power supply. It operates using a hacky but functional method of voltage level shifting for communication. Although outside the official PD specifications, it has been tested and confirmed to work with multiple devices. 27 | It is outside the spec for the protocol encoding - but still a valid voltage on that line(!). In worst case scenario, the power supply will issue a PD protocol recovery over and over. 28 | Also the current state does only drive one CC-line. So in your design you have to combine the CC1/CC2 into one pin, which works not so reliable with all cables [as raspberry users have noticed](https://www.scorpia.co.uk/2019/06/28/pi4-not-working-with-some-chargers-or-why-you-need-two-cc-resistors/) **or** simply rotate the plug if the device doesn't come up. 29 | 30 | Alternatively use the second transistor in the MUN5233 to drive the same ESP32 RX pin low (unverified) and use a second TX pin, driving the second CC line as well. Needs another (or two) GPIOs. Something for next year or so :) 31 | 32 | ## TODOs & Improvements 33 | 34 | - **Code cleanup:** Currently, the caller must calculate checksums. The TX path should handle CRC. A separate logging task, as sending responses is time critical. A lot of small things that should get cleaned up. 35 | - **Retransmission Handling:** Implement automatic retransmission when a GoodCRC is missing. 36 | - **Improved Packet Factory:** Functions to construct different PD packets with proper encapsulation. 37 | 38 | ## Hardware Requirements 39 | 40 | - **ESP32-C3** 41 | - **MUN5233 NPN Transistor** I am using the MUN5233DW with two transistors ([datasheet](https://www.farnell.com/datasheets/1672232.pdf)) 42 | - **5.1kΩ** pulldown on CC 43 | - **USB PD Power Supply** 44 | - **CC Line Access** for monitoring/sniffing 45 | 46 | ## Disclaimer 47 | 48 | This project is an experimental, hacky implementation and does not fully comply with USB PD specifications. Use at your own risk! 49 | If you want to contribute, please do so. I will happily share access to the repository. 50 | 51 | ---------- 52 | 53 | ## License 54 | 55 | MIT License 56 | -------------------------------------------------------------------------------- /include/pd_types.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #define BUILD_LE_UINT16(arr, idx) ((arr[(idx)]) | ((arr[(idx) + 1]) << 8)) 6 | #define BUILD_LE_UINT32(arr, idx) ((arr[(idx)]) | ((arr[(idx) + 1]) << 8) | ((arr[(idx) + 2]) << 16) | ((arr[(idx) + 3]) << 24)) 7 | 8 | #define SPLIT_LE_UINT16(val, arr, idx) \ 9 | do \ 10 | { \ 11 | arr[(idx)] = (val) & 0xFF; \ 12 | arr[(idx) + 1] = ((val) >> 8) & 0xFF; \ 13 | } while (0) 14 | 15 | #define SPLIT_LE_UINT32(val, arr, idx) \ 16 | do \ 17 | { \ 18 | arr[(idx)] = (val) & 0xFF; \ 19 | arr[(idx) + 1] = ((val) >> 8) & 0xFF; \ 20 | arr[(idx) + 2] = ((val) >> 16) & 0xFF; \ 21 | arr[(idx) + 3] = ((val) >> 24) & 0xFF; \ 22 | } while (0) 23 | 24 | /* Enum for special 4b5b symbols */ 25 | typedef enum 26 | { 27 | HEX_0 = 0x0, 28 | HEX_1 = 0x1, 29 | HEX_2 = 0x2, 30 | HEX_3 = 0x3, 31 | HEX_4 = 0x4, 32 | HEX_5 = 0x5, 33 | HEX_6 = 0x6, 34 | HEX_7 = 0x7, 35 | HEX_8 = 0x8, 36 | HEX_9 = 0x9, 37 | HEX_A = 0xA, 38 | HEX_B = 0xB, 39 | HEX_C = 0xC, 40 | HEX_D = 0xD, 41 | HEX_E = 0xE, 42 | HEX_F = 0xF, 43 | SYNC_1 = 0x10, 44 | SYNC_2 = 0x11, 45 | RST_1 = 0x12, 46 | RST_2 = 0x13, 47 | EOP = 0x14, 48 | SYNC_3 = 0x15, 49 | ERROR = 0xFF 50 | } line_code_symbol_t; 51 | 52 | typedef enum 53 | { 54 | PD_BUF_TYPE_INVALID = 0, 55 | PD_BUF_TYPE_TIMINGS, 56 | PD_BUF_TYPE_SYMBOLS, 57 | PD_BUF_TYPE_DATA, 58 | } buf_type_t; 59 | 60 | typedef enum 61 | { 62 | PD_TARGET_SOP, 63 | PD_TARGET_SOP_P, 64 | PD_TARGET_SOP_PP, 65 | PD_TARGET_SOP_PD, 66 | PD_TARGET_SOP_PPD, 67 | PD_TARGET_HARD_RESET, 68 | PD_TARGET_CABLE_RESET, 69 | } pd_rx_target_t; 70 | 71 | #define TARGET_SOP (SYNC_1 | (SYNC_1 << 8) | (SYNC_1 << 16) | (SYNC_2 << 24)) 72 | #define TARGET_SOP_P (SYNC_1 | (SYNC_1 << 8) | (SYNC_3 << 16) | (SYNC_3 << 24)) 73 | #define TARGET_SOP_PP (SYNC_1 | (SYNC_3 << 8) | (SYNC_1 << 16) | (SYNC_3 << 24)) 74 | #define TARGET_SOP_PD (SYNC_1 | (RST_2 << 8) | (RST_2 << 16) | (SYNC_3 << 24)) 75 | #define TARGET_SOP_PPD (SYNC_1 | (RST_2 << 8) | (SYNC_3 << 16) | (SYNC_2 << 24)) 76 | #define TARGET_HARD_RESET (RST_1 | (RST_1 << 8) | (RST_1 << 16) | (RST_2 << 24)) 77 | #define TARGET_CABLE_RESET (RST_1 | (SYNC_1 << 8) | (RST_1 << 16) | (SYNC_3 << 24)) 78 | 79 | typedef enum 80 | { 81 | PD_RX_INIT = 0, 82 | PD_RX_PREAMBLE, 83 | PD_RX_SOP, 84 | PD_RX_PAYLOAD, 85 | PD_RX_FINISHED 86 | } pd_rx_state_t; 87 | 88 | typedef enum 89 | { 90 | PD_TX_PATTERN, 91 | PD_TX_SYNC, 92 | PD_TX_DATA, 93 | PD_TX_EOP, 94 | PD_TX_DONE 95 | } pd_tx_state_t; 96 | 97 | typedef enum 98 | { 99 | PD_PACKET_RECEIVED, 100 | PD_PACKET_RECEIVED_ACKNOWLEDGED, 101 | PD_PACKET_SENT, 102 | PD_PACKET_SENT_ACKNOWLEDGED 103 | } pd_packet_dir_t; 104 | 105 | typedef struct 106 | { 107 | pd_rx_target_t target; 108 | uint8_t message_id; 109 | } pd_rx_ack_t; 110 | 111 | typedef struct 112 | { 113 | /* - PD working variables - */ 114 | pd_rx_state_t state; 115 | 116 | /* - BMC working variables - */ 117 | uint32_t bit_count; 118 | uint32_t bit_data; 119 | bool short_pulse; 120 | int last_shortened; 121 | /* we have 2 bytes for header, 7*4 for payload, 4 for checksum and one EOP symbol */ 122 | int symbol_count; 123 | uint8_t symbols[/*2 * (2 + 7 * 4 + 4) + 1 */ 256]; 124 | 125 | /* - parsed data for next layer - */ 126 | pd_packet_dir_t dir; 127 | pd_rx_target_t target; 128 | buf_type_t type; 129 | uint8_t length; 130 | uint8_t payload[/*2 + 7 * 4 + 4 */ 256]; 131 | 132 | uint64_t start_time; 133 | } pd_rx_buf_t; 134 | 135 | typedef struct 136 | { 137 | bool level; 138 | uint8_t data_pos; 139 | uint8_t sync_bits; 140 | uint8_t sync_symbols; 141 | uint8_t eop_symbols; 142 | pd_tx_state_t state; 143 | } pd_tx_ctx_t; 144 | 145 | typedef struct 146 | { 147 | bool connected; 148 | uint8_t message_id; 149 | uint8_t requested_object; 150 | bool requested_pps; 151 | uint8_t accepted_object; 152 | uint32_t request_voltage_mv; 153 | uint32_t request_current_ma; 154 | uint64_t request_last_timestamp; 155 | } pd_state_t; 156 | 157 | typedef enum 158 | { 159 | PD_CONTROL_RESERVED = 0x00, 160 | PD_CONTROL_GOOD_CRC = 0x01, 161 | PD_CONTROL_GOTO_MIN = 0x02, /* Deprecated */ 162 | PD_CONTROL_ACCEPT = 0x03, 163 | PD_CONTROL_REJECT = 0x04, 164 | PD_CONTROL_PING = 0x05, /* Deprecated */ 165 | PD_CONTROL_PS_RDY = 0x06, 166 | PD_CONTROL_GET_SOURCE_CAP = 0x07, 167 | PD_CONTROL_GET_SINK_CAP = 0x08, 168 | PD_CONTROL_DR_SWAP = 0x09, 169 | PD_CONTROL_PR_SWAP = 0x0A, 170 | PD_CONTROL_VCONN_SWAP = 0x0B, 171 | PD_CONTROL_WAIT = 0x0C, 172 | PD_CONTROL_SOFT_RESET = 0x0D, 173 | PD_CONTROL_DATA_RESET = 0x0E, 174 | PD_CONTROL_DATA_RESET_COMPLETE = 0x0F, 175 | PD_CONTROL_NOT_SUPPORTED = 0x10, 176 | PD_CONTROL_GET_SOURCE_CAP_EXTENDED = 0x11, 177 | PD_CONTROL_GET_STATUS = 0x12, 178 | PD_CONTROL_FR_SWAP = 0x13, 179 | PD_CONTROL_GET_PPS_STATUS = 0x14, 180 | PD_CONTROL_GET_COUNTRY_CODES = 0x15, 181 | PD_CONTROL_GET_SINK_CAP_EXTENDED = 0x16, 182 | PD_CONTROL_GET_SOURCE_INFO = 0x17, 183 | PD_CONTROL_GET_REVISION = 0x18, 184 | PD_DATA_SOURCE_CAPABILITIES = 0x01, 185 | PD_DATA_REQUEST = 0x02, 186 | PD_DATA_BIST = 0x03, 187 | PD_DATA_SINK_CAPABILITIES = 0x04, 188 | PD_DATA_BATTERY_STATUS = 0x05, 189 | PD_DATA_ALERT = 0x06, 190 | PD_DATA_GET_COUNTRY_INFO = 0x07, 191 | PD_DATA_ENTER_USB = 0x08, 192 | PD_DATA_EPR_REQUEST = 0x09, 193 | PD_DATA_EPR_MODE = 0x0A, 194 | PD_DATA_SOURCE_INFO = 0x0B, 195 | PD_DATA_REVISION = 0x0C, 196 | PD_VENDOR_MESSAGE = 0x0F 197 | } pd_message_type_t; 198 | 199 | typedef enum 200 | { 201 | PD_MODE_IDLE, 202 | PD_MODE_SINK 203 | } pd_mode_t; 204 | -------------------------------------------------------------------------------- /include/pd_proto.h: -------------------------------------------------------------------------------- 1 | 2 | #pragma once 3 | 4 | #define EXTENDED_SHIFT 15 5 | #define EXTENDED_MASK 0x01 6 | #define NUM_DATA_OBJ_SHIFT 12 7 | #define NUM_DATA_OBJ_MASK 0x07 8 | #define MESSAGE_ID_SHIFT 9 9 | #define MESSAGE_ID_MASK 0x07 10 | #define POWER_ROLE_SHIFT 8 11 | #define POWER_ROLE_MASK 0x01 12 | #define SPEC_REVISION_SHIFT 6 13 | #define SPEC_REVISION_MASK 0x03 14 | #define DATA_ROLE_SHIFT 5 15 | #define DATA_ROLE_MASK 0x01 16 | #define MESSAGE_TYPE_MASK 0x1F 17 | 18 | /* Structured VDM Header */ 19 | #define SVID_SHIFT 16 20 | #define VDM_TYPE_SHIFT 15 21 | #define VDM_VERSION_SHIFT 13 22 | #define VDM_MINOR_SHIFT 11 23 | #define OBJ_POS_SHIFT 8 24 | #define CMD_TYPE_SHIFT 6 25 | #define COMMAND_SHIFT 0 26 | 27 | #define SVID_MASK 0x0000FFFF 28 | #define VDM_TYPE_MASK 0x00000001 29 | #define VDM_VERSION_MASK 0x00000003 30 | #define VDM_MINOR_MASK 0x00000003 31 | #define OBJ_POS_MASK 0x00000007 32 | #define CMD_TYPE_MASK 0x00000003 33 | #define RESERVED_MASK 0x00000001 34 | #define COMMAND_MASK 0x0000001F 35 | 36 | #define PD_VDM_SID_PD 0xFF00 37 | 38 | /* ID Header VDO */ 39 | #define USB_HOST_SHIFT 31 40 | #define USB_DEVICE_SHIFT 30 41 | #define SOP_PRODUCT_TYPE_SHIFT 27 42 | #define MODAL_OPERATION_SHIFT 26 43 | #define USB_VENDOR_ID_SHIFT 0 44 | 45 | #define USB_HOST_MASK 0x00000001 46 | #define USB_DEVICE_MASK 0x00000001 47 | #define SOP_PRODUCT_TYPE_MASK 0x00000007 48 | #define MODAL_OPERATION_MASK 0x00000001 49 | #define USB_VENDOR_ID_MASK 0x0000FFFF 50 | 51 | /* Product VDO */ 52 | #define USB_PRODUCT_ID_SHIFT 16 53 | #define BCD_DEVICE_SHIFT 0 54 | 55 | #define USB_PRODUCT_ID_MASK 0x0000FFFF 56 | #define BCD_DEVICE_MASK 0x0000FFFF 57 | 58 | /* Cable VDO1 */ 59 | #define HW_VERSION_SHIFT 28 60 | #define FW_VERSION_SHIFT 24 61 | #define VDO_VERSION_SHIFT 21 62 | #define PLUG_TYPE_SHIFT 18 63 | #define EPR_CAPABLE_SHIFT 17 64 | #define CABLE_LATENCY_SHIFT 13 65 | #define CABLE_TERMINATION_SHIFT 11 66 | #define MAX_VBUS_VOLTAGE_SHIFT 9 67 | #define SBU_SUPPORTED_SHIFT 8 68 | #define SBU_TYPE_SHIFT 7 69 | #define VBUS_CURRENT_SHIFT 5 70 | #define VBUS_THROUGH_SHIFT 4 71 | #define SOP_CONTROLLER_SHIFT 3 72 | #define USB_SPEED_SHIFT 0 73 | 74 | #define HW_VERSION_MASK 0x0000000F 75 | #define FW_VERSION_MASK 0x0000000F 76 | #define VDO_VERSION_MASK 0x00000007 77 | #define PLUG_TYPE_MASK 0x00000003 78 | #define EPR_CAPABLE_MASK 0x00000001 79 | #define CABLE_LATENCY_MASK 0x0000000F 80 | #define CABLE_TERMINATION_MASK 0x00000003 81 | #define MAX_VBUS_VOLTAGE_MASK 0x00000003 82 | #define SBU_SUPPORTED_MASK 0x00000001 83 | #define SBU_TYPE_MASK 0x00000001 84 | #define VBUS_CURRENT_MASK 0x00000003 85 | #define VBUS_THROUGH_MASK 0x00000001 86 | #define SOP_CONTROLLER_MASK 0x00000001 87 | #define USB_SPEED_MASK 0x00000007 88 | 89 | /* Cable VDO2 */ 90 | #define MAX_OPERATING_TEMP_SHIFT 24 91 | #define SHUTDOWN_TEMP_SHIFT 16 92 | #define U3_CLD_POWER_SHIFT 12 93 | #define U3_TO_U0_TRANSITION_SHIFT 11 94 | #define PHYSICAL_CONNECTION_SHIFT 10 95 | #define ACTIVE_ELEMENT_SHIFT 9 96 | #define USB4_SUPPORTED_SHIFT 8 97 | #define USB2_HUB_HOPS_SHIFT 6 98 | #define USB2_SUPPORTED_SHIFT 5 99 | #define USB3_2_SUPPORTED_SHIFT 4 100 | #define USB_LANES_SUPPORTED_SHIFT 3 101 | #define OPTICALLY_ISOLATED_SHIFT 2 102 | #define USB4_ASYMMETRIC_SHIFT 1 103 | #define USB_GEN_SHIFT 0 104 | 105 | #define MAX_OPERATING_TEMP_MASK 0x000000FF 106 | #define SHUTDOWN_TEMP_MASK 0x000000FF 107 | #define U3_CLD_POWER_MASK 0x00000007 108 | #define U3_TO_U0_TRANSITION_MASK 0x00000001 109 | #define PHYSICAL_CONNECTION_MASK 0x00000001 110 | #define ACTIVE_ELEMENT_MASK 0x00000001 111 | #define USB4_SUPPORTED_MASK 0x00000001 112 | #define USB2_HUB_HOPS_MASK 0x00000003 113 | #define USB2_SUPPORTED_MASK 0x00000001 114 | #define USB3_2_SUPPORTED_MASK 0x00000001 115 | #define USB_LANES_SUPPORTED_MASK 0x00000001 116 | #define OPTICALLY_ISOLATED_MASK 0x00000001 117 | #define USB4_ASYMMETRIC_MASK 0x00000001 118 | #define USB_GEN_MASK 0x00000001 119 | 120 | typedef enum 121 | { 122 | PD_VDM_CMD_TYPE_REQ = 0, 123 | PD_VDM_CMD_TYPE_ACK, 124 | PD_VDM_CMD_TYPE_NAK, 125 | PD_VDM_CMD_TYPE_BUSY, 126 | } pd_vdm_cmd_type; 127 | 128 | typedef enum 129 | { 130 | PD_VDM_CMD_DISCOVER_IDENTIY = 1, 131 | PD_VDM_CMD_DISCOVER_SVIDS, 132 | PD_VDM_CMD_DISCOVER_MODES, 133 | PD_VDM_CMD_ENTER_MODE, 134 | PD_VDM_CMD_EXIT_MODE, 135 | PD_VDM_CMD_ATTENTION 136 | } pd_vdm_command; 137 | 138 | typedef enum 139 | { 140 | PD_DATA_ROLE_UFP = 0, 141 | PD_DATA_ROLE_DFP = 1, 142 | PD_DATA_ROLE_CABLE = 1, 143 | } pd_data_role_t; 144 | 145 | typedef struct 146 | { 147 | uint8_t extended; 148 | uint8_t num_data_objects; 149 | uint8_t message_id; 150 | pd_data_role_t power_role; 151 | uint8_t spec_revision; 152 | pd_data_role_t data_role; 153 | pd_message_type_t message_type; 154 | } pd_msg_header; 155 | 156 | typedef struct pd_msg_s pd_msg; 157 | 158 | struct pd_msg_s 159 | { 160 | pd_rx_target_t target; 161 | pd_msg_header header; 162 | uint32_t pdo[7]; 163 | bool immediate; 164 | void (*cbr)(pd_msg *msg, bool success); 165 | void *cbr_private; 166 | }; 167 | 168 | typedef struct 169 | { 170 | uint16_t svid; 171 | uint8_t vdm_type; 172 | uint8_t vdm_version_major; 173 | uint8_t vdm_version_minor; 174 | uint8_t object_position; 175 | pd_vdm_cmd_type command_type; 176 | pd_vdm_command command; 177 | } pd_vdm_header; 178 | 179 | typedef struct 180 | { 181 | uint8_t usb_host; 182 | uint8_t usb_device; 183 | uint8_t sop_product_type; 184 | uint8_t modal_operation; 185 | uint16_t usb_vendor_id; 186 | } pd_vdm_id_header_vdo; 187 | 188 | typedef struct 189 | { 190 | uint32_t usb_if_xid; 191 | } pd_vdm_crt_stat_vdo; 192 | 193 | typedef struct 194 | { 195 | uint16_t usb_product_id; 196 | uint16_t bcd_device; 197 | } pd_vdm_product_vdo; 198 | 199 | typedef struct 200 | { 201 | uint8_t hw_version; 202 | uint8_t fw_version; 203 | uint8_t vdo_version; 204 | uint8_t plug_type; 205 | uint8_t epr_capable; 206 | uint8_t cable_latency; 207 | uint8_t cable_termination; 208 | uint8_t max_vbus_voltage; 209 | uint8_t sbu_supported; 210 | uint8_t sbu_type; 211 | uint8_t vbus_current; 212 | uint8_t vbus_through; 213 | uint8_t sop_controller; 214 | uint8_t usb_speed; 215 | } pd_vdm_cable_vdo1; 216 | 217 | typedef struct 218 | { 219 | uint8_t max_operating_temp; 220 | uint8_t shutdown_temp; 221 | uint8_t u3_cld_power; 222 | uint8_t u3_to_u0_transition; 223 | uint8_t physical_connection; 224 | uint8_t active_element; 225 | uint8_t usb4_supported; 226 | uint8_t usb2_hub_hops; 227 | uint8_t usb2_supported; 228 | uint8_t usb3_2_supported; 229 | uint8_t usb_lanes_supported; 230 | uint8_t optically_isolated; 231 | uint8_t usb4_asymmetric; 232 | uint8_t usb_gen; 233 | } pd_vdm_cable_vdo2; 234 | 235 | typedef struct 236 | { 237 | pd_vdm_header vdm_header; 238 | pd_vdm_id_header_vdo id_header; 239 | pd_vdm_crt_stat_vdo crt_stat; 240 | pd_vdm_product_vdo product; 241 | pd_vdm_cable_vdo1 cable_1; 242 | pd_vdm_cable_vdo2 cable_2; 243 | } pd_vdm_packet; 244 | 245 | void pd_parse_msg_header(pd_msg_header *hdr, uint8_t *data); 246 | void pd_build_msg_header(pd_msg_header *hdr, uint8_t *data); 247 | void pd_dump_msg_header(pd_msg_header *hdr); 248 | 249 | void pd_parse_vdm(pd_vdm_packet *pkt, pd_msg *msg); 250 | void pd_build_vdm(pd_vdm_packet *pkt, pd_msg *msg); 251 | void pd_dump_vdm(pd_vdm_packet *pkt); 252 | -------------------------------------------------------------------------------- /src/crc32.c: -------------------------------------------------------------------------------- 1 | /* Crc - 32 BIT ANSI X3.66 CRC checksum files */ 2 | 3 | /* from https://github.com/couchbase/kv_engine/blob/master/engines/ep/src/crc32.c */ 4 | 5 | #include "freertos/FreeRTOS.h" 6 | #include "freertos/task.h" 7 | 8 | #include "crc32.h" 9 | 10 | /**********************************************************************\ 11 | |* Demonstration program to compute the 32-bit CRC used as the frame *| 12 | |* check sequence in ADCCP (ANSI X3.66, also known as FIPS PUB 71 *| 13 | |* and FED-STD-1003, the U.S. versions of CCITT's X.25 link-level *| 14 | |* protocol). The 32-bit FCS was added via the Federal Register, *| 15 | |* 1 June 1982, p.23798. I presume but don't know for certain that *| 16 | |* this polynomial is or will be included in CCITT V.41, which *| 17 | |* defines the 16-bit CRC (often called CRC-CCITT) polynomial. FIPS *| 18 | |* PUB 78 says that the 32-bit FCS reduces otherwise undetected *| 19 | |* errors by a factor of 10^-5 over 16-bit FCS. *| 20 | \**********************************************************************/ 21 | 22 | /* Need an unsigned type capable of holding 32 bits; */ 23 | 24 | /* Copyright (C) 1986 Gary S. Brown. You may use this program, or 25 | code or tables extracted from it, as desired without restriction.*/ 26 | 27 | /* First, the polynomial itself and its table of feedback terms. The */ 28 | /* polynomial is */ 29 | /* X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 */ 30 | /* Note that we take it "backwards" and put the highest-order term in */ 31 | /* the lowest-order bit. The X^32 term is "implied"; the LSB is the */ 32 | /* X^31 term, etc. The X^0 term (usually shown as "+1") results in */ 33 | /* the MSB being 1. */ 34 | 35 | /* Note that the usual hardware shift register implementation, which */ 36 | /* is what we're using (we're merely optimizing it by doing eight-bit */ 37 | /* chunks at a time) shifts bits into the lowest-order term. In our */ 38 | /* implementation, that means shifting towards the right. Why do we */ 39 | /* do it this way? Because the calculated CRC must be transmitted in */ 40 | /* order from highest-order term to lowest-order term. UARTs transmit */ 41 | /* characters in order from LSB to MSB. By storing the CRC this way, */ 42 | /* we hand it to the UART in the order low-byte to high-byte; the UART */ 43 | /* sends each low-bit to hight-bit; and the result is transmission bit */ 44 | /* by bit from highest- to lowest-order term without requiring any bit */ 45 | /* shuffling on our part. Reception works similarly. */ 46 | 47 | /* The feedback terms table consists of 256, 32-bit entries. Notes: */ 48 | /* */ 49 | /* 1. The table can be generated at runtime if desired; code to do so */ 50 | /* is shown later. It might not be obvious, but the feedback */ 51 | /* terms simply represent the results of eight shift/xor opera- */ 52 | /* tions for all combinations of data and CRC register values. */ 53 | /* */ 54 | /* 2. The CRC accumulation logic is the same for all CRC polynomials, */ 55 | /* be they sixteen or thirty-two bits wide. You simply choose the */ 56 | /* appropriate table. Alternatively, because the table can be */ 57 | /* generated at runtime, you can start by generating the table for */ 58 | /* the polynomial in question and use exactly the same "updcrc", */ 59 | /* if your application needn't simultaneously handle two CRC */ 60 | /* polynomials. (Note, however, that XMODEM is strange.) */ 61 | /* */ 62 | /* 3. For 16-bit CRCs, the table entries need be only 16 bits wide; */ 63 | /* of course, 32-bit entries work OK if the high 16 bits are zero. */ 64 | /* */ 65 | /* 4. The values must be right-shifted by eight bits by the "updcrc" */ 66 | /* logic; the shift must be unsigned (bring in zeroes). On some */ 67 | /* hardware you could probably optimize the shift in assembler by */ 68 | /* using byte-swap instructions. */ 69 | 70 | const uint32_t IRAM_ATTR crc_32_tab[] = {/* CRC polynomial 0xedb88320 */ 71 | 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 72 | 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 73 | 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, 74 | 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 75 | 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 76 | 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 77 | 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, 78 | 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 79 | 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 80 | 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 81 | 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, 82 | 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, 83 | 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 84 | 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 85 | 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, 86 | 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 87 | 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 88 | 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 89 | 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 90 | 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, 91 | 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 92 | 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 93 | 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, 94 | 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 95 | 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 96 | 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 97 | 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, 98 | 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 99 | 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 100 | 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 101 | 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 102 | 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 103 | 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 104 | 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 105 | 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, 106 | 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, 107 | 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 108 | 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 109 | 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 110 | 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, 111 | 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 112 | 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 113 | 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d}; 114 | 115 | #define UPDC32(octet, crc) (crc_32_tab[((crc) ^ (octet)) & 0xff] ^ ((crc) >> 8)) 116 | 117 | uint32_t IRAM_ATTR crc32buf(const uint8_t *buf, size_t len) 118 | { 119 | register uint32_t oldcrc32; 120 | 121 | oldcrc32 = 0xFFFFFFFF; 122 | 123 | for (; len; --len, ++buf) 124 | { 125 | oldcrc32 = UPDC32(*buf, oldcrc32); 126 | } 127 | 128 | return ~oldcrc32; 129 | } 130 | -------------------------------------------------------------------------------- /src/cmd.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | #include 4 | #include 5 | #include "esp_system.h" 6 | #include "esp_log.h" 7 | #include "esp_console.h" 8 | #include "esp_partition.h" 9 | #include "esp_vfs_dev.h" 10 | #include "esp_vfs_fat.h" 11 | #include "nvs.h" 12 | #include "nvs_flash.h" 13 | #include "cmd_system.h" 14 | #include "cmd_wifi.h" 15 | #include "cmd_nvs.h" 16 | #include "argtable3/argtable3.h" 17 | 18 | #include "pd.h" 19 | #include "pd_tx.h" 20 | #include "pd_proto.h" 21 | 22 | #define PROMPT_STR "usb_pd" 23 | #define TAG "cmd" 24 | #define CONFIG_CONSOLE_MAX_COMMAND_LINE_LENGTH 64 25 | 26 | #if SOC_USB_SERIAL_JTAG_SUPPORTED 27 | #if !CONFIG_ESP_CONSOLE_SECONDARY_NONE 28 | #warning "A secondary serial console is not useful when using the console component. Please disable it in menuconfig." 29 | #endif 30 | #endif 31 | 32 | esp_console_repl_t *repl = NULL; 33 | esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); 34 | 35 | static struct 36 | { 37 | struct arg_int *object; 38 | struct arg_int *voltage_mv; 39 | struct arg_int *current_ma; 40 | struct arg_end *end; 41 | } cmd_req_pps_args; 42 | 43 | static struct 44 | { 45 | struct arg_int *object; 46 | struct arg_int *current_ma; 47 | struct arg_end *end; 48 | } cmd_req_obj_args; 49 | 50 | static struct 51 | { 52 | struct arg_int *command; 53 | struct arg_int *mode; 54 | struct arg_end *end; 55 | } cmd_vdm_args; 56 | 57 | static int cmd_req_pps(int argc, char **argv) 58 | { 59 | int nerrors = arg_parse(argc, argv, (void **)&cmd_req_pps_args); 60 | if (nerrors != 0) 61 | { 62 | arg_print_errors(stderr, cmd_req_pps_args.end, argv[0]); 63 | return 1; 64 | } 65 | 66 | uint16_t arg_obj = *cmd_req_pps_args.object->ival; 67 | uint16_t arg_mv = *cmd_req_pps_args.voltage_mv->ival; 68 | uint16_t arg_ma = *cmd_req_pps_args.current_ma->ival; 69 | 70 | pd_request_pps(arg_obj, arg_mv, arg_ma, 0); 71 | 72 | return 0; 73 | } 74 | 75 | static int cmd_req_obj(int argc, char **argv) 76 | { 77 | int nerrors = arg_parse(argc, argv, (void **)&cmd_req_obj_args); 78 | if (nerrors != 0) 79 | { 80 | arg_print_errors(stderr, cmd_req_obj_args.end, argv[0]); 81 | return 1; 82 | } 83 | 84 | uint16_t arg_obj = *cmd_req_pps_args.object->ival; 85 | uint16_t arg_ma = *cmd_req_pps_args.current_ma->ival; 86 | 87 | pd_request(arg_obj, arg_ma, 0); 88 | 89 | return 0; 90 | } 91 | 92 | static int cmd_vdm(int argc, char **argv) 93 | { 94 | int nerrors = arg_parse(argc, argv, (void **)&cmd_vdm_args); 95 | if (nerrors != 0) 96 | { 97 | arg_print_errors(stderr, cmd_vdm_args.end, argv[0]); 98 | return 1; 99 | } 100 | 101 | uint16_t arg_command = *cmd_vdm_args.command->ival; 102 | uint16_t arg_mode = cmd_vdm_args.mode->count ? *cmd_vdm_args.mode->ival : 0; 103 | 104 | pd_msg response = {0}; 105 | 106 | response.target = PD_TARGET_SOP; 107 | response.header.power_role = PD_DATA_ROLE_UFP; 108 | response.header.spec_revision = 1; 109 | response.header.message_type = PD_VENDOR_MESSAGE; 110 | 111 | pd_vdm_packet resp_vdm = { 112 | .vdm_header = { 113 | .svid = PD_VDM_SID_PD, 114 | .vdm_type = 1, 115 | .vdm_version_major = 1, 116 | .vdm_version_minor = 0, 117 | .object_position = arg_mode, 118 | .command_type = PD_VDM_CMD_TYPE_REQ, 119 | .command = (pd_vdm_command)arg_command, 120 | }, 121 | }; 122 | 123 | pd_build_vdm(&resp_vdm, &response); 124 | pd_tx_enqueue(&response); 125 | 126 | return 0; 127 | } 128 | 129 | static int cmd_get_src_cap(int argc, char **argv) 130 | { 131 | pd_send_control(PD_CONTROL_GET_SOURCE_CAP); 132 | 133 | return 0; 134 | } 135 | 136 | static int list_partitions(int argc, char **argv) 137 | { 138 | /* Get the iterator for all partitions */ 139 | const esp_partition_t *partition; 140 | esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL); 141 | 142 | if (it == NULL) 143 | { 144 | printf("No partitions found.\n"); 145 | return ESP_OK; 146 | } 147 | 148 | printf("Partitions:\n"); 149 | printf("------------------------------------------------------------\n"); 150 | printf("| Type | Subtype | Address | Size | Label |\n"); 151 | printf("------------------------------------------------------------\n"); 152 | 153 | /* Iterate through all partitions */ 154 | while (it != NULL) 155 | { 156 | partition = esp_partition_get(it); 157 | printf("| %-11s | %-11s | 0x%08" PRIx32 " | %-7" PRId32 " | %-5s\n", 158 | partition->type == ESP_PARTITION_TYPE_APP ? "app" : "data", 159 | partition->subtype == ESP_PARTITION_SUBTYPE_ANY ? "any" : "specific", 160 | partition->address, 161 | partition->size, 162 | partition->label); 163 | 164 | it = esp_partition_next(it); 165 | } 166 | 167 | printf("------------------------------------------------------------\n"); 168 | 169 | /* Free the iterator */ 170 | esp_partition_iterator_release(it); 171 | return ESP_OK; 172 | } 173 | 174 | const esp_console_cmd_t req_get_src_cap_cmd = { 175 | .command = "get_src_cap", 176 | .help = "Request source capabilities report." 177 | "t.b.d\n", 178 | .hint = NULL, 179 | .func = &cmd_get_src_cap, 180 | .argtable = NULL}; 181 | 182 | const esp_console_cmd_t req_pps_cmd = { 183 | .command = "req_pps", 184 | .help = "Request a PPS mode." 185 | "t.b.d\n", 186 | .hint = NULL, 187 | .func = &cmd_req_pps, 188 | .argtable = &cmd_req_pps_args}; 189 | 190 | const esp_console_cmd_t req_obj_cmd = { 191 | .command = "req_obj", 192 | .help = "Request a normal mode." 193 | "t.b.d\n", 194 | .hint = NULL, 195 | .func = &cmd_req_obj, 196 | .argtable = &cmd_req_obj_args}; 197 | 198 | const esp_console_cmd_t vdm_cmd = { 199 | .command = "vdm", 200 | .help = "Send a Vendor Defined Message (VDM) request.\n" 201 | "\n" 202 | "This command allows sending VDM requests as specified by the USB Power Delivery protocol.\n" 203 | "\n" 204 | "Parameters:\n" 205 | " - command:\n" 206 | " 0 = Reserved, Shall Not be used\n" 207 | " 1 = Discover Identity\n" 208 | " 2 = Discover SVIDs\n" 209 | " 3 = Discover Modes\n" 210 | " 4 = Enter Mode\n" 211 | " 5 = Exit Mode\n" 212 | " 6 = Attention\n" 213 | " 7-15 = Reserved, Shall Not be used\n" 214 | " 16…31 = SVID Specific Commands\n" 215 | "\n" 216 | " - object:\n" 217 | " For Enter Mode, Exit Mode, and Attention Commands (Requests/Responses):\n" 218 | " - 000b = Reserved and Shall Not be used\n" 219 | " - 001b…110b = Index into the list of VDOs to identify the desired Mode VDO\n" 220 | " - 111b = Exit all Active Modes (equivalent to a power-on reset). Shall only be used with the Exit Mode Command.\n" 221 | " Commands 0…3, 7…15:\n" 222 | " - 000b\n" 223 | " - 001b…111b = Reserved and Shall Not be used\n" 224 | " SVID Specific Commands (16…31) are defined by the SVID.\n", 225 | .hint = NULL, 226 | .func = &cmd_vdm, 227 | .argtable = &cmd_vdm_args}; 228 | 229 | const esp_console_cmd_t cmd_list_partitions = { 230 | .command = "list_partitions", 231 | .help = "List all partitions in the device", 232 | .hint = NULL, 233 | .func = &list_partitions, 234 | }; 235 | 236 | void cmd_init() 237 | { 238 | repl_config.prompt = PROMPT_STR ">"; 239 | repl_config.max_cmdline_length = CONFIG_CONSOLE_MAX_COMMAND_LINE_LENGTH; 240 | 241 | /* Register commands */ 242 | esp_console_register_help_command(); 243 | register_system_common(); 244 | #if SOC_LIGHT_SLEEP_SUPPORTED 245 | register_system_light_sleep(); 246 | #endif 247 | #if SOC_DEEP_SLEEP_SUPPORTED 248 | register_system_deep_sleep(); 249 | #endif 250 | #if (CONFIG_ESP_WIFI_ENABLED || CONFIG_ESP_HOST_WIFI_ENABLED) 251 | register_wifi(); 252 | #endif 253 | register_nvs(); 254 | 255 | cmd_req_pps_args.object = arg_int1(NULL, NULL, "", "object index"); 256 | cmd_req_pps_args.voltage_mv = arg_int1(NULL, NULL, "", "requested voltage"); 257 | cmd_req_pps_args.current_ma = arg_int1(NULL, NULL, "", "maximum current"); 258 | cmd_req_pps_args.end = arg_end(2); 259 | 260 | cmd_req_obj_args.object = arg_int1(NULL, NULL, "", "object index"); 261 | cmd_req_obj_args.current_ma = arg_int1(NULL, NULL, "", "maximum current"); 262 | cmd_req_obj_args.end = arg_end(2); 263 | 264 | cmd_vdm_args.command = arg_int1(NULL, NULL, "", "command to send"); 265 | cmd_vdm_args.mode = arg_int0(NULL, NULL, "", "mode to enter"); 266 | cmd_vdm_args.end = arg_end(2); 267 | 268 | ESP_ERROR_CHECK(esp_console_cmd_register(&cmd_list_partitions)); 269 | ESP_ERROR_CHECK(esp_console_cmd_register(&req_pps_cmd)); 270 | ESP_ERROR_CHECK(esp_console_cmd_register(&req_obj_cmd)); 271 | ESP_ERROR_CHECK(esp_console_cmd_register(&req_get_src_cap_cmd)); 272 | ESP_ERROR_CHECK(esp_console_cmd_register(&vdm_cmd)); 273 | } 274 | 275 | void cmd_main(void) 276 | { 277 | #if defined(CONFIG_ESP_CONSOLE_UART_DEFAULT) || defined(CONFIG_ESP_CONSOLE_UART_CUSTOM) 278 | esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); 279 | ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl)); 280 | 281 | #elif defined(CONFIG_ESP_CONSOLE_USB_CDC) 282 | esp_console_dev_usb_cdc_config_t hw_config = ESP_CONSOLE_DEV_CDC_CONFIG_DEFAULT(); 283 | ESP_ERROR_CHECK(esp_console_new_repl_usb_cdc(&hw_config, &repl_config, &repl)); 284 | 285 | #elif defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) 286 | esp_console_dev_usb_serial_jtag_config_t hw_config = ESP_CONSOLE_DEV_USB_SERIAL_JTAG_CONFIG_DEFAULT(); 287 | ESP_ERROR_CHECK(esp_console_new_repl_usb_serial_jtag(&hw_config, &repl_config, &repl)); 288 | 289 | #else 290 | #error Unsupported console type 291 | #endif 292 | 293 | ESP_ERROR_CHECK(esp_console_start_repl(repl)); 294 | } 295 | -------------------------------------------------------------------------------- /src/pd_rx.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "esp_log.h" 5 | #include "esp_timer.h" 6 | 7 | #include "driver/gpio.h" 8 | #include "driver/rmt_rx.h" 9 | 10 | #include "freertos/FreeRTOS.h" 11 | #include "freertos/task.h" 12 | 13 | #include "pd_types.h" 14 | #include "pd_config.h" 15 | #include "pd_coding.h" 16 | #include "pd_rx.h" 17 | #include "pd_tx.h" 18 | #include "pd.h" 19 | #include "crc32.h" 20 | 21 | #define TAG "PD-RX" 22 | 23 | /* PD bit rate is ~600kHz, so use a multiple of that */ 24 | #define PD_RX_FREQ (10000000) 25 | #define PD_RX_SYMS (64) 26 | #define PD_RX_LONG_DURATION (33) /* 3.3us */ 27 | #define PD_RX_SHORT_DURATION (PD_RX_LONG_DURATION / 2) 28 | #define PD_RX_HIGH_DURATION ((PD_RX_SHORT_DURATION * 3) / 2) 29 | 30 | uint8_t pd_dummy_buffer[64 * 4]; 31 | 32 | extern QueueHandle_t pd_queue_rx_ack; 33 | extern QueueHandle_t pd_queue_rx_data; 34 | extern QueueHandle_t pd_queue_empty; 35 | 36 | static rmt_channel_handle_t pd_rx_chan = NULL; 37 | static volatile bool pd_rx_ongoing_flag = false; 38 | 39 | static bool pd_acknowlegde[6] = { 40 | [PD_TARGET_SOP] = true, 41 | #ifdef PD_TEST_EMARKER_CABLE 42 | [PD_TARGET_SOP_P] = true, 43 | [PD_TARGET_SOP_PP] = true, 44 | #endif 45 | }; 46 | 47 | bool IRAM_ATTR 48 | pd_rx_ongoing() 49 | { 50 | return pd_rx_ongoing_flag; 51 | } 52 | 53 | static IRAM_ATTR bool pd_rc_bmc_handle_pulse(uint32_t duration) 54 | { 55 | static pd_rx_buf_t *ctx = NULL; 56 | 57 | /* we care ourselves for our buffers */ 58 | if (!ctx) 59 | { 60 | if (xQueueReceiveFromISR(pd_queue_empty, &ctx, NULL) != pdTRUE) 61 | { 62 | return false; 63 | } 64 | ctx->state = PD_RX_INIT; 65 | ctx->start_time = esp_timer_get_time(); 66 | } 67 | 68 | /* non-pulses are ignored and signal end-of-reception */ 69 | if (!duration) 70 | { 71 | ctx->state = PD_RX_INIT; 72 | return false; 73 | } 74 | 75 | /* first action - initialize working variables */ 76 | if (ctx->state == PD_RX_INIT) 77 | { 78 | memset(ctx, 0x00, sizeof(pd_rx_buf_t)); 79 | ctx->state = PD_RX_PREAMBLE; 80 | } 81 | 82 | /* grant some extra time if the first short one was very short */ 83 | bool long_pulse = (duration > PD_RX_HIGH_DURATION + ctx->last_shortened); 84 | if (!long_pulse && duration > PD_RX_SHORT_DURATION) 85 | { 86 | ctx->last_shortened = PD_RX_SHORT_DURATION - duration; 87 | } 88 | else 89 | { 90 | ctx->last_shortened = 0; 91 | } 92 | 93 | /* depending on the last state, handle long and short pulses */ 94 | if (ctx->short_pulse) 95 | { 96 | ctx->short_pulse = false; 97 | 98 | /* had a short pulse, now only another short pulse is valid */ 99 | if (long_pulse) 100 | { 101 | /* nope, that was not expected */ 102 | ctx->state = PD_RX_INIT; 103 | } 104 | else 105 | { 106 | ctx->bit_data >>= 1; 107 | ctx->bit_data |= 0x10; 108 | ctx->bit_count++; 109 | } 110 | } 111 | else 112 | { 113 | if (long_pulse) 114 | { 115 | ctx->bit_data >>= 1; 116 | ctx->bit_data |= 0x00; 117 | ctx->bit_count++; 118 | } 119 | else 120 | { 121 | /* expect another short pulse */ 122 | ctx->short_pulse = true; 123 | } 124 | } 125 | 126 | /* wait for a successfully decoded SYNC_1 during preamble */ 127 | if (ctx->state == PD_RX_PREAMBLE) 128 | { 129 | if (line_code_decode[ctx->bit_data] == SYNC_1 || line_code_decode[ctx->bit_data] == RST_1) 130 | { 131 | ctx->state = PD_RX_SOP; 132 | ctx->bit_count = 5; 133 | } 134 | } 135 | 136 | /* fall through, enqueueing the SYNC_1 as well if we just synchronized */ 137 | if (ctx->state == PD_RX_SOP) 138 | { 139 | /* will also catch the fist SYNC symbol detected in preamble */ 140 | if (ctx->bit_count == 5) 141 | { 142 | ctx->bit_count %= 5; 143 | uint8_t symbol = line_code_decode[ctx->bit_data]; 144 | 145 | ctx->symbols[ctx->symbol_count++] = symbol; 146 | 147 | if (ctx->symbol_count >= 4) 148 | { 149 | switch (BUILD_LE_UINT32(ctx->symbols, 0)) 150 | { 151 | case TARGET_SOP: 152 | ctx->target = PD_TARGET_SOP; 153 | ctx->state = PD_RX_PAYLOAD; 154 | break; 155 | case TARGET_SOP_P: 156 | ctx->target = PD_TARGET_SOP_P; 157 | ctx->state = PD_RX_PAYLOAD; 158 | break; 159 | case TARGET_SOP_PP: 160 | ctx->target = PD_TARGET_SOP_PP; 161 | ctx->state = PD_RX_PAYLOAD; 162 | break; 163 | case TARGET_SOP_PD: 164 | ctx->target = PD_TARGET_SOP_PD; 165 | ctx->state = PD_RX_PAYLOAD; 166 | break; 167 | case TARGET_SOP_PPD: 168 | ctx->target = PD_TARGET_SOP_PPD; 169 | ctx->state = PD_RX_PAYLOAD; 170 | break; 171 | case TARGET_HARD_RESET: 172 | ctx->target = PD_TARGET_HARD_RESET; 173 | ctx->state = PD_RX_PAYLOAD; 174 | break; 175 | case TARGET_CABLE_RESET: 176 | ctx->target = PD_TARGET_CABLE_RESET; 177 | ctx->state = PD_RX_PAYLOAD; 178 | break; 179 | default: 180 | ctx->state = PD_RX_INIT; 181 | break; 182 | } 183 | } 184 | } 185 | } 186 | 187 | /* fall through, enqueueing the SYNC_1 as well if we just synchronized */ 188 | if (ctx->state == PD_RX_PAYLOAD) 189 | { 190 | if (ctx->bit_count == 5) 191 | { 192 | ctx->bit_count %= 5; 193 | uint8_t symbol = line_code_decode[ctx->bit_data]; 194 | 195 | if (ctx->symbol_count < sizeof(ctx->symbols)) 196 | { 197 | ctx->symbols[ctx->symbol_count++] = symbol; 198 | } 199 | 200 | if (symbol == EOP) 201 | { 202 | ctx->state = PD_RX_FINISHED; 203 | } 204 | } 205 | } 206 | 207 | if (ctx->state == PD_RX_FINISHED) 208 | { 209 | pd_rx_ongoing_flag = false; 210 | /* do most of the parsing already here as it is time critical. 211 | unfortunately the RMT TX cannot be started from IRAM, so we need a bottom half. */ 212 | 213 | /* in doubt hand over raw frame */ 214 | ctx->type = PD_BUF_TYPE_SYMBOLS; 215 | 216 | /* check if that was a valid packet with 5 symbols (4 SOP plus EOP) */ 217 | if (ctx->symbol_count >= 5) 218 | { 219 | ctx->length = MIN(sizeof(ctx->payload), (ctx->symbol_count - 5) / 2); 220 | 221 | for (int pos = 0; pos < ctx->length; pos++) 222 | { 223 | ctx->payload[pos] = ctx->symbols[4 + 2 * pos + 0] | (ctx->symbols[4 + 2 * pos + 1] << 4); 224 | } 225 | 226 | if (ctx->length > 4) 227 | { 228 | /* 1.2us for CRC calculation */ 229 | uint32_t crc_calc = crc32buf(ctx->payload, ctx->length - 4); 230 | uint32_t crc_pkt = BUILD_LE_UINT32(ctx->payload, ctx->length - 4); 231 | if (crc_calc == crc_pkt) 232 | { 233 | ctx->type = PD_BUF_TYPE_DATA; 234 | } 235 | } 236 | } 237 | 238 | bool yield = false; 239 | 240 | ctx->dir = pd_acknowlegde[ctx->target] ? PD_PACKET_RECEIVED_ACKNOWLEDGED : PD_PACKET_RECEIVED; 241 | 242 | if (ctx->type == PD_BUF_TYPE_DATA && ctx->dir == PD_PACKET_RECEIVED_ACKNOWLEDGED) 243 | { 244 | uint16_t header = ctx->payload[0] | (ctx->payload[1] << 8); 245 | 246 | /* Extract individual fields */ 247 | uint8_t num_data_objects = (header >> 12) & 0x07; 248 | uint32_t message_id = (header >> 9) & 0x07; 249 | uint8_t data_role = (header >> 5) & 0x01; 250 | uint8_t message_type = header & 0x1F; 251 | bool is_data = num_data_objects > 0; 252 | 253 | pd_rx_ack_t ack = {.message_id = message_id, .target = ctx->target}; 254 | 255 | /* do not respond to our packets or to GoodCRC */ 256 | if (data_role == PD_DATA_ROLE_DFP && (is_data || message_type != PD_CONTROL_GOOD_CRC)) 257 | { 258 | if (xQueueSendFromISR(pd_queue_rx_ack, &ack, NULL) != pdTRUE) 259 | { 260 | ESP_LOGE(TAG, "Failed to enqueue tx ack"); 261 | } 262 | yield = true; 263 | } 264 | } 265 | 266 | /* Send the buffer to the user space queue and get a new one */ 267 | if (xQueueSendFromISR(pd_queue_rx_data, &ctx, NULL) != pdTRUE) 268 | { 269 | xQueueSendFromISR(pd_queue_empty, &ctx, NULL); 270 | } 271 | ctx = NULL; 272 | 273 | return yield; 274 | } 275 | 276 | return false; 277 | } 278 | 279 | void IRAM_ATTR pd_rx_start() 280 | { 281 | rmt_receive_config_t receive_config = { 282 | .signal_range_min_ns = 800, 283 | .signal_range_max_ns = 5000, 284 | .flags.en_partial_rx = true}; 285 | 286 | ESP_ERROR_CHECK(rmt_receive(pd_rx_chan, pd_dummy_buffer, sizeof(pd_dummy_buffer), &receive_config)); 287 | gpio_set_level(GPIO_CC1_IN, 1); 288 | } 289 | 290 | static IRAM_ATTR bool pd_rx_done_cbr(rmt_channel_handle_t channel, const rmt_rx_done_event_data_t *edata, void *user_data) 291 | { 292 | bool yield = false; 293 | 294 | /* 295 | if (pd_tx_ongoing()) 296 | { 297 | if (edata->flags.is_last) 298 | { 299 | pd_rc_bmc_handle_pulse(0); 300 | pd_rx_start(); 301 | } 302 | return false; 303 | }*/ 304 | 305 | pd_rx_ongoing_flag = true; 306 | 307 | for (int pos = 0; pos < edata->num_symbols; pos++) 308 | { 309 | yield |= pd_rc_bmc_handle_pulse(edata->received_symbols[pos].duration0); 310 | yield |= pd_rc_bmc_handle_pulse(edata->received_symbols[pos].duration1); 311 | } 312 | 313 | if (edata->flags.is_last) 314 | { 315 | pd_rc_bmc_handle_pulse(0); 316 | pd_rx_ongoing_flag = false; 317 | pd_rx_start(); 318 | } 319 | 320 | return yield; 321 | } 322 | 323 | void pd_rx_init() 324 | { 325 | rmt_rx_channel_config_t rx_chan_config = { 326 | .clk_src = RMT_CLK_SRC_DEFAULT, 327 | .resolution_hz = PD_RX_FREQ, 328 | .mem_block_symbols = PD_RX_SYMS, 329 | .gpio_num = GPIO_CC1_IN, 330 | .flags.invert_in = false, 331 | .flags.with_dma = false, 332 | .flags.io_loop_back = true, 333 | .intr_priority = 3, 334 | }; 335 | rmt_rx_event_callbacks_t cbs = { 336 | .on_recv_done = pd_rx_done_cbr, 337 | }; 338 | 339 | ESP_ERROR_CHECK(rmt_new_rx_channel(&rx_chan_config, &pd_rx_chan)); 340 | ESP_ERROR_CHECK(rmt_rx_register_event_callbacks(pd_rx_chan, &cbs, NULL)); 341 | ESP_ERROR_CHECK(rmt_enable(pd_rx_chan)); 342 | pd_rx_start(); 343 | } 344 | -------------------------------------------------------------------------------- /src/pd_tx.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "esp_log.h" 5 | 6 | #include "driver/gpio.h" 7 | #include "driver/rmt_tx.h" 8 | 9 | /* 10 | * This section is needed for reconfiguring the Tx GPIO just before transmission to output mode 11 | * and then back to input mode after transmission. This is necessary to prevent interference with 12 | * other transmissions. Reconfiguring using new Rx RMT channels each time would be too time-consuming. 13 | */ 14 | #include "driver/rmt_types.h" // Include RMT driver types 15 | #include "../src/rmt_private.h" // Include private RMT definitions 16 | #include "soc/rmt_periph.h" // Required for accessing rmt_signal_conn_t and rmt_periph_signals. 17 | extern const rmt_signal_conn_t rmt_periph_signals; // External declaration of RMT peripheral signals 18 | 19 | #include "freertos/FreeRTOS.h" 20 | #include "freertos/task.h" 21 | 22 | #include "pd_config.h" 23 | #include "pd_coding.h" 24 | #include "pd_proto.h" 25 | #include "pd_rx.h" 26 | #include "pd_tx.h" 27 | #include "pd.h" 28 | #include "crc32.h" 29 | 30 | #define TAG "PD-TX" 31 | 32 | #define PD_TX_FREQ (10000000) 33 | #define PD_TX_SYMS (64) 34 | #define PD_TX_SHORT_DURATION (16) /* 1.6us */ 35 | 36 | static rmt_channel_handle_t pd_tx_chan; 37 | static rmt_encoder_handle_t pd_tx_encoder; 38 | static QueueHandle_t pd_queue_tx; 39 | static QueueHandle_t pd_queue_tx_acks; 40 | 41 | extern QueueHandle_t pd_queue_rx_data_log; 42 | extern QueueHandle_t pd_queue_empty; 43 | 44 | static volatile bool pd_tx_ongoing_flag = false; 45 | static uint8_t pd_tx_message_id = 0; 46 | 47 | bool IRAM_ATTR pd_tx_ongoing() 48 | { 49 | return pd_tx_ongoing_flag; 50 | } 51 | 52 | void IRAM_ATTR pd_tx_active() 53 | { 54 | #ifdef GPIO_CC1 55 | gpio_set_drive_capability(GPIO_CC1, GPIO_DRIVE_CAP_0); 56 | #endif 57 | gpio_set_drive_capability(GPIO_TX, GPIO_DRIVE_CAP_0); 58 | esp_rom_gpio_connect_out_signal( 59 | GPIO_TX, 60 | rmt_periph_signals.groups[pd_tx_chan->group->group_id].channels[pd_tx_chan->channel_id + RMT_TX_CHANNEL_OFFSET_IN_GROUP].tx_sig, 61 | true, false); 62 | #ifdef GPIO_CC1 63 | gpio_set_direction(GPIO_CC1, GPIO_MODE_OUTPUT); 64 | gpio_set_level(GPIO_CC1, 0); 65 | /* we now have configured the CC1 pin and TX pin to drive against each other. 66 | with these drive capabilities, we get a voltage divider to approx 1.7V, which is closer to 67 | the expected 1.1V on the PD lines */ 68 | #else 69 | /* we now have a weak TX pin driving 3.3V on the PD bus line. also works, its just far from specs. */ 70 | #endif 71 | } 72 | 73 | void IRAM_ATTR pd_tx_inactive() 74 | { 75 | /* now configure the TX pin back to an input so communication isn't blocked. order is chosen that there are less spikes. */ 76 | #ifdef GPIO_CC1 77 | gpio_set_direction(GPIO_CC1, GPIO_MODE_INPUT); 78 | #endif 79 | gpio_set_direction(GPIO_TX, GPIO_MODE_INPUT); 80 | #ifdef GPIO_CC1 81 | gpio_set_pull_mode(GPIO_CC1, GPIO_FLOATING); 82 | #endif 83 | gpio_set_pull_mode(GPIO_TX, GPIO_FLOATING); 84 | } 85 | 86 | static IRAM_ATTR void add_bit(pd_tx_ctx_t *ctx, rmt_symbol_word_t *symbols, size_t *symbols_used, bool bit, uint32_t short_duration) 87 | { 88 | /* 89 | * In this encoding scheme: 90 | * - A 0-bit creates two equally long pulses of the same level. 91 | * - A 1-bit creates an alternating bit pair. 92 | */ 93 | symbols[*symbols_used].level0 = ctx->level; 94 | symbols[*symbols_used].duration0 = short_duration; 95 | symbols[*symbols_used].duration1 = short_duration; 96 | if (!bit) 97 | { 98 | ctx->level = !ctx->level; 99 | } 100 | symbols[*symbols_used].level1 = !ctx->level; 101 | 102 | (*symbols_used)++; 103 | } 104 | 105 | static IRAM_ATTR void add_half(pd_tx_ctx_t *ctx, rmt_symbol_word_t *symbols, size_t *symbols_used, uint8_t half) 106 | { 107 | for (int pos = 0; pos < 5; pos++) 108 | { 109 | add_bit(ctx, symbols, symbols_used, half & 1, PD_TX_SHORT_DURATION); 110 | half >>= 1; 111 | } 112 | } 113 | 114 | static IRAM_ATTR size_t pd_tx_enc_cbr(const void *data, size_t data_size, 115 | size_t symbols_written, size_t symbols_free, 116 | rmt_symbol_word_t *symbols, bool *done, void *arg) 117 | { 118 | size_t symbols_used = 0; 119 | pd_tx_ctx_t *ctx = (pd_tx_ctx_t *)arg; 120 | 121 | if (symbols_written == 0) 122 | { 123 | /* reset all states */ 124 | memset(ctx, 0, sizeof(pd_tx_ctx_t)); 125 | ctx->state = PD_TX_PATTERN; 126 | ctx->level = true; 127 | pd_tx_ongoing_flag = true; 128 | } 129 | 130 | /* We need a minimum of 10 symbol spaces per byte */ 131 | bool loop = true; 132 | while (loop) 133 | { 134 | if (symbols_used >= symbols_free) 135 | { 136 | break; 137 | } 138 | 139 | switch (ctx->state) 140 | { 141 | case PD_TX_PATTERN: 142 | { 143 | if (ctx->sync_bits >= 64) 144 | { 145 | ctx->state = PD_TX_SYNC; 146 | break; 147 | } 148 | add_bit(ctx, symbols, &symbols_used, ctx->sync_bits & 1, PD_TX_SHORT_DURATION); 149 | ctx->sync_bits++; 150 | break; 151 | } 152 | 153 | case PD_TX_SYNC: 154 | { 155 | if (ctx->sync_symbols >= 4) 156 | { 157 | ctx->data_pos = 1; 158 | ctx->state = PD_TX_DATA; 159 | break; 160 | } 161 | uint32_t sync_symbol = 0; 162 | uint8_t sync_symbols[4]; 163 | 164 | switch ((pd_rx_target_t)((uint8_t *)data)[0]) 165 | { 166 | case PD_TARGET_SOP: 167 | sync_symbol = TARGET_SOP; 168 | break; 169 | case PD_TARGET_SOP_P: 170 | sync_symbol = TARGET_SOP_P; 171 | break; 172 | case PD_TARGET_SOP_PP: 173 | sync_symbol = TARGET_SOP_PP; 174 | break; 175 | case PD_TARGET_SOP_PD: 176 | sync_symbol = TARGET_SOP_PD; 177 | break; 178 | case PD_TARGET_SOP_PPD: 179 | sync_symbol = TARGET_SOP_PPD; 180 | break; 181 | case PD_TARGET_HARD_RESET: 182 | sync_symbol = TARGET_HARD_RESET; 183 | break; 184 | case PD_TARGET_CABLE_RESET: 185 | sync_symbol = TARGET_CABLE_RESET; 186 | break; 187 | } 188 | SPLIT_LE_UINT32(sync_symbol, sync_symbols, 0); 189 | 190 | add_half(ctx, symbols, &symbols_used, line_code_encode[sync_symbols[ctx->sync_symbols]]); 191 | ctx->sync_symbols++; 192 | break; 193 | } 194 | 195 | case PD_TX_DATA: 196 | { 197 | if (ctx->data_pos >= data_size) 198 | { 199 | ctx->state = PD_TX_EOP; 200 | break; 201 | } 202 | if ((symbols_used + 10) > symbols_free) 203 | { 204 | loop = false; 205 | break; 206 | } 207 | 208 | /* if all bytes transmitted, finish */ 209 | uint8_t data_byte = ((uint8_t *)data)[ctx->data_pos]; 210 | uint8_t half_lower = line_code_encode[data_byte & 0x0F]; 211 | uint8_t half_upper = line_code_encode[data_byte >> 4]; 212 | 213 | add_half(ctx, symbols, &symbols_used, half_lower); 214 | add_half(ctx, symbols, &symbols_used, half_upper); 215 | 216 | ctx->data_pos++; 217 | break; 218 | } 219 | 220 | case PD_TX_EOP: 221 | { 222 | if (ctx->eop_symbols) 223 | { 224 | ctx->state = PD_TX_DONE; 225 | break; 226 | } 227 | add_half(ctx, symbols, &symbols_used, line_code_encode[EOP]); 228 | /* create a longer final edge */ 229 | add_bit(ctx, symbols, &symbols_used, 0, 2 * PD_TX_SHORT_DURATION); 230 | ctx->eop_symbols++; 231 | break; 232 | } 233 | 234 | case PD_TX_DONE: 235 | { 236 | /* not documented good enough IMO - only set done when no symbols got enqueued */ 237 | loop = false; 238 | *done = !symbols_used; 239 | break; 240 | } 241 | } 242 | } 243 | 244 | if (symbols_written == 0) 245 | { 246 | /* first transmission starts now */ 247 | pd_tx_active(); 248 | } 249 | 250 | return symbols_used; 251 | } 252 | 253 | bool IRAM_ATTR pd_tx_done_cbr(rmt_channel_handle_t tx_chan, const rmt_tx_done_event_data_t *edata, void *user_ctx) 254 | { 255 | pd_tx_inactive(); 256 | pd_tx_ongoing_flag = false; 257 | return false; 258 | } 259 | 260 | void IRAM_ATTR pd_tx_start(const uint8_t *data, size_t length) 261 | { 262 | rmt_transmit_config_t config = { 263 | .loop_count = 0, 264 | }; 265 | 266 | ESP_ERROR_CHECK(rmt_transmit(pd_tx_chan, pd_tx_encoder, data, length, &config)); 267 | } 268 | 269 | void IRAM_ATTR pd_tx_task(void *pvParameters) 270 | { 271 | uint8_t buffer[1 + 2 + 7 * 4 + 4]; 272 | pd_msg *msg; 273 | 274 | while (1) 275 | { 276 | if (xQueueReceive(pd_queue_tx, &msg, portMAX_DELAY) != pdTRUE) 277 | { 278 | continue; 279 | } 280 | 281 | msg->header.message_id = pd_tx_message_id; 282 | if (!msg->target) 283 | { 284 | msg->target = PD_TARGET_SOP; 285 | } 286 | 287 | /* we can only handle normal messages with header, pdos and crc */ 288 | size_t length = 0; 289 | 290 | buffer[0] = msg->target; 291 | length += 1; 292 | 293 | /* construct the 16 bit header */ 294 | pd_build_msg_header(&msg->header, &buffer[length]); 295 | length += 2; 296 | 297 | /* append all PDOs*/ 298 | for (int pdo = 0; pdo < msg->header.num_data_objects; pdo++) 299 | { 300 | SPLIT_LE_UINT32(msg->pdo[pdo], buffer, length); 301 | length += 4; 302 | } 303 | 304 | /* finally calc and append the CRC */ 305 | uint32_t crc = crc32buf(&buffer[1], length - 1); 306 | SPLIT_LE_UINT32(crc, buffer, length); 307 | length += 4; 308 | 309 | /* now retry three times to send the message and get an ACK for it */ 310 | bool ack = false; 311 | uint32_t retries = 1; 312 | do 313 | { 314 | /* transmit our buffer */ 315 | if (!msg->immediate) 316 | { 317 | while (pd_rx_ongoing() || pd_tx_ongoing()) 318 | { 319 | vPortYield(); 320 | } 321 | } 322 | 323 | pd_tx_start(buffer, length); 324 | 325 | /* wait for the RX path to detect an ack */ 326 | uint32_t ack_id = 0; 327 | while (xQueueReceive(pd_queue_tx_acks, &ack_id, 10 / portTICK_PERIOD_MS) == pdTRUE) 328 | { 329 | ack = (ack_id == pd_tx_message_id); 330 | } 331 | 332 | #ifdef PD_LOG_TX_PACKETS 333 | /* log the message */ 334 | pd_rx_buf_t *rx_data; 335 | if (xQueueReceive(pd_queue_empty, &rx_data, 0)) 336 | { 337 | memset(rx_data, 0x00, sizeof(pd_rx_buf_t)); 338 | 339 | rx_data->type = PD_BUF_TYPE_DATA; 340 | rx_data->target = msg->target; 341 | rx_data->dir = ack ? PD_PACKET_SENT_ACKNOWLEDGED : PD_PACKET_SENT; 342 | 343 | rx_data->length = length - 1; 344 | memcpy(rx_data->payload, &buffer[1], rx_data->length); 345 | 346 | if (xQueueSend(pd_queue_rx_data_log, &rx_data, 0) != pdTRUE) 347 | { 348 | ESP_LOGE(TAG, "Failed to return buffer to pd_queue_empty"); 349 | free(rx_data); 350 | } 351 | } 352 | #endif 353 | } while (retries-- && !ack); 354 | 355 | if (ack) 356 | { 357 | pd_tx_message_id = (pd_tx_message_id + 1) & MESSAGE_ID_MASK; 358 | } 359 | 360 | if (msg->cbr) 361 | { 362 | msg->cbr(msg, ack); 363 | } 364 | } 365 | } 366 | 367 | void pd_tx_init() 368 | { 369 | const rmt_tx_channel_config_t tx_chan_config = { 370 | .clk_src = RMT_CLK_SRC_DEFAULT, 371 | .resolution_hz = PD_TX_FREQ, 372 | .mem_block_symbols = PD_TX_SYMS, 373 | .gpio_num = GPIO_TX, 374 | .trans_queue_depth = 10, 375 | .flags.io_loop_back = true, 376 | .flags.invert_out = false, 377 | .flags.with_dma = false, 378 | .flags.io_od_mode = false, 379 | }; 380 | 381 | const rmt_tx_event_callbacks_t cbr = { 382 | .on_trans_done = &pd_tx_done_cbr, 383 | }; 384 | 385 | const rmt_simple_encoder_config_t encoder_cfg = { 386 | .callback = pd_tx_enc_cbr, 387 | .min_chunk_size = 10, 388 | .arg = calloc(1, sizeof(pd_tx_ctx_t)), 389 | }; 390 | 391 | ESP_LOGI(TAG, " Init TX channel"); 392 | ESP_LOGI(TAG, " Register channel"); 393 | ESP_ERROR_CHECK(rmt_new_tx_channel(&tx_chan_config, &pd_tx_chan)); 394 | ESP_LOGI(TAG, " Register callback"); 395 | ESP_ERROR_CHECK(rmt_tx_register_event_callbacks(pd_tx_chan, &cbr, NULL)); 396 | ESP_LOGI(TAG, " Create encoder"); 397 | ESP_ERROR_CHECK(rmt_new_simple_encoder(&encoder_cfg, &pd_tx_encoder)); 398 | ESP_LOGI(TAG, " Enable channel"); 399 | ESP_ERROR_CHECK(rmt_enable(pd_tx_chan)); 400 | 401 | gpio_set_direction(GPIO_TX, GPIO_MODE_INPUT); 402 | gpio_set_pull_mode(GPIO_TX, GPIO_FLOATING); 403 | 404 | pd_queue_tx = xQueueCreate(PD_BUFFER_COUNT, sizeof(pd_msg *)); 405 | if (pd_queue_tx == NULL) 406 | { 407 | ESP_LOGE(TAG, "Failed to create pd_queue_tx"); 408 | return; 409 | } 410 | 411 | pd_queue_tx_acks = xQueueCreate(PD_BUFFER_COUNT, sizeof(uint32_t)); 412 | if (pd_queue_tx_acks == NULL) 413 | { 414 | ESP_LOGE(TAG, "Failed to create pd_queue_tx_acks"); 415 | return; 416 | } 417 | 418 | xTaskCreate(pd_tx_task, "pd_tx_task", 4096, NULL, PD_TX_TASK_PRIO, NULL); 419 | ESP_LOGI(TAG, " Done"); 420 | } 421 | 422 | uint16_t IRAM_ATTR pd_tx_header( 423 | uint8_t extended, uint8_t num_data_objects, uint8_t message_id, 424 | uint8_t power_role, uint8_t spec_revision, uint8_t data_role, 425 | uint8_t message_type) 426 | { 427 | uint16_t header = 0; 428 | 429 | /* Construct the 16-bit header */ 430 | header |= (extended & 0x01) << 15; 431 | header |= (num_data_objects & 0x07) << 12; 432 | header |= (message_id & 0x07) << 9; 433 | header |= (power_role & 0x01) << 8; 434 | header |= (spec_revision & 0x03) << 6; 435 | header |= (data_role & 0x01) << 5; 436 | header |= (message_type & 0x1F); 437 | 438 | return header; 439 | } 440 | 441 | void pd_tx_enqueue(pd_msg *msg) 442 | { 443 | pd_msg *copy = malloc(sizeof(pd_msg)); 444 | memcpy(copy, msg, sizeof(pd_msg)); 445 | 446 | /* Return the buffer to the empty buffer queue */ 447 | if (xQueueSend(pd_queue_tx, ©, portMAX_DELAY) != pdTRUE) 448 | { 449 | ESP_LOGE(TAG, "Failed to send buffer to pd_queue_tx"); 450 | free(copy); 451 | } 452 | vPortYield(); 453 | } 454 | 455 | void pd_tx_ack_received(uint32_t msg_id) 456 | { 457 | /* Return the buffer to the empty buffer queue */ 458 | if (xQueueSend(pd_queue_tx_acks, &msg_id, portMAX_DELAY) != pdTRUE) 459 | { 460 | ESP_LOGE(TAG, "Failed to send buffer to pd_queue_tx_acks"); 461 | } 462 | } 463 | -------------------------------------------------------------------------------- /src/pd_proto.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | 5 | #include "esp_log.h" 6 | #include "driver/gpio.h" 7 | #include "freertos/FreeRTOS.h" 8 | #include "freertos/task.h" 9 | 10 | #include "pd_types.h" 11 | #include "pd_proto.h" 12 | #include "pd_config.h" 13 | #include "pd.h" 14 | #include "crc32.h" 15 | 16 | #define TAG "PD" 17 | 18 | void pd_dump_msg_header(pd_msg_header *hdr) 19 | { 20 | ESP_LOGE(TAG, " Header Fields%s", (hdr->extended) ? " (extended)" : ""); 21 | ESP_LOGE(TAG, " DO: %" PRIu8 ", ID: %" PRIu8 ", PPR/CP: %" PRIu8 ", Rev: %" PRIu8 ", PDR: %" PRIu8 ", Type: %" PRIu8 "", 22 | hdr->num_data_objects, hdr->message_id, hdr->power_role, hdr->spec_revision, hdr->data_role, hdr->message_type); 23 | } 24 | 25 | void pd_dump_vdm(pd_vdm_packet *pkt) 26 | { 27 | ESP_LOGI(TAG, " Vendor Message:"); 28 | ESP_LOGI(TAG, " SVID: 0x%04X", pkt->vdm_header.svid); 29 | ESP_LOGI(TAG, " VDM Type: %s", pkt->vdm_header.vdm_type ? "Structured" : "Unstructured"); 30 | 31 | if (pkt->vdm_header.vdm_type) 32 | { 33 | const char *type[] = {"REQ", "ACK", "NAK", "BUSY"}; 34 | const char *cmd[] = {"Reserved", "Discover Identity", "Discover SVIDs", "Discover Modes", "Enter Mode", "Exit Mode", "Attention"}; 35 | ESP_LOGI(TAG, " VDM Version: %u.%u", pkt->vdm_header.vdm_version_major, pkt->vdm_header.vdm_version_minor); 36 | ESP_LOGI(TAG, " Object Position: %u", pkt->vdm_header.object_position); 37 | ESP_LOGI(TAG, " Command Type: %u (%s)", pkt->vdm_header.command_type, 38 | (pkt->vdm_header.command_type < 7) ? type[pkt->vdm_header.command_type] : (pkt->vdm_header.command_type < 16) ? "Reserved" 39 | : "SVID Specific"); 40 | ESP_LOGI(TAG, " Command: %u (%s)", pkt->vdm_header.command, cmd[pkt->vdm_header.command]); 41 | } 42 | 43 | /* 0 REQ, 1 ACK */ 44 | if (pkt->vdm_header.command_type == 1) 45 | { 46 | ESP_LOGI(TAG, " ID Header VDO:"); 47 | ESP_LOGI(TAG, " USB Host Capable: %" PRIu8, pkt->id_header.usb_host); 48 | ESP_LOGI(TAG, " USB Device Capable: %" PRIu8, pkt->id_header.usb_device); 49 | ESP_LOGI(TAG, " SOP' Product Type: %" PRIu8, pkt->id_header.sop_product_type); 50 | ESP_LOGI(TAG, " Modal Operation Supported: %" PRIu8, pkt->id_header.modal_operation); 51 | ESP_LOGI(TAG, " USB Vendor ID: 0x%04" PRIX16, pkt->id_header.usb_vendor_id); 52 | 53 | ESP_LOGI(TAG, " Cert Stat VDO:"); 54 | ESP_LOGI(TAG, " USB-IF XID: 0x%08" PRIX32, pkt->crt_stat.usb_if_xid); 55 | 56 | ESP_LOGI(TAG, " Product VDO:"); 57 | ESP_LOGI(TAG, " USB Product ID: 0x%04" PRIX16, pkt->product.usb_product_id); 58 | ESP_LOGI(TAG, " Device Version: 0x%04" PRIX16, pkt->product.bcd_device); 59 | 60 | if (pkt->id_header.sop_product_type == 3 || pkt->id_header.sop_product_type == 4) 61 | { 62 | ESP_LOGI(TAG, " Cable VDO1:"); 63 | ESP_LOGI(TAG, " HW Version: %" PRIu8, pkt->cable_1.hw_version); 64 | ESP_LOGI(TAG, " FW Version: %" PRIu8, pkt->cable_1.fw_version); 65 | ESP_LOGI(TAG, " VDO Version: %" PRIu8, pkt->cable_1.vdo_version); 66 | ESP_LOGI(TAG, " Plug Type: %" PRIu8, pkt->cable_1.plug_type); 67 | ESP_LOGI(TAG, " EPR Capable: %" PRIu8, pkt->cable_1.epr_capable); 68 | ESP_LOGI(TAG, " Cable Latency: %" PRIu8, pkt->cable_1.cable_latency); 69 | ESP_LOGI(TAG, " Cable Termination: %" PRIu8, pkt->cable_1.cable_termination); 70 | ESP_LOGI(TAG, " Max VBUS Voltage: %" PRIu8, pkt->cable_1.max_vbus_voltage); 71 | ESP_LOGI(TAG, " SBU Supported: %" PRIu8, pkt->cable_1.sbu_supported); 72 | ESP_LOGI(TAG, " SBU Type: %" PRIu8, pkt->cable_1.sbu_type); 73 | ESP_LOGI(TAG, " VBUS Current Handling: %" PRIu8, pkt->cable_1.vbus_current); 74 | ESP_LOGI(TAG, " VBUS Through Cable: %" PRIu8, pkt->cable_1.vbus_through); 75 | ESP_LOGI(TAG, " SOP'' Controller Present: %" PRIu8, pkt->cable_1.sop_controller); 76 | 77 | if (pkt->id_header.sop_product_type == 4) 78 | { 79 | ESP_LOGI(TAG, " Cable VDO2:"); 80 | ESP_LOGI(TAG, " Max Operating Temperature: %" PRIu8 "°C", pkt->cable_2.max_operating_temp); 81 | ESP_LOGI(TAG, " Shutdown Temperature: %" PRIu8 "°C", pkt->cable_2.shutdown_temp); 82 | ESP_LOGI(TAG, " U3/CLd Power: %" PRIu8, pkt->cable_2.u3_cld_power); 83 | ESP_LOGI(TAG, " U3 to U0 Transition Mode: %" PRIu8, pkt->cable_2.u3_to_u0_transition); 84 | ESP_LOGI(TAG, " Physical Connection: %" PRIu8, pkt->cable_2.physical_connection); 85 | ESP_LOGI(TAG, " Active Element: %" PRIu8, pkt->cable_2.active_element); 86 | ESP_LOGI(TAG, " USB4 Supported: %" PRIu8, pkt->cable_2.usb4_supported); 87 | ESP_LOGI(TAG, " USB 2.0 Hub Hops Consumed: %" PRIu8, pkt->cable_2.usb2_hub_hops); 88 | ESP_LOGI(TAG, " USB 2.0 Supported: %" PRIu8, pkt->cable_2.usb2_supported); 89 | ESP_LOGI(TAG, " USB 3.2 Supported: %" PRIu8, pkt->cable_2.usb3_2_supported); 90 | ESP_LOGI(TAG, " USB Lanes Supported: %" PRIu8, pkt->cable_2.usb_lanes_supported); 91 | ESP_LOGI(TAG, " Optically Isolated: %" PRIu8, pkt->cable_2.optically_isolated); 92 | ESP_LOGI(TAG, " USB4 Asym. Mode Supported: %" PRIu8, pkt->cable_2.usb4_asymmetric); 93 | ESP_LOGI(TAG, " USB Gen 1b (Gen 2 plus): %" PRIu8, pkt->cable_2.usb_gen); 94 | } 95 | } 96 | } 97 | } 98 | 99 | void pd_parse_vdm(pd_vdm_packet *pkt, pd_msg *msg) 100 | { 101 | uint32_t vdm_header = msg->pdo[0]; 102 | 103 | pkt->vdm_header.svid = (vdm_header >> SVID_SHIFT) & SVID_MASK; 104 | pkt->vdm_header.vdm_type = (vdm_header >> VDM_TYPE_SHIFT) & VDM_TYPE_MASK; 105 | pkt->vdm_header.vdm_version_major = (vdm_header >> VDM_VERSION_SHIFT) & VDM_VERSION_MASK; 106 | pkt->vdm_header.vdm_version_minor = (vdm_header >> VDM_MINOR_SHIFT) & VDM_MINOR_MASK; 107 | pkt->vdm_header.object_position = (vdm_header >> OBJ_POS_SHIFT) & OBJ_POS_MASK; 108 | pkt->vdm_header.command_type = (vdm_header >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 109 | pkt->vdm_header.command = (vdm_header >> COMMAND_SHIFT) & COMMAND_MASK; 110 | 111 | /* 0 REQ, 1 ACK */ 112 | if (pkt->vdm_header.command_type == 1) 113 | { 114 | /* ID Header VDO */ 115 | uint32_t id_header = msg->pdo[1]; 116 | pkt->id_header.usb_host = (id_header >> USB_HOST_SHIFT) & USB_HOST_MASK; 117 | pkt->id_header.usb_device = (id_header >> USB_DEVICE_SHIFT) & USB_DEVICE_MASK; 118 | pkt->id_header.sop_product_type = (id_header >> SOP_PRODUCT_TYPE_SHIFT) & SOP_PRODUCT_TYPE_MASK; 119 | pkt->id_header.modal_operation = (id_header >> MODAL_OPERATION_SHIFT) & MODAL_OPERATION_MASK; 120 | pkt->id_header.usb_vendor_id = (id_header >> USB_VENDOR_ID_SHIFT) & USB_VENDOR_ID_MASK; 121 | /* Cert Stat VDO */ 122 | pkt->crt_stat.usb_if_xid = msg->pdo[2]; 123 | /* Product VDO */ 124 | uint32_t product_vdo = msg->pdo[3]; 125 | pkt->product.usb_product_id = (product_vdo >> USB_PRODUCT_ID_SHIFT) & USB_PRODUCT_ID_MASK; 126 | pkt->product.bcd_device = (product_vdo >> BCD_DEVICE_SHIFT) & BCD_DEVICE_MASK; 127 | 128 | if (pkt->id_header.sop_product_type == 3 || pkt->id_header.sop_product_type == 4) 129 | { 130 | /* Cable VDO1 */ 131 | uint32_t cable_vdo1 = msg->pdo[4]; 132 | pkt->cable_1.hw_version = (cable_vdo1 >> HW_VERSION_SHIFT) & HW_VERSION_MASK; 133 | pkt->cable_1.fw_version = (cable_vdo1 >> FW_VERSION_SHIFT) & FW_VERSION_MASK; 134 | pkt->cable_1.vdo_version = (cable_vdo1 >> VDO_VERSION_SHIFT) & VDO_VERSION_MASK; 135 | pkt->cable_1.plug_type = (cable_vdo1 >> PLUG_TYPE_SHIFT) & PLUG_TYPE_MASK; 136 | pkt->cable_1.epr_capable = (cable_vdo1 >> EPR_CAPABLE_SHIFT) & EPR_CAPABLE_MASK; 137 | pkt->cable_1.cable_latency = (cable_vdo1 >> CABLE_LATENCY_SHIFT) & CABLE_LATENCY_MASK; 138 | pkt->cable_1.cable_termination = (cable_vdo1 >> CABLE_TERMINATION_SHIFT) & CABLE_TERMINATION_MASK; 139 | pkt->cable_1.max_vbus_voltage = (cable_vdo1 >> MAX_VBUS_VOLTAGE_SHIFT) & MAX_VBUS_VOLTAGE_MASK; 140 | pkt->cable_1.sbu_supported = (cable_vdo1 >> SBU_SUPPORTED_SHIFT) & SBU_SUPPORTED_MASK; 141 | pkt->cable_1.sbu_type = (cable_vdo1 >> SBU_TYPE_SHIFT) & SBU_TYPE_MASK; 142 | pkt->cable_1.vbus_current = (cable_vdo1 >> VBUS_CURRENT_SHIFT) & VBUS_CURRENT_MASK; 143 | pkt->cable_1.vbus_through = (cable_vdo1 >> VBUS_THROUGH_SHIFT) & VBUS_THROUGH_MASK; 144 | pkt->cable_1.sop_controller = (cable_vdo1 >> SOP_CONTROLLER_SHIFT) & SOP_CONTROLLER_MASK; 145 | 146 | if (pkt->id_header.sop_product_type == 4) 147 | { 148 | /* Cable VDO2 */ 149 | uint32_t cable_vdo2 = msg->pdo[5]; 150 | pkt->cable_2.max_operating_temp = (cable_vdo2 >> MAX_OPERATING_TEMP_SHIFT) & MAX_OPERATING_TEMP_MASK; 151 | pkt->cable_2.shutdown_temp = (cable_vdo2 >> SHUTDOWN_TEMP_SHIFT) & SHUTDOWN_TEMP_MASK; 152 | pkt->cable_2.u3_cld_power = (cable_vdo2 >> U3_CLD_POWER_SHIFT) & U3_CLD_POWER_MASK; 153 | pkt->cable_2.u3_to_u0_transition = (cable_vdo2 >> U3_TO_U0_TRANSITION_SHIFT) & U3_TO_U0_TRANSITION_MASK; 154 | pkt->cable_2.physical_connection = (cable_vdo2 >> PHYSICAL_CONNECTION_SHIFT) & PHYSICAL_CONNECTION_MASK; 155 | pkt->cable_2.active_element = (cable_vdo2 >> ACTIVE_ELEMENT_SHIFT) & ACTIVE_ELEMENT_MASK; 156 | pkt->cable_2.usb4_supported = (cable_vdo2 >> USB4_SUPPORTED_SHIFT) & USB4_SUPPORTED_MASK; 157 | pkt->cable_2.usb2_hub_hops = (cable_vdo2 >> USB2_HUB_HOPS_SHIFT) & USB2_HUB_HOPS_MASK; 158 | pkt->cable_2.usb2_supported = (cable_vdo2 >> USB2_SUPPORTED_SHIFT) & USB2_SUPPORTED_MASK; 159 | pkt->cable_2.usb3_2_supported = (cable_vdo2 >> USB3_2_SUPPORTED_SHIFT) & USB3_2_SUPPORTED_MASK; 160 | pkt->cable_2.usb_lanes_supported = (cable_vdo2 >> USB_LANES_SUPPORTED_SHIFT) & USB_LANES_SUPPORTED_MASK; 161 | pkt->cable_2.optically_isolated = (cable_vdo2 >> OPTICALLY_ISOLATED_SHIFT) & OPTICALLY_ISOLATED_MASK; 162 | pkt->cable_2.usb4_asymmetric = (cable_vdo2 >> USB4_ASYMMETRIC_SHIFT) & USB4_ASYMMETRIC_MASK; 163 | pkt->cable_2.usb_gen = (cable_vdo2 >> USB_GEN_SHIFT) & USB_GEN_MASK; 164 | } 165 | } 166 | } 167 | } 168 | 169 | void pd_build_vdm(pd_vdm_packet *pkt, pd_msg *msg) 170 | { 171 | uint32_t header = 0; 172 | header |= ((pkt->vdm_header.svid & SVID_MASK) << SVID_SHIFT); 173 | header |= ((pkt->vdm_header.vdm_type & VDM_TYPE_MASK) << VDM_TYPE_SHIFT); 174 | header |= ((pkt->vdm_header.vdm_version_major & VDM_VERSION_MASK) << VDM_VERSION_SHIFT); 175 | header |= ((pkt->vdm_header.vdm_version_minor & VDM_MINOR_MASK) << VDM_MINOR_SHIFT); 176 | header |= ((pkt->vdm_header.object_position & OBJ_POS_MASK) << OBJ_POS_SHIFT); 177 | header |= ((pkt->vdm_header.command_type & CMD_TYPE_MASK) << CMD_TYPE_SHIFT); 178 | header |= ((pkt->vdm_header.command & COMMAND_MASK) << COMMAND_SHIFT); 179 | msg->header.num_data_objects = 0; 180 | msg->pdo[msg->header.num_data_objects++] = header; 181 | 182 | /* 0 REQ, 1 ACK */ 183 | if (pkt->vdm_header.command_type == 1) 184 | { 185 | /* ID Header VDO */ 186 | msg->pdo[msg->header.num_data_objects++] = ((pkt->id_header.usb_host & USB_HOST_MASK) << USB_HOST_SHIFT) | 187 | ((pkt->id_header.usb_device & USB_DEVICE_MASK) << USB_DEVICE_SHIFT) | 188 | ((pkt->id_header.sop_product_type & SOP_PRODUCT_TYPE_MASK) << SOP_PRODUCT_TYPE_SHIFT) | 189 | ((pkt->id_header.modal_operation & MODAL_OPERATION_MASK) << MODAL_OPERATION_SHIFT) | 190 | ((pkt->id_header.usb_vendor_id & USB_VENDOR_ID_MASK) << USB_VENDOR_ID_SHIFT); 191 | 192 | /* Cert Stat VDO */ 193 | msg->pdo[msg->header.num_data_objects++] = pkt->crt_stat.usb_if_xid; 194 | 195 | /* Product VDO */ 196 | msg->pdo[msg->header.num_data_objects++] = ((pkt->product.usb_product_id & USB_PRODUCT_ID_MASK) << USB_PRODUCT_ID_SHIFT) | 197 | ((pkt->product.bcd_device & BCD_DEVICE_MASK) << BCD_DEVICE_SHIFT); 198 | 199 | if (pkt->id_header.sop_product_type == 3 || pkt->id_header.sop_product_type == 4) 200 | { 201 | uint32_t cable_vdo1 = 0; 202 | cable_vdo1 |= (pkt->cable_1.hw_version & HW_VERSION_MASK) << HW_VERSION_SHIFT; 203 | cable_vdo1 |= (pkt->cable_1.fw_version & FW_VERSION_MASK) << FW_VERSION_SHIFT; 204 | cable_vdo1 |= (pkt->cable_1.vdo_version & VDO_VERSION_MASK) << VDO_VERSION_SHIFT; 205 | cable_vdo1 |= (pkt->cable_1.plug_type & PLUG_TYPE_MASK) << PLUG_TYPE_SHIFT; 206 | cable_vdo1 |= (pkt->cable_1.epr_capable & EPR_CAPABLE_MASK) << EPR_CAPABLE_SHIFT; 207 | cable_vdo1 |= (pkt->cable_1.cable_latency & CABLE_LATENCY_MASK) << CABLE_LATENCY_SHIFT; 208 | cable_vdo1 |= (pkt->cable_1.cable_termination & CABLE_TERMINATION_MASK) << CABLE_TERMINATION_SHIFT; 209 | cable_vdo1 |= (pkt->cable_1.max_vbus_voltage & MAX_VBUS_VOLTAGE_MASK) << MAX_VBUS_VOLTAGE_SHIFT; 210 | cable_vdo1 |= (pkt->cable_1.sbu_supported & SBU_SUPPORTED_MASK) << SBU_SUPPORTED_SHIFT; 211 | cable_vdo1 |= (pkt->cable_1.sbu_type & SBU_TYPE_MASK) << SBU_TYPE_SHIFT; 212 | cable_vdo1 |= (pkt->cable_1.vbus_current & VBUS_CURRENT_MASK) << VBUS_CURRENT_SHIFT; 213 | cable_vdo1 |= (pkt->cable_1.vbus_through & VBUS_THROUGH_MASK) << VBUS_THROUGH_SHIFT; 214 | cable_vdo1 |= (pkt->cable_1.sop_controller & SOP_CONTROLLER_MASK) << SOP_CONTROLLER_SHIFT; 215 | cable_vdo1 |= (pkt->cable_1.usb_speed & USB_SPEED_MASK) << USB_SPEED_SHIFT; 216 | msg->pdo[msg->header.num_data_objects++] = cable_vdo1; 217 | 218 | if (pkt->id_header.sop_product_type == 4) 219 | { 220 | /* Cable VDO2 */ 221 | uint32_t cable_vdo2 = 0; 222 | cable_vdo2 |= (pkt->cable_2.max_operating_temp & MAX_OPERATING_TEMP_MASK) << MAX_OPERATING_TEMP_SHIFT; 223 | cable_vdo2 |= (pkt->cable_2.shutdown_temp & SHUTDOWN_TEMP_MASK) << SHUTDOWN_TEMP_SHIFT; 224 | cable_vdo2 |= (pkt->cable_2.u3_cld_power & U3_CLD_POWER_MASK) << U3_CLD_POWER_SHIFT; 225 | cable_vdo2 |= (pkt->cable_2.u3_to_u0_transition & U3_TO_U0_TRANSITION_MASK) << U3_TO_U0_TRANSITION_SHIFT; 226 | cable_vdo2 |= (pkt->cable_2.physical_connection & PHYSICAL_CONNECTION_MASK) << PHYSICAL_CONNECTION_SHIFT; 227 | cable_vdo2 |= (pkt->cable_2.active_element & ACTIVE_ELEMENT_MASK) << ACTIVE_ELEMENT_SHIFT; 228 | cable_vdo2 |= (pkt->cable_2.usb4_supported & USB4_SUPPORTED_MASK) << USB4_SUPPORTED_SHIFT; 229 | cable_vdo2 |= (pkt->cable_2.usb2_hub_hops & USB2_HUB_HOPS_MASK) << USB2_HUB_HOPS_SHIFT; 230 | cable_vdo2 |= (pkt->cable_2.usb2_supported & USB2_SUPPORTED_MASK) << USB2_SUPPORTED_SHIFT; 231 | cable_vdo2 |= (pkt->cable_2.usb3_2_supported & USB3_2_SUPPORTED_MASK) << USB3_2_SUPPORTED_SHIFT; 232 | cable_vdo2 |= (pkt->cable_2.usb_lanes_supported & USB_LANES_SUPPORTED_MASK) << USB_LANES_SUPPORTED_SHIFT; 233 | cable_vdo2 |= (pkt->cable_2.optically_isolated & OPTICALLY_ISOLATED_MASK) << OPTICALLY_ISOLATED_SHIFT; 234 | cable_vdo2 |= (pkt->cable_2.usb4_asymmetric & USB4_ASYMMETRIC_MASK) << USB4_ASYMMETRIC_SHIFT; 235 | cable_vdo2 |= (pkt->cable_2.usb_gen & USB_GEN_MASK) << USB_GEN_SHIFT; 236 | msg->pdo[msg->header.num_data_objects++] = cable_vdo2; 237 | } 238 | } 239 | } 240 | } 241 | 242 | void pd_parse_msg_header(pd_msg_header *hdr, uint8_t *data) 243 | { 244 | uint16_t header = BUILD_LE_UINT16(data, 0); 245 | 246 | /* Extract individual fields */ 247 | hdr->extended = (header >> EXTENDED_SHIFT) & EXTENDED_MASK; 248 | hdr->num_data_objects = (header >> NUM_DATA_OBJ_SHIFT) & NUM_DATA_OBJ_MASK; 249 | hdr->message_id = (header >> MESSAGE_ID_SHIFT) & MESSAGE_ID_MASK; 250 | hdr->power_role = (header >> POWER_ROLE_SHIFT) & POWER_ROLE_MASK; 251 | hdr->spec_revision = (header >> SPEC_REVISION_SHIFT) & SPEC_REVISION_MASK; 252 | hdr->data_role = (header >> DATA_ROLE_SHIFT) & DATA_ROLE_MASK; 253 | hdr->message_type = header & MESSAGE_TYPE_MASK; 254 | } 255 | 256 | void pd_build_msg_header(pd_msg_header *hdr, uint8_t *data) 257 | { 258 | uint16_t header = 0; 259 | 260 | /* Build header from struct fields */ 261 | header |= (hdr->extended & EXTENDED_MASK) << EXTENDED_SHIFT; 262 | header |= (hdr->num_data_objects & NUM_DATA_OBJ_MASK) << NUM_DATA_OBJ_SHIFT; 263 | header |= (hdr->message_id & MESSAGE_ID_MASK) << MESSAGE_ID_SHIFT; 264 | header |= (hdr->power_role & POWER_ROLE_MASK) << POWER_ROLE_SHIFT; 265 | header |= (hdr->spec_revision & SPEC_REVISION_MASK) << SPEC_REVISION_SHIFT; 266 | header |= (hdr->data_role & DATA_ROLE_MASK) << DATA_ROLE_SHIFT; 267 | header |= (hdr->message_type & MESSAGE_TYPE_MASK); 268 | 269 | SPLIT_LE_UINT16(header, data, 0); 270 | } 271 | -------------------------------------------------------------------------------- /src/pd.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | 5 | #include "esp_system.h" 6 | #include "esp_flash.h" 7 | #include "esp_rom_gpio.h" 8 | #include "esp_timer.h" 9 | #include "esp_chip_info.h" 10 | #include "esp_efuse.h" 11 | #include "esp_log.h" 12 | #include "esp_mac.h" 13 | #include "esp_random.h" 14 | #include "driver/gpio.h" 15 | #include "freertos/FreeRTOS.h" 16 | #include "freertos/task.h" 17 | 18 | #include "pd_types.h" 19 | #include "pd_proto.h" 20 | #include "pd_config.h" 21 | #include "pd_rx.h" 22 | #include "pd_tx.h" 23 | #include "pd.h" 24 | #include "crc32.h" 25 | 26 | QueueHandle_t pd_queue_rx_ack; 27 | QueueHandle_t pd_queue_rx_data; 28 | QueueHandle_t pd_queue_rx_data_log; 29 | QueueHandle_t pd_queue_empty; 30 | 31 | static pd_state_t state; 32 | 33 | #define TAG "PD" 34 | 35 | void pd_mode(pd_mode_t mode) 36 | { 37 | gpio_config_t io_conf = { 38 | .intr_type = GPIO_INTR_DISABLE, 39 | .pull_down_en = 0, 40 | .pull_up_en = 0}; 41 | 42 | switch (mode) 43 | { 44 | case PD_MODE_IDLE: 45 | { 46 | #ifdef GPIO_CC1 47 | io_conf.mode = GPIO_MODE_INPUT; 48 | io_conf.pin_bit_mask = (1ULL << GPIO_CC1); 49 | gpio_config(&io_conf); 50 | #endif 51 | 52 | io_conf.mode = GPIO_MODE_INPUT; 53 | io_conf.pin_bit_mask = (1ULL << GPIO_PD); 54 | gpio_config(&io_conf); 55 | 56 | break; 57 | } 58 | 59 | case PD_MODE_SINK: 60 | { 61 | #ifdef GPIO_CC1 62 | io_conf.mode = GPIO_MODE_INPUT; 63 | io_conf.pin_bit_mask = (1ULL << GPIO_CC1); 64 | gpio_config(&io_conf); 65 | #endif 66 | 67 | io_conf.mode = GPIO_MODE_OUTPUT; 68 | io_conf.pin_bit_mask = (1ULL << GPIO_PD); 69 | gpio_config(&io_conf); 70 | 71 | io_conf.mode = GPIO_MODE_INPUT_OUTPUT; 72 | io_conf.pull_down_en = true; 73 | io_conf.pin_bit_mask = (1ULL << GPIO_CC1_IN); 74 | gpio_config(&io_conf); 75 | 76 | gpio_set_drive_capability(GPIO_PD, GPIO_DRIVE_CAP_3); 77 | gpio_set_drive_capability(GPIO_CC1_IN, GPIO_DRIVE_CAP_0); 78 | 79 | gpio_set_level(GPIO_CC1_IN, 1); 80 | gpio_set_level(GPIO_PD, 0); 81 | 82 | break; 83 | } 84 | } 85 | } 86 | 87 | /* Function to initialize the queues and preallocate buffers */ 88 | static void pd_init_queues(void) 89 | { 90 | /* Create queues */ 91 | pd_queue_rx_ack = xQueueCreate(PD_BUFFER_COUNT, sizeof(pd_rx_ack_t)); 92 | if (pd_queue_rx_ack == NULL) 93 | { 94 | ESP_LOGE(TAG, "Failed to create buffer_from_isr_queue"); 95 | return; 96 | } 97 | 98 | pd_queue_rx_data = xQueueCreate(PD_BUFFER_COUNT, sizeof(pd_rx_buf_t *)); 99 | if (pd_queue_rx_data == NULL) 100 | { 101 | ESP_LOGE(TAG, "Failed to create buffer_from_isr_queue"); 102 | return; 103 | } 104 | 105 | pd_queue_rx_data_log = xQueueCreate(PD_BUFFER_COUNT, sizeof(pd_rx_buf_t *)); 106 | if (pd_queue_rx_data_log == NULL) 107 | { 108 | ESP_LOGE(TAG, "Failed to create buffer_from_isr_queue"); 109 | return; 110 | } 111 | 112 | pd_queue_empty = xQueueCreate(PD_BUFFER_COUNT, sizeof(pd_rx_buf_t *)); 113 | if (pd_queue_empty == NULL) 114 | { 115 | ESP_LOGE(TAG, "Failed to create pd_queue_empty"); 116 | return; 117 | } 118 | 119 | /* Preallocate buffers and push them to the pd_queue_empty */ 120 | for (int index = 0; index < PD_BUFFER_COUNT; index++) 121 | { 122 | pd_rx_buf_t *buffer = calloc(1, sizeof(pd_rx_buf_t)); 123 | if (buffer == NULL) 124 | { 125 | ESP_LOGE(TAG, "Failed to allocate buffer %d", index); 126 | break; 127 | } 128 | 129 | if (xQueueSend(pd_queue_empty, &buffer, portMAX_DELAY) != pdTRUE) 130 | { 131 | ESP_LOGE(TAG, "Failed to add buffer %d to pd_queue_empty", index); 132 | free(buffer); 133 | } 134 | } 135 | } 136 | 137 | void pd_protocol_task(void *pvParameters) 138 | { 139 | pd_rx_buf_t *rx_data; 140 | 141 | while (1) 142 | { 143 | if (xQueueReceive(pd_queue_rx_data, &rx_data, 100 / portTICK_PERIOD_MS) != pdTRUE) 144 | { 145 | /* call some functions periodically */ 146 | pd_request_timer(); 147 | continue; 148 | } 149 | 150 | switch (rx_data->type) 151 | { 152 | case PD_BUF_TYPE_DATA: 153 | { 154 | /* if we weren't addressed (we shall not handle), stop here */ 155 | if (rx_data->dir != PD_PACKET_RECEIVED_ACKNOWLEDGED) 156 | { 157 | goto skip; 158 | } 159 | 160 | pd_msg_header hdr; 161 | pd_parse_msg_header(&hdr, rx_data->payload); 162 | 163 | pd_msg rx_msg; 164 | for (int i = 0; i < hdr.num_data_objects; i++) 165 | { 166 | rx_msg.pdo[i] = BUILD_LE_UINT32(rx_data->payload, 2 + i * 4); 167 | } 168 | 169 | /* when no objects, then its a control message */ 170 | if (hdr.num_data_objects == 0) 171 | { 172 | switch (hdr.message_type) 173 | { 174 | case PD_CONTROL_SOFT_RESET: 175 | { 176 | pd_msg response = {0}; 177 | 178 | response.target = rx_data->target; 179 | response.immediate = true; 180 | response.header.num_data_objects = 0; 181 | response.header.power_role = PD_DATA_ROLE_UFP; 182 | response.header.spec_revision = 2; 183 | response.header.data_role = PD_DATA_ROLE_UFP; 184 | response.header.message_type = PD_CONTROL_ACCEPT; 185 | 186 | pd_tx_enqueue(&response); 187 | break; 188 | } 189 | 190 | case PD_CONTROL_GOOD_CRC: 191 | if (hdr.data_role == PD_DATA_ROLE_DFP) 192 | { 193 | pd_tx_ack_received(hdr.message_id); 194 | } 195 | break; 196 | 197 | case PD_CONTROL_REJECT: 198 | if (state.requested_object != 0) 199 | { 200 | state.accepted_object = 0; 201 | state.requested_object = 0; 202 | } 203 | break; 204 | 205 | case PD_CONTROL_ACCEPT: 206 | if (state.requested_object != 0) 207 | { 208 | state.accepted_object = state.requested_object; 209 | } 210 | break; 211 | 212 | case PD_CONTROL_PS_RDY: 213 | break; 214 | default: 215 | break; 216 | } 217 | } 218 | else 219 | { 220 | switch (hdr.message_type) 221 | { 222 | case PD_VENDOR_MESSAGE: 223 | { 224 | pd_vdm_packet req_vdm; 225 | 226 | pd_parse_vdm(&req_vdm, &rx_msg); 227 | 228 | if (rx_data->target == PD_TARGET_SOP_P && req_vdm.vdm_header.command_type == PD_VDM_CMD_TYPE_REQ && req_vdm.vdm_header.command == PD_VDM_CMD_DISCOVER_IDENTIY) 229 | { 230 | #ifdef PD_TEST_EMARKER_CABLE 231 | /* ToDo: this requires proper pulldown on the other CC as well */ 232 | pd_msg response = {0}; 233 | 234 | response.target = PD_TARGET_SOP_P; 235 | response.header.power_role = PD_DATA_ROLE_CABLE; 236 | response.header.spec_revision = 1; 237 | response.header.message_type = PD_VENDOR_MESSAGE; 238 | 239 | pd_vdm_packet resp_vdm = { 240 | .vdm_header = { 241 | .svid = PD_VDM_SID_PD, 242 | .vdm_type = 1, 243 | .vdm_version_major = 1, 244 | .vdm_version_minor = 0, 245 | .object_position = 0, 246 | .command_type = PD_VDM_CMD_TYPE_ACK, 247 | .command = PD_VDM_CMD_DISCOVER_IDENTIY, 248 | }, 249 | .id_header = {.usb_host = 0, .usb_device = 0, .sop_product_type = 3, .modal_operation = 0, .usb_vendor_id = 0xDEAD}, 250 | .crt_stat.usb_if_xid = 0, 251 | .product.bcd_device = 0xBEEF, 252 | .product.usb_product_id = 0xDEAD, 253 | .cable_1 = {.hw_version = 1, .fw_version = 2, .vdo_version = 0, .plug_type = 2, .epr_capable = 1, .cable_latency = 1, .cable_termination = 0, .max_vbus_voltage = 3, .sbu_supported = 0, .sbu_type = 0, .vbus_current = 2, .vbus_through = 1, .usb_speed = 4}, 254 | }; 255 | 256 | pd_build_vdm(&resp_vdm, &response); 257 | 258 | #if 0 259 | /* hardcode to fake an authentic cable */ 260 | response.pdo[0] = 0xFF008041; 261 | response.pdo[1] = 0x18000000; 262 | response.pdo[2] = 0x00000000; 263 | response.pdo[3] = 0x00000000; 264 | response.pdo[4] = 0x00082052; 265 | #endif 266 | 267 | response.header.num_data_objects = 5; 268 | 269 | pd_tx_enqueue(&response); 270 | #endif 271 | } 272 | 273 | break; 274 | } 275 | break; 276 | 277 | case PD_DATA_SOURCE_CAPABILITIES: 278 | { 279 | state.requested_object = 0; 280 | 281 | for (uint32_t index = 0; !state.requested_object && index < hdr.num_data_objects; index++) 282 | { 283 | uint32_t pdo_value = rx_msg.pdo[index]; 284 | uint32_t type = (pdo_value >> 30) & 0x03; 285 | 286 | switch (type) 287 | { 288 | case 0: 289 | { 290 | uint32_t voltage = ((pdo_value >> 10) & 0x3FF) * 50; /* in 50mV units */ 291 | uint32_t current = (pdo_value & 0x3FF) * 10; /* in 10mA units */ 292 | 293 | if (voltage == state.request_voltage_mv && current >= state.request_current_ma) 294 | { 295 | state.requested_object = index + 1; 296 | state.requested_pps = false; 297 | } 298 | break; 299 | } 300 | 301 | case 3: 302 | { 303 | uint32_t subtype = (pdo_value >> 28) & 0x03; 304 | 305 | switch (subtype) 306 | { 307 | case 0: 308 | { 309 | uint32_t max_voltage = ((pdo_value >> 17) & 0xFF) * 100; /* in 100mV units */ 310 | uint32_t min_voltage = ((pdo_value >> 8) & 0xFF) * 100; /* in 100mV units */ 311 | uint32_t max_current = ((pdo_value >> 0) & 0x7F) * 50; /* in 50mA units */ 312 | 313 | if (min_voltage <= state.request_voltage_mv && max_voltage >= state.request_voltage_mv && max_current >= state.request_current_ma) 314 | { 315 | state.requested_object = index + 1; 316 | state.requested_pps = true; 317 | } 318 | 319 | break; 320 | } 321 | default: 322 | break; 323 | } 324 | break; 325 | } 326 | default: 327 | break; 328 | } 329 | } 330 | 331 | if (!state.requested_object) 332 | { 333 | state.requested_object = 1; 334 | } 335 | pd_refresh_request(true); 336 | 337 | break; 338 | } 339 | default: 340 | break; 341 | } 342 | } 343 | 344 | break; 345 | } 346 | case PD_BUF_TYPE_SYMBOLS: 347 | { 348 | if (rx_data->target == PD_TARGET_HARD_RESET) 349 | { 350 | pd_state_reset(); 351 | } 352 | else if (rx_data->target == PD_TARGET_CABLE_RESET) 353 | { 354 | pd_state_reset(); 355 | } 356 | break; 357 | } 358 | default: 359 | { 360 | break; 361 | } 362 | } 363 | 364 | skip: 365 | 366 | /* Return the buffer to the log queue */ 367 | if (xQueueSend(pd_queue_rx_data_log, &rx_data, portMAX_DELAY) != pdTRUE) 368 | { 369 | ESP_LOGE(TAG, "Failed to return buffer to pd_queue_empty"); 370 | free(rx_data); 371 | } 372 | } 373 | } 374 | 375 | void pd_refresh_request(bool immediate) 376 | { 377 | if (state.requested_pps) 378 | { 379 | pd_request_pps(state.requested_object, state.request_voltage_mv, state.request_current_ma, immediate); 380 | } 381 | else 382 | { 383 | pd_request(state.requested_object, state.request_current_ma, immediate); 384 | } 385 | state.request_last_timestamp = esp_timer_get_time(); 386 | } 387 | 388 | void pd_vdm(int command, int mode) 389 | { 390 | pd_msg response = {0}; 391 | 392 | response.target = PD_TARGET_SOP; 393 | response.immediate = false; 394 | response.header.num_data_objects = 0; 395 | response.header.power_role = PD_DATA_ROLE_UFP; 396 | response.header.spec_revision = 2; 397 | response.header.data_role = PD_DATA_ROLE_UFP; 398 | response.header.message_type = PD_VENDOR_MESSAGE; 399 | 400 | pd_tx_enqueue(&response); 401 | } 402 | 403 | void pd_send_control(pd_message_type_t message_id) 404 | { 405 | pd_msg response = {0}; 406 | 407 | response.target = PD_TARGET_SOP; 408 | response.immediate = false; 409 | response.header.num_data_objects = 0; 410 | response.header.power_role = PD_DATA_ROLE_UFP; 411 | response.header.spec_revision = 2; 412 | response.header.data_role = PD_DATA_ROLE_UFP; 413 | response.header.message_type = message_id; 414 | 415 | pd_tx_enqueue(&response); 416 | } 417 | 418 | void pd_request(uint8_t object, uint32_t current_ma, bool immediate) 419 | { 420 | pd_msg response = {0}; 421 | 422 | response.target = PD_TARGET_SOP; 423 | response.immediate = immediate; 424 | response.header.num_data_objects = 1; 425 | response.header.power_role = PD_DATA_ROLE_UFP; 426 | response.header.spec_revision = 2; 427 | response.header.data_role = PD_DATA_ROLE_UFP; 428 | response.header.message_type = PD_DATA_REQUEST; 429 | 430 | response.pdo[0] |= (object) << 28; 431 | response.pdo[0] |= (current_ma / 10) << 10; 432 | response.pdo[0] |= (current_ma / 10) << 0; 433 | 434 | pd_tx_enqueue(&response); 435 | } 436 | 437 | void pd_request_pps(uint8_t object, uint32_t voltage_mv, uint32_t current_ma, bool immediate) 438 | { 439 | pd_msg response = {0}; 440 | 441 | response.target = PD_TARGET_SOP; 442 | response.immediate = immediate; 443 | response.header.num_data_objects = 1; 444 | response.header.power_role = PD_DATA_ROLE_UFP; 445 | response.header.spec_revision = 2; 446 | response.header.data_role = PD_DATA_ROLE_UFP; 447 | response.header.message_type = PD_DATA_REQUEST; 448 | 449 | response.pdo[0] |= (object) << 28; 450 | response.pdo[0] |= (voltage_mv / 20) << 9; 451 | response.pdo[0] |= (current_ma / 50) << 0; 452 | 453 | pd_tx_enqueue(&response); 454 | } 455 | 456 | /* re-request the same object again periodically */ 457 | void pd_request_timer() 458 | { 459 | if (!state.requested_object || !state.accepted_object) 460 | { 461 | return; 462 | } 463 | 464 | if (state.requested_object != state.accepted_object) 465 | { 466 | return; 467 | } 468 | 469 | uint64_t timestamp = esp_timer_get_time(); 470 | if (timestamp - state.request_last_timestamp > (PD_REQUEST_REFRESH_MS) * 1000) 471 | { 472 | pd_refresh_request(false); 473 | } 474 | } 475 | 476 | void pd_log_task(void *pvParameters) 477 | { 478 | pd_rx_buf_t *rx_data; 479 | 480 | while (1) 481 | { 482 | if (xQueueReceive(pd_queue_rx_data_log, &rx_data, portMAX_DELAY) != pdTRUE) 483 | { 484 | continue; 485 | } 486 | 487 | ESP_LOGI(TAG, ""); 488 | 489 | switch (rx_data->type) 490 | { 491 | case PD_BUF_TYPE_DATA: 492 | { 493 | switch (rx_data->target) 494 | { 495 | case PD_TARGET_SOP: 496 | ESP_LOGI(TAG, "Target: SOP"); 497 | break; 498 | case PD_TARGET_SOP_P: 499 | ESP_LOGI(TAG, "Target: SOP'"); 500 | break; 501 | case PD_TARGET_SOP_PP: 502 | ESP_LOGI(TAG, "Target: SOP''"); 503 | break; 504 | case PD_TARGET_SOP_PD: 505 | ESP_LOGI(TAG, "Target: SOP' Debug"); 506 | break; 507 | case PD_TARGET_SOP_PPD: 508 | ESP_LOGI(TAG, "Target: SOP'' Debug"); 509 | break; 510 | case PD_TARGET_HARD_RESET: 511 | ESP_LOGI(TAG, "Target: Hard Reset"); 512 | break; 513 | case PD_TARGET_CABLE_RESET: 514 | ESP_LOGI(TAG, "Target: Cable Reset"); 515 | break; 516 | default: 517 | ESP_LOGI(TAG, "Target: Unknown (0x%02" PRIX8 ")", rx_data->target); 518 | break; 519 | } 520 | 521 | switch (rx_data->dir) 522 | { 523 | case PD_PACKET_RECEIVED: 524 | break; 525 | case PD_PACKET_RECEIVED_ACKNOWLEDGED: 526 | ESP_LOGW(TAG, " Acknowledged"); 527 | break; 528 | case PD_PACKET_SENT: 529 | ESP_LOGE(TAG, " Sent, but no ACK"); 530 | break; 531 | case PD_PACKET_SENT_ACKNOWLEDGED: 532 | ESP_LOGW(TAG, " Sent"); 533 | break; 534 | } 535 | 536 | pd_msg_header hdr; 537 | pd_parse_msg_header(&hdr, rx_data->payload); 538 | 539 | pd_msg rx_msg; 540 | for (int i = 0; i < hdr.num_data_objects; i++) 541 | { 542 | rx_msg.pdo[i] = BUILD_LE_UINT32(rx_data->payload, 2 + i * 4); 543 | } 544 | 545 | /* Print the fields */ 546 | 547 | ESP_LOGI(TAG, " Header Fields%s", (hdr.extended) ? " (extended)" : ""); 548 | 549 | ESP_LOGI(TAG, " DO: %" PRIu8 ", ID: %" PRIu8 ", PPR/CP: %" PRIu8 ", Rev: %" PRIu8 ", PDR: %" PRIu8 ", Type: %" PRIu8 "", 550 | hdr.num_data_objects, hdr.message_id, hdr.power_role, hdr.spec_revision, hdr.data_role, hdr.message_type); 551 | 552 | /* when no objects, then its a control message */ 553 | if (hdr.num_data_objects == 0) 554 | { 555 | ESP_LOGI(TAG, " Control:"); 556 | switch (hdr.message_type) 557 | { 558 | case PD_CONTROL_SOFT_RESET: 559 | ESP_LOGI(TAG, " Soft Reset"); 560 | break; 561 | 562 | case PD_CONTROL_GOOD_CRC: 563 | ESP_LOGI(TAG, " Good CRC"); 564 | break; 565 | 566 | case PD_CONTROL_REJECT: 567 | ESP_LOGI(TAG, " Rejected"); 568 | break; 569 | 570 | case PD_CONTROL_ACCEPT: 571 | ESP_LOGI(TAG, " Accepted"); 572 | break; 573 | 574 | case PD_CONTROL_PS_RDY: 575 | ESP_LOGI(TAG, " Power supply ready"); 576 | break; 577 | 578 | default: 579 | ESP_LOGI(TAG, " Not implemented yet: 0x%02" PRIx8, hdr.message_type); 580 | break; 581 | } 582 | } 583 | else 584 | { 585 | ESP_LOGI(TAG, " Data:"); 586 | switch (hdr.message_type) 587 | { 588 | case PD_VENDOR_MESSAGE: 589 | { 590 | for (uint32_t index = 0; index < hdr.num_data_objects; index++) 591 | { 592 | ESP_LOGI(TAG, " Data #%" PRIu32 ": 0x%08" PRIx32, index, rx_msg.pdo[index]); 593 | } 594 | 595 | pd_vdm_packet vdm; 596 | pd_parse_vdm(&vdm, &rx_msg); 597 | pd_dump_vdm(&vdm); 598 | break; 599 | } 600 | 601 | case PD_DATA_REQUEST: 602 | { 603 | ESP_LOGI(TAG, " Request"); 604 | uint8_t object = ((rx_msg.pdo[0] >> 28) & 0x1F) - 1; 605 | uint32_t operating_current = ((rx_msg.pdo[0] >> 10) & 0x3FF) * 10; 606 | uint32_t max_operating_current = ((rx_msg.pdo[0] >> 0) & 0x3FF) * 10; 607 | ESP_LOGI(TAG, " Object #%" PRIu8 " (ToDo: dumping in fixed format, will not match when it's PPS)", object); 608 | ESP_LOGI(TAG, " Current %" PRIu32 "mA", operating_current); 609 | ESP_LOGI(TAG, " Current Max %" PRIu32 "mA", max_operating_current); 610 | break; 611 | } 612 | 613 | case PD_DATA_SOURCE_CAPABILITIES: 614 | { 615 | ESP_LOGI(TAG, " Source Capabilities:"); 616 | for (uint32_t index = 0; index < hdr.num_data_objects; index++) 617 | { 618 | uint32_t pdo_value = rx_msg.pdo[index]; 619 | uint32_t type = (pdo_value >> 30) & 0x03; 620 | 621 | switch (type) 622 | { 623 | case 0: 624 | { 625 | ESP_LOGI(TAG, " #%" PRIu32 ": Fixed Supply PDO", index); 626 | uint32_t voltage = (pdo_value >> 10) & 0x3FF; /* in 50mV units */ 627 | uint32_t current = pdo_value & 0x3FF; /* in 10mA units */ 628 | uint32_t epr_capable = (pdo_value >> 23) & 0x01; 629 | float watts = (voltage * 50 * current * 10) / 1000000.0; 630 | 631 | ESP_LOGI(TAG, " %" PRIu32 " mV, %" PRIu32 " mA (%2.2f W%s)", 632 | voltage * 50, current * 10, watts, 633 | epr_capable ? ", EPR" : ""); 634 | 635 | break; 636 | } 637 | case 1: 638 | { 639 | ESP_LOGI(TAG, " #%" PRIu32 ": Battery Supply PDO", index); 640 | 641 | uint32_t max_voltage = (pdo_value >> 20) & 0x1FF; /* in 50mV units */ 642 | uint32_t min_voltage = (pdo_value >> 10) & 0x1FF; /* in 50mV units */ 643 | uint32_t max_power = (pdo_value >> 0) & 0x1FF; /* in 250mW units */ 644 | 645 | ESP_LOGI(TAG, " %" PRIu32 " mV - %" PRIu32 " mV, %" PRIu32 " mW", 646 | min_voltage * 50, max_voltage * 50, max_power * 250); 647 | break; 648 | } 649 | case 2: 650 | { 651 | ESP_LOGI(TAG, " #%" PRIu32 ": Variable Supply (non-battery) PDO", index); 652 | 653 | uint32_t max_voltage = (pdo_value >> 20) & 0x1FF; /* in 50mV units */ 654 | uint32_t min_voltage = (pdo_value >> 10) & 0x1FF; /* in 50mV units */ 655 | uint32_t max_power = (pdo_value >> 0) & 0x1FF; /* in 250mW units */ 656 | 657 | ESP_LOGI(TAG, " %" PRIu32 " mV - %" PRIu32 " mV, %" PRIu32 " mW", 658 | min_voltage * 50, max_voltage * 50, max_power * 250); 659 | break; 660 | } 661 | case 3: 662 | { 663 | uint32_t subtype = (pdo_value >> 28) & 0x03; 664 | 665 | switch (subtype) 666 | { 667 | case 0: 668 | { 669 | ESP_LOGI(TAG, " #%" PRIu32 ": Augmented PDO (SPR PPS)", index); 670 | bool limited = (pdo_value >> 27) & 0x01; 671 | uint32_t max_voltage = (pdo_value >> 17) & 0xFF; /* in 100mV units */ 672 | uint32_t min_voltage = (pdo_value >> 8) & 0xFF; /* in 100mV units */ 673 | uint32_t max_current = (pdo_value >> 0) & 0x7F; /* in 50mA units */ 674 | 675 | ESP_LOGI(TAG, " %" PRIu32 " mV - %" PRIu32 " mV, %" PRIu32 " mA (%s)", 676 | min_voltage * 100, max_voltage * 100, max_current * 50, limited ? "Limited" : "Unlimited"); 677 | break; 678 | } 679 | case 1: 680 | { 681 | 682 | ESP_LOGI(TAG, " #%" PRIu32 ": Augmented PDO (EPR AVS)", index); 683 | uint32_t peak_current = (pdo_value >> 26) & 0x03; 684 | uint32_t max_voltage = (pdo_value >> 17) & 0xFF; /* in 100mV units */ 685 | uint32_t min_voltage = (pdo_value >> 8) & 0xFF; /* in 100mV units */ 686 | uint32_t pdp = (pdo_value >> 0) & 0x7F; /* in 1W units */ 687 | 688 | ESP_LOGI(TAG, " Peak Current: %" PRIu32 ", Voltage Range: %" PRIu32 " mV - %" PRIu32 " mV, PDP: %" PRIu32 " W", 689 | peak_current, min_voltage * 100, max_voltage * 100, pdp); 690 | break; 691 | } 692 | case 2: 693 | { 694 | 695 | ESP_LOGI(TAG, " #%" PRIu32 ": Augmented PDO (SPR AVS)", index); 696 | uint32_t peak_current = (pdo_value >> 26) & 0x03; 697 | uint32_t max_current_15 = (pdo_value >> 10) & 0x1FF; /* in 10mA units */ 698 | uint32_t max_current_20 = (pdo_value >> 0) & 0x1FF; /* in 10mA units */ 699 | 700 | ESP_LOGI(TAG, " Peak Current: %" PRIu32 ", %" PRIu32 " mA@15V, %" PRIu32 " mA@20V", 701 | peak_current, max_current_15 * 10, max_current_20 * 10); 702 | break; 703 | } 704 | case 3: 705 | { 706 | 707 | ESP_LOGI(TAG, " #%" PRIu32 ": Augmented PDO (unknown)", index); 708 | break; 709 | } 710 | 711 | default: 712 | break; 713 | } 714 | break; 715 | } 716 | } 717 | } 718 | break; 719 | } 720 | 721 | default: 722 | { 723 | ESP_LOGI(TAG, " Not implemented yet: 0x%02" PRIx8, hdr.message_type); 724 | break; 725 | } 726 | } 727 | } 728 | break; 729 | } 730 | case PD_BUF_TYPE_SYMBOLS: 731 | { 732 | if (rx_data->target == PD_TARGET_HARD_RESET) 733 | { 734 | ESP_LOGE(TAG, "Reset:"); 735 | ESP_LOGE(TAG, " Hard Reset"); 736 | } 737 | else if (rx_data->target == PD_TARGET_CABLE_RESET) 738 | { 739 | ESP_LOGE(TAG, "Reset:"); 740 | ESP_LOGE(TAG, " Cable Reset"); 741 | } 742 | else 743 | { 744 | ESP_LOGE(TAG, "Failed packet:"); 745 | ESP_LOGE(TAG, " Raw symbols:"); 746 | ESP_LOG_BUFFER_HEX(TAG, rx_data->symbols, rx_data->symbol_count); 747 | ESP_LOGE(TAG, " Parsed data:"); 748 | ESP_LOG_BUFFER_HEX(TAG, rx_data->payload, rx_data->length); 749 | } 750 | break; 751 | } 752 | case PD_BUF_TYPE_TIMINGS: 753 | { 754 | ESP_LOGI(TAG, " Timings:"); 755 | ESP_LOG_BUFFER_HEX(TAG, rx_data->symbols, rx_data->symbol_count); 756 | break; 757 | } 758 | default: 759 | { 760 | ESP_LOGI(TAG, " Unknown buffer type"); 761 | break; 762 | } 763 | } 764 | 765 | /* Return the buffer to the empty buffer queue */ 766 | if (xQueueSend(pd_queue_empty, &rx_data, portMAX_DELAY) != pdTRUE) 767 | { 768 | ESP_LOGE(TAG, "Failed to return buffer to pd_queue_empty"); 769 | free(rx_data); 770 | } 771 | 772 | vTaskDelay(10 / portTICK_PERIOD_MS); 773 | } 774 | } 775 | 776 | /** 777 | * @brief Bottom half that handles RX packets from the ISR and triggers the confirmation. 778 | * 779 | * This function is very time-critical as it processes received packets and sends a confirmation 780 | * (GoodCRC) within less than a millisecond. After sending the confirmation, it hands over the 781 | * buffer to the slower user task. 782 | */ 783 | 784 | void IRAM_ATTR pd_rx_ack_task() 785 | { 786 | pd_rx_ack_t ack; 787 | uint8_t buffer[32]; 788 | 789 | while (1) 790 | { 791 | if (xQueueReceive(pd_queue_rx_ack, &ack, portMAX_DELAY) != pdTRUE) 792 | { 793 | continue; 794 | } 795 | 796 | pd_msg response = {0}; 797 | 798 | response.target = ack.target; 799 | response.header.message_id = ack.message_id; 800 | response.header.num_data_objects = 0; 801 | response.header.power_role = PD_DATA_ROLE_UFP; 802 | response.header.spec_revision = 2; 803 | response.header.data_role = PD_DATA_ROLE_UFP; 804 | response.header.message_type = PD_CONTROL_GOOD_CRC; 805 | 806 | size_t length = 0; 807 | buffer[0] = response.target; 808 | length += 1; 809 | 810 | /* construct the 16 bit header */ 811 | pd_build_msg_header(&response.header, &buffer[length]); 812 | length += 2; 813 | 814 | /* finally calc and append the CRC */ 815 | uint32_t crc = crc32buf(&buffer[1], length - 1); 816 | SPLIT_LE_UINT32(crc, buffer, length); 817 | length += 4; 818 | 819 | pd_tx_start(buffer, length); 820 | } 821 | } 822 | 823 | void pd_state_reset() 824 | { 825 | memset(&state, 0, sizeof(state)); 826 | state.request_voltage_mv = 12345; 827 | state.request_current_ma = 1000; 828 | } 829 | 830 | void pd_init() 831 | { 832 | ESP_LOGI(TAG, " * Initialize PD"); 833 | pd_init_queues(); 834 | pd_state_reset(); 835 | 836 | /* the rx_ack task needs highes priority as it has to respons with a RMT tx within a few hundred usec */ 837 | xTaskCreate(pd_rx_ack_task, "pd_rx_ack_task", 4096, NULL, PD_RX_ACK_TASK_PRIO, NULL); 838 | /* the user task turned out to also be a bit "time critical". every CAP message needs to be answered immediately */ 839 | xTaskCreate(pd_protocol_task, "pd_protocol_task", 4096, NULL, PD_PROTOCOL_TASK_PRIO, NULL); 840 | xTaskCreate(pd_log_task, "pd_log_task", 4096, NULL, PD_LOG_TASK_PRIO, NULL); 841 | 842 | ESP_LOGI(TAG, " * Initialize RX"); 843 | pd_rx_init(); 844 | ESP_LOGI(TAG, " * Initialize TX"); 845 | pd_tx_init(); 846 | ESP_LOGI(TAG, " * Enter sink mode"); 847 | pd_mode(PD_MODE_SINK); 848 | 849 | if (0) 850 | { 851 | uint8_t *buf = calloc(1, 100); 852 | while (1) 853 | { 854 | for (int pos = 0; pos < 100; pos++) 855 | { 856 | buf[pos] = (2 * pos) << 4 | (2 * pos + 1); 857 | vTaskDelay(75 / portTICK_PERIOD_MS); 858 | pd_tx_start(buf, 1 + pos); 859 | } 860 | } 861 | } 862 | 863 | if (0) 864 | { 865 | while (1) 866 | { 867 | for (int pos = 0; pos < 100; pos++) 868 | { 869 | vTaskDelay(10000 / portTICK_PERIOD_MS); 870 | 871 | uint8_t buf[64] = {0}; 872 | int pos = 0; 873 | 874 | ESP_LOGI(TAG, " Get status"); 875 | uint16_t header_tx = pd_tx_header(0, 0, state.message_id++, 0, 2, PD_DATA_ROLE_UFP, PD_CONTROL_GET_STATUS); 876 | 877 | buf[pos++] = header_tx; 878 | buf[pos++] = header_tx >> 8; 879 | 880 | uint32_t crc = crc32buf(buf, pos); 881 | buf[pos++] = crc; 882 | buf[pos++] = crc >> 8; 883 | buf[pos++] = crc >> 16; 884 | buf[pos++] = crc >> 24; 885 | 886 | pd_tx(buf, pos); 887 | } 888 | } 889 | } 890 | } 891 | -------------------------------------------------------------------------------- /sdkconfig.lolin_c3_mini: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file. DO NOT EDIT. 3 | # Espressif IoT Development Framework (ESP-IDF) 5.3.1 Project Configuration 4 | # 5 | CONFIG_SOC_ADC_SUPPORTED=y 6 | CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y 7 | CONFIG_SOC_UART_SUPPORTED=y 8 | CONFIG_SOC_GDMA_SUPPORTED=y 9 | CONFIG_SOC_AHB_GDMA_SUPPORTED=y 10 | CONFIG_SOC_GPTIMER_SUPPORTED=y 11 | CONFIG_SOC_TWAI_SUPPORTED=y 12 | CONFIG_SOC_BT_SUPPORTED=y 13 | CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y 14 | CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y 15 | CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y 16 | CONFIG_SOC_XT_WDT_SUPPORTED=y 17 | CONFIG_SOC_PHY_SUPPORTED=y 18 | CONFIG_SOC_WIFI_SUPPORTED=y 19 | CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y 20 | CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y 21 | CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG=y 22 | CONFIG_SOC_EFUSE_SUPPORTED=y 23 | CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y 24 | CONFIG_SOC_RTC_MEM_SUPPORTED=y 25 | CONFIG_SOC_I2S_SUPPORTED=y 26 | CONFIG_SOC_RMT_SUPPORTED=y 27 | CONFIG_SOC_SDM_SUPPORTED=y 28 | CONFIG_SOC_GPSPI_SUPPORTED=y 29 | CONFIG_SOC_LEDC_SUPPORTED=y 30 | CONFIG_SOC_I2C_SUPPORTED=y 31 | CONFIG_SOC_SYSTIMER_SUPPORTED=y 32 | CONFIG_SOC_SUPPORT_COEXISTENCE=y 33 | CONFIG_SOC_AES_SUPPORTED=y 34 | CONFIG_SOC_MPI_SUPPORTED=y 35 | CONFIG_SOC_SHA_SUPPORTED=y 36 | CONFIG_SOC_HMAC_SUPPORTED=y 37 | CONFIG_SOC_DIG_SIGN_SUPPORTED=y 38 | CONFIG_SOC_FLASH_ENC_SUPPORTED=y 39 | CONFIG_SOC_SECURE_BOOT_SUPPORTED=y 40 | CONFIG_SOC_MEMPROT_SUPPORTED=y 41 | CONFIG_SOC_BOD_SUPPORTED=y 42 | CONFIG_SOC_CLK_TREE_SUPPORTED=y 43 | CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y 44 | CONFIG_SOC_WDT_SUPPORTED=y 45 | CONFIG_SOC_SPI_FLASH_SUPPORTED=y 46 | CONFIG_SOC_RNG_SUPPORTED=y 47 | CONFIG_SOC_LIGHT_SLEEP_SUPPORTED=y 48 | CONFIG_SOC_DEEP_SLEEP_SUPPORTED=y 49 | CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT=y 50 | CONFIG_SOC_PM_SUPPORTED=y 51 | CONFIG_SOC_XTAL_SUPPORT_40M=y 52 | CONFIG_SOC_AES_SUPPORT_DMA=y 53 | CONFIG_SOC_AES_GDMA=y 54 | CONFIG_SOC_AES_SUPPORT_AES_128=y 55 | CONFIG_SOC_AES_SUPPORT_AES_256=y 56 | CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y 57 | CONFIG_SOC_ADC_ARBITER_SUPPORTED=y 58 | CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y 59 | CONFIG_SOC_ADC_MONITOR_SUPPORTED=y 60 | CONFIG_SOC_ADC_DMA_SUPPORTED=y 61 | CONFIG_SOC_ADC_PERIPH_NUM=2 62 | CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5 63 | CONFIG_SOC_ADC_ATTEN_NUM=4 64 | CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1 65 | CONFIG_SOC_ADC_PATT_LEN_MAX=8 66 | CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 67 | CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 68 | CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 69 | CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 70 | CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 71 | CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 72 | CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 73 | CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 74 | CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 75 | CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 76 | CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y 77 | CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y 78 | CONFIG_SOC_ADC_SHARED_POWER=y 79 | CONFIG_SOC_APB_BACKUP_DMA=y 80 | CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y 81 | CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y 82 | CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000 83 | CONFIG_SOC_CPU_CORES_NUM=1 84 | CONFIG_SOC_CPU_INTR_NUM=32 85 | CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y 86 | CONFIG_SOC_CPU_HAS_CSR_PC=y 87 | CONFIG_SOC_CPU_BREAKPOINTS_NUM=8 88 | CONFIG_SOC_CPU_WATCHPOINTS_NUM=8 89 | CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x80000000 90 | CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072 91 | CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 92 | CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 93 | CONFIG_SOC_AHB_GDMA_VERSION=1 94 | CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1 95 | CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=3 96 | CONFIG_SOC_GPIO_PORT=1 97 | CONFIG_SOC_GPIO_PIN_COUNT=22 98 | CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y 99 | CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y 100 | CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y 101 | CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y 102 | CONFIG_SOC_GPIO_IN_RANGE_MAX=21 103 | CONFIG_SOC_GPIO_OUT_RANGE_MAX=21 104 | CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0 105 | CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT=6 106 | CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000003FFFC0 107 | CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y 108 | CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM=3 109 | CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 110 | CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 111 | CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y 112 | CONFIG_SOC_I2C_NUM=1 113 | CONFIG_SOC_HP_I2C_NUM=1 114 | CONFIG_SOC_I2C_FIFO_LEN=32 115 | CONFIG_SOC_I2C_CMD_REG_NUM=8 116 | CONFIG_SOC_I2C_SUPPORT_SLAVE=y 117 | CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y 118 | CONFIG_SOC_I2C_SUPPORT_XTAL=y 119 | CONFIG_SOC_I2C_SUPPORT_RTC=y 120 | CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y 121 | CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y 122 | CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE=y 123 | CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y 124 | CONFIG_SOC_I2S_NUM=1 125 | CONFIG_SOC_I2S_HW_VERSION_2=y 126 | CONFIG_SOC_I2S_SUPPORTS_XTAL=y 127 | CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y 128 | CONFIG_SOC_I2S_SUPPORTS_PCM=y 129 | CONFIG_SOC_I2S_SUPPORTS_PDM=y 130 | CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y 131 | CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 132 | CONFIG_SOC_I2S_SUPPORTS_TDM=y 133 | CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y 134 | CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y 135 | CONFIG_SOC_LEDC_CHANNEL_NUM=6 136 | CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 137 | CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y 138 | CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 139 | CONFIG_SOC_MMU_PERIPH_NUM=1 140 | CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 141 | CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 142 | CONFIG_SOC_RMT_GROUPS=1 143 | CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2 144 | CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2 145 | CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4 146 | CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 147 | CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y 148 | CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y 149 | CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y 150 | CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y 151 | CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y 152 | CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y 153 | CONFIG_SOC_RMT_SUPPORT_XTAL=y 154 | CONFIG_SOC_RMT_SUPPORT_APB=y 155 | CONFIG_SOC_RMT_SUPPORT_RC_FAST=y 156 | CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 157 | CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108 158 | CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND=y 159 | CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND=y 160 | CONFIG_SOC_RTCIO_PIN_COUNT=0 161 | CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4 162 | CONFIG_SOC_MPI_OPERATIONS_NUM=3 163 | CONFIG_SOC_RSA_MAX_BIT_LEN=3072 164 | CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 165 | CONFIG_SOC_SHA_SUPPORT_DMA=y 166 | CONFIG_SOC_SHA_SUPPORT_RESUME=y 167 | CONFIG_SOC_SHA_GDMA=y 168 | CONFIG_SOC_SHA_SUPPORT_SHA1=y 169 | CONFIG_SOC_SHA_SUPPORT_SHA224=y 170 | CONFIG_SOC_SHA_SUPPORT_SHA256=y 171 | CONFIG_SOC_SDM_GROUPS=1 172 | CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4 173 | CONFIG_SOC_SDM_CLK_SUPPORT_APB=y 174 | CONFIG_SOC_SPI_PERIPH_NUM=2 175 | CONFIG_SOC_SPI_MAX_CS_NUM=6 176 | CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 177 | CONFIG_SOC_SPI_SUPPORT_DDRCLK=y 178 | CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y 179 | CONFIG_SOC_SPI_SUPPORT_CD_SIG=y 180 | CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y 181 | CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y 182 | CONFIG_SOC_SPI_SUPPORT_CLK_APB=y 183 | CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y 184 | CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y 185 | CONFIG_SOC_SPI_SCT_SUPPORTED=y 186 | CONFIG_SOC_SPI_SCT_REG_NUM=14 187 | CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX=y 188 | CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX=0x3FFFA 189 | CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y 190 | CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 191 | CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y 192 | CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y 193 | CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y 194 | CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y 195 | CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y 196 | CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y 197 | CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y 198 | CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y 199 | CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y 200 | CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y 201 | CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y 202 | CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y 203 | CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 204 | CONFIG_SOC_SYSTIMER_ALARM_NUM=3 205 | CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 206 | CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 207 | CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y 208 | CONFIG_SOC_SYSTIMER_INT_LEVEL=y 209 | CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y 210 | CONFIG_SOC_TIMER_GROUPS=2 211 | CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1 212 | CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 213 | CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y 214 | CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y 215 | CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2 216 | CONFIG_SOC_MWDT_SUPPORT_XTAL=y 217 | CONFIG_SOC_TWAI_CONTROLLER_NUM=1 218 | CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y 219 | CONFIG_SOC_TWAI_BRP_MIN=2 220 | CONFIG_SOC_TWAI_BRP_MAX=16384 221 | CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y 222 | CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y 223 | CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y 224 | CONFIG_SOC_EFUSE_DIS_USB_JTAG=y 225 | CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y 226 | CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y 227 | CONFIG_SOC_EFUSE_DIS_ICACHE=y 228 | CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y 229 | CONFIG_SOC_SECURE_BOOT_V2_RSA=y 230 | CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 231 | CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y 232 | CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y 233 | CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32 234 | CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y 235 | CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y 236 | CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 237 | CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=512 238 | CONFIG_SOC_UART_NUM=2 239 | CONFIG_SOC_UART_HP_NUM=2 240 | CONFIG_SOC_UART_FIFO_LEN=128 241 | CONFIG_SOC_UART_BITRATE_MAX=5000000 242 | CONFIG_SOC_UART_SUPPORT_APB_CLK=y 243 | CONFIG_SOC_UART_SUPPORT_RTC_CLK=y 244 | CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y 245 | CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y 246 | CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y 247 | CONFIG_SOC_COEX_HW_PTI=y 248 | CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 249 | CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 250 | CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 251 | CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y 252 | CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y 253 | CONFIG_SOC_PM_SUPPORT_CPU_PD=y 254 | CONFIG_SOC_PM_SUPPORT_WIFI_PD=y 255 | CONFIG_SOC_PM_SUPPORT_BT_PD=y 256 | CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y 257 | CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y 258 | CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y 259 | CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y 260 | CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y 261 | CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y 262 | CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y 263 | CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y 264 | CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y 265 | CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y 266 | CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y 267 | CONFIG_SOC_WIFI_HW_TSF=y 268 | CONFIG_SOC_WIFI_FTM_SUPPORT=y 269 | CONFIG_SOC_WIFI_GCMP_SUPPORT=y 270 | CONFIG_SOC_WIFI_WAPI_SUPPORT=y 271 | CONFIG_SOC_WIFI_CSI_SUPPORT=y 272 | CONFIG_SOC_WIFI_MESH_SUPPORT=y 273 | CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y 274 | CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND=y 275 | CONFIG_SOC_BLE_SUPPORTED=y 276 | CONFIG_SOC_BLE_MESH_SUPPORTED=y 277 | CONFIG_SOC_BLE_50_SUPPORTED=y 278 | CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y 279 | CONFIG_SOC_BLUFI_SUPPORTED=y 280 | CONFIG_SOC_PHY_COMBO_MODULE=y 281 | CONFIG_IDF_CMAKE=y 282 | CONFIG_IDF_TOOLCHAIN="gcc" 283 | CONFIG_IDF_TARGET_ARCH_RISCV=y 284 | CONFIG_IDF_TARGET_ARCH="riscv" 285 | CONFIG_IDF_TARGET="esp32c3" 286 | CONFIG_IDF_INIT_VERSION="5.3.1" 287 | CONFIG_IDF_TARGET_ESP32C3=y 288 | CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005 289 | 290 | # 291 | # Build type 292 | # 293 | CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y 294 | # CONFIG_APP_BUILD_TYPE_RAM is not set 295 | CONFIG_APP_BUILD_GENERATE_BINARIES=y 296 | CONFIG_APP_BUILD_BOOTLOADER=y 297 | CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y 298 | # CONFIG_APP_REPRODUCIBLE_BUILD is not set 299 | # CONFIG_APP_NO_BLOBS is not set 300 | # end of Build type 301 | 302 | # 303 | # Bootloader config 304 | # 305 | 306 | # 307 | # Bootloader manager 308 | # 309 | CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y 310 | CONFIG_BOOTLOADER_PROJECT_VER=1 311 | # end of Bootloader manager 312 | 313 | CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 314 | CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y 315 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set 316 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set 317 | # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set 318 | # CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set 319 | # CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set 320 | # CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set 321 | CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y 322 | # CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set 323 | # CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set 324 | CONFIG_BOOTLOADER_LOG_LEVEL=3 325 | 326 | # 327 | # Serial Flash Configurations 328 | # 329 | # CONFIG_BOOTLOADER_FLASH_DC_AWARE is not set 330 | CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y 331 | # end of Serial Flash Configurations 332 | 333 | # CONFIG_BOOTLOADER_FACTORY_RESET is not set 334 | # CONFIG_BOOTLOADER_APP_TEST is not set 335 | CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y 336 | CONFIG_BOOTLOADER_WDT_ENABLE=y 337 | # CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set 338 | CONFIG_BOOTLOADER_WDT_TIME_MS=9000 339 | # CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set 340 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set 341 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set 342 | # CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set 343 | CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 344 | # CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set 345 | # end of Bootloader config 346 | 347 | # 348 | # Security features 349 | # 350 | CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y 351 | CONFIG_SECURE_BOOT_V2_PREFERRED=y 352 | # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set 353 | # CONFIG_SECURE_BOOT is not set 354 | # CONFIG_SECURE_FLASH_ENC_ENABLED is not set 355 | CONFIG_SECURE_ROM_DL_MODE_ENABLED=y 356 | # end of Security features 357 | 358 | # 359 | # Application manager 360 | # 361 | CONFIG_APP_COMPILE_TIME_DATE=y 362 | # CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set 363 | # CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set 364 | # CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set 365 | CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9 366 | # end of Application manager 367 | 368 | CONFIG_ESP_ROM_HAS_CRC_LE=y 369 | CONFIG_ESP_ROM_HAS_CRC_BE=y 370 | CONFIG_ESP_ROM_HAS_MZ_CRC32=y 371 | CONFIG_ESP_ROM_HAS_JPEG_DECODE=y 372 | CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y 373 | CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3 374 | CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y 375 | CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y 376 | CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV=y 377 | CONFIG_ESP_ROM_GET_CLK_FREQ=y 378 | CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y 379 | CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y 380 | CONFIG_ESP_ROM_HAS_SPI_FLASH=y 381 | CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y 382 | CONFIG_ESP_ROM_HAS_NEWLIB=y 383 | CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y 384 | CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME=y 385 | CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y 386 | CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y 387 | CONFIG_ESP_ROM_HAS_SW_FLOAT=y 388 | CONFIG_ESP_ROM_USB_OTG_NUM=-1 389 | CONFIG_ESP_ROM_HAS_VERSION=y 390 | CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB=y 391 | 392 | # 393 | # Boot ROM Behavior 394 | # 395 | CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y 396 | # CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set 397 | # CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set 398 | # CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set 399 | # end of Boot ROM Behavior 400 | 401 | # 402 | # Serial flasher config 403 | # 404 | CONFIG_ESPTOOLPY_NO_STUB=y 405 | # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set 406 | # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set 407 | CONFIG_ESPTOOLPY_FLASHMODE_DIO=y 408 | # CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set 409 | CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y 410 | CONFIG_ESPTOOLPY_FLASHMODE="dio" 411 | CONFIG_ESPTOOLPY_FLASHFREQ_80M=y 412 | # CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set 413 | # CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set 414 | # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set 415 | CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y 416 | CONFIG_ESPTOOLPY_FLASHFREQ="80m" 417 | # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set 418 | CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y 419 | # CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set 420 | # CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set 421 | # CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set 422 | # CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set 423 | # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set 424 | # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set 425 | CONFIG_ESPTOOLPY_FLASHSIZE="2MB" 426 | # CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set 427 | CONFIG_ESPTOOLPY_BEFORE_RESET=y 428 | # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set 429 | CONFIG_ESPTOOLPY_BEFORE="default_reset" 430 | CONFIG_ESPTOOLPY_AFTER_RESET=y 431 | # CONFIG_ESPTOOLPY_AFTER_NORESET is not set 432 | CONFIG_ESPTOOLPY_AFTER="hard_reset" 433 | CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 434 | # end of Serial flasher config 435 | 436 | # 437 | # Partition Table 438 | # 439 | CONFIG_PARTITION_TABLE_SINGLE_APP=y 440 | # CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set 441 | # CONFIG_PARTITION_TABLE_TWO_OTA is not set 442 | # CONFIG_PARTITION_TABLE_CUSTOM is not set 443 | CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" 444 | CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" 445 | CONFIG_PARTITION_TABLE_OFFSET=0x8000 446 | CONFIG_PARTITION_TABLE_MD5=y 447 | # end of Partition Table 448 | 449 | # 450 | # Compiler options 451 | # 452 | CONFIG_COMPILER_OPTIMIZATION_DEBUG=y 453 | # CONFIG_COMPILER_OPTIMIZATION_SIZE is not set 454 | # CONFIG_COMPILER_OPTIMIZATION_PERF is not set 455 | # CONFIG_COMPILER_OPTIMIZATION_NONE is not set 456 | CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y 457 | # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set 458 | # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set 459 | CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y 460 | CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 461 | # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set 462 | CONFIG_COMPILER_HIDE_PATHS_MACROS=y 463 | # CONFIG_COMPILER_CXX_EXCEPTIONS is not set 464 | # CONFIG_COMPILER_CXX_RTTI is not set 465 | CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y 466 | # CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set 467 | # CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set 468 | # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set 469 | # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set 470 | # CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS is not set 471 | # CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set 472 | # CONFIG_COMPILER_DISABLE_GCC13_WARNINGS is not set 473 | # CONFIG_COMPILER_DUMP_RTL_FILES is not set 474 | CONFIG_COMPILER_RT_LIB_GCCLIB=y 475 | CONFIG_COMPILER_RT_LIB_NAME="gcc" 476 | # CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING is not set 477 | CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE=y 478 | # end of Compiler options 479 | 480 | # 481 | # Component config 482 | # 483 | 484 | # 485 | # Application Level Tracing 486 | # 487 | # CONFIG_APPTRACE_DEST_JTAG is not set 488 | CONFIG_APPTRACE_DEST_NONE=y 489 | # CONFIG_APPTRACE_DEST_UART0 is not set 490 | # CONFIG_APPTRACE_DEST_UART1 is not set 491 | # CONFIG_APPTRACE_DEST_USB_CDC is not set 492 | CONFIG_APPTRACE_DEST_UART_NONE=y 493 | CONFIG_APPTRACE_UART_TASK_PRIO=1 494 | CONFIG_APPTRACE_LOCK_ENABLE=y 495 | # end of Application Level Tracing 496 | 497 | # 498 | # Bluetooth 499 | # 500 | # CONFIG_BT_ENABLED is not set 501 | CONFIG_BT_ALARM_MAX_NUM=50 502 | # end of Bluetooth 503 | 504 | # 505 | # Console Library 506 | # 507 | # CONFIG_CONSOLE_SORTED_HELP is not set 508 | # end of Console Library 509 | 510 | # 511 | # Driver Configurations 512 | # 513 | 514 | # 515 | # TWAI Configuration 516 | # 517 | # CONFIG_TWAI_ISR_IN_IRAM is not set 518 | CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y 519 | # end of TWAI Configuration 520 | 521 | # 522 | # Legacy ADC Driver Configuration 523 | # 524 | # CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set 525 | 526 | # 527 | # Legacy ADC Calibration Configuration 528 | # 529 | # CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set 530 | # end of Legacy ADC Calibration Configuration 531 | # end of Legacy ADC Driver Configuration 532 | 533 | # 534 | # Legacy Timer Group Driver Configurations 535 | # 536 | # CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set 537 | # end of Legacy Timer Group Driver Configurations 538 | 539 | # 540 | # Legacy RMT Driver Configurations 541 | # 542 | # CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set 543 | # end of Legacy RMT Driver Configurations 544 | 545 | # 546 | # Legacy I2S Driver Configurations 547 | # 548 | # CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set 549 | # end of Legacy I2S Driver Configurations 550 | 551 | # 552 | # Legacy SDM Driver Configurations 553 | # 554 | # CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set 555 | # end of Legacy SDM Driver Configurations 556 | 557 | # 558 | # Legacy Temperature Sensor Driver Configurations 559 | # 560 | # CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set 561 | # end of Legacy Temperature Sensor Driver Configurations 562 | # end of Driver Configurations 563 | 564 | # 565 | # eFuse Bit Manager 566 | # 567 | # CONFIG_EFUSE_CUSTOM_TABLE is not set 568 | # CONFIG_EFUSE_VIRTUAL is not set 569 | CONFIG_EFUSE_MAX_BLK_LEN=256 570 | # end of eFuse Bit Manager 571 | 572 | # 573 | # ESP-TLS 574 | # 575 | CONFIG_ESP_TLS_USING_MBEDTLS=y 576 | CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y 577 | # CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set 578 | # CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set 579 | # CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not set 580 | # CONFIG_ESP_TLS_SERVER_MIN_AUTH_MODE_OPTIONAL is not set 581 | # CONFIG_ESP_TLS_PSK_VERIFICATION is not set 582 | # CONFIG_ESP_TLS_INSECURE is not set 583 | # end of ESP-TLS 584 | 585 | # 586 | # ADC and ADC Calibration 587 | # 588 | # CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set 589 | # CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set 590 | # CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set 591 | # CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set 592 | # CONFIG_ADC_ENABLE_DEBUG_LOG is not set 593 | # end of ADC and ADC Calibration 594 | 595 | # 596 | # Wireless Coexistence 597 | # 598 | CONFIG_ESP_COEX_ENABLED=y 599 | # CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set 600 | # end of Wireless Coexistence 601 | 602 | # 603 | # Common ESP-related 604 | # 605 | CONFIG_ESP_ERR_TO_NAME_LOOKUP=y 606 | # end of Common ESP-related 607 | 608 | # 609 | # ESP-Driver:GPIO Configurations 610 | # 611 | CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y 612 | # end of ESP-Driver:GPIO Configurations 613 | 614 | # 615 | # ESP-Driver:GPTimer Configurations 616 | # 617 | CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y 618 | # CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set 619 | # CONFIG_GPTIMER_ISR_IRAM_SAFE is not set 620 | # CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set 621 | # end of ESP-Driver:GPTimer Configurations 622 | 623 | # 624 | # ESP-Driver:I2C Configurations 625 | # 626 | # CONFIG_I2C_ISR_IRAM_SAFE is not set 627 | # CONFIG_I2C_ENABLE_DEBUG_LOG is not set 628 | # end of ESP-Driver:I2C Configurations 629 | 630 | # 631 | # ESP-Driver:I2S Configurations 632 | # 633 | # CONFIG_I2S_ISR_IRAM_SAFE is not set 634 | # CONFIG_I2S_ENABLE_DEBUG_LOG is not set 635 | # end of ESP-Driver:I2S Configurations 636 | 637 | # 638 | # ESP-Driver:LEDC Configurations 639 | # 640 | # CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set 641 | # end of ESP-Driver:LEDC Configurations 642 | 643 | # 644 | # ESP-Driver:RMT Configurations 645 | # 646 | CONFIG_RMT_ISR_IRAM_SAFE=y 647 | CONFIG_RMT_RECV_FUNC_IN_IRAM=y 648 | CONFIG_RMT_ENABLE_DEBUG_LOG=y 649 | # end of ESP-Driver:RMT Configurations 650 | 651 | # 652 | # ESP-Driver:Sigma Delta Modulator Configurations 653 | # 654 | # CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set 655 | # CONFIG_SDM_ENABLE_DEBUG_LOG is not set 656 | # end of ESP-Driver:Sigma Delta Modulator Configurations 657 | 658 | # 659 | # ESP-Driver:SPI Configurations 660 | # 661 | # CONFIG_SPI_MASTER_IN_IRAM is not set 662 | CONFIG_SPI_MASTER_ISR_IN_IRAM=y 663 | # CONFIG_SPI_SLAVE_IN_IRAM is not set 664 | CONFIG_SPI_SLAVE_ISR_IN_IRAM=y 665 | # end of ESP-Driver:SPI Configurations 666 | 667 | # 668 | # ESP-Driver:Temperature Sensor Configurations 669 | # 670 | # CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set 671 | # end of ESP-Driver:Temperature Sensor Configurations 672 | 673 | # 674 | # ESP-Driver:UART Configurations 675 | # 676 | # CONFIG_UART_ISR_IN_IRAM is not set 677 | # end of ESP-Driver:UART Configurations 678 | 679 | # 680 | # ESP-Driver:USB Serial/JTAG Configuration 681 | # 682 | CONFIG_USJ_ENABLE_USB_SERIAL_JTAG=y 683 | # CONFIG_USJ_NO_AUTO_LS_ON_CONNECTION is not set 684 | # end of ESP-Driver:USB Serial/JTAG Configuration 685 | 686 | # 687 | # Ethernet 688 | # 689 | CONFIG_ETH_ENABLED=y 690 | CONFIG_ETH_USE_SPI_ETHERNET=y 691 | # CONFIG_ETH_SPI_ETHERNET_DM9051 is not set 692 | # CONFIG_ETH_SPI_ETHERNET_W5500 is not set 693 | # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set 694 | # CONFIG_ETH_USE_OPENETH is not set 695 | # CONFIG_ETH_TRANSMIT_MUTEX is not set 696 | # end of Ethernet 697 | 698 | # 699 | # Event Loop Library 700 | # 701 | # CONFIG_ESP_EVENT_LOOP_PROFILING is not set 702 | CONFIG_ESP_EVENT_POST_FROM_ISR=y 703 | CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y 704 | # end of Event Loop Library 705 | 706 | # 707 | # GDB Stub 708 | # 709 | CONFIG_ESP_GDBSTUB_ENABLED=y 710 | # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set 711 | CONFIG_ESP_GDBSTUB_SUPPORT_TASKS=y 712 | CONFIG_ESP_GDBSTUB_MAX_TASKS=32 713 | # end of GDB Stub 714 | 715 | # 716 | # ESP HTTP client 717 | # 718 | CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y 719 | # CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set 720 | # CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set 721 | # CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT is not set 722 | # end of ESP HTTP client 723 | 724 | # 725 | # HTTP Server 726 | # 727 | CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 728 | CONFIG_HTTPD_MAX_URI_LEN=512 729 | CONFIG_HTTPD_ERR_RESP_NO_DELAY=y 730 | CONFIG_HTTPD_PURGE_BUF_LEN=32 731 | # CONFIG_HTTPD_LOG_PURGE_DATA is not set 732 | # CONFIG_HTTPD_WS_SUPPORT is not set 733 | # CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set 734 | # end of HTTP Server 735 | 736 | # 737 | # ESP HTTPS OTA 738 | # 739 | # CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set 740 | # CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set 741 | # end of ESP HTTPS OTA 742 | 743 | # 744 | # ESP HTTPS server 745 | # 746 | # CONFIG_ESP_HTTPS_SERVER_ENABLE is not set 747 | # end of ESP HTTPS server 748 | 749 | # 750 | # Hardware Settings 751 | # 752 | 753 | # 754 | # Chip revision 755 | # 756 | # CONFIG_ESP32C3_REV_MIN_0 is not set 757 | # CONFIG_ESP32C3_REV_MIN_1 is not set 758 | # CONFIG_ESP32C3_REV_MIN_2 is not set 759 | CONFIG_ESP32C3_REV_MIN_3=y 760 | # CONFIG_ESP32C3_REV_MIN_4 is not set 761 | # CONFIG_ESP32C3_REV_MIN_101 is not set 762 | CONFIG_ESP32C3_REV_MIN_FULL=3 763 | CONFIG_ESP_REV_MIN_FULL=3 764 | 765 | # 766 | # Maximum Supported ESP32-C3 Revision (Rev v1.99) 767 | # 768 | CONFIG_ESP32C3_REV_MAX_FULL=199 769 | CONFIG_ESP_REV_MAX_FULL=199 770 | # end of Chip revision 771 | 772 | # 773 | # MAC Config 774 | # 775 | CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y 776 | CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y 777 | CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y 778 | CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y 779 | CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y 780 | CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES=4 781 | # CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set 782 | CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y 783 | CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4 784 | # CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set 785 | # end of MAC Config 786 | 787 | # 788 | # Sleep Config 789 | # 790 | # CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set 791 | CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y 792 | # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set 793 | CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y 794 | CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0 795 | # CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set 796 | # CONFIG_ESP_SLEEP_DEBUG is not set 797 | CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y 798 | # CONFIG_ESP_SLEEP_EVENT_CALLBACKS is not set 799 | # end of Sleep Config 800 | 801 | # 802 | # RTC Clock Config 803 | # 804 | CONFIG_RTC_CLK_SRC_INT_RC=y 805 | # CONFIG_RTC_CLK_SRC_EXT_CRYS is not set 806 | # CONFIG_RTC_CLK_SRC_EXT_OSC is not set 807 | # CONFIG_RTC_CLK_SRC_INT_8MD256 is not set 808 | CONFIG_RTC_CLK_CAL_CYCLES=1024 809 | # end of RTC Clock Config 810 | 811 | # 812 | # Peripheral Control 813 | # 814 | CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y 815 | # end of Peripheral Control 816 | 817 | # 818 | # GDMA Configurations 819 | # 820 | CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y 821 | # CONFIG_GDMA_ISR_IRAM_SAFE is not set 822 | # CONFIG_GDMA_ENABLE_DEBUG_LOG is not set 823 | # end of GDMA Configurations 824 | 825 | # 826 | # Main XTAL Config 827 | # 828 | CONFIG_XTAL_FREQ_40=y 829 | CONFIG_XTAL_FREQ=40 830 | # end of Main XTAL Config 831 | 832 | CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y 833 | # end of Hardware Settings 834 | 835 | # 836 | # LCD and Touch Panel 837 | # 838 | 839 | # 840 | # LCD Touch Drivers are maintained in the IDF Component Registry 841 | # 842 | 843 | # 844 | # LCD Peripheral Configuration 845 | # 846 | # CONFIG_LCD_ENABLE_DEBUG_LOG is not set 847 | # end of LCD Peripheral Configuration 848 | # end of LCD and Touch Panel 849 | 850 | # 851 | # ESP NETIF Adapter 852 | # 853 | CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 854 | CONFIG_ESP_NETIF_TCPIP_LWIP=y 855 | # CONFIG_ESP_NETIF_LOOPBACK is not set 856 | CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y 857 | # CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set 858 | # CONFIG_ESP_NETIF_L2_TAP is not set 859 | # CONFIG_ESP_NETIF_BRIDGE_EN is not set 860 | # end of ESP NETIF Adapter 861 | 862 | # 863 | # Partition API Configuration 864 | # 865 | # end of Partition API Configuration 866 | 867 | # 868 | # PHY 869 | # 870 | CONFIG_ESP_PHY_ENABLED=y 871 | CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y 872 | # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set 873 | CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 874 | CONFIG_ESP_PHY_MAX_TX_POWER=20 875 | # CONFIG_ESP_PHY_MAC_BB_PD is not set 876 | # CONFIG_ESP_PHY_REDUCE_TX_POWER is not set 877 | CONFIG_ESP_PHY_ENABLE_USB=y 878 | # CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set 879 | CONFIG_ESP_PHY_RF_CAL_PARTIAL=y 880 | # CONFIG_ESP_PHY_RF_CAL_NONE is not set 881 | # CONFIG_ESP_PHY_RF_CAL_FULL is not set 882 | CONFIG_ESP_PHY_CALIBRATION_MODE=0 883 | # CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set 884 | # end of PHY 885 | 886 | # 887 | # Power Management 888 | # 889 | CONFIG_PM_ENABLE=y 890 | CONFIG_PM_DFS_INIT_AUTO=y 891 | # CONFIG_PM_PROFILING is not set 892 | # CONFIG_PM_TRACE is not set 893 | # CONFIG_PM_SLP_IRAM_OPT is not set 894 | # CONFIG_PM_RTOS_IDLE_OPT is not set 895 | CONFIG_PM_SLP_DISABLE_GPIO=y 896 | CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL=1 897 | CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y 898 | # CONFIG_PM_LIGHT_SLEEP_CALLBACKS is not set 899 | # end of Power Management 900 | 901 | # 902 | # ESP PSRAM 903 | # 904 | 905 | # 906 | # ESP Ringbuf 907 | # 908 | # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set 909 | # end of ESP Ringbuf 910 | 911 | # 912 | # ESP System Settings 913 | # 914 | # CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set 915 | CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y 916 | CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 917 | # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set 918 | CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y 919 | # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set 920 | # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set 921 | CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 922 | CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y 923 | CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y 924 | CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y 925 | # CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set 926 | 927 | # 928 | # Memory protection 929 | # 930 | CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y 931 | CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y 932 | # end of Memory protection 933 | 934 | CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 935 | CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 936 | CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 937 | CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y 938 | # CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set 939 | CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 940 | CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 941 | # CONFIG_ESP_CONSOLE_UART_DEFAULT is not set 942 | CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y 943 | # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set 944 | # CONFIG_ESP_CONSOLE_NONE is not set 945 | CONFIG_ESP_CONSOLE_SECONDARY_NONE=y 946 | CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y 947 | CONFIG_ESP_CONSOLE_UART_NUM=-1 948 | CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM=3 949 | CONFIG_ESP_INT_WDT=y 950 | CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 951 | CONFIG_ESP_TASK_WDT_EN=y 952 | CONFIG_ESP_TASK_WDT_INIT=y 953 | # CONFIG_ESP_TASK_WDT_PANIC is not set 954 | CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 955 | CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 956 | # CONFIG_ESP_PANIC_HANDLER_IRAM is not set 957 | # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set 958 | CONFIG_ESP_DEBUG_OCDAWARE=y 959 | CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y 960 | 961 | # 962 | # Brownout Detector 963 | # 964 | CONFIG_ESP_BROWNOUT_DET=y 965 | CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y 966 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set 967 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set 968 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set 969 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set 970 | # CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set 971 | CONFIG_ESP_BROWNOUT_DET_LVL=7 972 | # end of Brownout Detector 973 | 974 | CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y 975 | CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y 976 | CONFIG_ESP_SYSTEM_HW_PC_RECORD=y 977 | # end of ESP System Settings 978 | 979 | # 980 | # IPC (Inter-Processor Call) 981 | # 982 | CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 983 | # end of IPC (Inter-Processor Call) 984 | 985 | # 986 | # ESP Timer (High Resolution Timer) 987 | # 988 | # CONFIG_ESP_TIMER_PROFILING is not set 989 | CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y 990 | CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y 991 | CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 992 | CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 993 | # CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set 994 | CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 995 | CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y 996 | CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y 997 | # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set 998 | CONFIG_ESP_TIMER_IMPL_SYSTIMER=y 999 | # end of ESP Timer (High Resolution Timer) 1000 | 1001 | # 1002 | # Wi-Fi 1003 | # 1004 | CONFIG_ESP_WIFI_ENABLED=y 1005 | CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 1006 | CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 1007 | # CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set 1008 | CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y 1009 | CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1 1010 | CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32 1011 | CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER=y 1012 | # CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUFFER is not set 1013 | CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF=0 1014 | CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF=5 1015 | # CONFIG_ESP_WIFI_CSI_ENABLED is not set 1016 | CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y 1017 | CONFIG_ESP_WIFI_TX_BA_WIN=6 1018 | CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y 1019 | CONFIG_ESP_WIFI_RX_BA_WIN=6 1020 | CONFIG_ESP_WIFI_NVS_ENABLED=y 1021 | CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 1022 | CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 1023 | CONFIG_ESP_WIFI_IRAM_OPT=y 1024 | # CONFIG_ESP_WIFI_EXTRA_IRAM_OPT is not set 1025 | CONFIG_ESP_WIFI_RX_IRAM_OPT=y 1026 | CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y 1027 | CONFIG_ESP_WIFI_ENABLE_SAE_PK=y 1028 | CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y 1029 | CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y 1030 | # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set 1031 | CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50 1032 | CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10 1033 | CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15 1034 | # CONFIG_ESP_WIFI_FTM_ENABLE is not set 1035 | CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y 1036 | # CONFIG_ESP_WIFI_GCMP_SUPPORT is not set 1037 | CONFIG_ESP_WIFI_GMAC_SUPPORT=y 1038 | CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y 1039 | # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set 1040 | CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 1041 | CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y 1042 | CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y 1043 | # CONFIG_ESP_WIFI_EAP_TLS1_3 is not set 1044 | # CONFIG_ESP_WIFI_WAPI_PSK is not set 1045 | # CONFIG_ESP_WIFI_SUITE_B_192 is not set 1046 | # CONFIG_ESP_WIFI_11KV_SUPPORT is not set 1047 | # CONFIG_ESP_WIFI_MBO_SUPPORT is not set 1048 | # CONFIG_ESP_WIFI_ENABLE_ROAMING_APP is not set 1049 | # CONFIG_ESP_WIFI_DPP_SUPPORT is not set 1050 | # CONFIG_ESP_WIFI_11R_SUPPORT is not set 1051 | # CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set 1052 | 1053 | # 1054 | # WPS Configuration Options 1055 | # 1056 | # CONFIG_ESP_WIFI_WPS_STRICT is not set 1057 | # CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set 1058 | # end of WPS Configuration Options 1059 | 1060 | # CONFIG_ESP_WIFI_DEBUG_PRINT is not set 1061 | # CONFIG_ESP_WIFI_TESTING_OPTIONS is not set 1062 | CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT=y 1063 | # CONFIG_ESP_WIFI_ENT_FREE_DYNAMIC_BUFFER is not set 1064 | # end of Wi-Fi 1065 | 1066 | # 1067 | # Core dump 1068 | # 1069 | # CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set 1070 | # CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set 1071 | CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y 1072 | # end of Core dump 1073 | 1074 | # 1075 | # FAT Filesystem support 1076 | # 1077 | CONFIG_FATFS_VOLUME_COUNT=2 1078 | CONFIG_FATFS_LFN_NONE=y 1079 | # CONFIG_FATFS_LFN_HEAP is not set 1080 | # CONFIG_FATFS_LFN_STACK is not set 1081 | # CONFIG_FATFS_SECTOR_512 is not set 1082 | CONFIG_FATFS_SECTOR_4096=y 1083 | # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set 1084 | CONFIG_FATFS_CODEPAGE_437=y 1085 | # CONFIG_FATFS_CODEPAGE_720 is not set 1086 | # CONFIG_FATFS_CODEPAGE_737 is not set 1087 | # CONFIG_FATFS_CODEPAGE_771 is not set 1088 | # CONFIG_FATFS_CODEPAGE_775 is not set 1089 | # CONFIG_FATFS_CODEPAGE_850 is not set 1090 | # CONFIG_FATFS_CODEPAGE_852 is not set 1091 | # CONFIG_FATFS_CODEPAGE_855 is not set 1092 | # CONFIG_FATFS_CODEPAGE_857 is not set 1093 | # CONFIG_FATFS_CODEPAGE_860 is not set 1094 | # CONFIG_FATFS_CODEPAGE_861 is not set 1095 | # CONFIG_FATFS_CODEPAGE_862 is not set 1096 | # CONFIG_FATFS_CODEPAGE_863 is not set 1097 | # CONFIG_FATFS_CODEPAGE_864 is not set 1098 | # CONFIG_FATFS_CODEPAGE_865 is not set 1099 | # CONFIG_FATFS_CODEPAGE_866 is not set 1100 | # CONFIG_FATFS_CODEPAGE_869 is not set 1101 | # CONFIG_FATFS_CODEPAGE_932 is not set 1102 | # CONFIG_FATFS_CODEPAGE_936 is not set 1103 | # CONFIG_FATFS_CODEPAGE_949 is not set 1104 | # CONFIG_FATFS_CODEPAGE_950 is not set 1105 | CONFIG_FATFS_CODEPAGE=437 1106 | CONFIG_FATFS_FS_LOCK=0 1107 | CONFIG_FATFS_TIMEOUT_MS=10000 1108 | CONFIG_FATFS_PER_FILE_CACHE=y 1109 | # CONFIG_FATFS_USE_FASTSEEK is not set 1110 | CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 1111 | # CONFIG_FATFS_IMMEDIATE_FSYNC is not set 1112 | # CONFIG_FATFS_USE_LABEL is not set 1113 | CONFIG_FATFS_LINK_LOCK=y 1114 | # end of FAT Filesystem support 1115 | 1116 | # 1117 | # FreeRTOS 1118 | # 1119 | 1120 | # 1121 | # Kernel 1122 | # 1123 | # CONFIG_FREERTOS_SMP is not set 1124 | CONFIG_FREERTOS_UNICORE=y 1125 | CONFIG_FREERTOS_HZ=100 1126 | CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y 1127 | # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set 1128 | # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set 1129 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y 1130 | CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 1131 | CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=4096 1132 | # CONFIG_FREERTOS_USE_IDLE_HOOK is not set 1133 | # CONFIG_FREERTOS_USE_TICK_HOOK is not set 1134 | CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 1135 | # CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set 1136 | CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME="Tmr Svc" 1137 | # CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU0 is not set 1138 | CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY=y 1139 | CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY=0x7FFFFFFF 1140 | CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 1141 | CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 1142 | CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 1143 | CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 1144 | CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 1145 | # CONFIG_FREERTOS_USE_TRACE_FACILITY is not set 1146 | # CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES is not set 1147 | # CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set 1148 | CONFIG_FREERTOS_USE_TICKLESS_IDLE=y 1149 | CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP=3 1150 | # CONFIG_FREERTOS_USE_APPLICATION_TASK_TAG is not set 1151 | # end of Kernel 1152 | 1153 | # 1154 | # Port 1155 | # 1156 | CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y 1157 | CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y 1158 | CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y 1159 | # CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK is not set 1160 | # CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set 1161 | CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y 1162 | CONFIG_FREERTOS_ISR_STACKSIZE=4096 1163 | CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y 1164 | CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y 1165 | CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y 1166 | # CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set 1167 | CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y 1168 | # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set 1169 | # CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set 1170 | # end of Port 1171 | 1172 | CONFIG_FREERTOS_PORT=y 1173 | CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF 1174 | CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y 1175 | CONFIG_FREERTOS_DEBUG_OCDAWARE=y 1176 | CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y 1177 | CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y 1178 | CONFIG_FREERTOS_NUMBER_OF_CORES=1 1179 | # end of FreeRTOS 1180 | 1181 | # 1182 | # Hardware Abstraction Layer (HAL) and Low Level (LL) 1183 | # 1184 | CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y 1185 | # CONFIG_HAL_ASSERTION_DISABLE is not set 1186 | # CONFIG_HAL_ASSERTION_SILENT is not set 1187 | # CONFIG_HAL_ASSERTION_ENABLE is not set 1188 | CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 1189 | CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y 1190 | CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y 1191 | # end of Hardware Abstraction Layer (HAL) and Low Level (LL) 1192 | 1193 | # 1194 | # Heap memory debugging 1195 | # 1196 | CONFIG_HEAP_POISONING_DISABLED=y 1197 | # CONFIG_HEAP_POISONING_LIGHT is not set 1198 | # CONFIG_HEAP_POISONING_COMPREHENSIVE is not set 1199 | CONFIG_HEAP_TRACING_OFF=y 1200 | # CONFIG_HEAP_TRACING_STANDALONE is not set 1201 | # CONFIG_HEAP_TRACING_TOHOST is not set 1202 | # CONFIG_HEAP_USE_HOOKS is not set 1203 | # CONFIG_HEAP_TASK_TRACKING is not set 1204 | # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set 1205 | # CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set 1206 | # end of Heap memory debugging 1207 | 1208 | # 1209 | # Log output 1210 | # 1211 | # CONFIG_LOG_DEFAULT_LEVEL_NONE is not set 1212 | # CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set 1213 | # CONFIG_LOG_DEFAULT_LEVEL_WARN is not set 1214 | CONFIG_LOG_DEFAULT_LEVEL_INFO=y 1215 | # CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set 1216 | # CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set 1217 | CONFIG_LOG_DEFAULT_LEVEL=3 1218 | CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y 1219 | # CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set 1220 | # CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set 1221 | CONFIG_LOG_MAXIMUM_LEVEL=3 1222 | # CONFIG_LOG_MASTER_LEVEL is not set 1223 | CONFIG_LOG_COLORS=y 1224 | CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y 1225 | # CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set 1226 | # end of Log output 1227 | 1228 | # 1229 | # LWIP 1230 | # 1231 | CONFIG_LWIP_ENABLE=y 1232 | CONFIG_LWIP_LOCAL_HOSTNAME="espressif" 1233 | # CONFIG_LWIP_NETIF_API is not set 1234 | CONFIG_LWIP_TCPIP_TASK_PRIO=18 1235 | # CONFIG_LWIP_TCPIP_CORE_LOCKING is not set 1236 | # CONFIG_LWIP_CHECK_THREAD_SAFETY is not set 1237 | CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y 1238 | # CONFIG_LWIP_L2_TO_L3_COPY is not set 1239 | # CONFIG_LWIP_IRAM_OPTIMIZATION is not set 1240 | # CONFIG_LWIP_EXTRA_IRAM_OPTIMIZATION is not set 1241 | CONFIG_LWIP_TIMERS_ONDEMAND=y 1242 | CONFIG_LWIP_ND6=y 1243 | # CONFIG_LWIP_FORCE_ROUTER_FORWARDING is not set 1244 | CONFIG_LWIP_MAX_SOCKETS=10 1245 | # CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set 1246 | # CONFIG_LWIP_SO_LINGER is not set 1247 | CONFIG_LWIP_SO_REUSE=y 1248 | CONFIG_LWIP_SO_REUSE_RXTOALL=y 1249 | # CONFIG_LWIP_SO_RCVBUF is not set 1250 | # CONFIG_LWIP_NETBUF_RECVINFO is not set 1251 | CONFIG_LWIP_IP_DEFAULT_TTL=64 1252 | CONFIG_LWIP_IP4_FRAG=y 1253 | CONFIG_LWIP_IP6_FRAG=y 1254 | # CONFIG_LWIP_IP4_REASSEMBLY is not set 1255 | # CONFIG_LWIP_IP6_REASSEMBLY is not set 1256 | CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 1257 | # CONFIG_LWIP_IP_FORWARD is not set 1258 | # CONFIG_LWIP_STATS is not set 1259 | CONFIG_LWIP_ESP_GRATUITOUS_ARP=y 1260 | CONFIG_LWIP_GARP_TMR_INTERVAL=60 1261 | CONFIG_LWIP_ESP_MLDV6_REPORT=y 1262 | CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 1263 | CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 1264 | CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y 1265 | # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set 1266 | CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y 1267 | # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set 1268 | CONFIG_LWIP_DHCP_OPTIONS_LEN=68 1269 | CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 1270 | CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 1271 | 1272 | # 1273 | # DHCP server 1274 | # 1275 | CONFIG_LWIP_DHCPS=y 1276 | CONFIG_LWIP_DHCPS_LEASE_UNIT=60 1277 | CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 1278 | CONFIG_LWIP_DHCPS_STATIC_ENTRIES=y 1279 | # end of DHCP server 1280 | 1281 | # CONFIG_LWIP_AUTOIP is not set 1282 | CONFIG_LWIP_IPV4=y 1283 | CONFIG_LWIP_IPV6=y 1284 | # CONFIG_LWIP_IPV6_AUTOCONFIG is not set 1285 | CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 1286 | # CONFIG_LWIP_IPV6_FORWARD is not set 1287 | # CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set 1288 | CONFIG_LWIP_NETIF_LOOPBACK=y 1289 | CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 1290 | 1291 | # 1292 | # TCP 1293 | # 1294 | CONFIG_LWIP_MAX_ACTIVE_TCP=16 1295 | CONFIG_LWIP_MAX_LISTENING_TCP=16 1296 | CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y 1297 | CONFIG_LWIP_TCP_MAXRTX=12 1298 | CONFIG_LWIP_TCP_SYNMAXRTX=12 1299 | CONFIG_LWIP_TCP_MSS=1440 1300 | CONFIG_LWIP_TCP_TMR_INTERVAL=250 1301 | CONFIG_LWIP_TCP_MSL=60000 1302 | CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 1303 | CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5760 1304 | CONFIG_LWIP_TCP_WND_DEFAULT=5760 1305 | CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 1306 | CONFIG_LWIP_TCP_ACCEPTMBOX_SIZE=6 1307 | CONFIG_LWIP_TCP_QUEUE_OOSEQ=y 1308 | CONFIG_LWIP_TCP_OOSEQ_TIMEOUT=6 1309 | CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS=4 1310 | # CONFIG_LWIP_TCP_SACK_OUT is not set 1311 | CONFIG_LWIP_TCP_OVERSIZE_MSS=y 1312 | # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set 1313 | # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set 1314 | CONFIG_LWIP_TCP_RTO_TIME=1500 1315 | # end of TCP 1316 | 1317 | # 1318 | # UDP 1319 | # 1320 | CONFIG_LWIP_MAX_UDP_PCBS=16 1321 | CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 1322 | # end of UDP 1323 | 1324 | # 1325 | # Checksums 1326 | # 1327 | # CONFIG_LWIP_CHECKSUM_CHECK_IP is not set 1328 | # CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set 1329 | CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y 1330 | # end of Checksums 1331 | 1332 | CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 1333 | CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y 1334 | # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set 1335 | CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF 1336 | # CONFIG_LWIP_PPP_SUPPORT is not set 1337 | CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 1338 | CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 1339 | # CONFIG_LWIP_SLIP_SUPPORT is not set 1340 | 1341 | # 1342 | # ICMP 1343 | # 1344 | CONFIG_LWIP_ICMP=y 1345 | # CONFIG_LWIP_MULTICAST_PING is not set 1346 | # CONFIG_LWIP_BROADCAST_PING is not set 1347 | # end of ICMP 1348 | 1349 | # 1350 | # LWIP RAW API 1351 | # 1352 | CONFIG_LWIP_MAX_RAW_PCBS=16 1353 | # end of LWIP RAW API 1354 | 1355 | # 1356 | # SNTP 1357 | # 1358 | CONFIG_LWIP_SNTP_MAX_SERVERS=1 1359 | # CONFIG_LWIP_DHCP_GET_NTP_SRV is not set 1360 | CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 1361 | CONFIG_LWIP_SNTP_STARTUP_DELAY=y 1362 | CONFIG_LWIP_SNTP_MAXIMUM_STARTUP_DELAY=5000 1363 | # end of SNTP 1364 | 1365 | # 1366 | # DNS 1367 | # 1368 | CONFIG_LWIP_DNS_MAX_SERVERS=3 1369 | # CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set 1370 | # end of DNS 1371 | 1372 | CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 1373 | CONFIG_LWIP_ESP_LWIP_ASSERT=y 1374 | 1375 | # 1376 | # Hooks 1377 | # 1378 | # CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set 1379 | CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y 1380 | # CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set 1381 | CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y 1382 | # CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set 1383 | # CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set 1384 | CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y 1385 | # CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set 1386 | # CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set 1387 | CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y 1388 | # CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set 1389 | # CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set 1390 | CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y 1391 | # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set 1392 | # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set 1393 | CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y 1394 | # CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set 1395 | # CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set 1396 | # end of Hooks 1397 | 1398 | # CONFIG_LWIP_DEBUG is not set 1399 | # end of LWIP 1400 | 1401 | # 1402 | # mbedTLS 1403 | # 1404 | CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y 1405 | # CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set 1406 | # CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set 1407 | CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y 1408 | CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 1409 | CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 1410 | # CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set 1411 | # CONFIG_MBEDTLS_DEBUG is not set 1412 | 1413 | # 1414 | # mbedTLS v3.x related 1415 | # 1416 | # CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set 1417 | # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set 1418 | # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set 1419 | # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set 1420 | CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y 1421 | CONFIG_MBEDTLS_PKCS7_C=y 1422 | # end of mbedTLS v3.x related 1423 | 1424 | # 1425 | # Certificate Bundle 1426 | # 1427 | CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y 1428 | CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y 1429 | # CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set 1430 | # CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set 1431 | # CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set 1432 | # CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEPRECATED_LIST is not set 1433 | CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 1434 | # end of Certificate Bundle 1435 | 1436 | # CONFIG_MBEDTLS_ECP_RESTARTABLE is not set 1437 | CONFIG_MBEDTLS_CMAC_C=y 1438 | CONFIG_MBEDTLS_HARDWARE_AES=y 1439 | CONFIG_MBEDTLS_AES_USE_INTERRUPT=y 1440 | CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL=0 1441 | CONFIG_MBEDTLS_GCM_SUPPORT_NON_AES_CIPHER=y 1442 | CONFIG_MBEDTLS_HARDWARE_MPI=y 1443 | CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y 1444 | CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y 1445 | CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0 1446 | CONFIG_MBEDTLS_HARDWARE_SHA=y 1447 | CONFIG_MBEDTLS_ROM_MD5=y 1448 | # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set 1449 | # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set 1450 | CONFIG_MBEDTLS_HAVE_TIME=y 1451 | # CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set 1452 | # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set 1453 | CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y 1454 | CONFIG_MBEDTLS_SHA512_C=y 1455 | CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y 1456 | # CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set 1457 | # CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set 1458 | # CONFIG_MBEDTLS_TLS_DISABLED is not set 1459 | CONFIG_MBEDTLS_TLS_SERVER=y 1460 | CONFIG_MBEDTLS_TLS_CLIENT=y 1461 | CONFIG_MBEDTLS_TLS_ENABLED=y 1462 | 1463 | # 1464 | # TLS Key Exchange Methods 1465 | # 1466 | # CONFIG_MBEDTLS_PSK_MODES is not set 1467 | CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y 1468 | CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y 1469 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y 1470 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y 1471 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y 1472 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y 1473 | # end of TLS Key Exchange Methods 1474 | 1475 | CONFIG_MBEDTLS_SSL_RENEGOTIATION=y 1476 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y 1477 | # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set 1478 | # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set 1479 | CONFIG_MBEDTLS_SSL_ALPN=y 1480 | CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y 1481 | CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y 1482 | 1483 | # 1484 | # Symmetric Ciphers 1485 | # 1486 | CONFIG_MBEDTLS_AES_C=y 1487 | # CONFIG_MBEDTLS_CAMELLIA_C is not set 1488 | # CONFIG_MBEDTLS_DES_C is not set 1489 | # CONFIG_MBEDTLS_BLOWFISH_C is not set 1490 | # CONFIG_MBEDTLS_XTEA_C is not set 1491 | CONFIG_MBEDTLS_CCM_C=y 1492 | CONFIG_MBEDTLS_GCM_C=y 1493 | # CONFIG_MBEDTLS_NIST_KW_C is not set 1494 | # end of Symmetric Ciphers 1495 | 1496 | # CONFIG_MBEDTLS_RIPEMD160_C is not set 1497 | 1498 | # 1499 | # Certificates 1500 | # 1501 | CONFIG_MBEDTLS_PEM_PARSE_C=y 1502 | CONFIG_MBEDTLS_PEM_WRITE_C=y 1503 | CONFIG_MBEDTLS_X509_CRL_PARSE_C=y 1504 | CONFIG_MBEDTLS_X509_CSR_PARSE_C=y 1505 | # end of Certificates 1506 | 1507 | CONFIG_MBEDTLS_ECP_C=y 1508 | # CONFIG_MBEDTLS_DHM_C is not set 1509 | CONFIG_MBEDTLS_ECDH_C=y 1510 | CONFIG_MBEDTLS_ECDSA_C=y 1511 | # CONFIG_MBEDTLS_ECJPAKE_C is not set 1512 | CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y 1513 | CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y 1514 | CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y 1515 | CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y 1516 | CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y 1517 | CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y 1518 | CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y 1519 | CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y 1520 | CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y 1521 | CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y 1522 | CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y 1523 | CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y 1524 | CONFIG_MBEDTLS_ECP_NIST_OPTIM=y 1525 | CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM=y 1526 | # CONFIG_MBEDTLS_POLY1305_C is not set 1527 | # CONFIG_MBEDTLS_CHACHA20_C is not set 1528 | # CONFIG_MBEDTLS_HKDF_C is not set 1529 | # CONFIG_MBEDTLS_THREADING_C is not set 1530 | CONFIG_MBEDTLS_ERROR_STRINGS=y 1531 | # end of mbedTLS 1532 | 1533 | # 1534 | # ESP-MQTT Configurations 1535 | # 1536 | CONFIG_MQTT_PROTOCOL_311=y 1537 | # CONFIG_MQTT_PROTOCOL_5 is not set 1538 | CONFIG_MQTT_TRANSPORT_SSL=y 1539 | CONFIG_MQTT_TRANSPORT_WEBSOCKET=y 1540 | CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y 1541 | # CONFIG_MQTT_MSG_ID_INCREMENTAL is not set 1542 | # CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set 1543 | # CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set 1544 | # CONFIG_MQTT_USE_CUSTOM_CONFIG is not set 1545 | # CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set 1546 | # CONFIG_MQTT_CUSTOM_OUTBOX is not set 1547 | # end of ESP-MQTT Configurations 1548 | 1549 | # 1550 | # Newlib 1551 | # 1552 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y 1553 | # CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set 1554 | # CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set 1555 | # CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set 1556 | # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set 1557 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y 1558 | # CONFIG_NEWLIB_NANO_FORMAT is not set 1559 | CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y 1560 | # CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set 1561 | # CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set 1562 | # CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set 1563 | # end of Newlib 1564 | 1565 | # 1566 | # NVS 1567 | # 1568 | # CONFIG_NVS_ENCRYPTION is not set 1569 | # CONFIG_NVS_ASSERT_ERROR_CHECK is not set 1570 | # CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set 1571 | # end of NVS 1572 | 1573 | # 1574 | # OpenThread 1575 | # 1576 | # CONFIG_OPENTHREAD_ENABLED is not set 1577 | 1578 | # 1579 | # Thread Operational Dataset 1580 | # 1581 | CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" 1582 | CONFIG_OPENTHREAD_MESH_LOCAL_PREFIX="fd00:db8:a0:0::/64" 1583 | CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 1584 | CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 1585 | CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" 1586 | CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" 1587 | CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" 1588 | # end of Thread Operational Dataset 1589 | 1590 | CONFIG_OPENTHREAD_XTAL_ACCURACY=130 1591 | # CONFIG_OPENTHREAD_SPINEL_ONLY is not set 1592 | CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE=y 1593 | 1594 | # 1595 | # Thread Address Query Config 1596 | # 1597 | # end of Thread Address Query Config 1598 | # end of OpenThread 1599 | 1600 | # 1601 | # Protocomm 1602 | # 1603 | CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y 1604 | CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y 1605 | CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y 1606 | # end of Protocomm 1607 | 1608 | # 1609 | # PThreads 1610 | # 1611 | CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 1612 | CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 1613 | CONFIG_PTHREAD_STACK_MIN=768 1614 | CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 1615 | CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" 1616 | # end of PThreads 1617 | 1618 | # 1619 | # MMU Config 1620 | # 1621 | CONFIG_MMU_PAGE_SIZE_64KB=y 1622 | CONFIG_MMU_PAGE_MODE="64KB" 1623 | CONFIG_MMU_PAGE_SIZE=0x10000 1624 | # end of MMU Config 1625 | 1626 | # 1627 | # Main Flash configuration 1628 | # 1629 | 1630 | # 1631 | # SPI Flash behavior when brownout 1632 | # 1633 | CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y 1634 | CONFIG_SPI_FLASH_BROWNOUT_RESET=y 1635 | # end of SPI Flash behavior when brownout 1636 | 1637 | # 1638 | # Optional and Experimental Features (READ DOCS FIRST) 1639 | # 1640 | 1641 | # 1642 | # Features here require specific hardware (READ DOCS FIRST!) 1643 | # 1644 | CONFIG_SPI_FLASH_SUSPEND_QVL_SUPPORTED=y 1645 | # CONFIG_SPI_FLASH_AUTO_SUSPEND is not set 1646 | CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50 1647 | # end of Optional and Experimental Features (READ DOCS FIRST) 1648 | # end of Main Flash configuration 1649 | 1650 | # 1651 | # SPI Flash driver 1652 | # 1653 | # CONFIG_SPI_FLASH_VERIFY_WRITE is not set 1654 | # CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set 1655 | CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y 1656 | # CONFIG_SPI_FLASH_ROM_IMPL is not set 1657 | CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y 1658 | # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set 1659 | # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set 1660 | # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set 1661 | CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y 1662 | CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 1663 | CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 1664 | CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 1665 | # CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set 1666 | # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set 1667 | # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set 1668 | 1669 | # 1670 | # Auto-detect flash chips 1671 | # 1672 | CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y 1673 | CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y 1674 | CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y 1675 | CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y 1676 | CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y 1677 | CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y 1678 | CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y 1679 | CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y 1680 | CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y 1681 | CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y 1682 | CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y 1683 | CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y 1684 | CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y 1685 | # end of Auto-detect flash chips 1686 | 1687 | CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y 1688 | # end of SPI Flash driver 1689 | 1690 | # 1691 | # SPIFFS Configuration 1692 | # 1693 | CONFIG_SPIFFS_MAX_PARTITIONS=3 1694 | 1695 | # 1696 | # SPIFFS Cache Configuration 1697 | # 1698 | CONFIG_SPIFFS_CACHE=y 1699 | CONFIG_SPIFFS_CACHE_WR=y 1700 | # CONFIG_SPIFFS_CACHE_STATS is not set 1701 | # end of SPIFFS Cache Configuration 1702 | 1703 | CONFIG_SPIFFS_PAGE_CHECK=y 1704 | CONFIG_SPIFFS_GC_MAX_RUNS=10 1705 | # CONFIG_SPIFFS_GC_STATS is not set 1706 | CONFIG_SPIFFS_PAGE_SIZE=256 1707 | CONFIG_SPIFFS_OBJ_NAME_LEN=32 1708 | # CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set 1709 | CONFIG_SPIFFS_USE_MAGIC=y 1710 | CONFIG_SPIFFS_USE_MAGIC_LENGTH=y 1711 | CONFIG_SPIFFS_META_LENGTH=4 1712 | CONFIG_SPIFFS_USE_MTIME=y 1713 | 1714 | # 1715 | # Debug Configuration 1716 | # 1717 | # CONFIG_SPIFFS_DBG is not set 1718 | # CONFIG_SPIFFS_API_DBG is not set 1719 | # CONFIG_SPIFFS_GC_DBG is not set 1720 | # CONFIG_SPIFFS_CACHE_DBG is not set 1721 | # CONFIG_SPIFFS_CHECK_DBG is not set 1722 | # CONFIG_SPIFFS_TEST_VISUALISATION is not set 1723 | # end of Debug Configuration 1724 | # end of SPIFFS Configuration 1725 | 1726 | # 1727 | # TCP Transport 1728 | # 1729 | 1730 | # 1731 | # Websocket 1732 | # 1733 | CONFIG_WS_TRANSPORT=y 1734 | CONFIG_WS_BUFFER_SIZE=1024 1735 | # CONFIG_WS_DYNAMIC_BUFFER is not set 1736 | # end of Websocket 1737 | # end of TCP Transport 1738 | 1739 | # 1740 | # Unity unit testing library 1741 | # 1742 | CONFIG_UNITY_ENABLE_FLOAT=y 1743 | CONFIG_UNITY_ENABLE_DOUBLE=y 1744 | # CONFIG_UNITY_ENABLE_64BIT is not set 1745 | # CONFIG_UNITY_ENABLE_COLOR is not set 1746 | CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y 1747 | # CONFIG_UNITY_ENABLE_FIXTURE is not set 1748 | # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set 1749 | # end of Unity unit testing library 1750 | 1751 | # 1752 | # Virtual file system 1753 | # 1754 | CONFIG_VFS_SUPPORT_IO=y 1755 | CONFIG_VFS_SUPPORT_DIR=y 1756 | CONFIG_VFS_SUPPORT_SELECT=y 1757 | CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y 1758 | # CONFIG_VFS_SELECT_IN_RAM is not set 1759 | CONFIG_VFS_SUPPORT_TERMIOS=y 1760 | CONFIG_VFS_MAX_COUNT=8 1761 | 1762 | # 1763 | # Host File System I/O (Semihosting) 1764 | # 1765 | CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 1766 | # end of Host File System I/O (Semihosting) 1767 | # end of Virtual file system 1768 | 1769 | # 1770 | # Wear Levelling 1771 | # 1772 | # CONFIG_WL_SECTOR_SIZE_512 is not set 1773 | CONFIG_WL_SECTOR_SIZE_4096=y 1774 | CONFIG_WL_SECTOR_SIZE=4096 1775 | # end of Wear Levelling 1776 | 1777 | # 1778 | # Wi-Fi Provisioning Manager 1779 | # 1780 | CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 1781 | CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 1782 | # CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION is not set 1783 | CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y 1784 | # CONFIG_WIFI_PROV_STA_FAST_SCAN is not set 1785 | # end of Wi-Fi Provisioning Manager 1786 | # end of Component config 1787 | 1788 | CONFIG_IDF_EXPERIMENTAL_FEATURES=y 1789 | 1790 | # Deprecated options for backward compatibility 1791 | # CONFIG_APP_BUILD_TYPE_ELF_RAM is not set 1792 | # CONFIG_NO_BLOBS is not set 1793 | # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set 1794 | # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set 1795 | # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set 1796 | CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y 1797 | # CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set 1798 | # CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set 1799 | CONFIG_LOG_BOOTLOADER_LEVEL=3 1800 | # CONFIG_APP_ROLLBACK_ENABLE is not set 1801 | # CONFIG_FLASH_ENCRYPTION_ENABLED is not set 1802 | # CONFIG_FLASHMODE_QIO is not set 1803 | # CONFIG_FLASHMODE_QOUT is not set 1804 | CONFIG_FLASHMODE_DIO=y 1805 | # CONFIG_FLASHMODE_DOUT is not set 1806 | CONFIG_MONITOR_BAUD=115200 1807 | CONFIG_OPTIMIZATION_LEVEL_DEBUG=y 1808 | CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y 1809 | CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y 1810 | # CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set 1811 | # CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set 1812 | CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y 1813 | # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set 1814 | # CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set 1815 | CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 1816 | # CONFIG_CXX_EXCEPTIONS is not set 1817 | CONFIG_STACK_CHECK_NONE=y 1818 | # CONFIG_STACK_CHECK_NORM is not set 1819 | # CONFIG_STACK_CHECK_STRONG is not set 1820 | # CONFIG_STACK_CHECK_ALL is not set 1821 | # CONFIG_WARN_WRITE_STRINGS is not set 1822 | # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set 1823 | CONFIG_ESP32_APPTRACE_DEST_NONE=y 1824 | CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y 1825 | # CONFIG_EXTERNAL_COEX_ENABLE is not set 1826 | # CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set 1827 | # CONFIG_EVENT_LOOP_PROFILING is not set 1828 | CONFIG_POST_EVENTS_FROM_ISR=y 1829 | CONFIG_POST_EVENTS_FROM_IRAM_ISR=y 1830 | CONFIG_GDBSTUB_SUPPORT_TASKS=y 1831 | CONFIG_GDBSTUB_MAX_TASKS=32 1832 | # CONFIG_OTA_ALLOW_HTTP is not set 1833 | # CONFIG_ESP_SYSTEM_PD_FLASH is not set 1834 | CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y 1835 | CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y 1836 | # CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set 1837 | # CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set 1838 | # CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set 1839 | CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024 1840 | CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y 1841 | # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set 1842 | CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 1843 | CONFIG_ESP32_PHY_MAX_TX_POWER=20 1844 | # CONFIG_MAC_BB_PD is not set 1845 | # CONFIG_ESP32_PHY_MAC_BB_PD is not set 1846 | # CONFIG_REDUCE_PHY_TX_POWER is not set 1847 | # CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set 1848 | CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y 1849 | # CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set 1850 | CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y 1851 | CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160 1852 | CONFIG_ESP32C3_MEMPROT_FEATURE=y 1853 | CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK=y 1854 | CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 1855 | CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 1856 | CONFIG_MAIN_TASK_STACK_SIZE=3584 1857 | # CONFIG_CONSOLE_UART_DEFAULT is not set 1858 | # CONFIG_CONSOLE_UART_CUSTOM is not set 1859 | # CONFIG_CONSOLE_UART_NONE is not set 1860 | # CONFIG_ESP_CONSOLE_UART_NONE is not set 1861 | CONFIG_CONSOLE_UART_NUM=-1 1862 | CONFIG_INT_WDT=y 1863 | CONFIG_INT_WDT_TIMEOUT_MS=300 1864 | CONFIG_TASK_WDT=y 1865 | CONFIG_ESP_TASK_WDT=y 1866 | # CONFIG_TASK_WDT_PANIC is not set 1867 | CONFIG_TASK_WDT_TIMEOUT_S=5 1868 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 1869 | # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set 1870 | CONFIG_ESP32C3_DEBUG_OCDAWARE=y 1871 | CONFIG_BROWNOUT_DET=y 1872 | CONFIG_ESP32C3_BROWNOUT_DET=y 1873 | CONFIG_ESP32C3_BROWNOUT_DET=y 1874 | CONFIG_BROWNOUT_DET_LVL_SEL_7=y 1875 | CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y 1876 | # CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set 1877 | # CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set 1878 | # CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set 1879 | # CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set 1880 | # CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set 1881 | # CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set 1882 | # CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set 1883 | # CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set 1884 | # CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set 1885 | # CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set 1886 | CONFIG_BROWNOUT_DET_LVL=7 1887 | CONFIG_ESP32C3_BROWNOUT_DET_LVL=7 1888 | CONFIG_IPC_TASK_STACK_SIZE=1024 1889 | CONFIG_TIMER_TASK_STACK_SIZE=3584 1890 | CONFIG_ESP32_WIFI_ENABLED=y 1891 | CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 1892 | CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 1893 | # CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set 1894 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y 1895 | CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 1896 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 1897 | # CONFIG_ESP32_WIFI_CSI_ENABLED is not set 1898 | CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y 1899 | CONFIG_ESP32_WIFI_TX_BA_WIN=6 1900 | CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y 1901 | CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y 1902 | CONFIG_ESP32_WIFI_RX_BA_WIN=6 1903 | CONFIG_ESP32_WIFI_RX_BA_WIN=6 1904 | CONFIG_ESP32_WIFI_NVS_ENABLED=y 1905 | CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 1906 | CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 1907 | CONFIG_ESP32_WIFI_IRAM_OPT=y 1908 | CONFIG_ESP32_WIFI_RX_IRAM_OPT=y 1909 | CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y 1910 | CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y 1911 | CONFIG_WPA_MBEDTLS_CRYPTO=y 1912 | CONFIG_WPA_MBEDTLS_TLS_CLIENT=y 1913 | # CONFIG_WPA_WAPI_PSK is not set 1914 | # CONFIG_WPA_SUITE_B_192 is not set 1915 | # CONFIG_WPA_11KV_SUPPORT is not set 1916 | # CONFIG_WPA_MBO_SUPPORT is not set 1917 | # CONFIG_WPA_DPP_SUPPORT is not set 1918 | # CONFIG_WPA_11R_SUPPORT is not set 1919 | # CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set 1920 | # CONFIG_WPA_WPS_STRICT is not set 1921 | # CONFIG_WPA_DEBUG_PRINT is not set 1922 | # CONFIG_WPA_TESTING_OPTIONS is not set 1923 | # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set 1924 | # CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set 1925 | CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y 1926 | CONFIG_TIMER_TASK_PRIORITY=1 1927 | CONFIG_TIMER_TASK_STACK_DEPTH=2048 1928 | CONFIG_TIMER_QUEUE_LENGTH=10 1929 | # CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set 1930 | # CONFIG_HAL_ASSERTION_SILIENT is not set 1931 | # CONFIG_L2_TO_L3_COPY is not set 1932 | CONFIG_ESP_GRATUITOUS_ARP=y 1933 | CONFIG_GARP_TMR_INTERVAL=60 1934 | CONFIG_TCPIP_RECVMBOX_SIZE=32 1935 | CONFIG_TCP_MAXRTX=12 1936 | CONFIG_TCP_SYNMAXRTX=12 1937 | CONFIG_TCP_MSS=1440 1938 | CONFIG_TCP_MSL=60000 1939 | CONFIG_TCP_SND_BUF_DEFAULT=5760 1940 | CONFIG_TCP_WND_DEFAULT=5760 1941 | CONFIG_TCP_RECVMBOX_SIZE=6 1942 | CONFIG_TCP_QUEUE_OOSEQ=y 1943 | CONFIG_TCP_OVERSIZE_MSS=y 1944 | # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set 1945 | # CONFIG_TCP_OVERSIZE_DISABLE is not set 1946 | CONFIG_UDP_RECVMBOX_SIZE=6 1947 | CONFIG_TCPIP_TASK_STACK_SIZE=3072 1948 | CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y 1949 | # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set 1950 | CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF 1951 | # CONFIG_PPP_SUPPORT is not set 1952 | CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y 1953 | # CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set 1954 | # CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set 1955 | # CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set 1956 | CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 1957 | CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 1958 | CONFIG_ESP32_PTHREAD_STACK_MIN=768 1959 | CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 1960 | CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" 1961 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y 1962 | # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set 1963 | # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set 1964 | CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y 1965 | CONFIG_SUPPORT_TERMIOS=y 1966 | CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 1967 | # End of deprecated options 1968 | --------------------------------------------------------------------------------