├── .gitignore ├── .library_mapping.xml ├── .project ├── .settings ├── com.sigasi.hdt.vhdl.version.prefs └── org.eclipse.core.resources.prefs ├── LICENSE ├── README.md ├── doc └── tcc-v6-gabriel-final.pdf ├── fpga ├── lattice │ └── ann_vhdl │ │ ├── ann_vhdl_Implmnt │ │ ├── .recordref │ │ ├── AutoConstraint_network.sdc │ │ ├── ann_vhdl.edf │ │ ├── ann_vhdl.fse │ │ ├── ann_vhdl.htm │ │ ├── ann_vhdl.map │ │ ├── ann_vhdl.sap │ │ ├── ann_vhdl.scf │ │ ├── ann_vhdl.srd │ │ ├── ann_vhdl.srm │ │ ├── ann_vhdl.srr │ │ ├── ann_vhdl.srs │ │ ├── ann_vhdl_cck.rpt │ │ ├── ann_vhdl_multi_srs_gen.htm │ │ ├── ann_vhdl_scck.rpt │ │ ├── ann_vhdl_synplify.fdc │ │ ├── backup │ │ │ └── ann_vhdl.srr │ │ ├── dm │ │ │ └── layer0.xdm │ │ ├── rpt_network.areasrr │ │ ├── rpt_network_areasrr.htm │ │ ├── run_options.txt │ │ ├── sbt │ │ │ └── Log │ │ │ │ └── iceCube0.log │ │ ├── scratchproject.prs │ │ ├── synlog │ │ │ ├── ann_vhdl_compiler.srr │ │ │ ├── ann_vhdl_compiler.srr.rptmap │ │ │ ├── ann_vhdl_fpga_mapper.srr │ │ │ ├── ann_vhdl_fpga_mapper.szr │ │ │ ├── ann_vhdl_fpga_mapper.xck │ │ │ ├── ann_vhdl_multi_srs_gen.srr │ │ │ ├── ann_vhdl_premap.srr │ │ │ ├── ann_vhdl_premap.szr │ │ │ ├── layer0.tlg.rptmap │ │ │ ├── report │ │ │ │ ├── ann_vhdl_compiler_errors.txt │ │ │ │ ├── ann_vhdl_compiler_notes.txt │ │ │ │ ├── ann_vhdl_compiler_runstatus.xml │ │ │ │ ├── ann_vhdl_compiler_warnings.txt │ │ │ │ ├── ann_vhdl_fpga_mapper_area_report.xml │ │ │ │ ├── ann_vhdl_fpga_mapper_combined_clk.rpt │ │ │ │ ├── ann_vhdl_fpga_mapper_errors.txt │ │ │ │ ├── ann_vhdl_fpga_mapper_notes.txt │ │ │ │ ├── ann_vhdl_fpga_mapper_opt_report.xml │ │ │ │ ├── ann_vhdl_fpga_mapper_resourceusage.rpt │ │ │ │ ├── ann_vhdl_fpga_mapper_runstatus.xml │ │ │ │ ├── ann_vhdl_fpga_mapper_timing_report.xml │ │ │ │ ├── ann_vhdl_fpga_mapper_warnings.txt │ │ │ │ ├── ann_vhdl_premap_errors.txt │ │ │ │ ├── ann_vhdl_premap_notes.txt │ │ │ │ ├── ann_vhdl_premap_runstatus.xml │ │ │ │ └── ann_vhdl_premap_warnings.txt │ │ │ └── syntax_constraint_check.rpt.rptmap │ │ ├── syntmp │ │ │ ├── ann_vhdl.plg │ │ │ ├── ann_vhdl_multi_srs_gen_srr.htm │ │ │ ├── ann_vhdl_multi_srs_gen_toc.htm │ │ │ ├── ann_vhdl_srr.htm │ │ │ ├── ann_vhdl_toc.htm │ │ │ ├── closed.png │ │ │ ├── cmdrec_compiler.log │ │ │ ├── cmdrec_fpga_mapper.log │ │ │ ├── cmdrec_multi_srs_gen.log │ │ │ ├── cmdrec_premap.log │ │ │ ├── open.png │ │ │ ├── run_option.xml │ │ │ └── synenc │ │ │ │ └── synenc.lst │ │ └── synwork │ │ │ ├── .cckTransfer │ │ │ ├── .complist │ │ │ ├── ann_vhdl_comp.fdep │ │ │ ├── ann_vhdl_comp.srs │ │ │ ├── ann_vhdl_m.srm │ │ │ ├── ann_vhdl_m_srm │ │ │ ├── 1.srm │ │ │ └── fileinfo.srm │ │ │ ├── ann_vhdl_mult.srs │ │ │ ├── ann_vhdl_mult_srs │ │ │ ├── 1.srs │ │ │ ├── fileinfo.srs │ │ │ └── skeleton.srs │ │ │ ├── ann_vhdl_prem.fse │ │ │ ├── ann_vhdl_prem.srd │ │ │ ├── layer0.fdep │ │ │ ├── layer0.fdeporig │ │ │ ├── layer0.srs │ │ │ ├── layer0.tlg │ │ │ ├── vhdl.tbl │ │ │ └── vhdlcfg.tbl │ │ ├── ann_vhdl_sbt.project │ │ ├── ann_vhdl_syn.prd │ │ ├── stdout.log │ │ └── synlog.tcl └── xilinx │ └── ann-vhdl │ ├── act_func_isim_beh.exe │ ├── act_func_tb_isim_beh.exe │ ├── act_func_tb_isim_beh.wdb │ ├── ann-vhdl.xise │ ├── fuse.log │ ├── fuse.xmsgs │ ├── fuseRelaunch.cmd │ ├── ipcore_dir │ ├── coregen.cgc │ ├── coregen.cgp │ ├── coregen.log │ ├── dist_mem_gen_v7_2.asy │ ├── dist_mem_gen_v7_2.vhd │ ├── dist_mem_gen_v7_2.vho │ ├── dist_mem_gen_v7_2.xco │ ├── dist_mem_gen_v7_2.xise │ ├── dist_mem_gen_v7_2 │ │ ├── dist_mem_gen_v7_2_readme.txt │ │ └── doc │ │ │ └── pg063-dist-mem-gen.pdf │ ├── dist_mem_gen_v7_2_flist.txt │ └── dist_mem_gen_v7_2_xmdf.tcl │ ├── isim.cmd │ ├── isim.log │ ├── isim │ ├── act_func_tb_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── act_func_tb_isim_beh.exe │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ └── work │ │ │ ├── a_2599789339_3671711236.c │ │ │ ├── a_2599789339_3671711236.didat │ │ │ ├── a_2599789339_3671711236.lin64.o │ │ │ ├── a_4019868472_2587733704.c │ │ │ ├── a_4019868472_2587733704.didat │ │ │ ├── a_4019868472_2587733704.lin64.o │ │ │ ├── act_func_tb_isim_beh.exe_main.c │ │ │ ├── act_func_tb_isim_beh.exe_main.lin64.o │ │ │ ├── p_1475539293.c │ │ │ ├── p_1475539293.didat │ │ │ └── p_1475539293.lin64.o │ ├── lockfile │ ├── pn_info │ ├── precompiled.exe.sim │ │ ├── ieee │ │ │ ├── p_1242562249.c │ │ │ ├── p_1242562249.didat │ │ │ ├── p_1242562249.lin64.o │ │ │ ├── p_2592010699.c │ │ │ ├── p_2592010699.didat │ │ │ ├── p_2592010699.lin64.o │ │ │ ├── p_3564397177.c │ │ │ ├── p_3564397177.didat │ │ │ ├── p_3564397177.lin64.o │ │ │ ├── p_3972351953.c │ │ │ ├── p_3972351953.didat │ │ │ └── p_3972351953.lin64.o │ │ ├── ieee_proposed │ │ │ ├── p_0892474878.c │ │ │ ├── p_0892474878.didat │ │ │ ├── p_0892474878.lin64.o │ │ │ ├── p_2011092313.c │ │ │ ├── p_2011092313.didat │ │ │ └── p_2011092313.lin64.o │ │ └── std │ │ │ ├── textio.c │ │ │ ├── textio.didat │ │ │ └── textio.lin64.o │ ├── temp │ │ ├── act_func.vdb │ │ ├── act_func_tb.vdb │ │ └── types.vdb │ └── work │ │ ├── act_func.vdb │ │ ├── act_func_tb.vdb │ │ └── types.vdb │ ├── network_test_2_4_1.wcfg │ ├── network_test_tb_isim_beh.exe │ ├── network_test_tb_isim_beh1.wdb │ ├── network_test_tb_isim_beh2.wdb │ ├── neuron_tb_isim_beh.exe │ ├── neuron_tb_isim_beh.wdb │ └── xilinxsim.ini ├── ide ├── .library_mapping.xml ├── .project ├── .settings │ ├── com.sigasi.hdt.vhdl.version.prefs │ └── org.eclipse.core.resources.prefs ├── act_func.vhd ├── network.vhd ├── network_test.vhd ├── network_test_tb.vhd ├── neuron.vhd └── types.vhd ├── old ├── compile.tcl └── interpolador_funcao_tanh.vhd └── src ├── act_func.vhd ├── act_func_tb.vhd ├── network.vhd ├── network_tb.vhd ├── network_test.vhd ├── network_test_tb.vhd ├── neuron.vhd ├── neuron_tb.vhd └── types.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | # Created by https://www.gitignore.io/api/modelsim,xilinxise 3 | 4 | ### ModelSim ### 5 | # ignore ModelSim generated files and directories (temp files and so on) 6 | [_@]* 7 | 8 | # ignore compilation output of ModelSim 9 | *.mti 10 | *.dat 11 | *.dbs 12 | *.psm 13 | *.bak 14 | *.cmp 15 | *.jpg 16 | *.html 17 | *.bsf 18 | 19 | # ignore simulation output of ModelSim 20 | wlf* 21 | *.wlf 22 | *.vstf 23 | *.ucdb 24 | cov*/ 25 | transcript* 26 | sc_dpiheader.h 27 | vsim.dbg 28 | 29 | ### XilinxISE ### 30 | # intermediate build files 31 | *.bgn 32 | *.bit 33 | *.bld 34 | *.cmd_log 35 | *.drc 36 | *.ll 37 | *.lso 38 | *.msd 39 | *.msk 40 | *.ncd 41 | *.ngc 42 | *.ngd 43 | *.ngr 44 | *.pad 45 | *.par 46 | *.pcf 47 | *.prj 48 | *.ptwx 49 | *.rbb 50 | *.rbd 51 | *.stx 52 | *.syr 53 | *.twr 54 | *.twx 55 | *.unroutes 56 | *.ut 57 | *.xpi 58 | *.xst 59 | *_bitgen.xwbt 60 | *_envsettings.html 61 | *_map.map 62 | *_map.mrp 63 | *_map.ngm 64 | *_map.xrpt 65 | *_ngdbuild.xrpt 66 | *_pad.csv 67 | *_pad.txt 68 | *_par.xrpt 69 | *_summary.html 70 | *_summary.xml 71 | *_usage.xml 72 | *_xst.xrpt 73 | 74 | # iMPACT generated files 75 | _impactbatch.log 76 | impact.xsl 77 | impact_impact.xwbt 78 | ise_impact.cmd 79 | webtalk_impact.xml 80 | 81 | # Core Generator generated files 82 | xaw2verilog.log 83 | 84 | # project-wide generated files 85 | *.gise 86 | par_usage_statistics.html 87 | usage_statistics_webtalk.html 88 | webtalk.log 89 | webtalk_pn.xml 90 | 91 | # generated folders 92 | iseconfig/ 93 | xlnx_auto_0_xdb/ 94 | xst/ 95 | _ngo/ 96 | _xmsgs/ 97 | 98 | # End of https://www.gitignore.io/api/modelsim,xilinxise 99 | -------------------------------------------------------------------------------- /.library_mapping.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | ann-vhdl 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.xtext.ui.shared.xtextBuilder 10 | 11 | 12 | 13 | 14 | 15 | com.sigasi.hdt.vhdl.ui.vhdlNature 16 | org.eclipse.xtext.ui.shared.xtextNature 17 | 18 | 19 | 20 | Common Libraries 21 | 2 22 | virtual:/virtual 23 | 24 | 25 | Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt 26 | 1 27 | sigasiresource:/vhdl/readme2.txt 28 | 29 | 30 | Common Libraries/IEEE 31 | 2 32 | sigasiresource:/vhdl/2008/IEEE 33 | 34 | 35 | Common Libraries/STD 36 | 2 37 | sigasiresource:/vhdl/2008/STD 38 | 39 | 40 | Common Libraries/ieee_proposed 41 | 2 42 | /home/gabriel/.Xilinx/14.7/ISE_DS/ISE/vhdl/src/ieee_proposed 43 | 44 | 45 | Common Libraries/IEEE/Synopsys 46 | 2 47 | sigasiresource:/vhdl/2008/IEEE%20Synopsys 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /.settings/com.sigasi.hdt.vhdl.version.prefs: -------------------------------------------------------------------------------- 1 | =2008 2 | -------------------------------------------------------------------------------- /.settings/org.eclipse.core.resources.prefs: -------------------------------------------------------------------------------- 1 | eclipse.preferences.version=1 2 | encoding//Common\ Libraries/IEEE=utf-8 3 | encoding//Common\ Libraries/IEEE/Synopsys=utf-8 4 | encoding//Common\ Libraries/STD=utf-8 5 | encoding/Common\ Libraries=utf-8 6 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Creative Commons Legal Code 2 | 3 | CC0 1.0 Universal 4 | 5 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 6 | LEGAL SERVICES. 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Affirmer understands and acknowledges that Creative Commons is not a 120 | party to this document and has no duty or obligation with respect to 121 | this CC0 or use of the Work. 122 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | A HARDWARE IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS FOR INFERENCE 2 | ===================================================================== 3 | 4 | The growing investment in the use of artificial neural networks for end-user services, which require low latency and high responsiveness, make it desirable to have dedicated hardware accelerators for inference. FPGA (*Field-Programmable Gate Arrays*) programmable devices have the required ideal flexibility for the deployment of artificial neural network accelerators, while being able to support different architectural network models and still keeping performance. A modular artificial neural network design is developed in hardware description language in order to allow inference from reconfigurable devices with desirable performance. The modular design enables it to be easily scaled to support new neural network architectures and different activation functions. The project’s validation is verified by a hardware implementation of a simple and widely known neural network (*exclusive*-OR (XOR) function). 5 | 6 | 7 | Implementation 8 | -------------- 9 | The VHDL code was developed in a modular fashion, allowing different activation functions and mixing of different neuron approaches (*e.g.* behavioral, structural, area or speed optimizations *etc*). The same modularity is observed in artifical neural networks, so that developing on this same fashion becomes intuitive. Developing and adding different activation functions or neural architectures thus becomes trivial. 10 | 11 | The code uses the following hierarchical organization, from lowest to highest level: 12 | 13 | ``` 14 | types.vhd 15 | ``` 16 | Integer and fractional bit size configuration for the components (defaults to Q16.16). Some other functions for easier conversion and value setting in VHDL. Mainly responsible for setting the desired network precision (compromise between performance and precision); 17 | 18 | ``` 19 | act_func.vhd 20 | ``` 21 | Activation functions implementation. Other activation functions or reimplementation of existing activation function must be implemented in this file through an `architecture`; 22 | 23 | ``` 24 | neuron.vhd 25 | ``` 26 | Artificial neuron implementation. New neuron descriptions must be implemented in this file through an `architecture`. Neurons use an activation function described in `act_func.vhd`. Thus, it is possible to mix different activation functions on the same neural network, as needed; 27 | 28 | ``` 29 | network.vhd 30 | ``` 31 | Implementation of the network and its interconnections. This is where the neurons are instantiated and positioned on the network, as needed in the architecture. Different architectures can be implemented. The inputs of the network are directly connected to the input neurons. The network is controlled through the neuron connections of the hidden layer. 32 | 33 | 34 | Remarks 35 | ------- 36 | Further work is needed to address a few issues: 37 | * Routing becomes non-trivial for wider networks and can be difficult; 38 | * More complex activation functions need to be implemented; 39 | * Better documentation is needed; 40 | * An automated way of converting high-level code to its VHDL equivalent should be made (perhaps using ONNX as an intermediate representation); 41 | * More testing is needed. 42 | 43 | 44 | 45 | ``` 46 | gabrieljcs [at] protonmail [dot] com 47 | ``` 48 | -------------------------------------------------------------------------------- /doc/tcc-v6-gabriel-final.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/doc/tcc-v6-gabriel-final.pdf -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/.recordref: -------------------------------------------------------------------------------- 1 | network port input_i_0[15:-16] input_i[31:0] 2 | network port input_i_1[15:-16] input_i[63:32] 3 | network port output_o_0[15:-16] output_o[31:0] 4 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/AutoConstraint_network.sdc: -------------------------------------------------------------------------------- 1 | 2 | #Begin clock constraint 3 | define_clock -name {network|clk} {p:network|clk} -period 7.607 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 3.804 -route 0.000 4 | #End clock constraint 5 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.fse: -------------------------------------------------------------------------------- 1 | 2 | fsm_encoding {15402401} onehot 3 | 4 | fsm_state_encoding {15402401} idle {00001} 5 | 6 | fsm_state_encoding {15402401} reg_inputs {00010} 7 | 8 | fsm_state_encoding {15402401} mult {00100} 9 | 10 | fsm_state_encoding {15402401} sum {01000} 11 | 12 | fsm_state_encoding {15402401} act_func {10000} 13 | 14 | fsm_registers {15402401} {current_state[0]} {current_state[1]} {current_state[2]} {current_state[3]} {current_state[4]} 15 | 16 | fsm_encoding {15402401} onehot 17 | 18 | fsm_state_encoding {15402401} idle {00001} 19 | 20 | fsm_state_encoding {15402401} reg_inputs {00010} 21 | 22 | fsm_state_encoding {15402401} mult {00100} 23 | 24 | fsm_state_encoding {15402401} sum {01000} 25 | 26 | fsm_state_encoding {15402401} act_func {10000} 27 | 28 | fsm_registers {15402401} {current_state[0]} {current_state[1]} {current_state[2]} {current_state[3]} {current_state[4]} 29 | 30 | fsm_encoding {15402401} onehot 31 | 32 | fsm_state_encoding {15402401} idle {00001} 33 | 34 | fsm_state_encoding {15402401} reg_inputs {00010} 35 | 36 | fsm_state_encoding {15402401} mult {00100} 37 | 38 | fsm_state_encoding {15402401} sum {01000} 39 | 40 | fsm_state_encoding {15402401} act_func {10000} 41 | 42 | fsm_registers {15402401} {current_state[0]} {current_state[1]} {current_state[2]} {current_state[3]} {current_state[4]} 43 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.htm: -------------------------------------------------------------------------------- 1 | 2 | 3 | syntmp/ann_vhdl_srr.htm log file 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.map: -------------------------------------------------------------------------------- 1 | %%% protect protected_file 2 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.scf: -------------------------------------------------------------------------------- 1 | # Written by Synplify Pro version maplat, Build 1612R. Synopsys Run ID: sid1513091999 2 | # Top Level Design Parameters 3 | 4 | # Clocks 5 | create_clock -period 7.607 -waveform {0.000 3.804} -name {network|clk} [get_ports {clk}] 6 | 7 | # Virtual Clocks 8 | 9 | # Generated Clocks 10 | 11 | # Paths Between Clocks 12 | 13 | # Multicycle Constraints 14 | 15 | # Point-to-point Delay Constraints 16 | 17 | # False Path Constraints 18 | 19 | # Output Load Constraints 20 | 21 | # Driving Cell Constraints 22 | 23 | # Input Delay Constraints 24 | 25 | # Output Delay Constraints 26 | 27 | # Wire Loads 28 | 29 | # Other Constraints 30 | 31 | # syn_hier Attributes 32 | 33 | # set_case Attributes 34 | 35 | # Clock Delay Constraints 36 | 37 | # syn_mode Attributes 38 | 39 | # Cells 40 | 41 | # Port DRC Rules 42 | 43 | # Input Transition Constraints 44 | 45 | # Unused constraints (intentionally commented out) 46 | 47 | # Non-forward-annotatable constraints (intentionally commented out) 48 | 49 | # Block Path constraints 50 | 51 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srd -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srm -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srs -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_multi_srs_gen.htm: -------------------------------------------------------------------------------- 1 | 2 | 3 | syntmp/ann_vhdl_multi_srs_gen_srr.htm log file 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_scck.rpt: -------------------------------------------------------------------------------- 1 | # Synopsys Constraint Checker(syntax only), version maplat, Build 1612R, built Dec 5 2016 2 | # Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. 3 | 4 | # Written on Tue Dec 12 13:19:58 2017 5 | 6 | 7 | ##### DESIGN INFO ####################################################### 8 | 9 | Top View: "network" 10 | Constraint File(s): (none) 11 | 12 | #Run constraint checker to find more issues with constraints. 13 | ######################################################################### 14 | 15 | 16 | 17 | No issues found in constraint syntax. 18 | 19 | 20 | 21 | Clock Summary 22 | ************* 23 | 24 | Start Requested Requested Clock Clock Clock 25 | Clock Frequency Period Type Group Load 26 | -------------------------------------------------------------------------------------------------------------------------------------- 27 | network|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 15 28 | neuron_0|current_state_derived_clock[1] 1.0 MHz 1000.000 derived (from network|clk) Autoconstr_clkgroup_0 65 29 | neuron_0|current_state_derived_clock[3] 1.0 MHz 1000.000 derived (from network|clk) Autoconstr_clkgroup_0 5346 30 | neuron_1|current_state_derived_clock[1] 1.0 MHz 1000.000 derived (from network|clk) Autoconstr_clkgroup_0 65 31 | neuron_1|current_state_derived_clock[3] 1.0 MHz 1000.000 derived (from network|clk) Autoconstr_clkgroup_0 5346 32 | neuron_2|current_state_derived_clock[1] 1.0 MHz 1000.000 derived (from network|clk) Autoconstr_clkgroup_0 65 33 | neuron_2|current_state_derived_clock[3] 1.0 MHz 1000.000 derived (from network|clk) Autoconstr_clkgroup_0 5346 34 | ====================================================================================================================================== 35 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_synplify.fdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_synplify.fdc -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/backup/ann_vhdl.srr: -------------------------------------------------------------------------------- 1 | #Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec 2 2016 2 | #install: /home/gabriel/.lscc/iCEcube2.2017.08/synpbase 3 | #OS: Linux 4 | #Hostname: cygnus 5 | 6 | # Tue Dec 12 13:09:28 2017 7 | 8 | #Implementation: ann_vhdl_Implmnt 9 | 10 | Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016 11 | @N|Running in 64-bit mode 12 | Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. 13 | 14 | @N:Top-level is not specified. Trying to extract automatically... 15 | Synopsys VHDL Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016 16 | @N|Running in 64-bit mode 17 | Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. 18 | 19 | Running on host :cygnus 20 | @N: CD720 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps 21 | @E: Can't open input file /home/gabriel/ann-vhdl/src/network_fpga.vhd 22 | # Tue Dec 12 13:09:28 2017 23 | 24 | ###########################################################] 25 | @E::VHDL compiler failed 26 | @END 27 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime 28 | # Tue Dec 12 13:09:28 2017 29 | 30 | ###########################################################] 31 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/dm/layer0.xdm: -------------------------------------------------------------------------------- 1 | %%% protect protected_file 2 | @EG 4 | - 5 | ]17p0Osk0CksRsPC#MHF=3"4j 6 | "> 7 | !S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> 8 | S 9 | S"/ 10 | S 11 | S"/ 12 | 13 | SF<1kCsOR"b=/lEFCN/oLCsHDD/3#/OOHOB k.LC34.j(U3j/M#$b#LNCH/DLE/P8j.jUk/MlHCsOE3P8N"R=""cR"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S 14 | S 15 | SF<1kCsOR"b=/lEFCN/oLCsHDD/3#/OOHOB k.LC34.j(U3j/M#$b#LNCH/DLE/P8j.jUs/NH30EP"E8R"N=nD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-" 16 | />S1SS1S"/ 18 | 19 | SF<1kCsOR"b=/lEFCN/oLCsHDD/3#/OOHOB k.LC34.j(U3j/M#$b#LNCH/DLE/P8j.jUH/VG_C8b3 oP"E8R"N=4Rj"DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/ 20 | 21 | SF<1kCsOR"b=/lEFCN/oLCsHDD/3#/OOHOB k.LC34.j(U3j/M#$b#LNCH/DLE/P8j.jUH/VG_C8VNDF0$_0b3C#P"E8R"N=4R."DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/ 22 | 23 | SF<1kCsOR"b=/lEFCN/oLCsHDM/NME-P8#D/sDO/NH00O0C-C/#0N_O0VOkM38PE"=RN""4cR"D=PDE8"DROH=#0""RgRHbD#"0=R"46/S> 24 | SF<1kCsOR"b=/lEFCN/oLCsHDM/NME-P8#D/sDO/NH00O0C-C/#0MsCkFPM3ER8"N4="6D"R=E"P8RD"O#DH0R="4gcR"DRbH=#0"nR4" 25 | />S1S"/ 26 | /S<1sFkO>C# 27 | < 28 | S!R--vkF8DsCRFRF0- 29 | ->SF<)FM0R=F"IsM 3CF0IsM 3_sGF" 30 | /> 31 | < 32 | S!R--vkF8D7CRCMVHHF0HM-R->< 33 | S7RCVMI="F3s N_O0VOkM3M0NED"R=E"P8>D" 34 | 35 | SR 36 | SR 37 | SR"/ 38 | 39 | SR 40 | SR 41 | SR"/ 42 | /S<7>CV 43 | < 44 | S!R--vkF8D7CRCMVHHF0HM-R->< 45 | S7RCVMI="F3s MsCkFLM3CPENHNFsDD"R=E"P8>D" 46 | R/ 47 | "/ 48 | "/ 49 | 50 | SR"/ 51 | SqSS 53 | SS 54 | SS 55 | SS 56 | SS 57 | S 59 | 60 | SC<)V=RM"sIF O3N0k_VM0O3N"MER"H=N_O0VOkM_#HM0 61 | ">SS/S<)>CV 63 | /S<7>CV 64 | < 65 | S!R--vkF8D7CRCMVHHF0HM-R->< 66 | S7RCVMI="F3s MIC0F3s MF_GsD"R=E"P8>D" 67 | R/ 68 | "/ 69 | 70 | SRS 71 | SS 72 | SS 73 | SSqSS 75 | SS 76 | S 77 | SR 78 | SR 80 | 81 | SC<)V=RM"sIF C3MkMsF3ELCNFPHs"NDR"H=M>4" 82 | SSSR/ 83 | SSSS"/ 85 | S 86 | SSS 89 | SqSS/S<)>CV 91 | 92 | SWS 93 | SqSS 94 | SSR 95 | S)S7<7/]ps10kkO0s 98 | C>@ 99 | 100 | 101 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/rpt_network.areasrr: -------------------------------------------------------------------------------- 1 | #### START OF AREA REPORT #####[ 2 | 3 | Part: ICE40HX1KTQ144 (Lattice) 4 | 5 | ----------------------------------------------------------------------- 6 | ######## Utilization report for Top level view: network ######## 7 | ======================================================================= 8 | 9 | SEQUENTIAL ELEMENTS 10 | Name Total elements Utilization Notes 11 | -------------------------------------------------- 12 | FLOPS 21 100 % 13 | ================================================== 14 | Total SEQUENTIAL ELEMENTS in the block network: 21 (0.19 % Utilization) 15 | 16 | 17 | COMBINATIONAL LOGIC 18 | Name Total elements Utilization Notes 19 | --------------------------------------------------- 20 | LUTS 10136 100 % 21 | CARRYS 887 100 % 22 | =================================================== 23 | Total COMBINATIONAL LOGIC in the block network: 11023 (98.79 % Utilization) 24 | 25 | 26 | IO PADS 27 | Name Total elements Utilization Notes 28 | ------------------------------------------------- 29 | PADS 100 100 % 30 | ================================================= 31 | Total IO PADS in the block network: 100 (0.90 % Utilization) 32 | 33 | -------------------------------------------------------------- 34 | ######## Utilization report for cell: neuron_0 ######## 35 | Instance path: network.neuron_0 36 | ============================================================== 37 | 38 | SEQUENTIAL ELEMENTS 39 | Name Total elements Utilization Notes 40 | -------------------------------------------------- 41 | FLOPS 7 33.3 % 42 | ================================================== 43 | Total SEQUENTIAL ELEMENTS in the block network.neuron_0: 7 (0.06 % Utilization) 44 | 45 | 46 | COMBINATIONAL LOGIC 47 | Name Total elements Utilization Notes 48 | --------------------------------------------------- 49 | LUTS 3309 32.6 % 50 | CARRYS 281 31.7 % 51 | =================================================== 52 | Total COMBINATIONAL LOGIC in the block network.neuron_0: 3590 (32.17 % Utilization) 53 | 54 | ------------------------------------------------------------------ 55 | ######## Utilization report for cell: act_func_2_1 ######## 56 | Instance path: neuron_0.act_func_2_1 57 | ================================================================== 58 | 59 | COMBINATIONAL LOGIC 60 | Name Total elements Utilization Notes 61 | --------------------------------------------------- 62 | LUTS 1652 16.3 % 63 | CARRYS 110 12.4 % 64 | =================================================== 65 | Total COMBINATIONAL LOGIC in the block neuron_0.act_func_2_1: 1762 (15.79 % Utilization) 66 | 67 | -------------------------------------------------------------- 68 | ######## Utilization report for cell: neuron_1 ######## 69 | Instance path: network.neuron_1 70 | ============================================================== 71 | 72 | SEQUENTIAL ELEMENTS 73 | Name Total elements Utilization Notes 74 | -------------------------------------------------- 75 | FLOPS 7 33.3 % 76 | ================================================== 77 | Total SEQUENTIAL ELEMENTS in the block network.neuron_1: 7 (0.06 % Utilization) 78 | 79 | 80 | COMBINATIONAL LOGIC 81 | Name Total elements Utilization Notes 82 | --------------------------------------------------- 83 | LUTS 3314 32.7 % 84 | CARRYS 303 34.2 % 85 | =================================================== 86 | Total COMBINATIONAL LOGIC in the block network.neuron_1: 3617 (32.42 % Utilization) 87 | 88 | ------------------------------------------------------------------ 89 | ######## Utilization report for cell: act_func_2_0 ######## 90 | Instance path: neuron_1.act_func_2_0 91 | ================================================================== 92 | 93 | COMBINATIONAL LOGIC 94 | Name Total elements Utilization Notes 95 | --------------------------------------------------- 96 | LUTS 1778 17.5 % 97 | CARRYS 132 14.9 % 98 | =================================================== 99 | Total COMBINATIONAL LOGIC in the block neuron_1.act_func_2_0: 1910 (17.12 % Utilization) 100 | 101 | -------------------------------------------------------------- 102 | ######## Utilization report for cell: neuron_2 ######## 103 | Instance path: network.neuron_2 104 | ============================================================== 105 | 106 | SEQUENTIAL ELEMENTS 107 | Name Total elements Utilization Notes 108 | -------------------------------------------------- 109 | FLOPS 7 33.3 % 110 | ================================================== 111 | Total SEQUENTIAL ELEMENTS in the block network.neuron_2: 7 (0.06 % Utilization) 112 | 113 | 114 | COMBINATIONAL LOGIC 115 | Name Total elements Utilization Notes 116 | --------------------------------------------------- 117 | LUTS 3513 34.7 % 118 | CARRYS 303 34.2 % 119 | =================================================== 120 | Total COMBINATIONAL LOGIC in the block network.neuron_2: 3816 (34.20 % Utilization) 121 | 122 | ---------------------------------------------------------------- 123 | ######## Utilization report for cell: act_func_2 ######## 124 | Instance path: neuron_2.act_func_2 125 | ================================================================ 126 | 127 | COMBINATIONAL LOGIC 128 | Name Total elements Utilization Notes 129 | --------------------------------------------------- 130 | LUTS 1889 18.6 % 131 | CARRYS 132 14.9 % 132 | =================================================== 133 | Total COMBINATIONAL LOGIC in the block neuron_2.act_func_2: 2021 (18.11 % Utilization) 134 | 135 | 136 | ##### END OF AREA REPORT #####] 137 | 138 | -------------------------------------------------------------------------------- /fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/rpt_network_areasrr.htm: -------------------------------------------------------------------------------- 1 | 2 | #### START OF AREA REPORT #####[
  3 | Part:			ICE40HX1KTQ144 (Lattice)
  4 | 
  5 | Click here to go to specific block report:
  6 | 
network

neuron_2

act_func_2

neuron_1

act_func_2_0

neuron_0

act_func_2_1


  7 | -----------------------------------------------------------------------
  8 | ########   Utilization report for  Top level view:   network   ########
  9 | =======================================================================
 10 | 
 11 | SEQUENTIAL ELEMENTS
 12 | Name      Total elements     Utilization     Notes
 13 | --------------------------------------------------
 14 | FLOPS     21                 100 %                
 15 | ==================================================
 16 | Total SEQUENTIAL ELEMENTS in the block network:	21 (0.19 % Utilization)
 17 | 
 18 | 
Top

 19 | 
 20 | COMBINATIONAL LOGIC
 21 | Name       Total elements     Utilization     Notes
 22 | ---------------------------------------------------
 23 | LUTS       10136              100 %                
 24 | CARRYS     887                100 %                
 25 | ===================================================
 26 | Total COMBINATIONAL LOGIC in the block network:	11023 (98.79 % Utilization)
 27 | 
 28 | 
Top

 29 | 
 30 | IO PADS
 31 | Name     Total elements     Utilization     Notes
 32 | -------------------------------------------------
 33 | PADS     100                100 %                
 34 | =================================================
 35 | Total IO PADS in the block network:	100 (0.90 % Utilization)
 36 | 
 37 | 
Top

 38 | 
 39 | --------------------------------------------------------------
 40 | ########   Utilization report for  cell:   neuron_0   ########
 41 | Instance path:   network.neuron_0                             
 42 | ==============================================================
 43 | 
 44 | SEQUENTIAL ELEMENTS
 45 | Name      Total elements     Utilization     Notes
 46 | --------------------------------------------------
 47 | FLOPS     7                  33.3 %               
 48 | ==================================================
 49 | Total SEQUENTIAL ELEMENTS in the block network.neuron_0:	7 (0.06 % Utilization)
 50 | 
 51 | 
Top

 52 | 
 53 | COMBINATIONAL LOGIC
 54 | Name       Total elements     Utilization     Notes
 55 | ---------------------------------------------------
 56 | LUTS       3309               32.6 %               
 57 | CARRYS     281                31.7 %               
 58 | ===================================================
 59 | Total COMBINATIONAL LOGIC in the block network.neuron_0:	3590 (32.17 % Utilization)
 60 | 
 61 | 
Top

 62 | 
 63 | ------------------------------------------------------------------
 64 | ########   Utilization report for  cell:   act_func_2_1   ########
 65 | Instance path:   neuron_0.act_func_2_1                            
 66 | ==================================================================
 67 | 
 68 | COMBINATIONAL LOGIC
 69 | Name       Total elements     Utilization     Notes
 70 | ---------------------------------------------------
 71 | LUTS       1652               16.3 %               
 72 | CARRYS     110                12.4 %               
 73 | ===================================================
 74 | Total COMBINATIONAL LOGIC in the block neuron_0.act_func_2_1:	1762 (15.79 % Utilization)
 75 | 
 76 | 
Top

 77 | 
 78 | --------------------------------------------------------------
 79 | ########   Utilization report for  cell:   neuron_1   ########
 80 | Instance path:   network.neuron_1                             
 81 | ==============================================================
 82 | 
 83 | SEQUENTIAL ELEMENTS
 84 | Name      Total elements     Utilization     Notes
 85 | --------------------------------------------------
 86 | FLOPS     7                  33.3 %               
 87 | ==================================================
 88 | Total SEQUENTIAL ELEMENTS in the block network.neuron_1:	7 (0.06 % Utilization)
 89 | 
 90 | 
Top

 91 | 
 92 | COMBINATIONAL LOGIC
 93 | Name       Total elements     Utilization     Notes
 94 | ---------------------------------------------------
 95 | LUTS       3314               32.7 %               
 96 | CARRYS     303                34.2 %               
 97 | ===================================================
 98 | Total COMBINATIONAL LOGIC in the block network.neuron_1:	3617 (32.42 % Utilization)
 99 | 
100 | 
Top

101 | 
102 | ------------------------------------------------------------------
103 | ########   Utilization report for  cell:   act_func_2_0   ########
104 | Instance path:   neuron_1.act_func_2_0                            
105 | ==================================================================
106 | 
107 | COMBINATIONAL LOGIC
108 | Name       Total elements     Utilization     Notes
109 | ---------------------------------------------------
110 | LUTS       1778               17.5 %               
111 | CARRYS     132                14.9 %               
112 | ===================================================
113 | Total COMBINATIONAL LOGIC in the block neuron_1.act_func_2_0:	1910 (17.12 % Utilization)
114 | 
115 | 
Top

116 | 
117 | --------------------------------------------------------------
118 | ########   Utilization report for  cell:   neuron_2   ########
119 | Instance path:   network.neuron_2                             
120 | ==============================================================
121 | 
122 | SEQUENTIAL ELEMENTS
123 | Name      Total elements     Utilization     Notes
124 | --------------------------------------------------
125 | FLOPS     7                  33.3 %               
126 | ==================================================
127 | Total SEQUENTIAL ELEMENTS in the block network.neuron_2:	7 (0.06 % Utilization)
128 | 
129 | 
Top

130 | 
131 | COMBINATIONAL LOGIC
132 | Name       Total elements     Utilization     Notes
133 | ---------------------------------------------------
134 | LUTS       3513               34.7 %               
135 | CARRYS     303                34.2 %               
136 | ===================================================
137 | Total COMBINATIONAL LOGIC in the block network.neuron_2:	3816 (34.20 % Utilization)
138 | 
139 | 
Top

140 | 
141 | ----------------------------------------------------------------
142 | ########   Utilization report for  cell:   act_func_2   ########
143 | Instance path:   neuron_2.act_func_2                            
144 | ================================================================
145 | 
146 | COMBINATIONAL LOGIC
147 | Name       Total elements     Utilization     Notes
148 | ---------------------------------------------------
149 | LUTS       1889               18.6 %               
150 | CARRYS     132                14.9 %               
151 | ===================================================
152 | Total COMBINATIONAL LOGIC in the block neuron_2.act_func_2:	2021 (18.11 % Utilization)
153 | 
154 | 
Top

155 | 
156 | ##### END OF AREA REPORT #####]
157 | 
158 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/run_options.txt:
--------------------------------------------------------------------------------
 1 | #--  Synopsys, Inc.
 2 | #--  Version L-2016.09L+ice40
 3 | #--  Project file /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/run_options.txt
 4 | #--  Written on Tue Dec 12 13:19:57 2017
 5 | 
 6 | 
 7 | #project files
 8 | add_file -vhdl -lib work "../../../src/lattice-test/act_func.vhd"
 9 | add_file -vhdl -lib work "../../../src/lattice-test/network.vhd"
10 | add_file -vhdl -lib work "../../../src/lattice-test/neuron.vhd"
11 | add_file -vhdl -lib work "../../../src/lattice-test/types.vhd"
12 | 
13 | 
14 | 
15 | #implementation: "ann_vhdl_Implmnt"
16 | impl -add ann_vhdl_Implmnt -type fpga
17 | 
18 | #
19 | #implementation attributes
20 | 
21 | set_option -vlog_std v2001
22 | set_option -project_relative_includes 1
23 | 
24 | #device options
25 | set_option -technology SBTiCE40
26 | set_option -part iCE40HX1K
27 | set_option -package TQ144
28 | set_option -speed_grade ""
29 | set_option -part_companion ""
30 | 
31 | #compilation/mapping options
32 | 
33 | # hdl_compiler_options
34 | set_option -distributed_compile 0
35 | 
36 | # mapper_without_write_options
37 | set_option -frequency auto
38 | set_option -srs_instrumentation 1
39 | 
40 | # mapper_options
41 | set_option -write_verilog 0
42 | set_option -write_vhdl 0
43 | 
44 | # Lattice iCE40
45 | set_option -maxfan 10000
46 | set_option -rw_check_on_ram 0
47 | set_option -disable_io_insertion 0
48 | set_option -pipe 1
49 | set_option -retiming 0
50 | set_option -update_models_cp 0
51 | set_option -fix_gated_and_generated_clocks 1
52 | set_option -run_prop_extract 1
53 | 
54 | # NFilter
55 | set_option -no_sequential_opt 0
56 | 
57 | # sequential_optimization_options
58 | set_option -symbolic_fsm_compiler 1
59 | 
60 | # Compiler Options
61 | set_option -compiler_compatible 0
62 | set_option -resource_sharing 1
63 | 
64 | # Compiler Options
65 | set_option -auto_infer_blackbox 0
66 | 
67 | # Compiler Options
68 | set_option -vhdl2008 1
69 | 
70 | #automatic place and route (vendor) options
71 | set_option -write_apr_constraint 1
72 | 
73 | #set result format/file last
74 | project -result_file "ann_vhdl_Implmnt/ann_vhdl.edf"
75 | impl -active "ann_vhdl_Implmnt"
76 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/scratchproject.prs:
--------------------------------------------------------------------------------
 1 | #--  Synopsys, Inc.
 2 | #--  Version L-2016.09L+ice40
 3 | #--  Project file /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/scratchproject.prs
 4 | 
 5 | #project files
 6 | add_file -vhdl -lib work "/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd"
 7 | add_file -vhdl -lib work "/home/gabriel/ann-vhdl/src/lattice-test/network.vhd"
 8 | add_file -vhdl -lib work "/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd"
 9 | add_file -vhdl -lib work "/home/gabriel/ann-vhdl/src/lattice-test/types.vhd"
10 | 
11 | 
12 | 
13 | #implementation: "ann_vhdl_Implmnt"
14 | impl -add /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt -type fpga
15 | 
16 | #
17 | #implementation attributes
18 | 
19 | set_option -vlog_std v2001
20 | set_option -project_relative_includes 1
21 | set_option -include_path {/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/}
22 | 
23 | #device options
24 | set_option -technology SBTiCE40
25 | set_option -part iCE40HX1K
26 | set_option -package TQ144
27 | set_option -speed_grade ""
28 | set_option -part_companion ""
29 | 
30 | #compilation/mapping options
31 | 
32 | # hdl_compiler_options
33 | set_option -distributed_compile 0
34 | 
35 | # mapper_without_write_options
36 | set_option -frequency auto
37 | set_option -srs_instrumentation 1
38 | 
39 | # mapper_options
40 | set_option -write_verilog 0
41 | set_option -write_vhdl 0
42 | 
43 | # Lattice iCE40
44 | set_option -maxfan 10000
45 | set_option -rw_check_on_ram 0
46 | set_option -disable_io_insertion 0
47 | set_option -pipe 1
48 | set_option -retiming 0
49 | set_option -update_models_cp 0
50 | set_option -fix_gated_and_generated_clocks 1
51 | set_option -run_prop_extract 1
52 | 
53 | # NFilter
54 | set_option -no_sequential_opt 0
55 | 
56 | # sequential_optimization_options
57 | set_option -symbolic_fsm_compiler 1
58 | 
59 | # Compiler Options
60 | set_option -compiler_compatible 0
61 | set_option -resource_sharing 1
62 | 
63 | # Compiler Options
64 | set_option -auto_infer_blackbox 0
65 | 
66 | # Compiler Options
67 | set_option -vhdl2008 1
68 | 
69 | #automatic place and route (vendor) options
70 | set_option -write_apr_constraint 1
71 | 
72 | #set result format/file last
73 | project -result_file "/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.edf"
74 | impl -active "ann_vhdl_Implmnt"
75 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_compiler.srr:
--------------------------------------------------------------------------------
 1 | Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016
 2 | @N|Running in 64-bit mode
 3 | Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 4 | 
 5 | Synopsys VHDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016
 6 | @N|Running in 64-bit mode
 7 | Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 8 | 
 9 | Running on host :cygnus
10 | @N: CD720 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std.vhd":146:18:146:21|Setting time resolution to ps
11 | @N:"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Top entity is set to network.
12 | File /home/gabriel/ann-vhdl/src/lattice-test/types.vhd changed - recompiling
13 | File /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_pkg.vhd changed - recompiling
14 | File /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_generic_pkg.vhd changed - recompiling
15 | File /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd changed - recompiling
16 | File /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/math_real.vhd changed - recompiling
17 | File /home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd changed - recompiling
18 | File /home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd changed - recompiling
19 | File /home/gabriel/ann-vhdl/src/lattice-test/network.vhd changed - recompiling
20 | VHDL syntax check successful!
21 | 
22 | Compiler output is up to date.  No re-compile necessary
23 | 
24 | @N: CD231 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
25 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
26 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
27 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Synthesizing work.network.n_xor.
28 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
29 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
30 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":32:8:32:16|Signal weight_n1 is undriven. Either assign the signal a value or remove the signal declaration.
31 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":35:8:35:16|Signal weight_n2 is undriven. Either assign the signal a value or remove the signal declaration.
32 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":38:8:38:16|Signal weight_n3 is undriven. Either assign the signal a value or remove the signal declaration.
33 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":8:7:8:12|Synthesizing work.neuron.behavioral.
34 | @N: CD231 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":25:12:25:13|Using onehot encoding for type state. For example, enumeration idle is mapped to "10000".
35 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
36 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
37 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":12:7:12:14|Synthesizing work.act_func.tanh.
38 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
39 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
40 | Post processing for work.act_func.tanh
41 | Post processing for work.neuron.behavioral
42 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal sum_s(16 downto -16); possible missing assignment in an if or case statement.
43 | @A: CL109 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Too many clocks (> 8) for set/reset analysis of mult_s, try moving enabling expressions outside process
44 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Latch generated from process for signal mult_s(31 downto -32); possible missing assignment in an if or case statement.
45 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Latch generated from process for signal index(31 downto 0); possible missing assignment in an if or case statement.
46 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal input_s_1(15 downto -16); possible missing assignment in an if or case statement.
47 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal input_s_0(15 downto -16); possible missing assignment in an if or case statement.
48 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":31:66:31:71|Latch generated from process for signal done_s; possible missing assignment in an if or case statement.
49 | Post processing for work.network.n_xor
50 | @N: CL201 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Trying to extract state machine for register current_state.
51 | Extracted state machine for register current_state
52 | State machine has 5 reachable states with original encodings of:
53 |    00001
54 |    00010
55 |    00100
56 |    01000
57 |    10000
58 | 
59 | At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)
60 | 
61 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime
62 | 
63 | Process completed successfully.
64 | # Tue Dec 12 13:19:57 2017
65 | 
66 | ###########################################################]
67 | Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016
68 | @N|Running in 64-bit mode
69 | 
70 | Linker output is up to date. No re-linking necessary
71 | 
72 | 
73 | At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
74 | 
75 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime
76 | 
77 | Process completed successfully.
78 | # Tue Dec 12 13:19:57 2017
79 | 
80 | ###########################################################]
81 | @END
82 | 
83 | At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
84 | 
85 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime
86 | 
87 | Process completed successfully.
88 | # Tue Dec 12 13:19:57 2017
89 | 
90 | ###########################################################]
91 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_compiler.srr.rptmap:
--------------------------------------------------------------------------------
1 | ./synlog/ann_vhdl_compiler.srr,ann_vhdl_compiler.srr,Compile Log
2 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.szr:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.szr


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.xck:
--------------------------------------------------------------------------------
1 | CKID0001:@|S:clk_ibuf_gb_io@|E:n3.current_state_ret_1@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
2 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_multi_srs_gen.srr:
--------------------------------------------------------------------------------
 1 | Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016
 2 | @N|Running in 64-bit mode
 3 | @N: NF107 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Selected library: work cell: network view n_xor as top level
 4 | @N: NF107 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Selected library: work cell: network view n_xor as top level
 5 | 
 6 | At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
 7 | 
 8 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 9 | 
10 | Process completed successfully.
11 | # Tue Dec 12 13:12:00 2017
12 | 
13 | ###########################################################]
14 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_premap.srr:
--------------------------------------------------------------------------------
 1 | # Tue Dec 12 13:19:58 2017
 2 | 
 3 | Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec  5 2016 09:30:53
 4 | Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 5 | Product Version L-2016.09L+ice40
 6 | 
 7 | Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
 8 | 
 9 | @A: MF827 |No constraint file specified.
10 | @L: /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_scck.rpt 
11 | Printing clock  summary report in "/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_scck.rpt" file 
12 | @N: MF248 |Running in 64-bit mode.
13 | @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
14 | 
15 | Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
16 | 
17 | 
18 | Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
19 | 
20 | 
21 | Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
22 | 
23 | 
24 | Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB)
25 | 
26 | ICG Latch Removal Summary:
27 | Number of ICG latches removed:	0
28 | Number of ICG latches not removed:	0
29 | syn_allowed_resources : blockrams=16  set on top level netlist network
30 | 
31 | Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)
32 | 
33 | 
34 | 
35 | Clock Summary
36 | *****************
37 | 
38 | Start                                       Requested     Requested     Clock                          Clock                     Clock
39 | Clock                                       Frequency     Period        Type                           Group                     Load 
40 | --------------------------------------------------------------------------------------------------------------------------------------
41 | network|clk                                 1.0 MHz       1000.000      inferred                       Autoconstr_clkgroup_0     15   
42 | neuron_0|current_state_derived_clock[1]     1.0 MHz       1000.000      derived (from network|clk)     Autoconstr_clkgroup_0     65   
43 | neuron_0|current_state_derived_clock[3]     1.0 MHz       1000.000      derived (from network|clk)     Autoconstr_clkgroup_0     5346 
44 | neuron_1|current_state_derived_clock[1]     1.0 MHz       1000.000      derived (from network|clk)     Autoconstr_clkgroup_0     65   
45 | neuron_1|current_state_derived_clock[3]     1.0 MHz       1000.000      derived (from network|clk)     Autoconstr_clkgroup_0     5346 
46 | neuron_2|current_state_derived_clock[1]     1.0 MHz       1000.000      derived (from network|clk)     Autoconstr_clkgroup_0     65   
47 | neuron_2|current_state_derived_clock[3]     1.0 MHz       1000.000      derived (from network|clk)     Autoconstr_clkgroup_0     5346 
48 | ======================================================================================================================================
49 | 
50 | @W: MT529 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Found inferred clock network|clk which controls 15 sequential elements including n1.current_state[0:4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
51 | 
52 | Finished Pre Mapping Phase.
53 | @N: BN225 |Writing default property annotation file /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap.
54 | 
55 | Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)
56 | 
57 | Encoding state machine current_state[0:4] (in view: work.neuron_2(behavioral))
58 | original code -> new code
59 |    00001 -> 00001
60 |    00010 -> 00010
61 |    00100 -> 00100
62 |    01000 -> 01000
63 |    10000 -> 10000
64 | Encoding state machine current_state[0:4] (in view: work.neuron_1(behavioral))
65 | original code -> new code
66 |    00001 -> 00001
67 |    00010 -> 00010
68 |    00100 -> 00100
69 |    01000 -> 01000
70 |    10000 -> 10000
71 | Encoding state machine current_state[0:4] (in view: work.neuron_0(behavioral))
72 | original code -> new code
73 |    00001 -> 00001
74 |    00010 -> 00010
75 |    00100 -> 00100
76 |    01000 -> 01000
77 |    10000 -> 10000
78 | None
79 | None
80 | 
81 | Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
82 | 
83 | Pre-mapping successful!
84 | 
85 | At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 136MB)
86 | 
87 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime
88 | # Tue Dec 12 13:19:59 2017
89 | 
90 | ###########################################################]
91 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_premap.szr:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_premap.szr


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/layer0.tlg.rptmap:
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1 | ./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
2 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_errors.txt:
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1 | @E: Can't open input file /home/gabriel/ann-vhdl/src/network_fpga.vhd
2 | @E::VHDL compiler failed
3 | 
4 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_notes.txt:
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 1 | @N|Running in 64-bit mode
 2 | @N|Running in 64-bit mode
 3 | @N: CD720 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std.vhd":146:18:146:21|Setting time resolution to ps
 4 | @N:"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Top entity is set to network.
 5 | @N: CD231 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
 6 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
 7 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
 8 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Synthesizing work.network.n_xor.
 9 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
10 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
11 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":8:7:8:12|Synthesizing work.neuron.behavioral.
12 | @N: CD231 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":25:12:25:13|Using onehot encoding for type state. For example, enumeration idle is mapped to "10000".
13 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
14 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
15 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":12:7:12:14|Synthesizing work.act_func.tanh.
16 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
17 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
18 | @N: CL201 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Trying to extract state machine for register current_state.
19 | @N|Running in 64-bit mode
20 | 
21 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_runstatus.xml:
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 1 | 
 2 | 
 6 | 
 7 |  
 8 |   
 9 |     /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_compiler.srr
10 |     Synopsys HDL Compiler
11 |    
12 |   
13 |     Completed    
14 |   
15 |  
16 | 			
17 |   19
18 |   /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_notes.txt
19 |   
20 | 			
21 |   9
22 |   /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_warnings.txt
23 |   
24 | 			
25 |   0
26 |   /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_errors.txt
27 |   
28 | 			
29 |   -
30 |   
31 | 			
32 |   00h:00m:00s
33 |   
34 | 			
35 |   -
36 |   
37 | 			
38 |   1513091997
39 |   
40 | 			
41 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_compiler_warnings.txt:
--------------------------------------------------------------------------------
 1 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":32:8:32:16|Signal weight_n1 is undriven. Either assign the signal a value or remove the signal declaration.
 2 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":35:8:35:16|Signal weight_n2 is undriven. Either assign the signal a value or remove the signal declaration.
 3 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":38:8:38:16|Signal weight_n3 is undriven. Either assign the signal a value or remove the signal declaration.
 4 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal sum_s(16 downto -16); possible missing assignment in an if or case statement.
 5 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Latch generated from process for signal mult_s(31 downto -32); possible missing assignment in an if or case statement.
 6 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Latch generated from process for signal index(31 downto 0); possible missing assignment in an if or case statement.
 7 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal input_s_1(15 downto -16); possible missing assignment in an if or case statement.
 8 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal input_s_0(15 downto -16); possible missing assignment in an if or case statement.
 9 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":31:66:31:71|Latch generated from process for signal done_s; possible missing assignment in an if or case statement.
10 | 
11 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_area_report.xml:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 6 | 
 7 | 
 8 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_resourceusage.rpt
 9 | Resource Usage
10 | 
11 | 
12 | 100
13 | 
14 | 
15 | 21
16 | 
17 | 
18 | 0
19 | 
20 | 
21 | 887
22 | 
23 | 
24 | 10136
25 | 
26 | 
27 | 


--------------------------------------------------------------------------------
/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_combined_clk.rpt:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | @S |Clock Optimization Summary
 4 | 
 5 | 
 6 | #### START OF CLOCK OPTIMIZATION REPORT #####[
 7 | 
 8 | 1 non-gated/non-generated clock tree(s) driving 21 clock pin(s) of sequential element(s)
 9 | 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
10 | 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
11 | 
12 | =============================== Non-Gated/Non-Generated Clocks ===============================
13 | Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance       
14 | ----------------------------------------------------------------------------------------------
15 | @K:CKID0001       clk_ibuf_gb_io      SB_GB_IO               21         n3.current_state_ret_1
16 | ==============================================================================================
17 | 
18 | 
19 | ##### END OF CLOCK OPTIMIZATION REPORT ######]
20 | 
21 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_errors.txt:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_errors.txt


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_notes.txt:
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 1 | @N: MF248 |Running in 64-bit mode.
 2 | @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 3 | @N: MT206 |Auto Constrain mode is enabled
 4 | @N: MO106 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":69:46:69:46|Found ROM .delname. (in view: work.act_func_0(tanh)) with 32 words by 17 bits.
 5 | @N: MO106 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":68:13:68:13|Found ROM .delname. (in view: work.act_func_0(tanh)) with 32 words by 16 bits.
 6 | @N: MO106 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":69:46:69:46|Found ROM .delname. (in view: work.act_func_1(tanh)) with 32 words by 17 bits.
 7 | @N: MO106 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":68:13:68:13|Found ROM .delname. (in view: work.act_func_1(tanh)) with 32 words by 16 bits.
 8 | @N: MO106 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":69:46:69:46|Found ROM .delname. (in view: work.act_func_2(tanh)) with 32 words by 17 bits.
 9 | @N: MO106 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":68:13:68:13|Found ROM .delname. (in view: work.act_func_2(tanh)) with 32 words by 16 bits.
10 | @N: MF578 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Incompatible asynchronous control logic preventing generated clock conversion of n3.input_s_1[31] (in view: work.network(n_xor)).
11 | @N: BN362 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Removing sequential instance n3.current_state[3] (in view: work.network(n_xor)) because it does not drive other instances.
12 | @N: BN362 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Removing sequential instance n3.current_state[1] (in view: work.network(n_xor)) because it does not drive other instances.
13 | @N: BN362 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Removing sequential instance n2.current_state[3] (in view: work.network(n_xor)) because it does not drive other instances.
14 | @N: BN362 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Removing sequential instance n2.current_state[1] (in view: work.network(n_xor)) because it does not drive other instances.
15 | @N: BN362 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Removing sequential instance n1.current_state[3] (in view: work.network(n_xor)) because it does not drive other instances.
16 | @N: BN362 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Removing sequential instance n1.current_state[1] (in view: work.network(n_xor)) because it does not drive other instances.
17 | @N: FX1016 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":14:2:14:4|SB_GB_IO inserted on the port clk.
18 | @N: FX1016 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":15:2:15:4|SB_GB_IO inserted on the port rst.
19 | @N: MT611 :|Automatically generated clock neuron_2|current_state_derived_clock[3] is not used and is being removed
20 | @N: MT611 :|Automatically generated clock neuron_2|current_state_derived_clock[1] is not used and is being removed
21 | @N: MT611 :|Automatically generated clock neuron_1|current_state_derived_clock[3] is not used and is being removed
22 | @N: MT611 :|Automatically generated clock neuron_1|current_state_derived_clock[1] is not used and is being removed
23 | @N: MT611 :|Automatically generated clock neuron_0|current_state_derived_clock[3] is not used and is being removed
24 | @N: MT611 :|Automatically generated clock neuron_0|current_state_derived_clock[1] is not used and is being removed
25 | @N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
26 | @N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
27 | @N: FX1056 |Writing EDF file: /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.edf
28 | @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
29 | @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
30 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_opt_report.xml:
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 1 | 
 2 | 
 6 | 
 7 | 
 8 | 1 / 0
 9 | 
10 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_combined_clk.rpt
11 | START OF CLOCK OPTIMIZATION REPORT
12 | 
13 | 
14 | 
15 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_resourceusage.rpt:
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 1 | ---------------------------------------
 2 | Resource Usage Report for network 
 3 | 
 4 | Mapping to part: ice40hx1ktq144
 5 | Cell usage:
 6 | GND             6 uses
 7 | SB_CARRY        887 uses
 8 | SB_DFFR         12 uses
 9 | SB_DFFS         9 uses
10 | VCC             6 uses
11 | SB_LUT4         10136 uses
12 | 
13 | I/O ports: 100
14 | I/O primitives: 100
15 | SB_GB_IO       2 uses
16 | SB_IO          98 uses
17 | 
18 | I/O Register bits:                  0
19 | Register bits not including I/Os:   21 (1%)
20 | 
21 | @S |Mapping Summary:
22 | Total  LUTs: 10136 (791%)
23 | 
24 | Distribution of All Consumed LUTs = LUT4 
25 | Distribution of All Consumed Luts 10136 = 10136 
26 | 
27 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_runstatus.xml:
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 1 | 
 2 | 
 6 | 
 7 | 
 8 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.srr
 9 | Synopsys Lattice Technology Mapper
10 | 
11 | 
12 | Completed
13 | 
14 | 
15 | 
16 | 29
17 | 
18 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_notes.txt
19 | 
20 | 
21 | 
22 | 1824
23 | 
24 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_warnings.txt
25 | 
26 | 
27 | 
28 | 0
29 | 
30 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_errors.txt
31 | 
32 | 
33 | 
34 | 0h:01m:49s
35 | 
36 | 
37 | 0h:01m:50s
38 | 
39 | 
40 | 313MB
41 | 
42 | 
43 | 1513092109
44 | 
45 | 
46 | 
47 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper_timing_report.xml:
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 1 | 
 2 | 
 6 | 
 7 | 
 8 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.srr
 9 | START OF TIMING REPORT
10 | 
11 | 
12 | Clock Name
13 | Req Freq
14 | Est Freq
15 | Slack
16 | 
17 | 
18 | network|clk
19 | 131.5 MHz
20 | 111.7 MHz
21 | -1.342
22 | 
23 | 
24 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_errors.txt:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_errors.txt


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_notes.txt:
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1 | @N: MF248 |Running in 64-bit mode.
2 | @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
3 | @N: BN225 |Writing default property annotation file /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap.
4 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_runstatus.xml:
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 1 | 
 2 | 
 6 | 
 7 | 
 8 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_premap.srr
 9 | Synopsys Lattice Technology Pre-mapping
10 | 
11 | 
12 | Completed
13 | 
14 | 
15 | 
16 | 3
17 | 
18 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_notes.txt
19 | 
20 | 
21 | 
22 | 1
23 | 
24 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_warnings.txt
25 | 
26 | 
27 | 
28 | 0
29 | 
30 | /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_errors.txt
31 | 
32 | 
33 | 
34 | 0h:00m:00s
35 | 
36 | 
37 | 0h:00m:00s
38 | 
39 | 
40 | 136MB
41 | 
42 | 
43 | 1513091999
44 | 
45 | 
46 | 
47 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap_warnings.txt:
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1 | @W: MT529 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Found inferred clock network|clk which controls 15 sequential elements including n1.current_state[0:4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
2 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/syntax_constraint_check.rpt.rptmap:
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1 | ./ann_vhdl_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
2 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl.plg:
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 1 | @P:  Worst Slack : -1.342
 2 | @P:  network|clk - Estimated Frequency : 111.7 MHz
 3 | @P:  network|clk - Requested Frequency : 131.5 MHz
 4 | @P:  network|clk - Estimated Period : 8.949
 5 | @P:  network|clk - Requested Period : 7.607
 6 | @P:  network|clk - Slack : -1.342
 7 | @P: network Part : ice40hx1ktq144
 8 | @P: network I/O primitives : 100
 9 | @P: network I/O Register bits : 0
10 | @P: network Register bits (Non I/O) : 21 (1%)
11 | @P: network Total Luts : 10136 (791%)
12 | @P:  CPU Time : 0h:01m:49s
13 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl_multi_srs_gen_srr.htm:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016
 4 | @N: :  | Running in 64-bit mode 
 5 | @N:NF107 : network.vhd(8) | Selected library: work cell: network view n_xor as top level
 6 | @N:NF107 : network.vhd(8) | Selected library: work cell: network view n_xor as top level
 7 | 
 8 | At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
 9 | 
10 | Process took 0h:00m:01s realtime, 0h:00m:01s cputime
11 | 
12 | Process completed successfully.
13 | # Tue Dec 12 13:12:00 2017
14 | 
15 | ###########################################################]
16 | 
17 | 

18 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl_multi_srs_gen_toc.htm:
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 1 |   
 2 |   
 3 |     
 4 |       
 5 |    
 6 | 
 7 |   
 8 |    
 9 |     
21 | 
22 |    
23 | 
24 |   
25 |  


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl_toc.htm:
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 1 |   
 2 |   
 3 |     
 4 |       
 5 |    
 6 | 
 7 |   
 8 |    
 9 |     
41 | 
42 |    
43 | 
44 |   
45 |  


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/closed.png:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/closed.png


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/cmdrec_compiler.log:
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 1 | /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/c_hdl  -osyn  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs  -hdllog  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_compiler.srr  -encrypt  -mp  1  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -primux -fixsmult -infer_seqShift -ice -sdff_counter -nram -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -vhdl2008  -ignore_undefined_lib  -lib work /home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd -lib work /home/gabriel/ann-vhdl/src/lattice-test/network.vhd -lib work /home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd -lib work /home/gabriel/ann-vhdl/src/lattice-test/types.vhd 
 2 | rc:0 success:1 runtime:0
 3 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs|io:o|time:1513091519|size:13141|exec:0
 4 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_compiler.srr|io:o|time:1513091997|size:7368|exec:0
 5 | file:/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd|io:i|time:1513091238|size:3474|exec:0
 6 | file:/home/gabriel/ann-vhdl/src/lattice-test/network.vhd|io:i|time:1513091358|size:2628|exec:0
 7 | file:/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd|io:i|time:1513091222|size:2813|exec:0
 8 | file:/home/gabriel/ann-vhdl/src/lattice-test/types.vhd|io:i|time:1513091213|size:1909|exec:0
 9 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/c_hdl|io:i|time:1513077237|size:5690328|exec:1
10 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/c_hdl|io:i|time:1513077230|size:365|exec:1
11 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/cmdrec_fpga_mapper.log:
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 1 | /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/m_generic  -prodtype  synplify_pro  -encrypt  -pro  -rundir  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt   -part iCE40HX1K  -package TQ144    -maxfan 10000 -RWCheckOnRam 0 -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -summaryfile /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_fpga_mapper.xml  -flow mapping  -multisrs  -oedif  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.edf   -autoconstraint  -freq 1,000   /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd  -sap  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap  -otap  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.tap  -omap  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.map  -devicelib  /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/generic/sb_ice40.v  -sap  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap  -ologparam  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl.plg  -osyn  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srm  -prjdir  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/  -prjname  ann_vhdl_syn  -log  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.srr 
 2 | rc:1 success:1 runtime:110
 3 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.edf|io:o|time:1513092108|size:6464125|exec:0
 4 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd|io:i|time:1513091998|size:52779|exec:0
 5 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap|io:o|time:1513091999|size:3586|exec:0
 6 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.tap|io:o|time:0|size:0|exec:0
 7 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.map|io:o|time:1513092109|size:27|exec:0
 8 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/generic/sb_ice40.v|io:i|time:1513077232|size:220434|exec:0
 9 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap|io:o|time:1513091999|size:3586|exec:0
10 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl.plg|io:o|time:1513092109|size:462|exec:0
11 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srm|io:o|time:1513092109|size:16374|exec:0
12 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_fpga_mapper.srr|io:o|time:1513092109|size:460484|exec:0
13 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/m_generic|io:i|time:1513077245|size:32925640|exec:1
14 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/m_generic|io:i|time:1513077230|size:345|exec:1
15 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/cmdrec_multi_srs_gen.log:
--------------------------------------------------------------------------------
1 | /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/syn_nfilter  -link  -multisrs  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs  -osyn  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult.srs  -log  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_multi_srs_gen.srr 
2 | rc:0 success:1 runtime:0
3 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs|io:i|time:1513091519|size:13141|exec:0
4 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult.srs|io:o|time:1513091520|size:3212|exec:0
5 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_multi_srs_gen.srr|io:o|time:1513091520|size:668|exec:0
6 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/syn_nfilter|io:i|time:1513077249|size:11473624|exec:1
7 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/syn_nfilter|io:i|time:1513077230|size:366|exec:1
8 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/cmdrec_premap.log:
--------------------------------------------------------------------------------
 1 | /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/m_generic  -prodtype  synplify_pro  -encrypt  -pro  -rundir  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt   -part iCE40HX1K  -package TQ144    -maxfan 10000 -RWCheckOnRam 0 -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -summaryfile /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/report/ann_vhdl_premap.xml  -oedif  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.edf  -conchk_prepass  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_cck.rpt   -autoconstraint  -freq 1,000   /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult.srs  -flow prepass  -gcc_prepass  -osrd  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd  -qsap  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap  -devicelib  /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/generic/sb_ice40.v  -ologparam  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl.plg  -osyn  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd  -prjdir  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/  -prjname  ann_vhdl_syn  -log  /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_premap.srr 
 2 | rc:1 success:1 runtime:1
 3 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.edf|io:o|time:1513091800|size:6464125|exec:0
 4 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl_cck.rpt|io:o|time:1513091999|size:8581|exec:0
 5 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult.srs|io:i|time:1513091520|size:3212|exec:0
 6 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd|io:o|time:1513091998|size:52779|exec:0
 7 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.sap|io:o|time:1513091999|size:3586|exec:0
 8 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/generic/sb_ice40.v|io:i|time:1513077232|size:220434|exec:0
 9 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/ann_vhdl.plg|io:o|time:1513091998|size:0|exec:0
10 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd|io:o|time:1513091998|size:52779|exec:0
11 | file:/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synlog/ann_vhdl_premap.srr|io:o|time:1513091999|size:5041|exec:0
12 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/m_generic|io:i|time:1513077245|size:32925640|exec:1
13 | file:/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/bin/m_generic|io:i|time:1513077230|size:345|exec:1
14 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/open.png:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/open.png


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/run_option.xml:
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 1 |  
 2 |  
10 |  
11 |      
12 |      
13 |      
14 |      
15 |      
16 |      
17 |      
18 |      
19 |      
20 |      
21 |      
22 | 
23 | 
24 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/syntmp/synenc/synenc.lst:
--------------------------------------------------------------------------------
1 | "/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std.vhd"
2 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/.cckTransfer:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/.cckTransfer


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/.complist:
--------------------------------------------------------------------------------
1 | 
2 | : 0 work.network "/home/gabriel/ann-vhdl/src/lattice-test/network.vhd" 8 7 work.neuron work.neuron work.neuron 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.fdep:
--------------------------------------------------------------------------------
 1 | #OPTIONS:"|-layerid|0|-orig_srs|/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs|-autotop|-prodtype|synplify_pro|-primux|-fixsmult|-infer_seqShift|-ice|-sdff_counter|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work"
 2 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/c_vhdl":1513077237
 3 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/location.map":1513077236
 4 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std.vhd":1513077236
 5 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/snps_haps_pkg.vhd":1513077236
 6 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std1164.vhd":1513077236
 7 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std_textio.vhd":1513077236
 8 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/numeric.vhd":1513077236
 9 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/umr_capim.vhd":1513077236
10 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/arith.vhd":1513077236
11 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/unsigned.vhd":1513077236
12 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/hyperents.vhd":1513077236
13 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/types.vhd":1513091213
14 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_pkg.vhd":1513077236
15 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_generic_pkg.vhd":1513077236
16 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":1513077236
17 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/math_real.vhd":1513077236
18 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":1513091238
19 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":1513091222
20 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":1513091358
21 | 0			"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd" vhdl
22 | 1			"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd" vhdl
23 | 2			"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd" vhdl
24 | 3			"/home/gabriel/ann-vhdl/src/lattice-test/types.vhd" vhdl
25 | #Dependency Lists(Uses List)
26 | 0 3
27 | 1 3 2
28 | 2 3 0
29 | 3 -1
30 | #Dependency Lists(Users Of)
31 | 0 2
32 | 1 -1
33 | 2 1
34 | 3 0 1 2
35 | #Design Unit to File Association
36 | module work neuron 2
37 | arch work neuron behavioral 2
38 | module work network 1
39 | arch work network n_xor 1
40 | module work act_func 0
41 | arch work act_func threshold 0
42 | arch work act_func tanh 0
43 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m.srm:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m.srm


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m_srm/1.srm:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m_srm/1.srm


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m_srm/fileinfo.srm:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m_srm/fileinfo.srm


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult.srs:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult.srs


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult_srs/1.srs:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult_srs/1.srs


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult_srs/fileinfo.srs:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult_srs/fileinfo.srs


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult_srs/skeleton.srs:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_mult_srs/skeleton.srs


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.fse:
--------------------------------------------------------------------------------
 1 | 
 2 | fsm_encoding {15402401} onehot
 3 | 
 4 | fsm_state_encoding {15402401} idle {00001}
 5 | 
 6 | fsm_state_encoding {15402401} reg_inputs {00010}
 7 | 
 8 | fsm_state_encoding {15402401} mult {00100}
 9 | 
10 | fsm_state_encoding {15402401} sum {01000}
11 | 
12 | fsm_state_encoding {15402401} act_func {10000}
13 | 
14 | fsm_registers {15402401} {current_state[0]}  {current_state[1]}  {current_state[2]}  {current_state[3]}  {current_state[4]} 
15 | 
16 | fsm_encoding {15402401} onehot
17 | 
18 | fsm_state_encoding {15402401} idle {00001}
19 | 
20 | fsm_state_encoding {15402401} reg_inputs {00010}
21 | 
22 | fsm_state_encoding {15402401} mult {00100}
23 | 
24 | fsm_state_encoding {15402401} sum {01000}
25 | 
26 | fsm_state_encoding {15402401} act_func {10000}
27 | 
28 | fsm_registers {15402401} {current_state[0]}  {current_state[1]}  {current_state[2]}  {current_state[3]}  {current_state[4]} 
29 | 
30 | fsm_encoding {15402401} onehot
31 | 
32 | fsm_state_encoding {15402401} idle {00001}
33 | 
34 | fsm_state_encoding {15402401} reg_inputs {00010}
35 | 
36 | fsm_state_encoding {15402401} mult {00100}
37 | 
38 | fsm_state_encoding {15402401} sum {01000}
39 | 
40 | fsm_state_encoding {15402401} act_func {10000}
41 | 
42 | fsm_registers {15402401} {current_state[0]}  {current_state[1]}  {current_state[2]}  {current_state[3]}  {current_state[4]} 
43 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_prem.srd


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/layer0.fdep:
--------------------------------------------------------------------------------
 1 | #defaultlanguage:vhdl
 2 | #OPTIONS:"|-layerid|0|-orig_srs|/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs|-autotop|-prodtype|synplify_pro|-primux|-fixsmult|-infer_seqShift|-ice|-sdff_counter|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work"
 3 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/c_vhdl":1513077237
 4 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/location.map":1513077236
 5 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std.vhd":1513077236
 6 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/snps_haps_pkg.vhd":1513077236
 7 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std1164.vhd":1513077236
 8 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std_textio.vhd":1513077236
 9 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/numeric.vhd":1513077236
10 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/umr_capim.vhd":1513077236
11 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/arith.vhd":1513077236
12 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/unsigned.vhd":1513077236
13 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/hyperents.vhd":1513077236
14 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/types.vhd":1513091213
15 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_pkg.vhd":1513077236
16 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_generic_pkg.vhd":1513077236
17 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":1513077236
18 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/math_real.vhd":1513077236
19 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":1513091238
20 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":1513091222
21 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":1513091358
22 | 0 "/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd" vhdl
23 | 1 "/home/gabriel/ann-vhdl/src/lattice-test/network.vhd" vhdl
24 | 2 "/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd" vhdl
25 | 3 "/home/gabriel/ann-vhdl/src/lattice-test/types.vhd" vhdl
26 | 
27 | # Dependency Lists (Uses list)
28 | 0 3 
29 | 1 2 3 
30 | 2 0 3 
31 | 3 -1
32 | 
33 | # Dependency Lists (Users Of)
34 | 0 2 
35 | 1 -1
36 | 2 1 
37 | 3 2 1 0 
38 | 
39 | # Design Unit to File Association
40 | arch work act_func tanh 0
41 | arch work act_func threshold 0
42 | module work act_func 0
43 | arch work network n_xor 1
44 | module work network 1
45 | arch work neuron behavioral 2
46 | module work neuron 2
47 | 
48 | 
49 | # Configuration files used
50 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/layer0.fdeporig:
--------------------------------------------------------------------------------
 1 | #defaultlanguage:vhdl
 2 | #OPTIONS:"|-layerid|0|-orig_srs|/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_comp.srs|-autotop|-prodtype|synplify_pro|-primux|-fixsmult|-infer_seqShift|-ice|-sdff_counter|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work"
 3 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/c_vhdl":1513077237
 4 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/location.map":1513077236
 5 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std.vhd":1513077236
 6 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/snps_haps_pkg.vhd":1513077236
 7 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std1164.vhd":1513077236
 8 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std_textio.vhd":1513077236
 9 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/numeric.vhd":1513077236
10 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/umr_capim.vhd":1513077236
11 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/arith.vhd":1513077236
12 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/unsigned.vhd":1513077236
13 | #CUR:"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd/hyperents.vhd":1513077236
14 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":1513091238
15 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":1513091358
16 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":1513091222
17 | #CUR:"/home/gabriel/ann-vhdl/src/lattice-test/types.vhd":1513091213
18 | 0 "/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd" vhdl
19 | 1 "/home/gabriel/ann-vhdl/src/lattice-test/network.vhd" vhdl
20 | 2 "/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd" vhdl
21 | 3 "/home/gabriel/ann-vhdl/src/lattice-test/types.vhd" vhdl
22 | 
23 | # Dependency Lists (Uses list)
24 | 0 3 
25 | 1 2 3 
26 | 2 0 3 
27 | 3 -1
28 | 
29 | # Dependency Lists (Users Of)
30 | 0 2 
31 | 1 -1
32 | 2 1 
33 | 3 2 1 0 
34 | 
35 | # Design Unit to File Association
36 | arch work act_func tanh 0
37 | arch work act_func threshold 0
38 | module work act_func 0
39 | arch work network n_xor 1
40 | module work network 1
41 | arch work neuron behavioral 2
42 | module work neuron 2
43 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/layer0.srs:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/layer0.srs


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/layer0.tlg:
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 1 | @N: CD231 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
 2 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
 3 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
 4 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":8:7:8:13|Synthesizing work.network.n_xor.
 5 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
 6 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
 7 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":32:8:32:16|Signal weight_n1 is undriven. Either assign the signal a value or remove the signal declaration.
 8 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":35:8:35:16|Signal weight_n2 is undriven. Either assign the signal a value or remove the signal declaration.
 9 | @W: CD638 :"/home/gabriel/ann-vhdl/src/lattice-test/network.vhd":38:8:38:16|Signal weight_n3 is undriven. Either assign the signal a value or remove the signal declaration.
10 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":8:7:8:12|Synthesizing work.neuron.behavioral.
11 | @N: CD231 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":25:12:25:13|Using onehot encoding for type state. For example, enumeration idle is mapped to "10000".
12 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
13 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
14 | @N: CD630 :"/home/gabriel/ann-vhdl/src/lattice-test/act_func.vhd":12:7:12:14|Synthesizing work.act_func.tanh.
15 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":46:33:46:34|Using sequential encoding for type fixed_overflow_style_type.
16 | @N: CD233 :"/home/gabriel/.lscc/iCEcube2.2017.08/synpbase/lib/vhd2008/fixed_float_types.vhd":44:30:44:31|Using sequential encoding for type fixed_round_style_type.
17 | Post processing for work.act_func.tanh
18 | Post processing for work.neuron.behavioral
19 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal sum_s(16 downto -16); possible missing assignment in an if or case statement.
20 | @A: CL109 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Too many clocks (> 8) for set/reset analysis of mult_s, try moving enabling expressions outside process
21 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Latch generated from process for signal mult_s(31 downto -32); possible missing assignment in an if or case statement.
22 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":29:81:29:81|Latch generated from process for signal index(31 downto 0); possible missing assignment in an if or case statement.
23 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal input_s_1(15 downto -16); possible missing assignment in an if or case statement.
24 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":50:2:50:5|Latch generated from process for signal input_s_0(15 downto -16); possible missing assignment in an if or case statement.
25 | @W: CL117 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":31:66:31:71|Latch generated from process for signal done_s; possible missing assignment in an if or case statement.
26 | Post processing for work.network.n_xor
27 | @N: CL201 :"/home/gabriel/ann-vhdl/src/lattice-test/neuron.vhd":40:2:40:3|Trying to extract state machine for register current_state.
28 | Extracted state machine for register current_state
29 | State machine has 5 reachable states with original encodings of:
30 |    00001
31 |    00010
32 |    00100
33 |    01000
34 |    10000
35 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/vhdl.tbl:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/vhdl.tbl


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/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/vhdlcfg.tbl:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/vhdlcfg.tbl


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/fpga/lattice/ann_vhdl/ann_vhdl_sbt.project:
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 1 | [Project]
 2 | ProjectVersion=2.0
 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 12 2017 08:41:24
 4 | ProjectName=ann_vhdl
 5 | Vendor=SiliconBlue
 6 | Synthesis=synplify
 7 | ProjectVFiles=../../../src/lattice-test/act_func.vhd=work,../../../src/lattice-test/network.vhd=work,../../../src/lattice-test/neuron.vhd=work,../../../src/lattice-test/types.vhd=work
 8 | ProjectCFiles=
 9 | CurImplementation=ann_vhdl_Implmnt
10 | Implementations=ann_vhdl_Implmnt
11 | StartFromSynthesis=yes
12 | IPGeneration=false
13 | 
14 | [ann_vhdl_Implmnt]
15 | DeviceFamily=iCE40
16 | Device=HX1K
17 | DevicePackage=TQ144
18 | DevicePower=
19 | NetlistFile=ann_vhdl_Implmnt/ann_vhdl.edf
20 | AdditionalEDIFFile=
21 | IPEDIFFile=
22 | DesignLib=
23 | DesignView=
24 | DesignCell=
25 | SynthesisSDCFile=ann_vhdl_Implmnt/ann_vhdl.scf
26 | UserPinConstraintFile=
27 | UserSDCFile=
28 | PhysicalConstraintFile=ann_vhdl_Implmnt/sbt/constraint/network_pcf_sbt.pcf
29 | BackendImplPathName=
30 | Devicevoltage=1.14
31 | DevicevoltagePerformance=+/-5%(datasheet default)
32 | DeviceTemperature=85
33 | TimingAnalysisBasedOn=Worst
34 | OperationRange=Commercial
35 | TypicalCustomTemperature=25
36 | WorstCustomTemperature=85
37 | BestCustomTemperature=0
38 | IOBankVoltages=topBank,2.5 bottomBank,2.5 leftBank,2.5 rightBank,2.5
39 | derValue=0.701346
40 | TimingPathNumberStick=0
41 | 
42 | [lse options]
43 | CarryChain=True
44 | CarryChainLength=0
45 | CommandLineOptions=
46 | EBRUtilization=100.00
47 | FSMEncodingStyle=Auto
48 | FixGatedClocks=True
49 | I/OInsertion=True
50 | IntermediateFileDump=False
51 | LoopLimit=1950
52 | MaximalFanout=10000
53 | MemoryInitialValueFileSearchPath=
54 | NumberOfCriticalPaths=3
55 | OptimizationGoal=Area
56 | PropagateConstants=True
57 | RAMStyle=Auto
58 | ROMStyle=Auto
59 | RWCheckOnRam=False
60 | RemoveDuplicateRegisters=True
61 | ResolvedMixedDrivers=False
62 | ResourceSharing=True
63 | TargetFrequency=
64 | TopLevelUnit=
65 | UseIORegister=Auto
66 | VHDL2008=False
67 | VerilogIncludeSearchPath=
68 | 
69 | [tool options]
70 | PlacerEffortLevel=high
71 | PlacerAutoLutCascade=yes
72 | PlacerAutoRamCascade=yes
73 | PlacerPowerDriven=no
74 | PlacerAreaDriven=no
75 | RouteWithTimingDriven=yes
76 | RouteWithPinPermutation=yes
77 | BitmapSPIFlashMode=yes
78 | BitmapRAM4KInit=yes
79 | BitmapInitRamBank=1111
80 | BitmapOscillatorFR=low
81 | BitmapEnableWarmBoot=yes
82 | BitmapDisableHeader=no
83 | BitmapSetSecurity=no
84 | BitmapSetNoUsedIONoPullup=no
85 | FloorPlannerShowFanInNets=yes
86 | FloorPlannerShowFanOutNets=yes
87 | HookTo3rdPartyTextEditor=no
88 | 
89 | 


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/fpga/lattice/ann_vhdl/ann_vhdl_syn.prd:
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 1 | #--  Synopsys, Inc.
 2 | #--  Version L-2016.09L+ice40
 3 | #--  Project file /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_syn.prd
 4 | #--  Written on Tue Dec 12 13:14:43 2017
 5 | 
 6 | #
 7 | ### Watch Implementation type ###
 8 | #
 9 | watch_impl -all
10 | #
11 | ### Watch Implementation properties ###
12 | #
13 | watch_prop -clear
14 | 


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/fpga/lattice/ann_vhdl/stdout.log:
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 1 | Running in Lattice mode
 2 | 
 3 | Starting:    /home/gabriel/.lscc/iCEcube2.2017.08/synpbase/linux_a_64/mbin/synplify
 4 | Install:     /home/gabriel/.lscc/iCEcube2.2017.08/synpbase
 5 | Hostname:    cygnus
 6 | Date:        Tue Dec 12 13:18:26 2017
 7 | Version:     L-2016.09L+ice40
 8 | 
 9 | Arguments:   -product synplify_pro ann_vhdl_syn.prj
10 | ProductType: synplify_pro
11 | 
12 | 
13 | 
14 | 
15 | auto_infer_blackbox is not supported in current product.
16 | New HDL Analyst: enabled
17 | log file: "/home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srr"
18 | Running: ann_vhdl_Implmnt in foreground
19 | 
20 | Running ann_vhdl_syn|ann_vhdl_Implmnt
21 | 
22 | Running: compile (Compile) on ann_vhdl_syn|ann_vhdl_Implmnt
23 | # Tue Dec 12 13:19:57 2017
24 | 
25 | Running: compile_flow (Compile Process) on ann_vhdl_syn|ann_vhdl_Implmnt
26 | # Tue Dec 12 13:19:57 2017
27 | 
28 | Running: compiler (Compile Input) on ann_vhdl_syn|ann_vhdl_Implmnt
29 | # Tue Dec 12 13:19:57 2017
30 | 
31 | compiler completed
32 | # Tue Dec 12 13:19:57 2017
33 | 
34 | Return Code: 0
35 | Run Time:00h:00m:00s
36 | 
37 | Running: multi_srs_gen (Multi-srs Generator) on ann_vhdl_syn|ann_vhdl_Implmnt
38 | # Tue Dec 12 13:19:57 2017
39 | Up-To-Date: multi_srs_gen. No run necessary
40 | Complete: Compile Process on ann_vhdl_syn|ann_vhdl_Implmnt
41 | 
42 | Running: premap (Pre-mapping) on ann_vhdl_syn|ann_vhdl_Implmnt
43 | # Tue Dec 12 13:19:58 2017
44 | 
45 | premap completed with warnings
46 | # Tue Dec 12 13:19:59 2017
47 | 
48 | Return Code: 1
49 | Run Time:00h:00m:01s
50 | Complete: Compile on ann_vhdl_syn|ann_vhdl_Implmnt
51 | 
52 | Running: map (Map) on ann_vhdl_syn|ann_vhdl_Implmnt
53 | # Tue Dec 12 13:19:59 2017
54 | 
55 | Running: fpga_mapper (Map & Optimize) on ann_vhdl_syn|ann_vhdl_Implmnt
56 | # Tue Dec 12 13:19:59 2017
57 | Copied /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/synwork/ann_vhdl_m.srm to /home/gabriel/ann-vhdl/fpga/lattice/ann_vhdl/ann_vhdl_Implmnt/ann_vhdl.srm
58 | 
59 | fpga_mapper completed with warnings
60 | # Tue Dec 12 13:21:49 2017
61 | 
62 | Return Code: 1
63 | Run Time:00h:01m:50s
64 | Complete: Map on ann_vhdl_syn|ann_vhdl_Implmnt
65 | Complete: Logic Synthesis on ann_vhdl_syn|ann_vhdl_Implmnt
66 | 
67 | ================================Application terminated by Ctrl-C
68 | 
69 | 


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/fpga/lattice/ann_vhdl/synlog.tcl:
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1 | project -load ann_vhdl_syn.prj
2 | project -run synthesis 
3 | 


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/fpga/xilinx/ann-vhdl/act_func_isim_beh.exe:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/act_func_isim_beh.exe


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/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.exe:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.exe


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/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.wdb:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.wdb


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/fpga/xilinx/ann-vhdl/fuse.log:
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 1 | Running: /home/gabriel/.Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.exe -prj /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_beh.prj work.act_func_tb 
 2 | ISim P.20131013 (signature 0xfbc00daa)
 3 | Number of CPUs detected in this system: 4
 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 8 
 5 | Determining compilation order of HDL files
 6 | Parsing VHDL file "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/../../../src/types.vhd" into library work
 7 | Parsing VHDL file "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/../../../src/act_func.vhd" into library work
 8 | Parsing VHDL file "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/../../../src/act_func_tb.vhd" into library work
 9 | Starting static elaboration
10 | Completed static elaboration
11 | Fuse Memory Usage: 101280 KB
12 | Fuse CPU Usage: 4500 ms
13 | Compiling package standard
14 | Compiling package std_logic_1164
15 | Compiling package numeric_std
16 | Compiling package textio
17 | Compiling package std_logic_textio
18 | Compiling package fixed_float_types
19 | Compiling package math_real
20 | Compiling package fixed_pkg
21 | Compiling package types
22 | Compiling architecture tanh of entity act_func [act_func_default]
23 | Compiling architecture tb of entity act_func_tb
24 | Time Resolution for simulation is 1ps.
25 | Compiled 12 VHDL Units
26 | Built simulation executable /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.exe
27 | Fuse Memory Usage: 699632 KB
28 | Fuse CPU Usage: 5040 ms
29 | GCC CPU Usage: 610 ms
30 | 


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/fpga/xilinx/ann-vhdl/fuse.xmsgs:
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 1 | 
 2 | 
 7 | 
 8 | 
 9 | 
10 | 


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/fpga/xilinx/ann-vhdl/fuseRelaunch.cmd:
--------------------------------------------------------------------------------
1 | -intstyle "ise" -incremental -lib "secureip" -o "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.exe" -prj "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_beh.prj" "work.act_func_tb" 
2 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/coregen.cgp:
--------------------------------------------------------------------------------
 1 | # Date: Mon Mar 19 05:19:09 2018
 2 | 
 3 | SET addpads = false
 4 | SET asysymbol = true
 5 | SET busformat = BusFormatAngleBracketNotRipped
 6 | SET createndf = false
 7 | SET designentry = VHDL
 8 | SET device = xc6slx16
 9 | SET devicefamily = spartan6
10 | SET flowvendor = Other
11 | SET formalverification = false
12 | SET foundationsym = false
13 | SET implementationfiletype = Ngc
14 | SET package = csg324
15 | SET removerpms = false
16 | SET simulationfiles = Behavioral
17 | SET speedgrade = -3
18 | SET verilogsim = false
19 | SET vhdlsim = true
20 | SET workingdirectory = ./tmp/
21 | 
22 | # CRC: 228a2e80
23 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/coregen.log:
--------------------------------------------------------------------------------
 1 | Welcome to Xilinx CORE Generator.
 2 | Help system initialized.
 3 | The IP Catalog has been reloaded.
 4 | Wrote CGP file for project 'coregen'.
 5 | Customize and GenerateINFO:sim:172 - Generating IP...
 6 | Applying current project options...
 7 | Finished applying current project options.
 8 | Resolving generics for 'dist_mem_gen_v7_2'...
 9 | Applying external generics to 'dist_mem_gen_v7_2'...
10 | Delivering associated files for 'dist_mem_gen_v7_2'...
11 | Delivering EJava files for 'dist_mem_gen_v7_2'...
12 | Generating implementation netlist for 'dist_mem_gen_v7_2'...
13 | INFO:sim - Pre-processing HDL files for 'dist_mem_gen_v7_2'...
14 | Running synthesis for 'dist_mem_gen_v7_2'
15 | Running ngcbuild...
16 | Writing VHO instantiation template for 'dist_mem_gen_v7_2'...
17 | Writing VHDL behavioral simulation model for 'dist_mem_gen_v7_2'...
18 | WARNING:sim - Overwriting existing file
19 |    /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v
20 |    7_2/doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation
21 | Delivered 2 files into directory
22 | /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_2
23 | Generating ASY schematic symbol...
24 | INFO:sim:949 - Finished generation of ASY schematic symbol.
25 | Generating metadata file...
26 | Generating ISE project file for 'dist_mem_gen_v7_2'...
27 | Generating ISE project...
28 | XCO file found: dist_mem_gen_v7_2.xco
29 | XMDF file found: dist_mem_gen_v7_2_xmdf.tcl
30 | Adding
31 | /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_2
32 | .asy -view all -origin_type imported
33 | Adding
34 | /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_2
35 | .ngc -view all -origin_type created
36 | Checking file
37 | "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_
38 | 2.ngc" for project device match ...
39 | File
40 | "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_
41 | 2.ngc" device information matches project device.
42 | Adding
43 | /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_2
44 | .vhd -view all -origin_type created
45 | INFO:HDLCompiler:1061 - Parsing VHDL file
46 |    "/home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_
47 |    v7_2.vhd" into library work
48 | INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
49 | Adding
50 | /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/ipcore_dir/tmp/_cg/dist_mem_gen_v7_2
51 | .vho -view all -origin_type imported
52 | INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
53 |    Please set the new top explicitly by running the "project set top" command.
54 |    To re-calculate the new top automatically, set the "Auto Implementation Top"
55 |    property to true.
56 | Top level has been set to "/dist_mem_gen_v7_2"
57 | Generating README file...
58 | Generating FLIST file...
59 | INFO:sim:948 - Finished FLIST file generation.
60 | Launching README viewer...
61 | Moving files to output directory...
62 | Finished moving files to output directory
63 | Saved CGP file for project 'coregen'.
64 | Recustomize and Generate (Under Original Project Settings)INFO:sim:172 - Generating IP...
65 | Cancelled executing Tcl generator.
66 | Closed project file.
67 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2.asy:
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 1 | Version 4
 2 | SymbolType BLOCK
 3 | TEXT 32 32 LEFT 4 dist_mem_gen_v7_2
 4 | RECTANGLE Normal 32 32 256 544
 5 | LINE Wide 0 80 32 80
 6 | PIN 0 80 LEFT 36
 7 | PINATTR PinName a[5:0]
 8 | PINATTR Polarity IN
 9 | LINE Wide 288 80 256 80
10 | PIN 288 80 RIGHT 36
11 | PINATTR PinName spo[15:0]
12 | PINATTR Polarity OUT
13 | 
14 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2.vhd:
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  1 | --------------------------------------------------------------------------------
  2 | --    This file is owned and controlled by Xilinx and must be used solely     --
  3 | --    for design, simulation, implementation and creation of design files     --
  4 | --    limited to Xilinx devices or technologies. Use with non-Xilinx          --
  5 | --    devices or technologies is expressly prohibited and immediately         --
  6 | --    terminates your license.                                                --
  7 | --                                                                            --
  8 | --    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
  9 | --    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
 10 | --    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
 11 | --    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
 12 | --    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
 13 | --    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
 14 | --    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
 15 | --    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
 16 | --    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
 17 | --    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
 18 | --    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
 19 | --    PARTICULAR PURPOSE.                                                     --
 20 | --                                                                            --
 21 | --    Xilinx products are not intended for use in life support appliances,    --
 22 | --    devices, or systems.  Use in such applications are expressly            --
 23 | --    prohibited.                                                             --
 24 | --                                                                            --
 25 | --    (c) Copyright 1995-2018 Xilinx, Inc.                                    --
 26 | --    All rights reserved.                                                    --
 27 | --------------------------------------------------------------------------------
 28 | --------------------------------------------------------------------------------
 29 | -- You must compile the wrapper file dist_mem_gen_v7_2.vhd when simulating
 30 | -- the core, dist_mem_gen_v7_2. When compiling the wrapper file, be sure to
 31 | -- reference the XilinxCoreLib VHDL simulation library. For detailed
 32 | -- instructions, please refer to the "CORE Generator Help".
 33 | 
 34 | -- The synthesis directives "translate_off/translate_on" specified
 35 | -- below are supported by Xilinx, Mentor Graphics and Synplicity
 36 | -- synthesis tools. Ensure they are correct for your synthesis tool(s).
 37 | 
 38 | LIBRARY ieee;
 39 | USE ieee.std_logic_1164.ALL;
 40 | -- synthesis translate_off
 41 | LIBRARY XilinxCoreLib;
 42 | -- synthesis translate_on
 43 | ENTITY dist_mem_gen_v7_2 IS
 44 |   PORT (
 45 |     a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
 46 |     spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
 47 |   );
 48 | END dist_mem_gen_v7_2;
 49 | 
 50 | ARCHITECTURE dist_mem_gen_v7_2_a OF dist_mem_gen_v7_2 IS
 51 | -- synthesis translate_off
 52 | COMPONENT wrapped_dist_mem_gen_v7_2
 53 |   PORT (
 54 |     a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
 55 |     spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
 56 |   );
 57 | END COMPONENT;
 58 | 
 59 | -- Configuration specification
 60 |   FOR ALL : wrapped_dist_mem_gen_v7_2 USE ENTITY XilinxCoreLib.dist_mem_gen_v7_2(behavioral)
 61 |     GENERIC MAP (
 62 |       c_addr_width => 6,
 63 |       c_default_data => "0",
 64 |       c_depth => 64,
 65 |       c_family => "spartan6",
 66 |       c_has_clk => 0,
 67 |       c_has_d => 0,
 68 |       c_has_dpo => 0,
 69 |       c_has_dpra => 0,
 70 |       c_has_i_ce => 0,
 71 |       c_has_qdpo => 0,
 72 |       c_has_qdpo_ce => 0,
 73 |       c_has_qdpo_clk => 0,
 74 |       c_has_qdpo_rst => 0,
 75 |       c_has_qdpo_srst => 0,
 76 |       c_has_qspo => 0,
 77 |       c_has_qspo_ce => 0,
 78 |       c_has_qspo_rst => 0,
 79 |       c_has_qspo_srst => 0,
 80 |       c_has_spo => 1,
 81 |       c_has_spra => 0,
 82 |       c_has_we => 0,
 83 |       c_mem_init_file => "no_coe_file_loaded",
 84 |       c_mem_type => 0,
 85 |       c_parser_type => 1,
 86 |       c_pipeline_stages => 0,
 87 |       c_qce_joined => 0,
 88 |       c_qualify_we => 0,
 89 |       c_read_mif => 0,
 90 |       c_reg_a_d_inputs => 0,
 91 |       c_reg_dpra_input => 0,
 92 |       c_sync_enable => 1,
 93 |       c_width => 16
 94 |     );
 95 | -- synthesis translate_on
 96 | BEGIN
 97 | -- synthesis translate_off
 98 | U0 : wrapped_dist_mem_gen_v7_2
 99 |   PORT MAP (
100 |     a => a,
101 |     spo => spo
102 |   );
103 | -- synthesis translate_on
104 | 
105 | END dist_mem_gen_v7_2_a;
106 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2.vho:
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 1 | --------------------------------------------------------------------------------
 2 | --    This file is owned and controlled by Xilinx and must be used solely     --
 3 | --    for design, simulation, implementation and creation of design files     --
 4 | --    limited to Xilinx devices or technologies. Use with non-Xilinx          --
 5 | --    devices or technologies is expressly prohibited and immediately         --
 6 | --    terminates your license.                                                --
 7 | --                                                                            --
 8 | --    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
 9 | --    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
10 | --    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
11 | --    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
12 | --    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
13 | --    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
14 | --    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
15 | --    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
16 | --    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
17 | --    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
18 | --    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
19 | --    PARTICULAR PURPOSE.                                                     --
20 | --                                                                            --
21 | --    Xilinx products are not intended for use in life support appliances,    --
22 | --    devices, or systems.  Use in such applications are expressly            --
23 | --    prohibited.                                                             --
24 | --                                                                            --
25 | --    (c) Copyright 1995-2018 Xilinx, Inc.                                    --
26 | --    All rights reserved.                                                    --
27 | --------------------------------------------------------------------------------
28 | 
29 | --------------------------------------------------------------------------------
30 | --    Generated from core with identifier: xilinx.com:ip:dist_mem_gen:7.2     --
31 | --                                                                            --
32 | --    Rev 1. The LogiCORE Xilinx Distributed Memory Generator creates area    --
33 | --    and performance optimized ROM blocks, single and dual port              --
34 | --    distributed memories, and SRL16-based memories for Xilinx FPGAs. The    --
35 | --    core supersedes the previously released LogiCORE Distributed Memory     --
36 | --    core. Use this core in all new designs for supported families           --
37 | --    wherever a distributed memory is required.                              --
38 | --------------------------------------------------------------------------------
39 | 
40 | -- The following code must appear in the VHDL architecture header:
41 | 
42 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
43 | COMPONENT dist_mem_gen_v7_2
44 |   PORT (
45 |     a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
46 |     spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
47 |   );
48 | END COMPONENT;
49 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------
50 | 
51 | -- The following code must appear in the VHDL architecture
52 | -- body. Substitute your own instance name and net names.
53 | 
54 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
55 | your_instance_name : dist_mem_gen_v7_2
56 |   PORT MAP (
57 |     a => a,
58 |     spo => spo
59 |   );
60 | -- INST_TAG_END ------ End INSTANTIATION Template ------------
61 | 
62 | -- You must compile the wrapper file dist_mem_gen_v7_2.vhd when simulating
63 | -- the core, dist_mem_gen_v7_2. When compiling the wrapper file, be sure to
64 | -- reference the XilinxCoreLib VHDL simulation library. For detailed
65 | -- instructions, please refer to the "CORE Generator Help".
66 | 
67 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2.xco:
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 1 | ##############################################################
 2 | #
 3 | # Xilinx Core Generator version 14.7
 4 | # Date: Mon Mar 19 05:21:19 2018
 5 | #
 6 | ##############################################################
 7 | #
 8 | #  This file contains the customisation parameters for a
 9 | #  Xilinx CORE Generator IP GUI. It is strongly recommended
10 | #  that you do not manually alter this file as it may cause
11 | #  unexpected and unsupported behavior.
12 | #
13 | ##############################################################
14 | #
15 | #  Generated from component: xilinx.com:ip:dist_mem_gen:7.2
16 | #
17 | ##############################################################
18 | #
19 | # BEGIN Project Options
20 | SET addpads = false
21 | SET asysymbol = true
22 | SET busformat = BusFormatAngleBracketNotRipped
23 | SET createndf = false
24 | SET designentry = VHDL
25 | SET device = xc6slx16
26 | SET devicefamily = spartan6
27 | SET flowvendor = Other
28 | SET formalverification = false
29 | SET foundationsym = false
30 | SET implementationfiletype = Ngc
31 | SET package = csg324
32 | SET removerpms = false
33 | SET simulationfiles = Behavioral
34 | SET speedgrade = -3
35 | SET verilogsim = false
36 | SET vhdlsim = true
37 | # END Project Options
38 | # BEGIN Select
39 | SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
40 | # END Select
41 | # BEGIN Parameters
42 | CSET ce_overrides=ce_overrides_sync_controls
43 | CSET coefficient_file=no_coe_file_loaded
44 | CSET common_output_ce=false
45 | CSET common_output_clk=false
46 | CSET component_name=dist_mem_gen_v7_2
47 | CSET data_width=16
48 | CSET default_data=0
49 | CSET default_data_radix=16
50 | CSET depth=64
51 | CSET dual_port_address=non_registered
52 | CSET dual_port_output_clock_enable=false
53 | CSET input_clock_enable=false
54 | CSET input_options=non_registered
55 | CSET memory_type=rom
56 | CSET output_options=non_registered
57 | CSET pipeline_stages=0
58 | CSET qualify_we_with_i_ce=false
59 | CSET reset_qdpo=false
60 | CSET reset_qsdpo=false
61 | CSET reset_qspo=false
62 | CSET simple_dual_port_address=non_registered
63 | CSET simple_dual_port_output_clock_enable=false
64 | CSET single_port_output_clock_enable=false
65 | CSET sync_reset_qdpo=false
66 | CSET sync_reset_qsdpo=false
67 | CSET sync_reset_qspo=false
68 | # END Parameters
69 | # BEGIN Extra information
70 | MISC pkg_timestamp=2012-11-21T20:07:40Z
71 | # END Extra information
72 | GENERATE
73 | # CRC: 510ab359
74 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2/dist_mem_gen_v7_2_readme.txt:
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  1 | CHANGE LOG for LogiCORE Distributed Memory Generator V7.2 Rev 1
  2 | 
  3 |                     Release Date: December 18, 2012
  4 | --------------------------------------------------------------------------------
  5 | 
  6 | Table of Contents
  7 | 
  8 | 1. INTRODUCTION 
  9 | 2. DEVICE SUPPORT    
 10 | 3. NEW FEATURE HISTORY   
 11 | 4. RESOLVED ISSUES 
 12 | 5. KNOWN ISSUES & LIMITATIONS 
 13 | 6. TECHNICAL SUPPORT & FEEDBACK
 14 | 7. CORE RELEASE HISTORY 
 15 | 8. LEGAL DISCLAIMER 
 16 | 
 17 | --------------------------------------------------------------------------------  
 18 | 
 19 | 
 20 | 1. INTRODUCTION
 21 | 
 22 | For installation instructions for this release, please go to:
 23 | 
 24 |   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
 25 | 
 26 | For system requirements:
 27 | 
 28 |    http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
 29 | 
 30 | This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator v7.2 Rev 1
 31 | solution. For the latest core updates, see the product page at:
 32 | 
 33 |    http://www.xilinx.com/products/ipcenter/DIST_MEM_GEN.htm
 34 | 
 35 | ................................................................................
 36 | 
 37 | 
 38 | 2. DEVICE SUPPORT
 39 | 
 40 | 
 41 |   2.1 ISE 
 42 | 
 43 |     The following device families are supported by the core for this release.
 44 | 
 45 | 
 46 |     All 7 Series devices
 47 |     Zynq-7000 devices
 48 |     All Virtex-6 devices
 49 |     All Spartan-6 devices
 50 |     All Virtex-5 devices
 51 |     All Spartan-3 devices
 52 |     All Virtex-4 devices
 53 | 
 54 | 
 55 |   2.2 Vivado 
 56 | 
 57 |     All 7 Series devices
 58 |     Zynq-7000 devices
 59 | 
 60 | ................................................................................
 61 | 
 62 | 
 63 | 3. NEW FEATURE HISTORY
 64 | 
 65 | 
 66 |   3.1 ISE 
 67 |   
 68 |     - ISE 14.4 software support
 69 | 
 70 | 
 71 |   3.2 Vivado
 72 |   
 73 |     - 2012.4 software support
 74 | 
 75 | ................................................................................
 76 | 
 77 | 
 78 | 4. RESOLVED ISSUES
 79 | 
 80 | 
 81 |   4.1 ISE 
 82 | 
 83 |     - N/A
 84 | 
 85 | 
 86 |   4.2 Vivado 
 87 | 
 88 |     - N/A
 89 | 
 90 | 
 91 | ................................................................................
 92 | 
 93 | 5. KNOWN ISSUES & LIMITATIONS
 94 | 
 95 | 
 96 |   5.1 ISE 
 97 | 
 98 |     There are not known issues for v7.2 Rev 1 of this core at time of release:
 99 | 
100 |   5.2 Vivado 
101 | 
102 |     The following are known issues for v7.2 Rev 1 of this core at time of release:
103 |      
104 |     1. Description: When Trying to upgrade to latest version of DMG from older verions, following error message is seen 
105 |        ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
106 |       
107 |        CR 665836 
108 | 
109 | The most recent information, including known issues, workarounds, and
110 | resolutions for this version is provided in the IP Release Notes Guide
111 | located at
112 | 
113 |    www.xilinx.com/support/documentation/user_guides/xtp025.pdf
114 | 
115 | ................................................................................
116 | 
117 | 
118 | 6. TECHNICAL SUPPORT & FEEDBACK
119 | 
120 | 
121 | To obtain technical support, create a WebCase at www.xilinx.com/support.
122 | Questions are routed to a team with expertise using this product.
123 | 
124 | Xilinx provides technical support for use of this product when used
125 | according to the guidelines described in the core documentation, and
126 | cannot guarantee timing, functionality, or support of this product for
127 | designs that do not follow specified guidelines.
128 | 
129 | ................................................................................
130 | 
131 | 
132 | 7. CORE RELEASE HISTORY
133 | 
134 | 
135 | Date        By            Version      Description
136 | ================================================================================
137 | 12/18/2012  Xilinx, Inc.  7.2 Rev 1    ISE 14.4 and Vivado 2012.4 support
138 | 07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support; Example test bench support
139 | 04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
140 | 01/18/2012  Xilinx, Inc.  6.3          ISE 13.4 support; Artix-7L and Automotive Artix-7 device support
141 | 06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
142 | 03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support
143 | 04/19/2010  Xilinx, Inc.  5.1          ISE 12.1 support
144 | 12/02/2009  Xilinx, Inc.  4.3          ISE 11.4 support; Spartan-6 Lower Power and Automotive Spartan-6 device support
145 | 09/16/2009  Xilinx, Inc.  4.2          11.3 support; Virtex-6 Lower Power and Virtex-6 HXT device support
146 | 06/24/2009  Xilinx, Inc.  4.1.1        11.2 support; Virtex-6 CXT device support
147 | 04/24/2009  Xilinx, Inc.  4.1          11.1 support; Revised to v4.1; Virtex-6 and Spartan-6 support
148 | 03/24/2008  Xilinx, Inc.  3.4          10.1 support; Revised to v3.4.
149 | 04/02/2007  Xilinx, Inc.  3.3          9.1i support; Revised to v3.3; Spartan-3AN and Spartan-3A DSP support
150 | 09/21/2006  Xilinx, Inc.  3.2          8.2i support; Revised to v3.2; Spartan-3A support
151 | 07/13/2006  Xilinx, Inc.  3.1          8.2i support; Revised to v3.1
152 | 01/18/2006  Xilinx, Inc.  2.1          8.1i support; Revised to v2.1
153 | 04/28/2005  Xilinx, Inc.  1.1          7.1i Service Pack 1 support; First release
154 | ================================================================================
155 | 
156 | ................................................................................
157 | 
158 | 
159 | 8. LEGAL DISCLAIMER
160 | 
161 | (c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
162 | 
163 |   This file contains confidential and proprietary information
164 |   of Xilinx, Inc. and is protected under U.S. and
165 |   international copyright and other intellectual property
166 |   laws.
167 | 
168 |   DISCLAIMER
169 |   This disclaimer is not a license and does not grant any
170 |   rights to the materials distributed herewith. Except as
171 |   otherwise provided in a valid license issued to you by
172 |   Xilinx, and to the maximum extent permitted by applicable
173 |   law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
174 |   WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
175 |   AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
176 |   BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
177 |   INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
178 |   (2) Xilinx shall not be liable (whether in contract or tort,
179 |   including negligence, or under any other theory of
180 |   liability) for any loss or damage of any kind or nature
181 |   related to, arising under or in connection with these
182 |   materials, including for any direct, or any indirect,
183 |   special, incidental, or consequential loss or damage
184 |   (including loss of data, profits, goodwill, or any type of
185 |   loss or damage suffered as a result of any action brought
186 |   by a third party) even if such damage or loss was
187 |   reasonably foreseeable or Xilinx had been advised of the
188 |   possibility of the same. 
189 | 
190 |   CRITICAL APPLICATIONS
191 |   Xilinx products are not designed or intended to be fail-
192 |   safe, or for use in any application requiring fail-safe
193 |   performance, such as life-support or safety devices or
194 |   systems, Class III medical devices, nuclear facilities,
195 |   applications related to the deployment of airbags, or any
196 |   other applications that could lead to death, personal
197 |   injury, or severe property or environmental damage
198 |   (individually and collectively, "Critical 
199 |   Applications"). Customer assumes the sole risk and 
200 |   liability of any use of Xilinx products in Critical 
201 |   Applications, subject only to applicable laws and 
202 |   regulations governing limitations on product liability. 
203 |  
204 |   THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
205 |   PART OF THIS FILE AT ALL TIMES.
206 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2/doc/pg063-dist-mem-gen.pdf:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2/doc/pg063-dist-mem-gen.pdf


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2_flist.txt:
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 1 | # Output products list for 
 2 | dist_mem_gen_v7_2/dist_mem_gen_v7_2_readme.txt
 3 | dist_mem_gen_v7_2/doc/dist_mem_gen_v7_2_vinfo.html
 4 | dist_mem_gen_v7_2/doc/pg063-dist-mem-gen.pdf
 5 | dist_mem_gen_v7_2.asy
 6 | dist_mem_gen_v7_2.gise
 7 | dist_mem_gen_v7_2.ngc
 8 | dist_mem_gen_v7_2.vhd
 9 | dist_mem_gen_v7_2.vho
10 | dist_mem_gen_v7_2.xco
11 | dist_mem_gen_v7_2.xise
12 | dist_mem_gen_v7_2_flist.txt
13 | dist_mem_gen_v7_2_xmdf.tcl
14 | 


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/fpga/xilinx/ann-vhdl/ipcore_dir/dist_mem_gen_v7_2_xmdf.tcl:
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 1 | # The package naming convention is _xmdf
 2 | package provide dist_mem_gen_v7_2_xmdf 1.0
 3 | 
 4 | # This includes some utilities that support common XMDF operations
 5 | package require utilities_xmdf
 6 | 
 7 | # Define a namespace for this package. The name of the name space
 8 | # is _xmdf
 9 | namespace eval ::dist_mem_gen_v7_2_xmdf {
10 | # Use this to define any statics
11 | }
12 | 
13 | # Function called by client to rebuild the params and port arrays
14 | # Optional when the use context does not require the param or ports
15 | # arrays to be available.
16 | proc ::dist_mem_gen_v7_2_xmdf::xmdfInit { instance } {
17 | # Variable containing name of library into which module is compiled
18 | # Recommendation: 
19 | # Required
20 | utilities_xmdf::xmdfSetData $instance Module Attributes Name dist_mem_gen_v7_2
21 | }
22 | # ::dist_mem_gen_v7_2_xmdf::xmdfInit
23 | 
24 | # Function called by client to fill in all the xmdf* data variables
25 | # based on the current settings of the parameters
26 | proc ::dist_mem_gen_v7_2_xmdf::xmdfApplyParams { instance } {
27 | 
28 | set fcount 0
29 | # Array containing libraries that are assumed to exist
30 | # Examples include unisim and xilinxcorelib
31 | # Optional
32 | # In this example, we assume that the unisim library will
33 | # be available to the simulation and synthesis tool
34 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
35 | utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
36 | incr fcount
37 | 
38 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2/dist_mem_gen_v7_2_readme.txt
39 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
40 | incr fcount
41 | 
42 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2/doc/dist_mem_gen_v7_2_vinfo.html
43 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
44 | incr fcount
45 | 
46 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2/doc/pg063-dist-mem-gen.pdf
47 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
48 | incr fcount
49 | 
50 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2.asy
51 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
52 | incr fcount
53 | 
54 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2.ngc
55 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
56 | incr fcount
57 | 
58 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2.vhd
59 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
60 | incr fcount
61 | 
62 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2.vho
63 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
64 | incr fcount
65 | 
66 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2.xco
67 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
68 | incr fcount
69 | 
70 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path dist_mem_gen_v7_2_xmdf.tcl
71 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
72 | incr fcount
73 | 
74 | utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module dist_mem_gen_v7_2
75 | incr fcount
76 | 
77 | }
78 | 
79 | # ::gen_comp_name_xmdf::xmdfApplyParams
80 | 


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/fpga/xilinx/ann-vhdl/isim.cmd:
--------------------------------------------------------------------------------
1 | onerror {resume}
2 | wave add /
3 | run 1000 ns;
4 | 


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/fpga/xilinx/ann-vhdl/isim.log:
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 1 | ISim log file
 2 | Running: /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/gabriel/ann-vhdl/fpga/xilinx/ann-vhdl/act_func_tb_isim_beh.wdb 
 3 | ISim P.20131013 (signature 0xfbc00daa)
 4 | WARNING: A WEBPACK license was found.
 5 | WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 6 | WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 7 | This is a Lite version of ISim.
 8 | Time resolution is 1 ps
 9 | # onerror resume
10 | # wave add /
11 | # run 1000 ns
12 | Simulator is doing circuit initialization process.
13 | Finished circuit initialization process.
14 | # run 1.00us
15 | # run 1.00us
16 | # exit 0
17 | 


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/act_func_tb_isim_beh.exe


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/isimcrash.log


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/isimkernel.log:
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 1 | Command line:
 2 |    act_func_tb_isim_beh.exe
 3 |      -simmode  gui
 4 |      -simrunnum  0
 5 |      -socket  46097
 6 | 
 7 | Sun May  6 22:30:04 2018
 8 | 
 9 | 
10 |  Elaboration Time: 0.02 sec
11 | 
12 |  Current Memory Usage: 196.604 Meg
13 | 
14 |  Total Signals          : 12
15 |  Total Nets             : 197
16 |  Total Signal Drivers   : 9
17 |  Total Blocks           : 10
18 |  Total Primitive Blocks : 9
19 |  Total Processes        : 9
20 |  Total Traceable Variables  : 64
21 |  Total Scalar Nets and Variables : 3983
22 | Total Line Count : 21
23 | 
24 |  Total Simulation Time: 0.07 sec
25 | 
26 |  Current Memory Usage: 272.105 Meg
27 | 
28 | Sun May  6 22:30:35 2018
29 | 
30 | 


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/a_2599789339_3671711236.didat


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/a_2599789339_3671711236.lin64.o:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/a_2599789339_3671711236.lin64.o


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/a_4019868472_2587733704.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/a_4019868472_2587733704.didat


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/a_4019868472_2587733704.lin64.o


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/act_func_tb_isim_beh.exe_main.c:
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 1 | /**********************************************************************/
 2 | /*   ____  ____                                                       */
 3 | /*  /   /\/   /                                                       */
 4 | /* /___/  \  /                                                        */
 5 | /* \   \   \/                                                       */
 6 | /*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
 7 | /*  /   /          All Right Reserved.                                 */
 8 | /* /---/   /\                                                         */
 9 | /* \   \  /  \                                                      */
10 | /*  \___\/\___\                                                    */
11 | /***********************************************************************/
12 | 
13 | #include "xsi.h"
14 | 
15 | struct XSI_INFO xsi_info;
16 | 
17 | char *WORK_P_1475539293;
18 | char *IEEE_P_1242562249;
19 | char *IEEE_P_2592010699;
20 | char *STD_STANDARD;
21 | char *IEEE_PROPOSED_P_0892474878;
22 | char *STD_TEXTIO;
23 | char *IEEE_P_3972351953;
24 | char *IEEE_PROPOSED_P_2011092313;
25 | char *IEEE_P_3564397177;
26 | 
27 | 
28 | int main(int argc, char **argv)
29 | {
30 |     xsi_init_design(argc, argv);
31 |     xsi_register_info(&xsi_info);
32 | 
33 |     xsi_register_min_prec_unit(-12);
34 |     ieee_p_2592010699_init();
35 |     ieee_p_1242562249_init();
36 |     std_textio_init();
37 |     ieee_p_3564397177_init();
38 |     ieee_proposed_p_2011092313_init();
39 |     ieee_p_3972351953_init();
40 |     ieee_proposed_p_0892474878_init();
41 |     work_p_1475539293_init();
42 |     work_a_4019868472_2587733704_init();
43 |     work_a_2599789339_3671711236_init();
44 | 
45 | 
46 |     xsi_register_tops("work_a_2599789339_3671711236");
47 | 
48 |     WORK_P_1475539293 = xsi_get_engine_memory("work_p_1475539293");
49 |     IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
50 |     IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
51 |     xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
52 |     STD_STANDARD = xsi_get_engine_memory("std_standard");
53 |     IEEE_PROPOSED_P_0892474878 = xsi_get_engine_memory("ieee_proposed_p_0892474878");
54 |     STD_TEXTIO = xsi_get_engine_memory("std_textio");
55 |     IEEE_P_3972351953 = xsi_get_engine_memory("ieee_p_3972351953");
56 |     IEEE_PROPOSED_P_2011092313 = xsi_get_engine_memory("ieee_proposed_p_2011092313");
57 |     IEEE_P_3564397177 = xsi_get_engine_memory("ieee_p_3564397177");
58 | 
59 |     return xsi_run_simulation(argc, argv);
60 | 
61 | }
62 | 


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/act_func_tb_isim_beh.exe_main.lin64.o


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/p_1475539293.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/p_1475539293.didat


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/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/p_1475539293.lin64.o:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/act_func_tb_isim_beh.exe.sim/work/p_1475539293.lin64.o


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/fpga/xilinx/ann-vhdl/isim/lockfile:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/lockfile


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/fpga/xilinx/ann-vhdl/isim/pn_info:
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1 | 14.7
2 | 


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_1242562249.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_1242562249.didat


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_1242562249.lin64.o:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_1242562249.lin64.o


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_2592010699.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_2592010699.didat


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3564397177.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3564397177.didat


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3564397177.lin64.o:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3564397177.lin64.o


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3972351953.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3972351953.didat


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3972351953.lin64.o:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee/p_3972351953.lin64.o


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_0892474878.didat:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_0892474878.didat


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_0892474878.lin64.o:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_0892474878.lin64.o


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_2011092313.c:
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 1 | /**********************************************************************/
 2 | /*   ____  ____                                                       */
 3 | /*  /   /\/   /                                                       */
 4 | /* /___/  \  /                                                        */
 5 | /* \   \   \/                                                       */
 6 | /*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
 7 | /*  /   /          All Right Reserved.                                 */
 8 | /* /---/   /\                                                         */
 9 | /* \   \  /  \                                                      */
10 | /*  \___\/\___\                                                    */
11 | /***********************************************************************/
12 | 
13 | /* This file is designed for use with ISim build 0xfbc00daa */
14 | 
15 | #define XSI_HIDE_SYMBOL_SPEC true
16 | #include "xsi.h"
17 | #include 
18 | #ifdef __GNUC__
19 | #include 
20 | #else
21 | #include 
22 | #define alloca _alloca
23 | #endif
24 | 
25 | 
26 | 
27 | 
28 | extern void ieee_proposed_p_2011092313_init()
29 | {
30 | 	xsi_register_didat("ieee_proposed_p_2011092313", "isim/precompiled.exe.sim/ieee_proposed/p_2011092313.didat");
31 | }
32 | 


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_2011092313.didat


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/ieee_proposed/p_2011092313.lin64.o


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/fpga/xilinx/ann-vhdl/isim/precompiled.exe.sim/std/textio.c:
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 1 | /**********************************************************************/
 2 | /*   ____  ____                                                       */
 3 | /*  /   /\/   /                                                       */
 4 | /* /___/  \  /                                                        */
 5 | /* \   \   \/                                                       */
 6 | /*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
 7 | /*  /   /          All Right Reserved.                                 */
 8 | /* /---/   /\                                                         */
 9 | /* \   \  /  \                                                      */
10 | /*  \___\/\___\                                                    */
11 | /***********************************************************************/
12 | 
13 | /* This file is designed for use with ISim build 0xfbc00daa */
14 | 
15 | #define XSI_HIDE_SYMBOL_SPEC true
16 | #include "xsi.h"
17 | #include 
18 | #ifdef __GNUC__
19 | #include 
20 | #else
21 | #include 
22 | #define alloca _alloca
23 | #endif
24 | 
25 | 
26 | 
27 | 
28 | extern void std_textio_init()
29 | {
30 | 	xsi_register_didat("std_textio", "isim/precompiled.exe.sim/std/textio.didat");
31 | }
32 | 


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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/temp/act_func.vdb


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/fpga/xilinx/ann-vhdl/isim/work/act_func.vdb:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/work/act_func.vdb


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/fpga/xilinx/ann-vhdl/isim/work/act_func_tb.vdb:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/work/act_func_tb.vdb


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/fpga/xilinx/ann-vhdl/isim/work/types.vdb:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/isim/work/types.vdb


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/fpga/xilinx/ann-vhdl/network_test_tb_isim_beh1.wdb:
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/fpga/xilinx/ann-vhdl/network_test_tb_isim_beh2.wdb:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/network_test_tb_isim_beh2.wdb


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/fpga/xilinx/ann-vhdl/neuron_tb_isim_beh.exe:
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https://raw.githubusercontent.com/gabrieljcs/ann-vhdl/79668c06a5d2ffb8c192f79b916e0dbc6eec55cd/fpga/xilinx/ann-vhdl/neuron_tb_isim_beh.exe


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/fpga/xilinx/ann-vhdl/neuron_tb_isim_beh.wdb:
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/fpga/xilinx/ann-vhdl/xilinxsim.ini:
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1 | work=isim/work
2 | 


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/ide/.library_mapping.xml:
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 1 | 
 2 | 
 3 |   
 4 |   
 5 |   
 6 |   
 7 |   
 8 |   
 9 | 
10 | 


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/ide/.project:
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 1 | 
 2 | 
 3 | 	sigasi
 4 | 	
 5 | 	
 6 | 	
 7 | 	
 8 | 		
 9 | 			org.eclipse.xtext.ui.shared.xtextBuilder
10 | 			
11 | 			
12 | 		
13 | 	
14 | 	
15 | 		com.sigasi.hdt.vhdl.ui.vhdlNature
16 | 		org.eclipse.xtext.ui.shared.xtextNature
17 | 	
18 | 	
19 | 		
20 | 			Common Libraries
21 | 			2
22 | 			virtual:/virtual
23 | 		
24 | 		
25 | 			Common Libraries/IEEE
26 | 			2
27 | 			sigasiresource:/vhdl/93/IEEE
28 | 		
29 | 		
30 | 			Common Libraries/IEEE Proposed
31 | 			2
32 | 			/home/gabriel/.Xilinx/14.7/ISE_DS/ISE/vhdl/src/ieee_proposed
33 | 		
34 | 		
35 | 			Common Libraries/IEEE Synopsys
36 | 			2
37 | 			sigasiresource:/vhdl/93/IEEE%20Synopsys
38 | 		
39 | 		
40 | 			Common Libraries/STD
41 | 			2
42 | 			sigasiresource:/vhdl/93/STD
43 | 		
44 | 		
45 | 			Common Libraries/readme.txt
46 | 			1
47 | 			sigasiresource:/vhdl/readme.txt
48 | 		
49 | 	
50 | 
51 | 


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/ide/.settings/com.sigasi.hdt.vhdl.version.prefs:
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1 | =93
2 | 


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1 | eclipse.preferences.version=1
2 | encoding//Common\ Libraries/IEEE=utf-8
3 | encoding//Common\ Libraries/IEEE\ Synopsys=utf-8
4 | encoding//Common\ Libraries/STD=utf-8
5 | encoding/Common\ Libraries=utf-8
6 | 


--------------------------------------------------------------------------------
/ide/act_func.vhd:
--------------------------------------------------------------------------------
1 | ../src/act_func.vhd


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/ide/network.vhd:
--------------------------------------------------------------------------------
1 | ../src/network.vhd


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/ide/network_test.vhd:
--------------------------------------------------------------------------------
1 | ../../ann-vhdl/src/network_test.vhd


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/ide/network_test_tb.vhd:
--------------------------------------------------------------------------------
1 | ../src/network_test_tb.vhd


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/ide/neuron.vhd:
--------------------------------------------------------------------------------
1 | ../src/neuron.vhd


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/ide/types.vhd:
--------------------------------------------------------------------------------
1 | ../src/types.vhd


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/old/compile.tcl:
--------------------------------------------------------------------------------
 1 | # TCL ModelSim compile script
 2 | 
 3 | # Sets the compiler
 4 | #set compiler vlog
 5 | set compiler vcom
 6 | 
 7 | # Creates work library if it doesn't already exists
 8 | if { ![file exist work] } {
 9 | 	vlib work
10 | 	vmap work work
11 | }
12 | 
13 | #########################
14 | ### Source files list ###
15 | #########################
16 | 
17 | set sourceFiles {
18 | 	types.vhd
19 | 	act_func.vhd
20 | 	act_func_tb.vhd
21 | 	neuron.vhd
22 | 	network.vhd
23 | 	network_tb.vhd
24 | }
25 | 
26 | #set testBench Pipeline_tb
27 | 
28 | ###################
29 | ### Compilation ###
30 | ###################
31 | 
32 | if { [llength $sourceFiles] > 0 } {
33 | 	
34 | 	foreach file $sourceFiles {
35 | 		if [ catch {$compiler $file} ] {
36 | 			puts "\n*** ERROR compiling file $file :( ***" 
37 | 			return;
38 | 		}
39 | 	}
40 | }
41 | 
42 | 
43 | ################################
44 | ### Lists the compiled files ###
45 | ################################
46 | 
47 | if { [llength $sourceFiles] > 0 } {
48 | 	
49 | 	puts "\n*** Compiled files:"  
50 | 	
51 | 	foreach file $sourceFiles {
52 | 		puts \t$file
53 | 	}
54 | }
55 | 
56 | 
57 | puts "\n*** Compilation OK ;) ***"


--------------------------------------------------------------------------------
/old/interpolador_funcao_tanh.vhd:
--------------------------------------------------------------------------------
 1 | -------------------------------------------------------------------------------
 2 | -- Title      : Interpolador para a função tangente hiperbólica
 3 | -- Project    : 
 4 | -------------------------------------------------------------------------------
 5 | -- File       : interpolador_funcao_tanh.vhd
 6 | -- Author     : Giovani Baratto  
 7 | -- Company    : UFSM - CT - DELC
 8 | -- Created    : 2017-11-08
 9 | -- Last update: 2017-11-09
10 | -- Platform   : 
11 | -- Standard   : VHDL'93/02
12 | -------------------------------------------------------------------------------
13 | -- Description: Este interpolador linear calcula a tangente hiperbólica de
14 | --              entrada. Os valores de entrada e de saída estão no formato
15 | --              Q16.16, ou seja, formato em ponto fixo com 16 bits na parte
16 | --              inteira e 16 bits na parte fracionária. Os coeficientes angular
17 | --              a e linear b da interpolação, são armazenados dois vetores de
18 | --              constantes. O valor da entrada pode estar entre -3.5 a 3.5,
19 | --              aproximadamente.
20 | -------------------------------------------------------------------------------
21 | -- Copyright (c) 2017 
22 | -------------------------------------------------------------------------------
23 | -- Revisions  :
24 | -- Date        Version  Author  Description
25 | -- 2017-11-08  1.0      gfbaratto       Created
26 | -------------------------------------------------------------------------------
27 | 
28 | ------------------------------------------------------------------------------------------------------------------------
29 | library ieee;
30 | use ieee.std_logic_1164.all;
31 | use ieee.numeric_std.all;
32 | library ieee_proposed;
33 | use ieee_proposed.fixed_pkg.all;
34 | ------------------------------------------------------------------------------------------------------------------------
35 | 
36 | ------------------------------------------------------------------------------------------------------------------------
37 | entity interpolador_funcao_tanh is
38 |   port(entrada : in  sfixed(15 downto -16);   -- argumento da função 
39 |        saida   : out sfixed(15 downto -16));  -- o valor da tangente hiperbólica do argumento entrada
40 | end entity interpolador_funcao_tanh;
41 | ------------------------------------------------------------------------------------------------------------------------
42 | 
43 | ------------------------------------------------------------------------------------------------------------------------
44 | architecture simples of interpolador_funcao_tanh is
45 |   type array_sfixed is array(integer range<>) of sfixed(15 downto -16);
46 |   constant a : array_sfixed(0 to 31) := (                       -- coeficientes angulares
47 |     0  => to_sfixed(0.979675, 15, -16), 1 => to_sfixed(0.868794, 15, -16),
48 |     2  => to_sfixed(0.692127, 15, -16), 3 => to_sfixed(0.505781, 15, -16),
49 |     4  => to_sfixed(0.346758, 15, -16), 5 => to_sfixed(0.227458, 15, -16),
50 |     6  => to_sfixed(0.144909, 15, -16), 7 => to_sfixed(0.0906082, 15, -16),
51 |     8  => to_sfixed(0.0559941, 15, -16), 9 => to_sfixed(0.0343527, 15, -16),
52 |     10 => to_sfixed(0.0209817, 15, -16), 11 => to_sfixed(0.0127801, 15, -16),
53 |     12 => to_sfixed(0.00777153, 15, -16), 13 => to_sfixed(0.00472105, 15, -16),
54 |     14 => to_sfixed(0.00286618, 15, -16), 15 => to_sfixed(0.00173943, 15, -16),
55 |     16 => to_sfixed(0.00173943, 15, -16), 17 => to_sfixed(0.00286618, 15, -16),
56 |     18 => to_sfixed(0.00472105, 15, -16), 19 => to_sfixed(0.00777153, 15, -16),
57 |     20 => to_sfixed(0.0127801, 15, -16), 21 => to_sfixed(0.0209817, 15, -16),
58 |     22 => to_sfixed(0.0343527, 15, -16), 23 => to_sfixed(0.0559941, 15, -16),
59 |     24 => to_sfixed(0.0906082, 15, -16), 25 => to_sfixed(0.144909, 15, -16),
60 |     26 => to_sfixed(0.227458, 15, -16), 27 => to_sfixed(0.346758, 15, -16),
61 |     28 => to_sfixed(0.505781, 15, -16), 29 => to_sfixed(0.692127, 15, -16),
62 |     30 => to_sfixed(0.868794, 15, -16), 31 => to_sfixed(0.979675, 15, -16)
63 |     );
64 |   constant b : array_sfixed(0 to 31) := (                       -- coeficientes lineares
65 |     0  => to_sfixed(0, 15, -16), 1 => to_sfixed(0.0277202, 15, -16),
66 |     2  => to_sfixed(0.116054, 15, -16), 3 => to_sfixed(0.255813, 15, -16),
67 |     4  => to_sfixed(0.414836, 15, -16), 5 => to_sfixed(0.563961, 15, -16),
68 |     6  => to_sfixed(0.687785, 15, -16), 7 => to_sfixed(0.782811, 15, -16),
69 |     8  => to_sfixed(0.852039, 15, -16), 9 => to_sfixed(0.900732, 15, -16),
70 |     10 => to_sfixed(0.93416, 15, -16), 11 => to_sfixed(0.956714, 15, -16),
71 |     12 => to_sfixed(0.97174, 15, -16), 13 => to_sfixed(0.981654, 15, -16),
72 |     14 => to_sfixed(0.988146, 15, -16), 15 => to_sfixed(0.992372, 15, -16),
73 |     16 => to_sfixed(-0.992372, 15, -16), 17 => to_sfixed(-0.988146, 15, -16),
74 |     18 => to_sfixed(-0.981654, 15, -16), 19 => to_sfixed(-0.97174, 15, -16),
75 |     20 => to_sfixed(-0.956714, 15, -16), 21 => to_sfixed(-0.93416, 15, -16),
76 |     22 => to_sfixed(-0.900732, 15, -16), 23 => to_sfixed(-0.852039, 15, -16),
77 |     24 => to_sfixed(-0.782811, 15, -16), 25 => to_sfixed(-0.687785, 15, -16),
78 |     26 => to_sfixed(-0.563961, 15, -16), 27 => to_sfixed(-0.414836, 15, -16),
79 |     28 => to_sfixed(-0.255813, 15, -16), 29 => to_sfixed(-0.116054, 15, -16),
80 |     30 => to_sfixed(-0.0277202, 15, -16), 31 => to_sfixed(0, 15, -16)
81 |     );
82 |   signal multiplicacao : sfixed(31 downto -32);
83 |   signal soma          : sfixed(16 downto -16);
84 |   signal indice        : integer := 0;
85 | begin
86 |   --    calculamos a interpolação com a fórmula saida = a[i] * entrada + b[i].
87 |   --    para o índice i usamos 5 bits da entrada (3 bits menos significativos
88 |   --    da parte inteira e os 2 bits mais significativos da parte fracionária.
89 |   indice        <= to_integer(unsigned(entrada(2 downto -2)));  -- encontramos o índice dos coeficientes a e b
90 |   multiplicacao <= a(indice) * entrada;                         -- a[i] * entrada
91 |   soma          <= resize(multiplicacao, 15, -16) + b(indice);  -- a[i] * entrada + b[i]
92 |   saida         <= resize(soma, 15, -16);                       -- atualizamos a saída do interpolador
93 | end architecture simples;
94 | ------------------------------------------------------------------------------------------------------------------------
95 | 
96 | 


--------------------------------------------------------------------------------
/src/act_func.vhd:
--------------------------------------------------------------------------------
  1 | --------------------------------------------------------------------------------
  2 | --! @file
  3 | --! @brief Definition of activation functions
  4 | --! @author Gabriel de Jesus Coelho da Silva
  5 | --------------------------------------------------------------------------------
  6 | 
  7 | --! Use standard library with logic elements
  8 | library ieee;
  9 | use ieee.std_logic_1164.all;
 10 | use ieee.numeric_std.all;
 11 | 
 12 | --! Use proposed library with fixed point definition
 13 | library ieee_proposed;
 14 | use ieee_proposed.fixed_pkg.all;
 15 | 
 16 | --! Use custom library for ease of use
 17 | use work.types.all;
 18 | 
 19 | --! Applies the specified activation function to the input
 20 | 
 21 | --! This element takes as input a sfixed_bus (@see @file types.vhd) and outputs 
 22 | --! the activation function specified as the instantiated architecture.
 23 | entity act_func is
 24 | 	port(
 25 | 		clk      : in  std_logic;  --! Clock, for synchronous implementation
 26 | 		input_i  : in  sfixed_bus; --! Activation function input
 27 | 		output_o : out sfixed_bus := (others => '0') --! Activation function
 28 | 		                                             --! output
 29 | 	);
 30 | end entity act_func;
 31 | 
 32 | -- @brief Threshold
 33 | -- @details McCulloch-Pitts "all-or-none" activation function (threshold).
 34 | architecture threshold of act_func is
 35 | begin
 36 | 	output_o <= to_sfixed_a(1) when input_i >= 0 else to_sfixed_a(0);
 37 | end architecture threshold;
 38 | 
 39 | -- @brief Rectified Linear Unit (ReLU)
 40 | -- @details A simple ReLU (f(x) = max(0, x))
 41 | architecture relu of act_func is
 42 | begin
 43 | 	output_o <= input_i when input_i >= 0 else to_sfixed_a(0);
 44 | end architecture relu;
 45 | 
 46 | -- @brief Tanh
 47 | -- @details Linearly interpolated hyperbolic tangent (tanh).
 48 | -- @author Giovani Baratto 
 49 | architecture tanh of act_func is
 50 | 	constant a : sfixed_bus_array(0 to 31) := ( -- angular coefficients
 51 | 		0  => to_sfixed_a(0.979675),    1 => to_sfixed_a(0.868794),
 52 | 		2  => to_sfixed_a(0.692127),    3 => to_sfixed_a(0.505781),
 53 | 		4  => to_sfixed_a(0.346758),    5 => to_sfixed_a(0.227458),
 54 | 		6  => to_sfixed_a(0.144909),    7 => to_sfixed_a(0.0906082),
 55 | 		8  => to_sfixed_a(0.0559941),   9 => to_sfixed_a(0.0343527),
 56 | 		10 => to_sfixed_a(0.0209817),  11 => to_sfixed_a(0.0127801),
 57 | 		12 => to_sfixed_a(0.00777153), 13 => to_sfixed_a(0.00472105),
 58 | 		14 => to_sfixed_a(0.00286618), 15 => to_sfixed_a(0.00173943),
 59 | 		16 => to_sfixed_a(0.00173943), 17 => to_sfixed_a(0.00286618),
 60 | 		18 => to_sfixed_a(0.00472105), 19 => to_sfixed_a(0.00777153),
 61 | 		20 => to_sfixed_a(0.0127801),  21 => to_sfixed_a(0.0209817),
 62 | 		22 => to_sfixed_a(0.0343527),  23 => to_sfixed_a(0.0559941),
 63 | 		24 => to_sfixed_a(0.0906082),  25 => to_sfixed_a(0.144909),
 64 | 		26 => to_sfixed_a(0.227458),   27 => to_sfixed_a(0.346758),
 65 | 		28 => to_sfixed_a(0.505781),   29 => to_sfixed_a(0.692127),
 66 | 		30 => to_sfixed_a(0.868794),   31 => to_sfixed_a(0.979675));
 67 | 
 68 | 	constant b : sfixed_bus_array(0 to 31) := ( -- linear coefficients
 69 | 		0  => to_sfixed_a(0),           1 => to_sfixed_a(0.0277202),
 70 | 		2  => to_sfixed_a(0.116054),    3 => to_sfixed_a(0.255813),
 71 | 		4  => to_sfixed_a(0.414836),    5 => to_sfixed_a(0.563961),
 72 | 		6  => to_sfixed_a(0.687785),    7 => to_sfixed_a(0.782811),
 73 | 		8  => to_sfixed_a(0.852039),    9 => to_sfixed_a(0.900732),
 74 | 		10 => to_sfixed_a(0.93416),    11 => to_sfixed_a(0.956714),
 75 | 		12 => to_sfixed_a(0.97174),    13 => to_sfixed_a(0.981654),
 76 | 		14 => to_sfixed_a(0.988146),   15 => to_sfixed_a(0.992372),
 77 | 		16 => to_sfixed_a(-0.992372),  17 => to_sfixed_a(-0.988146),
 78 | 		18 => to_sfixed_a(-0.981654),  19 => to_sfixed_a(-0.97174),
 79 | 		20 => to_sfixed_a(-0.956714),  21 => to_sfixed_a(-0.93416),
 80 | 		22 => to_sfixed_a(-0.900732),  23 => to_sfixed_a(-0.852039),
 81 | 		24 => to_sfixed_a(-0.782811),  25 => to_sfixed_a(-0.687785),
 82 | 		26 => to_sfixed_a(-0.563961),  27 => to_sfixed_a(-0.414836),
 83 | 		28 => to_sfixed_a(-0.255813),  29 => to_sfixed_a(-0.116054),
 84 | 		30 => to_sfixed_a(-0.0277202), 31 => to_sfixed_a(0)
 85 | 	);
 86 | 	signal mult_s   : sfixed(2*int - 1 downto -2*frac) := (others => '0');
 87 | 	signal sum_s    : sfixed(int downto -frac)         := (others => '0');
 88 | 	signal index    : integer                          := 0;
 89 | 	signal output_s : sfixed_bus;
 90 | begin
 91 | 	index    <= to_integer(unsigned(input_i(2 downto -2))); -- index of a & b
 92 | 
 93 | 	mult_s   <= a(index) * input_i; -- a[i] * inputs
 94 | 
 95 | 	sum_s    <= resize(mult_s, int - 1, -frac) + b(index); -- a[i] * input + 
 96 | 	                                                       -- b[i]
 97 | 
 98 | 	output_s <= to_sfixed_a(1)	when input_i >  3.5 else
 99 | 	            to_sfixed_a(-1) when input_i < -3.5 else
100 | 	            resize(sum_s, int - 1, -frac); -- output = a[i] * input + b[i]
101 | 
102 | 	-- for synchronous implementation
103 | 	process(clk)
104 | 	begin
105 | 		if (clk'event and clk = '1') then
106 | 			output_o <= output_s;
107 | 		end if;
108 | 	end process;
109 | end architecture tanh;


--------------------------------------------------------------------------------
/src/act_func_tb.vhd:
--------------------------------------------------------------------------------
 1 | library ieee;
 2 | use ieee.std_logic_1164.all;
 3 | use ieee.numeric_std.all;
 4 | 
 5 | use ieee.std_logic_textio.all;
 6 | use std.textio.all;
 7 | 
 8 | use work.types.all;
 9 | 
10 | library ieee_proposed;
11 | use ieee_proposed.fixed_pkg.all;
12 | 
13 | entity act_func_tb is
14 | end entity act_func_tb;
15 | 
16 | architecture tb of act_func_tb is
17 | 
18 | 	constant half_period : time := 10 ns;
19 | 
20 | 	signal clk      : std_logic := '0';
21 | 	signal input_i  : sfixed_bus := to_sfixed_a(0);
22 | 	signal output_o : sfixed_bus;
23 | 
24 | 	signal input_r  : real;
25 | 	signal output_r : real;
26 | 
27 | 	file file_o       : text;
28 | 
29 | begin
30 | 
31 | 	UUT : entity work.act_func(tanh)
32 | 		port map(
33 | 			clk      => clk,
34 | 			input_i  => input_i,
35 | 			output_o => output_o
36 | 		);
37 | 
38 | 	clk <= not clk after half_period;
39 | 
40 | 	input_r  <= to_real(input_i);
41 | 	output_r <= to_real(output_o);
42 | 
43 | 	--    __    __    __    __    __    __    __    __
44 | 	-- __|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |
45 | 	--      ______        ______
46 | 	-- ____|      |______|      |_____|
47 | 	--        ______        ______
48 | 	-- ______|      |______|      |_____|
49 | 	-- 0    15     30     45      60   75
50 | 
51 | 	--input_i <= to_sfixed_a(0), to_sfixed_a(10) after 5 ns, to_sfixed_a(-3) after 35 ns, to_sfixed_a(-10) after 65 ns, to_sfixed_a(20) after 95 ns;
52 | 	--start_i <= '0', '1' after 15 ns, '0' after 35 ns, '1' after 45 ns, '0' after 65 ns, '1' after 75 ns, '0' after 95 ns, '1' after 105 ns, '0' after 125 ns, '1' after 135 ns, '0' after 155 ns;
53 | 
54 | 	process
55 | 		variable to_write : line;
56 | 		variable x        : real;
57 | 	begin
58 | 		file_open(file_o, "tanh-vhdl.dat", write_mode);
59 | 		x := -5.0;
60 | 		while (x <= 5.0) loop
61 | 			write(to_write, x);
62 | 			write(to_write, " ");
63 | 			input_i <= to_sfixed_a(x);
64 | 			wait for half_period * 3;
65 | 			write(to_write, output_r);
66 | 			writeline(file_o, to_write);
67 | 			x := x + 0.1;
68 | 		end loop;
69 | 		file_close(file_o);
70 | 		wait;
71 | 	end process;
72 | 	
73 | end architecture tb;
74 | 


--------------------------------------------------------------------------------
/src/network.vhd:
--------------------------------------------------------------------------------
  1 | --------------------------------------------------------------------------------
  2 | --! @file
  3 | --! @brief Neural network instantiation
  4 | --! @author Gabriel de Jesus Coelho da Silva
  5 | --------------------------------------------------------------------------------
  6 | 
  7 | --! Use standard library with logic elements
  8 | library ieee;
  9 | use ieee.std_logic_1164.all;
 10 | use ieee.numeric_std.all;
 11 | 
 12 | --! Use proposed library with fixed point definition
 13 | library ieee_proposed;
 14 | use ieee_proposed.fixed_pkg.all;
 15 | 
 16 | --! Use custom library for ease of use
 17 | use work.types.all;
 18 | 
 19 | entity network is
 20 | 	generic(
 21 | 		inputs  : integer := 2;         --! Network inputs
 22 | 		outputs : integer := 1          --! Network outputs
 23 | 	);
 24 | 	port(
 25 | 		clk      : in  std_logic;	--! Clock input
 26 | 		rst      : in  std_logic;	--! Reset output
 27 | 		start_i  : in  std_logic;	--! Start input, indicates to start the calculation
 28 | 		input_i  : in  sfixed_bus_array(inputs - 1 downto 0); --! Network input
 29 | 		output_o : out sfixed_bus_array(outputs - 1 downto 0) := (others => (others => '0')); --! Network output
 30 | 		done_o   : out std_logic                              := '0' --! Done output, indicates completion
 31 | 	);
 32 | end entity network;
 33 | 
 34 | architecture n_xor of network is
 35 | 	signal output_n1 : sfixed_bus;
 36 | 	signal output_n2 : sfixed_bus;
 37 | 	signal done_n1   : std_logic;
 38 | 	signal done_n2   : std_logic;
 39 | 	signal start_n3  : std_logic;
 40 | 	signal output_s  : sfixed_bus_array(outputs - 1 downto 0);
 41 | 	signal input_n3  : sfixed_bus_array(inputs - 1 downto 0);
 42 | 	constant weight_n1 : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(-1.5) ),
 43 | 	                                                           ( to_sfixed_a(1) ),
 44 | 	                                                           ( to_sfixed_a(1) ));
 45 | 	constant weight_n2 : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(-0.5) ),
 46 | 	                                                           ( to_sfixed_a(1) ),
 47 | 	                                                           ( to_sfixed_a(1) ));
 48 | 	constant weight_n3 : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(-0.5) ),
 49 | 	                                                           ( to_sfixed_a(-2) ),
 50 | 	                                                           ( to_sfixed_a(1) ));
 51 | begin
 52 | 
 53 | 	-- First layer
 54 | 
 55 | 	n1 : entity work.neuron
 56 | 		generic map(
 57 | 			inputs => inputs
 58 | 		)
 59 | 		port map(
 60 | 			clk      => clk,
 61 | 			rst      => rst,
 62 | 			start_i  => start_i,
 63 | 			input_i  => input_i,
 64 | 			weight_i => weight_n1,
 65 | 			output_o => output_n1,
 66 | 			done_o   => done_n1
 67 | 		);
 68 | 
 69 | 	n2 : entity work.neuron
 70 | 		generic map(
 71 | 			inputs => inputs
 72 | 		)
 73 | 		port map(
 74 | 			clk      => clk,
 75 | 			rst      => rst,
 76 | 			start_i  => start_i,
 77 | 			input_i  => input_i,
 78 | 			weight_i => weight_n2,
 79 | 			output_o => output_n2,
 80 | 			done_o   => done_n2
 81 | 		);
 82 | 
 83 | 	-- Second layer
 84 | 	n3 : entity work.neuron
 85 | 		generic map(
 86 | 			inputs => inputs
 87 | 		)
 88 | 		port map(
 89 | 			clk      => clk,
 90 | 			rst      => rst,
 91 | 			start_i  => start_n3,
 92 | 			input_i  => input_n3,
 93 | 			weight_i => weight_n3,
 94 | 			output_o => output_s(0),
 95 | 			done_o   => done_o
 96 | 		);
 97 | 
 98 | 	input_n3 <= ((output_n1), (output_n2));
 99 | 	start_n3 <= done_n1 and done_n2;
100 | 	output_o <= output_s;
101 | 
102 | end architecture n_xor;
103 | 


--------------------------------------------------------------------------------
/src/network_tb.vhd:
--------------------------------------------------------------------------------
 1 | library ieee;
 2 | use ieee.std_logic_1164.all;
 3 | use ieee.numeric_std.all;
 4 | use work.types.all;
 5 | 
 6 | entity network_tb is
 7 | end entity network_tb;
 8 | 
 9 | architecture n_xor of network_tb is
10 | 	
11 | 	constant inputs : integer := 2;
12 | 	constant outputs : integer := 1;
13 | 	
14 | 	constant half_period : time := 10 ns;
15 | 	
16 | 	signal clk      : std_logic := '0';
17 | 	signal rst      : std_logic := '0';
18 | 	signal input_i  : sfixed_bus_array(inputs - 1 downto 0);
19 | 	signal start_i  : std_logic := '0';
20 | 	signal output_o : sfixed_bus_array(outputs - 1 downto 0);
21 | 	signal done_o   : std_logic;
22 | 	signal input_r  : real_array(inputs - 1 downto 0);
23 | 	signal output_r : real_array(outputs - 1 downto 0);
24 | 
25 | begin
26 | 
27 | 	network_inst : entity work.network(n_xor)
28 | 		generic map(
29 | 			inputs  => inputs,
30 | 			outputs => outputs
31 | 		)
32 | 		port map(
33 | 			clk      => clk,
34 | 			rst      => rst,
35 | 			start_i  => start_i,
36 | 			input_i  => input_i,
37 | 			output_o => output_o,
38 | 			done_o   => done_o
39 | 		);
40 | 		
41 | 		clk <= not clk after half_period;
42 | 		
43 | 		start_stimuli : process is
44 | 		begin
45 | 			start_i <= '0', '1' after 15 ns, '0' after 30 ns;
46 | 			wait until done_o = '1';
47 | 		end process start_stimuli;
48 | 			
49 | 		
50 | 		input_stimuli : process is
51 | 		begin
52 | 			input_i <= (( to_sfixed_a(0) ), ( to_sfixed_a(0) ));
53 | 			wait until done_o = '1';
54 | 			input_i <= (( to_sfixed_a(0) ), ( to_sfixed_a(1) ));
55 | 			wait until done_o = '1';
56 | 			input_i <= (( to_sfixed_a(1) ), ( to_sfixed_a(0) ));
57 | 			wait until done_o = '1';
58 | 			input_i <= (( to_sfixed_a(1) ), ( to_sfixed_a(1) ));
59 | 			wait until done_o = '1';
60 | 		end process input_stimuli;
61 | 		
62 | 		input_r <= to_real(input_i);
63 | 		output_r <= to_real(output_o);
64 | 		
65 | end architecture n_xor;
66 | 


--------------------------------------------------------------------------------
/src/network_test.vhd:
--------------------------------------------------------------------------------
  1 | library ieee;
  2 | use ieee.std_logic_1164.all;
  3 | use ieee.numeric_std.all;
  4 | library ieee_proposed;
  5 | use ieee_proposed.fixed_pkg.all;
  6 | use work.types.all;
  7 | 
  8 | entity network_test is
  9 | 	generic(
 10 | 		inputs  : integer := 2;         -- Network inputs
 11 | 		outputs : integer := 1          -- Network outputs
 12 | 	);
 13 | 	port(
 14 | 		clk      : in  std_logic;
 15 | 		rst      : in  std_logic;
 16 | 		start_i  : in  std_logic;
 17 | 		input_i  : in  sfixed_bus_array(inputs - 1 downto 0);
 18 | 		output_o : out sfixed_bus_array(outputs - 1 downto 0) := (others => (others => '0'));
 19 | 		done_o   : out std_logic                              := '0'
 20 | 	);
 21 | end entity network_test;
 22 | 
 23 | architecture n_test_2_4_1 of network_test is
 24 | 	signal output_n1   : sfixed_bus;
 25 | 	signal output_n2   : sfixed_bus;
 26 | 	signal done_n1     : std_logic;
 27 | 	signal done_n2     : std_logic;
 28 | 	signal done_n1_h   : std_logic;
 29 | 	signal done_n2_h   : std_logic;
 30 | 	signal done_n3_h   : std_logic;
 31 | 	signal done_n4_h   : std_logic;
 32 | 	signal start_h     : std_logic;
 33 | 	signal start_o_l   : std_logic;
 34 | 	signal output_s    : sfixed_bus_array(outputs - 1 downto 0);
 35 | 	signal input_o_l   : sfixed_bus_array(3 downto 0);
 36 | 	constant weight_n1   : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(1) ),
 37 | 	                                                             ( to_sfixed_a(2) ),
 38 | 	                                                             ( to_sfixed_a(2) ));
 39 | 	constant weight_n2   : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(-0.5) ),
 40 | 	                                                             ( to_sfixed_a(1) ),
 41 | 	                                                             ( to_sfixed_a(1) ));
 42 | 	constant weight_n1_h : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(-0.5) ),
 43 | 	                                                             ( to_sfixed_a(-1) ),
 44 | 	                                                             ( to_sfixed_a(1) ));
 45 | 	constant weight_n2_h : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(-1.5) ),
 46 | 	                                                             ( to_sfixed_a(1) ),
 47 | 	                                                             ( to_sfixed_a(2.5) ));
 48 | 	constant weight_n3_h : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(1) ),
 49 | 	                                                            ( to_sfixed_a(-1) ),
 50 | 	                                                            ( to_sfixed_a(0.5) ));
 51 | 	constant weight_n4_h : sfixed_bus_array(inputs downto 0) := (( to_sfixed_a(2) ),
 52 | 	                                                            ( to_sfixed_a(-2) ),
 53 | 	                                                            ( to_sfixed_a(1.5) ));
 54 | 	constant weight_n_o  : sfixed_bus_array(4 downto 0)      := (( to_sfixed_a(1) ),
 55 | 	                                                            ( to_sfixed_a(2) ),
 56 | 	                                                            ( to_sfixed_a(1.5) ),
 57 | 	                                                            ( to_sfixed_a(-1.5) ),																				  
 58 | 	                                                            ( to_sfixed_a(-1) ));
 59 | 
 60 | 	signal input_h     : sfixed_bus_array(inputs - 1 downto 0);
 61 | 	signal output_n1_h : sfixed_bus;
 62 | 	signal output_n2_h : sfixed_bus;
 63 | 	signal output_n3_h : sfixed_bus;
 64 | 	signal output_n4_h : sfixed_bus;
 65 | begin
 66 | 
 67 | 	-- First layer
 68 | 	n1 : entity work.neuron
 69 | 		generic map(
 70 | 			inputs => inputs
 71 | 		)
 72 | 		port map(
 73 | 			clk      => clk,
 74 | 			rst      => start_o_l,
 75 | 			start_i  => start_i,
 76 | 			input_i  => input_i,
 77 | 			weight_i => weight_n1,
 78 | 			output_o => output_n1,
 79 | 			done_o   => done_n1
 80 | 		);
 81 | 
 82 | 	n2 : entity work.neuron
 83 | 		generic map(
 84 | 			inputs => inputs
 85 | 		)
 86 | 		port map(
 87 | 			clk      => clk,
 88 | 			rst      => start_o_l,
 89 | 			start_i  => start_i,
 90 | 			input_i  => input_i,
 91 | 			weight_i => weight_n2,
 92 | 			output_o => output_n2,
 93 | 			done_o   => done_n2
 94 | 		);
 95 | 
 96 | 	-- Hidden layer
 97 | 	n1_h : entity work.neuron
 98 | 		generic map(
 99 | 			inputs => inputs
100 | 		)
101 | 		port map(
102 | 			clk      => clk,
103 | 			rst      => rst,
104 | 			start_i  => start_h,
105 | 			input_i  => input_h,
106 | 			weight_i => weight_n1_h,
107 | 			output_o => output_n1_h,
108 | 			done_o   => done_n1_h
109 | 		);
110 | 
111 | 	n2_h : entity work.neuron
112 | 		generic map(
113 | 			inputs => inputs
114 | 		)
115 | 		port map(
116 | 			clk      => clk,
117 | 			rst      => rst,
118 | 			start_i  => start_h,
119 | 			input_i  => input_h,
120 | 			weight_i => weight_n2_h,
121 | 			output_o => output_n2_h,
122 | 			done_o   => done_n2_h
123 | 		);
124 | 
125 | 	n3_h : entity work.neuron
126 | 		generic map(
127 | 			inputs => inputs
128 | 		)
129 | 		port map(
130 | 			clk      => clk,
131 | 			rst      => rst,
132 | 			start_i  => start_h,
133 | 			input_i  => input_h,
134 | 			weight_i => weight_n3_h,
135 | 			output_o => output_n3_h,
136 | 			done_o   => done_n3_h
137 | 		);
138 | 
139 | 	n4_h : entity work.neuron
140 | 		generic map(
141 | 			inputs => inputs
142 | 		)
143 | 		port map(
144 | 			clk      => clk,
145 | 			rst      => rst,
146 | 			start_i  => start_h,
147 | 			input_i  => input_h,
148 | 			weight_i => weight_n4_h,
149 | 			output_o => output_n4_h,
150 | 			done_o   => done_n4_h
151 | 		);
152 | 
153 | 	-- Output layer
154 | 	n_o : entity work.neuron
155 | 		generic map(
156 | 			inputs => 4
157 | 		)
158 | 		port map(
159 | 			clk      => clk,
160 | 			rst      => rst,
161 | 			start_i  => start_o_l,
162 | 			input_i  => input_o_l,
163 | 			weight_i => weight_n_o,
164 | 			output_o => output_s(0),
165 | 			done_o   => done_o
166 | 		);
167 | 
168 | 	start_h <= done_n1 and done_n2;
169 | 	input_h <= ((output_n1), (output_n2));
170 | 
171 | 	start_o_l <= done_n1_h and done_n2_h and done_n3_h and done_n4_h;
172 | 	input_o_l <= ((output_n1_h), (output_n2_h), (output_n3_h), (output_n4_h));
173 | 
174 | 	output_o <= output_s;
175 | 
176 | end architecture n_test_2_4_1;
177 | 


--------------------------------------------------------------------------------
/src/network_test_tb.vhd:
--------------------------------------------------------------------------------
 1 | library ieee;
 2 | use ieee.std_logic_1164.all;
 3 | use ieee.numeric_std.all;
 4 | use ieee.math_real.all; -- tanh(x) etc
 5 | use work.types.all;
 6 | 
 7 | entity network_test_tb is
 8 | end entity network_test_tb;
 9 | 
10 | architecture n_test_2_4_1 of network_test_tb is
11 | 	
12 | 	constant inputs : integer := 2;
13 | 	constant outputs : integer := 1;
14 | 	
15 | 	constant half_period : time := 10 ns;
16 | 	
17 | 	signal clk      : std_logic := '0';
18 | 	signal rst      : std_logic := '0';
19 | 	signal input_i  : sfixed_bus_array(inputs - 1 downto 0);
20 | 	signal start_i  : std_logic := '0';
21 | 	signal output_o : sfixed_bus_array(outputs - 1 downto 0);
22 | 	signal done_o   : std_logic;
23 | 	signal input_r  : real_array(inputs - 1 downto 0);
24 | 	signal output_r : real_array(outputs - 1 downto 0);
25 | 	signal output_e : real_array(outputs - 1 downto 0);
26 | 
27 | begin
28 | 
29 | 	network_inst : entity work.network_test(n_test_2_4_1)
30 | 		generic map(
31 | 			inputs  => inputs,
32 | 			outputs => outputs
33 | 		)
34 | 		port map(
35 | 			clk      => clk,
36 | 			rst      => rst,
37 | 			start_i  => start_i,
38 | 			input_i  => input_i,
39 | 			output_o => output_o,
40 | 			done_o   => done_o
41 | 		);
42 | 		
43 | 		clk <= not clk after half_period;
44 | 		
45 | 		start_stimuli : process is
46 | 		begin
47 | 			start_i <= '0', '1' after 15 ns, '0' after 30 ns;
48 | 			wait until done_o = '1';
49 | 		end process start_stimuli;
50 | 			
51 | 		
52 | 		input_stimuli : process is
53 | 		begin
54 | 			input_i <= (( to_sfixed_a(0.7) ), ( to_sfixed_a(0.7) ));
55 | 			wait until done_o = '1';
56 | 			input_i <= (( to_sfixed_a(0) ), ( to_sfixed_a(0) ));
57 | 			wait until done_o = '1';
58 | 			input_i <= (( to_sfixed_a(0) ), ( to_sfixed_a(1) ));
59 | 			wait until done_o = '1';
60 | 			input_i <= (( to_sfixed_a(1) ), ( to_sfixed_a(0) ));
61 | 			wait until done_o = '1';
62 | 			input_i <= (( to_sfixed_a(1) ), ( to_sfixed_a(1) ));
63 | 			wait until done_o = '1';
64 | 		end process input_stimuli;
65 | 		
66 | 		input_r <= to_real(input_i);
67 | 		output_r <= to_real(output_o);
68 | 		
69 | 		-- output_e <= 
70 | 		
71 | end architecture n_test_2_4_1;
72 | 


--------------------------------------------------------------------------------
/src/neuron.vhd:
--------------------------------------------------------------------------------
  1 | --------------------------------------------------------------------------------
  2 | --! @file
  3 | --! @brief Single neuron instance
  4 | --! @author Gabriel de Jesus Coelho da Silva
  5 | --------------------------------------------------------------------------------
  6 | 
  7 | --! Use standard library with logic elements
  8 | library ieee;
  9 | use ieee.std_logic_1164.all;
 10 | use ieee.numeric_std.all;
 11 | 
 12 | --! Use proposed library with fixed point definition
 13 | library ieee_proposed;
 14 | use ieee_proposed.fixed_pkg.all;
 15 | 
 16 | --! Use custom library for ease of use
 17 | use work.types.all;
 18 | 
 19 | --! A single neuron with generic "N" inputs
 20 | 
 21 | --! This element takes "N" inputs and "N + 1" weights of the type
 22 | --! sfixed_bus_array (@see @file types.vhd), multiplies the "N"th input by the
 23 | --! "N+1"th weight, sums the resulting multiplications and outputs the
 24 | --! activation function defined by the instantiated architecture (@see @file 
 25 | --! act_func.vhd) applied to the sum.
 26 | entity neuron is
 27 | 	generic(
 28 | 		inputs : integer := 3            --! Number of inputs into the neuron
 29 | 	);
 30 | 	port(
 31 | 		clk      : in  std_logic;        --! Clock input
 32 | 		rst      : in  std_logic;        --! Reset input
 33 | 		start_i  : in  std_logic;        --! Start input, indicates to start
 34 | 		                                 --! the calculation
 35 | 		input_i  : in  sfixed_bus_array(inputs - 1 downto 0); --! Neuron inputs
 36 | 		weight_i : in  sfixed_bus_array(inputs downto 0); --! Neuron weights 
 37 | 		                                                  --! (including bias)
 38 | 		output_o : out sfixed_bus := (others => '0');     --! Neuron output
 39 | 		done_o   : out std_logic  := '0' --! Done output, indicates completion
 40 | 	);
 41 | end entity neuron;
 42 | 
 43 | architecture behavioral of neuron is
 44 | 	type state is (idle, reg_inputs, mult, sum, act_func);
 45 | 	signal current_state, next_state : state;
 46 | 
 47 | 	signal input_s        : sfixed_bus_array(inputs - 1 downto 0) := 
 48 | 		(others => (others => '0'));
 49 | 	signal sum_s          : sfixed(int downto -frac)              := 
 50 | 		(others => '0');
 51 | 	signal mult_s         : sfixed(2 * int - 1 downto -2 * frac)  := 
 52 | 		(others => '0');
 53 | 	signal index          : integer                               := inputs;
 54 | 	signal weight_s       : sfixed_bus_array(inputs downto 0)     := weight_i;
 55 | 	signal output_s       : sfixed_bus                            := 
 56 | 		(others => '0');
 57 | 	signal act_func_input : sfixed_bus                            := 
 58 | 		resize(sum_s, int - 1, -frac);
 59 | 	signal done_s         : std_logic                             := '0';
 60 | begin
 61 | 
 62 | 	fsm_lower : process(clk, rst) is
 63 | 	begin
 64 | 		-- synchronous reset results in better performance
 65 | 		-- because of multiplier blocks and RAM registers inferred
 66 | 		if rising_edge(clk) then
 67 | 			if rst = '1' then
 68 | 				current_state <= idle;
 69 | 			end if;
 70 | 			current_state <= next_state;
 71 | 		end if;
 72 | 	end process fsm_lower;
 73 | 
 74 | 	fsm_upper : process(current_state, input_i, input_s, start_i, weight_s, 
 75 | 		mult_s) is
 76 | 		-- do NOT include "index" or "sum_s" here
 77 | 	begin
 78 | 		case current_state is
 79 | 			when idle =>
 80 | 				done_s <= '0';
 81 | 				if start_i = '1' then
 82 | 					next_state <= reg_inputs;
 83 | 				else
 84 | 					next_state <= current_state;
 85 | 				end if;
 86 | 
 87 | 			when reg_inputs =>
 88 | 				input_s <= input_i;
 89 | 				sum_s   <= resize(weight_s(inputs), int, -frac);
 90 | 				-- bias is already added to sum
 91 | 				mult_s  <= (others => '0');
 92 | 				index   <= inputs;
 93 | 
 94 | 				next_state <= mult;
 95 | 
 96 | 			when mult =>
 97 | 				if index = 0 then
 98 | 					next_state <= act_func;
 99 | 				else
100 | 					mult_s     <= input_s(index - 1) * weight_s(index - 1);
101 | 					next_state <= sum;
102 | 				end if;
103 | 
104 | 			when sum =>
105 | 				index      <= index - 1;
106 | 				sum_s      <= resize(sum_s, int - 1, -frac) + 
107 | 					resize(mult_s, int - 1, -frac);
108 | 				next_state <= mult;
109 | 
110 | 			when act_func =>
111 | 				done_s     <= '1';
112 | 				next_state <= idle;
113 | 
114 | 		end case;
115 | 
116 | 	end process fsm_upper;
117 | 
118 | 	--! Activation function instantiation
119 | 	act_func_inst : entity work.act_func(tanh)
120 | 		port map(
121 | 			clk      => clk,
122 | 			input_i  => act_func_input,
123 | 			output_o => output_s
124 | 		);
125 | 
126 | 	done_o         <= done_s;
127 | 	output_o       <= output_s;
128 | 	weight_s       <= weight_i;
129 | 	act_func_input <= resize(sum_s, int - 1, -frac);
130 | 
131 | end architecture behavioral;
132 | 


--------------------------------------------------------------------------------
/src/neuron_tb.vhd:
--------------------------------------------------------------------------------
 1 | library ieee;
 2 | use ieee.std_logic_1164.all;
 3 | use ieee.numeric_std.all;
 4 | library ieee_proposed;
 5 | use ieee_proposed.fixed_pkg.all;
 6 | use work.types.all;
 7 | 
 8 | entity neuron_tb is
 9 | end entity neuron_tb;
10 | 
11 | architecture tb of neuron_tb is
12 | 
13 | 	constant half_period : time := 10 ns;
14 | 
15 | 	constant inputs : integer := 2;
16 | 
17 | 	signal clk      : std_logic                         := '0';
18 | 	signal rst      : std_logic                         := '0';
19 | 	signal start_i  : std_logic                         := '0';
20 | 	signal input_i  : sfixed_bus_array(inputs - 1 downto 0);
21 | 	signal weight_i : sfixed_bus_array(inputs downto 0) := (to_sfixed_a(10),
22 | 	                                                        to_sfixed_a(20),
23 | 	                                                        to_sfixed_a(30));
24 | 	signal output_o : sfixed_bus;
25 | 	signal done_o   : std_logic;
26 | 
27 | 	signal input_r  : real_array(inputs - 1 downto 0);
28 | 	signal weight_r : real_array(inputs downto 0);
29 | 	signal output_r : real;
30 | 
31 | begin
32 | 
33 | 	UUT : entity work.neuron(behavioral)
34 | 		generic map(
35 | 			inputs => inputs
36 | 		)
37 | 		port map(
38 | 			clk      => clk,
39 | 			rst      => rst,
40 | 			start_i  => start_i,
41 | 			input_i  => input_i,
42 | 			weight_i => weight_i,
43 | 			output_o => output_o,
44 | 			done_o   => done_o
45 | 		);
46 | 
47 | 	clk <= not clk after half_period;
48 | 
49 | 	input_r  <= to_real(input_i);
50 | 	weight_r <= to_real(weight_i);
51 | 	output_r <= to_real(output_o);
52 | 
53 | 	input_i <= ((to_sfixed_a(0)), to_sfixed_a(20));
54 | 	start_i <= '0', '1' after 15 ns, '0' after 30 ns;
55 | 
56 | end architecture tb;
57 | 


--------------------------------------------------------------------------------
/src/types.vhd:
--------------------------------------------------------------------------------
 1 | --------------------------------------------------------------------------------
 2 | --! @file
 3 | --! @brief Custom types definition for ease of use
 4 | --! @author Gabriel de Jesus Coelho da Silva
 5 | --------------------------------------------------------------------------------
 6 | 
 7 | --! Use standard library with logic elements
 8 | library ieee;
 9 | use ieee.std_logic_1164.all;
10 | use ieee.numeric_std.all;
11 | 
12 | --! Use proposed library with fixed point definition
13 | library ieee_proposed;
14 | use ieee_proposed.fixed_pkg.all;
15 | 
16 | package types is
17 | 
18 | 	--! std_logic_vector type extension --
19 | 
20 | 	--! The width of the bus
21 | 	constant width : integer := 8;
22 | 	
23 | 	--! Bus and array of bus definitions
24 | 	subtype std_logic_bus is std_logic_vector(width - 1 downto 0);
25 | 	type std_logic_bus_array is array (integer range <>) of std_logic_bus;
26 | 
27 | 
28 | 	--! sfixed type extension --
29 | 
30 | 	constant int  : integer := 16; --! Size of the integer part
31 | 	constant frac : integer := 16; --! Size of the fractionary part
32 | 
33 | 	--! Bus and array of bus definitions
34 | 	subtype sfixed_bus is sfixed(int - 1 downto -frac);
35 | 	type sfixed_bus_array is array (integer range <>) of sfixed_bus;
36 | 
37 | 
38 | 	--! Real type extension
39 | 
40 | 	--! Array of real
41 | 	type real_array is array (integer range <>) of real;
42 | 
43 | 	--! Functions that convert to sfixed using the previosly defined sizes of 
44 | 	--! integer and fractionary parts
45 | 	function to_sfixed_a(arg : real) return unresolved_sfixed;
46 | 	function to_sfixed_a(arg : integer) return unresolved_sfixed;
47 | 	function to_real(arg : sfixed_bus_array) return real_array;
48 | 
49 | end package types;
50 | 
51 | --
52 | package body types is
53 | 
54 | 	--! Automatically applies indexes on to_sfixed
55 | 	function to_sfixed_a(arg : real) return unresolved_sfixed is
56 | 		variable result : unresolved_sfixed(int - 1 downto -frac);
57 | 	begin
58 | 		result := to_sfixed(arg         => arg,
59 | 		                    left_index  => int - 1,
60 | 		                    right_index => -frac);
61 | 		return result;
62 | 	end function to_sfixed_a;
63 | 
64 | 	--! Automatically applies indexes on to_sfixed
65 | 	function to_sfixed_a(arg : integer) return unresolved_sfixed is
66 | 		variable result : unresolved_sfixed(int - 1 downto -frac);
67 | 	begin
68 | 		result := to_sfixed(arg         => arg,
69 | 		                    left_index  => int - 1,
70 | 		                    right_index => -frac);
71 | 		return result;
72 | 	end function to_sfixed_a;
73 | 
74 | 	--! Converts an sfixed_bus_array to a real_array (for easier visualization)
75 | 	function to_real(arg : sfixed_bus_array) return real_array is
76 | 		variable result : real_array(arg'range);
77 | 	begin
78 | 		for i in arg'range loop
79 | 			result(i) := to_real(arg => arg(i));
80 | 		end loop;
81 | 		return result;
82 | 	end function to_real;
83 | 
84 | end package body types;


--------------------------------------------------------------------------------