├── LICENSE ├── README.md ├── misc └── caminit │ ├── .gitignore │ └── picam_init.cc ├── verilog_cores ├── .gitignore ├── Makefile ├── README.md ├── csi │ ├── header_ecc.v │ └── rx_packet_handler.v ├── csi2.core ├── link │ └── csi_rx_ice40.v ├── misc │ └── downsample.v ├── phy │ ├── byte_aligner.v │ ├── dphy_iserdes.v │ ├── dphy_oserdes.v │ └── word_combiner.v └── test │ └── icebreaker │ ├── .gitignore │ ├── Makefile │ ├── constraints.py │ ├── icecam.pcf │ ├── top.v │ └── uart.v └── vhdl_rx ├── .gitignore ├── LICENSE.notes ├── README.md ├── demo-top ├── framebuffer_top.vhd ├── mig_a.prj └── ov13850_demo.vhd ├── dvi-tx ├── dvi_tx_clk_drv.vhd ├── dvi_tx_tmds_enc.vhd ├── dvi_tx_tmds_phy.vhd └── dvi_tx_top.vhd ├── examples ├── .gitignore └── ov13850_demo │ ├── ov13850_demo.cache │ └── ip │ │ ├── 54144841a4506c29 │ │ ├── 54144841a4506c29.xci │ │ ├── dvi_pll_sim_netlist.v │ │ └── dvi_pll_stub.v │ │ ├── 548aa35948ad692b │ │ ├── 548aa35948ad692b.xci │ │ ├── camera_pll_sim_netlist.v │ │ └── camera_pll_stub.v │ │ └── 75280199e9655e6a │ │ ├── 75280199e9655e6a.xci │ │ ├── dvi_pll_sim_netlist.v │ │ └── dvi_pll_stub.v │ ├── ov13850_demo.ip_user_files │ ├── ip │ │ ├── camera_pll │ │ │ └── camera_pll_stub.v │ │ ├── ddr3_if │ │ │ └── ddr3_if_stub.v │ │ ├── dvi_pll │ │ │ └── dvi_pll_stub.v │ │ ├── ila_0 │ │ │ └── ila_0_stub.v │ │ ├── input_line_buffer │ │ │ └── input_line_buffer_stub.v │ │ └── output_line_buffer │ │ │ └── output_line_buffer_stub.v │ ├── ipstatic │ │ ├── hdl │ │ │ ├── fifo_generator_v13_1_rfs.v │ │ │ └── fifo_generator_v13_1_rfs.vhd │ │ └── simulation │ │ │ ├── blk_mem_gen_v8_3.v │ │ │ └── fifo_generator_vlog_beh.v │ ├── mem_init_files │ │ ├── mig_a.prj │ │ └── mig_b.prj │ └── sim_scripts │ │ ├── camera_pll_1 │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ ├── vcs │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── ddr3_if │ │ ├── activehdl │ │ │ ├── glbl.v │ │ │ └── mig_b.prj │ │ ├── ies │ │ │ ├── glbl.v │ │ │ └── mig_b.prj │ │ ├── modelsim │ │ │ ├── glbl.v │ │ │ └── mig_b.prj │ │ ├── questa │ │ │ ├── glbl.v │ │ │ └── mig_b.prj │ │ ├── riviera │ │ │ ├── glbl.v │ │ │ └── mig_b.prj │ │ ├── vcs │ │ │ ├── glbl.v │ │ │ └── mig_b.prj │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ └── vlog.prj │ │ ├── ddr3_if_1 │ │ ├── activehdl │ │ │ ├── glbl.v │ │ │ └── mig_a.prj │ │ ├── ies │ │ │ ├── glbl.v │ │ │ └── mig_a.prj │ │ ├── modelsim │ │ │ ├── glbl.v │ │ │ └── mig_a.prj │ │ ├── questa │ │ │ ├── glbl.v │ │ │ └── mig_a.prj │ │ ├── riviera │ │ │ ├── glbl.v │ │ │ └── mig_a.prj │ │ ├── vcs │ │ │ ├── glbl.v │ │ │ └── mig_a.prj │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ ├── mig_a.prj │ │ │ └── vlog.prj │ │ ├── dvi_pll_1 │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ ├── vcs │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── framebuffer-ctrl │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ └── vcs │ │ │ └── glbl.v │ │ ├── ila_0 │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ ├── vcs │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── input_line_buffer │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ ├── vcs │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── input_line_buffer_1 │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ ├── vcs │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ ├── output_line_buffer │ │ ├── activehdl │ │ │ └── glbl.v │ │ ├── ies │ │ │ └── glbl.v │ │ ├── modelsim │ │ │ └── glbl.v │ │ ├── questa │ │ │ └── glbl.v │ │ ├── riviera │ │ │ └── glbl.v │ │ ├── vcs │ │ │ └── glbl.v │ │ └── xsim │ │ │ ├── cmd.tcl │ │ │ ├── glbl.v │ │ │ └── vlog.prj │ │ └── output_line_buffer_1 │ │ ├── activehdl │ │ └── glbl.v │ │ ├── ies │ │ └── glbl.v │ │ ├── modelsim │ │ └── glbl.v │ │ ├── questa │ │ └── glbl.v │ │ ├── riviera │ │ └── glbl.v │ │ ├── vcs │ │ └── glbl.v │ │ └── xsim │ │ ├── cmd.tcl │ │ ├── glbl.v │ │ └── vlog.prj │ ├── ov13850_demo.runs │ ├── camera_pll_synth_1 │ │ ├── camera_pll.tcl │ │ └── dont_touch.xdc │ ├── ddr3_if_synth_1 │ │ └── ddr3_if.tcl │ ├── dvi_pll_synth_1 │ │ ├── dont_touch.xdc │ │ └── dvi_pll.tcl │ ├── impl_1 │ │ └── ov13850_demo.tcl │ ├── input_line_buffer_synth_1 │ │ ├── dont_touch.xdc │ │ ├── input_line_buffer.tcl │ │ ├── input_line_buffer_sim_netlist.v │ │ └── input_line_buffer_stub.v │ ├── output_line_buffer_synth_1 │ │ ├── dont_touch.xdc │ │ ├── output_line_buffer.tcl │ │ ├── output_line_buffer_sim_netlist.v │ │ └── output_line_buffer_stub.v │ └── synth_1 │ │ ├── .Xil │ │ └── ov13850_demo_propImpl.xdc │ │ └── ov13850_demo.tcl │ ├── ov13850_demo.sim │ └── sim_1 │ │ └── synth │ │ └── func │ │ ├── genesys2_fbtest.tcl │ │ ├── genesys2_fbtest_func_synth.v │ │ └── genesys2_fbtest_vlog.prj │ ├── ov13850_demo.srcs │ ├── constrs_1 │ │ └── imports │ │ │ ├── constraints │ │ │ └── ddr3_if.xdc │ │ │ └── new │ │ │ └── genesys2.xdc │ └── sources_1 │ │ └── ip │ │ ├── camera_pll_1 │ │ ├── camera_pll.v │ │ ├── camera_pll.xci │ │ ├── camera_pll.xdc │ │ ├── camera_pll_board.xdc │ │ ├── camera_pll_clk_wiz.v │ │ ├── camera_pll_ooc.xdc │ │ ├── camera_pll_sim_netlist.v │ │ └── camera_pll_stub.v │ │ ├── ddr3_if │ │ ├── mig_a.prj │ │ └── mig_b.prj │ │ ├── ddr3_if_1 │ │ ├── ddr3_if.xci │ │ ├── ddr3_if │ │ │ └── user_design │ │ │ │ ├── constraints │ │ │ │ ├── ddr3_if.xdc │ │ │ │ └── ddr3_if_ooc.xdc │ │ │ │ └── rtl │ │ │ │ ├── axi │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_addr_decode.v │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_read.v │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg.v │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg_bank.v │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_top.v │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_write.v │ │ │ │ ├── mig_7series_v4_0_axi_mc.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_ar_channel.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_aw_channel.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_b_channel.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_arbiter.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_fsm.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_translator.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_fifo.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_incr_cmd.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_r_channel.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_simple_fifo.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_w_channel.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_wr_cmd_fsm.v │ │ │ │ ├── mig_7series_v4_0_axi_mc_wrap_cmd.v │ │ │ │ ├── mig_7series_v4_0_ddr_a_upsizer.v │ │ │ │ ├── mig_7series_v4_0_ddr_axi_register_slice.v │ │ │ │ ├── mig_7series_v4_0_ddr_axi_upsizer.v │ │ │ │ ├── mig_7series_v4_0_ddr_axic_register_slice.v │ │ │ │ ├── mig_7series_v4_0_ddr_carry_and.v │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_and.v │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_or.v │ │ │ │ ├── mig_7series_v4_0_ddr_carry_or.v │ │ │ │ ├── mig_7series_v4_0_ddr_command_fifo.v │ │ │ │ ├── mig_7series_v4_0_ddr_comparator.v │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel.v │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel_static.v │ │ │ │ ├── mig_7series_v4_0_ddr_r_upsizer.v │ │ │ │ └── mig_7series_v4_0_ddr_w_upsizer.v │ │ │ │ ├── clocking │ │ │ │ ├── mig_7series_v4_0_clk_ibuf.v │ │ │ │ ├── mig_7series_v4_0_infrastructure.v │ │ │ │ ├── mig_7series_v4_0_iodelay_ctrl.v │ │ │ │ └── mig_7series_v4_0_tempmon.v │ │ │ │ ├── controller │ │ │ │ ├── mig_7series_v4_0_arb_mux.v │ │ │ │ ├── mig_7series_v4_0_arb_row_col.v │ │ │ │ ├── mig_7series_v4_0_arb_select.v │ │ │ │ ├── mig_7series_v4_0_bank_cntrl.v │ │ │ │ ├── mig_7series_v4_0_bank_common.v │ │ │ │ ├── mig_7series_v4_0_bank_compare.v │ │ │ │ ├── mig_7series_v4_0_bank_mach.v │ │ │ │ ├── mig_7series_v4_0_bank_queue.v │ │ │ │ ├── mig_7series_v4_0_bank_state.v │ │ │ │ ├── mig_7series_v4_0_col_mach.v │ │ │ │ ├── mig_7series_v4_0_mc.v │ │ │ │ ├── mig_7series_v4_0_rank_cntrl.v │ │ │ │ ├── mig_7series_v4_0_rank_common.v │ │ │ │ ├── mig_7series_v4_0_rank_mach.v │ │ │ │ └── mig_7series_v4_0_round_robin_arb.v │ │ │ │ ├── ddr3_if.v │ │ │ │ ├── ddr3_if_mig.v │ │ │ │ ├── ddr3_if_mig_sim.v │ │ │ │ ├── ecc │ │ │ │ ├── mig_7series_v4_0_ecc_buf.v │ │ │ │ ├── mig_7series_v4_0_ecc_dec_fix.v │ │ │ │ ├── mig_7series_v4_0_ecc_gen.v │ │ │ │ ├── mig_7series_v4_0_ecc_merge_enc.v │ │ │ │ └── mig_7series_v4_0_fi_xor.v │ │ │ │ ├── ip_top │ │ │ │ ├── mig_7series_v4_0_mem_intfc.v │ │ │ │ └── mig_7series_v4_0_memc_ui_top_axi.v │ │ │ │ ├── phy │ │ │ │ ├── mig_7series_v4_0_ddr_byte_group_io.v │ │ │ │ ├── mig_7series_v4_0_ddr_byte_lane.v │ │ │ │ ├── mig_7series_v4_0_ddr_calib_top.v │ │ │ │ ├── mig_7series_v4_0_ddr_if_post_fifo.v │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy.v │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy_wrapper.v │ │ │ │ ├── mig_7series_v4_0_ddr_of_pre_fifo.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_4lanes.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_init.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_cntlr.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_data.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_edge.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_lim.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_mux.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_samp.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_oclkdelay_cal.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_prbs_rdlvl.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_rdlvl.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_tempmon.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_top.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrcal.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl.v │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v │ │ │ │ ├── mig_7series_v4_0_ddr_prbs_gen.v │ │ │ │ ├── mig_7series_v4_0_ddr_skip_calib_tap.v │ │ │ │ ├── mig_7series_v4_0_poc_cc.v │ │ │ │ ├── mig_7series_v4_0_poc_edge_store.v │ │ │ │ ├── mig_7series_v4_0_poc_meta.v │ │ │ │ ├── mig_7series_v4_0_poc_pd.v │ │ │ │ ├── mig_7series_v4_0_poc_tap_base.v │ │ │ │ └── mig_7series_v4_0_poc_top.v │ │ │ │ └── ui │ │ │ │ ├── mig_7series_v4_0_ui_cmd.v │ │ │ │ ├── mig_7series_v4_0_ui_rd_data.v │ │ │ │ ├── mig_7series_v4_0_ui_top.v │ │ │ │ └── mig_7series_v4_0_ui_wr_data.v │ │ ├── ddr3_if_sim_netlist.v │ │ ├── ddr3_if_stub.v │ │ └── mig_a.prj │ │ ├── dvi_pll_1 │ │ ├── dvi_pll.v │ │ ├── dvi_pll.xci │ │ ├── dvi_pll.xdc │ │ ├── dvi_pll_board.xdc │ │ ├── dvi_pll_clk_wiz.v │ │ ├── dvi_pll_ooc.xdc │ │ ├── dvi_pll_sim_netlist.v │ │ └── dvi_pll_stub.v │ │ ├── input_line_buffer_1 │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── input_line_buffer.xci │ │ ├── input_line_buffer_ooc.xdc │ │ ├── input_line_buffer_sim_netlist.v │ │ ├── input_line_buffer_stub.v │ │ ├── misc │ │ │ └── blk_mem_gen_v8_3.vhd │ │ ├── sim │ │ │ └── input_line_buffer.v │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_3.v │ │ └── synth │ │ │ └── input_line_buffer.vhd │ │ └── output_line_buffer_1 │ │ ├── hdl │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── misc │ │ └── blk_mem_gen_v8_3.vhd │ │ ├── output_line_buffer.xci │ │ ├── output_line_buffer_ooc.xdc │ │ ├── output_line_buffer_sim_netlist.v │ │ ├── output_line_buffer_stub.v │ │ ├── sim │ │ └── output_line_buffer.v │ │ ├── simulation │ │ └── blk_mem_gen_v8_3.v │ │ └── synth │ │ └── output_line_buffer.vhd │ └── ov13850_demo.xpr ├── framebuffer-ctrl ├── framebuffer_ctrl.vhd ├── input_line_buffer.xci └── output_line_buffer.xci ├── mipi-csi-rx ├── csi_rx_10bit_unpack.vhd ├── csi_rx_4_lane_link.vhd ├── csi_rx_byte_align.vhd ├── csi_rx_clock_det.vhd ├── csi_rx_hdr_ecc.vhd ├── csi_rx_hs_clk_phy.vhd ├── csi_rx_hs_lane_phy.vhd ├── csi_rx_idelayctrl_gen.vhd ├── csi_rx_line_buffer.vhd ├── csi_rx_packet_handler.vhd ├── csi_rx_top.vhd ├── csi_rx_video_output.vhd ├── csi_rx_word_align.vhd └── synth.ys ├── ov-cam-control ├── manual_focus.vhd ├── ov13850_4k_regs.vhd ├── ov13850_control_top.vhd ├── ov16825_1080p120_regs.vhd ├── ov_i2c_control.vhd └── vcm_i2c_control.vhd └── video-misc ├── image_gain_wb.vhd ├── simple_debayer.vhd ├── test_pattern_gen.vhd ├── video_fb_output.vhd ├── video_register.vhd └── video_timing_ctrl.vhd /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gatecat/CSI2Rx/HEAD/LICENSE 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