├── boot ├── boot.bin └── boot.mif ├── gb.qpf ├── ops ├── Makefile ├── gen.py ├── z80.bus ├── ops.txt └── cbops.txt ├── scripts ├── color.py ├── tomif.py ├── gbflash.py └── controls.py ├── memory ├── tram.qip ├── vram.qip ├── bgram.qip ├── hiram.qip ├── loram.qip ├── bootrom.qip ├── mbc1ram.qip ├── bootrom_bb.v ├── hiram_bb.v ├── loram_bb.v ├── mbc1ram_bb.v ├── tram_bb.v ├── bootrom.v ├── hiram.v ├── loram.v ├── mbc1ram.v ├── tram.v ├── vram_bb.v ├── bgram_bb.v ├── vram.v └── bgram.v ├── div.v ├── seg7.v ├── boot.v ├── audio.v ├── joypad.v ├── link.v ├── dma.v ├── inthandle.v ├── timer.v ├── mbc1.v ├── uart.v ├── mmap.v ├── z80_alu.v ├── sram.v ├── hdmi.v ├── README.md ├── z80.v ├── gb.v └── gb.sdc /boot/boot.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/geky/gb/HEAD/boot/boot.bin -------------------------------------------------------------------------------- /gb.qpf: -------------------------------------------------------------------------------- 1 | DATE = "23:22:14 December 01, 2014" 2 | QUARTUS_VERSION = "13.0" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "gb" 7 | -------------------------------------------------------------------------------- /ops/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: genops.txt gencbops.txt 3 | 4 | genops.txt: gen.py z80.bus ops.txt 5 | ./gen.py 1 z80.bus ops.txt > genops.txt 6 | 7 | gencbops.txt: gen.py z80.bus cbops.txt 8 | ./gen.py 2 z80.bus cbops.txt > gencbops.txt 9 | -------------------------------------------------------------------------------- /scripts/color.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python2 2 | 3 | import sys 4 | 5 | 6 | def main(): 7 | rgb = sys.argv[1:4] 8 | rgb = map(int, rgb) 9 | rgb = [a >> 3 for a in rgb] 10 | gb = (rgb[2] << 10) | (rgb[1] << 5) | rgb[0] 11 | print "16'h%x" % gb 12 | 13 | if __name__=="__main__": 14 | main() 15 | -------------------------------------------------------------------------------- /memory/tram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "tram_bb.v"] 6 | -------------------------------------------------------------------------------- /memory/vram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "vram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vram_bb.v"] 6 | -------------------------------------------------------------------------------- /memory/bgram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "bgram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "bgram_bb.v"] 6 | -------------------------------------------------------------------------------- /memory/hiram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hiram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hiram_bb.v"] 6 | -------------------------------------------------------------------------------- /memory/loram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "loram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "loram_bb.v"] 6 | -------------------------------------------------------------------------------- /memory/bootrom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "bootrom.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "bootrom_bb.v"] 6 | -------------------------------------------------------------------------------- /memory/mbc1ram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mbc1ram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mbc1ram_bb.v"] 6 | -------------------------------------------------------------------------------- /div.v: -------------------------------------------------------------------------------- 1 | // 2 | // Clock Divider 3 | // 4 | 5 | module div(in, out); 6 | 7 | // division amount 8 | parameter DIV = 1; 9 | parameter COUNT = DIV / 2; 10 | 11 | input in; 12 | output reg out; 13 | 14 | reg [$clog2(COUNT)-1:0] count = 0; 15 | 16 | always @(posedge in) begin 17 | if (count == COUNT-1) begin 18 | out <= ~out; 19 | count <= 0; 20 | end else begin 21 | count <= count + 1'b1; 22 | end 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /scripts/tomif.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python2 2 | 3 | import sys 4 | 5 | def main(): 6 | with open(sys.argv[1]) as f: 7 | data = f.read() 8 | 9 | print "-- Generated dump of %s" % sys.argv[1] 10 | 11 | print "WIDTH=8;" 12 | print "DEPTH=%s;" % len(data) 13 | print 14 | print "ADDRESS_RADIX=HEX;" 15 | print "DATA_RADIX=HEX;" 16 | print 17 | print "CONTENT BEGIN" 18 | 19 | for i,x in enumerate(data): 20 | print "\t%s\t:\t%s;" % (hex(i)[2:], hex(ord(x))[2:]) 21 | 22 | print "END;" 23 | 24 | 25 | 26 | if __name__ == "__main__": 27 | main() 28 | -------------------------------------------------------------------------------- /scripts/gbflash.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python2 2 | 3 | import sys 4 | import time 5 | 6 | def main(): 7 | assert len(sys.argv) == 5 8 | 9 | start = int(sys.argv[1], 16) 10 | count = int(sys.argv[2], 16) 11 | 12 | with open(sys.argv[3], 'rb') as input: 13 | data = input.read()[:count] 14 | 15 | with open(sys.argv[4], 'wb') as dev: 16 | putword(dev, start) 17 | putword(dev, count) 18 | 19 | for x in data: 20 | put(dev, x) 21 | 22 | 23 | def put(dev, x): 24 | dev.write(x) 25 | 26 | def putword(dev, x): 27 | put(dev, chr(0xff & (x >> 24))) 28 | put(dev, chr(0xff & (x >> 16))) 29 | put(dev, chr(0xff & (x >> 8))) 30 | put(dev, chr(0xff & (x ))) 31 | 32 | 33 | if __name__ == "__main__": 34 | main() 35 | -------------------------------------------------------------------------------- /seg7.v: -------------------------------------------------------------------------------- 1 | // 2 | // bit vectors to 7 segment display 3 | // 4 | 5 | module seg(data, hex); 6 | 7 | input [3:0] data; 8 | output reg [6:0] hex; 9 | 10 | always @(*) begin 11 | case (data) 12 | 4'h0: hex = 7'b1000000; 13 | 4'h1: hex = 7'b1111001; 14 | 4'h2: hex = 7'b0100100; 15 | 4'h3: hex = 7'b0110000; 16 | 4'h4: hex = 7'b0011001; 17 | 4'h5: hex = 7'b0010010; 18 | 4'h6: hex = 7'b0000010; 19 | 4'h7: hex = 7'b1111000; 20 | 4'h8: hex = 7'b0000000; 21 | 4'h9: hex = 7'b0011000; 22 | 4'ha: hex = 7'b0001000; 23 | 4'hb: hex = 7'b0000011; 24 | 4'hc: hex = 7'b1000110; 25 | 4'hd: hex = 7'b0100001; 26 | 4'he: hex = 7'b0000110; 27 | 4'hf: hex = 7'b0001110; 28 | endcase 29 | end 30 | 31 | endmodule 32 | 33 | 34 | 35 | module seg16(data, hexs); 36 | 37 | input [15:0] data; 38 | output [27:0] hexs; 39 | 40 | seg h0(data[15:12], hexs[27:21]); 41 | seg h1(data[11:8], hexs[20:14]); 42 | seg h2(data[7:4], hexs[13:7]); 43 | seg h3(data[3:0], hexs[6:0]); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /boot.v: -------------------------------------------------------------------------------- 1 | module boot( 2 | clockgb, resetn, 3 | address, indata, outdata, load, store, 4 | boot_active 5 | ); 6 | 7 | input clockgb; 8 | input resetn; 9 | 10 | input [15:0] address; 11 | input [7:0] indata; 12 | output [7:0] outdata; 13 | input load; 14 | input store; 15 | 16 | output boot_active = boot_load[1]; 17 | 18 | 19 | wire [15:0] boot_address; 20 | wire [7:0] boot_outdata; 21 | wire boot_preload; 22 | 23 | bootrom bootrom ( 24 | boot_address[7:0], 25 | clockgb, 26 | boot_outdata 27 | ); 28 | 29 | mmap #(16'h0000, 16'h00ff) rom_mmap( 30 | clockgb, resetn, 31 | address, indata, outdata, load, store, 32 | boot_address,, boot_outdata, boot_preload 33 | ); 34 | 35 | 36 | reg boot_enabled; 37 | reg boot_load [2]; 38 | 39 | always @(posedge clockgb or negedge resetn) begin 40 | if (!resetn) begin 41 | boot_enabled <= 1'b1; 42 | boot_load[0] <= 0; 43 | boot_load[0] <= 0; 44 | end else begin 45 | boot_load[0] <= boot_enabled && boot_preload; 46 | boot_load[1] <= boot_load[0]; 47 | 48 | if (disable_store) begin 49 | boot_enabled <= 1'b0; 50 | end 51 | end 52 | end 53 | 54 | 55 | wire disable_store; 56 | 57 | rrmmap #(16'hff50) disable_mmap( 58 | clockgb, resetn, 59 | address, indata,, load, store,,,,, 60 | disable_store 61 | ); 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /scripts/controls.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python2 2 | 3 | import sys 4 | import os 5 | import pygame 6 | 7 | KEY_A = pygame.K_RETURN 8 | KEY_B = pygame.K_QUOTE 9 | KEY_START = pygame.K_SPACE 10 | KEY_SELECT = pygame.K_e 11 | KEY_UP = pygame.K_w 12 | KEY_DOWN = pygame.K_s 13 | KEY_LEFT = pygame.K_a 14 | KEY_RIGHT = pygame.K_d 15 | 16 | def main(): 17 | assert len(sys.argv) == 2 18 | 19 | with open(sys.argv[1], 'wb') as output: 20 | pygame.init() 21 | pygame.display.set_mode((256,256)) 22 | pygame.display.set_caption("Input Here") 23 | 24 | print "Waiting for Input" 25 | 26 | prev_mask = 0 27 | 28 | while True: 29 | pygame.event.pump() 30 | keys = pygame.key.get_pressed() 31 | 32 | mask = 0 33 | 34 | if keys[KEY_A]: mask |= 0x01 35 | if keys[KEY_B]: mask |= 0x02 36 | if keys[KEY_SELECT]: mask |= 0x04 37 | if keys[KEY_START]: mask |= 0x08 38 | if keys[KEY_RIGHT]: mask |= 0x10 39 | if keys[KEY_LEFT]: mask |= 0x20 40 | if keys[KEY_UP]: mask |= 0x40 41 | if keys[KEY_DOWN]: mask |= 0x80 42 | 43 | if mask != prev_mask: 44 | output.write(chr(mask)) 45 | output.flush() 46 | prev_mask = mask 47 | 48 | 49 | if __name__=="__main__": 50 | main() 51 | -------------------------------------------------------------------------------- /audio.v: -------------------------------------------------------------------------------- 1 | module audio( 2 | clock25mhz, clock12500khz, resetn, 3 | sample, 4 | 5 | //////////// Audio ////////// 6 | AUD_ADCDAT, 7 | AUD_ADCLRCK, 8 | AUD_BCLK, 9 | AUD_DACDAT, 10 | AUD_DACLRCK, 11 | AUD_XCK 12 | ); 13 | 14 | input clock25mhz; 15 | input clock12500khz; 16 | input resetn; 17 | 18 | input [23:0] sample; 19 | 20 | //////////// Audio ////////// 21 | input AUD_ADCDAT; 22 | inout AUD_ADCLRCK; 23 | inout AUD_BCLK = ~clock12500khz; 24 | output AUD_DACDAT = pbdat; 25 | inout AUD_DACLRCK = pblrc; 26 | output AUD_XCK = ~clock25mhz; 27 | 28 | 29 | reg [23:0] buffer; 30 | reg [4:0] buffer_ctr; 31 | 32 | reg pblrc; 33 | reg pbdat; 34 | 35 | reg [1:0] state; 36 | 37 | 38 | always @(posedge clock12500khz or negedge resetn) begin 39 | if (!resetn) begin 40 | state <= 0; 41 | pblrc <= 1; 42 | pbdat <= 0; 43 | end else begin 44 | if (state == 0) begin 45 | buffer <= sample; 46 | pblrc <= 0; 47 | pbdat <= buffer[23]; 48 | buffer_ctr <= 23; 49 | state <= 1; 50 | end else if (state == 1) begin 51 | pblrc <= 0; 52 | pbdat <= buffer[buffer_ctr]; 53 | 54 | if (buffer_ctr == 0) begin 55 | buffer_ctr <= 23; 56 | state <= 2; 57 | end else begin 58 | buffer_ctr <= buffer_ctr - 1'b1; 59 | state <= 1; 60 | end 61 | end else if (state == 2) begin 62 | pblrc <= 1; 63 | pbdat <= buffer[buffer_ctr]; 64 | 65 | if (buffer_ctr == 0) begin 66 | buffer_ctr <= 23; 67 | state <= 3; 68 | end else begin 69 | buffer_ctr <= buffer_ctr - 1'b1; 70 | state <= 2; 71 | end 72 | end else begin 73 | buffer <= sample; 74 | pblrc <= 1; 75 | pbdat <= 0; 76 | buffer_ctr <= 23; 77 | state <= 1; 78 | end 79 | end 80 | end 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /joypad.v: -------------------------------------------------------------------------------- 1 | module joypad( 2 | clock460800hz, clockgb, resetn, joy_int, 3 | address, indata, outdata, load, store, 4 | 5 | //////////// Uart to USB ////////// 6 | UART_RX, 7 | UART_TX 8 | ); 9 | 10 | input clock460800hz; 11 | input clockgb; 12 | input resetn; 13 | output reg joy_int; 14 | 15 | input [15:0] address; 16 | input [7:0] indata; 17 | output [7:0] outdata; 18 | input load; 19 | input store; 20 | 21 | input UART_RX; 22 | output UART_TX = 1'b1; 23 | 24 | 25 | reg [1:0] joy_sel; 26 | reg [7:0] joy_buttons; 27 | 28 | reg [7:0] joy_outdata; 29 | 30 | always @(*) begin 31 | joy_outdata = {2'b0, joy_sel, 4'hf}; 32 | 33 | if (joy_sel[0]) begin 34 | joy_outdata = joy_outdata & ~joy_buttons[3:0]; 35 | end 36 | 37 | if (joy_sel[1]) begin 38 | joy_outdata = joy_outdata & ~joy_buttons[7:4]; 39 | end 40 | end 41 | 42 | 43 | wire [7:0] uart_data; 44 | wire uart_recv; 45 | 46 | uartrx uartrx( 47 | clock460800hz, resetn, uart_data, uart_recv, 48 | UART_RX 49 | ); 50 | 51 | always @(posedge clockgb or negedge resetn) begin 52 | if (!resetn) begin 53 | joy_sel <= 0; 54 | joy_buttons <= 0; 55 | joy_int <= 0; 56 | end else begin 57 | joy_int <= 0; 58 | 59 | if (joy_store) begin 60 | joy_sel <= joy_indata[5:4]; 61 | end 62 | 63 | if (uart_recv) begin 64 | joy_buttons <= uart_data; 65 | 66 | if (uart_data & ~joy_buttons) begin 67 | joy_int <= 1'b1; 68 | end 69 | end 70 | end 71 | end 72 | 73 | 74 | wire [7:0] joy_indata; 75 | wire joy_store; 76 | 77 | rrmmap #(16'hff00) joy_mmap( 78 | clockgb, resetn, 79 | address, indata, outdata, load, store,, 80 | joy_indata, joy_outdata,, joy_store 81 | ); 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /link.v: -------------------------------------------------------------------------------- 1 | module link( 2 | clock115200hz, clockgb, resetn, 3 | address, indata, outdata, load, store, 4 | 5 | //////////// Uart to USB ////////// 6 | UART_RX, 7 | UART_TX 8 | ); 9 | 10 | 11 | input clock115200hz; 12 | input clockgb; 13 | input resetn; 14 | 15 | input [15:0] address; 16 | input [7:0] indata; 17 | output [7:0] outdata; 18 | input load; 19 | input store; 20 | 21 | input UART_RX; 22 | output UART_TX = tx; 23 | 24 | 25 | reg [7:0] data; 26 | reg sending; 27 | 28 | reg [3:0] state; 29 | reg tx; 30 | 31 | 32 | always @(posedge clock115200hz or negedge resetn) begin 33 | if (!resetn) begin 34 | tx <= 1'b1; 35 | state <= 0; 36 | end else begin 37 | if (state == 0) begin 38 | tx <= 1'b1; 39 | state <= sending ? 4'h1 : 4'h0; 40 | end else begin 41 | tx <= state == 4'h1 ? 1'h0 : data[state-2]; 42 | state <= state == 4'h9 ? 4'h0 : state + 1'b1; 43 | end 44 | end 45 | end 46 | 47 | always @(posedge clockgb or negedge resetn) begin 48 | if (!resetn) begin 49 | data <= 0; 50 | sending <= 0; 51 | end else begin 52 | if (sio_store) begin 53 | sending <= sio_indata[7]; 54 | end else if (state != 0) begin 55 | sending <= 0; 56 | end 57 | 58 | if (data_store) begin 59 | data <= data_indata; 60 | end 61 | end 62 | end 63 | 64 | 65 | wire [7:0] data_indata; 66 | wire [7:0] data_data; 67 | wire data_store; 68 | 69 | rrmmap #(16'hff01) data_mmap( 70 | clockgb, resetn, 71 | address, indata, data_data, load, store,, 72 | data_indata, data,, data_store 73 | ); 74 | 75 | wire [7:0] sio_indata; 76 | wire [7:0] sio_data; 77 | wire sio_store; 78 | 79 | rrmmap #(16'hff02) sio_mmap( 80 | clockgb, resetn, 81 | address, indata, sio_data, load, store,, 82 | sio_indata, {state != 0 || sending, 7'h00},, sio_store 83 | ); 84 | 85 | wire [7:0] outdata = data_data | sio_data; 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /dma.v: -------------------------------------------------------------------------------- 1 | module dma( 2 | clockgb, resetn, 3 | address, indata, outdata, load, store, 4 | dma_address, dma_indata, dma_outdata, dma_load, dma_store, 5 | dma_active 6 | ); 7 | 8 | parameter DMA_COUNT = 8'ha0; 9 | parameter DMA_DEST = 8'hfe; 10 | 11 | input clockgb; 12 | input resetn; 13 | 14 | input [15:0] address; 15 | input [7:0] indata; 16 | output [7:0] outdata; 17 | input load; 18 | input store; 19 | 20 | output reg [15:0] dma_address; 21 | input [7:0] dma_indata; 22 | output reg [7:0] dma_outdata; 23 | output reg dma_load; 24 | output reg dma_store; 25 | 26 | 27 | output reg dma_active; 28 | reg [7:0] dma_hi; 29 | reg [7:0] dma_lo; 30 | reg [1:0] dma_state; 31 | reg [7:0] dma_temp; 32 | 33 | always @(*) begin 34 | if (dma_state < 2) begin 35 | dma_address = {dma_hi, dma_lo}; 36 | end else begin 37 | dma_address = {DMA_DEST, dma_lo}; 38 | end 39 | 40 | if (dma_active) begin 41 | dma_load = (dma_state == 0); 42 | dma_store = (dma_state == 3); 43 | end else begin 44 | dma_load = 0; 45 | dma_store = 0; 46 | end 47 | end 48 | 49 | always @(posedge clockgb or negedge resetn) begin 50 | if (!resetn) begin 51 | dma_hi <= 0; 52 | dma_lo <= 0; 53 | dma_active <= 0; 54 | dma_state <= 0; 55 | end else begin 56 | if (dmac_store) begin 57 | dma_hi <= dmac_indata; 58 | dma_lo <= 0; 59 | dma_active <= 1'b1; 60 | dma_state <= 0; 61 | end 62 | 63 | if (dma_active) begin 64 | if (dma_state == 3) begin 65 | if (dma_lo + 1'b1 == DMA_COUNT) begin 66 | dma_active <= 0; 67 | end 68 | 69 | dma_lo <= dma_lo + 1'b1; 70 | end 71 | 72 | dma_state <= dma_state + 1'b1; 73 | dma_outdata <= dma_indata; 74 | end 75 | end 76 | end 77 | 78 | 79 | wire [7:0] dmac_indata; 80 | wire dmac_store; 81 | 82 | rrmmap #(16'hff46) dmac_mmap( 83 | clockgb, resetn, 84 | address, indata, outdata, load, store,, 85 | dmac_indata, dma_hi,, dmac_store 86 | ); 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /inthandle.v: -------------------------------------------------------------------------------- 1 | module inthandle( 2 | clockgb, resetn, 3 | address, indata, outdata, load, store, 4 | interrupts, 5 | intreq, intaddress, intack, 6 | dints 7 | ); 8 | 9 | input clockgb; 10 | input resetn; 11 | 12 | input [15:0] address; 13 | input [7:0] indata; 14 | output [7:0] outdata; 15 | input load; 16 | input store; 17 | 18 | input [4:0] interrupts; 19 | output reg intreq; 20 | output reg [15:0] intaddress; 21 | input intack; 22 | 23 | output [4:0] dints = intf; 24 | 25 | 26 | reg [2:0] intnum; 27 | 28 | reg [4:0] intf; 29 | reg [4:0] inte; 30 | 31 | 32 | always @(*) begin 33 | integer i; 34 | 35 | intreq = 1'b0; 36 | intnum = 1'b0; 37 | 38 | for (i=5-1; i >= 0; i=i-1) begin 39 | if (intf[i] && inte[i]) begin 40 | intreq = 1'b1; 41 | intnum = i[2:0]; 42 | end 43 | end 44 | 45 | case (intnum) 46 | 0: intaddress = 16'h40; 47 | 1: intaddress = 16'h48; 48 | 2: intaddress = 16'h50; 49 | 3: intaddress = 16'h58; 50 | 4: intaddress = 16'h60; 51 | default: intaddress = 16'h00; 52 | endcase 53 | end 54 | 55 | always @(posedge clockgb or negedge resetn) begin 56 | integer i; 57 | 58 | if (!resetn) begin 59 | intf <= 0; 60 | inte <= 0; 61 | end else begin 62 | for (i=0; i < 5; i=i+1) begin 63 | if (interrupts[i]) begin 64 | intf[i] <= 1'b1; 65 | end else if (intreq && intack && i == intnum) begin 66 | intf[i] <= 1'b0; 67 | end 68 | end 69 | 70 | if (intf_store) begin 71 | intf <= intf_indata; 72 | end 73 | if (inte_store) begin 74 | inte <= inte_indata; 75 | end 76 | end 77 | end 78 | 79 | 80 | wire [4:0] intf_indata; 81 | wire [7:0] intf_data; 82 | wire intf_store; 83 | 84 | rrmmap #(16'hff0f) intf_mmap( 85 | clockgb, resetn, 86 | address, indata, intf_data, load, store,, 87 | intf_indata, intf,, intf_store 88 | ); 89 | 90 | wire [4:0] inte_indata; 91 | wire [7:0] inte_data; 92 | wire inte_store; 93 | 94 | rrmmap #(16'hffff) inte_mmap( 95 | clockgb, resetn, 96 | address, indata, inte_data, load, store,, 97 | inte_indata, inte,, inte_store 98 | ); 99 | 100 | assign outdata = intf_data | inte_data; 101 | 102 | endmodule 103 | -------------------------------------------------------------------------------- /timer.v: -------------------------------------------------------------------------------- 1 | module timer( 2 | clockgb, resetn, overflow_int, 3 | address, indata, outdata, load, store, 4 | dtimer 5 | ); 6 | 7 | input clockgb; 8 | input resetn; 9 | output overflow_int = overflow; 10 | 11 | input [15:0] address; 12 | input [7:0] indata; 13 | output [7:0] outdata; 14 | input load; 15 | input store; 16 | 17 | output [7:0] dtimer = timer; 18 | 19 | 20 | reg [7:0] tma; 21 | reg [7:0] tac; 22 | 23 | reg [15:0] tdiv; 24 | reg [7:0] timer; 25 | reg [15:0] ndiv; 26 | reg [7:0] ntimer; 27 | reg increment; 28 | reg overflow; 29 | 30 | always @(*) begin 31 | ndiv = tdiv + 1'b1; 32 | 33 | case (tac[1:0]) 34 | 1: increment = !ndiv[3] && tdiv[3]; 35 | 2: increment = !ndiv[5] && tdiv[5]; 36 | 3: increment = !ndiv[7] && tdiv[7]; 37 | 0: increment = !ndiv[9] && tdiv[9]; 38 | endcase 39 | 40 | if (tac[2] && increment) begin 41 | if ({1'b0, timer} + 1'b1 > 8'hff) begin 42 | overflow = 1'b1; 43 | ntimer = tma; 44 | end else begin 45 | overflow = 0; 46 | ntimer = timer + 1'b1; 47 | end 48 | end else begin 49 | overflow = 0; 50 | ntimer = timer; 51 | end 52 | end 53 | 54 | 55 | always @(posedge clockgb or negedge resetn) begin 56 | if (!resetn) begin 57 | timer <= 0; 58 | tdiv <= 0; 59 | tma <= 0; 60 | tac <= 0; 61 | end else begin 62 | tdiv <= ndiv; 63 | timer <= ntimer; 64 | 65 | if (timer_store) begin 66 | timer <= timer_indata; 67 | end 68 | if (tdiv_store) begin 69 | tdiv <= 0; 70 | end 71 | if (tma_store) begin 72 | tma <= tma_indata; 73 | end 74 | if (tac_store) begin 75 | tac <= tac_indata; 76 | end 77 | end 78 | end 79 | 80 | 81 | wire [7:0] tdiv_data; 82 | wire tdiv_store; 83 | 84 | rrmmap #(16'hff04) tdiv_mmap( 85 | clockgb, resetn, 86 | address, indata, tdiv_data, load, store,,, 87 | tdiv[15:8],, tdiv_store 88 | ); 89 | 90 | wire [7:0] timer_indata; 91 | wire [7:0] timer_data; 92 | wire timer_store; 93 | 94 | rrmmap #(16'hff05) timer_mmap( 95 | clockgb, resetn, 96 | address, indata, timer_data, load, store,, 97 | timer_indata, timer,, timer_store 98 | ); 99 | 100 | wire [7:0] tma_indata; 101 | wire [7:0] tma_data; 102 | wire tma_store; 103 | 104 | rrmmap #(16'hff06) tma_mmap( 105 | clockgb, resetn, 106 | address, indata, tma_data, load, store,, 107 | tma_indata, tma,, tma_store 108 | ); 109 | 110 | wire [7:0] tac_indata; 111 | wire [7:0] tac_data; 112 | wire tac_store; 113 | 114 | rrmmap #(16'hff07) tac_mmap( 115 | clockgb, resetn, 116 | address, indata, tac_data, load, store,, 117 | tac_indata, tac,, tac_store 118 | ); 119 | 120 | assign outdata = tdiv_data | timer_data | tma_data | tac_data; 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /mbc1.v: -------------------------------------------------------------------------------- 1 | module mbc1( 2 | clockgb, clock115200hz, clock460800hz, resetn, 3 | address, indata, outdata, load, store, prog, 4 | 5 | //////////// Uart to USB ////////// 6 | UART_RX, 7 | UART_TX, 8 | 9 | //////////// SRAM ////////// 10 | SRAM_A, 11 | SRAM_CE_n, 12 | SRAM_D, 13 | SRAM_LB_n, 14 | SRAM_OE_n, 15 | SRAM_UB_n, 16 | SRAM_WE_n 17 | ); 18 | 19 | input clockgb; 20 | input clock115200hz; 21 | input clock460800hz; 22 | input resetn; 23 | 24 | input [15:0] address; 25 | input [7:0] indata; 26 | output [7:0] outdata; 27 | input load; 28 | input store; 29 | input prog; 30 | 31 | //////////// Uart to USB ////////// 32 | input UART_RX; 33 | output UART_TX; 34 | 35 | //////////// SRAM ////////// 36 | output [17:0] SRAM_A; 37 | inout [15:0] SRAM_D; 38 | output SRAM_CE_n; 39 | output SRAM_UB_n; 40 | output SRAM_LB_n; 41 | output SRAM_OE_n; 42 | output SRAM_WE_n; 43 | 44 | 45 | // Banked ROM // 46 | reg [18:0] sram_address; 47 | wire [7:0] sram_data; 48 | 49 | sram cart_sram( 50 | clockgb, clock115200hz, clock460800hz, resetn, 51 | sram_address,, sram_data, load, 1'b0, prog, 52 | 53 | //////////// Uart to USB ////////// 54 | UART_RX, 55 | UART_TX, 56 | 57 | //////////// SRAM ////////// 58 | SRAM_A, 59 | SRAM_CE_n, 60 | SRAM_D, 61 | SRAM_LB_n, 62 | SRAM_OE_n, 63 | SRAM_UB_n, 64 | SRAM_WE_n 65 | ); 66 | 67 | 68 | reg [4:0] bank; 69 | 70 | always @(*) begin 71 | if (rom_address < 16'h4000) begin 72 | sram_address = {5'b0, rom_address[13:0]}; 73 | end else begin 74 | sram_address = {bank, rom_address[13:0]}; 75 | end 76 | end 77 | 78 | always @(posedge clockgb or negedge resetn) begin 79 | if (!resetn) begin 80 | bank <= 5'b1; 81 | end else begin 82 | if (bank_store) begin 83 | if (bank_indata[4:0] == 0) begin 84 | bank <= 5'b1; 85 | end else begin 86 | bank <= bank_indata[4:0]; 87 | end 88 | end 89 | end 90 | end 91 | 92 | 93 | wire [15:0] rom_address; 94 | wire [7:0] rom_data; 95 | 96 | mmap #(16'h0000, 16'h7fff) rom_mmap( 97 | clockgb, resetn, 98 | address, indata, rom_data, load, store, 99 | rom_address,, sram_data 100 | ); 101 | 102 | wire [7:0] bank_indata; 103 | wire bank_store; 104 | 105 | mmap #(16'h2000, 16'h3fff) bank_mmap( 106 | clockgb, resetn, 107 | address, indata,, load, store,, 108 | bank_indata,,, bank_store 109 | ); 110 | 111 | 112 | // Banked RAM // 113 | wire [15:0] ram_address; 114 | wire [7:0] ram_indata; 115 | wire [7:0] ram_outdata; 116 | wire [7:0] ram_data; 117 | wire ram_store; 118 | 119 | mbc1ram ram( 120 | ram_address[12:0], 121 | clockgb, 122 | ram_indata, 123 | ram_store, 124 | ram_outdata 125 | ); 126 | 127 | mmap #(16'ha000, 16'hbfff) ram_mmap( 128 | clockgb, resetn, 129 | address, outdata, ram_data, load, store, 130 | ram_address, ram_indata, ram_outdata,, ram_store 131 | ); 132 | 133 | assign outdata = rom_data | ram_data; 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /uart.v: -------------------------------------------------------------------------------- 1 | // 2 | // UART interface 3 | // 4 | 5 | module uarttx( 6 | clock115200hz, resetn, data, send, ready, 7 | UART_TX 8 | ); 9 | 10 | input clock115200hz; 11 | input resetn; 12 | input [7:0] data; 13 | input send; 14 | output reg ready; 15 | output UART_TX = tx; 16 | 17 | reg tx; 18 | reg [3:0] state; 19 | 20 | always @(posedge clock115200hz or negedge resetn) begin 21 | if (!resetn) begin 22 | tx <= 1'b1; 23 | ready <= 0; 24 | state <= 0; 25 | end else begin 26 | if (state == 0) begin 27 | tx <= 1'b1; 28 | ready <= send ? 1'b0 : 1'b1; 29 | state <= send ? 4'h1 : 4'h0; 30 | end else begin 31 | tx <= state == 4'h1 ? 1'b0 : data[state-2]; 32 | state <= state == 4'h9 ? 4'h0 : state + 1'b1; 33 | end 34 | end 35 | end 36 | 37 | endmodule 38 | 39 | 40 | module cheapuartrx( 41 | clock115200hz, resetn, data, recv, 42 | UART_RX 43 | ); 44 | 45 | input clock115200hz; 46 | input resetn; 47 | output reg [7:0] data; 48 | output reg recv; 49 | input UART_RX; 50 | 51 | wire rx = UART_RX; 52 | reg [3:0] state; 53 | reg [7:0] buffer; 54 | 55 | always @(posedge clock115200hz or negedge resetn) begin 56 | if (!resetn) begin 57 | data <= 0; 58 | recv <= 0; 59 | state <= 0; 60 | end else begin 61 | if (state == 0) begin 62 | recv <= 1'b0; 63 | state <= rx == 1'b0 ? 4'h1 : 4'h0; 64 | end else if (state != 9) begin 65 | buffer[state-1] <= rx; 66 | state <= state + 1'b1; 67 | end else begin 68 | data <= buffer; 69 | recv <= 1'b1; 70 | state <= 4'h0; 71 | end 72 | end 73 | end 74 | 75 | endmodule 76 | 77 | 78 | module uartrx( 79 | clock460800, resetn, data, recv, 80 | UART_RX 81 | ); 82 | 83 | input clock460800; 84 | input resetn; 85 | output reg [7:0] data; 86 | output reg recv; 87 | input UART_RX; 88 | 89 | wire rx = UART_RX; 90 | reg [3:0] state; 91 | reg [1:0] step; 92 | reg [7:0] buffer; 93 | reg [2:0] count; 94 | 95 | always @(posedge clock460800 or negedge resetn) begin 96 | if (!resetn) begin 97 | data <= 0; 98 | recv <= 0; 99 | state <= 0; 100 | end else begin 101 | if (state == 0) begin 102 | recv <= 1'b0; 103 | state <= rx == 1'b0 ? 4'h1 : 4'h0; 104 | step <= 1'h1; 105 | end else if (state == 1) begin 106 | if (step != 2'h3) begin 107 | step <= step + 1'b1; 108 | end else begin 109 | state <= state + 1'b1; 110 | count <= 0; 111 | step <= 0; 112 | end 113 | end else if (state != 10) begin 114 | if (step != 2'h3) begin 115 | count <= count + rx; 116 | step <= step + 1'b1; 117 | end else begin 118 | buffer[state-2] <= (count+rx) > 2; 119 | state <= state + 1'b1; 120 | count <= 0; 121 | step <= 0; 122 | end 123 | end else begin 124 | data <= buffer; 125 | recv <= 1'b1; 126 | 127 | if (step != 2'h3) begin 128 | step <= step + 1'b1; 129 | end else begin 130 | state <= 4'h0; 131 | end 132 | end 133 | end 134 | end 135 | 136 | endmodule 137 | -------------------------------------------------------------------------------- /mmap.v: -------------------------------------------------------------------------------- 1 | module mmap( 2 | clock, resetn, 3 | m_address, m_indata, m_outdata, m_load, m_store, 4 | address, indata, outdata, load, store 5 | ); 6 | 7 | parameter START; 8 | parameter END = START; 9 | 10 | input clock; 11 | input resetn; 12 | 13 | input [15:0] m_address; 14 | input [7:0] m_indata; 15 | output reg [7:0] m_outdata; 16 | input m_load; 17 | input m_store; 18 | 19 | output reg [15:0] address; 20 | output reg [7:0] indata; 21 | input [7:0] outdata; 22 | output reg load; 23 | output reg store; 24 | 25 | reg [15:0] r_load [2]; 26 | 27 | always @(*) begin 28 | if (m_address >= START && m_address <= END) begin 29 | address = m_address - START; 30 | indata = m_indata; 31 | load = m_load; 32 | store = m_store; 33 | end else begin 34 | address = 0; 35 | indata = 0; 36 | load = 0; 37 | store = 0; 38 | end 39 | 40 | if (r_load[1]) begin 41 | m_outdata = outdata; 42 | end else begin 43 | m_outdata = 0; 44 | end 45 | end 46 | 47 | always @(posedge clock or negedge resetn) begin 48 | if (!resetn) begin 49 | r_load[0] <= 0; 50 | r_load[1] <= 0; 51 | end else begin 52 | r_load[0] <= load; 53 | r_load[1] <= r_load[0]; 54 | end 55 | end 56 | 57 | endmodule 58 | 59 | 60 | module rmmap( 61 | clock, resetn, 62 | m_address, m_indata, m_outdata, m_load, m_store, 63 | address, indata, outdata, load, store 64 | ); 65 | 66 | parameter START; 67 | parameter END = START; 68 | 69 | input clock; 70 | input resetn; 71 | 72 | input [15:0] m_address; 73 | input [7:0] m_indata; 74 | output [7:0] m_outdata; 75 | input m_load; 76 | input m_store; 77 | 78 | output reg [15:0] address; 79 | output reg [7:0] indata; 80 | input [7:0] outdata; 81 | output reg load; 82 | output reg store; 83 | 84 | wire [15:0] r_address; 85 | wire [7:0] r_indata; 86 | wire r_load; 87 | wire r_store; 88 | 89 | mmap #(START, END) mmap( 90 | clock, resetn, 91 | m_address, m_indata, m_outdata, m_load, m_store, 92 | r_address, r_indata, outdata, r_load, r_store 93 | ); 94 | 95 | always @(posedge clock or negedge resetn) begin 96 | if (!resetn) begin 97 | address <= 0; 98 | indata <= 0; 99 | load <= 0; 100 | store <= 0; 101 | end else begin 102 | address <= r_address; 103 | indata <= r_indata; 104 | load <= r_load; 105 | store <= r_store; 106 | end 107 | end 108 | 109 | endmodule 110 | 111 | 112 | module rrmmap( 113 | clock, resetn, 114 | m_address, m_indata, m_outdata, m_load, m_store, 115 | address, indata, outdata, load, store 116 | ); 117 | 118 | parameter START; 119 | parameter END = START; 120 | 121 | input clock; 122 | input resetn; 123 | 124 | input [15:0] m_address; 125 | input [7:0] m_indata; 126 | output [7:0] m_outdata; 127 | input m_load; 128 | input m_store; 129 | 130 | output [15:0] address; 131 | output [7:0] indata; 132 | input [7:0] outdata; 133 | output load; 134 | output store; 135 | 136 | reg [7:0] r_outdata; 137 | 138 | rmmap #(START, END) rmmap( 139 | clock, resetn, 140 | m_address, m_indata, m_outdata, m_load, m_store, 141 | address, indata, r_outdata, load, store 142 | ); 143 | 144 | always @(posedge clock or negedge resetn) begin 145 | if (!resetn) begin 146 | r_outdata <= 0; 147 | end else begin 148 | r_outdata <= outdata; 149 | end 150 | end 151 | 152 | endmodule 153 | 154 | -------------------------------------------------------------------------------- /z80_alu.v: -------------------------------------------------------------------------------- 1 | module z80_alu(d, op, a, b, f, nf); 2 | 3 | input [4:0] op; 4 | input [15:0] a; 5 | input [15:0] b; 6 | output reg [15:0] d; 7 | input [3:0] f; 8 | output [3:0] nf; 9 | 10 | wire n = f[2]; 11 | wire h = f[1]; 12 | wire c = f[0]; 13 | 14 | assign nf = {nz, 1'bx, nh, nc}; 15 | wire nz = (d[7:0] == 0); 16 | reg nh; 17 | reg nc; 18 | 19 | 20 | always @(*) begin 21 | case (op) 22 | OR: d = {a[15:8], a[7:0] | b[7:0]}; 23 | AND: d = {a[15:8], a[7:0] & b[7:0]}; 24 | XOR: d = {a[15:8], a[7:0] ^ b[7:0]}; 25 | CPL: d = ~a; 26 | 27 | ADD: d = a + b; 28 | ADC: d = a + b + c; 29 | ADD2: d = a + b; 30 | SUB: d = a - b; 31 | SBC: d = a - b - c; 32 | 33 | RLC: d = {8'h00, a[6:0], a[7]}; 34 | RL: d = {8'h00, a[6:0], c}; 35 | RRC: d = {8'h00, a[0], a[7:1]}; 36 | RR: d = {8'h00, c, a[7:1]}; 37 | SLA: d = {8'h00, a[6:0], 1'b0}; 38 | SRA: d = {8'h00, a[7], a[7:1]}; 39 | SRL: d = {8'h00, 1'b0, a[7:1]}; 40 | 41 | SWAP: d = {8'h00, a[3:0], a[7:4]}; 42 | SWAP2: d = {a[7:0], a[15:8]}; 43 | 44 | DAA: begin 45 | d = a; 46 | 47 | if (n) begin 48 | if (c) d[7:0] = d[7:0] - 8'h60; 49 | if (h) d[7:0] = d[7:0] - 8'h06; 50 | end else begin 51 | if (c || d[7:0] > 8'h99) d[7:0] = d[7:0] + 8'h60; 52 | if (h || d[3:0] > 8'h09) d[7:0] = d[7:0] + 8'h06; 53 | end 54 | end 55 | default: d = 0; 56 | endcase 57 | end 58 | 59 | 60 | reg [16:0] hspace; 61 | reg [16:0] cspace; 62 | 63 | always @(*) begin 64 | nh = 0; 65 | nc = 0; 66 | hspace = 0; 67 | cspace = 0; 68 | 69 | case (op) 70 | ADD: begin hspace = ({1'b0, a[3:0]} + {1'b0, b[3:0]}); nh = hspace[4]; 71 | cspace = ({1'b0, a[7:0]} + {1'b0, b[7:0]}); nc = cspace[8]; end 72 | ADC: begin hspace = ({1'b0, a[3:0]} + {1'b0, b[3:0]} + c); nh = hspace[4]; 73 | cspace = ({1'b0, a[7:0]} + {1'b0, b[7:0]} + c); nc = cspace[8]; end 74 | ADD2: begin hspace = ({1'b0, a[11:0]} + {1'b0, b[11:0]}); nh = hspace[12]; 75 | cspace = ({1'b0, a[15:0]} + {1'b0, b[15:0]}); nc = cspace[16]; end 76 | SUB: begin hspace = ({1'b0, a[3:0]} - {1'b0, b[3:0]}); nh = hspace[4]; 77 | cspace = ({1'b0, a[7:0]} - {1'b0, b[7:0]}); nc = cspace[8]; end 78 | SBC: begin hspace = ({1'b0, a[3:0]} - {1'b0, b[3:0]} - c); nh = hspace[4]; 79 | cspace = ({1'b0, a[7:0]} - {1'b0, b[7:0]} - c); nc = cspace[8]; end 80 | 81 | RLC: nc = a[7]; 82 | RL: nc = a[7]; 83 | RRC: nc = a[0]; 84 | RR: nc = a[0]; 85 | SLA: nc = a[7]; 86 | SRA: nc = a[0]; 87 | SRL: nc = a[0]; 88 | DAA: nc = !n && a[7:0] > 8'h99; 89 | default: nc = 0; 90 | endcase 91 | end 92 | 93 | 94 | parameter OR = 5'h00; 95 | parameter AND = 5'h01; 96 | parameter XOR = 5'h02; 97 | parameter CPL = 5'h03; 98 | parameter ADD2 = 5'h04; 99 | parameter ADD = 5'h05; 100 | parameter ADC = 5'h06; 101 | parameter SUB = 5'h07; 102 | parameter SBC = 5'h08; 103 | parameter RLC = 5'h09; 104 | parameter RL = 5'h0a; 105 | parameter RRC = 5'h0b; 106 | parameter RR = 5'h0c; 107 | parameter SLA = 5'h0d; 108 | parameter SRA = 5'h0e; 109 | parameter SRL = 5'h0f; 110 | parameter SWAP = 5'h10; 111 | parameter SWAP2 = 5'h11; 112 | parameter DAA = 5'h12; 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /sram.v: -------------------------------------------------------------------------------- 1 | module sram( 2 | clock, clock115200hz, clock460800hz, resetn, 3 | address, indata, outdata, load, store, prog, 4 | 5 | //////////// Uart to USB ////////// 6 | UART_RX, 7 | UART_TX, 8 | 9 | //////////// SRAM ////////// 10 | SRAM_A, 11 | SRAM_CE_n, 12 | SRAM_D, 13 | SRAM_LB_n, 14 | SRAM_OE_n, 15 | SRAM_UB_n, 16 | SRAM_WE_n 17 | ); 18 | 19 | input clock; 20 | input clock115200hz; 21 | input clock460800hz; 22 | input resetn; 23 | 24 | input [18:0] address; 25 | input [7:0] indata; 26 | output reg [7:0] outdata; 27 | input load; 28 | input store; 29 | input prog; 30 | 31 | //////////// Uart to USB ////////// 32 | input UART_RX; 33 | output UART_TX; 34 | 35 | //////////// SRAM ////////// 36 | output [17:0] SRAM_A = ram_address[18:1]; 37 | inout [15:0] SRAM_D = ram_bus; 38 | output SRAM_CE_n = ~1'b1; 39 | output SRAM_UB_n = ~ram_bytes[1]; 40 | output SRAM_LB_n = ~ram_bytes[0]; 41 | output SRAM_OE_n = ~ram_load; 42 | output SRAM_WE_n = ~ram_store; 43 | 44 | 45 | wire [15:0] ram_bus = ram_store ? {ram_outdata, ram_outdata} : 16'hzzzz; 46 | wire [1:0] ram_bytes = ram_address[0] ? 2'b01 : 2'b10; 47 | 48 | reg [18:0] ram_address; 49 | reg [7:0] ram_outdata; 50 | reg ram_load; 51 | reg ram_store; 52 | 53 | wire [7:0] ram_indata = ram_address[0] ? SRAM_D[7:0] : SRAM_D[15:8]; 54 | 55 | 56 | wire [7:0] uart_data; 57 | wire uart_recv; 58 | reg uart_recv_ack; 59 | 60 | uartrx comm_uart (clock460800hz, resetn, uart_data, uart_recv, UART_RX); 61 | uarttx check_uart (clock115200hz, resetn, uart_data, uart_recv, , UART_TX); 62 | 63 | 64 | reg [31:0] flash_address; 65 | reg [31:0] flash_count; 66 | reg [3:0] flash_state; 67 | 68 | always @(posedge clock or negedge resetn) begin 69 | if (!resetn) begin 70 | ram_address <= 0; 71 | ram_outdata <= 0; 72 | ram_load <= 0; 73 | ram_store <= 0; 74 | outdata <= 0; 75 | 76 | flash_state <= 0; 77 | uart_recv_ack <= 0; 78 | end else if (prog) begin 79 | uart_recv_ack <= uart_recv; 80 | 81 | if (uart_recv && !uart_recv_ack) begin 82 | case (flash_state) 83 | 4'h0: begin flash_state <= 4'h1; flash_address <= {flash_address[23:0], uart_data}; end 84 | 4'h1: begin flash_state <= 4'h2; flash_address <= {flash_address[23:0], uart_data}; end 85 | 4'h2: begin flash_state <= 4'h3; flash_address <= {flash_address[23:0], uart_data}; end 86 | 4'h3: begin flash_state <= 4'h4; flash_address <= {flash_address[23:0], uart_data}; end 87 | 4'h4: begin flash_state <= 4'h5; flash_count <= {flash_count[23:0], uart_data}; end 88 | 4'h5: begin flash_state <= 4'h6; flash_count <= {flash_count[23:0], uart_data}; end 89 | 4'h6: begin flash_state <= 4'h7; flash_count <= {flash_count[23:0], uart_data}; end 90 | 4'h7: begin flash_state <= 4'h8; flash_count <= {flash_count[23:0], uart_data}; end 91 | 4'h8: begin 92 | if (flash_count == 0) begin 93 | flash_state <= 4'h0; 94 | end else begin 95 | flash_address <= flash_address + 1'b1; 96 | flash_count <= flash_count - 1'b1; 97 | ram_address <= flash_address[18:0]; 98 | ram_outdata <= uart_data; 99 | ram_load <= 1'b0; 100 | ram_store <= 1'b1; 101 | end 102 | end 103 | endcase 104 | end 105 | end else begin 106 | ram_address <= address; 107 | ram_outdata <= indata; 108 | ram_load <= load; 109 | ram_store <= store; 110 | outdata <= ram_indata; 111 | 112 | flash_state <= 0; 113 | uart_recv_ack <= 0; 114 | end 115 | end 116 | 117 | endmodule 118 | -------------------------------------------------------------------------------- /boot/boot.mif: -------------------------------------------------------------------------------- 1 | -- Generated dump of boot.bin 2 | WIDTH=8; 3 | DEPTH=256; 4 | 5 | ADDRESS_RADIX=HEX; 6 | DATA_RADIX=HEX; 7 | 8 | CONTENT BEGIN 9 | 0 : 31; 10 | 1 : fe; 11 | 2 : ff; 12 | 3 : af; 13 | 4 : 21; 14 | 5 : ff; 15 | 6 : 9f; 16 | 7 : 32; 17 | 8 : cb; 18 | 9 : 7c; 19 | a : 20; 20 | b : fb; 21 | c : 21; 22 | d : 26; 23 | e : ff; 24 | f : e; 25 | 10 : 11; 26 | 11 : 3e; 27 | 12 : 80; 28 | 13 : 32; 29 | 14 : e2; 30 | 15 : c; 31 | 16 : 3e; 32 | 17 : f3; 33 | 18 : e2; 34 | 19 : 32; 35 | 1a : 3e; 36 | 1b : 77; 37 | 1c : 77; 38 | 1d : 3e; 39 | 1e : fc; 40 | 1f : e0; 41 | 20 : 47; 42 | 21 : 11; 43 | 22 : 4; 44 | 23 : 1; 45 | 24 : 21; 46 | 25 : 10; 47 | 26 : 80; 48 | 27 : 1a; 49 | 28 : cd; 50 | 29 : 95; 51 | 2a : 0; 52 | 2b : cd; 53 | 2c : 96; 54 | 2d : 0; 55 | 2e : 13; 56 | 2f : 7b; 57 | 30 : fe; 58 | 31 : 34; 59 | 32 : 20; 60 | 33 : f3; 61 | 34 : 11; 62 | 35 : d8; 63 | 36 : 0; 64 | 37 : 6; 65 | 38 : 8; 66 | 39 : 1a; 67 | 3a : 13; 68 | 3b : 22; 69 | 3c : 23; 70 | 3d : 5; 71 | 3e : 20; 72 | 3f : f9; 73 | 40 : 3e; 74 | 41 : 19; 75 | 42 : ea; 76 | 43 : 10; 77 | 44 : 99; 78 | 45 : 21; 79 | 46 : 2f; 80 | 47 : 99; 81 | 48 : e; 82 | 49 : c; 83 | 4a : 3d; 84 | 4b : 28; 85 | 4c : 8; 86 | 4d : 32; 87 | 4e : d; 88 | 4f : 20; 89 | 50 : f9; 90 | 51 : 2e; 91 | 52 : f; 92 | 53 : 18; 93 | 54 : f3; 94 | 55 : 67; 95 | 56 : 3e; 96 | 57 : 64; 97 | 58 : 57; 98 | 59 : e0; 99 | 5a : 42; 100 | 5b : 3e; 101 | 5c : 91; 102 | 5d : e0; 103 | 5e : 40; 104 | 5f : 4; 105 | 60 : 1e; 106 | 61 : 2; 107 | 62 : e; 108 | 63 : c; 109 | 64 : f0; 110 | 65 : 44; 111 | 66 : fe; 112 | 67 : 90; 113 | 68 : 20; 114 | 69 : fa; 115 | 6a : d; 116 | 6b : 20; 117 | 6c : f7; 118 | 6d : 1d; 119 | 6e : 20; 120 | 6f : f2; 121 | 70 : e; 122 | 71 : 13; 123 | 72 : 24; 124 | 73 : 7c; 125 | 74 : 1e; 126 | 75 : 83; 127 | 76 : fe; 128 | 77 : 62; 129 | 78 : 28; 130 | 79 : 6; 131 | 7a : 1e; 132 | 7b : c1; 133 | 7c : fe; 134 | 7d : 64; 135 | 7e : 20; 136 | 7f : 6; 137 | 80 : 7b; 138 | 81 : e2; 139 | 82 : c; 140 | 83 : 3e; 141 | 84 : 87; 142 | 85 : e2; 143 | 86 : f0; 144 | 87 : 42; 145 | 88 : 90; 146 | 89 : e0; 147 | 8a : 42; 148 | 8b : 15; 149 | 8c : 20; 150 | 8d : d2; 151 | 8e : 5; 152 | 8f : 20; 153 | 90 : 4f; 154 | 91 : 16; 155 | 92 : 20; 156 | 93 : 18; 157 | 94 : cb; 158 | 95 : 4f; 159 | 96 : 6; 160 | 97 : 4; 161 | 98 : c5; 162 | 99 : cb; 163 | 9a : 11; 164 | 9b : 17; 165 | 9c : c1; 166 | 9d : cb; 167 | 9e : 11; 168 | 9f : 17; 169 | a0 : 5; 170 | a1 : 20; 171 | a2 : f5; 172 | a3 : 22; 173 | a4 : 23; 174 | a5 : 22; 175 | a6 : 23; 176 | a7 : c9; 177 | a8 : ce; 178 | a9 : ed; 179 | aa : 66; 180 | ab : 66; 181 | ac : cc; 182 | ad : d; 183 | ae : 0; 184 | af : b; 185 | b0 : 3; 186 | b1 : 73; 187 | b2 : 0; 188 | b3 : 83; 189 | b4 : 0; 190 | b5 : c; 191 | b6 : 0; 192 | b7 : d; 193 | b8 : 0; 194 | b9 : 8; 195 | ba : 11; 196 | bb : 1f; 197 | bc : 88; 198 | bd : 89; 199 | be : 0; 200 | bf : e; 201 | c0 : dc; 202 | c1 : cc; 203 | c2 : 6e; 204 | c3 : e6; 205 | c4 : dd; 206 | c5 : dd; 207 | c6 : d9; 208 | c7 : 99; 209 | c8 : bb; 210 | c9 : bb; 211 | ca : 67; 212 | cb : 63; 213 | cc : 6e; 214 | cd : e; 215 | ce : ec; 216 | cf : cc; 217 | d0 : dd; 218 | d1 : dc; 219 | d2 : 99; 220 | d3 : 9f; 221 | d4 : bb; 222 | d5 : b9; 223 | d6 : 33; 224 | d7 : 3e; 225 | d8 : 3c; 226 | d9 : 42; 227 | da : b9; 228 | db : a5; 229 | dc : b9; 230 | dd : a5; 231 | de : 42; 232 | df : 3c; 233 | e0 : 21; 234 | e1 : 4; 235 | e2 : 1; 236 | e3 : 11; 237 | e4 : a8; 238 | e5 : 0; 239 | e6 : 1a; 240 | e7 : 13; 241 | e8 : be; 242 | e9 : 20; 243 | ea : fe; 244 | eb : 23; 245 | ec : 7d; 246 | ed : fe; 247 | ee : 34; 248 | ef : 20; 249 | f0 : f5; 250 | f1 : 6; 251 | f2 : 19; 252 | f3 : 78; 253 | f4 : 86; 254 | f5 : 23; 255 | f6 : 5; 256 | f7 : 20; 257 | f8 : fb; 258 | f9 : 86; 259 | fa : 20; 260 | fb : fe; 261 | fc : 3e; 262 | fd : 1; 263 | fe : e0; 264 | ff : 50; 265 | END; 266 | -------------------------------------------------------------------------------- /hdmi.v: -------------------------------------------------------------------------------- 1 | module hdmi( 2 | clock25mhz, resetn, 3 | x, y, 4 | r, g, b, 5 | 6 | //////////// HDMI-TX ////////// 7 | HDMI_TX_CLK, 8 | HDMI_TX_D, 9 | HDMI_TX_DE, 10 | HDMI_TX_HS, 11 | HDMI_TX_INT, 12 | HDMI_TX_VS 13 | ); 14 | 15 | parameter CYCLE_DELAY = 0; 16 | 17 | parameter WIDTH = 160; 18 | parameter HEIGHT = 144; 19 | parameter XDIV = 3; 20 | parameter YDIV = 3; 21 | parameter XSTART = 80; 22 | parameter YSTART = 24; 23 | parameter XEND = XSTART + XDIV*WIDTH; 24 | parameter YEND = YSTART + YDIV*HEIGHT; 25 | 26 | parameter HSIZE = 640; 27 | parameter VSIZE = 480; 28 | parameter HTOTAL = 800; 29 | parameter VTOTAL = 525; 30 | parameter HSYNC = 96; 31 | parameter VSYNC = 2; 32 | parameter HSTART = 144; 33 | parameter VSTART = 34; 34 | parameter HEND = HSTART + HSIZE; 35 | parameter VEND = VSTART + VSIZE; 36 | 37 | 38 | input clock25mhz; 39 | input resetn; 40 | output reg [11:0] x; 41 | output reg [11:0] y; 42 | input [7:0] r; 43 | input [7:0] g; 44 | input [7:0] b; 45 | 46 | output HDMI_TX_CLK = ~clock25mhz; 47 | output [23:0] HDMI_TX_D = hdmi_data; 48 | output HDMI_TX_DE = hdmi_de[1]; 49 | output HDMI_TX_HS = hdmi_hsync[1]; 50 | output HDMI_TX_VS = hdmi_vsync[1]; 51 | input HDMI_TX_INT; 52 | 53 | 54 | reg [23:0] hdmi_data; 55 | reg hdmi_de [2]; 56 | reg hdmi_hsync [2]; 57 | reg hdmi_vsync [2]; 58 | 59 | reg [11:0] hdmi_hprecount; 60 | reg [11:0] hdmi_vprecount; 61 | reg [11:0] hdmi_hcount; 62 | reg [11:0] hdmi_vcount; 63 | wire hdmi_hactive = hdmi_hcount >= HSTART && hdmi_hcount < HEND; 64 | wire hdmi_vactive = hdmi_vcount >= VSTART && hdmi_vcount < VEND; 65 | wire hdmi_active = hdmi_hactive && hdmi_vactive; 66 | wire hdmi_hpresync = ~(hdmi_hcount < HSYNC); 67 | wire hdmi_vpresync = ~(hdmi_vcount < VSYNC); 68 | 69 | always @(posedge clock25mhz or negedge resetn) begin 70 | if (!resetn) begin 71 | hdmi_de[0] <= 0; 72 | hdmi_de[1] <= 0; 73 | hdmi_hsync[0] <= 0; 74 | hdmi_hsync[1] <= 0; 75 | hdmi_vsync[0] <= 0; 76 | hdmi_vsync[1] <= 0; 77 | hdmi_hcount <= 0; 78 | hdmi_vcount <= 0; 79 | end else begin 80 | hdmi_de[0] <= hdmi_active; 81 | hdmi_de[1] <= hdmi_de[0]; 82 | hdmi_hsync[0] <= hdmi_hpresync; 83 | hdmi_hsync[1] <= hdmi_hsync[0]; 84 | hdmi_vsync[0] <= hdmi_vpresync; 85 | hdmi_vsync[1] <= hdmi_vsync[0]; 86 | 87 | if (hdmi_hcount + 1'b1 == HTOTAL) begin 88 | hdmi_hcount <= 0; 89 | 90 | if (hdmi_vcount + 1'b1 == VTOTAL) begin 91 | hdmi_vcount <= 0; 92 | end else begin 93 | hdmi_vcount <= hdmi_vcount + 1'b1; 94 | end 95 | end else begin 96 | hdmi_hcount <= hdmi_hcount + 1'b1; 97 | end 98 | end 99 | end 100 | 101 | 102 | wire xactive = hdmi_hcount >= HSTART+XSTART && hdmi_hcount < HSTART+XEND; 103 | wire yactive = hdmi_vcount >= VSTART+YSTART && hdmi_vcount < VSTART+YEND; 104 | wire xsetup = hdmi_hcount >= HSTART+XSTART-CYCLE_DELAY && hdmi_hcount < HSTART+XEND-CYCLE_DELAY; 105 | wire ysetup = hdmi_vcount >= VSTART+YSTART && hdmi_vcount < VSTART+YEND; 106 | 107 | reg [$clog2(XDIV)-1:0] xcount; 108 | reg [$clog2(YDIV)-1:0] ycount; 109 | 110 | always @(posedge clock25mhz or negedge resetn) begin 111 | if (!resetn) begin 112 | hdmi_data <= 0; 113 | xcount <= 0; 114 | x <= 0; 115 | ycount <= 0; 116 | y <= 0; 117 | end else begin 118 | if (xactive && yactive) begin 119 | hdmi_data <= {r, g, b}; 120 | end else begin 121 | hdmi_data <= 0; 122 | end 123 | 124 | if (xsetup && ysetup) begin 125 | if (xcount + 1'b1 == XDIV) begin 126 | xcount <= 0; 127 | if (x + 1'b1 == WIDTH) begin 128 | x <= 0; 129 | if (ycount + 1'b1 == YDIV) begin 130 | ycount <= 0; 131 | if (y + 1'b1 == HEIGHT) begin 132 | y <= 0; 133 | end else begin 134 | y <= y + 1'b1; 135 | end 136 | end else begin 137 | ycount <= ycount + 1'b1; 138 | end 139 | end else begin 140 | x <= x + 1'b1; 141 | end 142 | end else begin 143 | xcount <= xcount + 1'b1; 144 | end 145 | end 146 | end 147 | end 148 | 149 | endmodule 150 | 151 | -------------------------------------------------------------------------------- /memory/bootrom_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: bootrom.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module bootrom ( 36 | address, 37 | clock, 38 | q); 39 | 40 | input [7:0] address; 41 | input clock; 42 | output [7:0] q; 43 | `ifndef ALTERA_RESERVED_QIS 44 | // synopsys translate_off 45 | `endif 46 | tri1 clock; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_on 49 | `endif 50 | 51 | endmodule 52 | 53 | // ============================================================ 54 | // CNX file retrieval info 55 | // ============================================================ 56 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 59 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 61 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 62 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 65 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 66 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 67 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 68 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 69 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 70 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 71 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 72 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 73 | // Retrieval info: PRIVATE: MIFfilename STRING "./boot/boot.mif" 74 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 75 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 76 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 77 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 78 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 79 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 80 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 81 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 82 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 83 | // Retrieval info: PRIVATE: rden NUMERIC "0" 84 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 85 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 88 | // Retrieval info: CONSTANT: INIT_FILE STRING "./boot/boot.mif" 89 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 90 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 91 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 92 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 93 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 94 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 95 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 96 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 97 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 98 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 99 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 100 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 101 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 102 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 103 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 104 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.v TRUE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.inc FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.cmp FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.bsf FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom_inst.v FALSE 110 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom_bb.v TRUE 111 | // Retrieval info: LIB_FILE: altera_mf 112 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # The Very Gameboy Emulator # 2 | 3 | [Current Repo](https://github.com/geky/gb) 4 | 5 | The Very Gameboy Emulator, as I'm calling it, is a functional 6 | implementation of the original Nintendo Gameboy in Verilog targeting 7 | the [Cyclone V GX](http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830). 8 | The Emulator communicates over UART for controller input and displays 9 | the Gameboy's graphics over HDMI along with the Gameboy's audio. The 10 | Emulator was implemented for CS 350c, the Advanced Computer Architecture 11 | class taught by Professor Ahmed Gheith at UT. 12 | 13 | Unfortunately, the emulator not completely accurate and has a few major 14 | limitations. The biggest limitation currently is the restriction to 15 | 512kbyte roms or less due to the size of the external SRAM and lack of 16 | functioning DDR controller. Additionally, battery backed RAM is not fully 17 | implemented, which both prevents saving, and can cause very interesting 18 | artifacts on games that expect a consistent initial state. 19 | 20 | For a more depth explanation of how the Gameboy is implemented, feel free 21 | to look at the [Report](REPORT.md) required for the class. 22 | 23 | ## Instructions ## 24 | 25 | These quick instructions are going to assume you are already able to load 26 | images onto the Cyclone V. 27 | 28 | First, you will need to connect the board over HDMI and run the initial 29 | image until the test picture is displayed. This is due to the HDMI chip 30 | needing several I2C registers initialized which would require significant 31 | overhead to take care of in the emulator. 32 | 33 | Next, you should be able to load the emulator's image onto the board. The 34 | screen should appear slightly greenish, and the state machine shown on the 35 | 7-seg displays should initialize to the default state "0041" 36 | 37 | Several switches are used to configure the running emulator: 38 | ``` 39 | Switches 40 | [9 8 7 6 5 4 3 2 1 0] 41 | | | | | | | \-----/- Used to select the current display on the 7-segs 42 | | | | | | \- 1/16th clock 43 | | | | | \- 1/8th clock 44 | | | | \- 1/4th clock 45 | | | \- normal clock 46 | | \- 2x clock 47 | \- enable flashing 48 | ``` 49 | 50 | To run the emulator at normal speed, you will want to enable only switch 7. 51 | If no rom has been flashed, you should see a corrupted square slide down the 52 | screen. This is actually normal behaviour for the original Gameboy. 53 | 54 | To flash the emulator with a rom, you will need to enable switch 9. If you 55 | leave the emulator itself running, very strange things can happen, so it is 56 | suggested to leave the other switches disabled. You should then plug the board 57 | to a Linux machine over a USB cable and connect through UART. The "gbflash" 58 | script can then be used to flash the Emulator with a Gameboy rom. The offset 59 | and size of the ROM must be specified in hexadecimal. These can be found by 60 | using the hexdump command on the rom itself. The following commands can be 61 | used assuming the device appears as /dev/ttyUSB0. 62 | ``` bash 63 | sudo chmod 777 /dev/ttyUSB0 64 | stty -F /dev/ttyUSB0 115200 65 | ./scripts/gbflash.py 0 80000 rom.gb /dev/ttyUSB0 66 | ``` 67 | 68 | To send controller input over UART, the "controls" script can be used as 69 | long as an xsession is currently running. 70 | ``` bash 71 | ./scripts/controls.py /dev/ttyUSB0 72 | ``` 73 | 74 | By default controls are mapped as such, although this can easily be changed 75 | by modifying the python script to use different PyGame key values. 76 | 77 | - Up/Left/Down/Right = W/A/S/D 78 | - A/B = Enter/Quote 79 | - Start/Select = Space/E 80 | 81 | ## Debugging ## 82 | 83 | There are several displays to assist with debugging. First the leds on the 84 | board can be used to get a large amount of information of the processor state 85 | ``` 86 | Red LEDS 87 | [9 8 7 6 5 4 3 2 1 0] 88 | | | | | | \-/- PPU Display mode 89 | | | | | \- VBlank interrupt 90 | | | | \- Display status interrupt 91 | | | \- Timer interrupt 92 | | \- Link cable interrupt 93 | \- Joypad interrupt 94 | 95 | Green LEDS 96 | [7 6 5 4 3 2 1 0] 97 | | | | | \-/ \-/- CPU load and store signals 98 | | | | | \- DMA load and store signals 99 | | | | \- Carry flag 100 | | | \- Half-carry flag 101 | | \- Subtraction flag 102 | \- Zero flag 103 | ``` 104 | 105 | Additionally, the 4 on board 7-segs can display a 16-bit hex value specified 106 | by the lowest 4 switches 107 | - 0000 = State machine state 108 | - 0100 = Timer value 109 | - 1000 = AF Register pair 110 | - 1001 = BC Register pair 111 | - 1010 = DE Register pair 112 | - 1011 = HL Register pair 113 | - 1100 = Stack Pointer 114 | - 1101 = Program Counter 115 | 116 | Finally, the link cable is transmits all written data through the UART 117 | connection and can be monitored like so. 118 | ``` bash 119 | screen /dev/ttyUSB0 115200 120 | ``` 121 | 122 | ## Resources ### 123 | 124 | The following are very useful resources for Gameboy information and are really 125 | what made this project possible. 126 | 127 | - [Opcode Listing](http://www.pastraiser.com/cpu/gameboy/gameboy_opcodes.html) A very useful listing of the LR35902 instructions 128 | - [Gameboy Manual](http://marc.rawer.de/Gameboy/Docs/GBCPUman.pdf) Documentation on the Gameboy for writing software which covers the expected functionality. 129 | - [Gameboy Dev Wiki](http://gbdev.gg8.se/wiki/articles/Main_Page) A collection of important information regarding the Gameboy for emulation. 130 | -------------------------------------------------------------------------------- /ops/gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python2 2 | 3 | import sys 4 | import re 5 | 6 | 7 | CATS = "\\b(AF|BC|DE|HL|SP|PC)\\b" 8 | CC = {"NZ": ("4'b0xxx", "4'b1xxx"), 9 | "NC": ("4'bxxx0", "4'bxxx1"), 10 | "Z": ("4'b1xxx", "4'b0xxx"), 11 | "C": ("4'bxxx1", "4'bxxx0")} 12 | 13 | GCOND = "D_UC, OR, A_UC, B_F, 2'b00, CC_xxxx" 14 | GNOP = "D_0, OR, A_0, B_0, 2'b00, CC_xxxx" 15 | GSKIP = lambda x: "D_PC, ADD, A_PC, B_%s, 2'b00, CC_xxxx" % x 16 | 17 | 18 | def getbus(bus): 19 | u = {"COND": ["__COND %0"]} 20 | optypes = [] 21 | 22 | for l in bus.splitlines(): 23 | l = re.sub('#.*', '', l).rstrip() 24 | 25 | if l: 26 | if l[0] == ' ': 27 | optypes[-1] += ',' + l.lstrip() 28 | else: 29 | optypes.append(l) 30 | 31 | for t in optypes: 32 | ops = t[12:].split(',') 33 | res = [] 34 | 35 | for p in (p.strip().split(' ') for p in ops): 36 | if len(p) == 1: 37 | m = re.split('[()]', p[0]) 38 | if len(m) > 1: 39 | res += [i.replace('%0', m[1]) for i in u[m[0]]] 40 | elif m[0]: 41 | res += u[m[0]] 42 | else: 43 | assert len(p) == 4, "Not enough bus assignments" 44 | res.append(' '.join(p)) 45 | 46 | u[t[:12].rstrip()] = res 47 | 48 | return u 49 | 50 | def main(): 51 | assert len(sys.argv) == 4 52 | 53 | opset = int(sys.argv[1]) 54 | 55 | u = None 56 | 57 | with open(sys.argv[2]) as f: 58 | u = getbus(f.read()) 59 | 60 | names = None 61 | ops = None 62 | cycles = None 63 | flags = None 64 | 65 | with open(sys.argv[3]) as f: 66 | data = [a.strip() for a in f.read().splitlines()] 67 | names = data[0::3] 68 | cycles = [[int(c)-4*(opset-1) for c in re.findall('[0-9]+', a)] 69 | for a in data[1::3]] 70 | flags = data[2::3] 71 | ops = [re.findall('[A-Z]+', a) for a in names] 72 | cats = [re.findall(CATS, a) for a in names] 73 | mods = [re.findall('[(),a-z0-9+-]', a) for a in names] 74 | 75 | for o,c,m in zip(ops,cats,mods): 76 | if c: o[0] += '2' 77 | if not o[1:] and not c and not m: o[0] += '_' 78 | o[0] += ''.join(m) 79 | 80 | conds = 0 81 | 82 | for x,op in enumerate(ops): 83 | out = u[op[0]] 84 | gen = ["\t// %s" % names[x]] 85 | num = hex(0x100 + x)[3:] + hex(opset)[2:] 86 | 87 | cc = "CC_" + "".join(flags[x].split()).replace("-", "x") 88 | 89 | i = 0 90 | for ni,line in enumerate(out): 91 | if "__COND" in line: 92 | skip = int(line.split()[1]) 93 | (t,f) = CC[op[1]] 94 | 95 | gen.append(("\t16'h%s%s: ucode <= {16'h003%s, " % 96 | (num, hex(i)[2:], hex(conds)[2:])) + GCOND + "};") 97 | gen.append(("\t{%s, 12'h3%s}: ucode <= {16'h%s%s, " % 98 | (t, hex(conds)[2:], num, hex(i+2)[2:])) + GNOP + "};") 99 | gen.append(("\t{%s, 12'h3%s}: ucode <= {__END, " % 100 | (f, hex(conds)[2:])) + 101 | (GNOP if skip == 0 else GSKIP(skip)) + "};") 102 | 103 | i += 2 104 | conds += 1 105 | 106 | if i+3 < cycles[x][2]: 107 | state = "16'h004%s" % (hex(cycles[x][2]-(i+3))[2:]) 108 | gen[-1] = gen[-1].replace("__END", state) 109 | else: 110 | gen[-1] = gen[-1].replace("__END", "16'h0000") 111 | 112 | continue 113 | 114 | a = [a.strip() for a in line.split()] 115 | a[0] = "D_" + a[0] 116 | a[2] = "A_" + a[2] 117 | a[3] = "B_" + a[3] 118 | 119 | if a[1][-1] == "s": 120 | a.append("2'b01") 121 | a[1] = a[1][:-1] 122 | elif a[1][-1] == "l": 123 | a.append("2'b10") 124 | a[1] = a[1][:-1] 125 | else: 126 | a.append("2'b00") 127 | 128 | if a[1][-1] == "~": 129 | a.append(cc) 130 | a[1] = a[1][:-1] 131 | else: 132 | a.append("CC_xxxx") 133 | 134 | res = ("\t16'h%s%s: ucode <= {__NEXT, %s};" % 135 | (num, hex(i)[2:], ", ".join(a))) 136 | 137 | if ni < len(out)-1: 138 | res = res.replace("__NEXT", "16'h%s%s" % (num, hex(i+1)[2:])) 139 | elif ni == len(out)-1: 140 | res = res.replace("__NEXT", "__END") 141 | 142 | gen.append(res) 143 | i += 1 144 | 145 | # cycle count includes 3 for fetch 146 | gen = "\n".join(gen) 147 | if len(op) > 1: gen = gen.replace('$0', op[1]) 148 | if len(op) > 2: gen = gen.replace('$1', op[2]) 149 | 150 | if i+3 < cycles[x][1]: 151 | state = "16'h004%s" % (hex(cycles[x][1]-(i+3))[2:]) 152 | gen = gen.replace("__END", state) 153 | elif i+3 == cycles[x][1]: 154 | gen = gen.replace("__END", "16'h0000") 155 | else: 156 | assert False, "Too many cycles :(" 157 | 158 | if cc != "CC_xxxx" and cc not in gen: 159 | # this now occurs in ccf 160 | #assert False, "Condition codes not set :(" 161 | pass 162 | 163 | print gen 164 | 165 | if __name__ == "__main__": 166 | main() 167 | -------------------------------------------------------------------------------- /memory/hiram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: hiram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module hiram ( 36 | address, 37 | clock, 38 | data, 39 | wren, 40 | q); 41 | 42 | input [6:0] address; 43 | input clock; 44 | input [7:0] data; 45 | input wren; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | endmodule 56 | 57 | // ============================================================ 58 | // CNX file retrieval info 59 | // ============================================================ 60 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 64 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 66 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 67 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 71 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 72 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 73 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 74 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 75 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 76 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 77 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 78 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 79 | // Retrieval info: PRIVATE: MIFfilename STRING "" 80 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128" 81 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 82 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 83 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 85 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 86 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 87 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 88 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 89 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 90 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "7" 91 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 92 | // Retrieval info: PRIVATE: rden NUMERIC "0" 93 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 96 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 97 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 98 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 99 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" 100 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 101 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 102 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 103 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 104 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 105 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" 106 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 107 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 108 | // Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]" 109 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 110 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 111 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 112 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 113 | // Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 114 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 116 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 117 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.inc FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.cmp FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.bsf FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram_inst.v FALSE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram_bb.v TRUE 124 | // Retrieval info: LIB_FILE: altera_mf 125 | -------------------------------------------------------------------------------- /memory/loram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: loram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module loram ( 36 | address, 37 | clock, 38 | data, 39 | wren, 40 | q); 41 | 42 | input [12:0] address; 43 | input clock; 44 | input [7:0] data; 45 | input wren; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | endmodule 56 | 57 | // ============================================================ 58 | // CNX file retrieval info 59 | // ============================================================ 60 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 64 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 66 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 67 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 71 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 72 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 73 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 74 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 75 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 76 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 77 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 78 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 79 | // Retrieval info: PRIVATE: MIFfilename STRING "" 80 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" 81 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 82 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 83 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 85 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 86 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 87 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 88 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 89 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 90 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "13" 91 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 92 | // Retrieval info: PRIVATE: rden NUMERIC "0" 93 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 96 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 97 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 98 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 99 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" 100 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 101 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 102 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 103 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 104 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 105 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" 106 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 107 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 108 | // Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" 109 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 110 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 111 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 112 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 113 | // Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 114 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 116 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 117 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.inc FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.cmp FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.bsf FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram_inst.v FALSE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram_bb.v TRUE 124 | // Retrieval info: LIB_FILE: altera_mf 125 | -------------------------------------------------------------------------------- /memory/mbc1ram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: mbc1ram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module mbc1ram ( 36 | address, 37 | clock, 38 | data, 39 | wren, 40 | q); 41 | 42 | input [12:0] address; 43 | input clock; 44 | input [7:0] data; 45 | input wren; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | endmodule 56 | 57 | // ============================================================ 58 | // CNX file retrieval info 59 | // ============================================================ 60 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 64 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 66 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 67 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 71 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 72 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 73 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 74 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 75 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 76 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 77 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 78 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 79 | // Retrieval info: PRIVATE: MIFfilename STRING "" 80 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" 81 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 82 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 83 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 85 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 86 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 87 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 88 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 89 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 90 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "13" 91 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 92 | // Retrieval info: PRIVATE: rden NUMERIC "0" 93 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 96 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 97 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 98 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 99 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" 100 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 101 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 102 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 103 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 104 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 105 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" 106 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 107 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 108 | // Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" 109 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 110 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 111 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 112 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 113 | // Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 114 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 116 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 117 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.inc FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.cmp FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.bsf FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram_inst.v FALSE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram_bb.v TRUE 124 | // Retrieval info: LIB_FILE: altera_mf 125 | -------------------------------------------------------------------------------- /memory/tram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: tram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module tram ( 36 | address, 37 | byteena, 38 | clock, 39 | data, 40 | wren, 41 | q); 42 | 43 | input [11:0] address; 44 | input [1:0] byteena; 45 | input clock; 46 | input [15:0] data; 47 | input wren; 48 | output [15:0] q; 49 | `ifndef ALTERA_RESERVED_QIS 50 | // synopsys translate_off 51 | `endif 52 | tri1 [1:0] byteena; 53 | tri1 clock; 54 | `ifndef ALTERA_RESERVED_QIS 55 | // synopsys translate_on 56 | `endif 57 | 58 | endmodule 59 | 60 | // ============================================================ 61 | // CNX file retrieval info 62 | // ============================================================ 63 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 65 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 66 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 67 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 68 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" 69 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 70 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 71 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 72 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 73 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 74 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 75 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 76 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 77 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 78 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 79 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 80 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 81 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 82 | // Retrieval info: PRIVATE: MIFfilename STRING "" 83 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "3072" 84 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 85 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2" 86 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 87 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 88 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 89 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 90 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 91 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 92 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 93 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 94 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 95 | // Retrieval info: PRIVATE: rden NUMERIC "0" 96 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 97 | // Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" 98 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 99 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 100 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 101 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 102 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 103 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "3072" 104 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 105 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 106 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 107 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 108 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE" 109 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 110 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 111 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" 112 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 113 | // Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]" 114 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 115 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 116 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 117 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 118 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 119 | // Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 120 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 121 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 122 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 123 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 124 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.v TRUE 125 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.inc FALSE 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.cmp FALSE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.bsf FALSE 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram_inst.v FALSE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram_bb.v TRUE 130 | // Retrieval info: LIB_FILE: altera_mf 131 | -------------------------------------------------------------------------------- /memory/bootrom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: bootrom.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module bootrom ( 41 | address, 42 | clock, 43 | q); 44 | 45 | input [7:0] address; 46 | input clock; 47 | output [7:0] q; 48 | `ifndef ALTERA_RESERVED_QIS 49 | // synopsys translate_off 50 | `endif 51 | tri1 clock; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_on 54 | `endif 55 | 56 | wire [7:0] sub_wire0; 57 | wire [7:0] q = sub_wire0[7:0]; 58 | 59 | altsyncram altsyncram_component ( 60 | .address_a (address), 61 | .clock0 (clock), 62 | .q_a (sub_wire0), 63 | .aclr0 (1'b0), 64 | .aclr1 (1'b0), 65 | .address_b (1'b1), 66 | .addressstall_a (1'b0), 67 | .addressstall_b (1'b0), 68 | .byteena_a (1'b1), 69 | .byteena_b (1'b1), 70 | .clock1 (1'b1), 71 | .clocken0 (1'b1), 72 | .clocken1 (1'b1), 73 | .clocken2 (1'b1), 74 | .clocken3 (1'b1), 75 | .data_a ({8{1'b1}}), 76 | .data_b (1'b1), 77 | .eccstatus (), 78 | .q_b (), 79 | .rden_a (1'b1), 80 | .rden_b (1'b1), 81 | .wren_a (1'b0), 82 | .wren_b (1'b0)); 83 | defparam 84 | altsyncram_component.address_aclr_a = "NONE", 85 | altsyncram_component.clock_enable_input_a = "BYPASS", 86 | altsyncram_component.clock_enable_output_a = "BYPASS", 87 | altsyncram_component.init_file = "./boot/boot.mif", 88 | altsyncram_component.intended_device_family = "Cyclone V", 89 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 90 | altsyncram_component.lpm_type = "altsyncram", 91 | altsyncram_component.numwords_a = 256, 92 | altsyncram_component.operation_mode = "ROM", 93 | altsyncram_component.outdata_aclr_a = "NONE", 94 | altsyncram_component.outdata_reg_a = "CLOCK0", 95 | altsyncram_component.widthad_a = 8, 96 | altsyncram_component.width_a = 8, 97 | altsyncram_component.width_byteena_a = 1; 98 | 99 | 100 | endmodule 101 | 102 | // ============================================================ 103 | // CNX file retrieval info 104 | // ============================================================ 105 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 106 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 107 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 108 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 109 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 110 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 111 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 112 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 113 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 114 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 115 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 116 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 117 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 118 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 119 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 120 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 121 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 122 | // Retrieval info: PRIVATE: MIFfilename STRING "./boot/boot.mif" 123 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 124 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 125 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 126 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 127 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 128 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 129 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 130 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 131 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 132 | // Retrieval info: PRIVATE: rden NUMERIC "0" 133 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 134 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 137 | // Retrieval info: CONSTANT: INIT_FILE STRING "./boot/boot.mif" 138 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 139 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 140 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 141 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 142 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 143 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 144 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 145 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 146 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 147 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 148 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 149 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 150 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 151 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 152 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 153 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 154 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.v TRUE 155 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.inc FALSE 156 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.cmp FALSE 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.bsf FALSE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom_inst.v FALSE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL bootrom_bb.v TRUE 160 | // Retrieval info: LIB_FILE: altera_mf 161 | -------------------------------------------------------------------------------- /memory/hiram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: hiram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module hiram ( 41 | address, 42 | clock, 43 | data, 44 | wren, 45 | q); 46 | 47 | input [6:0] address; 48 | input clock; 49 | input [7:0] data; 50 | input wren; 51 | output [7:0] q; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_off 54 | `endif 55 | tri1 clock; 56 | `ifndef ALTERA_RESERVED_QIS 57 | // synopsys translate_on 58 | `endif 59 | 60 | wire [7:0] sub_wire0; 61 | wire [7:0] q = sub_wire0[7:0]; 62 | 63 | altsyncram altsyncram_component ( 64 | .address_a (address), 65 | .clock0 (clock), 66 | .data_a (data), 67 | .wren_a (wren), 68 | .q_a (sub_wire0), 69 | .aclr0 (1'b0), 70 | .aclr1 (1'b0), 71 | .address_b (1'b1), 72 | .addressstall_a (1'b0), 73 | .addressstall_b (1'b0), 74 | .byteena_a (1'b1), 75 | .byteena_b (1'b1), 76 | .clock1 (1'b1), 77 | .clocken0 (1'b1), 78 | .clocken1 (1'b1), 79 | .clocken2 (1'b1), 80 | .clocken3 (1'b1), 81 | .data_b (1'b1), 82 | .eccstatus (), 83 | .q_b (), 84 | .rden_a (1'b1), 85 | .rden_b (1'b1), 86 | .wren_b (1'b0)); 87 | defparam 88 | altsyncram_component.clock_enable_input_a = "BYPASS", 89 | altsyncram_component.clock_enable_output_a = "BYPASS", 90 | altsyncram_component.intended_device_family = "Cyclone V", 91 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 92 | altsyncram_component.lpm_type = "altsyncram", 93 | altsyncram_component.numwords_a = 128, 94 | altsyncram_component.operation_mode = "SINGLE_PORT", 95 | altsyncram_component.outdata_aclr_a = "NONE", 96 | altsyncram_component.outdata_reg_a = "CLOCK0", 97 | altsyncram_component.power_up_uninitialized = "FALSE", 98 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 99 | altsyncram_component.widthad_a = 7, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 113 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 115 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 116 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 120 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 121 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 122 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 123 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 124 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 125 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 126 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 127 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 128 | // Retrieval info: PRIVATE: MIFfilename STRING "" 129 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128" 130 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 131 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 132 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 134 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 135 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 138 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 139 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "7" 140 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 141 | // Retrieval info: PRIVATE: rden NUMERIC "0" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 145 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 146 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 147 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 148 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" 149 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 150 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 151 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 152 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 153 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 154 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" 155 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 156 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 157 | // Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]" 158 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 159 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 160 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 161 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 162 | // Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 163 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 164 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 165 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 166 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.v TRUE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.inc FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.cmp FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram.bsf FALSE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram_inst.v FALSE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL hiram_bb.v TRUE 173 | // Retrieval info: LIB_FILE: altera_mf 174 | -------------------------------------------------------------------------------- /memory/loram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: loram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module loram ( 41 | address, 42 | clock, 43 | data, 44 | wren, 45 | q); 46 | 47 | input [12:0] address; 48 | input clock; 49 | input [7:0] data; 50 | input wren; 51 | output [7:0] q; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_off 54 | `endif 55 | tri1 clock; 56 | `ifndef ALTERA_RESERVED_QIS 57 | // synopsys translate_on 58 | `endif 59 | 60 | wire [7:0] sub_wire0; 61 | wire [7:0] q = sub_wire0[7:0]; 62 | 63 | altsyncram altsyncram_component ( 64 | .address_a (address), 65 | .clock0 (clock), 66 | .data_a (data), 67 | .wren_a (wren), 68 | .q_a (sub_wire0), 69 | .aclr0 (1'b0), 70 | .aclr1 (1'b0), 71 | .address_b (1'b1), 72 | .addressstall_a (1'b0), 73 | .addressstall_b (1'b0), 74 | .byteena_a (1'b1), 75 | .byteena_b (1'b1), 76 | .clock1 (1'b1), 77 | .clocken0 (1'b1), 78 | .clocken1 (1'b1), 79 | .clocken2 (1'b1), 80 | .clocken3 (1'b1), 81 | .data_b (1'b1), 82 | .eccstatus (), 83 | .q_b (), 84 | .rden_a (1'b1), 85 | .rden_b (1'b1), 86 | .wren_b (1'b0)); 87 | defparam 88 | altsyncram_component.clock_enable_input_a = "BYPASS", 89 | altsyncram_component.clock_enable_output_a = "BYPASS", 90 | altsyncram_component.intended_device_family = "Cyclone V", 91 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 92 | altsyncram_component.lpm_type = "altsyncram", 93 | altsyncram_component.numwords_a = 8192, 94 | altsyncram_component.operation_mode = "SINGLE_PORT", 95 | altsyncram_component.outdata_aclr_a = "NONE", 96 | altsyncram_component.outdata_reg_a = "CLOCK0", 97 | altsyncram_component.power_up_uninitialized = "FALSE", 98 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 99 | altsyncram_component.widthad_a = 13, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 113 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 115 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 116 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 120 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 121 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 122 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 123 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 124 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 125 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 126 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 127 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 128 | // Retrieval info: PRIVATE: MIFfilename STRING "" 129 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" 130 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 131 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 132 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 134 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 135 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 138 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 139 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "13" 140 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 141 | // Retrieval info: PRIVATE: rden NUMERIC "0" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 145 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 146 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 147 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 148 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" 149 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 150 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 151 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 152 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 153 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 154 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" 155 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 156 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 157 | // Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" 158 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 159 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 160 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 161 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 162 | // Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 163 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 164 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 165 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 166 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.v TRUE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.inc FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.cmp FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram.bsf FALSE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram_inst.v FALSE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL loram_bb.v TRUE 173 | // Retrieval info: LIB_FILE: altera_mf 174 | -------------------------------------------------------------------------------- /memory/mbc1ram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: mbc1ram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module mbc1ram ( 41 | address, 42 | clock, 43 | data, 44 | wren, 45 | q); 46 | 47 | input [12:0] address; 48 | input clock; 49 | input [7:0] data; 50 | input wren; 51 | output [7:0] q; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_off 54 | `endif 55 | tri1 clock; 56 | `ifndef ALTERA_RESERVED_QIS 57 | // synopsys translate_on 58 | `endif 59 | 60 | wire [7:0] sub_wire0; 61 | wire [7:0] q = sub_wire0[7:0]; 62 | 63 | altsyncram altsyncram_component ( 64 | .address_a (address), 65 | .clock0 (clock), 66 | .data_a (data), 67 | .wren_a (wren), 68 | .q_a (sub_wire0), 69 | .aclr0 (1'b0), 70 | .aclr1 (1'b0), 71 | .address_b (1'b1), 72 | .addressstall_a (1'b0), 73 | .addressstall_b (1'b0), 74 | .byteena_a (1'b1), 75 | .byteena_b (1'b1), 76 | .clock1 (1'b1), 77 | .clocken0 (1'b1), 78 | .clocken1 (1'b1), 79 | .clocken2 (1'b1), 80 | .clocken3 (1'b1), 81 | .data_b (1'b1), 82 | .eccstatus (), 83 | .q_b (), 84 | .rden_a (1'b1), 85 | .rden_b (1'b1), 86 | .wren_b (1'b0)); 87 | defparam 88 | altsyncram_component.clock_enable_input_a = "BYPASS", 89 | altsyncram_component.clock_enable_output_a = "BYPASS", 90 | altsyncram_component.intended_device_family = "Cyclone V", 91 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 92 | altsyncram_component.lpm_type = "altsyncram", 93 | altsyncram_component.numwords_a = 8192, 94 | altsyncram_component.operation_mode = "SINGLE_PORT", 95 | altsyncram_component.outdata_aclr_a = "NONE", 96 | altsyncram_component.outdata_reg_a = "CLOCK0", 97 | altsyncram_component.power_up_uninitialized = "FALSE", 98 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 99 | altsyncram_component.widthad_a = 13, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 113 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 115 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 116 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 120 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 121 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 122 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 123 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 124 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 125 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 126 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 127 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 128 | // Retrieval info: PRIVATE: MIFfilename STRING "" 129 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" 130 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 131 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 132 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 134 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 135 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 138 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 139 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "13" 140 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 141 | // Retrieval info: PRIVATE: rden NUMERIC "0" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 145 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 146 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 147 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 148 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" 149 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 150 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 151 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 152 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 153 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 154 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" 155 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 156 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 157 | // Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" 158 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 159 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 160 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 161 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 162 | // Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 163 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 164 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 165 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 166 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.v TRUE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.inc FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.cmp FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram.bsf FALSE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram_inst.v FALSE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL mbc1ram_bb.v TRUE 173 | // Retrieval info: LIB_FILE: altera_mf 174 | -------------------------------------------------------------------------------- /memory/tram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: tram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module tram ( 41 | address, 42 | byteena, 43 | clock, 44 | data, 45 | wren, 46 | q); 47 | 48 | input [11:0] address; 49 | input [1:0] byteena; 50 | input clock; 51 | input [15:0] data; 52 | input wren; 53 | output [15:0] q; 54 | `ifndef ALTERA_RESERVED_QIS 55 | // synopsys translate_off 56 | `endif 57 | tri1 [1:0] byteena; 58 | tri1 clock; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_on 61 | `endif 62 | 63 | wire [15:0] sub_wire0; 64 | wire [15:0] q = sub_wire0[15:0]; 65 | 66 | altsyncram altsyncram_component ( 67 | .address_a (address), 68 | .byteena_a (byteena), 69 | .clock0 (clock), 70 | .data_a (data), 71 | .wren_a (wren), 72 | .q_a (sub_wire0), 73 | .aclr0 (1'b0), 74 | .aclr1 (1'b0), 75 | .address_b (1'b1), 76 | .addressstall_a (1'b0), 77 | .addressstall_b (1'b0), 78 | .byteena_b (1'b1), 79 | .clock1 (1'b1), 80 | .clocken0 (1'b1), 81 | .clocken1 (1'b1), 82 | .clocken2 (1'b1), 83 | .clocken3 (1'b1), 84 | .data_b (1'b1), 85 | .eccstatus (), 86 | .q_b (), 87 | .rden_a (1'b1), 88 | .rden_b (1'b1), 89 | .wren_b (1'b0)); 90 | defparam 91 | altsyncram_component.byte_size = 8, 92 | altsyncram_component.clock_enable_input_a = "BYPASS", 93 | altsyncram_component.clock_enable_output_a = "BYPASS", 94 | altsyncram_component.intended_device_family = "Cyclone V", 95 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 96 | altsyncram_component.lpm_type = "altsyncram", 97 | altsyncram_component.numwords_a = 3072, 98 | altsyncram_component.operation_mode = "SINGLE_PORT", 99 | altsyncram_component.outdata_aclr_a = "NONE", 100 | altsyncram_component.outdata_reg_a = "CLOCK0", 101 | altsyncram_component.power_up_uninitialized = "FALSE", 102 | altsyncram_component.read_during_write_mode_port_a = "DONT_CARE", 103 | altsyncram_component.widthad_a = 12, 104 | altsyncram_component.width_a = 16, 105 | altsyncram_component.width_byteena_a = 2; 106 | 107 | 108 | endmodule 109 | 110 | // ============================================================ 111 | // CNX file retrieval info 112 | // ============================================================ 113 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 114 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 115 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 116 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 117 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 118 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" 119 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 120 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 121 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 122 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 123 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 124 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 125 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 126 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 127 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 128 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 129 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 130 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 131 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 132 | // Retrieval info: PRIVATE: MIFfilename STRING "" 133 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "3072" 134 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 135 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2" 136 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 137 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 138 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 139 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 140 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 141 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 142 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 143 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 144 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 145 | // Retrieval info: PRIVATE: rden NUMERIC "0" 146 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 147 | // Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" 148 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 149 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 150 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 151 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 152 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 153 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "3072" 154 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 155 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 156 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 157 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 158 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE" 159 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 160 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 161 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" 162 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 163 | // Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]" 164 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 165 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 166 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 167 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 168 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 169 | // Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0 170 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 171 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 172 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 173 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.v TRUE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.inc FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.cmp FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram.bsf FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram_inst.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL tram_bb.v TRUE 180 | // Retrieval info: LIB_FILE: altera_mf 181 | -------------------------------------------------------------------------------- /memory/vram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: vram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module vram ( 36 | data, 37 | rdaddress, 38 | rdclock, 39 | wraddress, 40 | wrclock, 41 | wren, 42 | q); 43 | 44 | input [5:0] data; 45 | input [15:0] rdaddress; 46 | input rdclock; 47 | input [15:0] wraddress; 48 | input wrclock; 49 | input wren; 50 | output [5:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 wrclock; 55 | tri0 wren; 56 | `ifndef ALTERA_RESERVED_QIS 57 | // synopsys translate_on 58 | `endif 59 | 60 | endmodule 61 | 62 | // ============================================================ 63 | // CNX file retrieval info 64 | // ============================================================ 65 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 66 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 67 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 69 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 71 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 72 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 73 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 74 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 75 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 76 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 77 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 78 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 79 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 80 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 81 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 82 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 83 | // Retrieval info: PRIVATE: Clock NUMERIC "1" 84 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 85 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 86 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 87 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 88 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 89 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 90 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 91 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 92 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 93 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 94 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 95 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "221184" 96 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 97 | // Retrieval info: PRIVATE: MIFfilename STRING "" 98 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 99 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 100 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" 101 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 102 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 103 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 104 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 105 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 106 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 107 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 108 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 109 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 110 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 111 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 112 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 113 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 114 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 115 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6" 116 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6" 117 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6" 118 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6" 119 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 120 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 121 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 122 | // Retrieval info: PRIVATE: enable NUMERIC "0" 123 | // Retrieval info: PRIVATE: rden NUMERIC "0" 124 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 125 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" 126 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" 127 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 128 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 129 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 130 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 131 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 132 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "36864" 133 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "36864" 134 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 135 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 136 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" 137 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 138 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16" 139 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16" 140 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "6" 141 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "6" 142 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 143 | // Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL "data[5..0]" 144 | // Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]" 145 | // Retrieval info: USED_PORT: rdaddress 0 0 16 0 INPUT NODEFVAL "rdaddress[15..0]" 146 | // Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" 147 | // Retrieval info: USED_PORT: wraddress 0 0 16 0 INPUT NODEFVAL "wraddress[15..0]" 148 | // Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" 149 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 150 | // Retrieval info: CONNECT: @address_a 0 0 16 0 wraddress 0 0 16 0 151 | // Retrieval info: CONNECT: @address_b 0 0 16 0 rdaddress 0 0 16 0 152 | // Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 153 | // Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 154 | // Retrieval info: CONNECT: @data_a 0 0 6 0 data 0 0 6 0 155 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 156 | // Retrieval info: CONNECT: q 0 0 6 0 @q_b 0 0 6 0 157 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v TRUE 163 | // Retrieval info: LIB_FILE: altera_mf 164 | -------------------------------------------------------------------------------- /ops/z80.bus: -------------------------------------------------------------------------------- 1 | # Definition of bus connections for various opcode types 2 | 3 | # These are just used as macros inside other instructions 4 | FETCH PC ADDl PC 1 5 | STASH TEMP OR D8 0 6 | NOP 0 OR 0 0 7 | 8 | # Special opcodes 9 | NOP_ NOP 10 | HALT_ # Halting and prefix instructions 11 | PREFIX # are handled externally 12 | STOP0 PC SUB PC 1 13 | 14 | # Move instructions 15 | LD, $0 OR $1 0 16 | LD2,d16 FETCH, NOP, STASH 17 | FETCH, NOP, $0 OR D16 0 18 | LD2(), DATA OR $1 0 19 | 0 ORs $0 0, NOP 20 | LD2(+), DATA OR $1 0 21 | $0 ADDs $0 1, NOP 22 | LD2(-), DATA OR $1 0 23 | $0 SUBs $0 1, NOP 24 | 25 | LD,d8 FETCH, NOP 26 | $0 OR D8 0 27 | LD2(),d8 FETCH, NOP 28 | DATA OR D8 0 29 | 0 ORs $0 0, NOP 30 | LD2(a16), FETCH, NOP, STASH 31 | FETCH, DATA OR $0 0 32 | TEMP ADDs D16 1, NOP 33 | DATA SWAP2 $0 0 34 | 0 ORs TEMP 0, NOP 35 | 36 | LD2,() 0 ORl $1 0, NOP 37 | $0 OR D8 0 38 | LD2,(+) $1 ADDl $1 1, NOP 39 | $0 OR D8 0 40 | LD2,(-) $1 SUBl $1 1, NOP 41 | $0 OR D8 0 42 | 43 | LDH(a8), FETCH, NOP 44 | TEMP OR MASK D8 45 | DATA OR $0 0 46 | 0 ORs TEMP 0, NOP 47 | LDH,(a8) FETCH, NOP 48 | TEMP OR MASK D8 49 | 0 ORl TEMP 0, NOP 50 | $0 OR D8 0 51 | LD(a16), FETCH, NOP, STASH 52 | FETCH, DATA OR $0 0 53 | 0 ORs D16 0, NOP 54 | LD,(a16) FETCH, NOP, STASH 55 | FETCH, NOP 56 | 0 ORl D16 0, NOP 57 | $0 OR D8 0 58 | 59 | LD(), TEMP OR MASK $0 60 | DATA OR $1 0 61 | 0 ORs TEMP 0, NOP 62 | LD,() TEMP OR MASK $1 63 | 0 ORl TEMP 0, NOP 64 | $0 OR D8 0 65 | LD2,+r8 FETCH, NOP 66 | $0 ADD2~ $1 D8 67 | LD2, $0 OR $1 0 68 | 69 | # Increment and decrement instructions 70 | INC $0 ADD~ $0 1 71 | INC2 INC 72 | INC2() 0 ORl $0 0, NOP 73 | DATA ADD~ D8 1 74 | 0 ORs $0 0, NOP 75 | 76 | DEC $0 SUB~ $0 1 77 | DEC2 DEC 78 | DEC2() 0 ORl $0 0, NOP 79 | DATA SUB~ D8 1 80 | 0 ORs $0 0, NOP 81 | 82 | # Arithmetic instructions 83 | ADD2, $0 ADD2~ $0 $1 84 | ADD2,r8 FETCH, NOP 85 | $0 ADD2~ $0 D8 86 | ADD, $0 ADD~ $0 $1 87 | ADD2,() 0 ORl $1 0, NOP 88 | $0 ADD~ $0 D8 89 | ADD,d8 FETCH, NOP 90 | $0 ADD~ $0 D8 91 | 92 | ADC, $0 ADC~ $0 $1 93 | ADC2,() 0 ORl $1 0, NOP 94 | $0 ADC~ $0 D8 95 | ADC,d8 FETCH, NOP 96 | $0 ADC~ $0 D8 97 | 98 | SUB A SUB~ A $0 99 | SUB2() 0 ORl $0 0, NOP 100 | A SUB~ A D8 101 | SUBd8 FETCH, NOP 102 | A SUB~ A D8 103 | 104 | SBC, $0 SBC~ $0 $1 105 | SBC2,() 0 ORl $1 0, NOP 106 | $0 SBC~ $0 D8 107 | SBC,d8 FETCH, NOP 108 | $0 SBC~ $0 D8 109 | 110 | AND A AND~ A $0 111 | AND2() 0 ORl $0 0, NOP 112 | A AND~ A D8 113 | ANDd8 FETCH, NOP 114 | A AND~ A D8 115 | 116 | XOR A XOR~ A $0 117 | XOR2() 0 ORl $0 0, NOP 118 | A XOR~ A D8 119 | XORd8 FETCH, NOP 120 | A XOR~ A D8 121 | 122 | OR A OR~ A $0 123 | OR2() 0 ORl $0 0, NOP 124 | A OR~ A D8 125 | ORd8 FETCH, NOP 126 | A OR~ A D8 127 | 128 | CP 0 SUB~ A $0 129 | CP2() 0 ORl $0 0, NOP 130 | 0 SUB~ A D8 131 | CPd8 FETCH, NOP 132 | 0 SUB~ A D8 133 | 134 | # Control flow instructions 135 | JRr8 FETCH, NOP 136 | PC ADD PC D8 137 | JR,r8 COND(1), JRr8 138 | 139 | RET_ SP ADDl SP 1, NOP, STASH 140 | SP ADDl SP 1, NOP 141 | PC OR D16 0 142 | RET COND(0), RET_ 143 | 144 | JPa16 FETCH, NOP, STASH 145 | FETCH, NOP 146 | PC OR D16 0 147 | JP,a16 COND(2), JPa16 148 | JP2() PC OR $0 0 149 | 150 | CALLa16 TEMP ADD PC 2 151 | SP SUB SP 1 152 | DATA SWAP2 TEMP 0 153 | SP SUBs SP 1, NOP 154 | DATA OR TEMP 0 155 | 0 ORs SP 0, NOP 156 | FETCH, NOP, STASH 157 | FETCH, NOP 158 | PC OR D16 0 159 | CALL,a16 COND(2), CALLa16 160 | 161 | RST SP SUB SP 1 162 | DATA SWAP2 PC 0 163 | SP SUBs SP 1, NOP 164 | DATA OR PC 0 165 | 0 ORs SP 0, NOP 166 | PC OR %0 0 167 | 168 | RST00 RST(0) 169 | RST08 RST(8) 170 | RST10 RST(10) 171 | RST18 RST(18) 172 | RST20 RST(20) 173 | RST28 RST(28) 174 | RST30 RST(30) 175 | RST38 RST(38) 176 | 177 | # Interupt handling instructions 178 | RETI_ SP ADDl SP 1, NOP, STASH 179 | SP ADDl SP 1, NOP 180 | PC OR D16 0 181 | IE OR 1 0 182 | DI_ IE OR 0 0 183 | EI_ IE OR 1 0 184 | 185 | # Stack manipulation instructions 186 | POP2 SP ADDl SP 1, NOP, STASH 187 | SP ADDl SP 1, NOP 188 | $0 OR~ D16 0 189 | 190 | PUSH2 SP SUB SP 1 191 | DATA SWAP2 $0 0 192 | SP SUBs SP 1, NOP 193 | DATA OR $0 0 194 | 0 ORs SP 0, NOP 195 | 196 | # Misc instructions 197 | DAA_ A DAA~ A 0 198 | CPL_ A CPL~ A 0 199 | SCF_ 0 OR~ 0 0 200 | CCF_ AF XOR~ AF 10 201 | 202 | # Rotate/Shift instructions 203 | RLCA_ A RLC~ A 0 204 | RLC $0 RLC~ $0 0 205 | RLC2() 0 ORl $0 0, NOP 206 | DATA RLC~ D8 0 207 | 0 ORs $0 0, NOP 208 | RLA_ A RL~ A 0 209 | RL $0 RL~ $0 0 210 | RL2() 0 ORl $0 0, NOP 211 | DATA RL~ D8 0 212 | 0 ORs $0 0, NOP 213 | 214 | RRCA_ A RRC~ A 0 215 | RRC2() 0 ORl $0 0, NOP 216 | DATA RRC~ D8 0 217 | 0 ORs $0 0, NOP 218 | RRC $0 RRC~ $0 0 219 | RRA_ A RR~ A 0 220 | RR $0 RR~ $0 0 221 | RR2() 0 ORl $0 0, NOP 222 | DATA RR~ D8 0 223 | 0 ORs $0 0, NOP 224 | 225 | SLA $0 SLA~ $0 0 226 | SLA2() 0 ORl $0 0, NOP 227 | DATA SLA~ D8 0 228 | 0 ORs $0 0, NOP 229 | 230 | SRA $0 SRA~ $0 0 231 | SRA2() 0 ORl $0 0, NOP 232 | DATA SRA~ D8 0 233 | 0 ORs $0 0, NOP 234 | 235 | SRL $0 SRL~ $0 0 236 | SRL2() 0 ORl $0 0, NOP 237 | DATA SRL~ D8 0 238 | 0 ORs $0 0, NOP 239 | 240 | SWAP $0 SWAP~ $0 0 241 | SWAP2() 0 ORl $0 0, NOP 242 | DATA SWAP~ D8 0 243 | 0 ORs $0 0, NOP 244 | 245 | # Bitwise operations 246 | BIT 0 AND~ $0 %0 247 | BIT2 0 ORl $0 0, NOP 248 | 0 AND~ D8 %0 249 | 250 | BIT0, BIT(1) 251 | BIT1, BIT(2) 252 | BIT2, BIT(4) 253 | BIT3, BIT(8) 254 | BIT4, BIT(10) 255 | BIT5, BIT(20) 256 | BIT6, BIT(40) 257 | BIT7, BIT(80) 258 | BIT20,() BIT2(1) 259 | BIT21,() BIT2(2) 260 | BIT22,() BIT2(4) 261 | BIT23,() BIT2(8) 262 | BIT24,() BIT2(10) 263 | BIT25,() BIT2(20) 264 | BIT26,() BIT2(40) 265 | BIT27,() BIT2(80) 266 | 267 | RES $0 AND $0 %0 268 | RES2 0 ORl $0 0, NOP 269 | DATA AND D8 %0 270 | 0 ORs $0 0, NOP 271 | 272 | RES0, RES(fe) 273 | RES1, RES(fd) 274 | RES2, RES(fb) 275 | RES3, RES(f7) 276 | RES4, RES(ef) 277 | RES5, RES(df) 278 | RES6, RES(bf) 279 | RES7, RES(7f) 280 | RES20,() RES2(fe) 281 | RES21,() RES2(fd) 282 | RES22,() RES2(fb) 283 | RES23,() RES2(f7) 284 | RES24,() RES2(ef) 285 | RES25,() RES2(df) 286 | RES26,() RES2(bf) 287 | RES27,() RES2(7f) 288 | 289 | SET $0 OR $0 %0 290 | SET2 0 ORl $0 0, NOP 291 | DATA OR D8 %0 292 | 0 ORs $0 0, NOP 293 | 294 | SET0, SET(1) 295 | SET1, SET(2) 296 | SET2, SET(4) 297 | SET3, SET(8) 298 | SET4, SET(10) 299 | SET5, SET(20) 300 | SET6, SET(40) 301 | SET7, SET(80) 302 | SET20,() SET2(1) 303 | SET21,() SET2(2) 304 | SET22,() SET2(4) 305 | SET23,() SET2(8) 306 | SET24,() SET2(10) 307 | SET25,() SET2(20) 308 | SET26,() SET2(40) 309 | SET27,() SET2(80) 310 | 311 | -------------------------------------------------------------------------------- /memory/bgram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: bgram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module bgram ( 36 | address_a, 37 | address_b, 38 | clock, 39 | data_a, 40 | data_b, 41 | wren_a, 42 | wren_b, 43 | q_a, 44 | q_b); 45 | 46 | input [10:0] address_a; 47 | input [10:0] address_b; 48 | input clock; 49 | input [7:0] data_a; 50 | input [7:0] data_b; 51 | input wren_a; 52 | input wren_b; 53 | output [7:0] q_a; 54 | output [7:0] q_b; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_off 57 | `endif 58 | tri1 clock; 59 | tri0 wren_a; 60 | tri0 wren_b; 61 | `ifndef ALTERA_RESERVED_QIS 62 | // synopsys translate_on 63 | `endif 64 | 65 | endmodule 66 | 67 | // ============================================================ 68 | // CNX file retrieval info 69 | // ============================================================ 70 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 71 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 72 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 73 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 74 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 75 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 76 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 77 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 78 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 79 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 80 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 81 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 82 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 83 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 84 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 85 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 86 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 87 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 88 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 89 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 90 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 91 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 92 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 93 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 94 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 95 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 96 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 97 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 98 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 99 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 100 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" 101 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 102 | // Retrieval info: PRIVATE: MIFfilename STRING "" 103 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 104 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 105 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 106 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 107 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 108 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 109 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 110 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 111 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 112 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 113 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 114 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 115 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 116 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 117 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 118 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 119 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 120 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" 121 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" 122 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" 123 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" 124 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 125 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 126 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 127 | // Retrieval info: PRIVATE: enable NUMERIC "0" 128 | // Retrieval info: PRIVATE: rden NUMERIC "0" 129 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 130 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 131 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 132 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 133 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 134 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 135 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 136 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 137 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 138 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" 139 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" 140 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 141 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 142 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 143 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 144 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 145 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 146 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 147 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 148 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 149 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" 150 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" 151 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 152 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" 153 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 154 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 155 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 156 | // Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]" 157 | // Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]" 158 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 159 | // Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" 160 | // Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" 161 | // Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" 162 | // Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" 163 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 164 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 165 | // Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0 166 | // Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0 167 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 168 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 169 | // Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 170 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 171 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 172 | // Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 173 | // Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.v TRUE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.inc FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.cmp FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.bsf FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram_inst.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram_bb.v TRUE 180 | // Retrieval info: LIB_FILE: altera_mf 181 | -------------------------------------------------------------------------------- /ops/ops.txt: -------------------------------------------------------------------------------- 1 | NOP 2 | 1 4 3 | - - - - 4 | LD BC,d16 5 | 3 12 6 | - - - - 7 | LD (BC),A 8 | 1 8 9 | - - - - 10 | INC BC 11 | 1 8 12 | - - - - 13 | INC B 14 | 1 4 15 | Z 0 H - 16 | DEC B 17 | 1 4 18 | Z 1 H - 19 | LD B,d8 20 | 2 8 21 | - - - - 22 | RLCA 23 | 1 4 24 | 0 0 0 C 25 | LD (a16),SP 26 | 3 20 27 | - - - - 28 | ADD HL,BC 29 | 1 8 30 | - 0 H C 31 | LD A,(BC) 32 | 1 8 33 | - - - - 34 | DEC BC 35 | 1 8 36 | - - - - 37 | INC C 38 | 1 4 39 | Z 0 H - 40 | DEC C 41 | 1 4 42 | Z 1 H - 43 | LD C,d8 44 | 2 8 45 | - - - - 46 | RRCA 47 | 1 4 48 | 0 0 0 C 49 | STOP 0 50 | 2 4 51 | - - - - 52 | LD DE,d16 53 | 3 12 54 | - - - - 55 | LD (DE),A 56 | 1 8 57 | - - - - 58 | INC DE 59 | 1 8 60 | - - - - 61 | INC D 62 | 1 4 63 | Z 0 H - 64 | DEC D 65 | 1 4 66 | Z 1 H - 67 | LD D,d8 68 | 2 8 69 | - - - - 70 | RLA 71 | 1 4 72 | 0 0 0 C 73 | JR r8 74 | 2 12 75 | - - - - 76 | ADD HL,DE 77 | 1 8 78 | - 0 H C 79 | LD A,(DE) 80 | 1 8 81 | - - - - 82 | DEC DE 83 | 1 8 84 | - - - - 85 | INC E 86 | 1 4 87 | Z 0 H - 88 | DEC E 89 | 1 4 90 | Z 1 H - 91 | LD E,d8 92 | 2 8 93 | - - - - 94 | RRA 95 | 1 4 96 | 0 0 0 C 97 | JR NZ,r8 98 | 2 12/8 99 | - - - - 100 | LD HL,d16 101 | 3 12 102 | - - - - 103 | LD (HL+),A 104 | 1 8 105 | - - - - 106 | INC HL 107 | 1 8 108 | - - - - 109 | INC H 110 | 1 4 111 | Z 0 H - 112 | DEC H 113 | 1 4 114 | Z 1 H - 115 | LD H,d8 116 | 2 8 117 | - - - - 118 | DAA 119 | 1 4 120 | Z - 0 C 121 | JR Z,r8 122 | 2 12/8 123 | - - - - 124 | ADD HL,HL 125 | 1 8 126 | - 0 H C 127 | LD A,(HL+) 128 | 1 8 129 | - - - - 130 | DEC HL 131 | 1 8 132 | - - - - 133 | INC L 134 | 1 4 135 | Z 0 H - 136 | DEC L 137 | 1 4 138 | Z 1 H - 139 | LD L,d8 140 | 2 8 141 | - - - - 142 | CPL 143 | 1 4 144 | - 1 1 - 145 | JR NC,r8 146 | 2 12/8 147 | - - - - 148 | LD SP,d16 149 | 3 12 150 | - - - - 151 | LD (HL-),A 152 | 1 8 153 | - - - - 154 | INC SP 155 | 1 8 156 | - - - - 157 | INC (HL) 158 | 1 12 159 | Z 0 H - 160 | DEC (HL) 161 | 1 12 162 | Z 1 H - 163 | LD (HL),d8 164 | 2 12 165 | - - - - 166 | SCF 167 | 1 4 168 | - 0 0 1 169 | JR C,r8 170 | 2 12/8 171 | - - - - 172 | ADD HL,SP 173 | 1 8 174 | - 0 H C 175 | LD A,(HL-) 176 | 1 8 177 | - - - - 178 | DEC SP 179 | 1 8 180 | - - - - 181 | INC A 182 | 1 4 183 | Z 0 H - 184 | DEC A 185 | 1 4 186 | Z 1 H - 187 | LD A,d8 188 | 2 8 189 | - - - - 190 | CCF 191 | 1 4 192 | - 0 0 - 193 | LD B,B 194 | 1 4 195 | - - - - 196 | LD B,C 197 | 1 4 198 | - - - - 199 | LD B,D 200 | 1 4 201 | - - - - 202 | LD B,E 203 | 1 4 204 | - - - - 205 | LD B,H 206 | 1 4 207 | - - - - 208 | LD B,L 209 | 1 4 210 | - - - - 211 | LD B,(HL) 212 | 1 8 213 | - - - - 214 | LD B,A 215 | 1 4 216 | - - - - 217 | LD C,B 218 | 1 4 219 | - - - - 220 | LD C,C 221 | 1 4 222 | - - - - 223 | LD C,D 224 | 1 4 225 | - - - - 226 | LD C,E 227 | 1 4 228 | - - - - 229 | LD C,H 230 | 1 4 231 | - - - - 232 | LD C,L 233 | 1 4 234 | - - - - 235 | LD C,(HL) 236 | 1 8 237 | - - - - 238 | LD C,A 239 | 1 4 240 | - - - - 241 | LD D,B 242 | 1 4 243 | - - - - 244 | LD D,C 245 | 1 4 246 | - - - - 247 | LD D,D 248 | 1 4 249 | - - - - 250 | LD D,E 251 | 1 4 252 | - - - - 253 | LD D,H 254 | 1 4 255 | - - - - 256 | LD D,L 257 | 1 4 258 | - - - - 259 | LD D,(HL) 260 | 1 8 261 | - - - - 262 | LD D,A 263 | 1 4 264 | - - - - 265 | LD E,B 266 | 1 4 267 | - - - - 268 | LD E,C 269 | 1 4 270 | - - - - 271 | LD E,D 272 | 1 4 273 | - - - - 274 | LD E,E 275 | 1 4 276 | - - - - 277 | LD E,H 278 | 1 4 279 | - - - - 280 | LD E,L 281 | 1 4 282 | - - - - 283 | LD E,(HL) 284 | 1 8 285 | - - - - 286 | LD E,A 287 | 1 4 288 | - - - - 289 | LD H,B 290 | 1 4 291 | - - - - 292 | LD H,C 293 | 1 4 294 | - - - - 295 | LD H,D 296 | 1 4 297 | - - - - 298 | LD H,E 299 | 1 4 300 | - - - - 301 | LD H,H 302 | 1 4 303 | - - - - 304 | LD H,L 305 | 1 4 306 | - - - - 307 | LD H,(HL) 308 | 1 8 309 | - - - - 310 | LD H,A 311 | 1 4 312 | - - - - 313 | LD L,B 314 | 1 4 315 | - - - - 316 | LD L,C 317 | 1 4 318 | - - - - 319 | LD L,D 320 | 1 4 321 | - - - - 322 | LD L,E 323 | 1 4 324 | - - - - 325 | LD L,H 326 | 1 4 327 | - - - - 328 | LD L,L 329 | 1 4 330 | - - - - 331 | LD L,(HL) 332 | 1 8 333 | - - - - 334 | LD L,A 335 | 1 4 336 | - - - - 337 | LD (HL),B 338 | 1 8 339 | - - - - 340 | LD (HL),C 341 | 1 8 342 | - - - - 343 | LD (HL),D 344 | 1 8 345 | - - - - 346 | LD (HL),E 347 | 1 8 348 | - - - - 349 | LD (HL),H 350 | 1 8 351 | - - - - 352 | LD (HL),L 353 | 1 8 354 | - - - - 355 | HALT 356 | 1 4 357 | - - - - 358 | LD (HL),A 359 | 1 8 360 | - - - - 361 | LD A,B 362 | 1 4 363 | - - - - 364 | LD A,C 365 | 1 4 366 | - - - - 367 | LD A,D 368 | 1 4 369 | - - - - 370 | LD A,E 371 | 1 4 372 | - - - - 373 | LD A,H 374 | 1 4 375 | - - - - 376 | LD A,L 377 | 1 4 378 | - - - - 379 | LD A,(HL) 380 | 1 8 381 | - - - - 382 | LD A,A 383 | 1 4 384 | - - - - 385 | ADD A,B 386 | 1 4 387 | Z 0 H C 388 | ADD A,C 389 | 1 4 390 | Z 0 H C 391 | ADD A,D 392 | 1 4 393 | Z 0 H C 394 | ADD A,E 395 | 1 4 396 | Z 0 H C 397 | ADD A,H 398 | 1 4 399 | Z 0 H C 400 | ADD A,L 401 | 1 4 402 | Z 0 H C 403 | ADD A,(HL) 404 | 1 8 405 | Z 0 H C 406 | ADD A,A 407 | 1 4 408 | Z 0 H C 409 | ADC A,B 410 | 1 4 411 | Z 0 H C 412 | ADC A,C 413 | 1 4 414 | Z 0 H C 415 | ADC A,D 416 | 1 4 417 | Z 0 H C 418 | ADC A,E 419 | 1 4 420 | Z 0 H C 421 | ADC A,H 422 | 1 4 423 | Z 0 H C 424 | ADC A,L 425 | 1 4 426 | Z 0 H C 427 | ADC A,(HL) 428 | 1 8 429 | Z 0 H C 430 | ADC A,A 431 | 1 4 432 | Z 0 H C 433 | SUB B 434 | 1 4 435 | Z 1 H C 436 | SUB C 437 | 1 4 438 | Z 1 H C 439 | SUB D 440 | 1 4 441 | Z 1 H C 442 | SUB E 443 | 1 4 444 | Z 1 H C 445 | SUB H 446 | 1 4 447 | Z 1 H C 448 | SUB L 449 | 1 4 450 | Z 1 H C 451 | SUB (HL) 452 | 1 8 453 | Z 1 H C 454 | SUB A 455 | 1 4 456 | Z 1 H C 457 | SBC A,B 458 | 1 4 459 | Z 1 H C 460 | SBC A,C 461 | 1 4 462 | Z 1 H C 463 | SBC A,D 464 | 1 4 465 | Z 1 H C 466 | SBC A,E 467 | 1 4 468 | Z 1 H C 469 | SBC A,H 470 | 1 4 471 | Z 1 H C 472 | SBC A,L 473 | 1 4 474 | Z 1 H C 475 | SBC A,(HL) 476 | 1 8 477 | Z 1 H C 478 | SBC A,A 479 | 1 4 480 | Z 1 H C 481 | AND B 482 | 1 4 483 | Z 0 1 0 484 | AND C 485 | 1 4 486 | Z 0 1 0 487 | AND D 488 | 1 4 489 | Z 0 1 0 490 | AND E 491 | 1 4 492 | Z 0 1 0 493 | AND H 494 | 1 4 495 | Z 0 1 0 496 | AND L 497 | 1 4 498 | Z 0 1 0 499 | AND (HL) 500 | 1 8 501 | Z 0 1 0 502 | AND A 503 | 1 4 504 | Z 0 1 0 505 | XOR B 506 | 1 4 507 | Z 0 0 0 508 | XOR C 509 | 1 4 510 | Z 0 0 0 511 | XOR D 512 | 1 4 513 | Z 0 0 0 514 | XOR E 515 | 1 4 516 | Z 0 0 0 517 | XOR H 518 | 1 4 519 | Z 0 0 0 520 | XOR L 521 | 1 4 522 | Z 0 0 0 523 | XOR (HL) 524 | 1 8 525 | Z 0 0 0 526 | XOR A 527 | 1 4 528 | Z 0 0 0 529 | OR B 530 | 1 4 531 | Z 0 0 0 532 | OR C 533 | 1 4 534 | Z 0 0 0 535 | OR D 536 | 1 4 537 | Z 0 0 0 538 | OR E 539 | 1 4 540 | Z 0 0 0 541 | OR H 542 | 1 4 543 | Z 0 0 0 544 | OR L 545 | 1 4 546 | Z 0 0 0 547 | OR (HL) 548 | 1 8 549 | Z 0 0 0 550 | OR A 551 | 1 4 552 | Z 0 0 0 553 | CP B 554 | 1 4 555 | Z 1 H C 556 | CP C 557 | 1 4 558 | Z 1 H C 559 | CP D 560 | 1 4 561 | Z 1 H C 562 | CP E 563 | 1 4 564 | Z 1 H C 565 | CP H 566 | 1 4 567 | Z 1 H C 568 | CP L 569 | 1 4 570 | Z 1 H C 571 | CP (HL) 572 | 1 8 573 | Z 1 H C 574 | CP A 575 | 1 4 576 | Z 1 H C 577 | RET NZ 578 | 1 20/8 579 | - - - - 580 | POP BC 581 | 1 12 582 | - - - - 583 | JP NZ,a16 584 | 3 16/12 585 | - - - - 586 | JP a16 587 | 3 16 588 | - - - - 589 | CALL NZ,a16 590 | 3 24/12 591 | - - - - 592 | PUSH BC 593 | 1 16 594 | - - - - 595 | ADD A,d8 596 | 2 8 597 | Z 0 H C 598 | RST 00H 599 | 1 16 600 | - - - - 601 | RET Z 602 | 1 20/8 603 | - - - - 604 | RET 605 | 1 16 606 | - - - - 607 | JP Z,a16 608 | 3 16/12 609 | - - - - 610 | PREFIX CB 611 | 1 4 612 | - - - - 613 | CALL Z,a16 614 | 3 24/12 615 | - - - - 616 | CALL a16 617 | 3 24 618 | - - - - 619 | ADC A,d8 620 | 2 8 621 | Z 0 H C 622 | RST 08H 623 | 1 16 624 | - - - - 625 | RET NC 626 | 1 20/8 627 | - - - - 628 | POP DE 629 | 1 12 630 | - - - - 631 | JP NC,a16 632 | 3 16/12 633 | - - - - 634 | NOP 635 | 1 4 636 | - - - - 637 | CALL NC,a16 638 | 3 24/12 639 | - - - - 640 | PUSH DE 641 | 1 16 642 | - - - - 643 | SUB d8 644 | 2 8 645 | Z 1 H C 646 | RST 10H 647 | 1 16 648 | - - - - 649 | RET C 650 | 1 20/8 651 | - - - - 652 | RETI 653 | 1 16 654 | - - - - 655 | JP C,a16 656 | 3 16/12 657 | - - - - 658 | NOP 659 | 1 4 660 | - - - - 661 | CALL C,a16 662 | 3 24/12 663 | - - - - 664 | NOP 665 | 1 4 666 | - - - - 667 | SBC A,d8 668 | 2 8 669 | Z 1 H C 670 | RST 18H 671 | 1 16 672 | - - - - 673 | LDH (a8),A 674 | 2 12 675 | - - - - 676 | POP HL 677 | 1 12 678 | - - - - 679 | LD (C),A 680 | 2 8 681 | - - - - 682 | NOP 683 | 1 4 684 | - - - - 685 | NOP 686 | 1 4 687 | - - - - 688 | PUSH HL 689 | 1 16 690 | - - - - 691 | AND d8 692 | 2 8 693 | Z 0 1 0 694 | RST 20H 695 | 1 16 696 | - - - - 697 | ADD SP,r8 698 | 2 16 699 | 0 0 H C 700 | JP (HL) 701 | 1 4 702 | - - - - 703 | LD (a16),A 704 | 3 16 705 | - - - - 706 | NOP 707 | 1 4 708 | - - - - 709 | NOP 710 | 1 4 711 | - - - - 712 | NOP 713 | 1 4 714 | - - - - 715 | XOR d8 716 | 2 8 717 | Z 0 0 0 718 | RST 28H 719 | 1 16 720 | - - - - 721 | LDH A,(a8) 722 | 2 12 723 | - - - - 724 | POP AF 725 | 1 12 726 | Z N H C 727 | LD A,(C) 728 | 2 8 729 | - - - - 730 | DI 731 | 1 4 732 | - - - - 733 | NOP 734 | 1 4 735 | - - - - 736 | PUSH AF 737 | 1 16 738 | - - - - 739 | OR d8 740 | 2 8 741 | Z 0 0 0 742 | RST 30H 743 | 1 16 744 | - - - - 745 | LD HL,SP+r8 746 | 2 12 747 | 0 0 H C 748 | LD SP,HL 749 | 1 8 750 | - - - - 751 | LD A,(a16) 752 | 3 16 753 | - - - - 754 | EI 755 | 1 4 756 | - - - - 757 | NOP 758 | 1 4 759 | - - - - 760 | NOP 761 | 1 4 762 | - - - - 763 | CP d8 764 | 2 8 765 | Z 1 H C 766 | RST 38H 767 | 1 16 768 | - - - - 769 | -------------------------------------------------------------------------------- /ops/cbops.txt: -------------------------------------------------------------------------------- 1 | RLC B 2 | 2 8 3 | Z 0 0 C 4 | RLC C 5 | 2 8 6 | Z 0 0 C 7 | RLC D 8 | 2 8 9 | Z 0 0 C 10 | RLC E 11 | 2 8 12 | Z 0 0 C 13 | RLC H 14 | 2 8 15 | Z 0 0 C 16 | RLC L 17 | 2 8 18 | Z 0 0 C 19 | RLC (HL) 20 | 2 16 21 | Z 0 0 C 22 | RLC A 23 | 2 8 24 | Z 0 0 C 25 | RRC B 26 | 2 8 27 | Z 0 0 C 28 | RRC C 29 | 2 8 30 | Z 0 0 C 31 | RRC D 32 | 2 8 33 | Z 0 0 C 34 | RRC E 35 | 2 8 36 | Z 0 0 C 37 | RRC H 38 | 2 8 39 | Z 0 0 C 40 | RRC L 41 | 2 8 42 | Z 0 0 C 43 | RRC (HL) 44 | 2 16 45 | Z 0 0 C 46 | RRC A 47 | 2 8 48 | Z 0 0 C 49 | RL B 50 | 2 8 51 | Z 0 0 C 52 | RL C 53 | 2 8 54 | Z 0 0 C 55 | RL D 56 | 2 8 57 | Z 0 0 C 58 | RL E 59 | 2 8 60 | Z 0 0 C 61 | RL H 62 | 2 8 63 | Z 0 0 C 64 | RL L 65 | 2 8 66 | Z 0 0 C 67 | RL (HL) 68 | 2 16 69 | Z 0 0 C 70 | RL A 71 | 2 8 72 | Z 0 0 C 73 | RR B 74 | 2 8 75 | Z 0 0 C 76 | RR C 77 | 2 8 78 | Z 0 0 C 79 | RR D 80 | 2 8 81 | Z 0 0 C 82 | RR E 83 | 2 8 84 | Z 0 0 C 85 | RR H 86 | 2 8 87 | Z 0 0 C 88 | RR L 89 | 2 8 90 | Z 0 0 C 91 | RR (HL) 92 | 2 16 93 | Z 0 0 C 94 | RR A 95 | 2 8 96 | Z 0 0 C 97 | SLA B 98 | 2 8 99 | Z 0 0 C 100 | SLA C 101 | 2 8 102 | Z 0 0 C 103 | SLA D 104 | 2 8 105 | Z 0 0 C 106 | SLA E 107 | 2 8 108 | Z 0 0 C 109 | SLA H 110 | 2 8 111 | Z 0 0 C 112 | SLA L 113 | 2 8 114 | Z 0 0 C 115 | SLA (HL) 116 | 2 16 117 | Z 0 0 C 118 | SLA A 119 | 2 8 120 | Z 0 0 C 121 | SRA B 122 | 2 8 123 | Z 0 0 C 124 | SRA C 125 | 2 8 126 | Z 0 0 C 127 | SRA D 128 | 2 8 129 | Z 0 0 C 130 | SRA E 131 | 2 8 132 | Z 0 0 C 133 | SRA H 134 | 2 8 135 | Z 0 0 C 136 | SRA L 137 | 2 8 138 | Z 0 0 C 139 | SRA (HL) 140 | 2 16 141 | Z 0 0 C 142 | SRA A 143 | 2 8 144 | Z 0 0 C 145 | SWAP B 146 | 2 8 147 | Z 0 0 0 148 | SWAP C 149 | 2 8 150 | Z 0 0 0 151 | SWAP D 152 | 2 8 153 | Z 0 0 0 154 | SWAP E 155 | 2 8 156 | Z 0 0 0 157 | SWAP H 158 | 2 8 159 | Z 0 0 0 160 | SWAP L 161 | 2 8 162 | Z 0 0 0 163 | SWAP (HL) 164 | 2 16 165 | Z 0 0 0 166 | SWAP A 167 | 2 8 168 | Z 0 0 0 169 | SRL B 170 | 2 8 171 | Z 0 0 C 172 | SRL C 173 | 2 8 174 | Z 0 0 C 175 | SRL D 176 | 2 8 177 | Z 0 0 C 178 | SRL E 179 | 2 8 180 | Z 0 0 C 181 | SRL H 182 | 2 8 183 | Z 0 0 C 184 | SRL L 185 | 2 8 186 | Z 0 0 C 187 | SRL (HL) 188 | 2 16 189 | Z 0 0 C 190 | SRL A 191 | 2 8 192 | Z 0 0 C 193 | BIT 0,B 194 | 2 8 195 | Z 0 1 - 196 | BIT 0,C 197 | 2 8 198 | Z 0 1 - 199 | BIT 0,D 200 | 2 8 201 | Z 0 1 - 202 | BIT 0,E 203 | 2 8 204 | Z 0 1 - 205 | BIT 0,H 206 | 2 8 207 | Z 0 1 - 208 | BIT 0,L 209 | 2 8 210 | Z 0 1 - 211 | BIT 0,(HL) 212 | 2 16 213 | Z 0 1 - 214 | BIT 0,A 215 | 2 8 216 | Z 0 1 - 217 | BIT 1,B 218 | 2 8 219 | Z 0 1 - 220 | BIT 1,C 221 | 2 8 222 | Z 0 1 - 223 | BIT 1,D 224 | 2 8 225 | Z 0 1 - 226 | BIT 1,E 227 | 2 8 228 | Z 0 1 - 229 | BIT 1,H 230 | 2 8 231 | Z 0 1 - 232 | BIT 1,L 233 | 2 8 234 | Z 0 1 - 235 | BIT 1,(HL) 236 | 2 16 237 | Z 0 1 - 238 | BIT 1,A 239 | 2 8 240 | Z 0 1 - 241 | BIT 2,B 242 | 2 8 243 | Z 0 1 - 244 | BIT 2,C 245 | 2 8 246 | Z 0 1 - 247 | BIT 2,D 248 | 2 8 249 | Z 0 1 - 250 | BIT 2,E 251 | 2 8 252 | Z 0 1 - 253 | BIT 2,H 254 | 2 8 255 | Z 0 1 - 256 | BIT 2,L 257 | 2 8 258 | Z 0 1 - 259 | BIT 2,(HL) 260 | 2 16 261 | Z 0 1 - 262 | BIT 2,A 263 | 2 8 264 | Z 0 1 - 265 | BIT 3,B 266 | 2 8 267 | Z 0 1 - 268 | BIT 3,C 269 | 2 8 270 | Z 0 1 - 271 | BIT 3,D 272 | 2 8 273 | Z 0 1 - 274 | BIT 3,E 275 | 2 8 276 | Z 0 1 - 277 | BIT 3,H 278 | 2 8 279 | Z 0 1 - 280 | BIT 3,L 281 | 2 8 282 | Z 0 1 - 283 | BIT 3,(HL) 284 | 2 16 285 | Z 0 1 - 286 | BIT 3,A 287 | 2 8 288 | Z 0 1 - 289 | BIT 4,B 290 | 2 8 291 | Z 0 1 - 292 | BIT 4,C 293 | 2 8 294 | Z 0 1 - 295 | BIT 4,D 296 | 2 8 297 | Z 0 1 - 298 | BIT 4,E 299 | 2 8 300 | Z 0 1 - 301 | BIT 4,H 302 | 2 8 303 | Z 0 1 - 304 | BIT 4,L 305 | 2 8 306 | Z 0 1 - 307 | BIT 4,(HL) 308 | 2 16 309 | Z 0 1 - 310 | BIT 4,A 311 | 2 8 312 | Z 0 1 - 313 | BIT 5,B 314 | 2 8 315 | Z 0 1 - 316 | BIT 5,C 317 | 2 8 318 | Z 0 1 - 319 | BIT 5,D 320 | 2 8 321 | Z 0 1 - 322 | BIT 5,E 323 | 2 8 324 | Z 0 1 - 325 | BIT 5,H 326 | 2 8 327 | Z 0 1 - 328 | BIT 5,L 329 | 2 8 330 | Z 0 1 - 331 | BIT 5,(HL) 332 | 2 16 333 | Z 0 1 - 334 | BIT 5,A 335 | 2 8 336 | Z 0 1 - 337 | BIT 6,B 338 | 2 8 339 | Z 0 1 - 340 | BIT 6,C 341 | 2 8 342 | Z 0 1 - 343 | BIT 6,D 344 | 2 8 345 | Z 0 1 - 346 | BIT 6,E 347 | 2 8 348 | Z 0 1 - 349 | BIT 6,H 350 | 2 8 351 | Z 0 1 - 352 | BIT 6,L 353 | 2 8 354 | Z 0 1 - 355 | BIT 6,(HL) 356 | 2 16 357 | Z 0 1 - 358 | BIT 6,A 359 | 2 8 360 | Z 0 1 - 361 | BIT 7,B 362 | 2 8 363 | Z 0 1 - 364 | BIT 7,C 365 | 2 8 366 | Z 0 1 - 367 | BIT 7,D 368 | 2 8 369 | Z 0 1 - 370 | BIT 7,E 371 | 2 8 372 | Z 0 1 - 373 | BIT 7,H 374 | 2 8 375 | Z 0 1 - 376 | BIT 7,L 377 | 2 8 378 | Z 0 1 - 379 | BIT 7,(HL) 380 | 2 16 381 | Z 0 1 - 382 | BIT 7,A 383 | 2 8 384 | Z 0 1 - 385 | RES 0,B 386 | 2 8 387 | - - - - 388 | RES 0,C 389 | 2 8 390 | - - - - 391 | RES 0,D 392 | 2 8 393 | - - - - 394 | RES 0,E 395 | 2 8 396 | - - - - 397 | RES 0,H 398 | 2 8 399 | - - - - 400 | RES 0,L 401 | 2 8 402 | - - - - 403 | RES 0,(HL) 404 | 2 16 405 | - - - - 406 | RES 0,A 407 | 2 8 408 | - - - - 409 | RES 1,B 410 | 2 8 411 | - - - - 412 | RES 1,C 413 | 2 8 414 | - - - - 415 | RES 1,D 416 | 2 8 417 | - - - - 418 | RES 1,E 419 | 2 8 420 | - - - - 421 | RES 1,H 422 | 2 8 423 | - - - - 424 | RES 1,L 425 | 2 8 426 | - - - - 427 | RES 1,(HL) 428 | 2 16 429 | - - - - 430 | RES 1,A 431 | 2 8 432 | - - - - 433 | RES 2,B 434 | 2 8 435 | - - - - 436 | RES 2,C 437 | 2 8 438 | - - - - 439 | RES 2,D 440 | 2 8 441 | - - - - 442 | RES 2,E 443 | 2 8 444 | - - - - 445 | RES 2,H 446 | 2 8 447 | - - - - 448 | RES 2,L 449 | 2 8 450 | - - - - 451 | RES 2,(HL) 452 | 2 16 453 | - - - - 454 | RES 2,A 455 | 2 8 456 | - - - - 457 | RES 3,B 458 | 2 8 459 | - - - - 460 | RES 3,C 461 | 2 8 462 | - - - - 463 | RES 3,D 464 | 2 8 465 | - - - - 466 | RES 3,E 467 | 2 8 468 | - - - - 469 | RES 3,H 470 | 2 8 471 | - - - - 472 | RES 3,L 473 | 2 8 474 | - - - - 475 | RES 3,(HL) 476 | 2 16 477 | - - - - 478 | RES 3,A 479 | 2 8 480 | - - - - 481 | RES 4,B 482 | 2 8 483 | - - - - 484 | RES 4,C 485 | 2 8 486 | - - - - 487 | RES 4,D 488 | 2 8 489 | - - - - 490 | RES 4,E 491 | 2 8 492 | - - - - 493 | RES 4,H 494 | 2 8 495 | - - - - 496 | RES 4,L 497 | 2 8 498 | - - - - 499 | RES 4,(HL) 500 | 2 16 501 | - - - - 502 | RES 4,A 503 | 2 8 504 | - - - - 505 | RES 5,B 506 | 2 8 507 | - - - - 508 | RES 5,C 509 | 2 8 510 | - - - - 511 | RES 5,D 512 | 2 8 513 | - - - - 514 | RES 5,E 515 | 2 8 516 | - - - - 517 | RES 5,H 518 | 2 8 519 | - - - - 520 | RES 5,L 521 | 2 8 522 | - - - - 523 | RES 5,(HL) 524 | 2 16 525 | - - - - 526 | RES 5,A 527 | 2 8 528 | - - - - 529 | RES 6,B 530 | 2 8 531 | - - - - 532 | RES 6,C 533 | 2 8 534 | - - - - 535 | RES 6,D 536 | 2 8 537 | - - - - 538 | RES 6,E 539 | 2 8 540 | - - - - 541 | RES 6,H 542 | 2 8 543 | - - - - 544 | RES 6,L 545 | 2 8 546 | - - - - 547 | RES 6,(HL) 548 | 2 16 549 | - - - - 550 | RES 6,A 551 | 2 8 552 | - - - - 553 | RES 7,B 554 | 2 8 555 | - - - - 556 | RES 7,C 557 | 2 8 558 | - - - - 559 | RES 7,D 560 | 2 8 561 | - - - - 562 | RES 7,E 563 | 2 8 564 | - - - - 565 | RES 7,H 566 | 2 8 567 | - - - - 568 | RES 7,L 569 | 2 8 570 | - - - - 571 | RES 7,(HL) 572 | 2 16 573 | - - - - 574 | RES 7,A 575 | 2 8 576 | - - - - 577 | SET 0,B 578 | 2 8 579 | - - - - 580 | SET 0,C 581 | 2 8 582 | - - - - 583 | SET 0,D 584 | 2 8 585 | - - - - 586 | SET 0,E 587 | 2 8 588 | - - - - 589 | SET 0,H 590 | 2 8 591 | - - - - 592 | SET 0,L 593 | 2 8 594 | - - - - 595 | SET 0,(HL) 596 | 2 16 597 | - - - - 598 | SET 0,A 599 | 2 8 600 | - - - - 601 | SET 1,B 602 | 2 8 603 | - - - - 604 | SET 1,C 605 | 2 8 606 | - - - - 607 | SET 1,D 608 | 2 8 609 | - - - - 610 | SET 1,E 611 | 2 8 612 | - - - - 613 | SET 1,H 614 | 2 8 615 | - - - - 616 | SET 1,L 617 | 2 8 618 | - - - - 619 | SET 1,(HL) 620 | 2 16 621 | - - - - 622 | SET 1,A 623 | 2 8 624 | - - - - 625 | SET 2,B 626 | 2 8 627 | - - - - 628 | SET 2,C 629 | 2 8 630 | - - - - 631 | SET 2,D 632 | 2 8 633 | - - - - 634 | SET 2,E 635 | 2 8 636 | - - - - 637 | SET 2,H 638 | 2 8 639 | - - - - 640 | SET 2,L 641 | 2 8 642 | - - - - 643 | SET 2,(HL) 644 | 2 16 645 | - - - - 646 | SET 2,A 647 | 2 8 648 | - - - - 649 | SET 3,B 650 | 2 8 651 | - - - - 652 | SET 3,C 653 | 2 8 654 | - - - - 655 | SET 3,D 656 | 2 8 657 | - - - - 658 | SET 3,E 659 | 2 8 660 | - - - - 661 | SET 3,H 662 | 2 8 663 | - - - - 664 | SET 3,L 665 | 2 8 666 | - - - - 667 | SET 3,(HL) 668 | 2 16 669 | - - - - 670 | SET 3,A 671 | 2 8 672 | - - - - 673 | SET 4,B 674 | 2 8 675 | - - - - 676 | SET 4,C 677 | 2 8 678 | - - - - 679 | SET 4,D 680 | 2 8 681 | - - - - 682 | SET 4,E 683 | 2 8 684 | - - - - 685 | SET 4,H 686 | 2 8 687 | - - - - 688 | SET 4,L 689 | 2 8 690 | - - - - 691 | SET 4,(HL) 692 | 2 16 693 | - - - - 694 | SET 4,A 695 | 2 8 696 | - - - - 697 | SET 5,B 698 | 2 8 699 | - - - - 700 | SET 5,C 701 | 2 8 702 | - - - - 703 | SET 5,D 704 | 2 8 705 | - - - - 706 | SET 5,E 707 | 2 8 708 | - - - - 709 | SET 5,H 710 | 2 8 711 | - - - - 712 | SET 5,L 713 | 2 8 714 | - - - - 715 | SET 5,(HL) 716 | 2 16 717 | - - - - 718 | SET 5,A 719 | 2 8 720 | - - - - 721 | SET 6,B 722 | 2 8 723 | - - - - 724 | SET 6,C 725 | 2 8 726 | - - - - 727 | SET 6,D 728 | 2 8 729 | - - - - 730 | SET 6,E 731 | 2 8 732 | - - - - 733 | SET 6,H 734 | 2 8 735 | - - - - 736 | SET 6,L 737 | 2 8 738 | - - - - 739 | SET 6,(HL) 740 | 2 16 741 | - - - - 742 | SET 6,A 743 | 2 8 744 | - - - - 745 | SET 7,B 746 | 2 8 747 | - - - - 748 | SET 7,C 749 | 2 8 750 | - - - - 751 | SET 7,D 752 | 2 8 753 | - - - - 754 | SET 7,E 755 | 2 8 756 | - - - - 757 | SET 7,H 758 | 2 8 759 | - - - - 760 | SET 7,L 761 | 2 8 762 | - - - - 763 | SET 7,(HL) 764 | 2 16 765 | - - - - 766 | SET 7,A 767 | 2 8 768 | - - - - 769 | -------------------------------------------------------------------------------- /z80.v: -------------------------------------------------------------------------------- 1 | module z80( 2 | clock, resetn, 3 | address, indata, outdata, load, store, 4 | intreq, intaddress, intack, 5 | du, df, daf, dbc, dde, dhl, dsp, dpc 6 | ); 7 | 8 | input clock; 9 | input resetn; 10 | 11 | output [15:0] address = bus_a; 12 | input [7:0] indata; 13 | output reg [7:0] outdata; 14 | output load; 15 | output store; 16 | 17 | input intreq; 18 | input [15:0] intaddress; 19 | output reg intack; 20 | 21 | output [15:0] du = u; 22 | output [3:0] df = f; 23 | output [15:0] daf = {a,f,4'h0}; 24 | output [15:0] dbc = {b,c}; 25 | output [15:0] dde = {d,e}; 26 | output [15:0] dhl = {h,l}; 27 | output [15:0] dsp = sp; 28 | output [15:0] dpc = pc; 29 | 30 | 31 | reg [15:0] u; 32 | 33 | wire [15:0] uc_u; 34 | wire [4:0] uc_d; 35 | wire [4:0] uc_op; 36 | wire [4:0] uc_a; 37 | wire [4:0] uc_b; 38 | wire [4:0] uc_cc; 39 | 40 | reg ie; 41 | 42 | z80_ucode uc(u, clock, resetn, {uc_u, uc_d, uc_op, uc_a, uc_b, load, store, uc_cc}); 43 | 44 | always @(*) begin 45 | if (intreq && ie && (uc_u[7:0] == 8'h00 || uc_u[7:0] == 8'h70)) begin 46 | u = 16'h0050; 47 | end else if (uc_d == D_UC) begin 48 | u = {bus_d[7:0], bus_d[15:8]}; 49 | end else begin 50 | u = uc_u; 51 | end 52 | 53 | intack = (uc_d == D_IACK); 54 | end 55 | 56 | 57 | reg [7:0] a; 58 | reg [3:0] f; 59 | reg [7:0] b; 60 | reg [7:0] c; 61 | reg [7:0] d; 62 | reg [7:0] e; 63 | reg [7:0] h; 64 | reg [7:0] l; 65 | reg [15:0] sp; 66 | reg [15:0] pc; 67 | 68 | reg [15:0] temp; 69 | 70 | 71 | reg [15:0] bus_a; 72 | reg [15:0] bus_b; 73 | wire [15:0] bus_d; 74 | wire [3:0] nf; 75 | 76 | z80_alu alu(bus_d, uc_op, bus_a, bus_b, f, nf); 77 | 78 | 79 | always @(*) begin 80 | case (uc_a) 81 | A_0: bus_a = 16'h0; 82 | A_1: bus_a = 16'h1; 83 | A_8: bus_a = 16'h08; 84 | A_10: bus_a = 16'h10; 85 | A_18: bus_a = 16'h18; 86 | A_20: bus_a = 16'h20; 87 | A_28: bus_a = 16'h28; 88 | A_30: bus_a = 16'h30; 89 | A_38: bus_a = 16'h38; 90 | A_PC: bus_a = pc; 91 | A_UC: bus_a = {uc_u[7:0], uc_u[15:8]}; 92 | A_D16: bus_a = {indata, temp[7:0]}; 93 | A_D8: bus_a = {{8{indata[7]}}, indata}; 94 | A_A: bus_a = {{8{a[7]}}, a}; 95 | A_B: bus_a = {{8{b[7]}}, b}; 96 | A_C: bus_a = {{8{c[7]}}, c}; 97 | A_D: bus_a = {{8{d[7]}}, d}; 98 | A_E: bus_a = {{8{e[7]}}, e}; 99 | A_H: bus_a = {{8{h[7]}}, h}; 100 | A_L: bus_a = {{8{l[7]}}, l}; 101 | A_AF: bus_a = {a, f, 4'h0}; 102 | A_BC: bus_a = {b, c}; 103 | A_DE: bus_a = {d, e}; 104 | A_HL: bus_a = {h, l}; 105 | A_SP: bus_a = sp; 106 | A_IADDR: bus_a = intaddress; 107 | A_TEMP: bus_a = temp; 108 | A_MASK: bus_a = 16'hff00; 109 | default: bus_a = 16'h0000; 110 | endcase 111 | end 112 | 113 | always @(*) begin 114 | case (uc_b) 115 | B_0: bus_b = 16'h0; 116 | B_1: bus_b = 16'h1; 117 | B_2: bus_b = 16'h02; 118 | B_4: bus_b = 16'h04; 119 | B_8: bus_b = 16'h08; 120 | B_10: bus_b = 16'h10; 121 | B_20: bus_b = 16'h20; 122 | B_40: bus_b = 16'h40; 123 | B_80: bus_b = 16'h80; 124 | B_fe: bus_b = 16'hfe; 125 | B_fd: bus_b = 16'hfd; 126 | B_fb: bus_b = 16'hfb; 127 | B_f7: bus_b = 16'hf7; 128 | B_ef: bus_b = 16'hef; 129 | B_df: bus_b = 16'hdf; 130 | B_bf: bus_b = 16'hbf; 131 | B_7f: bus_b = 16'h7f; 132 | B_D8: bus_b = {{8{indata[7]}}, indata}; 133 | B_A: bus_b = {{8{a[7]}}, a}; 134 | B_F: bus_b = {8'h00, f, 4'h0}; 135 | B_B: bus_b = {{8{b[7]}}, b}; 136 | B_C: bus_b = {{8{c[7]}}, c}; 137 | B_D: bus_b = {{8{d[7]}}, d}; 138 | B_E: bus_b = {{8{e[7]}}, e}; 139 | B_H: bus_b = {{8{h[7]}}, h}; 140 | B_L: bus_b = {{8{l[7]}}, l}; 141 | B_BC: bus_b = {b, c}; 142 | B_DE: bus_b = {d, e}; 143 | B_HL: bus_b = {h, l}; 144 | B_SP: bus_b = sp; 145 | B_IE: bus_b = ie; 146 | default: bus_b = 16'h0000; 147 | endcase 148 | end 149 | 150 | always @(posedge clock or negedge resetn) begin 151 | if (!resetn) begin 152 | pc <= 16'h0000; 153 | sp <= 16'hfffe; 154 | a <= 8'h01; // 8'h11 for gbc 155 | f <= 4'hb; 156 | b <= 8'h00; 157 | c <= 8'h13; 158 | d <= 8'h00; 159 | e <= 8'hd8; 160 | h <= 8'h01; 161 | l <= 8'h4d; 162 | ie <= 0; 163 | end else begin 164 | case (uc_d) 165 | D_PC: pc <= bus_d; 166 | D_DATA: outdata <= bus_d[7:0]; 167 | D_A: a <= bus_d[7:0]; 168 | D_B: b <= bus_d[7:0]; 169 | D_C: c <= bus_d[7:0]; 170 | D_D: d <= bus_d[7:0]; 171 | D_E: e <= bus_d[7:0]; 172 | D_H: h <= bus_d[7:0]; 173 | D_L: l <= bus_d[7:0]; 174 | D_AF: begin a <= bus_d[15:8]; f <= bus_d[7:4]; end 175 | D_BC: begin b <= bus_d[15:8]; c <= bus_d[7:0]; end 176 | D_DE: begin d <= bus_d[15:8]; e <= bus_d[7:0]; end 177 | D_HL: begin h <= bus_d[15:8]; l <= bus_d[7:0]; end 178 | D_SP: sp <= bus_d; 179 | D_IE: ie <= bus_d[0]; 180 | D_TEMP: temp <= bus_d; 181 | endcase 182 | 183 | case (uc_cc) 184 | CC_Z0Hx: begin f[3] <= nf[3]; f[2] <= 1'b0; f[1] <= nf[1]; end 185 | CC_Z1Hx: begin f[3] <= nf[3]; f[2] <= 1'b1; f[1] <= nf[1]; end 186 | CC_000C: begin f[3] <= 1'b0; f[2] <= 1'b0; f[1] <= 1'b0; f[0] <= nf[0]; end 187 | CC_x0HC: begin f[2] <= 1'b0; f[1] <= nf[1]; f[0] <= nf[0]; end 188 | CC_Zx0C: begin f[3] <= nf[3]; f[1] <= 1'b0; f[0] <= nf[0]; end 189 | CC_x11x: begin f[2] <= 1'b1; f[1] <= 1'b1; end 190 | CC_x001: begin f[2] <= 1'b0; f[1] <= 1'b0; f[0] <= 1'b1; end 191 | CC_Z0HC: begin f[3] <= nf[3]; f[2] <= 1'b0; f[1] <= nf[1]; f[0] <= nf[0]; end 192 | CC_x00x: begin f[2] <= 1'b0; f[1] <= 1'b0; end 193 | CC_Z1HC: begin f[3] <= nf[3]; f[2] <= 1'b1; f[1] <= nf[1]; f[0] <= nf[0]; end 194 | CC_Z010: begin f[3] <= nf[3]; f[2] <= 1'b0; f[1] <= 1'b1; f[0] <= 1'b0; end 195 | CC_Z000: begin f[3] <= nf[3]; f[2] <= 1'b0; f[1] <= 1'b0; f[0] <= 1'b0; end 196 | CC_00HC: begin f[3] <= 1'b0; f[2] <= 1'b0; f[1] <= nf[1]; f[0] <= nf[0]; end 197 | CC_Z00C: begin f[3] <= nf[3]; f[2] <= 1'b0; f[1] <= 1'b0; f[0] <= nf[0]; end 198 | CC_Z01x: begin f[3] <= nf[3]; f[2] <= 1'b0; f[1] <= 1'b1; end 199 | endcase 200 | end 201 | end 202 | 203 | 204 | 205 | 206 | parameter D_0 = 5'h00; 207 | parameter D_PC = 5'h01; 208 | parameter D_UC = 5'h02; 209 | parameter D_A = 5'h03; 210 | parameter D_B = 5'h04; 211 | parameter D_C = 5'h05; 212 | parameter D_D = 5'h06; 213 | parameter D_E = 5'h07; 214 | parameter D_H = 5'h08; 215 | parameter D_L = 5'h09; 216 | parameter D_AF = 5'h0a; 217 | parameter D_BC = 5'h0b; 218 | parameter D_DE = 5'h0c; 219 | parameter D_HL = 5'h0d; 220 | parameter D_SP = 5'h0e; 221 | parameter D_IE = 5'h0f; 222 | parameter D_IACK = 5'h10; 223 | parameter D_TEMP = 5'h11; 224 | parameter D_DATA = 5'h12; 225 | 226 | parameter A_0 = 5'h00; 227 | parameter A_1 = 5'h01; 228 | parameter A_8 = 5'h02; 229 | parameter A_10 = 5'h03; 230 | parameter A_18 = 5'h04; 231 | parameter A_20 = 5'h05; 232 | parameter A_28 = 5'h06; 233 | parameter A_30 = 5'h07; 234 | parameter A_38 = 5'h08; 235 | parameter A_PC = 5'h09; 236 | parameter A_UC = 5'h0a; 237 | parameter A_D16 = 5'h0b; 238 | parameter A_D8 = 5'h0c; 239 | parameter A_A = 5'h0d; 240 | parameter A_B = 5'h0e; 241 | parameter A_C = 5'h0f; 242 | parameter A_D = 5'h10; 243 | parameter A_E = 5'h11; 244 | parameter A_H = 5'h12; 245 | parameter A_L = 5'h13; 246 | parameter A_AF = 5'h14; 247 | parameter A_BC = 5'h15; 248 | parameter A_DE = 5'h16; 249 | parameter A_HL = 5'h17; 250 | parameter A_SP = 5'h18; 251 | parameter A_IADDR = 5'h19; 252 | parameter A_TEMP = 5'h1a; 253 | parameter A_MASK = 5'h1b; 254 | 255 | parameter B_0 = 5'h00; 256 | parameter B_1 = 5'h01; 257 | parameter B_2 = 5'h02; 258 | parameter B_4 = 5'h03; 259 | parameter B_8 = 5'h04; 260 | parameter B_10 = 5'h05; 261 | parameter B_20 = 5'h06; 262 | parameter B_40 = 5'h07; 263 | parameter B_80 = 5'h08; 264 | parameter B_fe = 5'h09; 265 | parameter B_fd = 5'h0a; 266 | parameter B_fb = 5'h0b; 267 | parameter B_f7 = 5'h0c; 268 | parameter B_ef = 5'h0d; 269 | parameter B_df = 5'h0e; 270 | parameter B_bf = 5'h0f; 271 | parameter B_7f = 5'h10; 272 | parameter B_D8 = 5'h11; 273 | parameter B_A = 5'h12; 274 | parameter B_F = 5'h13; 275 | parameter B_B = 5'h14; 276 | parameter B_C = 5'h15; 277 | parameter B_D = 5'h16; 278 | parameter B_E = 5'h17; 279 | parameter B_H = 5'h18; 280 | parameter B_L = 5'h19; 281 | parameter B_BC = 5'h1a; 282 | parameter B_DE = 5'h1b; 283 | parameter B_HL = 5'h1c; 284 | parameter B_SP = 5'h1d; 285 | parameter B_IE = 5'h1e; 286 | 287 | parameter CC_xxxx = 5'h00; 288 | parameter CC_Z0Hx = 5'h01; 289 | parameter CC_Z1Hx = 5'h02; 290 | parameter CC_000C = 5'h03; 291 | parameter CC_x0HC = 5'h04; 292 | parameter CC_Zx0C = 5'h05; 293 | parameter CC_x11x = 5'h06; 294 | parameter CC_x001 = 5'h07; 295 | parameter CC_Z0HC = 5'h08; 296 | parameter CC_x00x = 5'h09; 297 | parameter CC_Z1HC = 5'h0a; 298 | parameter CC_Z010 = 5'h0b; 299 | parameter CC_Z000 = 5'h0c; 300 | parameter CC_00HC = 5'h0d; 301 | parameter CC_ZNHC = 5'h0e; 302 | parameter CC_Z00C = 5'h0f; 303 | parameter CC_Z01x = 5'h10; 304 | 305 | endmodule 306 | -------------------------------------------------------------------------------- /memory/vram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: vram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module vram ( 41 | data, 42 | rdaddress, 43 | rdclock, 44 | wraddress, 45 | wrclock, 46 | wren, 47 | q); 48 | 49 | input [5:0] data; 50 | input [15:0] rdaddress; 51 | input rdclock; 52 | input [15:0] wraddress; 53 | input wrclock; 54 | input wren; 55 | output [5:0] q; 56 | `ifndef ALTERA_RESERVED_QIS 57 | // synopsys translate_off 58 | `endif 59 | tri1 wrclock; 60 | tri0 wren; 61 | `ifndef ALTERA_RESERVED_QIS 62 | // synopsys translate_on 63 | `endif 64 | 65 | wire [5:0] sub_wire0; 66 | wire [5:0] q = sub_wire0[5:0]; 67 | 68 | altsyncram altsyncram_component ( 69 | .address_a (wraddress), 70 | .address_b (rdaddress), 71 | .clock0 (wrclock), 72 | .clock1 (rdclock), 73 | .data_a (data), 74 | .wren_a (wren), 75 | .q_b (sub_wire0), 76 | .aclr0 (1'b0), 77 | .aclr1 (1'b0), 78 | .addressstall_a (1'b0), 79 | .addressstall_b (1'b0), 80 | .byteena_a (1'b1), 81 | .byteena_b (1'b1), 82 | .clocken0 (1'b1), 83 | .clocken1 (1'b1), 84 | .clocken2 (1'b1), 85 | .clocken3 (1'b1), 86 | .data_b ({6{1'b1}}), 87 | .eccstatus (), 88 | .q_a (), 89 | .rden_a (1'b1), 90 | .rden_b (1'b1), 91 | .wren_b (1'b0)); 92 | defparam 93 | altsyncram_component.address_aclr_b = "NONE", 94 | altsyncram_component.address_reg_b = "CLOCK1", 95 | altsyncram_component.clock_enable_input_a = "BYPASS", 96 | altsyncram_component.clock_enable_input_b = "BYPASS", 97 | altsyncram_component.clock_enable_output_b = "BYPASS", 98 | altsyncram_component.intended_device_family = "Cyclone V", 99 | altsyncram_component.lpm_type = "altsyncram", 100 | altsyncram_component.numwords_a = 36864, 101 | altsyncram_component.numwords_b = 36864, 102 | altsyncram_component.operation_mode = "DUAL_PORT", 103 | altsyncram_component.outdata_aclr_b = "NONE", 104 | altsyncram_component.outdata_reg_b = "CLOCK1", 105 | altsyncram_component.power_up_uninitialized = "FALSE", 106 | altsyncram_component.widthad_a = 16, 107 | altsyncram_component.widthad_b = 16, 108 | altsyncram_component.width_a = 6, 109 | altsyncram_component.width_b = 6, 110 | altsyncram_component.width_byteena_a = 1; 111 | 112 | 113 | endmodule 114 | 115 | // ============================================================ 116 | // CNX file retrieval info 117 | // ============================================================ 118 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 120 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 121 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 122 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 123 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 125 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 126 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 127 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 128 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 129 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 130 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 131 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 132 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 133 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 134 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 135 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 136 | // Retrieval info: PRIVATE: Clock NUMERIC "1" 137 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 139 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 140 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 141 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 142 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 143 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 144 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 145 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 146 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 147 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 148 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "221184" 149 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 150 | // Retrieval info: PRIVATE: MIFfilename STRING "" 151 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 152 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 153 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" 154 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 155 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 156 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 157 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 158 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 159 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 160 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 161 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 162 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 163 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 164 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 165 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 166 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 167 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 168 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6" 169 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6" 170 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6" 171 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6" 172 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 173 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 174 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 175 | // Retrieval info: PRIVATE: enable NUMERIC "0" 176 | // Retrieval info: PRIVATE: rden NUMERIC "0" 177 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 178 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" 179 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" 180 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 181 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 182 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 183 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 184 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 185 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "36864" 186 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "36864" 187 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 188 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 189 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" 190 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 191 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16" 192 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16" 193 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "6" 194 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "6" 195 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 196 | // Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL "data[5..0]" 197 | // Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]" 198 | // Retrieval info: USED_PORT: rdaddress 0 0 16 0 INPUT NODEFVAL "rdaddress[15..0]" 199 | // Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" 200 | // Retrieval info: USED_PORT: wraddress 0 0 16 0 INPUT NODEFVAL "wraddress[15..0]" 201 | // Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" 202 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 203 | // Retrieval info: CONNECT: @address_a 0 0 16 0 wraddress 0 0 16 0 204 | // Retrieval info: CONNECT: @address_b 0 0 16 0 rdaddress 0 0 16 0 205 | // Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 206 | // Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 207 | // Retrieval info: CONNECT: @data_a 0 0 6 0 data 0 0 6 0 208 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 209 | // Retrieval info: CONNECT: q 0 0 6 0 @q_b 0 0 6 0 210 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE 211 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE 212 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE 213 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE 214 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE 215 | // Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v TRUE 216 | // Retrieval info: LIB_FILE: altera_mf 217 | -------------------------------------------------------------------------------- /gb.v: -------------------------------------------------------------------------------- 1 | 2 | //======================================================= 3 | // This code is generated by Terasic System Builder 4 | //======================================================= 5 | 6 | module gb( 7 | 8 | //////////// CLOCK ////////// 9 | CLOCK_125_p, 10 | CLOCK_50_B5B, 11 | CLOCK_50_B6A, 12 | CLOCK_50_B7A, 13 | CLOCK_50_B8A, 14 | 15 | //////////// LED ////////// 16 | LEDG, 17 | LEDR, 18 | 19 | //////////// KEY ////////// 20 | CPU_RESET_n, 21 | KEY, 22 | 23 | //////////// SW ////////// 24 | SW, 25 | 26 | //////////// SEG7 ////////// 27 | HEX0, 28 | HEX1, 29 | HEX2, 30 | HEX3, 31 | 32 | //////////// HDMI-TX ////////// 33 | HDMI_TX_CLK, 34 | HDMI_TX_D, 35 | HDMI_TX_DE, 36 | HDMI_TX_HS, 37 | HDMI_TX_INT, 38 | HDMI_TX_VS, 39 | 40 | //////////// Audio ////////// 41 | AUD_ADCDAT, 42 | AUD_ADCLRCK, 43 | AUD_BCLK, 44 | AUD_DACDAT, 45 | AUD_DACLRCK, 46 | AUD_XCK, 47 | 48 | //////////// I2C for Audio/HDMI-TX/Si5338/HSMC ////////// 49 | I2C_SCL, 50 | I2C_SDA, 51 | 52 | //////////// Uart to USB ////////// 53 | UART_RX, 54 | UART_TX, 55 | 56 | //////////// SRAM ////////// 57 | SRAM_A, 58 | SRAM_CE_n, 59 | SRAM_D, 60 | SRAM_LB_n, 61 | SRAM_OE_n, 62 | SRAM_UB_n, 63 | SRAM_WE_n 64 | ); 65 | 66 | //======================================================= 67 | // PARAMETER declarations 68 | //======================================================= 69 | 70 | 71 | //======================================================= 72 | // PORT declarations 73 | //======================================================= 74 | 75 | //////////// CLOCK ////////// 76 | input CLOCK_125_p; 77 | input CLOCK_50_B5B; 78 | input CLOCK_50_B6A; 79 | input CLOCK_50_B7A; 80 | input CLOCK_50_B8A; 81 | 82 | //////////// LED ////////// 83 | output [7:0] LEDG; 84 | output [9:0] LEDR; 85 | 86 | //////////// KEY ////////// 87 | input CPU_RESET_n; 88 | input [3:0] KEY; 89 | 90 | //////////// SW ////////// 91 | input [9:0] SW; 92 | 93 | //////////// SEG7 ////////// 94 | output [6:0] HEX0; 95 | output [6:0] HEX1; 96 | output [6:0] HEX2; 97 | output [6:0] HEX3; 98 | 99 | //////////// HDMI-TX ////////// 100 | output HDMI_TX_CLK; 101 | output [23:0] HDMI_TX_D; 102 | output HDMI_TX_DE; 103 | output HDMI_TX_HS; 104 | input HDMI_TX_INT; 105 | output HDMI_TX_VS; 106 | 107 | //////////// Audio ////////// 108 | input AUD_ADCDAT; 109 | inout AUD_ADCLRCK; 110 | inout AUD_BCLK; 111 | output AUD_DACDAT; 112 | inout AUD_DACLRCK; 113 | output AUD_XCK; 114 | 115 | //////////// I2C for Audio/HDMI-TX/Si5338/HSMC ////////// 116 | output I2C_SCL; 117 | inout I2C_SDA; 118 | 119 | //////////// Uart to USB ////////// 120 | input UART_RX; 121 | output UART_TX; 122 | 123 | //////////// SRAM ////////// 124 | output [17:0] SRAM_A; 125 | output SRAM_CE_n; 126 | inout [15:0] SRAM_D; 127 | output SRAM_LB_n; 128 | output SRAM_OE_n; 129 | output SRAM_UB_n; 130 | output SRAM_WE_n; 131 | 132 | 133 | 134 | // Clocking // 135 | wire clock50mhz = CLOCK_50_B5B; 136 | 137 | wire clock25mhz; 138 | wire clock12500khz; 139 | wire clock8mhz; 140 | wire clock4mhz; 141 | wire clock1mhz; 142 | wire clock250khz; 143 | wire clock62500hz; 144 | wire clock115200hz; 145 | wire clock460800hz; 146 | 147 | div #(2) div25mhz(clock50mhz, clock25mhz); 148 | div #(4) div12500khz(clock50mhz, clock12500khz); 149 | div #(6) div8mhz(clock50mhz, clock8mhz); 150 | div #(12) div4mhz(clock50mhz, clock4mhz); 151 | div #(434) div115200hz(clock50mhz, clock115200hz); // previously 434 152 | div #(434/4) div460800hz(clock50mhz, clock460800hz); 153 | 154 | div #(4) div1mhz(clock4mhz, clock1mhz); 155 | div #(4) div250khz(clock1mhz, clock250khz); 156 | div #(4) div62500hz(clock250khz, clock62500hz); 157 | 158 | wire clockgb = SW[8] ? clock8mhz : 159 | SW[7] ? clock4mhz : 160 | SW[6] ? clock1mhz : 161 | SW[5] ? clock250khz : 162 | SW[4] ? clock62500hz : KEY[3]; 163 | 164 | wire hard_resetn = KEY[1]; 165 | wire resetn = KEY[1] & KEY[0]; 166 | 167 | 168 | // Connecting Wires // 169 | reg [15:0] bus_address; 170 | reg [7:0] bus_outdata; 171 | reg bus_load; 172 | reg bus_store; 173 | 174 | wire [7:0] bus_data = ppu_data | link_data | timer_data | 175 | joy_data | dma_data | 176 | rom_data | loram_data; 177 | 178 | wire [7:0] cpu_data = hiram_data | int_data; 179 | 180 | 181 | always @(*) begin 182 | if (!dma_active) begin 183 | bus_address = cpu_address; 184 | bus_outdata = cpu_outdata; 185 | bus_load = cpu_load; 186 | bus_store = cpu_store; 187 | 188 | if (boot_active) begin 189 | cpu_indata = boot_data; 190 | end else begin 191 | cpu_indata = cpu_data | bus_data; 192 | end 193 | dma_indata = 0; 194 | end else begin 195 | bus_address = dma_address; 196 | bus_outdata = dma_outdata; 197 | bus_load = dma_load; 198 | bus_store = dma_store; 199 | 200 | cpu_indata = cpu_data; 201 | dma_indata = bus_data; 202 | end 203 | end 204 | 205 | 206 | assign UART_TX = link_tx & rom_tx & joy_tx; 207 | 208 | 209 | // Boot ROM // 210 | wire [7:0] boot_data; 211 | wire boot_active; 212 | 213 | boot boot( 214 | clockgb, resetn, 215 | bus_address, bus_outdata, boot_data, bus_load, bus_store, 216 | boot_active 217 | ); 218 | 219 | 220 | // APU // 221 | wire [7:0] apu_data; 222 | 223 | apu apu( 224 | clock25mhz, clock12500khz, clockgb, hard_resetn, resetn, 225 | bus_address, bus_outdata, apu_data, bus_load, bus_store, 226 | 227 | //////////// Audio ////////// 228 | AUD_ADCDAT, 229 | AUD_ADCLRCK, 230 | AUD_BCLK, 231 | AUD_DACDAT, 232 | AUD_DACLRCK, 233 | AUD_XCK 234 | ); 235 | 236 | 237 | 238 | // PPU // 239 | wire [7:0] ppu_data; 240 | wire vblank_int; 241 | wire lcdc_int; 242 | wire [1:0] dmode; 243 | 244 | ppu ppu( 245 | clock25mhz, clockgb, hard_resetn, resetn, vblank_int, lcdc_int, 246 | bus_address, bus_outdata, ppu_data, bus_load, bus_store, 247 | 248 | //////////// HDMI-TX ////////// 249 | HDMI_TX_CLK, 250 | HDMI_TX_D, 251 | HDMI_TX_DE, 252 | HDMI_TX_HS, 253 | HDMI_TX_INT, 254 | HDMI_TX_VS, 255 | dmode 256 | ); 257 | 258 | 259 | // Link Cable (Primarily for debugging) // 260 | wire [7:0] link_data; 261 | wire link_tx; 262 | 263 | link link( 264 | clock115200hz, clockgb, resetn, 265 | bus_address, bus_outdata, link_data, bus_load, bus_store, 266 | 267 | //////////// Uart to USB ////////// 268 | UART_RX, 269 | link_tx 270 | ); 271 | 272 | 273 | // Timer // 274 | wire [7:0] timer_data; 275 | wire timer_int; 276 | wire [7:0] dtimer; 277 | 278 | timer timer( 279 | clockgb, resetn, timer_int, 280 | bus_address, bus_outdata, timer_data, bus_load, bus_store, 281 | dtimer 282 | ); 283 | 284 | 285 | // Joypad over UART // 286 | wire [7:0] joy_data; 287 | wire joy_tx; 288 | wire joy_int; 289 | 290 | joypad joypad( 291 | clock460800hz, clockgb, resetn, joy_int, 292 | bus_address, bus_outdata, joy_data, bus_load, bus_store, 293 | 294 | //////////// Uart to USB ////////// 295 | UART_RX, 296 | joy_tx 297 | ); 298 | 299 | 300 | // DMA // 301 | wire [7:0] dma_data; 302 | 303 | wire [15:0] dma_address; 304 | wire [7:0] dma_outdata; 305 | reg [7:0] dma_indata; 306 | wire dma_load; 307 | wire dma_store; 308 | wire dma_active; 309 | 310 | dma dma( 311 | clockgb, resetn, 312 | bus_address, bus_outdata, dma_data, bus_load, bus_store, 313 | dma_address, dma_indata, dma_outdata, dma_load, dma_store, 314 | dma_active 315 | ); 316 | 317 | 318 | // Cartridge ROM // 319 | wire [7:0] rom_data; 320 | wire rom_tx; 321 | 322 | mbc1 mbc1( 323 | SW[9] ? clock4mhz : clockgb, clock115200hz, clock460800hz, resetn, 324 | bus_address, bus_outdata, rom_data, bus_load, bus_store, SW[9], 325 | 326 | //////////// Uart to USB ////////// 327 | UART_RX, 328 | rom_tx, 329 | 330 | //////////// SRAM ////////// 331 | SRAM_A, 332 | SRAM_CE_n, 333 | SRAM_D, 334 | SRAM_LB_n, 335 | SRAM_OE_n, 336 | SRAM_UB_n, 337 | SRAM_WE_n 338 | ); 339 | 340 | 341 | // Low RAM (Large) // 342 | wire [15:0] loram_address; 343 | wire [7:0] loram_indata; 344 | wire [7:0] loram_outdata; 345 | wire [7:0] loram_data; 346 | wire loram_store; 347 | 348 | loram loram( 349 | loram_address[12:0], 350 | clockgb, 351 | loram_indata, 352 | loram_store, 353 | loram_outdata 354 | ); 355 | 356 | mmap #(16'hc000, 16'hfdff) loram_mmap( 357 | clockgb, resetn, 358 | bus_address, bus_outdata, loram_data, bus_load, bus_store, 359 | loram_address, loram_indata, loram_outdata,, loram_store 360 | ); 361 | 362 | 363 | // High RAM (Small but faster) // 364 | wire [15:0] hiram_address; 365 | wire [7:0] hiram_indata; 366 | wire [7:0] hiram_outdata; 367 | wire [7:0] hiram_data; 368 | wire hiram_store; 369 | 370 | hiram hiram( 371 | hiram_address, 372 | clockgb, 373 | hiram_indata, 374 | hiram_store, 375 | hiram_outdata 376 | ); 377 | 378 | mmap #(16'hff80, 16'hfffe) hiram_mmap( 379 | clockgb, resetn, 380 | cpu_address, cpu_outdata, hiram_data, cpu_load, cpu_store, 381 | hiram_address, hiram_indata, hiram_outdata,, hiram_store 382 | ); 383 | 384 | 385 | // Interrupt Handling // 386 | wire [7:0] int_data; 387 | wire int_req; 388 | wire [15:0] int_address; 389 | wire int_ack; 390 | wire [4:0] dints; 391 | 392 | inthandle inth( 393 | clockgb, resetn, 394 | cpu_address, cpu_outdata, int_data, cpu_load, cpu_store, 395 | {joy_int, 1'b0, timer_int, lcdc_int, vblank_int}, 396 | int_req, int_address, int_ack, 397 | dints 398 | ); 399 | 400 | 401 | // CPU // 402 | wire [15:0] cpu_address; 403 | wire [7:0] cpu_outdata; 404 | reg [7:0] cpu_indata; 405 | wire cpu_load; 406 | wire cpu_store; 407 | 408 | wire [15:0] du; 409 | wire [3:0] df; 410 | wire [15:0] daf; 411 | wire [15:0] dbc; 412 | wire [15:0] dde; 413 | wire [15:0] dhl; 414 | wire [15:0] dsp; 415 | wire [15:0] dpc; 416 | 417 | z80 cpu( 418 | clockgb, resetn, 419 | cpu_address, cpu_indata, cpu_outdata, cpu_load, cpu_store, 420 | int_req, int_address, int_ack, 421 | du, df, daf, dbc, dde, dhl, dsp, dpc 422 | ); 423 | 424 | 425 | // Debugging Signals // 426 | assign LEDR[9:5] = dints; 427 | assign LEDR[1:0] = dmode; 428 | assign LEDG[7:4] = df; 429 | assign LEDG[3] = dma_load; 430 | assign LEDG[2] = dma_store; 431 | assign LEDG[1] = cpu_load; 432 | assign LEDG[0] = cpu_store; 433 | 434 | reg [15:0] debug; 435 | seg16 segs(debug, {HEX3,HEX2,HEX1,HEX0}); 436 | 437 | always @(*) begin 438 | case (SW[3:0]) 439 | 4'b1101: debug = dpc; 440 | 4'b1100: debug = dsp; 441 | 4'b1011: debug = dhl; 442 | 4'b1010: debug = dde; 443 | 4'b1001: debug = dbc; 444 | 4'b1000: debug = daf; 445 | 4'b0100: debug = dtimer; 446 | default: debug = du; 447 | endcase 448 | end 449 | 450 | endmodule 451 | -------------------------------------------------------------------------------- /memory/bgram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: bgram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module bgram ( 41 | address_a, 42 | address_b, 43 | clock, 44 | data_a, 45 | data_b, 46 | wren_a, 47 | wren_b, 48 | q_a, 49 | q_b); 50 | 51 | input [10:0] address_a; 52 | input [10:0] address_b; 53 | input clock; 54 | input [7:0] data_a; 55 | input [7:0] data_b; 56 | input wren_a; 57 | input wren_b; 58 | output [7:0] q_a; 59 | output [7:0] q_b; 60 | `ifndef ALTERA_RESERVED_QIS 61 | // synopsys translate_off 62 | `endif 63 | tri1 clock; 64 | tri0 wren_a; 65 | tri0 wren_b; 66 | `ifndef ALTERA_RESERVED_QIS 67 | // synopsys translate_on 68 | `endif 69 | 70 | wire [7:0] sub_wire0; 71 | wire [7:0] sub_wire1; 72 | wire [7:0] q_a = sub_wire0[7:0]; 73 | wire [7:0] q_b = sub_wire1[7:0]; 74 | 75 | altsyncram altsyncram_component ( 76 | .address_a (address_a), 77 | .address_b (address_b), 78 | .clock0 (clock), 79 | .data_a (data_a), 80 | .data_b (data_b), 81 | .wren_a (wren_a), 82 | .wren_b (wren_b), 83 | .q_a (sub_wire0), 84 | .q_b (sub_wire1), 85 | .aclr0 (1'b0), 86 | .aclr1 (1'b0), 87 | .addressstall_a (1'b0), 88 | .addressstall_b (1'b0), 89 | .byteena_a (1'b1), 90 | .byteena_b (1'b1), 91 | .clock1 (1'b1), 92 | .clocken0 (1'b1), 93 | .clocken1 (1'b1), 94 | .clocken2 (1'b1), 95 | .clocken3 (1'b1), 96 | .eccstatus (), 97 | .rden_a (1'b1), 98 | .rden_b (1'b1)); 99 | defparam 100 | altsyncram_component.address_reg_b = "CLOCK0", 101 | altsyncram_component.clock_enable_input_a = "BYPASS", 102 | altsyncram_component.clock_enable_input_b = "BYPASS", 103 | altsyncram_component.clock_enable_output_a = "BYPASS", 104 | altsyncram_component.clock_enable_output_b = "BYPASS", 105 | altsyncram_component.indata_reg_b = "CLOCK0", 106 | altsyncram_component.intended_device_family = "Cyclone V", 107 | altsyncram_component.lpm_type = "altsyncram", 108 | altsyncram_component.numwords_a = 2048, 109 | altsyncram_component.numwords_b = 2048, 110 | altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", 111 | altsyncram_component.outdata_aclr_a = "NONE", 112 | altsyncram_component.outdata_aclr_b = "NONE", 113 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 114 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 115 | altsyncram_component.power_up_uninitialized = "FALSE", 116 | altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", 117 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 118 | altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", 119 | altsyncram_component.widthad_a = 11, 120 | altsyncram_component.widthad_b = 11, 121 | altsyncram_component.width_a = 8, 122 | altsyncram_component.width_b = 8, 123 | altsyncram_component.width_byteena_a = 1, 124 | altsyncram_component.width_byteena_b = 1, 125 | altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; 126 | 127 | 128 | endmodule 129 | 130 | // ============================================================ 131 | // CNX file retrieval info 132 | // ============================================================ 133 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 134 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 135 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 136 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 137 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 139 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 140 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 141 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 142 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 143 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 144 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 145 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 146 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 147 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 148 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 149 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 150 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 151 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 152 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 153 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 154 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 155 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 156 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 157 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 158 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 159 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 160 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 161 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 162 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 163 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" 164 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 165 | // Retrieval info: PRIVATE: MIFfilename STRING "" 166 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 167 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 168 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 169 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 170 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 171 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 172 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 173 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 174 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 175 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 176 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 177 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 178 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 179 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 180 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 181 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 182 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 183 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" 184 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" 185 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" 186 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" 187 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 188 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 189 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 190 | // Retrieval info: PRIVATE: enable NUMERIC "0" 191 | // Retrieval info: PRIVATE: rden NUMERIC "0" 192 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 193 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 194 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 195 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 196 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 197 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 198 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 199 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 200 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 201 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" 202 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" 203 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 204 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 205 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 206 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 207 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 208 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 209 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 210 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 211 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 212 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" 213 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" 214 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 215 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" 216 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 217 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 218 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 219 | // Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]" 220 | // Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]" 221 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 222 | // Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" 223 | // Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" 224 | // Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" 225 | // Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" 226 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 227 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 228 | // Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0 229 | // Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0 230 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 231 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 232 | // Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 233 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 234 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 235 | // Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 236 | // Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 237 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.v TRUE 238 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.inc FALSE 239 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.cmp FALSE 240 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram.bsf FALSE 241 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram_inst.v FALSE 242 | // Retrieval info: GEN_FILE: TYPE_NORMAL bgram_bb.v TRUE 243 | // Retrieval info: LIB_FILE: altera_mf 244 | -------------------------------------------------------------------------------- /gb.sdc: -------------------------------------------------------------------------------- 1 | ## Generated SDC file "gb.sdc" 2 | 3 | ## Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 4 | ## Your use of Altera Corporation's design tools, logic functions 5 | ## and other software and tools, and its AMPP partner logic 6 | ## functions, and any output files from any of the foregoing 7 | ## (including device programming or simulation files), and any 8 | ## associated documentation or information are expressly subject 9 | ## to the terms and conditions of the Altera Program License 10 | ## Subscription Agreement, the Altera Quartus II License Agreement, 11 | ## the Altera MegaCore Function License Agreement, or other 12 | ## applicable license agreement, including, without limitation, 13 | ## that your use is for the sole purpose of programming logic 14 | ## devices manufactured by Altera and sold by Altera or its 15 | ## authorized distributors. Please refer to the applicable 16 | ## agreement for further details. 17 | 18 | 19 | ## VENDOR "Altera" 20 | ## PROGRAM "Quartus II" 21 | ## VERSION "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition" 22 | 23 | ## DATE "Thu Dec 04 13:52:27 2014" 24 | 25 | ## 26 | ## DEVICE "5CGXFC5C6F27C7" 27 | ## 28 | 29 | 30 | #************************************************************** 31 | # Time Information 32 | #************************************************************** 33 | 34 | set_time_format -unit ns -decimal_places 3 35 | 36 | 37 | 38 | #************************************************************** 39 | # Create Clock 40 | #************************************************************** 41 | 42 | create_clock -name {CLOCK_125_p} -period 8.000 -waveform { 0.000 4.000 } [get_ports {CLOCK_125_p}] 43 | create_clock -name {CLOCK_50_B5B} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50_B5B}] 44 | create_clock -name {CLOCK_50_B6A} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50_B6A}] 45 | create_clock -name {CLOCK_50_B7A} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50_B7A}] 46 | create_clock -name {CLOCK_50_B8A} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50_B8A}] 47 | create_clock -name {div:div4mhz|out} -period 250.000 -waveform { 0.000 125.000 } [get_nets {div4mhz|out}] 48 | create_clock -name {div:div115200hz|out} -period 8000.000 -waveform { 0.000 4000.000 } [get_nets {div115200hz|out}] 49 | create_clock -name {div:div460800hz|out} -period 2000.000 -waveform { 0.000 1000.000 } [get_nets {div460800hz|out}] 50 | create_clock -name {div:div12500khz|out} -period 80.000 -waveform { 0.000 40.000 } [get_nets {div12500khz|out}] 51 | create_clock -name {div:div25mhz|out} -period 40.000 -waveform { 0.000 20.000 } [get_nets {div25mhz|out}] 52 | 53 | 54 | #************************************************************** 55 | # Create Generated Clock 56 | #************************************************************** 57 | 58 | 59 | 60 | #************************************************************** 61 | # Set Clock Latency 62 | #************************************************************** 63 | 64 | 65 | 66 | #************************************************************** 67 | # Set Clock Uncertainty 68 | #************************************************************** 69 | 70 | set_clock_uncertainty -rise_from [get_clocks {div:div25mhz|out}] -rise_to [get_clocks {div:div25mhz|out}] 0.270 71 | set_clock_uncertainty -rise_from [get_clocks {div:div25mhz|out}] -fall_to [get_clocks {div:div25mhz|out}] 0.270 72 | set_clock_uncertainty -rise_from [get_clocks {div:div25mhz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 73 | set_clock_uncertainty -rise_from [get_clocks {div:div25mhz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 74 | set_clock_uncertainty -fall_from [get_clocks {div:div25mhz|out}] -rise_to [get_clocks {div:div25mhz|out}] 0.270 75 | set_clock_uncertainty -fall_from [get_clocks {div:div25mhz|out}] -fall_to [get_clocks {div:div25mhz|out}] 0.270 76 | set_clock_uncertainty -fall_from [get_clocks {div:div25mhz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 77 | set_clock_uncertainty -fall_from [get_clocks {div:div25mhz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 78 | set_clock_uncertainty -rise_from [get_clocks {div:div12500khz|out}] -rise_to [get_clocks {div:div12500khz|out}] 0.270 79 | set_clock_uncertainty -rise_from [get_clocks {div:div12500khz|out}] -fall_to [get_clocks {div:div12500khz|out}] 0.270 80 | set_clock_uncertainty -rise_from [get_clocks {div:div12500khz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 81 | set_clock_uncertainty -rise_from [get_clocks {div:div12500khz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 82 | set_clock_uncertainty -fall_from [get_clocks {div:div12500khz|out}] -rise_to [get_clocks {div:div12500khz|out}] 0.270 83 | set_clock_uncertainty -fall_from [get_clocks {div:div12500khz|out}] -fall_to [get_clocks {div:div12500khz|out}] 0.270 84 | set_clock_uncertainty -fall_from [get_clocks {div:div12500khz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 85 | set_clock_uncertainty -fall_from [get_clocks {div:div12500khz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 86 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {div:div460800hz|out}] 0.270 87 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {div:div460800hz|out}] 0.270 88 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {div:div115200hz|out}] 0.270 89 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {div:div115200hz|out}] 0.270 90 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {div:div4mhz|out}] 0.270 91 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {div:div4mhz|out}] 0.270 92 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 93 | set_clock_uncertainty -rise_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 94 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {div:div460800hz|out}] 0.270 95 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {div:div460800hz|out}] 0.270 96 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {div:div115200hz|out}] 0.270 97 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {div:div115200hz|out}] 0.270 98 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {div:div4mhz|out}] 0.270 99 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {div:div4mhz|out}] 0.270 100 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 101 | set_clock_uncertainty -fall_from [get_clocks {div:div460800hz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 102 | set_clock_uncertainty -rise_from [get_clocks {div:div115200hz|out}] -rise_to [get_clocks {div:div115200hz|out}] 0.270 103 | set_clock_uncertainty -rise_from [get_clocks {div:div115200hz|out}] -fall_to [get_clocks {div:div115200hz|out}] 0.270 104 | set_clock_uncertainty -rise_from [get_clocks {div:div115200hz|out}] -rise_to [get_clocks {div:div4mhz|out}] 0.270 105 | set_clock_uncertainty -rise_from [get_clocks {div:div115200hz|out}] -fall_to [get_clocks {div:div4mhz|out}] 0.270 106 | set_clock_uncertainty -rise_from [get_clocks {div:div115200hz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 107 | set_clock_uncertainty -rise_from [get_clocks {div:div115200hz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 108 | set_clock_uncertainty -fall_from [get_clocks {div:div115200hz|out}] -rise_to [get_clocks {div:div115200hz|out}] 0.270 109 | set_clock_uncertainty -fall_from [get_clocks {div:div115200hz|out}] -fall_to [get_clocks {div:div115200hz|out}] 0.270 110 | set_clock_uncertainty -fall_from [get_clocks {div:div115200hz|out}] -rise_to [get_clocks {div:div4mhz|out}] 0.270 111 | set_clock_uncertainty -fall_from [get_clocks {div:div115200hz|out}] -fall_to [get_clocks {div:div4mhz|out}] 0.270 112 | set_clock_uncertainty -fall_from [get_clocks {div:div115200hz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 113 | set_clock_uncertainty -fall_from [get_clocks {div:div115200hz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 114 | set_clock_uncertainty -rise_from [get_clocks {div:div4mhz|out}] -rise_to [get_clocks {div:div115200hz|out}] 0.270 115 | set_clock_uncertainty -rise_from [get_clocks {div:div4mhz|out}] -fall_to [get_clocks {div:div115200hz|out}] 0.270 116 | set_clock_uncertainty -rise_from [get_clocks {div:div4mhz|out}] -rise_to [get_clocks {div:div4mhz|out}] 0.270 117 | set_clock_uncertainty -rise_from [get_clocks {div:div4mhz|out}] -fall_to [get_clocks {div:div4mhz|out}] 0.270 118 | set_clock_uncertainty -rise_from [get_clocks {div:div4mhz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 119 | set_clock_uncertainty -rise_from [get_clocks {div:div4mhz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 120 | set_clock_uncertainty -fall_from [get_clocks {div:div4mhz|out}] -rise_to [get_clocks {div:div115200hz|out}] 0.270 121 | set_clock_uncertainty -fall_from [get_clocks {div:div4mhz|out}] -fall_to [get_clocks {div:div115200hz|out}] 0.270 122 | set_clock_uncertainty -fall_from [get_clocks {div:div4mhz|out}] -rise_to [get_clocks {div:div4mhz|out}] 0.270 123 | set_clock_uncertainty -fall_from [get_clocks {div:div4mhz|out}] -fall_to [get_clocks {div:div4mhz|out}] 0.270 124 | set_clock_uncertainty -fall_from [get_clocks {div:div4mhz|out}] -rise_to [get_clocks {CLOCK_50_B5B}] 0.270 125 | set_clock_uncertainty -fall_from [get_clocks {div:div4mhz|out}] -fall_to [get_clocks {CLOCK_50_B5B}] 0.270 126 | set_clock_uncertainty -rise_from [get_clocks {CLOCK_50_B5B}] -rise_to [get_clocks {CLOCK_50_B5B}] -setup 0.280 127 | set_clock_uncertainty -rise_from [get_clocks {CLOCK_50_B5B}] -rise_to [get_clocks {CLOCK_50_B5B}] -hold 0.270 128 | set_clock_uncertainty -rise_from [get_clocks {CLOCK_50_B5B}] -fall_to [get_clocks {CLOCK_50_B5B}] -setup 0.280 129 | set_clock_uncertainty -rise_from [get_clocks {CLOCK_50_B5B}] -fall_to [get_clocks {CLOCK_50_B5B}] -hold 0.270 130 | set_clock_uncertainty -fall_from [get_clocks {CLOCK_50_B5B}] -rise_to [get_clocks {CLOCK_50_B5B}] -setup 0.280 131 | set_clock_uncertainty -fall_from [get_clocks {CLOCK_50_B5B}] -rise_to [get_clocks {CLOCK_50_B5B}] -hold 0.270 132 | set_clock_uncertainty -fall_from [get_clocks {CLOCK_50_B5B}] -fall_to [get_clocks {CLOCK_50_B5B}] -setup 0.280 133 | set_clock_uncertainty -fall_from [get_clocks {CLOCK_50_B5B}] -fall_to [get_clocks {CLOCK_50_B5B}] -hold 0.270 134 | 135 | 136 | #************************************************************** 137 | # Set Input Delay 138 | #************************************************************** 139 | 140 | 141 | 142 | #************************************************************** 143 | # Set Output Delay 144 | #************************************************************** 145 | 146 | 147 | 148 | #************************************************************** 149 | # Set Clock Groups 150 | #************************************************************** 151 | 152 | 153 | 154 | #************************************************************** 155 | # Set False Path 156 | #************************************************************** 157 | 158 | 159 | 160 | #************************************************************** 161 | # Set Multicycle Path 162 | #************************************************************** 163 | 164 | 165 | 166 | #************************************************************** 167 | # Set Maximum Delay 168 | #************************************************************** 169 | 170 | 171 | 172 | #************************************************************** 173 | # Set Minimum Delay 174 | #************************************************************** 175 | 176 | 177 | 178 | #************************************************************** 179 | # Set Input Transition 180 | #************************************************************** 181 | 182 | --------------------------------------------------------------------------------