├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── Shakefile.hs ├── clash-1.4.6.yaml ├── image ├── font.dat └── intel8080 │ ├── Makefile │ ├── README │ ├── tinybasic-2.0.bin │ ├── tinybasic-2.0.hex │ └── tinybasic-2.0.prn ├── mk ├── package.yaml ├── src ├── Hardware │ ├── ACIA.hs │ └── TinyBASIC │ │ ├── Intel8080.hs │ │ ├── Keyboard.hs │ │ ├── Sim.hs │ │ └── Video.hs └── intel8080 │ ├── model.hs │ ├── serial-board.hs │ ├── sim.hs │ └── video-board.hs ├── stack.yaml ├── stack.yaml.lock └── target ├── nexys-a7-50t ├── serial │ └── src-hdl │ │ ├── TinyBASICSerial.v │ │ └── nexys-a7-50t.xdc └── video │ ├── ip │ └── ClockWiz25.xci │ └── src-hdl │ ├── TinyBASICVideo.v │ └── nexys-a7-50t.xdc ├── papilio-one ├── serial │ └── src-hdl │ │ ├── PapilioOne-Base.ucf │ │ ├── PapilioOne.ucf │ │ └── TinyBASICSerial.v └── video │ ├── ipcore_dir │ └── DCM25.xaw │ └── src-hdl │ ├── PapilioOne-Arcade.ucf │ ├── PapilioOne-Base.ucf │ ├── PapilioOne.ucf │ └── TinyBASICVideo.v └── papilio-pro ├── serial └── src-hdl │ ├── PapilioPro-Base.ucf │ ├── PapilioPro.ucf │ └── TinyBASICSerial.v └── video ├── ipcore_dir └── ClockMan25.xco └── src-hdl ├── PapilioPro-Arcade.ucf ├── PapilioPro-Base.ucf ├── PapilioPro.ucf └── TinyBASICVideo.v /.gitignore: -------------------------------------------------------------------------------- 1 | /*.cabal 2 | _build 3 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "clash-intel8080"] 2 | path = clash-intel8080 3 | url = git@github.com:gergoerdi/clash-intel8080.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Gergő Érdi (http://gergo.erdi.hu/) 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Tiny BASIC computer implemented in Clash 2 | ======================================== 3 | 4 | As seen in 5 | 6 | This code is part of the book *Retrocomputing with Clash: Haskell for 7 | FPGA Hardware Design* at . 8 | 9 | ## Building into a bitfile 10 | 11 | The included `mk` script runs the included Shake rules and creates a 12 | bitfile ready to upload on a supported FPGA dev board. Targets are 13 | made up from three specifiers: **core**, **IO** and **FPGA board**. 14 | 15 | Available CPU cores: 16 | 17 | - `intel8080` 18 | 19 | Available IO modes: 20 | 21 | - `serial`: serial IO 22 | - `video`: PS/2 keyboard input, 640⨯480 VGA output 23 | 24 | Available FPGA boards: 25 | 26 | - [`papilio-one`][1] (with the Arcade MegaWing for `video`) 27 | - [`papilio-pro`][2] (with the Arcade MegaWing for `video`) 28 | - [`nexys-a7-50t`][3] 29 | 30 | Note that only the Nexys A7-50T target is tested extensively, the 31 | others might accumulate some bit-rot. 32 | 33 | First, create a `build.mk` file that describes your local build 34 | environment and your build target: 35 | 36 | ``` 37 | VIVADO_ROOT=/path/to/vivado/installation 38 | TARGET=intel8080/video/nexys-a7-50t 39 | ``` 40 | 41 | Alternatively, if you are using the Vivado or ISE toolchain via a 42 | wrapper script (e.g. to run it in Docker), instead of `VIVADO_ROOT` or 43 | `ISE_ROOT`, you can set `VIVADO` or `ISE` to the wrapper script's name: 44 | 45 | ``` 46 | VIVADO=/path/to/vivado-wrapper 47 | ``` 48 | 49 | The script will be called with the first argument being the Vivado 50 | tool's name, and the rest of the arguments are the arguments to the 51 | tool itself. 52 | 53 | Once you have `build.mk`, you can run `mk` and upload to your FPGA 54 | board the `TinyBASICVIdeo.bit` file from the 55 | `_build/intel8080/video/nexys-a7-50t/synth/TinyBASICVIdeo/TinyBASICVideo.runs/impl_1` 56 | directory (or just do `./mk intel8080/video/nexys-a7-50t/upload`). 57 | 58 | ## Building the simulators 59 | 60 | There are two simulators included: 61 | 62 | * A ["very high-level"][4] simulation that only uses the CPU 63 | implementation from Clash, and the rest is Haskell. 64 | 65 | * A logic board simulation that simulates not just the CPU, but also 66 | the memory elements, including the memory address decoding. 67 | 68 | To build the simulations, just do a `stack build`. 69 | 70 | [1]: https://papilio.cc/index.php?n=Papilio.PapilioPro 71 | [2]: https://papilio.cc/index.php?n=Papilio.PapilioOne 72 | [3]: https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start 73 | [4]: https://gergo.erdi.hu/blog/2018-09-15-very_high-level_simulation_of_a_c_ash_cpu/ 74 | -------------------------------------------------------------------------------- /Shakefile.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE OverloadedStrings, RecordWildCards, NumericUnderscores #-} 2 | import Clash.Shake 3 | import Clash.Shake.Xilinx 4 | 5 | import Development.Shake 6 | import Development.Shake.Command 7 | import Development.Shake.FilePath 8 | import Development.Shake.Config 9 | import Development.Shake.Util 10 | 11 | import Clash.Prelude hiding (lift) 12 | import qualified Data.ByteString as BS 13 | import qualified Data.List as L 14 | import Data.Word 15 | import Data.Maybe (fromMaybe) 16 | import Control.Monad.Reader 17 | import Control.Monad.Trans.Class 18 | 19 | -- import Paths_tinybasic -- XXX 20 | 21 | targets = 22 | [ ("nexys-a7-50t", xilinxVivado nexysA750T, 100_000_000) 23 | , ("papilio-pro", xilinxISE papilioPro, 32_000_000) 24 | , ("papilio-one", xilinxISE papilioOne, 32_000_000) 25 | ] 26 | 27 | outDir = "_build" 28 | 29 | fontFile = outDir "font.bin" 30 | 31 | intel8080 :: Rules () 32 | intel8080 = do 33 | let binFile = outDir "intel8080/image.bin" 34 | binFile %> \out -> do 35 | let imageFile = "image/intel8080/tinybasic-2.0.bin" 36 | binImage (Just $ 0x0800) imageFile out 37 | 38 | do 39 | let targetDir = outDir "intel8080/video" 40 | 41 | kit@ClashKit{..} <- clashRules (targetDir "clash") Verilog 42 | [ "src" ] 43 | "src/intel8080/video-board.hs" 44 | [ "-Wno-partial-type-signatures" 45 | , "-fclash-inline-limit=600" 46 | ] $ 47 | need [binFile, fontFile] 48 | 49 | forM_ targets $ \(name, synth, _) -> do 50 | SynthKit{..} <- synth kit (targetDir name "synth") ("target" name "video") "TinyBASICVideo" 51 | 52 | mapM_ (uncurry $ nestedPhony ("intel8080/video" name)) $ 53 | ("bitfile", need [bitfile]): 54 | phonies 55 | 56 | nestedPhony ("intel8080/video") "clashi" $ 57 | clash ["--interactive", "src/intel8080/video-board.hs"] 58 | 59 | forM_ targets $ \(name, synth, clock) -> do 60 | let targetDir = outDir "intel8080/serial" name 61 | 62 | kit@ClashKit{..} <- clashRules (targetDir "clash") Verilog 63 | [ "src" ] 64 | "src/intel8080/serial-board.hs" 65 | [ "-Wno-partial-type-signatures" 66 | , "-fclash-inline-limit=600" 67 | , "-D__NATIVE_CLOCK__=" <> show clock 68 | ] $ 69 | need [binFile] 70 | SynthKit{..} <- synth kit (targetDir "synth") ("target" name "serial") "TinyBASICSerial" 71 | 72 | mapM_ (uncurry $ nestedPhony ("intel8080/serial" name)) $ 73 | ("clashi", clash ["--interactive", "src/intel8080/serial-board.hs"]) : 74 | ("bitfile", need [bitfile]): 75 | phonies 76 | 77 | main :: IO () 78 | main = shakeArgs shakeOptions{ shakeFiles = outDir } $ do 79 | useConfig "build.mk" 80 | 81 | phony "clean" $ do 82 | putNormal $ "Cleaning files in " <> outDir 83 | removeFilesAfter outDir [ "//*" ] 84 | 85 | fontFile %> \out -> do 86 | let imageFile = "image/font.dat" 87 | binImage (Just $ 8 * 256) imageFile out 88 | 89 | intel8080 90 | -------------------------------------------------------------------------------- /clash-1.4.6.yaml: -------------------------------------------------------------------------------- 1 | name: clash-1.4.6 2 | resolver: lts-18.14 3 | 4 | packages: 5 | - clash-prelude-1.4.6 6 | - clash-lib-1.4.6 7 | - clash-ghc-1.4.6 8 | -------------------------------------------------------------------------------- /image/font.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gergoerdi/clash-tinybasic/8cd35f8306c459b3fee198ac48ef17df56f97fa2/image/font.dat -------------------------------------------------------------------------------- /image/intel8080/Makefile: -------------------------------------------------------------------------------- 1 | all: tinybasic-2.0.bin 2 | 3 | %.bin: %.hex 4 | objcopy --gap-fill 0 --input-target=ihex --output-target=binary $< $@ 5 | 6 | -------------------------------------------------------------------------------- /image/intel8080/README: -------------------------------------------------------------------------------- 1 | ************************************************************* 2 | 3 | TINY BASIC FOR INTEL 8080 4 | VERSION 2.0 5 | BY LI-CHEN WANG 6 | MODIFIED AND TRANSLATED 7 | TO INTEL MNEMONICS 8 | BY ROGER RAUSKOLB 9 | 10 OCTOBER,1976 10 | @COPYLEFT 11 | ALL WRONGS RESERVED 12 | 13 | ************************************************************* 14 | 15 | From https://www.autometer.de/unix4fun/z80pack/ftp/altair 16 | -------------------------------------------------------------------------------- /image/intel8080/tinybasic-2.0.bin: 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:1007000050813B831D524E448425414253845053B3 114 | :10071000495A458459840B544F820884C95354451F 115 | :1007200050821282163E3D83332383393E833F3D00 116 | :10073000834E3C3D83463C8354835A21B006EFD51B 117 | :100740001A13FE2ECA5D0723BECA40073E7F1BBE9A 118 | :10075000DA640723BED2530723D1C33E073E7F236B 119 | :0C076000BED25F077E236EE67F67F1E9E2 120 | :00000001FF 121 | -------------------------------------------------------------------------------- /mk: -------------------------------------------------------------------------------- 1 | stack runhaskell --package clash-shake -- Shakefile.hs $@ 2 | -------------------------------------------------------------------------------- /package.yaml: -------------------------------------------------------------------------------- 1 | name: tinybasic 2 | version: 0.0.0.0 3 | synopsis: "TinyBASIC machine: CPU core and serial IO" 4 | homepage: https://github.com/gergoerdi/clash-tinybasic 5 | license: MIT 6 | author: Gergő Érdi 7 | maintainer: gergo@erdi.hu 8 | copyright: 2020 Gergő Érdi 9 | category: Hardware 10 | 11 | extra-source-files: 12 | - LICENSE 13 | - README.md 14 | 15 | data-files: 16 | - image/*/* 17 | 18 | dependencies: 19 | - base >= 4.7 && < 5 20 | - clash-prelude 21 | - ghc-typelits-natnormalise 22 | - ghc-typelits-extra 23 | - ghc-typelits-knownnat 24 | 25 | - retroclash-lib 26 | - clash-shake 27 | - intel8080 28 | 29 | - bytestring 30 | - mtl 31 | - transformers 32 | - array 33 | 34 | # Anything that Clash uses by default should go here 35 | default-extensions: 36 | - BinaryLiterals 37 | - ConstraintKinds 38 | - DataKinds 39 | - DeriveAnyClass 40 | - DeriveGeneric 41 | - DeriveLift 42 | - DerivingStrategies 43 | - ExplicitForAll 44 | - ExplicitNamespaces 45 | - FlexibleContexts 46 | - FlexibleInstances 47 | - KindSignatures 48 | - MagicHash 49 | - MonoLocalBinds 50 | - NoImplicitPrelude 51 | - NoStarIsType 52 | - NoStrictData 53 | - NoStrict 54 | - QuasiQuotes 55 | - ScopedTypeVariables 56 | - TemplateHaskellQuotes 57 | - TemplateHaskell 58 | - TypeApplications 59 | - TypeFamilies 60 | - TypeOperators 61 | 62 | ghc-options: 63 | -fexpose-all-unfoldings -fno-worker-wrapper 64 | -fplugin GHC.TypeLits.KnownNat.Solver 65 | -fplugin GHC.TypeLits.Normalise 66 | -fplugin GHC.TypeLits.Extra.Solver 67 | 68 | source-dirs: 69 | - src 70 | 71 | flags: 72 | sim: 73 | manual: True 74 | default: True 75 | 76 | executables: 77 | tinybasic-intel8080-model: 78 | main: intel8080/model.hs 79 | dependencies: 80 | - terminal 81 | when: 82 | - condition: "!flag(sim)" 83 | buildable: false 84 | 85 | tinybasic-intel8080-sim: 86 | main: intel8080/sim.hs 87 | dependencies: 88 | - retroclash-sim 89 | - terminal 90 | when: 91 | - condition: "!flag(sim)" 92 | buildable: false 93 | -------------------------------------------------------------------------------- /src/Hardware/ACIA.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE LambdaCase #-} 2 | module Hardware.ACIA where 3 | 4 | import Clash.Prelude 5 | 6 | import RetroClash.Utils 7 | import RetroClash.Port 8 | 9 | import Data.Maybe 10 | import Control.Monad.State 11 | import Control.Monad.Writer 12 | import Data.Traversable (for) 13 | import Control.Arrow (second) 14 | 15 | -- Asynchronous Communications Interface Adapter 16 | acia 17 | :: (HiddenClockResetEnable dom) 18 | => Signal dom (Maybe (Unsigned 8)) 19 | -> Signal dom Bool 20 | -> Signal dom (Maybe (PortCommand (Unsigned 1) (Unsigned 8))) 21 | -> (Signal dom (Unsigned 8), Signal dom (Maybe (Unsigned 8))) 22 | acia inByte outReady cmd = mealyStateB step Nothing (inByte, outReady, cmd) 23 | where 24 | step (inByte, outReady, cmd) = fmap (second getFirst) . runWriterT $ do 25 | traverse (put . Just) inByte 26 | fmap fromJustX $ for cmd $ \case 27 | ReadPort 0x0 -> do 28 | inReady <- isJust <$> get 29 | return $ bitCoerce $ 30 | False :> -- TODO: IRQ 31 | False :> -- TODO: parity error 32 | False :> -- TODO: receiver overrun 33 | False :> -- TODO: framing error 34 | False :> -- TODO: CTS 35 | False :> -- TODO: DCD 36 | outReady :> 37 | inReady :> 38 | Nil 39 | WritePort 0x0 x -> do 40 | return 0x00 41 | ReadPort 0x1 -> do 42 | queued <- get <* put Nothing 43 | return $ fromMaybe 0x00 queued 44 | WritePort 0x1 x -> do 45 | tell $ pure x 46 | return 0x00 47 | -------------------------------------------------------------------------------- /src/Hardware/TinyBASIC/Intel8080.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE RecordWildCards, NumericUnderscores #-} 2 | module Hardware.TinyBASIC.Intel8080 (logicBoard) where 3 | 4 | import Clash.Prelude hiding (rom) 5 | 6 | import Hardware.Intel8080 7 | import Hardware.Intel8080.CPU 8 | import Hardware.ACIA 9 | 10 | import RetroClash.Utils 11 | import RetroClash.CPU 12 | import RetroClash.Port 13 | import RetroClash.Memory 14 | import Data.Maybe (fromMaybe) 15 | 16 | logicBoard 17 | :: (HiddenClockResetEnable dom) 18 | => Signal dom (Maybe (Unsigned 8)) -> Signal dom Bool -> Signal dom (Maybe (Unsigned 8)) 19 | logicBoard inByte outReady = outByte 20 | where 21 | CPUOut{..} = intel8080 CPUIn{..} 22 | 23 | interruptRequest = pure False 24 | 25 | dataIn = Just <$> (0 |>. dataIn') 26 | (dataIn', outByte) = $(memoryMap [|Right 0 |>. _addrOut|] [|_dataOut|] $ do 27 | rom <- romFromFile (SNat @0x0800) [|"_build/intel8080/image.bin"|] 28 | ram <- ram0 (SNat @0x1800) 29 | (acia, outByte) <- port @(Unsigned 1) [|acia inByte outReady|] 30 | 31 | matchLeft @(Unsigned 8) $ do 32 | from 0x10 $ connect acia 33 | matchRight @(Unsigned 16) $ do 34 | from 0x0000 $ connect rom 35 | from 0x0800 $ connect ram 36 | 37 | return outByte) 38 | -------------------------------------------------------------------------------- /src/Hardware/TinyBASIC/Keyboard.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE ApplicativeDo #-} 2 | module Hardware.TinyBASIC.Keyboard where 3 | 4 | import Clash.Prelude 5 | 6 | import RetroClash.Utils 7 | import RetroClash.Clock 8 | import RetroClash.PS2 9 | import RetroClash.PS2.ASCII 10 | 11 | keyboard 12 | :: (HiddenClockResetEnable dom, KnownNat (ClockDivider dom (Microseconds 1))) 13 | => PS2 dom -> Signal dom (Maybe (Unsigned 8)) 14 | keyboard ps2 = fmap extend <$> (toChar <$> shift <*> ctrl <*> sc) 15 | where 16 | sc = parseScanCode . decodePS2 . samplePS2 $ ps2 17 | 18 | shift = keyState 0x012 sc .||. keyState 0x059 sc 19 | ctrl = keyState 0x014 sc .||. keyState 0x114 sc 20 | 21 | toChar shift ctrl sc = case asciiMap =<< keyPress =<< sc of 22 | Just 0x63 | ctrl -> Just 0x03 -- Ctrl-C 23 | Just c | not ctrl -> Just $ shiftASCII shift c 24 | _ -> Nothing 25 | 26 | shiftASCII :: Bool -> Unsigned 7 -> Unsigned 7 27 | shiftASCII shift c 28 | | c > 0x40 = if shift then c `setBit` 5 else c `clearBit` 5 29 | | c > 0x20 = if shift then c `clearBit` 4 else c 30 | | otherwise = c 31 | -------------------------------------------------------------------------------- /src/Hardware/TinyBASIC/Sim.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE LambdaCase #-} 2 | module Hardware.TinyBASIC.Sim where 3 | 4 | import Clash.Prelude hiding (lift) 5 | 6 | import Control.Monad 7 | import Control.Monad.Trans 8 | import Control.Monad.Trans.Maybe 9 | 10 | import Data.Char (ord, chr, isPrint) 11 | import System.Terminal 12 | 13 | sampleEvent 14 | :: (MonadInput m) 15 | => m (Maybe (Either Interrupt Event)) 16 | sampleEvent = awaitWith $ \int ev -> msum 17 | [ Just . Left <$> int 18 | , Just . Right <$> ev 19 | , return Nothing 20 | ] 21 | 22 | sampleKey 23 | :: (MonadInput (TerminalT t m), MonadPlus m) 24 | => TerminalT t m (Maybe (Unsigned 8)) 25 | sampleKey = sampleEvent >>= \case 26 | Just (Left int) -> return $ Just 0x03 27 | Just (Right (KeyEvent key mods)) 28 | | CharKey c <- key, mods == mempty -> return $ Just . fromIntegral . ord $ c 29 | | CharKey 'D' <- key, mods .&. ctrlKey /= mempty -> lift mzero 30 | | EnterKey <- key -> return $ Just . fromIntegral . ord $ '\r' 31 | _ -> return Nothing 32 | 33 | printByte :: (MonadPrinter m) => Unsigned 8 -> m () 34 | printByte val = case chr . fromIntegral $ val of 35 | '\r' -> putStringLn "" 36 | c | isPrint c -> putChar c >> flush 37 | _ -> return () 38 | -------------------------------------------------------------------------------- /src/Hardware/TinyBASIC/Video.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE NumericUnderscores, RecordWildCards #-} 2 | {-# LANGUAGE ViewPatterns, LambdaCase #-} 3 | module Hardware.TinyBASIC.Video where 4 | 5 | import Clash.Prelude 6 | import RetroClash.Utils 7 | import RetroClash.VGA 8 | import RetroClash.Video 9 | import RetroClash.Delayed 10 | import RetroClash.Clock 11 | 12 | import Data.Maybe 13 | import Control.Monad.State 14 | 15 | -- | 25 MHz clock, needed for the VGA mode we use. 16 | createDomain vSystem{vName="Dom25", vPeriod = hzToPeriod 25_175_000} 17 | 18 | -- TODO: make these parameters 19 | type TextWidth = 72 20 | type TextHeight = 50 21 | type TextSize = TextWidth * TextHeight 22 | type TextAddr = Index TextSize 23 | type TextCoord = (Index TextWidth, Index TextHeight) 24 | 25 | type FontWidth = 8 26 | type FontHeight = 8 27 | 28 | data EditorState 29 | = Ready (Index TextHeight) TextAddr (Index TextWidth) 30 | | Clear (Index TextHeight) TextAddr (Index TextWidth) 31 | deriving (Generic, NFDataX) 32 | 33 | screenEditor 34 | :: (HiddenClockResetEnable dom) 35 | => Signal dom (Maybe (Unsigned 8)) 36 | -> ( Signal dom (Maybe (TextAddr, Unsigned 8)) 37 | , Signal dom TextCoord 38 | , Signal dom Bool 39 | ) 40 | screenEditor = mealyStateB step (Ready 0 0 0) 41 | where 42 | base `offsetBy` x = base + fromIntegral x 43 | stride = snatToNum (SNat @TextWidth) 44 | nextLine = satAdd SatWrap stride 45 | 46 | step chr = do 47 | write <- putChar chr 48 | (cursor, ready) <- gets $ \case 49 | Clear y base x -> ((x, y), False) 50 | Ready y base x -> ((x, y), True) 51 | return (write, cursor, ready) 52 | 53 | putChar chr = get >>= \case 54 | Clear y base x -> do 55 | put $ maybe (Ready y base 0) (Clear y base) $ succIdx x 56 | return $ Just (base `offsetBy` x, 0x20) 57 | Ready y base x -> case chr of 58 | Nothing -> do 59 | return Nothing 60 | Just 0x0a -> do 61 | put $ Clear (nextIdx y) (nextLine base) 0 62 | return Nothing 63 | Just chr -> do 64 | put $ maybe (Clear (nextIdx y) (nextLine base) 0) (Ready y base) $ succIdx x 65 | return $ Just (base `offsetBy` x, chr) 66 | 67 | video 68 | :: (HiddenClockResetEnable Dom25) 69 | => Signal Dom25 TextCoord 70 | -> Signal Dom25 (Maybe (TextAddr, Unsigned 8)) 71 | -> ( Signal Dom25 Bool 72 | , VGAOut Dom25 8 8 8 73 | ) 74 | video (fromSignal -> cursor) (fromSignal -> w) = (frameEnd, delayVGA vgaSync rgb) 75 | where 76 | VGADriver{..} = vgaDriver vga640x480at60 77 | frameEnd = isFalling False (isJust <$> vgaY) 78 | 79 | (charX, glyphX) = scale @TextWidth (SNat @FontWidth) . center $ vgaX 80 | (charY, glyphY) = scale @TextHeight (SNat @FontHeight) . center $ vgaY 81 | charXY = fromSignal $ liftA2 (,) <$> charX <*> charY 82 | visible = isJust <$> charXY 83 | 84 | (newLine, lineAddr) = addressBy (snatToNum (SNat @TextWidth)) charY 85 | (newChar, charOffset) = addressBy 1 charX 86 | 87 | charAddr = lineAddr + charOffset 88 | charWrite = delayI Nothing w 89 | charLoad = delayedRam (blockRam1 ClearOnReset (SNat @TextSize) 0) charAddr charWrite 90 | 91 | glyphLoad = enable (delayI False newChar) $ fontRom charLoad (fromMaybe 0 <$> delayI Nothing (fromSignal glyphY)) 92 | newCol = delayI False $ fromSignal $ changed Nothing glyphX 93 | pixel = enable (delayI False visible) $ liftD2 shifterL glyphLoad newCol 94 | 95 | cursorOn = fromSignal $ oscillateWhen False $ riseEveryWhen (SNat @30) frameEnd 96 | isCursor = cursorOn .&&. charXY .==. (Just <$> cursor) 97 | 98 | pixel' = mux (delayI False isCursor) (fmap complement <$> pixel) pixel 99 | rgb = maybe frame palette <$> pixel' 100 | 101 | frame = (0x30, 0x30, 0x30) 102 | palette 0 = (0x00, 0x00, 0x00) 103 | palette 1 = (0x33, 0xff, 0x33) 104 | 105 | fontRom 106 | :: (HiddenClockResetEnable dom) 107 | => DSignal dom n (Unsigned 8) 108 | -> DSignal dom n (Index FontHeight) 109 | -> DSignal dom (n + 1) (Unsigned FontWidth) 110 | fontRom char row = delayedRom (fmap unpack . romFilePow2 "font.bin") $ 111 | toAddr <$> char <*> row 112 | where 113 | toAddr :: Unsigned 8 -> Index 8 -> Unsigned (8 + CLog 2 FontHeight) 114 | toAddr char row = bitCoerce (char, row) 115 | 116 | addressBy 117 | :: (HiddenClockResetEnable dom, NFDataX coord, NFDataX addr, Num coord, Eq coord, Num addr) 118 | => addr 119 | -> Signal dom (Maybe coord) 120 | -> (DSignal dom 0 Bool, DSignal dom 1 addr) 121 | addressBy stride coord = (new, addr) 122 | where 123 | start = fromSignal $ coord .== Just 0 124 | new = fromSignal $ changed Nothing coord 125 | addr = delayedRegister 0 $ \addr -> 126 | mux (delayI False start) 0 $ 127 | mux new (addr + pure stride) $ 128 | addr 129 | -------------------------------------------------------------------------------- /src/intel8080/model.hs: -------------------------------------------------------------------------------- 1 | import Clash.Prelude hiding (lift) 2 | 3 | import Hardware.Intel8080 4 | import Hardware.Intel8080.Model 5 | import Hardware.TinyBASIC.Sim 6 | 7 | import System.Terminal 8 | import Control.Monad.State 9 | import Control.Monad.Trans.Maybe 10 | import Data.Maybe 11 | import Data.Array.IO 12 | import qualified Data.ByteString as BS 13 | 14 | import Paths_tinybasic 15 | 16 | main :: IO () 17 | main = do 18 | (arr :: IOArray Addr Value) <- newArray (minBound, maxBound) 0x00 19 | 20 | romFile <- getDataFileName "image/intel8080/tinybasic-2.0.bin" 21 | bs <- fmap fromIntegral . BS.unpack <$> BS.readFile romFile 22 | zipWithM_ (writeArray arr) [0x0000..] bs 23 | 24 | let checkInput = do 25 | queued <- get 26 | when (isNothing queued) $ lift sampleKey >>= put 27 | gets isJust 28 | getInput = get <* put Nothing 29 | 30 | let getStatus = do 31 | inputReady <- checkInput 32 | let val | inputReady = 0x03 33 | | otherwise = 0x02 34 | return val 35 | putStatus val = return () 36 | 37 | getData = fromMaybe 0x00 <$> getInput 38 | putData val = lift $ printByte val 39 | 40 | let inPort port 41 | | port == statusPort = getStatus 42 | | port == dataPort = getData 43 | | otherwise = return 0x00 44 | 45 | outPort port x 46 | | port == statusPort = putStatus x >> return 0x00 47 | | port == dataPort = putData x >> return 0x00 48 | | otherwise = return 0x00 49 | 50 | runMaybeT $ withTerminal $ runTerminalT $ do 51 | let w = World 52 | { readMem = liftIO . readArray arr 53 | , writeMem = \addr x -> liftIO $ writeArray arr addr x 54 | , inPort = inPort 55 | , outPort = outPort 56 | } 57 | s = mkState 0x0000 58 | execStateT (runSoftCPU w s) Nothing 59 | 60 | return () 61 | where 62 | statusPort = 0x10 63 | dataPort = 0x11 64 | -------------------------------------------------------------------------------- /src/intel8080/serial-board.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE RecordWildCards, NumericUnderscores #-} 2 | {-# LANGUAGE CPP #-} 3 | 4 | import Clash.Prelude hiding (rom) 5 | import Clash.Annotations.TH 6 | 7 | import Hardware.TinyBASIC.Intel8080 8 | 9 | import RetroClash.Utils 10 | import RetroClash.Clock 11 | import RetroClash.SerialRx 12 | import RetroClash.SerialTx 13 | 14 | createDomain vSystem{vName="Native", vPeriod = hzToPeriod __NATIVE_CLOCK__} 15 | 16 | topEntity 17 | :: "CLK" ::: Clock Native 18 | -> "RESET" ::: Reset Native 19 | -> "RX" ::: Signal Native Bit 20 | -> "TX" ::: Signal Native Bit 21 | topEntity = withEnableGen board 22 | where 23 | board rx = tx 24 | where 25 | outByte = logicBoard inByte outReady 26 | 27 | inByte = fmap unpack <$> serialRx (SNat @9600) rx 28 | (tx, outReady) = serialTx (SNat @9600) (fmap pack <$> outByte) 29 | 30 | makeTopEntity 'topEntity 31 | -------------------------------------------------------------------------------- /src/intel8080/sim.hs: -------------------------------------------------------------------------------- 1 | import Clash.Prelude 2 | 3 | import RetroClash.Sim.IO 4 | import Hardware.TinyBASIC.Sim 5 | import Hardware.TinyBASIC.Intel8080 6 | 7 | import Control.Monad 8 | import Control.Monad.Trans 9 | import Control.Monad.Trans.Maybe 10 | import Data.Foldable (traverse_) 11 | import System.Terminal 12 | 13 | main :: IO () 14 | main = do 15 | sim <- simulateIO_ @System (uncurry logicBoard . unbundle) (Nothing, True) 16 | 17 | runMaybeT $ withTerminal $ runTerminalT $ forever $ sim $ \outByte -> do 18 | traverse_ printByte outByte 19 | inByte <- sampleKey 20 | return (inByte, True) 21 | return () 22 | -------------------------------------------------------------------------------- /src/intel8080/video-board.hs: -------------------------------------------------------------------------------- 1 | {-# LANGUAGE RecordWildCards, NumericUnderscores, LambdaCase #-} 2 | import Clash.Prelude 3 | import Clash.Annotations.TH 4 | 5 | import Hardware.TinyBASIC.Intel8080 6 | import Hardware.TinyBASIC.Keyboard 7 | import Hardware.TinyBASIC.Video 8 | 9 | import RetroClash.Utils 10 | import RetroClash.VGA 11 | import RetroClash.PS2 12 | 13 | topEntity 14 | :: "CLK_25MHZ" ::: Clock Dom25 15 | -> "RESET" ::: Reset Dom25 16 | -> "PS2" ::: PS2 Dom25 17 | -> "VGA" ::: VGAOut Dom25 8 8 8 18 | topEntity = withEnableGen board 19 | where 20 | board ps2 = vga 21 | where 22 | (frameEnd, vga) = video cursor vidWrite 23 | (vidWrite, cursor, vidReady) = screenEditor outByte 24 | 25 | outByte = logicBoard inByte vidReady 26 | inByte = keyboard ps2 27 | 28 | makeTopEntity 'topEntity 29 | -------------------------------------------------------------------------------- /stack.yaml: -------------------------------------------------------------------------------- 1 | resolver: clash-1.4.6.yaml 2 | 3 | extra-deps: 4 | - barbies-th-0.1.8 5 | - monoidal-containers-0.6.0.1 6 | 7 | - terminal-0.2.0.0 8 | 9 | - retroclash-lib-0.1.0 10 | - retroclash-sim-0.1.0 11 | - clash-shake-0.1.1 12 | 13 | packages: 14 | - clash-intel8080 15 | - . 16 | -------------------------------------------------------------------------------- /stack.yaml.lock: -------------------------------------------------------------------------------- 1 | # This file was autogenerated by Stack. 2 | # You should not edit this file by hand. 3 | # For more information, please see the documentation at: 4 | # https://docs.haskellstack.org/en/stable/lock_files 5 | 6 | packages: 7 | - completed: 8 | hackage: clash-prelude-1.4.6@sha256:fdc6a41cd9acd10f1fe5fc585d101590003a78453ed2f9a503c0e415d6165e73,15932 9 | pantry-tree: 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retroclash-sim-0.1.0@sha256:f4a83dd0c98e7f2bd41bfff748112d3b180f4bf7d3e66bcced54a6fe478e43ba,2408 58 | pantry-tree: 59 | size: 377 60 | sha256: 4addc5a473e11d2a79b3783d88743d981610492ac1bddd79ed25bd6f9788cc38 61 | original: 62 | hackage: retroclash-sim-0.1.0 63 | - completed: 64 | hackage: clash-shake-0.1.1@sha256:6a18bae71e08a1463d5851a09662dc294b11ecf31d7be504bb3037257841600e,1577 65 | pantry-tree: 66 | size: 570 67 | sha256: 2447a75d9749ba49358ae5691009737c584de1d1eb20f831d62110eaa39a5ede 68 | original: 69 | hackage: clash-shake-0.1.1 70 | snapshots: 71 | - completed: 72 | size: 586069 73 | url: https://raw.githubusercontent.com/commercialhaskell/stackage-snapshots/master/lts/18/14.yaml 74 | sha256: 87842ecbaa8ca9cee59a7e6be52369dbed82ed075cb4e0d152614a627e8fd488 75 | original: lts-18.14 76 | -------------------------------------------------------------------------------- /target/nexys-a7-50t/serial/src-hdl/TinyBASICSerial.v: -------------------------------------------------------------------------------- 1 | module TinyBASICSerial( 2 | input CLK100MHZ, 3 | input UART_TXD_IN, 4 | output UART_RXD_OUT 5 | ); 6 | 7 | topEntity u_topEntity 8 | (.CLK(CLK100MHZ), 9 | .RESET(1'b0), 10 | .RX(UART_TXD_IN), 11 | .TX(UART_RXD_OUT) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /target/nexys-a7-50t/serial/src-hdl/nexys-a7-50t.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Nexys A7-50T 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 8 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; 9 | 10 | 11 | ##Switches 12 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 13 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 14 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 15 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 16 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 17 | set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] 18 | set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] 19 | set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] 20 | set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] 21 | set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] 22 | set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] 23 | set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] 24 | set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] 25 | set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] 26 | set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] 27 | set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] 28 | 29 | ## LEDs 30 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] 31 | set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] 32 | set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] 33 | set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] 34 | set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] 35 | set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] 36 | set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] 37 | set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] 38 | set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] 39 | set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] 40 | set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] 41 | set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] 42 | set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] 43 | set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] 44 | set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] 45 | set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] 46 | 47 | ## RGB LEDs 48 | set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b 49 | set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g 50 | set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r 51 | set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b 52 | set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g 53 | set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r 54 | 55 | ##7 segment display 56 | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { SEG[6] }]; #IO_L24N_T3_A00_D16_14 Sch=ca 57 | set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { SEG[5] }]; #IO_25_14 Sch=cb 58 | set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { SEG[4] }]; #IO_25_15 Sch=cc 59 | set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { SEG[3] }]; #IO_L17P_T2_A26_15 Sch=cd 60 | set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SEG[2] }]; #IO_L13P_T2_MRCC_14 Sch=ce 61 | set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { SEG[1] }]; #IO_L19P_T3_A10_D26_14 Sch=cf 62 | set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { SEG[0] }]; #IO_L4P_T0_D04_14 Sch=cg 63 | 64 | set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp 65 | 66 | set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] 67 | set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] 68 | set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] 69 | set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] 70 | set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] 71 | set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] 72 | set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] 73 | set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] 74 | 75 | ##Buttons 76 | set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn 77 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc 78 | set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu 79 | set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl 80 | set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr 81 | set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd 82 | 83 | 84 | ##Pmod Headers 85 | ##Pmod Header JA 86 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] 87 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 88 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 89 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] 90 | set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] 91 | set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] 92 | set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] 93 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] 94 | 95 | ##Pmod Header JB 96 | set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] 97 | set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] 98 | set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] 99 | set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] 100 | set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] 101 | set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] 102 | set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] 103 | set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] 104 | 105 | ##Pmod Header JC 106 | set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] 107 | set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] 108 | set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] 109 | set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] 110 | set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] 111 | set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] 112 | set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] 113 | set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] 114 | 115 | ##Pmod Header JD 116 | set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] 117 | set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] 118 | set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] 119 | set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] 120 | set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] 121 | set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] 122 | set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] 123 | set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] 124 | 125 | ##Pmod Header JXADC 126 | set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] 127 | set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] 128 | set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] 129 | set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] 130 | set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] 131 | set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] 132 | set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] 133 | set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] 134 | 135 | ##VGA Connector 136 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 137 | set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 138 | set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 139 | set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] 140 | set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 141 | set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 142 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 143 | set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] 144 | set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 145 | set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 146 | set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] 147 | set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] 148 | set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs 149 | set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 150 | 151 | ##Micro SD Connector 152 | set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset 153 | set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd 154 | set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck 155 | set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd 156 | set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] 157 | set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] 158 | set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] 159 | set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] 160 | 161 | ##Accelerometer 162 | set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso 163 | set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi 164 | set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk 165 | set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn 166 | set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] 167 | set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] 168 | 169 | ##Temperature Sensor 170 | set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl 171 | set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda 172 | set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int 173 | set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct 174 | 175 | ##Omnidirectional Microphone 176 | set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk 177 | set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data 178 | set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel 179 | 180 | ##PWM Audio Amplifier 181 | set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm 182 | set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd 183 | 184 | ##USB-RS232 Interface 185 | set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in 186 | set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out 187 | set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts 188 | set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts 189 | 190 | ##USB HID (PS/2) 191 | set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk 192 | set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data 193 | 194 | ##SMSC Ethernet PHY 195 | set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc 196 | set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio 197 | set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn 198 | set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv 199 | set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr 200 | set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] 201 | set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] 202 | set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen 203 | set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] 204 | set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] 205 | set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk 206 | set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn 207 | 208 | ##Quad SPI Flash 209 | set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 210 | set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 211 | set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 212 | set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 213 | set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn 214 | -------------------------------------------------------------------------------- /target/nexys-a7-50t/video/ip/ClockWiz25.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | ClockWiz25 10 | 11 | 12 | false 13 | 100000000 14 | false 15 | 100000000 16 | false 17 | 100000000 18 | false 19 | 100000000 20 | 21 | 22 | 23 | 100000000 24 | 0 25 | 0.000 26 | 27 | 28 | 29 | 100000000 30 | 0 31 | 0.000 32 | 1 33 | LEVEL_HIGH 34 | 35 | 36 | 37 | 100000000 38 | 0 39 | 0.000 40 | 0 41 | 0 42 | 43 | 100000000 44 | 0 45 | 0.000 46 | 1 47 | 0 48 | 0 49 | 0 50 | 51 | 1 52 | 100000000 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 0 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 1 65 | 1 66 | 1 67 | 1 68 | 1 69 | 0.000 70 | AXI4LITE 71 | READ_WRITE 72 | 0 73 | 0 74 | 0 75 | 0 76 | 0 77 | 0 78 | MMCM 79 | cddcdone 80 | cddcreq 81 | 0000 82 | 0000 83 | clkfb_in_n 84 | clkfb_in 85 | clkfb_in_p 86 | SINGLE 87 | clkfb_out_n 88 | clkfb_out 89 | clkfb_out_p 90 | clkfb_stopped 91 | 100.0 92 | 100.0 93 | 0000 94 | 0000 95 | 25.173 96 | 0000 97 | 0000 98 | 100.000 99 | BUFG 100 | 50.0 101 | false 102 | 25.173 103 | 0.000 104 | 50.000 105 | 25.175 106 | 0.000 107 | 1 108 | 0000 109 | 0000 110 | 100.000 111 | BUFG 112 | 50.000 113 | false 114 | 100.000 115 | 0.000 116 | 50.000 117 | 100.000 118 | 0.000 119 | 1 120 | 0 121 | 0000 122 | 0000 123 | 100.000 124 | BUFG 125 | 50.000 126 | false 127 | 100.000 128 | 0.000 129 | 50.000 130 | 100.000 131 | 0.000 132 | 1 133 | 0 134 | 0000 135 | 0000 136 | 100.000 137 | BUFG 138 | 50.000 139 | false 140 | 100.000 141 | 0.000 142 | 50.000 143 | 100.000 144 | 0.000 145 | 1 146 | 0 147 | 0000 148 | 0000 149 | 100.000 150 | BUFG 151 | 50.000 152 | false 153 | 100.000 154 | 0.000 155 | 50.000 156 | 100.000 157 | 0.000 158 | 1 159 | 0 160 | 0000 161 | 0000 162 | 100.000 163 | BUFG 164 | 50.000 165 | false 166 | 100.000 167 | 0.000 168 | 50.000 169 | 100.000 170 | 0.000 171 | 1 172 | 0 173 | BUFG 174 | 50.000 175 | false 176 | 100.000 177 | 0.000 178 | 50.000 179 | 100.000 180 | 0.000 181 | 1 182 | 0 183 | VCO 184 | clk_in_sel 185 | CLKOUT_25MHZ 186 | clk_out2 187 | clk_out3 188 | clk_out4 189 | clk_out5 190 | clk_out6 191 | clk_out7 192 | CLK_VALID 193 | NA 194 | daddr 195 | dclk 196 | den 197 | din 198 | 0000 199 | 1 200 | 0.25175000000000003 201 | 0.25175000000000003 202 | 0.25175000000000003 203 | 0.25175000000000003 204 | 0.25175000000000003 205 | 0.25175000000000003 206 | dout 207 | drdy 208 | dwe 209 | 0 210 | 0 211 | 0 212 | 0 213 | 0 214 | 0 215 | 0 216 | 0 217 | FDBK_AUTO 218 | 0000 219 | 0000 220 | 0 221 | Input Clock Freq (MHz) Input Jitter (UI) 222 | __primary_________100.000____________0.010 223 | no_secondary_input_clock 224 | input_clk_stopped 225 | 0 226 | Units_MHz 227 | No_Jitter 228 | LOCKED 229 | 0000 230 | 0000 231 | 0000 232 | false 233 | false 234 | false 235 | false 236 | false 237 | false 238 | false 239 | false 240 | OPTIMIZED 241 | 36.375 242 | 0.000 243 | FALSE 244 | 10.000 245 | 10.000 246 | 36.125 247 | 0.500 248 | 0.000 249 | FALSE 250 | 1 251 | 0.500 252 | 0.000 253 | FALSE 254 | 1 255 | 0.500 256 | 0.000 257 | FALSE 258 | 1 259 | 0.500 260 | 0.000 261 | FALSE 262 | FALSE 263 | 1 264 | 0.500 265 | 0.000 266 | FALSE 267 | 1 268 | 0.500 269 | 0.000 270 | FALSE 271 | 1 272 | 0.500 273 | 0.000 274 | FALSE 275 | FALSE 276 | ZHOLD 277 | 4 278 | None 279 | 0.010 280 | 0.010 281 | FALSE 282 | 1 283 | Output Output Phase Duty Cycle Pk-to-Pk Phase 284 | Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 285 | CLKOUT_25MHZ____25.173______0.000______50.0______319.783____246.739 286 | no_CLK_OUT2_output 287 | no_CLK_OUT3_output 288 | no_CLK_OUT4_output 289 | no_CLK_OUT5_output 290 | no_CLK_OUT6_output 291 | no_CLK_OUT7_output 292 | 0 293 | 0 294 | WAVEFORM 295 | UNKNOWN 296 | false 297 | false 298 | false 299 | false 300 | false 301 | OPTIMIZED 302 | 1 303 | 0.000 304 | 1.000 305 | 1 306 | 0.500 307 | 0.000 308 | 1 309 | 0.500 310 | 0.000 311 | 1 312 | 0.500 313 | 0.000 314 | 1 315 | 0.500 316 | 0.000 317 | 1 318 | 0.500 319 | 0.000 320 | 1 321 | 0.500 322 | 0.000 323 | CLKFBOUT 324 | SYSTEM_SYNCHRONOUS 325 | 1 326 | No notes 327 | 0.010 328 | power_down 329 | 0000 330 | 1 331 | CLKIN_100MHZ 332 | MMCM 333 | AUTO 334 | 100.000 335 | 0.010 336 | 10.000 337 | Single_ended_clock_capable_pin 338 | psclk 339 | psdone 340 | psen 341 | psincdec 342 | 100.0 343 | 0 344 | reset 345 | 100.000 346 | 0.010 347 | 10.000 348 | clk_in2 349 | Single_ended_clock_capable_pin 350 | CENTER_HIGH 351 | 4000 352 | 0.004 353 | STATUS 354 | 11 355 | 32 356 | 100.0 357 | 100.0 358 | 100.0 359 | 100.0 360 | 0 361 | 0 362 | 0 363 | 0 364 | 0 365 | 0 366 | 0 367 | 0 368 | 0 369 | 0 370 | 0 371 | 1 372 | 0 373 | 0 374 | 1 375 | 0 376 | 0 377 | 0 378 | 1 379 | 0 380 | 1 381 | 0 382 | 0 383 | 0 384 | ClockWiz25 385 | MMCM 386 | false 387 | empty 388 | cddcdone 389 | cddcreq 390 | clkfb_in_n 391 | clkfb_in 392 | clkfb_in_p 393 | SINGLE 394 | clkfb_out_n 395 | clkfb_out 396 | clkfb_out_p 397 | clkfb_stopped 398 | 100.0 399 | 0.010 400 | 100.0 401 | 0.010 402 | BUFG 403 | 319.783 404 | false 405 | 246.739 406 | 50.000 407 | 25.175 408 | 0.000 409 | 1 410 | true 411 | BUFG 412 | 0.0 413 | false 414 | 0.0 415 | 50.000 416 | 100.000 417 | 0.000 418 | 1 419 | false 420 | BUFG 421 | 0.0 422 | false 423 | 0.0 424 | 50.000 425 | 100.000 426 | 0.000 427 | 1 428 | false 429 | BUFG 430 | 0.0 431 | false 432 | 0.0 433 | 50.000 434 | 100.000 435 | 0.000 436 | 1 437 | false 438 | BUFG 439 | 0.0 440 | false 441 | 0.0 442 | 50.000 443 | 100.000 444 | 0.000 445 | 1 446 | false 447 | BUFG 448 | 0.0 449 | false 450 | 0.0 451 | 50.000 452 | 100.000 453 | 0.000 454 | 1 455 | false 456 | BUFG 457 | 0.0 458 | false 459 | 0.0 460 | 50.000 461 | 100.000 462 | 0.000 463 | 1 464 | false 465 | 600.000 466 | Custom 467 | Custom 468 | clk_in_sel 469 | CLKOUT_25MHZ 470 | false 471 | clk_out2 472 | false 473 | clk_out3 474 | false 475 | clk_out4 476 | false 477 | clk_out5 478 | false 479 | clk_out6 480 | false 481 | clk_out7 482 | false 483 | CLK_VALID 484 | auto 485 | ClockWiz25 486 | daddr 487 | dclk 488 | den 489 | Custom 490 | Custom 491 | din 492 | dout 493 | drdy 494 | dwe 495 | false 496 | false 497 | false 498 | false 499 | false 500 | false 501 | false 502 | false 503 | false 504 | FDBK_AUTO 505 | input_clk_stopped 506 | frequency 507 | Enable_AXI 508 | Units_MHz 509 | Units_UI 510 | UI 511 | No_Jitter 512 | LOCKED 513 | OPTIMIZED 514 | 36.375 515 | 0.000 516 | false 517 | 10.000 518 | 10.000 519 | 36.125 520 | 0.500 521 | 0.000 522 | false 523 | 1 524 | 0.500 525 | 0.000 526 | false 527 | 1 528 | 0.500 529 | 0.000 530 | false 531 | 1 532 | 0.500 533 | 0.000 534 | false 535 | false 536 | 1 537 | 0.500 538 | 0.000 539 | false 540 | 1 541 | 0.500 542 | 0.000 543 | false 544 | 1 545 | 0.500 546 | 0.000 547 | false 548 | false 549 | ZHOLD 550 | 4 551 | None 552 | 0.010 553 | 0.010 554 | false 555 | 1 556 | false 557 | false 558 | WAVEFORM 559 | false 560 | UNKNOWN 561 | OPTIMIZED 562 | 4 563 | 0.000 564 | 10.000 565 | 1 566 | 0.500 567 | 0.000 568 | 1 569 | 0.500 570 | 0.000 571 | 1 572 | 0.500 573 | 0.000 574 | 1 575 | 0.500 576 | 0.000 577 | 1 578 | 0.500 579 | 0.000 580 | 1 581 | 0.500 582 | 0.000 583 | CLKFBOUT 584 | SYSTEM_SYNCHRONOUS 585 | 1 586 | None 587 | 0.010 588 | power_down 589 | 1 590 | CLKIN_100MHZ 591 | MMCM 592 | mmcm_adv 593 | 100.000 594 | 0.010 595 | 10.000 596 | Single_ended_clock_capable_pin 597 | psclk 598 | psdone 599 | psen 600 | psincdec 601 | 100.0 602 | REL_PRIMARY 603 | Custom 604 | reset 605 | ACTIVE_HIGH 606 | 100.000 607 | 0.010 608 | 10.000 609 | clk_in2 610 | Single_ended_clock_capable_pin 611 | CENTER_HIGH 612 | 250 613 | 0.004 614 | STATUS 615 | empty 616 | 100.0 617 | 100.0 618 | 100.0 619 | 100.0 620 | false 621 | false 622 | false 623 | false 624 | false 625 | false 626 | false 627 | true 628 | false 629 | false 630 | true 631 | false 632 | false 633 | false 634 | true 635 | false 636 | true 637 | false 638 | false 639 | false 640 | artix7 641 | digilentinc.com:nexys-a7-50t:part0:1.0 642 | 643 | xc7a50ti 644 | csg324 645 | VERILOG 646 | 647 | MIXED 648 | -1L 649 | 650 | I 651 | TRUE 652 | TRUE 653 | IP_Flow 654 | 3 655 | TRUE 656 | . 657 | 658 | . 659 | 2019.1 660 | OUT_OF_CONTEXT 661 | 662 | 663 | 664 | 665 | 666 | 667 | 668 | 669 | 670 | 671 | 672 | 673 | 674 | 675 | 676 | 677 | 678 | 679 | 680 | 681 | 682 | 683 | 684 | 685 | 686 | 687 | 688 | 689 | 690 | 691 | 692 | 693 | 694 | 695 | 696 | 697 | 698 | -------------------------------------------------------------------------------- /target/nexys-a7-50t/video/src-hdl/TinyBASICVideo.v: -------------------------------------------------------------------------------- 1 | module TinyBASICVideo( 2 | input CLK100MHZ, 3 | input PS2_CLK, 4 | input PS2_DATA, 5 | output VGA_HS, 6 | output VGA_VS, 7 | output [3:0] VGA_R, 8 | output [3:0] VGA_G, 9 | output [3:0] VGA_B 10 | ); 11 | 12 | wire CLK_25MHZ; 13 | wire CLK_LOCKED; 14 | wire [7:0] VGA_RED_FULL; 15 | wire [7:0] VGA_GREEN_FULL; 16 | wire [7:0] VGA_BLUE_FULL; 17 | 18 | assign VGA_R = VGA_RED_FULL[7:4]; 19 | assign VGA_G = VGA_GREEN_FULL[7:4]; 20 | assign VGA_B = VGA_BLUE_FULL[7:4]; 21 | 22 | ClockWiz25 u_ClockWiz25 23 | (.CLKIN_100MHZ(CLK100MHZ), 24 | .CLKOUT_25MHZ(CLK_25MHZ), 25 | .LOCKED(CLK_LOCKED), 26 | .reset(1'b0) 27 | ); 28 | 29 | topEntity u_topEntity 30 | (.CLK_25MHZ(CLK_25MHZ), 31 | .RESET(!CLK_LOCKED), 32 | .PS2_CLK(PS2_CLK), 33 | .PS2_DATA(PS2_DATA), 34 | .VGA_HSYNC(VGA_HS), 35 | .VGA_VSYNC(VGA_VS), 36 | .VGA_RED(VGA_RED_FULL), 37 | .VGA_GREEN(VGA_GREEN_FULL), 38 | .VGA_BLUE(VGA_BLUE_FULL) 39 | ); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /target/nexys-a7-50t/video/src-hdl/nexys-a7-50t.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Nexys A7-50T 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 8 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; 9 | 10 | 11 | ##Switches 12 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 13 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 14 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 15 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 16 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 17 | set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] 18 | set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] 19 | set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] 20 | set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] 21 | set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] 22 | set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] 23 | set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] 24 | set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] 25 | set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] 26 | set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] 27 | set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] 28 | 29 | ## LEDs 30 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] 31 | set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] 32 | set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] 33 | set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] 34 | set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] 35 | set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] 36 | set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] 37 | set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] 38 | set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] 39 | set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] 40 | set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] 41 | set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] 42 | set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] 43 | set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] 44 | set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] 45 | set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] 46 | 47 | ## RGB LEDs 48 | set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b 49 | set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g 50 | set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r 51 | set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b 52 | set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g 53 | set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r 54 | 55 | ##7 segment display 56 | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { SEG[6] }]; #IO_L24N_T3_A00_D16_14 Sch=ca 57 | set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { SEG[5] }]; #IO_25_14 Sch=cb 58 | set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { SEG[4] }]; #IO_25_15 Sch=cc 59 | set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { SEG[3] }]; #IO_L17P_T2_A26_15 Sch=cd 60 | set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SEG[2] }]; #IO_L13P_T2_MRCC_14 Sch=ce 61 | set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { SEG[1] }]; #IO_L19P_T3_A10_D26_14 Sch=cf 62 | set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { SEG[0] }]; #IO_L4P_T0_D04_14 Sch=cg 63 | 64 | set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp 65 | 66 | set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] 67 | set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] 68 | set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] 69 | set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] 70 | set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] 71 | set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] 72 | set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] 73 | set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] 74 | 75 | ##Buttons 76 | set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn 77 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc 78 | set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu 79 | set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl 80 | set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr 81 | set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd 82 | 83 | 84 | ##Pmod Headers 85 | ##Pmod Header JA 86 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] 87 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 88 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 89 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] 90 | set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] 91 | set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] 92 | set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] 93 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] 94 | 95 | ##Pmod Header JB 96 | set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] 97 | set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] 98 | set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] 99 | set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] 100 | set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] 101 | set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] 102 | set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] 103 | set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] 104 | 105 | ##Pmod Header JC 106 | set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] 107 | set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] 108 | set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] 109 | set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] 110 | set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] 111 | set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] 112 | set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] 113 | set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] 114 | 115 | ##Pmod Header JD 116 | set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] 117 | set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] 118 | set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] 119 | set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] 120 | set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] 121 | set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] 122 | set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] 123 | set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] 124 | 125 | ##Pmod Header JXADC 126 | set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] 127 | set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] 128 | set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] 129 | set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] 130 | set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] 131 | set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] 132 | set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] 133 | set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] 134 | 135 | ##VGA Connector 136 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 137 | set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 138 | set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 139 | set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] 140 | set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 141 | set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 142 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 143 | set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] 144 | set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 145 | set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 146 | set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] 147 | set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] 148 | set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs 149 | set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 150 | 151 | ##Micro SD Connector 152 | set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset 153 | set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd 154 | set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck 155 | set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd 156 | set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] 157 | set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] 158 | set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] 159 | set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] 160 | 161 | ##Accelerometer 162 | set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso 163 | set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi 164 | set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk 165 | set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn 166 | set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] 167 | set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] 168 | 169 | ##Temperature Sensor 170 | set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl 171 | set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda 172 | set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int 173 | set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct 174 | 175 | ##Omnidirectional Microphone 176 | set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk 177 | set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data 178 | set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel 179 | 180 | ##PWM Audio Amplifier 181 | set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm 182 | set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd 183 | 184 | ##USB-RS232 Interface 185 | set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in 186 | set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out 187 | set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts 188 | set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts 189 | 190 | ##USB HID (PS/2) 191 | set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk 192 | set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data 193 | 194 | ##SMSC Ethernet PHY 195 | set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc 196 | set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio 197 | set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn 198 | set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv 199 | set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr 200 | set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] 201 | set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] 202 | set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen 203 | set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] 204 | set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] 205 | set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk 206 | set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn 207 | 208 | ##Quad SPI Flash 209 | set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 210 | set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 211 | set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 212 | set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 213 | set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn 214 | -------------------------------------------------------------------------------- /target/papilio-one/serial/src-hdl/PapilioOne-Base.ucf: -------------------------------------------------------------------------------- 1 | CONFIG PROHIBIT=P99; 2 | CONFIG PROHIBIT=P43; 3 | CONFIG PROHIBIT=P42; 4 | CONFIG PROHIBIT=P39; 5 | CONFIG PROHIBIT=P49; 6 | CONFIG PROHIBIT=P48; 7 | CONFIG PROHIBIT=P47; 8 | CONFIG PART="XC3S500E-VQ100-5"; 9 | 10 | NET "CLK_32MHZ" LOC = "P89" | IOSTANDARD = LVCMOS25 | TNM_NET = CLK_32; 11 | TIMESPEC TS_CLK_32MHZ = PERIOD "CLK_32" 32 MHz HIGH 50%; 12 | -------------------------------------------------------------------------------- /target/papilio-one/serial/src-hdl/PapilioOne.ucf: -------------------------------------------------------------------------------- 1 | # NET RESET_BTN LOC="P67" | IOSTANDARD=LVTTL | PULLDOWN; # A11 2 | 3 | NET RX LOC="P90" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX 4 | NET TX LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX 5 | 6 | # NET JTAG_TMS LOC="P75" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS 7 | # NET JTAG_TCK LOC="P77" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK 8 | # NET JTAG_TDI LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI 9 | # NET JTAG_TDO LOC="P76" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO 10 | 11 | # NET FLASH_CS LOC="P24" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS 12 | # NET FLASH_CK LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK 13 | # NET FLASH_SI LOC="P27" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI 14 | # NET FLASH_SO LOC="P44" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO 15 | -------------------------------------------------------------------------------- /target/papilio-one/serial/src-hdl/TinyBASICSerial.v: -------------------------------------------------------------------------------- 1 | module TinyBASICSerial( 2 | input CLK_32MHZ, 3 | input RX, 4 | output TX 5 | ); 6 | 7 | topEntity u_topEntity 8 | (.CLK(CLK_32MHZ), 9 | .RESET(1'b0), 10 | .RX(RX), 11 | .TX(TX) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /target/papilio-one/video/ipcore_dir/DCM25.xaw: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.6e 3 | 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2g=;2h?87>51283>5}#>00??6*k:3g8 `<092.:<7<:;%32>73<,881>45+12811>"6<31c<,831>?5+4186?!4a2?1/?94n;%16>==#;10?i6*i6?5+4786a>"303?n7):n:648 1b=<2.?j7;8;%72>0`<,<919k5+558;?!3?2<80(;>5b:&51?6<,>818h5+7684<>"a2h1/=h4;7:&6e?7<,<31;6g<7;29 3>=091/:l486:9j75<72-<365>4$7c933=<07d8k:18'2==n>k0;6)87:928 31=??10e9750;&573-<<6:84;n06>5<#>103<6*9a;55?!7c2<:07b44?:%4;>=6<3f8j6=4+698;4>=h:l0;6)87:928?j4e290/:5470:9l6f<72-<365>4;n11>5<#>103<6*>c;00?!7e2:<07b=<:18'2=4?:%4;>=7<,?<1;;54o4a94?"1032;7)8n:648?j0d290/:5470:9~f6g=8381<7>t$7;913=n=<0;6)87:928 3g=??10c;=50;&573-5$7:9<5=#>h0<:65rs2;94?4|5=>1?:523`857>"6i39i7p}<1;296~;3<39;70<8:718 4g=:11v?850;0x912=:<16>:4:5:p1a<728q6894:c:&44?043ty8o7>51z?0e?323-=;68;4}r1a>5<7s-=;6;=4}r0;>5<7s-=;6;=4}|l74?6=9rwe8<4?:0y~j14=83;pqc:<:182xh3<3:1=vsa4483>4}zf=<1<7?t}|~DEE|3d0~DED|8tJK\vsO@ -------------------------------------------------------------------------------- /target/papilio-one/video/src-hdl/PapilioOne-Arcade.ucf: -------------------------------------------------------------------------------- 1 | # NET LEDS(3) LOC="P35" | IOSTANDARD=LVTTL; # A4 2 | # NET LEDS(2) LOC="P40" | IOSTANDARD=LVTTL; # A5 3 | # NET LEDS(1) LOC="P53" | IOSTANDARD=LVTTL; # A6 4 | # NET LEDS(0) LOC="P57" | IOSTANDARD=LVTTL; # A7 5 | 6 | NET PS2CLK_A LOC="P92" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C1 7 | NET PS2DATA_A LOC="P91" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C0 8 | 9 | # NET PS2CLK_B LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A13 10 | # NET PS2DATA_B LOC="P79" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A12 11 | 12 | # NET AUDIO_L LOC="P84" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # A14 13 | # NET AUDIO_R LOC="P86" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # A15 14 | 15 | NET VGA_VSYNC LOC="P94" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C2 16 | NET VGA_HSYNC LOC="P95" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C3 17 | NET VGA_RED(0) LOC="P98" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C4 18 | NET VGA_RED(1) LOC="P2" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C5 19 | NET VGA_RED(2) LOC="P3" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C6 20 | NET VGA_RED(3) LOC="P4" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C7 21 | NET VGA_GREEN(0) LOC="P68" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4 22 | NET VGA_GREEN(1) LOC="P66" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5 23 | NET VGA_GREEN(2) LOC="P63" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6 24 | NET VGA_GREEN(3) LOC="P61" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7 25 | NET VGA_BLUE(0) LOC="P85" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0 26 | NET VGA_BLUE(1) LOC="P83" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1 27 | NET VGA_BLUE(2) LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2 28 | NET VGA_BLUE(3) LOC="P71" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3 29 | 30 | # NET BUTTON_UP LOC="P54" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B9 31 | # NET BUTTON_DOWN LOC="P41" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B10 32 | # NET BUTTON_LEFT LOC="P58" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B8 33 | # NET BUTTON_RIGTH LOC="P36" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B11 34 | 35 | # NET JOYSTICK_A(0) LOC="P34" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B12 36 | # NET JOYSTICK_A(1) LOC="P25" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B14 37 | # NET JOYSTICK_A(2) LOC="P22" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B15 38 | # NET JOYSTICK_A(3) LOC="P23" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A1 39 | # NET JOYSTICK_A(4) LOC="P33" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A3 40 | # NET JOYSTICK_A(5) LOC="P32" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B13 41 | # NET JOYSTICK_A(7) LOC="P18" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A0 42 | # NET JOYSTICK_A(8) LOC="P26" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A2 43 | 44 | # NET JOYSTICK_B(0) LOC="P5" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C8 45 | # NET JOYSTICK_B(1) LOC="P10" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C10 46 | # NET JOYSTICK_B(2) LOC="P11" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C11 47 | # NET JOYSTICK_B(3) LOC="P15" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C13 48 | # NET JOYSTICK_B(4) LOC="P17" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C15 49 | # NET JOYSTICK_B(5) LOC="P9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C9 50 | # NET JOYSTICK_B(7) LOC="P12" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C12 51 | # NET JOYSTICK_B(8) LOC="P16" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C14 52 | -------------------------------------------------------------------------------- /target/papilio-one/video/src-hdl/PapilioOne-Base.ucf: -------------------------------------------------------------------------------- 1 | CONFIG PROHIBIT=P99; 2 | CONFIG PROHIBIT=P43; 3 | CONFIG PROHIBIT=P42; 4 | CONFIG PROHIBIT=P39; 5 | CONFIG PROHIBIT=P49; 6 | CONFIG PROHIBIT=P48; 7 | CONFIG PROHIBIT=P47; 8 | CONFIG PART="XC3S500E-VQ100-5"; 9 | 10 | NET "CLK_32MHZ" LOC = "P89" | IOSTANDARD = LVCMOS25 | TNM_NET = CLK_32; 11 | TIMESPEC TS_CLK_32MHZ = PERIOD "CLK_32" 32 MHz HIGH 50%; 12 | -------------------------------------------------------------------------------- /target/papilio-one/video/src-hdl/PapilioOne.ucf: -------------------------------------------------------------------------------- 1 | # NET RESET_BTN LOC="P67" | IOSTANDARD=LVTTL | PULLDOWN; # A11 2 | 3 | NET RX LOC="P90" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX 4 | NET TX LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX 5 | 6 | # NET JTAG_TMS LOC="P75" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS 7 | # NET JTAG_TCK LOC="P77" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK 8 | # NET JTAG_TDI LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI 9 | # NET JTAG_TDO LOC="P76" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO 10 | 11 | # NET FLASH_CS LOC="P24" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS 12 | # NET FLASH_CK LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK 13 | # NET FLASH_SI LOC="P27" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI 14 | # NET FLASH_SO LOC="P44" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO 15 | -------------------------------------------------------------------------------- /target/papilio-one/video/src-hdl/TinyBASICVideo.v: -------------------------------------------------------------------------------- 1 | module TinyBASICVideo( 2 | input CLK_32MHZ, 3 | input PS2CLK_A, 4 | input PS2DATA_A, 5 | output VGA_VSYNC, 6 | output VGA_HSYNC, 7 | output [3:0] VGA_RED, 8 | output [3:0] VGA_GREEN, 9 | output [3:0] VGA_BLUE 10 | ); 11 | 12 | wire CLK_25MHZ; 13 | wire CLK_LOCKED; 14 | wire [7:0] VGA_RED_FULL; 15 | wire [7:0] VGA_GREEN_FULL; 16 | wire [7:0] VGA_BLUE_FULL; 17 | 18 | assign VGA_RED = VGA_RED_FULL[7:4]; 19 | assign VGA_GREEN = VGA_GREEN_FULL[7:4]; 20 | assign VGA_BLUE = VGA_BLUE_FULL[7:4]; 21 | 22 | DCM25 u_DCM25 23 | (.CLKIN_IN(CLK_32MHZ), 24 | .CLKIN_IBUFG_OUT(), 25 | .CLK0_OUT(CLK_25MHZ), 26 | .LOCKED_OUT(CLK_LOCKED) 27 | ); 28 | 29 | topEntity u_topEntity 30 | (.CLK_25MHZ(CLK_25MHZ), 31 | .RESET(!CLK_LOCKED), 32 | .PS2_CLK(PS2CLK_A), 33 | .PS2_DATA(PS2DATA_A), 34 | .VGA_VSYNC(VGA_VSYNC), 35 | .VGA_HSYNC(VGA_HSYNC), 36 | .VGA_RED(VGA_RED_FULL[7:0]), 37 | .VGA_GREEN(VGA_GREEN_FULL[7:0]), 38 | .VGA_BLUE(VGA_BLUE_FULL[7:0]) 39 | ); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /target/papilio-pro/serial/src-hdl/PapilioPro-Base.ucf: -------------------------------------------------------------------------------- 1 | CONFIG PROHIBIT=P60; 2 | CONFIG PROHIBIT=P69; 3 | CONFIG PROHIBIT=P144; 4 | CONFIG PART="XC6SLX9-TQG144-2"; 5 | 6 | NET "CLK_32MHZ" LOC = "P94" | IOSTANDARD = LVTTL | TNM_NET = CLK_32; 7 | TIMESPEC TS_CLK_32MHZ = PERIOD "CLK_32" 32 MHz HIGH 50%; 8 | -------------------------------------------------------------------------------- /target/papilio-pro/serial/src-hdl/PapilioPro.ucf: -------------------------------------------------------------------------------- 1 | # NET LED1 LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED1 2 | # NET RESET_BTN LOC="P85" | IOSTANDARD=LVTTL | PULLDOWN; # A11 3 | 4 | NET RX LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX 5 | NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX 6 | 7 | # NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0 8 | # NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1 9 | # NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2 10 | # NET SDRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL; # SDRAM_ADDR3 11 | # NET SDRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL; # SDRAM_ADDR4 12 | # NET SDRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL; # SDRAM_ADDR5 13 | # NET SDRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL; # SDRAM_ADDR6 14 | # NET SDRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL; # SDRAM_ADDR7 15 | # NET SDRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL; # SDRAM_ADDR8 16 | # NET SDRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL; # SDRAM_ADDR9 17 | # NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL; # SDRAM_ADDR10 18 | # NET SDRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL; # SDRAM_ADDR11 19 | # NET SDRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL; # SDRAM_ADDR12 20 | # NET SDRAM_DATA(0) LOC="P9" | IOSTANDARD=LVTTL; # SDRAM_DATA0 21 | # NET SDRAM_DATA(1) LOC="P10" | IOSTANDARD=LVTTL; # SDRAM_DATA1 22 | # NET SDRAM_DATA(2) LOC="P11" | IOSTANDARD=LVTTL; # SDRAM_DATA2 23 | # NET SDRAM_DATA(3) LOC="P12" | IOSTANDARD=LVTTL; # SDRAM_DATA3 24 | # NET SDRAM_DATA(4) LOC="P14" | IOSTANDARD=LVTTL; # SDRAM_DATA4 25 | # NET SDRAM_DATA(5) LOC="P15" | IOSTANDARD=LVTTL; # SDRAM_DATA5 26 | # NET SDRAM_DATA(6) LOC="P16" | IOSTANDARD=LVTTL; # SDRAM_DATA6 27 | # NET SDRAM_DATA(7) LOC="P8" | IOSTANDARD=LVTTL; # SDRAM_DATA7 28 | # NET SDRAM_DATA(8) LOC="P21" | IOSTANDARD=LVTTL; # SDRAM_DATA8 29 | # NET SDRAM_DATA(9) LOC="P22" | IOSTANDARD=LVTTL; # SDRAM_DATA9 30 | # NET SDRAM_DATA(10) LOC="P23" | IOSTANDARD=LVTTL; # SDRAM_DATA10 31 | # NET SDRAM_DATA(11) LOC="P24" | IOSTANDARD=LVTTL; # SDRAM_DATA11 32 | # NET SDRAM_DATA(12) LOC="P26" | IOSTANDARD=LVTTL; # SDRAM_DATA12 33 | # NET SDRAM_DATA(13) LOC="P27" | IOSTANDARD=LVTTL; # SDRAM_DATA13 34 | # NET SDRAM_DATA(14) LOC="P29" | IOSTANDARD=LVTTL; # SDRAM_DATA14 35 | # NET SDRAM_DATA(15) LOC="P30" | IOSTANDARD=LVTTL; # SDRAM_DATA15 36 | # NET SDRAM_DQML LOC="P7" | IOSTANDARD=LVTTL; # SDRAM_DQML 37 | # NET SDRAM_DQMH LOC="P17" | IOSTANDARD=LVTTL; # SDRAM_DQMH 38 | # NET SDRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL; # SDRAM_BA0 39 | # NET SDRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL; # SDRAM_BA1 40 | # NET SDRAM_nWE LOC="P6" | IOSTANDARD=LVTTL; # SDRAM_nWE 41 | # NET SDRAM_nCAS LOC="P5" | IOSTANDARD=LVTTL; # SDRAM_nCAS 42 | # NET SDRAM_nRAS LOC="P2" | IOSTANDARD=LVTTL; # SDRAM_nRAS 43 | # NET SDRAM_CS LOC="P1" | IOSTANDARD=LVTTL; # SDRAM_CS 44 | # NET SDRAM_CLK LOC="P32" | IOSTANDARD=LVTTL; # SDRAM_CLK 45 | # NET SDRAM_CKE LOC="P33" | IOSTANDARD=LVTTL; # SDRAM_CKE 46 | 47 | # NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS 48 | # NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK 49 | # NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI 50 | # NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO 51 | 52 | # NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS 53 | # NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK 54 | # NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI 55 | # NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO 56 | -------------------------------------------------------------------------------- /target/papilio-pro/serial/src-hdl/TinyBASICSerial.v: -------------------------------------------------------------------------------- 1 | module TinyBASICSerial( 2 | input CLK_32MHZ, 3 | input RX, 4 | output TX 5 | ); 6 | 7 | topEntity u_topEntity 8 | (.CLK(CLK_32MHZ), 9 | .RESET(1'b0), 10 | .RX(RX), 11 | .TX(TX) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /target/papilio-pro/video/ipcore_dir/ClockMan25.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Fri Jun 14 00:46:00 2019 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:clk_wiz:3.6 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = VHDL 25 | SET device = xc6slx9 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = tqg144 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = false 36 | SET vhdlsim = true 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 40 | # END Select 41 | # BEGIN Parameters 42 | CSET calc_done=DONE 43 | CSET clk_in_sel_port=CLK_IN_SEL 44 | CSET clk_out1_port=CLK_OUT1 45 | CSET clk_out1_use_fine_ps_gui=false 46 | CSET clk_out2_port=CLK_OUT2 47 | CSET clk_out2_use_fine_ps_gui=false 48 | CSET clk_out3_port=CLK_OUT3 49 | CSET clk_out3_use_fine_ps_gui=false 50 | CSET clk_out4_port=CLK_OUT4 51 | CSET clk_out4_use_fine_ps_gui=false 52 | CSET clk_out5_port=CLK_OUT5 53 | CSET clk_out5_use_fine_ps_gui=false 54 | CSET clk_out6_port=CLK_OUT6 55 | CSET clk_out6_use_fine_ps_gui=false 56 | CSET clk_out7_port=CLK_OUT7 57 | CSET clk_out7_use_fine_ps_gui=false 58 | CSET clk_valid_port=CLK_VALID 59 | CSET clkfb_in_n_port=CLKFB_IN_N 60 | CSET clkfb_in_p_port=CLKFB_IN_P 61 | CSET clkfb_in_port=CLKFB_IN 62 | CSET clkfb_in_signaling=SINGLE 63 | CSET clkfb_out_n_port=CLKFB_OUT_N 64 | CSET clkfb_out_p_port=CLKFB_OUT_P 65 | CSET clkfb_out_port=CLKFB_OUT 66 | CSET clkfb_stopped_port=CLKFB_STOPPED 67 | CSET clkin1_jitter_ps=312.5 68 | CSET clkin1_ui_jitter=0.010 69 | CSET clkin2_jitter_ps=100.0 70 | CSET clkin2_ui_jitter=0.010 71 | CSET clkout1_drives=BUFG 72 | CSET clkout1_requested_duty_cycle=50.000 73 | CSET clkout1_requested_out_freq=25.175 74 | CSET clkout1_requested_phase=0.000 75 | CSET clkout2_drives=BUFG 76 | CSET clkout2_requested_duty_cycle=50.000 77 | CSET clkout2_requested_out_freq=1.000 78 | CSET clkout2_requested_phase=0.000 79 | CSET clkout2_used=false 80 | CSET clkout3_drives=BUFG 81 | CSET clkout3_requested_duty_cycle=50.000 82 | CSET clkout3_requested_out_freq=100.000 83 | CSET clkout3_requested_phase=0.000 84 | CSET clkout3_used=false 85 | CSET clkout4_drives=BUFG 86 | CSET clkout4_requested_duty_cycle=50.000 87 | CSET clkout4_requested_out_freq=100.000 88 | CSET clkout4_requested_phase=0.000 89 | CSET clkout4_used=false 90 | CSET clkout5_drives=BUFG 91 | CSET clkout5_requested_duty_cycle=50.000 92 | CSET clkout5_requested_out_freq=100.000 93 | CSET clkout5_requested_phase=0.000 94 | CSET clkout5_used=false 95 | CSET clkout6_drives=BUFG 96 | CSET clkout6_requested_duty_cycle=50.000 97 | CSET clkout6_requested_out_freq=100.000 98 | CSET clkout6_requested_phase=0.000 99 | CSET clkout6_used=false 100 | CSET clkout7_drives=BUFG 101 | CSET clkout7_requested_duty_cycle=50.000 102 | CSET clkout7_requested_out_freq=100.000 103 | CSET clkout7_requested_phase=0.000 104 | CSET clkout7_used=false 105 | CSET clock_mgr_type=AUTO 106 | CSET component_name=ClockMan25 107 | CSET daddr_port=DADDR 108 | CSET dclk_port=DCLK 109 | CSET dcm_clk_feedback=1X 110 | CSET dcm_clk_out1_port=CLKFX 111 | CSET dcm_clk_out2_port=CLKDV 112 | CSET dcm_clk_out3_port=CLK0 113 | CSET dcm_clk_out4_port=CLK0 114 | CSET dcm_clk_out5_port=CLK0 115 | CSET dcm_clk_out6_port=CLK0 116 | CSET dcm_clkdv_divide=16.0 117 | CSET dcm_clkfx_divide=2 118 | CSET dcm_clkfx_multiply=5 119 | CSET dcm_clkgen_clk_out1_port=CLKFX 120 | CSET dcm_clkgen_clk_out2_port=CLKFX 121 | CSET dcm_clkgen_clk_out3_port=CLKFX 122 | CSET dcm_clkgen_clkfx_divide=1 123 | CSET dcm_clkgen_clkfx_md_max=0.000 124 | CSET dcm_clkgen_clkfx_multiply=4 125 | CSET dcm_clkgen_clkfxdv_divide=2 126 | CSET dcm_clkgen_clkin_period=10.000 127 | CSET dcm_clkgen_notes=None 128 | CSET dcm_clkgen_spread_spectrum=NONE 129 | CSET dcm_clkgen_startup_wait=false 130 | CSET dcm_clkin_divide_by_2=true 131 | CSET dcm_clkin_period=31.250 132 | CSET dcm_clkout_phase_shift=NONE 133 | CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS 134 | CSET dcm_notes=None 135 | CSET dcm_phase_shift=0 136 | CSET dcm_pll_cascade=NONE 137 | CSET dcm_startup_wait=false 138 | CSET den_port=DEN 139 | CSET din_port=DIN 140 | CSET dout_port=DOUT 141 | CSET drdy_port=DRDY 142 | CSET dwe_port=DWE 143 | CSET feedback_source=FDBK_AUTO 144 | CSET in_freq_units=Units_MHz 145 | CSET in_jitter_units=Units_UI 146 | CSET input_clk_stopped_port=INPUT_CLK_STOPPED 147 | CSET jitter_options=UI 148 | CSET jitter_sel=No_Jitter 149 | CSET locked_port=LOCKED 150 | CSET mmcm_bandwidth=OPTIMIZED 151 | CSET mmcm_clkfbout_mult_f=4.000 152 | CSET mmcm_clkfbout_phase=0.000 153 | CSET mmcm_clkfbout_use_fine_ps=false 154 | CSET mmcm_clkin1_period=10.000 155 | CSET mmcm_clkin2_period=10.000 156 | CSET mmcm_clkout0_divide_f=4.000 157 | CSET mmcm_clkout0_duty_cycle=0.500 158 | CSET mmcm_clkout0_phase=0.000 159 | CSET mmcm_clkout0_use_fine_ps=false 160 | CSET mmcm_clkout1_divide=1 161 | CSET mmcm_clkout1_duty_cycle=0.500 162 | CSET mmcm_clkout1_phase=0.000 163 | CSET mmcm_clkout1_use_fine_ps=false 164 | CSET mmcm_clkout2_divide=1 165 | CSET mmcm_clkout2_duty_cycle=0.500 166 | CSET mmcm_clkout2_phase=0.000 167 | CSET mmcm_clkout2_use_fine_ps=false 168 | CSET mmcm_clkout3_divide=1 169 | CSET mmcm_clkout3_duty_cycle=0.500 170 | CSET mmcm_clkout3_phase=0.000 171 | CSET mmcm_clkout3_use_fine_ps=false 172 | CSET mmcm_clkout4_cascade=false 173 | CSET mmcm_clkout4_divide=1 174 | CSET mmcm_clkout4_duty_cycle=0.500 175 | CSET mmcm_clkout4_phase=0.000 176 | CSET mmcm_clkout4_use_fine_ps=false 177 | CSET mmcm_clkout5_divide=1 178 | CSET mmcm_clkout5_duty_cycle=0.500 179 | CSET mmcm_clkout5_phase=0.000 180 | CSET mmcm_clkout5_use_fine_ps=false 181 | CSET mmcm_clkout6_divide=1 182 | CSET mmcm_clkout6_duty_cycle=0.500 183 | CSET mmcm_clkout6_phase=0.000 184 | CSET mmcm_clkout6_use_fine_ps=false 185 | CSET mmcm_clock_hold=false 186 | CSET mmcm_compensation=ZHOLD 187 | CSET mmcm_divclk_divide=1 188 | CSET mmcm_notes=None 189 | CSET mmcm_ref_jitter1=0.010 190 | CSET mmcm_ref_jitter2=0.010 191 | CSET mmcm_startup_wait=false 192 | CSET num_out_clks=1 193 | CSET override_dcm=false 194 | CSET override_dcm_clkgen=false 195 | CSET override_mmcm=false 196 | CSET override_pll=false 197 | CSET platform=lin64 198 | CSET pll_bandwidth=OPTIMIZED 199 | CSET pll_clk_feedback=CLKFBOUT 200 | CSET pll_clkfbout_mult=22 201 | CSET pll_clkfbout_phase=0.000 202 | CSET pll_clkin_period=31.250 203 | CSET pll_clkout0_divide=28 204 | CSET pll_clkout0_duty_cycle=0.500 205 | CSET pll_clkout0_phase=0.000 206 | CSET pll_clkout1_divide=8 207 | CSET pll_clkout1_duty_cycle=0.500 208 | CSET pll_clkout1_phase=0.000 209 | CSET pll_clkout2_divide=1 210 | CSET pll_clkout2_duty_cycle=0.500 211 | CSET pll_clkout2_phase=0.000 212 | CSET pll_clkout3_divide=1 213 | CSET pll_clkout3_duty_cycle=0.500 214 | CSET pll_clkout3_phase=0.000 215 | CSET pll_clkout4_divide=1 216 | CSET pll_clkout4_duty_cycle=0.500 217 | CSET pll_clkout4_phase=0.000 218 | CSET pll_clkout5_divide=1 219 | CSET pll_clkout5_duty_cycle=0.500 220 | CSET pll_clkout5_phase=0.000 221 | CSET pll_compensation=SYSTEM_SYNCHRONOUS 222 | CSET pll_divclk_divide=1 223 | CSET pll_notes=None 224 | CSET pll_ref_jitter=0.010 225 | CSET power_down_port=POWER_DOWN 226 | CSET prim_in_freq=32 227 | CSET prim_in_jitter=0.010 228 | CSET prim_source=Single_ended_clock_capable_pin 229 | CSET primary_port=CLK_IN1 230 | CSET primitive=MMCM 231 | CSET primtype_sel=PLL_BASE 232 | CSET psclk_port=PSCLK 233 | CSET psdone_port=PSDONE 234 | CSET psen_port=PSEN 235 | CSET psincdec_port=PSINCDEC 236 | CSET relative_inclk=REL_PRIMARY 237 | CSET reset_port=RESET 238 | CSET secondary_in_freq=100.000 239 | CSET secondary_in_jitter=0.010 240 | CSET secondary_port=CLK_IN2 241 | CSET secondary_source=Single_ended_clock_capable_pin 242 | CSET ss_mod_freq=250 243 | CSET ss_mode=CENTER_HIGH 244 | CSET status_port=STATUS 245 | CSET summary_strings=empty 246 | CSET use_clk_valid=false 247 | CSET use_clkfb_stopped=false 248 | CSET use_dyn_phase_shift=false 249 | CSET use_dyn_reconfig=false 250 | CSET use_freeze=false 251 | CSET use_freq_synth=true 252 | CSET use_inclk_stopped=false 253 | CSET use_inclk_switchover=false 254 | CSET use_locked=true 255 | CSET use_max_i_jitter=false 256 | CSET use_min_o_jitter=false 257 | CSET use_min_power=false 258 | CSET use_phase_alignment=true 259 | CSET use_power_down=false 260 | CSET use_reset=false 261 | CSET use_spread_spectrum=false 262 | CSET use_spread_spectrum_1=false 263 | CSET use_status=false 264 | # END Parameters 265 | # BEGIN Extra information 266 | MISC pkg_timestamp=2012-05-10T12:44:55Z 267 | # END Extra information 268 | GENERATE 269 | # CRC: 2c0c41a4 270 | -------------------------------------------------------------------------------- /target/papilio-pro/video/src-hdl/PapilioPro-Arcade.ucf: -------------------------------------------------------------------------------- 1 | # NET LEDS(3) LOC="P61" | IOSTANDARD=LVTTL; # A4 2 | # NET LEDS(2) LOC="P66" | IOSTANDARD=LVTTL; # A5 3 | # NET LEDS(1) LOC="P67" | IOSTANDARD=LVTTL; # A6 4 | # NET LEDS(0) LOC="P75" | IOSTANDARD=LVTTL; # A7 5 | 6 | NET PS2CLK_A LOC="P115" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C1 7 | NET PS2DATA_A LOC="P114" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C0 8 | 9 | # NET PS2CLK_B LOC="P93" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A13 10 | # NET PS2DATA_B LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A12 11 | 12 | # NET AUDIO_L LOC="P98" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # A14 13 | # NET AUDIO_R LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # A15 14 | 15 | NET VGA_VSYNC LOC="P116" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C2 16 | NET VGA_HSYNC LOC="P117" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C3 17 | NET VGA_RED(0) LOC="P118" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C4 18 | NET VGA_RED(1) LOC="P119" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C5 19 | NET VGA_RED(2) LOC="P120" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C6 20 | NET VGA_RED(3) LOC="P121" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C7 21 | NET VGA_GREEN(0) LOC="P84" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4 22 | NET VGA_GREEN(1) LOC="P82" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5 23 | NET VGA_GREEN(2) LOC="P80" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6 24 | NET VGA_GREEN(3) LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7 25 | NET VGA_BLUE(0) LOC="P99" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0 26 | NET VGA_BLUE(1) LOC="P97" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1 27 | NET VGA_BLUE(2) LOC="P92" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2 28 | NET VGA_BLUE(3) LOC="P87" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3 29 | 30 | # NET BUTTON_UP LOC="P95" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B9 31 | # NET BUTTON_DOWN LOC="P62" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B10 32 | # NET BUTTON_LEFT LOC="P74" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B8 33 | # NET BUTTON_RIGHT LOC="P59" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B11 34 | 35 | # NET JOYSTICK_A(0) LOC="P57" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B12 36 | # NET JOYSTICK_A(1) LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B14 37 | # NET JOYSTICK_A(2) LOC="P47" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B15 38 | # NET JOYSTICK_A(3) LOC="P51" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A1 39 | # NET JOYSTICK_A(4) LOC="P58" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A3 40 | # NET JOYSTICK_A(5) LOC="P55" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # B13 41 | # NET JOYSTICK_A(7) LOC="P48" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A0 42 | # NET JOYSTICK_A(8) LOC="P56" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A2 43 | 44 | # NET JOYSTICK_B(0) LOC="P123" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C8 45 | # NET JOYSTICK_B(1) LOC="P126" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C10 46 | # NET JOYSTICK_B(2) LOC="P127" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C11 47 | # NET JOYSTICK_B(3) LOC="P132" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C13 48 | # NET JOYSTICK_B(4) LOC="P134" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C15 49 | # NET JOYSTICK_B(5) LOC="P124" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C9 50 | # NET JOYSTICK_B(7) LOC="P131" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C12 51 | # NET JOYSTICK_B(8) LOC="P133" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C14 52 | 53 | -------------------------------------------------------------------------------- /target/papilio-pro/video/src-hdl/PapilioPro-Base.ucf: -------------------------------------------------------------------------------- 1 | CONFIG PROHIBIT=P60; 2 | CONFIG PROHIBIT=P69; 3 | CONFIG PROHIBIT=P144; 4 | CONFIG PART="XC6SLX9-TQG144-2"; 5 | 6 | NET "CLK_32MHZ" LOC = "P94" | IOSTANDARD = LVTTL | TNM_NET = CLK_32; 7 | TIMESPEC TS_CLK_32MHZ = PERIOD "CLK_32" 32 MHz HIGH 50%; 8 | -------------------------------------------------------------------------------- /target/papilio-pro/video/src-hdl/PapilioPro.ucf: -------------------------------------------------------------------------------- 1 | # NET LED1 LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED1 2 | # NET RESET_BTN LOC="P85" | IOSTANDARD=LVTTL | PULLDOWN; # A11 3 | 4 | # NET RX LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX 5 | # NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX 6 | 7 | # NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0 8 | # NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1 9 | # NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2 10 | # NET SDRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL; # SDRAM_ADDR3 11 | # NET SDRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL; # SDRAM_ADDR4 12 | # NET SDRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL; # SDRAM_ADDR5 13 | # NET SDRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL; # SDRAM_ADDR6 14 | # NET SDRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL; # SDRAM_ADDR7 15 | # NET SDRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL; # SDRAM_ADDR8 16 | # NET SDRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL; # SDRAM_ADDR9 17 | # NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL; # SDRAM_ADDR10 18 | # NET SDRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL; # SDRAM_ADDR11 19 | # NET SDRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL; # SDRAM_ADDR12 20 | # NET SDRAM_DATA(0) LOC="P9" | IOSTANDARD=LVTTL; # SDRAM_DATA0 21 | # NET SDRAM_DATA(1) LOC="P10" | IOSTANDARD=LVTTL; # SDRAM_DATA1 22 | # NET SDRAM_DATA(2) LOC="P11" | IOSTANDARD=LVTTL; # SDRAM_DATA2 23 | # NET SDRAM_DATA(3) LOC="P12" | IOSTANDARD=LVTTL; # SDRAM_DATA3 24 | # NET SDRAM_DATA(4) LOC="P14" | IOSTANDARD=LVTTL; # SDRAM_DATA4 25 | # NET SDRAM_DATA(5) LOC="P15" | IOSTANDARD=LVTTL; # SDRAM_DATA5 26 | # NET SDRAM_DATA(6) LOC="P16" | IOSTANDARD=LVTTL; # SDRAM_DATA6 27 | # NET SDRAM_DATA(7) LOC="P8" | IOSTANDARD=LVTTL; # SDRAM_DATA7 28 | # NET SDRAM_DATA(8) LOC="P21" | IOSTANDARD=LVTTL; # SDRAM_DATA8 29 | # NET SDRAM_DATA(9) LOC="P22" | IOSTANDARD=LVTTL; # SDRAM_DATA9 30 | # NET SDRAM_DATA(10) LOC="P23" | IOSTANDARD=LVTTL; # SDRAM_DATA10 31 | # NET SDRAM_DATA(11) LOC="P24" | IOSTANDARD=LVTTL; # SDRAM_DATA11 32 | # NET SDRAM_DATA(12) LOC="P26" | IOSTANDARD=LVTTL; # SDRAM_DATA12 33 | # NET SDRAM_DATA(13) LOC="P27" | IOSTANDARD=LVTTL; # SDRAM_DATA13 34 | # NET SDRAM_DATA(14) LOC="P29" | IOSTANDARD=LVTTL; # SDRAM_DATA14 35 | # NET SDRAM_DATA(15) LOC="P30" | IOSTANDARD=LVTTL; # SDRAM_DATA15 36 | # NET SDRAM_DQML LOC="P7" | IOSTANDARD=LVTTL; # SDRAM_DQML 37 | # NET SDRAM_DQMH LOC="P17" | IOSTANDARD=LVTTL; # SDRAM_DQMH 38 | # NET SDRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL; # SDRAM_BA0 39 | # NET SDRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL; # SDRAM_BA1 40 | # NET SDRAM_nWE LOC="P6" | IOSTANDARD=LVTTL; # SDRAM_nWE 41 | # NET SDRAM_nCAS LOC="P5" | IOSTANDARD=LVTTL; # SDRAM_nCAS 42 | # NET SDRAM_nRAS LOC="P2" | IOSTANDARD=LVTTL; # SDRAM_nRAS 43 | # NET SDRAM_CS LOC="P1" | IOSTANDARD=LVTTL; # SDRAM_CS 44 | # NET SDRAM_CLK LOC="P32" | IOSTANDARD=LVTTL; # SDRAM_CLK 45 | # NET SDRAM_CKE LOC="P33" | IOSTANDARD=LVTTL; # SDRAM_CKE 46 | 47 | # NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS 48 | # NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK 49 | # NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI 50 | # NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO 51 | 52 | # NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS 53 | # NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK 54 | # NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI 55 | # NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO 56 | -------------------------------------------------------------------------------- /target/papilio-pro/video/src-hdl/TinyBASICVideo.v: -------------------------------------------------------------------------------- 1 | module TinyBASICVideo( 2 | input CLK_32MHZ, 3 | input PS2CLK_A, 4 | input PS2DATA_A, 5 | output VGA_VSYNC, 6 | output VGA_HSYNC, 7 | output [3:0] VGA_RED, 8 | output [3:0] VGA_GREEN, 9 | output [3:0] VGA_BLUE 10 | ); 11 | 12 | wire CLK_25MHZ; 13 | wire CLK_LOCKED; 14 | wire [7:0] VGA_RED_FULL; 15 | wire [7:0] VGA_GREEN_FULL; 16 | wire [7:0] VGA_BLUE_FULL; 17 | 18 | assign VGA_RED = VGA_RED_FULL[7:4]; 19 | assign VGA_GREEN = VGA_GREEN_FULL[7:4]; 20 | assign VGA_BLUE = VGA_BLUE_FULL[7:4]; 21 | 22 | ClockMan25 u_ClockMan25 23 | (.CLK_IN1(CLK_32MHZ), 24 | .CLK_OUT1(CLK_25MHZ), 25 | .LOCKED(CLK_LOCKED) 26 | ); 27 | 28 | topEntity u_topEntity 29 | (.CLK_25MHZ(CLK_25MHZ), 30 | .RESET(!CLK_LOCKED), 31 | .PS2_CLK(PS2CLK_A), 32 | .PS2_DATA(PS2DATA_A), 33 | .VGA_VSYNC(VGA_VSYNC), 34 | .VGA_HSYNC(VGA_HSYNC), 35 | .VGA_RED(VGA_RED_FULL[7:0]), 36 | .VGA_GREEN(VGA_GREEN_FULL[7:0]), 37 | .VGA_BLUE(VGA_BLUE_FULL[7:0]) 38 | ); 39 | 40 | endmodule 41 | --------------------------------------------------------------------------------