├── .gitignore ├── interface_jlink.cfg ├── flash_jlink.cfg ├── flash_stlink.cfg ├── interface_stlink.cfg ├── dump.cfg ├── flash.cfg ├── Core ├── Inc │ ├── lcd.h │ ├── buttons.h │ ├── flash.h │ ├── stm32h7xx_it.h │ ├── main.h │ └── stm32h7xx_hal_conf.h └── Src │ ├── buttons.c │ ├── lcd.c │ ├── stm32h7xx_it.c │ ├── flash.c │ ├── system_stm32h7xx.c │ ├── stm32h7xx_hal_msp.c │ └── main.c ├── STM32H7B0VBTx_FLASH.ld ├── Makefile ├── gw_base.ioc └── startup_stm32h7b0xx.s /.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | Drivers 3 | .mxproject -------------------------------------------------------------------------------- /interface_jlink.cfg: -------------------------------------------------------------------------------- 1 | source [find interface/jlink.cfg] 2 | transport select swd 3 | source [find target/stm32h7x.cfg] 4 | -------------------------------------------------------------------------------- /flash_jlink.cfg: -------------------------------------------------------------------------------- 1 | # Use this script to upload flash dumper using a JLink 2 | 3 | source [find interface_jlink.cfg] 4 | source [find flash.cfg] 5 | -------------------------------------------------------------------------------- /flash_stlink.cfg: -------------------------------------------------------------------------------- 1 | # Use this script to upload flash dumper using an STLink 2 | 3 | source [find interface_stlink.cfg] 4 | source [find flash.cfg] 5 | -------------------------------------------------------------------------------- /interface_stlink.cfg: -------------------------------------------------------------------------------- 1 | source [find interface/stlink.cfg] 2 | transport select hla_swd 3 | source [find target/stm32h7x.cfg] 4 | 5 | reset_config none 6 | -------------------------------------------------------------------------------- /dump.cfg: -------------------------------------------------------------------------------- 1 | source [find interface/jlink.cfg] 2 | transport select swd 3 | source [find target/stm32h7x.cfg] 4 | 5 | init 6 | sleep 1000 7 | echo "Dumping" 8 | dump_image flash_backup.bin 0x90000000 1048576 9 | echo "Done!" 10 | #exit 11 | -------------------------------------------------------------------------------- /flash.cfg: -------------------------------------------------------------------------------- 1 | init 2 | echo "Reset and halt" 3 | reset halt 4 | echo "Load image" 5 | load_image build/gw_base.elf 6 | reset halt 7 | sleep 1000 8 | echo "Set stack pointer" 9 | reg sp [mrw 0x20000000] 10 | reg pc [mrw 0x20000004] 11 | echo "Continuing..." 12 | resume 13 | -------------------------------------------------------------------------------- /Core/Inc/lcd.h: -------------------------------------------------------------------------------- 1 | #ifndef _LCD_H_ 2 | #define _LCD_H_ 3 | 4 | #include "stm32h7xx_hal.h" 5 | #include 6 | 7 | extern uint16_t framebuffer[320 * 240] __attribute__((section (".lcd"))); 8 | 9 | #define GFX_MAX_WIDTH 320 10 | 11 | void lcd_init(SPI_HandleTypeDef *spi, LTDC_HandleTypeDef *ltdc); 12 | void lcd_backlight_on(); 13 | void lcd_backlight_off(); 14 | #endif 15 | -------------------------------------------------------------------------------- /Core/Inc/buttons.h: -------------------------------------------------------------------------------- 1 | #ifndef _BUTTONS_H_ 2 | #define _BUTTONS_H_ 3 | 4 | #include 5 | 6 | #define B_Left (1 << 0) 7 | #define B_Up (1 << 1) 8 | #define B_Right (1 << 2) 9 | #define B_Down (1 << 3) 10 | #define B_A (1 << 4) 11 | #define B_B (1 << 5) 12 | #define B_TIME (1 << 6) 13 | #define B_GAME (1 << 7) 14 | #define B_PAUSE (1 << 8) 15 | 16 | uint32_t buttons_get(); 17 | 18 | #endif -------------------------------------------------------------------------------- /Core/Inc/flash.h: -------------------------------------------------------------------------------- 1 | #ifndef _FLASH_H_ 2 | #define _FLASH_H_ 3 | 4 | #include "stm32h7xx_hal.h" 5 | 6 | typedef enum { 7 | SPI_MODE = 0x00, 8 | QUAD_MODE = 0x01, 9 | } quad_mode_t; 10 | 11 | typedef enum { 12 | VENDOR_MX = 0x00, // MX25U8035F, Nintendo Stock Flash 13 | VENDOR_ISSI = 0x01, // IS25WP128F, 128Mb large flash 14 | } spi_chip_vendor_t; 15 | 16 | void OSPI_Init(OSPI_HandleTypeDef *hospi, quad_mode_t quad_mode, spi_chip_vendor_t vendor); 17 | void OSPI_EnableMemoryMappedMode(OSPI_HandleTypeDef *hospi1); 18 | void OSPI_Read(OSPI_HandleTypeDef *hospi, uint32_t address, uint8_t *buffer, size_t buffer_size); 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /Core/Src/buttons.c: -------------------------------------------------------------------------------- 1 | #include "buttons.h" 2 | 3 | #include "stm32h7xx_hal.h" 4 | #include "main.h" 5 | // HAL_GPIO_ReadPin 6 | // #define BTN_PAUSE_Pin GPIO_PIN_13 7 | // #define BTN_PAUSE_GPIO_Port GPIOC 8 | // #define BTN_GAME_Pin GPIO_PIN_1 9 | // #define BTN_GAME_GPIO_Port GPIOC 10 | // #define BTN_TIME_Pin GPIO_PIN_4 11 | // #define BTN_TIME_GPIO_Port GPIOC 12 | // #define BTN_A_Pin GPIO_PIN_9 13 | // #define BTN_A_GPIO_Port GPIOD 14 | // #define BTN_Left_Pin GPIO_PIN_11 15 | // #define BTN_Left_GPIO_Port GPIOD 16 | // #define BTN_Down_Pin GPIO_PIN_14 17 | // #define BTN_Down_GPIO_Port GPIOD 18 | // #define BTN_Right_Pin GPIO_PIN_15 19 | // #define BTN_Right_GPIO_Port GPIOD 20 | // #define BTN_Up_Pin GPIO_PIN_0 21 | // #define BTN_Up_GPIO_Port GPIOD 22 | // #define BTN_B_Pin GPIO_PIN_5 23 | // #define BTN_B_GPIO_Port GPIOD 24 | #include 25 | #define B_Left (1 << 0) 26 | #define B_Up (1 << 1) 27 | #define B_Right (1 << 2) 28 | #define B_Down (1 << 3) 29 | #define B_A (1 << 4) 30 | #define B_B (1 << 5) 31 | #define B_TIME (1 << 6) 32 | #define B_GAME (1 << 7) 33 | #define B_PAUSE (1 << 8) 34 | 35 | uint32_t buttons_get() { 36 | bool left = HAL_GPIO_ReadPin(BTN_Left_GPIO_Port, BTN_Left_Pin) == GPIO_PIN_RESET; 37 | bool right = HAL_GPIO_ReadPin(BTN_Right_GPIO_Port, BTN_Right_Pin) == GPIO_PIN_RESET; 38 | bool up = HAL_GPIO_ReadPin(BTN_Up_GPIO_Port, BTN_Up_Pin) == GPIO_PIN_RESET ; 39 | bool down = HAL_GPIO_ReadPin(BTN_Down_GPIO_Port, BTN_Down_Pin) == GPIO_PIN_RESET; 40 | bool a = HAL_GPIO_ReadPin(BTN_A_GPIO_Port, BTN_A_Pin) == GPIO_PIN_RESET; 41 | bool b = HAL_GPIO_ReadPin(BTN_A_GPIO_Port, BTN_B_Pin) == GPIO_PIN_RESET; 42 | bool time = HAL_GPIO_ReadPin(BTN_TIME_GPIO_Port, BTN_TIME_Pin) == GPIO_PIN_RESET; 43 | bool game = HAL_GPIO_ReadPin(BTN_GAME_GPIO_Port, BTN_GAME_Pin) == GPIO_PIN_RESET; 44 | bool pause = HAL_GPIO_ReadPin(BTN_PAUSE_GPIO_Port, BTN_PAUSE_Pin) == GPIO_PIN_RESET; 45 | 46 | return ( 47 | left | (up << 1) | (right << 2) | (down << 3) | (a << 4) | (b << 5) | (time << 6) | (game << 7) | (pause << 8) 48 | ); 49 | 50 | 51 | } -------------------------------------------------------------------------------- /Core/Inc/stm32h7xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32H7xx_IT_H 23 | #define __STM32H7xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Private includes ----------------------------------------------------------*/ 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN ET */ 36 | 37 | /* USER CODE END ET */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* USER CODE BEGIN EC */ 41 | 42 | /* USER CODE END EC */ 43 | 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* USER CODE BEGIN EM */ 46 | 47 | /* USER CODE END EM */ 48 | 49 | /* Exported functions prototypes ---------------------------------------------*/ 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void MemManage_Handler(void); 53 | void BusFault_Handler(void); 54 | void UsageFault_Handler(void); 55 | void SVC_Handler(void); 56 | void DebugMon_Handler(void); 57 | void PendSV_Handler(void); 58 | void SysTick_Handler(void); 59 | void DMA1_Stream0_IRQHandler(void); 60 | void SAI1_IRQHandler(void); 61 | void OCTOSPI1_IRQHandler(void); 62 | /* USER CODE BEGIN EFP */ 63 | 64 | /* USER CODE END EFP */ 65 | 66 | #ifdef __cplusplus 67 | } 68 | #endif 69 | 70 | #endif /* __STM32H7xx_IT_H */ 71 | 72 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 73 | -------------------------------------------------------------------------------- /Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2020 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MAIN_H 24 | #define __MAIN_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32h7xx_hal.h" 32 | 33 | /* Private includes ----------------------------------------------------------*/ 34 | /* USER CODE BEGIN Includes */ 35 | 36 | /* USER CODE END Includes */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* USER CODE BEGIN ET */ 40 | 41 | /* USER CODE END ET */ 42 | 43 | /* Exported constants --------------------------------------------------------*/ 44 | /* USER CODE BEGIN EC */ 45 | 46 | /* USER CODE END EC */ 47 | 48 | /* Exported macro ------------------------------------------------------------*/ 49 | /* USER CODE BEGIN EM */ 50 | 51 | /* USER CODE END EM */ 52 | 53 | /* Exported functions prototypes ---------------------------------------------*/ 54 | void Error_Handler(void); 55 | 56 | /* USER CODE BEGIN EFP */ 57 | 58 | /* USER CODE END EFP */ 59 | 60 | /* Private defines -----------------------------------------------------------*/ 61 | #define GPIO_Speaker_enable_Pin GPIO_PIN_3 62 | #define GPIO_Speaker_enable_GPIO_Port GPIOE 63 | #define BTN_PAUSE_Pin GPIO_PIN_13 64 | #define BTN_PAUSE_GPIO_Port GPIOC 65 | #define BTN_GAME_Pin GPIO_PIN_1 66 | #define BTN_GAME_GPIO_Port GPIOC 67 | #define BTN_TIME_Pin GPIO_PIN_5 68 | #define BTN_TIME_GPIO_Port GPIOC 69 | #define BTN_A_Pin GPIO_PIN_9 70 | #define BTN_A_GPIO_Port GPIOD 71 | #define BTN_Left_Pin GPIO_PIN_11 72 | #define BTN_Left_GPIO_Port GPIOD 73 | #define BTN_Down_Pin GPIO_PIN_14 74 | #define BTN_Down_GPIO_Port GPIOD 75 | #define BTN_Right_Pin GPIO_PIN_15 76 | #define BTN_Right_GPIO_Port GPIOD 77 | #define BTN_Up_Pin GPIO_PIN_0 78 | #define BTN_Up_GPIO_Port GPIOD 79 | #define BTN_B_Pin GPIO_PIN_5 80 | #define BTN_B_GPIO_Port GPIOD 81 | /* USER CODE BEGIN Private defines */ 82 | 83 | /* USER CODE END Private defines */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /* __MAIN_H */ 90 | 91 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 92 | -------------------------------------------------------------------------------- /Core/Src/lcd.c: -------------------------------------------------------------------------------- 1 | #include "lcd.h" 2 | #include "stm32h7xx_hal.h" 3 | #include "main.h" 4 | 5 | uint16_t framebuffer[320 * 240]; 6 | 7 | void lcd_backlight_off() { 8 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_RESET); 9 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); 10 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_RESET); 11 | } 12 | void lcd_backlight_on() { 13 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET); 14 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); 15 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_6, GPIO_PIN_SET); 16 | } 17 | 18 | void lcd_init(SPI_HandleTypeDef *spi, LTDC_HandleTypeDef *ltdc) { 19 | 20 | // Turn display *off* completely. 21 | lcd_backlight_off(); 22 | 23 | // 3.3v power to display *SET* to disable supply. 24 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_1, GPIO_PIN_SET); 25 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4, GPIO_PIN_RESET); 26 | 27 | 28 | // TURN OFF CHIP SELECT 29 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 30 | // TURN OFF PD8 31 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8, GPIO_PIN_RESET); 32 | 33 | // Turn off CS 34 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 35 | HAL_Delay(100); 36 | 37 | lcd_backlight_on(); 38 | 39 | 40 | // Wake 41 | // Enable 3.3v 42 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_1, GPIO_PIN_RESET); 43 | HAL_Delay(1); 44 | // Enable 1.8V 45 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4, GPIO_PIN_SET); 46 | // also assert CS, not sure where to put this yet 47 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 48 | HAL_Delay(7); 49 | 50 | 51 | 52 | // HAL_SPI_Transmit(spi, "\x55\x55\x55\x55\x55\x55\x55\x55\x55\x55", 10, 100); 53 | // Lets go, bootup sequence. 54 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8, GPIO_PIN_SET); 55 | HAL_Delay(2); 56 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8, GPIO_PIN_RESET); 57 | HAL_Delay(2); 58 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8, GPIO_PIN_SET); 59 | 60 | HAL_Delay(10); 61 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 62 | HAL_Delay(2); 63 | HAL_SPI_Transmit(spi, "\x08\x80", 2, 100); 64 | HAL_Delay(2); 65 | 66 | // CS 67 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 68 | // HAL_Delay(100); 69 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 70 | HAL_Delay(2); 71 | HAL_SPI_Transmit(spi, "\x6E\x80", 2, 100); 72 | HAL_Delay(2); 73 | // CS 74 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 75 | // HAL_Delay(100); 76 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 77 | HAL_Delay(2); 78 | HAL_SPI_Transmit(spi, "\x80\x80", 2, 100); 79 | 80 | HAL_Delay(2); 81 | // CS 82 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 83 | // HAL_Delay(100); 84 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 85 | HAL_Delay(2); 86 | HAL_SPI_Transmit(spi, "\x68\x00", 2, 100); 87 | HAL_Delay(2); 88 | // CS 89 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 90 | // HAL_Delay(100); 91 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 92 | HAL_Delay(2); 93 | HAL_SPI_Transmit(spi, "\xd0\x00", 2, 100); 94 | HAL_Delay(2); 95 | // CS 96 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 97 | // HAL_Delay(100); 98 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 99 | HAL_Delay(2); 100 | HAL_SPI_Transmit(spi, "\x1b\x00", 2, 100); 101 | 102 | HAL_Delay(2); 103 | // CS 104 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 105 | // HAL_Delay(100); 106 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 107 | HAL_Delay(2); 108 | HAL_SPI_Transmit(spi, "\xe0\x00", 2, 100); 109 | 110 | 111 | HAL_Delay(2); 112 | // CS 113 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 114 | // HAL_Delay(100); 115 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 116 | HAL_Delay(2); 117 | HAL_SPI_Transmit(spi, "\x6a\x80", 2, 100); 118 | 119 | HAL_Delay(2); 120 | // CS 121 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 122 | // HAL_Delay(100); 123 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 124 | HAL_Delay(2); 125 | HAL_SPI_Transmit(spi, "\x80\x00", 2, 100); 126 | HAL_Delay(2); 127 | // CS 128 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 129 | // HAL_Delay(100); 130 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); 131 | HAL_Delay(2); 132 | HAL_SPI_Transmit(spi, "\x14\x80", 2, 100); 133 | HAL_Delay(2); 134 | // CS 135 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 136 | 137 | 138 | HAL_LTDC_SetAddress(ltdc,(uint32_t) &framebuffer,0); 139 | } -------------------------------------------------------------------------------- /STM32H7B0VBTx_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** Author : Auto-generated by System Workbench for STM32 8 | ** 9 | ** Abstract : Linker script for STM32H7B0VBTx series 10 | ** 128Kbytes FLASH and 1216Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used. 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed “as is,” without any warranty 20 | ** of any kind. 21 | ** 22 | ***************************************************************************** 23 | ** @attention 24 | ** 25 | **

© COPYRIGHT(c) 2019 STMicroelectronics

26 | ** 27 | ** Redistribution and use in source and binary forms, with or without modification, 28 | ** are permitted provided that the following conditions are met: 29 | ** 1. Redistributions of source code must retain the above copyright notice, 30 | ** this list of conditions and the following disclaimer. 31 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 32 | ** this list of conditions and the following disclaimer in the documentation 33 | ** and/or other materials provided with the distribution. 34 | ** 3. Neither the name of STMicroelectronics nor the names of its contributors 35 | ** may be used to endorse or promote products derived from this software 36 | ** without specific prior written permission. 37 | ** 38 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | ** 49 | ***************************************************************************** 50 | */ 51 | 52 | /* Entry Point */ 53 | ENTRY(Reset_Handler) 54 | 55 | /* Highest address of the user mode stack */ 56 | _estack = 0x20020000; /* end of RAM */ 57 | /* Generate a link error if heap and stack don't fit into RAM */ 58 | _Min_Heap_Size = 0x200; /* required amount of heap */ 59 | _Min_Stack_Size = 0x400; /* required amount of stack */ 60 | 61 | /* Specify the memory areas */ 62 | MEMORY 63 | { 64 | ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K 65 | DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K 66 | RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 1024K 67 | FLASH (xr ) : ORIGIN = 0x8000000, LENGTH = 128K 68 | EXTFLASH (xr ) : ORIGIN = 0x90000000, LENGTH = 1024K 69 | } 70 | 71 | /* Define output sections */ 72 | SECTIONS 73 | { 74 | 75 | /* The startup code goes first into FLASH */ 76 | .isr_vector : 77 | { 78 | . = ALIGN(4); 79 | KEEP(*(.isr_vector)) /* Startup code */ 80 | . = ALIGN(4); 81 | } >DTCMRAM 82 | 83 | 84 | .lcd : 85 | { 86 | . = ALIGN(4); 87 | *(.lcd) 88 | *(.audio) 89 | . = ALIGN(4); 90 | } > DTCMRAM 91 | 92 | ._extflash : 93 | { 94 | . = ALIGN(4); 95 | _extflash = .; /* define a global symbols to point at the external flash */ 96 | } >EXTFLASH 97 | 98 | /* The program code and other data goes into FLASH */ 99 | .text : 100 | { 101 | . = ALIGN(4); 102 | *(.text) /* .text sections (code) */ 103 | *(.text*) /* .text* sections (code) */ 104 | *(.glue_7) /* glue arm to thumb code */ 105 | *(.glue_7t) /* glue thumb to arm code */ 106 | *(.eh_frame) 107 | 108 | KEEP (*(.init)) 109 | KEEP (*(.fini)) 110 | 111 | . = ALIGN(4); 112 | _etext = .; /* define a global symbols at end of code */ 113 | } >DTCMRAM 114 | 115 | /* Constant data goes into FLASH */ 116 | .rodata : 117 | { 118 | . = ALIGN(4); 119 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 120 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 121 | . = ALIGN(4); 122 | } >DTCMRAM 123 | 124 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 125 | .ARM : { 126 | __exidx_start = .; 127 | *(.ARM.exidx*) 128 | __exidx_end = .; 129 | } >DTCMRAM 130 | 131 | .preinit_array : 132 | { 133 | PROVIDE_HIDDEN (__preinit_array_start = .); 134 | KEEP (*(.preinit_array*)) 135 | PROVIDE_HIDDEN (__preinit_array_end = .); 136 | } >DTCMRAM 137 | .init_array : 138 | { 139 | PROVIDE_HIDDEN (__init_array_start = .); 140 | KEEP (*(SORT(.init_array.*))) 141 | KEEP (*(.init_array*)) 142 | PROVIDE_HIDDEN (__init_array_end = .); 143 | } >DTCMRAM 144 | .fini_array : 145 | { 146 | PROVIDE_HIDDEN (__fini_array_start = .); 147 | KEEP (*(SORT(.fini_array.*))) 148 | KEEP (*(.fini_array*)) 149 | PROVIDE_HIDDEN (__fini_array_end = .); 150 | } >DTCMRAM 151 | 152 | /* used by the startup to initialize data */ 153 | _sidata = LOADADDR(.data); 154 | 155 | /* Initialized data sections goes into RAM, load LMA copy after code */ 156 | .data : 157 | { 158 | . = ALIGN(4); 159 | _sdata = .; /* create a global symbol at data start */ 160 | *(.data) /* .data sections */ 161 | *(.data*) /* .data* sections */ 162 | 163 | . = ALIGN(4); 164 | _edata = .; /* define a global symbol at data end */ 165 | } >DTCMRAM 166 | 167 | 168 | /* Uninitialized data section */ 169 | . = ALIGN(4); 170 | .bss : 171 | { 172 | /* This is used by the startup in order to initialize the .bss secion */ 173 | _sbss = .; /* define a global symbol at bss start */ 174 | __bss_start__ = _sbss; 175 | *(.bss) 176 | *(.bss*) 177 | *(COMMON) 178 | 179 | . = ALIGN(4); 180 | _ebss = .; /* define a global symbol at bss end */ 181 | __bss_end__ = _ebss; 182 | } >DTCMRAM 183 | 184 | /* User_heap_stack section, used to check that there is enough RAM left */ 185 | ._user_heap_stack : 186 | { 187 | . = ALIGN(8); 188 | PROVIDE ( end = . ); 189 | PROVIDE ( _end = . ); 190 | . = . + _Min_Heap_Size; 191 | . = . + _Min_Stack_Size; 192 | . = ALIGN(8); 193 | } >DTCMRAM 194 | 195 | 196 | 197 | /* Remove information from the standard libraries */ 198 | /DISCARD/ : 199 | { 200 | libc.a ( * ) 201 | libm.a ( * ) 202 | libgcc.a ( * ) 203 | } 204 | 205 | .ARM.attributes 0 : { *(.ARM.attributes) } 206 | } 207 | 208 | 209 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ########################################################################################################################## 2 | # File automatically-generated by tool: [projectgenerator] version: [3.11.0-B13] date: [Fri Nov 27 17:05:07 CET 2020] 3 | ########################################################################################################################## 4 | 5 | # ------------------------------------------------ 6 | # Generic Makefile (based on gcc) 7 | # 8 | # ChangeLog : 9 | # 2017-02-10 - Several enhancements + project update mode 10 | # 2015-07-22 - first version 11 | # ------------------------------------------------ 12 | 13 | ###################################### 14 | # target 15 | ###################################### 16 | TARGET = gw_base 17 | 18 | 19 | ###################################### 20 | # building variables 21 | ###################################### 22 | # debug build? 23 | DEBUG = 1 24 | # optimization 25 | OPT = -Og 26 | 27 | 28 | ####################################### 29 | # paths 30 | ####################################### 31 | # Build path 32 | BUILD_DIR = build 33 | 34 | ###################################### 35 | # source 36 | ###################################### 37 | # C sources 38 | C_SOURCES = \ 39 | Core/Src/flash.c \ 40 | Core/Src/lcd.c \ 41 | Core/Src/buttons.c \ 42 | Core/Src/main.c \ 43 | Core/Src/stm32h7xx_it.c \ 44 | Core/Src/stm32h7xx_hal_msp.c \ 45 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ 46 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c \ 47 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c \ 48 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ 49 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \ 50 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \ 51 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \ 52 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \ 53 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \ 54 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \ 55 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \ 56 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \ 57 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \ 58 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \ 59 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \ 60 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \ 61 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \ 62 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \ 63 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \ 64 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \ 65 | Core/Src/system_stm32h7xx.c \ 66 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c \ 67 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c \ 68 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c \ 69 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c \ 70 | Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c 71 | 72 | # ASM sources 73 | ASM_SOURCES = \ 74 | startup_stm32h7b0xx.s 75 | 76 | 77 | ####################################### 78 | # binaries 79 | ####################################### 80 | PREFIX = arm-none-eabi- 81 | # The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) 82 | # either it can be added to the PATH environment variable. 83 | ifdef GCC_PATH 84 | CC = $(GCC_PATH)/$(PREFIX)gcc 85 | AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp 86 | CP = $(GCC_PATH)/$(PREFIX)objcopy 87 | SZ = $(GCC_PATH)/$(PREFIX)size 88 | else 89 | CC = $(PREFIX)gcc 90 | AS = $(PREFIX)gcc -x assembler-with-cpp 91 | CP = $(PREFIX)objcopy 92 | SZ = $(PREFIX)size 93 | endif 94 | HEX = $(CP) -O ihex 95 | BIN = $(CP) -O binary -S 96 | 97 | ####################################### 98 | # CFLAGS 99 | ####################################### 100 | # cpu 101 | CPU = -mcpu=cortex-m7 102 | 103 | # fpu 104 | FPU = -mfpu=fpv5-d16 105 | 106 | # float-abi 107 | FLOAT-ABI = -mfloat-abi=hard 108 | 109 | # mcu 110 | MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) 111 | 112 | # macros for gcc 113 | # AS defines 114 | AS_DEFS = 115 | 116 | # C defines 117 | C_DEFS = \ 118 | -DUSE_HAL_DRIVER \ 119 | -DSTM32H7B0xx 120 | 121 | 122 | # AS includes 123 | AS_INCLUDES = 124 | 125 | # C includes 126 | C_INCLUDES = \ 127 | -ICore/chocdoom \ 128 | -ICore/Inc \ 129 | -IDrivers/STM32H7xx_HAL_Driver/Inc \ 130 | -IDrivers/STM32H7xx_HAL_Driver/Inc/Legacy \ 131 | -IDrivers/CMSIS/Device/ST/STM32H7xx/Include \ 132 | -IDrivers/CMSIS/Include 133 | 134 | 135 | # compile gcc flags 136 | ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 137 | 138 | CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 139 | 140 | ifeq ($(DEBUG), 1) 141 | CFLAGS += -g -gdwarf-2 -O0 142 | endif 143 | 144 | 145 | # Generate dependency information 146 | CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" 147 | 148 | 149 | ####################################### 150 | # LDFLAGS 151 | ####################################### 152 | # link script 153 | LDSCRIPT = STM32H7B0VBTx_FLASH.ld 154 | 155 | # libraries 156 | LIBS = -lc -lm -lnosys 157 | LIBDIR = 158 | LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections 159 | 160 | # default action: build all 161 | all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin 162 | 163 | 164 | ####################################### 165 | # build the application 166 | ####################################### 167 | # list of objects 168 | OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) 169 | vpath %.c $(sort $(dir $(C_SOURCES))) 170 | # list of ASM program objects 171 | OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) 172 | vpath %.s $(sort $(dir $(ASM_SOURCES))) 173 | 174 | $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 175 | $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ 176 | 177 | $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) 178 | $(AS) -c $(CFLAGS) $< -o $@ 179 | 180 | $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile 181 | $(CC) $(OBJECTS) $(LDFLAGS) -o $@ 182 | $(SZ) $@ 183 | 184 | $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 185 | $(HEX) $< $@ 186 | 187 | $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 188 | $(BIN) $< $@ 189 | 190 | $(BUILD_DIR): 191 | mkdir $@ 192 | 193 | 194 | 195 | OPENOCD ?= openocd 196 | OCDIFACE ?= interface/stlink.cfg 197 | 198 | flash: $(BUILD_DIR)/$(TARGET).bin 199 | dd if=$(BUILD_DIR)/$(TARGET).bin of=$(BUILD_DIR)/$(TARGET)_flash.bin bs=1024 count=128 200 | $(OPENOCD) -f $(OCDIFACE) -c "transport select hla_swd" -f "target/stm32h7x.cfg" -c "reset_config none; program $(BUILD_DIR)/$(TARGET)_flash.bin 0x08000000 verify reset exit" 201 | 202 | .PHONY: flash 203 | 204 | GDB ?= $(PREFIX)gdb 205 | 206 | debug: $(BUILD_DIR)/$(TARGET).elf 207 | $(GDB) $< -ex "target extended-remote :3333" 208 | .PHONY: debug 209 | 210 | 211 | ####################################### 212 | # clean up 213 | ####################################### 214 | clean: 215 | -rm -fR $(BUILD_DIR) 216 | 217 | ####################################### 218 | # dependencies 219 | ####################################### 220 | -include $(wildcard $(BUILD_DIR)/*.d) 221 | 222 | # *** EOF *** 223 | -------------------------------------------------------------------------------- /Core/Src/stm32h7xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32h7xx_it.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* Private user code ---------------------------------------------------------*/ 54 | /* USER CODE BEGIN 0 */ 55 | 56 | /* USER CODE END 0 */ 57 | 58 | /* External variables --------------------------------------------------------*/ 59 | extern OSPI_HandleTypeDef hospi1; 60 | extern DMA_HandleTypeDef hdma_sai1_a; 61 | extern SAI_HandleTypeDef hsai_BlockA1; 62 | /* USER CODE BEGIN EV */ 63 | 64 | /* USER CODE END EV */ 65 | 66 | /******************************************************************************/ 67 | /* Cortex Processor Interruption and Exception Handlers */ 68 | /******************************************************************************/ 69 | /** 70 | * @brief This function handles Non maskable interrupt. 71 | */ 72 | void NMI_Handler(void) 73 | { 74 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 75 | 76 | /* USER CODE END NonMaskableInt_IRQn 0 */ 77 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 78 | 79 | /* USER CODE END NonMaskableInt_IRQn 1 */ 80 | } 81 | 82 | /** 83 | * @brief This function handles Hard fault interrupt. 84 | */ 85 | void HardFault_Handler(void) 86 | { 87 | /* USER CODE BEGIN HardFault_IRQn 0 */ 88 | 89 | /* USER CODE END HardFault_IRQn 0 */ 90 | while (1) 91 | { 92 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 93 | /* USER CODE END W1_HardFault_IRQn 0 */ 94 | } 95 | } 96 | 97 | /** 98 | * @brief This function handles Memory management fault. 99 | */ 100 | void MemManage_Handler(void) 101 | { 102 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 103 | 104 | /* USER CODE END MemoryManagement_IRQn 0 */ 105 | while (1) 106 | { 107 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 108 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 109 | } 110 | } 111 | 112 | /** 113 | * @brief This function handles Pre-fetch fault, memory access fault. 114 | */ 115 | void BusFault_Handler(void) 116 | { 117 | /* USER CODE BEGIN BusFault_IRQn 0 */ 118 | 119 | /* USER CODE END BusFault_IRQn 0 */ 120 | while (1) 121 | { 122 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 123 | /* USER CODE END W1_BusFault_IRQn 0 */ 124 | } 125 | } 126 | 127 | /** 128 | * @brief This function handles Undefined instruction or illegal state. 129 | */ 130 | void UsageFault_Handler(void) 131 | { 132 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 133 | 134 | /* USER CODE END UsageFault_IRQn 0 */ 135 | while (1) 136 | { 137 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 138 | /* USER CODE END W1_UsageFault_IRQn 0 */ 139 | } 140 | } 141 | 142 | /** 143 | * @brief This function handles System service call via SWI instruction. 144 | */ 145 | void SVC_Handler(void) 146 | { 147 | /* USER CODE BEGIN SVCall_IRQn 0 */ 148 | 149 | /* USER CODE END SVCall_IRQn 0 */ 150 | /* USER CODE BEGIN SVCall_IRQn 1 */ 151 | 152 | /* USER CODE END SVCall_IRQn 1 */ 153 | } 154 | 155 | /** 156 | * @brief This function handles Debug monitor. 157 | */ 158 | void DebugMon_Handler(void) 159 | { 160 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 161 | 162 | /* USER CODE END DebugMonitor_IRQn 0 */ 163 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 164 | 165 | /* USER CODE END DebugMonitor_IRQn 1 */ 166 | } 167 | 168 | /** 169 | * @brief This function handles Pendable request for system service. 170 | */ 171 | void PendSV_Handler(void) 172 | { 173 | /* USER CODE BEGIN PendSV_IRQn 0 */ 174 | 175 | /* USER CODE END PendSV_IRQn 0 */ 176 | /* USER CODE BEGIN PendSV_IRQn 1 */ 177 | 178 | /* USER CODE END PendSV_IRQn 1 */ 179 | } 180 | 181 | /** 182 | * @brief This function handles System tick timer. 183 | */ 184 | void SysTick_Handler(void) 185 | { 186 | /* USER CODE BEGIN SysTick_IRQn 0 */ 187 | 188 | /* USER CODE END SysTick_IRQn 0 */ 189 | HAL_IncTick(); 190 | /* USER CODE BEGIN SysTick_IRQn 1 */ 191 | 192 | /* USER CODE END SysTick_IRQn 1 */ 193 | } 194 | 195 | /******************************************************************************/ 196 | /* STM32H7xx Peripheral Interrupt Handlers */ 197 | /* Add here the Interrupt Handlers for the used peripherals. */ 198 | /* For the available peripheral interrupt handler names, */ 199 | /* please refer to the startup file (startup_stm32h7xx.s). */ 200 | /******************************************************************************/ 201 | 202 | /** 203 | * @brief This function handles DMA1 stream0 global interrupt. 204 | */ 205 | void DMA1_Stream0_IRQHandler(void) 206 | { 207 | /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ 208 | 209 | /* USER CODE END DMA1_Stream0_IRQn 0 */ 210 | HAL_DMA_IRQHandler(&hdma_sai1_a); 211 | /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ 212 | 213 | /* USER CODE END DMA1_Stream0_IRQn 1 */ 214 | } 215 | 216 | /** 217 | * @brief This function handles SAI1 global interrupt. 218 | */ 219 | void SAI1_IRQHandler(void) 220 | { 221 | /* USER CODE BEGIN SAI1_IRQn 0 */ 222 | 223 | /* USER CODE END SAI1_IRQn 0 */ 224 | HAL_SAI_IRQHandler(&hsai_BlockA1); 225 | /* USER CODE BEGIN SAI1_IRQn 1 */ 226 | 227 | /* USER CODE END SAI1_IRQn 1 */ 228 | } 229 | 230 | /** 231 | * @brief This function handles OCTOSPI1 global interrupt. 232 | */ 233 | void OCTOSPI1_IRQHandler(void) 234 | { 235 | /* USER CODE BEGIN OCTOSPI1_IRQn 0 */ 236 | 237 | /* USER CODE END OCTOSPI1_IRQn 0 */ 238 | HAL_OSPI_IRQHandler(&hospi1); 239 | /* USER CODE BEGIN OCTOSPI1_IRQn 1 */ 240 | 241 | /* USER CODE END OCTOSPI1_IRQn 1 */ 242 | } 243 | 244 | /* USER CODE BEGIN 1 */ 245 | 246 | /* USER CODE END 1 */ 247 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 248 | -------------------------------------------------------------------------------- /Core/Src/flash.c: -------------------------------------------------------------------------------- 1 | #include "flash.h" 2 | 3 | static quad_mode_t g_quad_mode = SPI_MODE; 4 | static spi_chip_vendor_t g_vendor = VENDOR_MX; 5 | 6 | void set_cmd_lines(OSPI_RegularCmdTypeDef *cmd, quad_mode_t quad_mode, spi_chip_vendor_t vendor, uint8_t has_address, uint8_t has_data) 7 | { 8 | if (quad_mode == SPI_MODE) { 9 | cmd->InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; 10 | cmd->AddressMode = has_address ? HAL_OSPI_ADDRESS_1_LINE : HAL_OSPI_ADDRESS_NONE; 11 | cmd->DataMode = has_data ? HAL_OSPI_DATA_1_LINE : HAL_OSPI_DATA_NONE; 12 | } else { 13 | // QUAD_MODE 14 | if (vendor == VENDOR_MX) { 15 | cmd->InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; 16 | cmd->AddressMode = has_address ? HAL_OSPI_ADDRESS_4_LINES : HAL_OSPI_ADDRESS_NONE; 17 | cmd->DataMode = has_data ? HAL_OSPI_DATA_4_LINES : HAL_OSPI_DATA_NONE; 18 | } else { 19 | // VENDOR_ISSI 20 | cmd->InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES; 21 | cmd->AddressMode = has_address ? HAL_OSPI_ADDRESS_4_LINES : HAL_OSPI_ADDRESS_NONE; 22 | cmd->DataMode = has_data ? HAL_OSPI_DATA_4_LINES : HAL_OSPI_DATA_NONE; 23 | } 24 | } 25 | } 26 | 27 | void OSPI_ReadBytes(OSPI_HandleTypeDef *hospi, uint8_t instruction, uint8_t *data, size_t len) 28 | { 29 | OSPI_RegularCmdTypeDef sCommand; 30 | memset(&sCommand, 0x0, sizeof(sCommand)); 31 | sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; 32 | sCommand.FlashId = 0; 33 | sCommand.Instruction = instruction; 34 | sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS; 35 | 36 | sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; 37 | sCommand.NbData = len; 38 | sCommand.DummyCycles = 0; 39 | sCommand.DQSMode = HAL_OSPI_DQS_DISABLE; 40 | sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; 41 | sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; 42 | 43 | if (g_vendor == VENDOR_MX) { 44 | set_cmd_lines(&sCommand, SPI_MODE, g_vendor, 0, 1); 45 | } else if (g_vendor == VENDOR_ISSI) { 46 | set_cmd_lines(&sCommand, g_quad_mode, g_vendor, 0, 1); 47 | } 48 | 49 | if (HAL_OSPI_Command(hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 50 | { 51 | Error_Handler(); 52 | } 53 | 54 | if(HAL_OSPI_Receive(hospi, data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { 55 | Error_Handler(); 56 | } 57 | } 58 | 59 | void OSPI_WriteBytes(OSPI_HandleTypeDef *hospi, uint8_t instruction, uint8_t dummy_cycles, uint8_t *data, size_t len, quad_mode_t quad_mode) 60 | { 61 | OSPI_RegularCmdTypeDef sCommand; 62 | memset(&sCommand, 0x0, sizeof(sCommand)); 63 | sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; 64 | sCommand.FlashId = 0; 65 | sCommand.Instruction = instruction; 66 | sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS; 67 | 68 | sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; 69 | sCommand.NbData = len; 70 | sCommand.DummyCycles = dummy_cycles; 71 | sCommand.DQSMode = HAL_OSPI_DQS_DISABLE; 72 | sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; 73 | sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; 74 | 75 | set_cmd_lines(&sCommand, quad_mode, g_vendor, 0, len > 0); 76 | 77 | if (HAL_OSPI_Command(hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 78 | { 79 | Error_Handler(); 80 | } 81 | 82 | if (len > 0) { 83 | if(HAL_OSPI_Transmit(hospi, data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { 84 | Error_Handler(); 85 | } 86 | } 87 | } 88 | 89 | void OSPI_Init(OSPI_HandleTypeDef *hospi, quad_mode_t quad_mode, spi_chip_vendor_t vendor) 90 | { 91 | if (vendor == VENDOR_ISSI) { 92 | // Disable quad mode (will do nothing in SPI mode) 93 | OSPI_WriteBytes(hospi, 0xf5, 0, NULL, 0, QUAD_MODE); 94 | HAL_Delay(2); 95 | } 96 | 97 | // Enable Reset 98 | OSPI_WriteBytes(hospi, 0x66, 0, NULL, 0, SPI_MODE); 99 | HAL_Delay(2); 100 | 101 | // Reset 102 | OSPI_WriteBytes(hospi, 0x99, 0, NULL, 0, SPI_MODE); 103 | HAL_Delay(20); 104 | 105 | g_vendor = vendor; 106 | g_quad_mode = quad_mode; 107 | 108 | if (quad_mode == QUAD_MODE) { 109 | if (vendor == VENDOR_MX) { 110 | // WRSR - Write Status Register 111 | // Set Quad Enable bit (6) in status register. Other bits = 0. 112 | uint8_t wr_status = 1<<6; 113 | uint8_t rd_status = 0xff; 114 | 115 | // Enable write to be allowed to change the status register 116 | OSPI_NOR_WriteEnable(hospi); 117 | 118 | // Loop until rd_status is updated 119 | while ((rd_status & wr_status) != wr_status) { 120 | OSPI_WriteBytes(hospi, 0x01, 0, wr_status, 1, SPI_MODE); 121 | OSPI_ReadBytes(hospi, 0x05, &rd_status, 1); 122 | } 123 | } else if (vendor == VENDOR_ISSI) { 124 | // Enable QPI mode 125 | OSPI_WriteBytes(hospi, 0x35, 0, NULL, 0, SPI_MODE); 126 | } 127 | } 128 | } 129 | 130 | void OSPI_ChipErase(OSPI_HandleTypeDef *hospi) 131 | { 132 | uint8_t status; 133 | 134 | // Send Chip Erase command 135 | OSPI_WriteBytes(hospi, 0x60, 0, NULL, 0, g_quad_mode); 136 | 137 | // Wait for Write In Progress Bit to be zero 138 | do { 139 | OSPI_ReadBytes(hospi, 0x05, &status, 1); 140 | HAL_Delay(100); 141 | } while((status & 0x01) == 0x01); 142 | } 143 | 144 | 145 | 146 | void _OSPI_Program(OSPI_HandleTypeDef *hospi, uint32_t address, uint8_t *buffer, size_t buffer_size) 147 | { 148 | uint8_t status; 149 | OSPI_RegularCmdTypeDef sCommand; 150 | 151 | memset(&sCommand, 0x0, sizeof(sCommand)); 152 | sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; 153 | sCommand.FlashId = 0; 154 | sCommand.Instruction = 0x02; // PP 155 | sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS; 156 | sCommand.Address = address; 157 | sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS; 158 | sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; 159 | sCommand.NbData = buffer_size; 160 | sCommand.DummyCycles = 0; 161 | sCommand.DQSMode = HAL_OSPI_DQS_DISABLE; 162 | sCommand.SIOOMode = HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD; 163 | sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; 164 | 165 | // For MX vendor in quad mode, use the 4PP command 166 | if (g_quad_mode == QUAD_MODE && g_vendor == VENDOR_MX) { 167 | sCommand.Instruction = 0x38; // 4PP 168 | } 169 | 170 | set_cmd_lines(&sCommand, g_quad_mode, g_vendor, 1, 1); 171 | 172 | if(buffer_size > 256) { 173 | Error_Handler(); 174 | } 175 | 176 | if (HAL_OSPI_Command(hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 177 | { 178 | Error_Handler(); 179 | } 180 | 181 | if(HAL_OSPI_Transmit(hospi, buffer, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { 182 | Error_Handler(); 183 | } 184 | 185 | // Wait for Write In Progress Bit to be zero 186 | do { 187 | OSPI_ReadBytes(hospi, 0x05, &status, 1); 188 | } while((status & 0x01) == 0x01); 189 | } 190 | 191 | void OSPI_Program(OSPI_HandleTypeDef *hospi, uint32_t address, uint8_t *buffer, size_t buffer_size) { 192 | unsigned iterations = buffer_size / 256; 193 | unsigned dest_page = address / 256; 194 | 195 | for(int i = 0; i < iterations; i++) { 196 | OSPI_NOR_WriteEnable(hospi); 197 | _OSPI_Program(hospi, (i + dest_page) * 256, buffer + (i * 256), buffer_size > 256 ? 256 : buffer_size); 198 | buffer_size -= 256; 199 | } 200 | } 201 | 202 | 203 | void _OSPI_Read(OSPI_HandleTypeDef *hospi, uint32_t address, uint8_t *buffer, size_t buffer_size) 204 | { 205 | uint8_t status; 206 | OSPI_RegularCmdTypeDef sCommand; 207 | 208 | memset(&sCommand, 0x0, sizeof(sCommand)); 209 | sCommand.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; 210 | sCommand.FlashId = 0; 211 | sCommand.Instruction = 0x0B; // FAST_READ 212 | sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS; 213 | sCommand.Address = address; 214 | sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS; 215 | sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; 216 | sCommand.NbData = buffer_size; 217 | sCommand.DummyCycles = 8; 218 | sCommand.DQSMode = HAL_OSPI_DQS_DISABLE; 219 | sCommand.SIOOMode = HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD; 220 | sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE; 221 | 222 | set_cmd_lines(&sCommand, g_quad_mode, g_vendor, 1, 1); 223 | 224 | if(buffer_size > 256) { 225 | Error_Handler(); 226 | } 227 | 228 | if (HAL_OSPI_Command(hospi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 229 | { 230 | Error_Handler(); 231 | } 232 | 233 | if(HAL_OSPI_Receive(hospi, buffer, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { 234 | Error_Handler(); 235 | } 236 | } 237 | 238 | void OSPI_Read(OSPI_HandleTypeDef *hospi, uint32_t address, uint8_t *buffer, size_t buffer_size) 239 | { 240 | unsigned iterations = buffer_size / 256; 241 | unsigned dest_page = address / 256; 242 | 243 | for(int i = 0; i < iterations; i++) { 244 | _OSPI_Read(hospi, (i + dest_page) * 256, buffer + (i * 256), buffer_size > 256 ? 256 : buffer_size); 245 | buffer_size -= 256; 246 | } 247 | } 248 | 249 | void OSPI_NOR_WriteEnable(OSPI_HandleTypeDef *hospi) 250 | { 251 | OSPI_WriteBytes(hospi, 0x06, 0, NULL, 0, g_quad_mode); 252 | } 253 | 254 | 255 | void OSPI_EnableMemoryMappedMode(OSPI_HandleTypeDef *spi) { 256 | OSPI_MemoryMappedTypeDef sMemMappedCfg; 257 | 258 | OSPI_RegularCmdTypeDef sCommand = { 259 | .Instruction = 0x0b, // FAST READ 260 | .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD, 261 | .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE, 262 | .OperationType = HAL_OSPI_OPTYPE_READ_CFG, 263 | .FlashId = 0, 264 | .InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE, 265 | .InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS, 266 | .AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE, 267 | .DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE, 268 | .DQSMode = HAL_OSPI_DQS_DISABLE, 269 | .AddressSize = HAL_OSPI_ADDRESS_24_BITS, 270 | .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD, 271 | .DummyCycles = 8, 272 | .AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_8_BITS, 273 | .AlternateBytes = 0x00, 274 | .NbData = 0, 275 | .AlternateBytes = 0x00, 276 | }; 277 | 278 | set_cmd_lines(&sCommand, g_quad_mode, g_vendor, 1, 1); 279 | 280 | if (g_quad_mode) { 281 | sCommand.Instruction = 0xeb; 282 | sCommand.DummyCycles = 6; 283 | } 284 | 285 | /* Memory-mapped mode configuration for Linear burst read operations */ 286 | if (HAL_OSPI_Command(spi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != 287 | HAL_OK) { 288 | Error_Handler(); 289 | } 290 | 291 | // Use read instruction for write (in order to not alter the flash by accident) 292 | sCommand.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG; 293 | if (HAL_OSPI_Command(spi, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != 294 | HAL_OK) { 295 | Error_Handler(); 296 | } 297 | 298 | /*Disable timeout counter for memory mapped mode*/ 299 | sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE; 300 | sMemMappedCfg.TimeOutPeriod = 0; 301 | /*Enable memory mapped mode*/ 302 | if (HAL_OSPI_MemoryMapped(spi, &sMemMappedCfg) != HAL_OK) { 303 | Error_Handler(); 304 | } 305 | } -------------------------------------------------------------------------------- /gw_base.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | SPI2.VirtualType=VM_MASTER 3 | PB10.Mode=RGB666 4 | PC7.Locked=true 5 | PD8.Locked=true 6 | RCC.RTCFreq_Value=32000 7 | PD0.Locked=true 8 | PD4.Locked=true 9 | RCC.CpuClockFreq_Value=280000000 10 | PB13.Signal=SPI2_SCK 11 | PA5.PinState=GPIO_PIN_SET 12 | PinOutPanel.RotationAngle=0 13 | SAI1.Instance-SAI_A_Master=SAI$Index_Block_A 14 | RCC.MCO1PinFreq_Value=64000000 15 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 16 | RCC.AHB4Freq_Value=280000000 17 | RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_CLKP 18 | RCC.LPTIM1Freq_Value=140000000 19 | OCTOSPI1.ChipSelectBoundary=0 20 | RCC.SAI2BFreq_Value=280000000 21 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false 22 | PD15.GPIOParameters=GPIO_PuPd,GPIO_Label 23 | RCC.I2C4Freq_Value=140000000 24 | PE2.Mode=OCTOSPI1_IOL_Port1L 25 | PD4.Signal=GPIO_Output 26 | PC7.Signal=LTDC_G6 27 | PB12.PinState=GPIO_PIN_SET 28 | RCC.DIVQ3Freq_Value=72000000 29 | PD0.Signal=GPIO_Input 30 | PD8.Signal=GPIO_Output 31 | PE5.Signal=SAI1_SCK_A 32 | ProjectManager.ProjectBuild=false 33 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 34 | PB2.Signal=OCTOSPIM_P1_CLK 35 | PA8.Locked=true 36 | PA4.Locked=true 37 | RCC.DIVM3=4 38 | PC1.GPIO_PuPd=GPIO_PULLUP 39 | VP_OCTOSPI1_VS_quad.Mode=quad_mode 40 | RCC.DIVM2=25 41 | PD1.GPIOParameters=PinState 42 | RCC.DIVM1=16 43 | RCC.DFSDM2Freq_Value=140000000 44 | ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0 45 | MxDb.Version=DB.6.0.10 46 | PE15.Locked=true 47 | LTDC.IPParameters=HSync,HBP,ActiveW,PCPolarity,WindowX1_L0,WindowY1_L0,Layers,PixelFormat_L0,Alpha0_L0,Alpha_L0,FBStartAdress_L0,ImageWidth_L0,ImageHeight_L0,Green_L0,VSync,ActiveH,VBP,HFP,VFP 48 | LTDC.PixelFormat_L0=LTDC_PIXEL_FORMAT_RGB565 49 | ProjectManager.BackupPrevious=false 50 | RCC.FMCFreq_Value=280000000 51 | RCC.SAI1CLockSelection=RCC_SAI1CLKSOURCE_PLL2 52 | Dma.SAI1_A.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING 53 | RCC.DFSDM2ACLkFreq_Value=140000000 54 | PB14.Mode=RGB666 55 | RCC.USART16Freq_Value=140000000 56 | PC9.Mode=RGB666 57 | SPI2.CalculateBaudRate=4.0 MBits/s 58 | PE2.Signal=OCTOSPIM_P1_IO2 59 | PA8.Signal=LTDC_R6 60 | PD14.GPIO_PuPd=GPIO_PULLUP 61 | PE13.Mode=RGB666 62 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false 63 | NVIC.SAI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true 64 | PD3.Mode=RGB666 65 | RCC.DIVR2Freq_Value=98304000 66 | LTDC.HSync=10 67 | ProjectManager.HalAssertFull=false 68 | RCC.DIVP2Freq_Value=98304000 69 | RCC.MCO2PinFreq_Value=280000000 70 | Mcu.Package=LQFP100 71 | PB1.Signal=OCTOSPIM_P1_IO0 72 | PA5.Locked=true 73 | SPI2.Mode=SPI_MODE_MASTER 74 | RCC.PLL3FRACN=0 75 | PD11.Locked=true 76 | PD12.Signal=OCTOSPIM_P1_IO1 77 | PD5.GPIOParameters=GPIO_PuPd,GPIO_Label 78 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 79 | PA10.Signal=LTDC_B4 80 | RCC.DFSDMFreq_Value=140000000 81 | PA5.GPIOParameters=PinState 82 | Dma.SAI1_A.0.SyncSignalID=NONE 83 | SAI1.VirtualMode-SAI_A_Master=VM_MASTER 84 | RCC.TraceFreq_Value=64000000 85 | LTDC.VSync=2 86 | RCC.APB4Freq_Value=140000000 87 | RCC.CECFreq_Value=32000 88 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 89 | RCC.LPUART1Freq_Value=140000000 90 | PB13.Mode=TX_Only_Simplex_Unidirect_Master 91 | PE6.Locked=true 92 | PD9.GPIO_PuPd=GPIO_PULLUP 93 | PD5.Locked=true 94 | PD15.Signal=GPIO_Input 95 | ProjectManager.CustomerFirmwarePackage= 96 | RCC.VCO3OutputFreq_Value=144000000 97 | PA6.GPIOParameters=PinState 98 | ProjectManager.ProjectFileName=gw_base.ioc 99 | PD9.GPIO_Label=BTN_A 100 | Mcu.PinsNb=53 101 | VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Mode=SAI_A_BASIC 102 | PC13.Locked=true 103 | PC13.Signal=GPIO_Input 104 | RCC.SWPMI1Freq_Value=140000000 105 | PD3.Signal=LTDC_G7 106 | PC6.Signal=LTDC_HSYNC 107 | PD1.Signal=GPIO_Output 108 | VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC.Signal=SAI1_VP_$IpInstance_SAIA_SAI_BASIC 109 | RCC.DIVP2=5 110 | PA6.PinState=GPIO_PIN_SET 111 | PC0.Signal=LTDC_G2 112 | PB14.Locked=true 113 | RCC.QSPIFreq_Value=64000000 114 | PD6.Mode=RGB666 115 | SAI1.RealAudioFreq-SAI_A_Master=48.0 KHz 116 | LTDC.ImageWidth_L0=320 117 | PD10.Signal=LTDC_B3 118 | PD4.PinState=GPIO_PIN_SET 119 | RCC.USART234578Freq_Value=140000000 120 | PA11.Locked=true 121 | RCC.Tim1OutputFreq_Value=280000000 122 | RCC.CDPPRE1=RCC_APB1_DIV2 123 | RCC.CDPPRE2=RCC_APB2_DIV2 124 | RCC.SPI123Freq_Value=64000000 125 | PB11.Mode=RGB666 126 | Mcu.Pin51=VP_SAI1_VP_$IpInstance_SAIA_SAI_BASIC 127 | Dma.SAI1_A.0.RequestNumber=1 128 | Mcu.Pin52=VP_SYS_VS_Systick 129 | Mcu.Pin50=VP_OCTOSPI1_VS_quad 130 | PC6.Mode=RGB666 131 | PC6.Locked=true 132 | PA9.Signal=LTDC_R5 133 | RCC.DIVN3=9 134 | RCC.DIVN2=192 135 | RCC.DIVN1=140 136 | PB5.Locked=true 137 | Mcu.Pin48=PB5 138 | Mcu.Pin49=PB8 139 | Mcu.Pin46=PD5 140 | Mcu.Pin47=PD6 141 | PB10.Signal=LTDC_G4 142 | PB14.Signal=LTDC_CLK 143 | PA5.Signal=GPIO_Output 144 | Mcu.Pin40=PC10 145 | Mcu.Pin41=PD0 146 | Mcu.Pin44=PD3 147 | Mcu.Pin45=PD4 148 | Mcu.Pin42=PD1 149 | Mcu.Pin43=PD2 150 | ProjectManager.LastFirmware=true 151 | Dma.SAI1_A.0.PeriphInc=DMA_PINC_DISABLE 152 | RCC.AHB12Freq_Value=280000000 153 | PA1.Mode=OCTOSPI1_IOL_Port1L 154 | PE6.Mode=SAI_A_Master 155 | PE15.Signal=LTDC_R7 156 | Mcu.Pin37=PA9 157 | Mcu.Pin38=PA10 158 | Mcu.Pin35=PC9 159 | Mcu.Pin36=PA8 160 | Mcu.Pin39=PA11 161 | SAI1.MckOutput=SAI_MCK_OUTPUT_DISABLE 162 | RCC.RNGFreq_Value=48000000 163 | Mcu.Pin30=PD12 164 | Mcu.Pin33=PC6 165 | Mcu.Pin34=PC7 166 | Mcu.Pin31=PD14 167 | Mcu.Pin32=PD15 168 | PA9.Locked=true 169 | Dma.SAI1_A.0.SyncRequestNumber=1 170 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false 171 | RCC.CDPPRE=RCC_APB3_DIV2 172 | ProjectManager.FreePins=false 173 | RCC.LPTIM2Freq_Value=140000000 174 | OCTOSPI1.FifoThreshold=4 175 | Mcu.Pin26=PD8 176 | Mcu.Pin27=PD9 177 | Mcu.Pin24=PB14 178 | ProjectManager.UnderRoot=false 179 | PE13.Locked=true 180 | Mcu.Pin25=PB15 181 | Mcu.Pin28=PD10 182 | Mcu.Pin29=PD11 183 | PD14.GPIOParameters=GPIO_PuPd,GPIO_Label 184 | PA4.Signal=GPIO_Output 185 | OCTOSPI1.MemoryType=HAL_OSPI_MEMTYPE_MACRONIX 186 | PB5.Signal=LTDC_B5 187 | Mcu.Pin22=PB12 188 | Mcu.Pin23=PB13 189 | Mcu.Pin20=PB10 190 | Mcu.Pin21=PB11 191 | PD12.Mode=OCTOSPI1_IOL_Port1L 192 | PD10.Locked=true 193 | PA10.Locked=true 194 | NVIC.ForceEnableDMAVector=true 195 | PD11.Signal=GPIO_Input 196 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false 197 | ProjectManager.CompilerOptimize=6 198 | PD15.Locked=true 199 | PD1.PinState=GPIO_PIN_RESET 200 | LTDC.Alpha_L0=255 201 | PA11.Signal=LTDC_R4 202 | ProjectManager.HeapSize=0x200 203 | Mcu.Pin15=PB1 204 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 205 | PB1.Mode=OCTOSPI1_IOL_Port1L 206 | Mcu.Pin16=PB2 207 | Mcu.Pin13=PC5 208 | PD0.GPIO_PuPd=GPIO_PULLUP 209 | Mcu.Pin14=PB0 210 | Mcu.Pin19=PE15 211 | RCC.LPTIM345Freq_Value=140000000 212 | ProjectManager.ComputerToolchain=false 213 | Mcu.Pin17=PE11 214 | Mcu.Pin18=PE13 215 | RCC.LTDCFreq_Value=6000000 216 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 217 | Mcu.Pin11=PA6 218 | OCTOSPI1.FreeRunningClock=HAL_OSPI_FREERUNCLK_DISABLE 219 | Mcu.Pin12=PA7 220 | PD0.GPIOParameters=GPIO_PuPd,GPIO_Label 221 | PB8.Mode=RGB666 222 | Mcu.Pin10=PA5 223 | PE2.Locked=true 224 | PE3.Signal=GPIO_Output 225 | PA8.Mode=RGB666 226 | SPI2.DataSize=SPI_DATASIZE_8BIT 227 | PD2.Signal=LTDC_B7 228 | RCC.HCLK3ClockFreq_Value=280000000 229 | RCC.DIVR3=24 230 | RCC.DIVR2=5 231 | PD1.Locked=true 232 | PB0.Signal=LTDC_R3 233 | Dma.SAI1_A.0.FIFOMode=DMA_FIFOMODE_DISABLE 234 | RCC.SAI2AFreq_Value=280000000 235 | PC0.Locked=true 236 | PC1.Signal=GPIO_Input 237 | PB12.GPIOParameters=PinState 238 | Dma.SAI1_A.0.Instance=DMA1_Stream0 239 | Dma.SAI1_A.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD 240 | SAI1.InitProtocol-SAI_A_Master=Enable 241 | LTDC.Alpha0_L0=255 242 | PE15.Mode=RGB666 243 | Mcu.Family=STM32H7 244 | Dma.SAI1_A.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber 245 | RCC.DIVQ2Freq_Value=245760000 246 | ProjectManager.MainLocation=Core/Src 247 | RCC.CDCPREFreq_Value=280000000 248 | RCC.SAI1Freq_Value=98304000 249 | RCC.CortexFreq_Value=280000000 250 | ProjectManager.KeepUserCode=true 251 | Mcu.UserName=STM32H7B0VBTx 252 | PD9.GPIOParameters=GPIO_PuPd,GPIO_Label 253 | OCTOSPI1.DeviceSize=20 254 | LTDC.HBP=51 255 | PC10.Locked=true 256 | PC10.Signal=LTDC_R2 257 | PC5.Locked=true 258 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_SPI2_Init-SPI2-false-HAL-true,6-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,7-MX_SAI1_Init-SAI1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true 259 | SAI1.VirtualProtocol-SAI_A_BASIC=VM_BASIC_PROTOCOL 260 | PD0.GPIO_Label=BTN_Up 261 | PA11.Mode=RGB666 262 | PC9.Locked=true 263 | PD6.Locked=true 264 | PD2.Locked=true 265 | RCC.VCO2OutputFreq_Value=491520000 266 | PC13.GPIO_Label=BTN_PAUSE 267 | PC1.Locked=true 268 | PB11.Signal=LTDC_G5 269 | PB15.Signal=SPI2_MOSI 270 | LTDC.PCPolarity=LTDC_PCPOLARITY_IIPC 271 | ProjectManager.StackSize=0x400 272 | RCC.VCOInput3Freq_Value=16000000 273 | Mcu.IP4=OCTOSPI1 274 | Mcu.IP5=RCC 275 | Mcu.IP2=LTDC 276 | PD11.GPIO_PuPd=GPIO_PULLUP 277 | Mcu.IP3=NVIC 278 | Mcu.IP0=CORTEX_M7 279 | Mcu.IP1=DMA 280 | OCTOSPI1.ClockPrescaler=1 281 | PE11.Mode=OCTOSPI1_Port1_NCS 282 | Mcu.UserConstants= 283 | PC1.GPIOParameters=GPIO_PuPd,GPIO_Label 284 | RCC.DIVP3Freq_Value=72000000 285 | RCC.SDMMCFreq_Value=280000000 286 | Mcu.ThirdPartyNb=0 287 | RCC.HCLKFreq_Value=280000000 288 | PD11.GPIO_Label=BTN_Left 289 | Mcu.IPNb=9 290 | ProjectManager.PreviousToolchain= 291 | RCC.SPDIFRXFreq_Value=280000000 292 | LTDC.WindowX1_L0=320 293 | PD8.GPIOParameters=PinState 294 | PD10.Mode=RGB666 295 | Mcu.Pin6=PC0 296 | Mcu.Pin7=PC1 297 | Mcu.Pin8=PA1 298 | Mcu.Pin9=PA4 299 | Dma.SAI1_A.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT 300 | SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 301 | PE3.PinState=GPIO_PIN_SET 302 | Mcu.Pin0=PE2 303 | Mcu.Pin1=PE3 304 | GPIO.groupedBy=Group By Peripherals 305 | Mcu.Pin2=PE4 306 | Mcu.Pin3=PE5 307 | Mcu.Pin4=PE6 308 | Mcu.Pin5=PC13 309 | RCC.DIVR3Freq_Value=6000000 310 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false 311 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true 312 | LTDC.VBP=6 313 | RCC.DIVP1Freq_Value=280000000 314 | PE13.Signal=LTDC_DE 315 | OCTOSPI1.ChipSelectHighTime=2 316 | PB5.Mode=RGB666 317 | File.Version=6 318 | PC13.GPIO_PuPd=GPIO_PULLUP 319 | PE3.GPIOParameters=PinState,GPIO_Label 320 | Dma.SAI1_A.0.EventEnable=DISABLE 321 | LTDC.HFP=12 322 | PE3.Locked=true 323 | PB8.Locked=true 324 | PE4.Mode=SAI_A_Master 325 | LTDC.ActiveW=320 326 | PE4.Signal=SAI1_FS_A 327 | Dma.RequestsNb=1 328 | PB0.Locked=true 329 | ProjectManager.ProjectName=gw_base 330 | RCC.APB3Freq_Value=140000000 331 | PA6.Signal=GPIO_Output 332 | PA7.Locked=true 333 | Dma.SAI1_A.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD 334 | PD5.GPIO_Label=BTN_B 335 | ProjectManager.ToolChainLocation= 336 | PD15.GPIO_PuPd=GPIO_PULLUP 337 | PD14.Locked=true 338 | RCC.DIVR1Freq_Value=280000000 339 | NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true 340 | SPI2.Direction=SPI_DIRECTION_2LINES_TXONLY 341 | PC5.Signal=GPIO_Input 342 | PD6.Signal=LTDC_B2 343 | SAI1.MonoStereoMode-SAI_A_Master=SAI_MONOMODE 344 | Dma.Request0=SAI1_A 345 | VP_OCTOSPI1_VS_quad.Signal=OCTOSPI1_VS_quad 346 | RCC.SRDPPRE=RCC_APB4_DIV2 347 | RCC.Tim2OutputFreq_Value=280000000 348 | RCC.DFSDMACLkFreq_Value=98304000 349 | PB15.Locked=true 350 | LTDC.FBStartAdress_L0=0x24000000 351 | OCTOSPI1.ClockMode=HAL_OSPI_CLOCK_MODE_0 352 | LTDC.VFP=8 353 | PD15.GPIO_Label=BTN_Right 354 | LTDC.WindowY1_L0=240 355 | PA7.Mode=RGB666 356 | PA10.Mode=RGB666 357 | ProjectManager.NoMain=false 358 | Dma.SAI1_A.0.Direction=DMA_MEMORY_TO_PERIPH 359 | Dma.SAI1_A.0.SignalID=NONE 360 | SPI2.NSSPMode=SPI_NSS_PULSE_DISABLE 361 | PC10.Mode=RGB666 362 | ProjectManager.DefaultFWLocation=true 363 | PD9.Signal=GPIO_Input 364 | PD5.Signal=GPIO_Input 365 | PB12.Locked=true 366 | ProjectManager.DeletePrevious=true 367 | PB10.Locked=true 368 | Dma.SAI1_A.0.MemInc=DMA_MINC_ENABLE 369 | PC5.GPIO_PuPd=GPIO_PULLUP 370 | RCC.FamilyName=M 371 | PC0.Mode=RGB666 372 | PD12.Locked=true 373 | RCC.SPI6Freq_Value=140000000 374 | PA9.Mode=RGB666 375 | RCC.SPI45Freq_Value=140000000 376 | PA4.PinState=GPIO_PIN_SET 377 | ProjectManager.TargetToolchain=Makefile 378 | Dma.SAI1_A.0.Mode=DMA_CIRCULAR 379 | RCC.VCO1OutputFreq_Value=560000000 380 | LTDC.ActiveH=240 381 | SAI1.ErrorAudioFreq-SAI_A_Master=0.0 % 382 | PC5.GPIOParameters=GPIO_PuPd,GPIO_Label 383 | RCC.AXIClockFreq_Value=280000000 384 | PE4.Locked=true 385 | SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,NSSPMode 386 | ProjectManager.RegisterCallBack= 387 | RCC.USBFreq_Value=280000000 388 | PE11.Signal=OCTOSPIM_P1_NCS 389 | PD3.Locked=true 390 | PA1.Signal=OCTOSPIM_P1_IO3 391 | RCC.CKPERFreq_Value=64000000 392 | SAI1.AudioFrequency-SAI_A_Master=SAI_AUDIO_FREQUENCY_48K 393 | PB1.Locked=true 394 | Dma.SAI1_A.0.Priority=DMA_PRIORITY_LOW 395 | PD2.Mode=RGB666 396 | PB0.Mode=RGB666 397 | board=custom 398 | SAI1.IPParameters=Instance-SAI_A_Master,VirtualMode-SAI_A_Master,MckOutput,RealAudioFreq-SAI_A_Master,ErrorAudioFreq-SAI_A_Master,InitProtocol-SAI_A_Master,VirtualProtocol-SAI_A_BASIC,MonoStereoMode-SAI_A_Master,AudioFrequency-SAI_A_Master 399 | PB15.Mode=TX_Only_Simplex_Unidirect_Master 400 | PD11.GPIOParameters=GPIO_PuPd,GPIO_Label 401 | RCC.VCOInput1Freq_Value=4000000 402 | RCC.APB2Freq_Value=140000000 403 | MxCube.Version=6.1.0 404 | LTDC.Layers=0 405 | PC13.GPIOParameters=GPIO_PuPd,GPIO_Label 406 | RCC.FDCANFreq_Value=280000000 407 | PE5.Mode=SAI_A_Master 408 | RCC.ADCFreq_Value=98304000 409 | PC1.GPIO_Label=BTN_GAME 410 | PD4.GPIOParameters=PinState 411 | VP_SYS_VS_Systick.Mode=SysTick 412 | PD5.GPIO_PuPd=GPIO_PULLUP 413 | PD14.GPIO_Label=BTN_Down 414 | PA4.GPIOParameters=PinState 415 | PE5.Locked=true 416 | PE6.Signal=SAI1_SD_A 417 | RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CDCPREFreq_Value,CDPPRE,CDPPRE1,CDPPRE2,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DFSDM2ACLkFreq_Value,DFSDM2Freq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL3FRACN,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1CLockSelection,SAI1Freq_Value,SAI2AFreq_Value,SAI2BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SRDPPRE,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value 418 | PE11.Locked=true 419 | ProjectManager.AskForMigrate=false 420 | Mcu.Name=STM32H7B0VBTx 421 | NVIC.OCTOSPI1_IRQn=true\:0\:0\:false\:true\:true\:1\:true\:true 422 | PB2.Locked=true 423 | Mcu.IP8=SYS 424 | PD14.Signal=GPIO_Input 425 | Mcu.IP6=SAI1 426 | Mcu.IP7=SPI2 427 | ProjectManager.CoupleFile=false 428 | RCC.SYSCLKFreq_VALUE=280000000 429 | RCC.I2C123Freq_Value=140000000 430 | PA1.Locked=true 431 | KeepUserPlacement=false 432 | PC5.GPIO_Label=BTN_TIME 433 | PB2.Mode=O1_P1_CLK 434 | RCC.QSPICLockSelection=RCC_OSPICLKSOURCE_CLKP 435 | LTDC.Green_L0=255 436 | OCTOSPI1.IPParameters=MemoryType,DeviceSize,FreeRunningClock,ClockMode,ClockPrescaler,FifoThreshold,ChipSelectHighTime,ChipSelectBoundary 437 | RCC.DIVQ1Freq_Value=280000000 438 | PB8.Signal=LTDC_B6 439 | PE3.GPIO_Label=GPIO_Speaker_enable 440 | PC9.Signal=LTDC_G3 441 | PC7.Mode=RGB666 442 | RCC.VCOInput2Freq_Value=2560000 443 | RCC.APB1Freq_Value=140000000 444 | PD9.Locked=true 445 | PD8.PinState=GPIO_PIN_SET 446 | LTDC.ImageHeight_L0=240 447 | PB11.Locked=true 448 | ProjectManager.DeviceId=STM32H7B0VBTx 449 | PB12.Signal=GPIO_Output 450 | ProjectManager.LibraryCopy=0 451 | Dma.SAI1_A.0.SyncEnable=DISABLE 452 | PA7.Signal=LTDC_VSYNC 453 | PA6.Locked=true 454 | -------------------------------------------------------------------------------- /Core/Src/system_stm32h7xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32h7xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32h7xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock, it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 22 | ****************************************************************************** 23 | * @attention 24 | * 25 | *

© Copyright (c) 2017 STMicroelectronics. 26 | * All rights reserved.

27 | * 28 | * This software component is licensed by ST under BSD 3-Clause license, 29 | * the "License"; You may not use this file except in compliance with the 30 | * License. You may obtain a copy of the License at: 31 | * opensource.org/licenses/BSD-3-Clause 32 | * 33 | ****************************************************************************** 34 | */ 35 | 36 | /** @addtogroup CMSIS 37 | * @{ 38 | */ 39 | 40 | /** @addtogroup stm32h7xx_system 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup STM32H7xx_System_Private_Includes 45 | * @{ 46 | */ 47 | 48 | #include "stm32h7xx.h" 49 | #include 50 | #if !defined (HSE_VALUE) 51 | #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ 52 | #endif /* HSE_VALUE */ 53 | 54 | #if !defined (CSI_VALUE) 55 | #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ 56 | #endif /* CSI_VALUE */ 57 | 58 | #if !defined (HSI_VALUE) 59 | #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ 60 | #endif /* HSI_VALUE */ 61 | 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32H7xx_System_Private_TypesDefinitions 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32H7xx_System_Private_Defines 76 | * @{ 77 | */ 78 | 79 | /************************* Miscellaneous Configuration ************************/ 80 | /*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ 81 | /* #define DATA_IN_D2_SRAM */ 82 | 83 | /*!< Uncomment the following line if you need to relocate your vector Table in 84 | Internal SRAM. */ 85 | /* #define VECT_TAB_SRAM */ 86 | #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. 87 | This value must be a multiple of 0x200. */ 88 | /******************************************************************************/ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @addtogroup STM32H7xx_System_Private_Macros 95 | * @{ 96 | */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** @addtogroup STM32H7xx_System_Private_Variables 103 | * @{ 104 | */ 105 | /* This variable is updated in three ways: 106 | 1) by calling CMSIS function SystemCoreClockUpdate() 107 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 108 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 109 | Note: If you use this function to configure the system clock; then there 110 | is no need to call the 2 first functions listed above, since SystemCoreClock 111 | variable is updated automatically. 112 | */ 113 | uint32_t SystemCoreClock = 64000000; 114 | uint32_t SystemD2Clock = 64000000; 115 | const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes 122 | * @{ 123 | */ 124 | 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @addtogroup STM32H7xx_System_Private_Functions 130 | * @{ 131 | */ 132 | 133 | /** 134 | * @brief Setup the microcontroller system 135 | * Initialize the FPU setting and vector table location 136 | * configuration. 137 | * @param None 138 | * @retval None 139 | */ 140 | void SystemInit (void) 141 | { 142 | #if defined (DATA_IN_D2_SRAM) 143 | __IO uint32_t tmpreg; 144 | #endif /* DATA_IN_D2_SRAM */ 145 | 146 | /* FPU settings ------------------------------------------------------------*/ 147 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 148 | SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 149 | #endif 150 | /* Reset the RCC clock configuration to the default reset state ------------*/ 151 | 152 | /* Increasing the CPU frequency */ 153 | if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 154 | { 155 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 156 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 157 | } 158 | 159 | /* Set HSION bit */ 160 | RCC->CR |= RCC_CR_HSION; 161 | 162 | /* Reset CFGR register */ 163 | RCC->CFGR = 0x00000000; 164 | 165 | /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ 166 | RCC->CR &= 0xEAF6ED7FU; 167 | 168 | /* Decreasing the number of wait states because of lower CPU frequency */ 169 | if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 170 | { 171 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 172 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 173 | } 174 | 175 | #if defined(D3_SRAM_BASE) 176 | /* Reset D1CFGR register */ 177 | RCC->D1CFGR = 0x00000000; 178 | 179 | /* Reset D2CFGR register */ 180 | RCC->D2CFGR = 0x00000000; 181 | 182 | /* Reset D3CFGR register */ 183 | RCC->D3CFGR = 0x00000000; 184 | #else 185 | /* Reset CDCFGR1 register */ 186 | RCC->CDCFGR1 = 0x00000000; 187 | 188 | /* Reset CDCFGR2 register */ 189 | RCC->CDCFGR2 = 0x00000000; 190 | 191 | /* Reset SRDCFGR register */ 192 | RCC->SRDCFGR = 0x00000000; 193 | #endif 194 | /* Reset PLLCKSELR register */ 195 | RCC->PLLCKSELR = 0x02020200; 196 | 197 | /* Reset PLLCFGR register */ 198 | RCC->PLLCFGR = 0x01FF0000; 199 | /* Reset PLL1DIVR register */ 200 | RCC->PLL1DIVR = 0x01010280; 201 | /* Reset PLL1FRACR register */ 202 | RCC->PLL1FRACR = 0x00000000; 203 | 204 | /* Reset PLL2DIVR register */ 205 | RCC->PLL2DIVR = 0x01010280; 206 | 207 | /* Reset PLL2FRACR register */ 208 | 209 | RCC->PLL2FRACR = 0x00000000; 210 | /* Reset PLL3DIVR register */ 211 | RCC->PLL3DIVR = 0x01010280; 212 | 213 | /* Reset PLL3FRACR register */ 214 | RCC->PLL3FRACR = 0x00000000; 215 | 216 | /* Reset HSEBYP bit */ 217 | RCC->CR &= 0xFFFBFFFFU; 218 | 219 | /* Disable all interrupts */ 220 | RCC->CIER = 0x00000000; 221 | 222 | #if (STM32H7_DEV_ID == 0x450UL) 223 | /* dual core CM7 or single core line */ 224 | if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 225 | { 226 | /* if stm32h7 revY*/ 227 | /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ 228 | *((__IO uint32_t*)0x51008108) = 0x000000001U; 229 | } 230 | #endif 231 | 232 | #if defined (DATA_IN_D2_SRAM) 233 | /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ 234 | #if defined(RCC_AHB2ENR_D2SRAM3EN) 235 | RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); 236 | #elif defined(RCC_AHB2ENR_D2SRAM2EN) 237 | RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); 238 | #else 239 | RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); 240 | #endif /* RCC_AHB2ENR_D2SRAM3EN */ 241 | 242 | tmpreg = RCC->AHB2ENR; 243 | (void) tmpreg; 244 | #endif /* DATA_IN_D2_SRAM */ 245 | 246 | #if defined(DUAL_CORE) && defined(CORE_CM4) 247 | /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ 248 | #ifdef VECT_TAB_SRAM 249 | SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 250 | #else 251 | SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 252 | #endif /* VECT_TAB_SRAM */ 253 | 254 | #else 255 | 256 | /* 257 | * Disable the FMC bank1 (enabled after reset). 258 | * This, prevents CPU speculation access on this bank which blocks the use of FMC during 259 | * 24us. During this time the others FMC master (such as LTDC) cannot use it! 260 | */ 261 | FMC_Bank1_R->BTCR[0] = 0x000030D2; 262 | 263 | /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ 264 | #ifdef VECT_TAB_SRAM 265 | SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ 266 | #else 267 | SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 268 | #endif 269 | 270 | #endif /*DUAL_CORE && CORE_CM4*/ 271 | 272 | } 273 | 274 | /** 275 | * @brief Update SystemCoreClock variable according to Clock Register Values. 276 | * The SystemCoreClock variable contains the core clock , it can 277 | * be used by the user application to setup the SysTick timer or configure 278 | * other parameters. 279 | * 280 | * @note Each time the core clock changes, this function must be called 281 | * to update SystemCoreClock variable value. Otherwise, any configuration 282 | * based on this variable will be incorrect. 283 | * 284 | * @note - The system frequency computed by this function is not the real 285 | * frequency in the chip. It is calculated based on the predefined 286 | * constant and the selected clock source: 287 | * 288 | * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) 289 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) 290 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) 291 | * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), 292 | * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. 293 | * 294 | * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value 295 | * 4 MHz) but the real value may vary depending on the variations 296 | * in voltage and temperature. 297 | * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value 298 | * 64 MHz) but the real value may vary depending on the variations 299 | * in voltage and temperature. 300 | * 301 | * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value 302 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real 303 | * frequency of the crystal used. Otherwise, this function may 304 | * have wrong result. 305 | * 306 | * - The result of this function could be not correct when using fractional 307 | * value for HSE crystal. 308 | * @param None 309 | * @retval None 310 | */ 311 | void SystemCoreClockUpdate (void) 312 | { 313 | uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; 314 | uint32_t common_system_clock; 315 | float_t fracn1, pllvco; 316 | 317 | 318 | /* Get SYSCLK source -------------------------------------------------------*/ 319 | 320 | switch (RCC->CFGR & RCC_CFGR_SWS) 321 | { 322 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ 323 | common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); 324 | break; 325 | 326 | case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ 327 | common_system_clock = CSI_VALUE; 328 | break; 329 | 330 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ 331 | common_system_clock = HSE_VALUE; 332 | break; 333 | 334 | case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ 335 | 336 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN 337 | SYSCLK = PLL_VCO / PLLR 338 | */ 339 | pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 340 | pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 341 | pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 342 | fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 343 | 344 | if (pllm != 0U) 345 | { 346 | switch (pllsource) 347 | { 348 | case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ 349 | 350 | hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; 351 | pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 352 | 353 | break; 354 | 355 | case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ 356 | pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 357 | break; 358 | 359 | case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ 360 | pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 361 | break; 362 | 363 | default: 364 | pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 365 | break; 366 | } 367 | pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 368 | common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); 369 | } 370 | else 371 | { 372 | common_system_clock = 0U; 373 | } 374 | break; 375 | 376 | default: 377 | common_system_clock = CSI_VALUE; 378 | break; 379 | } 380 | 381 | /* Compute SystemClock frequency --------------------------------------------------*/ 382 | #if defined (RCC_D1CFGR_D1CPRE) 383 | tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; 384 | 385 | /* common_system_clock frequency : CM7 CPU frequency */ 386 | common_system_clock >>= tmp; 387 | 388 | /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ 389 | SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 390 | 391 | #else 392 | tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; 393 | 394 | /* common_system_clock frequency : CM7 CPU frequency */ 395 | common_system_clock >>= tmp; 396 | 397 | /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ 398 | SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 399 | 400 | #endif 401 | 402 | #if defined(DUAL_CORE) && defined(CORE_CM4) 403 | SystemCoreClock = SystemD2Clock; 404 | #else 405 | SystemCoreClock = common_system_clock; 406 | #endif /* DUAL_CORE && CORE_CM4 */ 407 | } 408 | 409 | 410 | /** 411 | * @} 412 | */ 413 | 414 | /** 415 | * @} 416 | */ 417 | 418 | /** 419 | * @} 420 | */ 421 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 422 | -------------------------------------------------------------------------------- /Core/Src/stm32h7xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * File Name : stm32h7xx_hal_msp.c 5 | * Description : This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2020 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 71 | 72 | /* System interrupt init*/ 73 | 74 | /* USER CODE BEGIN MspInit 1 */ 75 | 76 | /* USER CODE END MspInit 1 */ 77 | } 78 | 79 | /** 80 | * @brief LTDC MSP Initialization 81 | * This function configures the hardware resources used in this example 82 | * @param hltdc: LTDC handle pointer 83 | * @retval None 84 | */ 85 | void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) 86 | { 87 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 88 | if(hltdc->Instance==LTDC) 89 | { 90 | /* USER CODE BEGIN LTDC_MspInit 0 */ 91 | 92 | /* USER CODE END LTDC_MspInit 0 */ 93 | /* Peripheral clock enable */ 94 | __HAL_RCC_LTDC_CLK_ENABLE(); 95 | 96 | __HAL_RCC_GPIOC_CLK_ENABLE(); 97 | __HAL_RCC_GPIOA_CLK_ENABLE(); 98 | __HAL_RCC_GPIOB_CLK_ENABLE(); 99 | __HAL_RCC_GPIOE_CLK_ENABLE(); 100 | __HAL_RCC_GPIOD_CLK_ENABLE(); 101 | /**LTDC GPIO Configuration 102 | PC0 ------> LTDC_G2 103 | PA7 ------> LTDC_VSYNC 104 | PB0 ------> LTDC_R3 105 | PE13 ------> LTDC_DE 106 | PE15 ------> LTDC_R7 107 | PB10 ------> LTDC_G4 108 | PB11 ------> LTDC_G5 109 | PB14 ------> LTDC_CLK 110 | PD10 ------> LTDC_B3 111 | PC6 ------> LTDC_HSYNC 112 | PC7 ------> LTDC_G6 113 | PC9 ------> LTDC_G3 114 | PA8 ------> LTDC_R6 115 | PA9 ------> LTDC_R5 116 | PA10 ------> LTDC_B4 117 | PA11 ------> LTDC_R4 118 | PC10 ------> LTDC_R2 119 | PD2 ------> LTDC_B7 120 | PD3 ------> LTDC_G7 121 | PD6 ------> LTDC_B2 122 | PB5 ------> LTDC_B5 123 | PB8 ------> LTDC_B6 124 | */ 125 | GPIO_InitStruct.Pin = GPIO_PIN_0; 126 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 127 | GPIO_InitStruct.Pull = GPIO_NOPULL; 128 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 129 | GPIO_InitStruct.Alternate = GPIO_AF11_LTDC; 130 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 131 | 132 | GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; 133 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 134 | GPIO_InitStruct.Pull = GPIO_NOPULL; 135 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 136 | GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 137 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 138 | 139 | GPIO_InitStruct.Pin = GPIO_PIN_0; 140 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 141 | GPIO_InitStruct.Pull = GPIO_NOPULL; 142 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 143 | GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; 144 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 145 | 146 | GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; 147 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 148 | GPIO_InitStruct.Pull = GPIO_NOPULL; 149 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 150 | GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 151 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 152 | 153 | GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_8; 154 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 155 | GPIO_InitStruct.Pull = GPIO_NOPULL; 156 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 157 | GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 158 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 159 | 160 | GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_3|GPIO_PIN_6; 161 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 162 | GPIO_InitStruct.Pull = GPIO_NOPULL; 163 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 164 | GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 165 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 166 | 167 | GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10; 168 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 169 | GPIO_InitStruct.Pull = GPIO_NOPULL; 170 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 171 | GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 172 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 173 | 174 | GPIO_InitStruct.Pin = GPIO_PIN_9; 175 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 176 | GPIO_InitStruct.Pull = GPIO_NOPULL; 177 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 178 | GPIO_InitStruct.Alternate = GPIO_AF10_LTDC; 179 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 180 | 181 | GPIO_InitStruct.Pin = GPIO_PIN_10; 182 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 183 | GPIO_InitStruct.Pull = GPIO_NOPULL; 184 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 185 | GPIO_InitStruct.Alternate = GPIO_AF12_LTDC; 186 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 187 | 188 | GPIO_InitStruct.Pin = GPIO_PIN_2; 189 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 190 | GPIO_InitStruct.Pull = GPIO_NOPULL; 191 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 192 | GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; 193 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 194 | 195 | GPIO_InitStruct.Pin = GPIO_PIN_5; 196 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 197 | GPIO_InitStruct.Pull = GPIO_NOPULL; 198 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 199 | GPIO_InitStruct.Alternate = GPIO_AF11_LTDC; 200 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 201 | 202 | /* USER CODE BEGIN LTDC_MspInit 1 */ 203 | 204 | /* USER CODE END LTDC_MspInit 1 */ 205 | } 206 | 207 | } 208 | 209 | /** 210 | * @brief LTDC MSP De-Initialization 211 | * This function freeze the hardware resources used in this example 212 | * @param hltdc: LTDC handle pointer 213 | * @retval None 214 | */ 215 | void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) 216 | { 217 | if(hltdc->Instance==LTDC) 218 | { 219 | /* USER CODE BEGIN LTDC_MspDeInit 0 */ 220 | 221 | /* USER CODE END LTDC_MspDeInit 0 */ 222 | /* Peripheral clock disable */ 223 | __HAL_RCC_LTDC_CLK_DISABLE(); 224 | 225 | /**LTDC GPIO Configuration 226 | PC0 ------> LTDC_G2 227 | PA7 ------> LTDC_VSYNC 228 | PB0 ------> LTDC_R3 229 | PE13 ------> LTDC_DE 230 | PE15 ------> LTDC_R7 231 | PB10 ------> LTDC_G4 232 | PB11 ------> LTDC_G5 233 | PB14 ------> LTDC_CLK 234 | PD10 ------> LTDC_B3 235 | PC6 ------> LTDC_HSYNC 236 | PC7 ------> LTDC_G6 237 | PC9 ------> LTDC_G3 238 | PA8 ------> LTDC_R6 239 | PA9 ------> LTDC_R5 240 | PA10 ------> LTDC_B4 241 | PA11 ------> LTDC_R4 242 | PC10 ------> LTDC_R2 243 | PD2 ------> LTDC_B7 244 | PD3 ------> LTDC_G7 245 | PD6 ------> LTDC_B2 246 | PB5 ------> LTDC_B5 247 | PB8 ------> LTDC_B6 248 | */ 249 | HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_9 250 | |GPIO_PIN_10); 251 | 252 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 253 | |GPIO_PIN_11); 254 | 255 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_14 256 | |GPIO_PIN_5|GPIO_PIN_8); 257 | 258 | HAL_GPIO_DeInit(GPIOE, GPIO_PIN_13|GPIO_PIN_15); 259 | 260 | HAL_GPIO_DeInit(GPIOD, GPIO_PIN_10|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6); 261 | 262 | /* USER CODE BEGIN LTDC_MspDeInit 1 */ 263 | 264 | /* USER CODE END LTDC_MspDeInit 1 */ 265 | } 266 | 267 | } 268 | 269 | /** 270 | * @brief OSPI MSP Initialization 271 | * This function configures the hardware resources used in this example 272 | * @param hospi: OSPI handle pointer 273 | * @retval None 274 | */ 275 | void HAL_OSPI_MspInit(OSPI_HandleTypeDef* hospi) 276 | { 277 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 278 | if(hospi->Instance==OCTOSPI1) 279 | { 280 | /* USER CODE BEGIN OCTOSPI1_MspInit 0 */ 281 | 282 | /* USER CODE END OCTOSPI1_MspInit 0 */ 283 | /* Peripheral clock enable */ 284 | __HAL_RCC_OCTOSPIM_CLK_ENABLE(); 285 | __HAL_RCC_OSPI1_CLK_ENABLE(); 286 | 287 | __HAL_RCC_GPIOE_CLK_ENABLE(); 288 | __HAL_RCC_GPIOA_CLK_ENABLE(); 289 | __HAL_RCC_GPIOB_CLK_ENABLE(); 290 | __HAL_RCC_GPIOD_CLK_ENABLE(); 291 | /**OCTOSPI1 GPIO Configuration 292 | PE2 ------> OCTOSPIM_P1_IO2 293 | PA1 ------> OCTOSPIM_P1_IO3 294 | PB1 ------> OCTOSPIM_P1_IO0 295 | PB2 ------> OCTOSPIM_P1_CLK 296 | PE11 ------> OCTOSPIM_P1_NCS 297 | PD12 ------> OCTOSPIM_P1_IO1 298 | */ 299 | GPIO_InitStruct.Pin = GPIO_PIN_2; 300 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 301 | GPIO_InitStruct.Pull = GPIO_NOPULL; 302 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 303 | GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 304 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 305 | 306 | GPIO_InitStruct.Pin = GPIO_PIN_1; 307 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 308 | GPIO_InitStruct.Pull = GPIO_NOPULL; 309 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 310 | GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 311 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 312 | 313 | GPIO_InitStruct.Pin = GPIO_PIN_1; 314 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 315 | GPIO_InitStruct.Pull = GPIO_NOPULL; 316 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 317 | GPIO_InitStruct.Alternate = GPIO_AF11_OCTOSPIM_P1; 318 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 319 | 320 | GPIO_InitStruct.Pin = GPIO_PIN_2; 321 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 322 | GPIO_InitStruct.Pull = GPIO_NOPULL; 323 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 324 | GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 325 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 326 | 327 | GPIO_InitStruct.Pin = GPIO_PIN_11; 328 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 329 | GPIO_InitStruct.Pull = GPIO_NOPULL; 330 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 331 | GPIO_InitStruct.Alternate = GPIO_AF11_OCTOSPIM_P1; 332 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 333 | 334 | GPIO_InitStruct.Pin = GPIO_PIN_12; 335 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 336 | GPIO_InitStruct.Pull = GPIO_NOPULL; 337 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 338 | GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 339 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 340 | 341 | /* USER CODE BEGIN OCTOSPI1_MspInit 1 */ 342 | 343 | /* USER CODE END OCTOSPI1_MspInit 1 */ 344 | } 345 | 346 | } 347 | 348 | /** 349 | * @brief OSPI MSP De-Initialization 350 | * This function freeze the hardware resources used in this example 351 | * @param hospi: OSPI handle pointer 352 | * @retval None 353 | */ 354 | void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef* hospi) 355 | { 356 | if(hospi->Instance==OCTOSPI1) 357 | { 358 | /* USER CODE BEGIN OCTOSPI1_MspDeInit 0 */ 359 | 360 | /* USER CODE END OCTOSPI1_MspDeInit 0 */ 361 | /* Peripheral clock disable */ 362 | __HAL_RCC_OCTOSPIM_CLK_DISABLE(); 363 | __HAL_RCC_OSPI1_CLK_DISABLE(); 364 | 365 | /**OCTOSPI1 GPIO Configuration 366 | PE2 ------> OCTOSPIM_P1_IO2 367 | PA1 ------> OCTOSPIM_P1_IO3 368 | PB1 ------> OCTOSPIM_P1_IO0 369 | PB2 ------> OCTOSPIM_P1_CLK 370 | PE11 ------> OCTOSPIM_P1_NCS 371 | PD12 ------> OCTOSPIM_P1_IO1 372 | */ 373 | HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_11); 374 | 375 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1); 376 | 377 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1|GPIO_PIN_2); 378 | 379 | HAL_GPIO_DeInit(GPIOD, GPIO_PIN_12); 380 | 381 | /* OCTOSPI1 interrupt DeInit */ 382 | HAL_NVIC_DisableIRQ(OCTOSPI1_IRQn); 383 | /* USER CODE BEGIN OCTOSPI1_MspDeInit 1 */ 384 | 385 | /* USER CODE END OCTOSPI1_MspDeInit 1 */ 386 | } 387 | 388 | } 389 | 390 | /** 391 | * @brief SPI MSP Initialization 392 | * This function configures the hardware resources used in this example 393 | * @param hspi: SPI handle pointer 394 | * @retval None 395 | */ 396 | void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) 397 | { 398 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 399 | if(hspi->Instance==SPI2) 400 | { 401 | /* USER CODE BEGIN SPI2_MspInit 0 */ 402 | 403 | /* USER CODE END SPI2_MspInit 0 */ 404 | /* Peripheral clock enable */ 405 | __HAL_RCC_SPI2_CLK_ENABLE(); 406 | 407 | __HAL_RCC_GPIOB_CLK_ENABLE(); 408 | /**SPI2 GPIO Configuration 409 | PB13 ------> SPI2_SCK 410 | PB15 ------> SPI2_MOSI 411 | */ 412 | GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; 413 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 414 | GPIO_InitStruct.Pull = GPIO_NOPULL; 415 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 416 | GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 417 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 418 | 419 | /* USER CODE BEGIN SPI2_MspInit 1 */ 420 | 421 | /* USER CODE END SPI2_MspInit 1 */ 422 | } 423 | 424 | } 425 | 426 | /** 427 | * @brief SPI MSP De-Initialization 428 | * This function freeze the hardware resources used in this example 429 | * @param hspi: SPI handle pointer 430 | * @retval None 431 | */ 432 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) 433 | { 434 | if(hspi->Instance==SPI2) 435 | { 436 | /* USER CODE BEGIN SPI2_MspDeInit 0 */ 437 | 438 | /* USER CODE END SPI2_MspDeInit 0 */ 439 | /* Peripheral clock disable */ 440 | __HAL_RCC_SPI2_CLK_DISABLE(); 441 | 442 | /**SPI2 GPIO Configuration 443 | PB13 ------> SPI2_SCK 444 | PB15 ------> SPI2_MOSI 445 | */ 446 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_15); 447 | 448 | /* USER CODE BEGIN SPI2_MspDeInit 1 */ 449 | 450 | /* USER CODE END SPI2_MspDeInit 1 */ 451 | } 452 | 453 | } 454 | 455 | extern DMA_HandleTypeDef hdma_sai1_a; 456 | 457 | static uint32_t SAI1_client =0; 458 | 459 | void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) 460 | { 461 | 462 | GPIO_InitTypeDef GPIO_InitStruct; 463 | /* SAI1 */ 464 | if(hsai->Instance==SAI1_Block_A) 465 | { 466 | /* Peripheral clock enable */ 467 | if (SAI1_client == 0) 468 | { 469 | __HAL_RCC_SAI1_CLK_ENABLE(); 470 | 471 | /* Peripheral interrupt init*/ 472 | HAL_NVIC_SetPriority(SAI1_IRQn, 0, 0); 473 | HAL_NVIC_EnableIRQ(SAI1_IRQn); 474 | } 475 | SAI1_client ++; 476 | 477 | /**SAI1_A_Block_A GPIO Configuration 478 | PE4 ------> SAI1_FS_A 479 | PE5 ------> SAI1_SCK_A 480 | PE6 ------> SAI1_SD_A 481 | */ 482 | GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; 483 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 484 | GPIO_InitStruct.Pull = GPIO_NOPULL; 485 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 486 | GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; 487 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 488 | 489 | /* Peripheral DMA init*/ 490 | 491 | hdma_sai1_a.Instance = DMA1_Stream0; 492 | hdma_sai1_a.Init.Request = DMA_REQUEST_SAI1_A; 493 | hdma_sai1_a.Init.Direction = DMA_MEMORY_TO_PERIPH; 494 | hdma_sai1_a.Init.PeriphInc = DMA_PINC_DISABLE; 495 | hdma_sai1_a.Init.MemInc = DMA_MINC_ENABLE; 496 | hdma_sai1_a.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 497 | hdma_sai1_a.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 498 | hdma_sai1_a.Init.Mode = DMA_CIRCULAR; 499 | hdma_sai1_a.Init.Priority = DMA_PRIORITY_LOW; 500 | hdma_sai1_a.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 501 | if (HAL_DMA_Init(&hdma_sai1_a) != HAL_OK) 502 | { 503 | Error_Handler(); 504 | } 505 | 506 | /* Several peripheral DMA handle pointers point to the same DMA handle. 507 | Be aware that there is only one channel to perform all the requested DMAs. */ 508 | __HAL_LINKDMA(hsai,hdmarx,hdma_sai1_a); 509 | 510 | __HAL_LINKDMA(hsai,hdmatx,hdma_sai1_a); 511 | 512 | } 513 | } 514 | 515 | void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) 516 | { 517 | /* SAI1 */ 518 | if(hsai->Instance==SAI1_Block_A) 519 | { 520 | SAI1_client --; 521 | if (SAI1_client == 0) 522 | { 523 | /* Peripheral clock disable */ 524 | __HAL_RCC_SAI1_CLK_DISABLE(); 525 | HAL_NVIC_DisableIRQ(SAI1_IRQn); 526 | } 527 | 528 | /**SAI1_A_Block_A GPIO Configuration 529 | PE4 ------> SAI1_FS_A 530 | PE5 ------> SAI1_SCK_A 531 | PE6 ------> SAI1_SD_A 532 | */ 533 | HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); 534 | 535 | HAL_DMA_DeInit(hsai->hdmarx); 536 | HAL_DMA_DeInit(hsai->hdmatx); 537 | } 538 | } 539 | 540 | /* USER CODE BEGIN 1 */ 541 | 542 | /* USER CODE END 1 */ 543 | 544 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 545 | -------------------------------------------------------------------------------- /Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | #include "buttons.h" 26 | #include "flash.h" 27 | #include "lcd.h" 28 | /* USER CODE END Includes */ 29 | 30 | /* Private typedef -----------------------------------------------------------*/ 31 | /* USER CODE BEGIN PTD */ 32 | 33 | /* USER CODE END PTD */ 34 | 35 | /* Private define ------------------------------------------------------------*/ 36 | /* USER CODE BEGIN PD */ 37 | /* USER CODE END PD */ 38 | 39 | /* Private macro -------------------------------------------------------------*/ 40 | /* USER CODE BEGIN PM */ 41 | 42 | /* USER CODE END PM */ 43 | 44 | /* Private variables ---------------------------------------------------------*/ 45 | 46 | LTDC_HandleTypeDef hltdc; 47 | 48 | OSPI_HandleTypeDef hospi1; 49 | 50 | SAI_HandleTypeDef hsai_BlockA1; 51 | DMA_HandleTypeDef hdma_sai1_a; 52 | 53 | SPI_HandleTypeDef hspi2; 54 | 55 | /* USER CODE BEGIN PV */ 56 | 57 | // Flag to indicate that dumping is done 58 | __attribute__((used)) uint32_t dump_done; 59 | 60 | /* USER CODE END PV */ 61 | 62 | /* Private function prototypes -----------------------------------------------*/ 63 | void SystemClock_Config(void); 64 | static void MX_GPIO_Init(void); 65 | static void MX_DMA_Init(void); 66 | static void MX_LTDC_Init(void); 67 | static void MX_SPI2_Init(void); 68 | static void MX_OCTOSPI1_Init(void); 69 | static void MX_SAI1_Init(void); 70 | static void MX_NVIC_Init(void); 71 | /* USER CODE BEGIN PFP */ 72 | 73 | /* USER CODE END PFP */ 74 | 75 | /* Private user code ---------------------------------------------------------*/ 76 | /* USER CODE BEGIN 0 */ 77 | 78 | void HAL_Delay(uint32_t Delay) 79 | { 80 | while (Delay--) { 81 | // Accurate at 48MHz sysclock 82 | for (int i = 0; i < 2 * 48000 / 3; i++) { 83 | __NOP(); 84 | } 85 | } 86 | } 87 | 88 | /* USER CODE END 0 */ 89 | 90 | /** 91 | * @brief The application entry point. 92 | * @retval int 93 | */ 94 | int main(void) 95 | { 96 | /* USER CODE BEGIN 1 */ 97 | /* USER CODE END 1 */ 98 | 99 | /* MCU Configuration--------------------------------------------------------*/ 100 | 101 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 102 | HAL_Init(); 103 | 104 | /* USER CODE BEGIN Init */ 105 | /* USER CODE END Init */ 106 | 107 | /* Configure the system clock */ 108 | SystemClock_Config(); 109 | 110 | /* USER CODE BEGIN SysInit */ 111 | 112 | /* USER CODE END SysInit */ 113 | 114 | /* Initialize all configured peripherals */ 115 | MX_GPIO_Init(); 116 | MX_DMA_Init(); 117 | MX_LTDC_Init(); 118 | MX_SPI2_Init(); 119 | MX_OCTOSPI1_Init(); 120 | MX_SAI1_Init(); 121 | 122 | /* Initialize interrupts */ 123 | MX_NVIC_Init(); 124 | /* USER CODE BEGIN 2 */ 125 | 126 | // lcd_init(&hspi2, &hltdc); 127 | // memset(framebuffer, 0xff, 320*240*2); 128 | 129 | // SPI_MODE or QUAD_MODE 130 | quad_mode_t quad_mode = SPI_MODE; 131 | 132 | // VENDOR_MX: MX25U8035F, Nintendo Stock Flash 133 | // VENDOR_ISSI: IS25WP128F, 128Mb large flash 134 | spi_chip_vendor_t vendor = VENDOR_MX; 135 | 136 | // Dump flash with normal commands 137 | memset(0x24000000, '\xFF', 1024 * 1024); 138 | OSPI_Init(&hospi1, quad_mode, vendor); 139 | OSPI_Read(&hospi1, 0, 0x24000000, 1024 * 1024); 140 | 141 | dump_done = 1; 142 | 143 | /* USER CODE END 2 */ 144 | 145 | /* Infinite loop */ 146 | /* USER CODE BEGIN WHILE */ 147 | while (1) 148 | { 149 | /* USER CODE END WHILE */ 150 | 151 | // Blink slowly to indicate that dumping is done 152 | lcd_backlight_off(); 153 | HAL_Delay(2000); 154 | lcd_backlight_on(); 155 | HAL_Delay(2000); 156 | 157 | /* USER CODE BEGIN 3 */ 158 | } 159 | /* USER CODE END 3 */ 160 | } 161 | 162 | /** 163 | * @brief System Clock Configuration 164 | * @retval None 165 | */ 166 | void SystemClock_Config(void) 167 | { 168 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 169 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 170 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 171 | 172 | /** Supply configuration update enable 173 | */ 174 | HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 175 | /** Configure the main internal regulator output voltage 176 | */ 177 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 178 | 179 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 180 | /** Macro to configure the PLL clock source 181 | */ 182 | __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSI); 183 | /** Initializes the RCC Oscillators according to the specified parameters 184 | * in the RCC_OscInitTypeDef structure. 185 | */ 186 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 187 | RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 188 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 189 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 190 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 191 | RCC_OscInitStruct.PLL.PLLM = 16; 192 | RCC_OscInitStruct.PLL.PLLN = 140; 193 | RCC_OscInitStruct.PLL.PLLP = 2; 194 | RCC_OscInitStruct.PLL.PLLQ = 2; 195 | RCC_OscInitStruct.PLL.PLLR = 2; 196 | RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 197 | RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 198 | RCC_OscInitStruct.PLL.PLLFRACN = 0; 199 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 200 | { 201 | Error_Handler(); 202 | } 203 | /** Initializes the CPU, AHB and APB buses clocks 204 | */ 205 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 206 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 207 | |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; 208 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 209 | RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 210 | RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 211 | RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 212 | RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 213 | RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 214 | RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 215 | 216 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) 217 | { 218 | Error_Handler(); 219 | } 220 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_SPI2 221 | |RCC_PERIPHCLK_SAI1|RCC_PERIPHCLK_OSPI 222 | |RCC_PERIPHCLK_CKPER; 223 | PeriphClkInitStruct.PLL2.PLL2M = 25; 224 | PeriphClkInitStruct.PLL2.PLL2N = 192; 225 | PeriphClkInitStruct.PLL2.PLL2P = 5; 226 | PeriphClkInitStruct.PLL2.PLL2Q = 2; 227 | PeriphClkInitStruct.PLL2.PLL2R = 5; 228 | PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1; 229 | PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 230 | PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 231 | PeriphClkInitStruct.PLL3.PLL3M = 4; 232 | PeriphClkInitStruct.PLL3.PLL3N = 9; 233 | PeriphClkInitStruct.PLL3.PLL3P = 2; 234 | PeriphClkInitStruct.PLL3.PLL3Q = 2; 235 | PeriphClkInitStruct.PLL3.PLL3R = 24; 236 | PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; 237 | PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; 238 | PeriphClkInitStruct.PLL3.PLL3FRACN = 0; 239 | PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_CLKP; 240 | PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; 241 | PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2; 242 | PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_CLKP; 243 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 244 | { 245 | Error_Handler(); 246 | } 247 | } 248 | 249 | /** 250 | * @brief NVIC Configuration. 251 | * @retval None 252 | */ 253 | static void MX_NVIC_Init(void) 254 | { 255 | /* OCTOSPI1_IRQn interrupt configuration */ 256 | HAL_NVIC_SetPriority(OCTOSPI1_IRQn, 0, 0); 257 | HAL_NVIC_EnableIRQ(OCTOSPI1_IRQn); 258 | } 259 | 260 | /** 261 | * @brief LTDC Initialization Function 262 | * @param None 263 | * @retval None 264 | */ 265 | static void MX_LTDC_Init(void) 266 | { 267 | 268 | /* USER CODE BEGIN LTDC_Init 0 */ 269 | 270 | /* USER CODE END LTDC_Init 0 */ 271 | 272 | LTDC_LayerCfgTypeDef pLayerCfg = {0}; 273 | 274 | /* USER CODE BEGIN LTDC_Init 1 */ 275 | 276 | /* USER CODE END LTDC_Init 1 */ 277 | hltdc.Instance = LTDC; 278 | hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; 279 | hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; 280 | hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; 281 | hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IIPC; 282 | hltdc.Init.HorizontalSync = 9; 283 | hltdc.Init.VerticalSync = 1; 284 | hltdc.Init.AccumulatedHBP = 60; 285 | hltdc.Init.AccumulatedVBP = 7; 286 | hltdc.Init.AccumulatedActiveW = 380; 287 | hltdc.Init.AccumulatedActiveH = 247; 288 | hltdc.Init.TotalWidth = 392; 289 | hltdc.Init.TotalHeigh = 255; 290 | hltdc.Init.Backcolor.Blue = 0; 291 | hltdc.Init.Backcolor.Green = 0; 292 | hltdc.Init.Backcolor.Red = 0; 293 | if (HAL_LTDC_Init(&hltdc) != HAL_OK) 294 | { 295 | Error_Handler(); 296 | } 297 | pLayerCfg.WindowX0 = 0; 298 | pLayerCfg.WindowX1 = 320; 299 | pLayerCfg.WindowY0 = 0; 300 | pLayerCfg.WindowY1 = 240; 301 | pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; 302 | pLayerCfg.Alpha = 255; 303 | pLayerCfg.Alpha0 = 255; 304 | pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; 305 | pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; 306 | pLayerCfg.FBStartAdress = 0x24000000; 307 | pLayerCfg.ImageWidth = 320; 308 | pLayerCfg.ImageHeight = 240; 309 | pLayerCfg.Backcolor.Blue = 0; 310 | pLayerCfg.Backcolor.Green = 255; 311 | pLayerCfg.Backcolor.Red = 0; 312 | if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) 313 | { 314 | Error_Handler(); 315 | } 316 | /* USER CODE BEGIN LTDC_Init 2 */ 317 | 318 | /* USER CODE END LTDC_Init 2 */ 319 | 320 | } 321 | 322 | /** 323 | * @brief OCTOSPI1 Initialization Function 324 | * @param None 325 | * @retval None 326 | */ 327 | static void MX_OCTOSPI1_Init(void) 328 | { 329 | 330 | /* USER CODE BEGIN OCTOSPI1_Init 0 */ 331 | 332 | /* USER CODE END OCTOSPI1_Init 0 */ 333 | 334 | OSPIM_CfgTypeDef sOspiManagerCfg = {0}; 335 | 336 | /* USER CODE BEGIN OCTOSPI1_Init 1 */ 337 | 338 | /* USER CODE END OCTOSPI1_Init 1 */ 339 | /* OCTOSPI1 parameter configuration*/ 340 | hospi1.Instance = OCTOSPI1; 341 | hospi1.Init.FifoThreshold = 4; 342 | hospi1.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; 343 | hospi1.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; 344 | hospi1.Init.DeviceSize = 20; 345 | hospi1.Init.ChipSelectHighTime = 2; 346 | hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; 347 | hospi1.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; 348 | hospi1.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED; 349 | hospi1.Init.ClockPrescaler = 1; 350 | hospi1.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; 351 | hospi1.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE; 352 | hospi1.Init.ChipSelectBoundary = 0; 353 | hospi1.Init.ClkChipSelectHighTime = 0; 354 | hospi1.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED; 355 | hospi1.Init.MaxTran = 0; 356 | hospi1.Init.Refresh = 0; 357 | if (HAL_OSPI_Init(&hospi1) != HAL_OK) 358 | { 359 | Error_Handler(); 360 | } 361 | sOspiManagerCfg.ClkPort = 1; 362 | sOspiManagerCfg.NCSPort = 1; 363 | sOspiManagerCfg.IOLowPort = HAL_OSPIM_IOPORT_1_LOW; 364 | if (HAL_OSPIM_Config(&hospi1, &sOspiManagerCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 365 | { 366 | Error_Handler(); 367 | } 368 | /* USER CODE BEGIN OCTOSPI1_Init 2 */ 369 | 370 | /* USER CODE END OCTOSPI1_Init 2 */ 371 | 372 | } 373 | 374 | /** 375 | * @brief SAI1 Initialization Function 376 | * @param None 377 | * @retval None 378 | */ 379 | static void MX_SAI1_Init(void) 380 | { 381 | 382 | /* USER CODE BEGIN SAI1_Init 0 */ 383 | 384 | /* USER CODE END SAI1_Init 0 */ 385 | 386 | /* USER CODE BEGIN SAI1_Init 1 */ 387 | 388 | /* USER CODE END SAI1_Init 1 */ 389 | hsai_BlockA1.Instance = SAI1_Block_A; 390 | hsai_BlockA1.Init.AudioMode = SAI_MODEMASTER_TX; 391 | hsai_BlockA1.Init.Synchro = SAI_ASYNCHRONOUS; 392 | hsai_BlockA1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; 393 | hsai_BlockA1.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; 394 | hsai_BlockA1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; 395 | hsai_BlockA1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_48K; 396 | hsai_BlockA1.Init.SynchroExt = SAI_SYNCEXT_DISABLE; 397 | hsai_BlockA1.Init.MonoStereoMode = SAI_MONOMODE; 398 | hsai_BlockA1.Init.CompandingMode = SAI_NOCOMPANDING; 399 | hsai_BlockA1.Init.TriState = SAI_OUTPUT_NOTRELEASED; 400 | if (HAL_SAI_InitProtocol(&hsai_BlockA1, SAI_I2S_STANDARD, SAI_PROTOCOL_DATASIZE_16BIT, 2) != HAL_OK) 401 | { 402 | Error_Handler(); 403 | } 404 | /* USER CODE BEGIN SAI1_Init 2 */ 405 | 406 | /* USER CODE END SAI1_Init 2 */ 407 | 408 | } 409 | 410 | /** 411 | * @brief SPI2 Initialization Function 412 | * @param None 413 | * @retval None 414 | */ 415 | static void MX_SPI2_Init(void) 416 | { 417 | 418 | /* USER CODE BEGIN SPI2_Init 0 */ 419 | 420 | /* USER CODE END SPI2_Init 0 */ 421 | 422 | /* USER CODE BEGIN SPI2_Init 1 */ 423 | 424 | /* USER CODE END SPI2_Init 1 */ 425 | /* SPI2 parameter configuration*/ 426 | hspi2.Instance = SPI2; 427 | hspi2.Init.Mode = SPI_MODE_MASTER; 428 | hspi2.Init.Direction = SPI_DIRECTION_2LINES_TXONLY; 429 | hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 430 | hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 431 | hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 432 | hspi2.Init.NSS = SPI_NSS_SOFT; 433 | hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; 434 | hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 435 | hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 436 | hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 437 | hspi2.Init.CRCPolynomial = 0x0; 438 | hspi2.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; 439 | hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 440 | hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 441 | hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 442 | hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 443 | hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 444 | hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 445 | hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 446 | hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 447 | hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; 448 | if (HAL_SPI_Init(&hspi2) != HAL_OK) 449 | { 450 | Error_Handler(); 451 | } 452 | /* USER CODE BEGIN SPI2_Init 2 */ 453 | 454 | /* USER CODE END SPI2_Init 2 */ 455 | 456 | } 457 | 458 | /** 459 | * Enable DMA controller clock 460 | */ 461 | static void MX_DMA_Init(void) 462 | { 463 | 464 | /* DMA controller clock enable */ 465 | __HAL_RCC_DMA1_CLK_ENABLE(); 466 | 467 | /* DMA interrupt init */ 468 | /* DMA1_Stream0_IRQn interrupt configuration */ 469 | HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 470 | HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 471 | 472 | } 473 | 474 | /** 475 | * @brief GPIO Initialization Function 476 | * @param None 477 | * @retval None 478 | */ 479 | static void MX_GPIO_Init(void) 480 | { 481 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 482 | 483 | /* GPIO Ports Clock Enable */ 484 | __HAL_RCC_GPIOE_CLK_ENABLE(); 485 | __HAL_RCC_GPIOC_CLK_ENABLE(); 486 | __HAL_RCC_GPIOA_CLK_ENABLE(); 487 | __HAL_RCC_GPIOB_CLK_ENABLE(); 488 | __HAL_RCC_GPIOD_CLK_ENABLE(); 489 | 490 | /*Configure GPIO pin Output Level */ 491 | HAL_GPIO_WritePin(GPIO_Speaker_enable_GPIO_Port, GPIO_Speaker_enable_Pin, GPIO_PIN_SET); 492 | 493 | /*Configure GPIO pin Output Level */ 494 | HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6, GPIO_PIN_SET); 495 | 496 | /*Configure GPIO pin Output Level */ 497 | HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); 498 | 499 | /*Configure GPIO pin Output Level */ 500 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8|GPIO_PIN_4, GPIO_PIN_SET); 501 | 502 | /*Configure GPIO pin Output Level */ 503 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_1, GPIO_PIN_RESET); 504 | 505 | /*Configure GPIO pin : GPIO_Speaker_enable_Pin */ 506 | GPIO_InitStruct.Pin = GPIO_Speaker_enable_Pin; 507 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 508 | GPIO_InitStruct.Pull = GPIO_NOPULL; 509 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 510 | HAL_GPIO_Init(GPIO_Speaker_enable_GPIO_Port, &GPIO_InitStruct); 511 | 512 | /*Configure GPIO pins : BTN_PAUSE_Pin BTN_GAME_Pin BTN_TIME_Pin */ 513 | GPIO_InitStruct.Pin = BTN_PAUSE_Pin|BTN_GAME_Pin|BTN_TIME_Pin; 514 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 515 | GPIO_InitStruct.Pull = GPIO_PULLUP; 516 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 517 | 518 | /*Configure GPIO pins : PA4 PA5 PA6 */ 519 | GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; 520 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 521 | GPIO_InitStruct.Pull = GPIO_NOPULL; 522 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 523 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 524 | 525 | /*Configure GPIO pin : PB12 */ 526 | GPIO_InitStruct.Pin = GPIO_PIN_12; 527 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 528 | GPIO_InitStruct.Pull = GPIO_NOPULL; 529 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 530 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 531 | 532 | /*Configure GPIO pins : PD8 PD1 PD4 */ 533 | GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_4; 534 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 535 | GPIO_InitStruct.Pull = GPIO_NOPULL; 536 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 537 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 538 | 539 | /*Configure GPIO pins : BTN_A_Pin BTN_Left_Pin BTN_Down_Pin BTN_Right_Pin 540 | BTN_Up_Pin BTN_B_Pin */ 541 | GPIO_InitStruct.Pin = BTN_A_Pin|BTN_Left_Pin|BTN_Down_Pin|BTN_Right_Pin 542 | |BTN_Up_Pin|BTN_B_Pin; 543 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 544 | GPIO_InitStruct.Pull = GPIO_PULLUP; 545 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 546 | 547 | } 548 | 549 | /* USER CODE BEGIN 4 */ 550 | 551 | /* USER CODE END 4 */ 552 | 553 | /** 554 | * @brief This function is executed in case of error occurrence. 555 | * @retval None 556 | */ 557 | void Error_Handler(void) 558 | { 559 | /* USER CODE BEGIN Error_Handler_Debug */ 560 | /* User can add his own implementation to report the HAL error return state */ 561 | while(1) { 562 | // Blink display to indicate failure 563 | lcd_backlight_off(); 564 | HAL_Delay(500); 565 | lcd_backlight_on(); 566 | HAL_Delay(500); 567 | } 568 | /* USER CODE END Error_Handler_Debug */ 569 | } 570 | 571 | #ifdef USE_FULL_ASSERT 572 | /** 573 | * @brief Reports the name of the source file and the source line number 574 | * where the assert_param error has occurred. 575 | * @param file: pointer to the source file name 576 | * @param line: assert_param error line source number 577 | * @retval None 578 | */ 579 | void assert_failed(uint8_t *file, uint32_t line) 580 | { 581 | /* USER CODE BEGIN 6 */ 582 | /* User can add his own implementation to report the file name and line number, 583 | tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 584 | /* USER CODE END 6 */ 585 | } 586 | #endif /* USE_FULL_ASSERT */ 587 | 588 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 589 | -------------------------------------------------------------------------------- /Core/Inc/stm32h7xx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_conf.h 4 | * @author MCD Application Team 5 | * @brief HAL configuration file. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32H7xx_HAL_CONF_H 22 | #define STM32H7xx_HAL_CONF_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | 31 | /* ########################## Module Selection ############################## */ 32 | /** 33 | * @brief This is the list of modules to be used in the HAL driver 34 | */ 35 | #define HAL_MODULE_ENABLED 36 | 37 | /* #define HAL_ADC_MODULE_ENABLED */ 38 | /* #define HAL_FDCAN_MODULE_ENABLED */ 39 | /* #define HAL_FMAC_MODULE_ENABLED */ 40 | /* #define HAL_CEC_MODULE_ENABLED */ 41 | /* #define HAL_COMP_MODULE_ENABLED */ 42 | /* #define HAL_CORDIC_MODULE_ENABLED */ 43 | /* #define HAL_CRC_MODULE_ENABLED */ 44 | /* #define HAL_CRYP_MODULE_ENABLED */ 45 | /* #define HAL_DAC_MODULE_ENABLED */ 46 | /* #define HAL_DCMI_MODULE_ENABLED */ 47 | /* #define HAL_DMA2D_MODULE_ENABLED */ 48 | /* #define HAL_ETH_MODULE_ENABLED */ 49 | /* #define HAL_NAND_MODULE_ENABLED */ 50 | /* #define HAL_NOR_MODULE_ENABLED */ 51 | /* #define HAL_OTFDEC_MODULE_ENABLED */ 52 | /* #define HAL_SRAM_MODULE_ENABLED */ 53 | /* #define HAL_SDRAM_MODULE_ENABLED */ 54 | /* #define HAL_HASH_MODULE_ENABLED */ 55 | /* #define HAL_HRTIM_MODULE_ENABLED */ 56 | /* #define HAL_HSEM_MODULE_ENABLED */ 57 | /* #define HAL_GFXMMU_MODULE_ENABLED */ 58 | /* #define HAL_JPEG_MODULE_ENABLED */ 59 | /* #define HAL_OPAMP_MODULE_ENABLED */ 60 | /* #define HAL_OSPI_MODULE_ENABLED */ 61 | #define HAL_OSPI_MODULE_ENABLED 62 | /* #define HAL_I2S_MODULE_ENABLED */ 63 | /* #define HAL_SMBUS_MODULE_ENABLED */ 64 | /* #define HAL_IWDG_MODULE_ENABLED */ 65 | /* #define HAL_LPTIM_MODULE_ENABLED */ 66 | #define HAL_LTDC_MODULE_ENABLED 67 | /* #define HAL_QSPI_MODULE_ENABLED */ 68 | /* #define HAL_RNG_MODULE_ENABLED */ 69 | /* #define HAL_RTC_MODULE_ENABLED */ 70 | #define HAL_SAI_MODULE_ENABLED 71 | /* #define HAL_SD_MODULE_ENABLED */ 72 | /* #define HAL_MMC_MODULE_ENABLED */ 73 | /* #define HAL_SPDIFRX_MODULE_ENABLED */ 74 | #define HAL_SPI_MODULE_ENABLED 75 | /* #define HAL_SWPMI_MODULE_ENABLED */ 76 | /* #define HAL_TIM_MODULE_ENABLED */ 77 | /* #define HAL_UART_MODULE_ENABLED */ 78 | /* #define HAL_USART_MODULE_ENABLED */ 79 | /* #define HAL_IRDA_MODULE_ENABLED */ 80 | /* #define HAL_SMARTCARD_MODULE_ENABLED */ 81 | /* #define HAL_WWDG_MODULE_ENABLED */ 82 | /* #define HAL_PCD_MODULE_ENABLED */ 83 | /* #define HAL_HCD_MODULE_ENABLED */ 84 | /* #define HAL_DFSDM_MODULE_ENABLED */ 85 | /* #define HAL_DSI_MODULE_ENABLED */ 86 | /* #define HAL_JPEG_MODULE_ENABLED */ 87 | /* #define HAL_MDIOS_MODULE_ENABLED */ 88 | /* #define HAL_PSSI_MODULE_ENABLED */ 89 | /* #define HAL_DTS_MODULE_ENABLED */ 90 | #define HAL_GPIO_MODULE_ENABLED 91 | #define HAL_DMA_MODULE_ENABLED 92 | #define HAL_MDMA_MODULE_ENABLED 93 | #define HAL_RCC_MODULE_ENABLED 94 | #define HAL_FLASH_MODULE_ENABLED 95 | #define HAL_EXTI_MODULE_ENABLED 96 | #define HAL_PWR_MODULE_ENABLED 97 | #define HAL_I2C_MODULE_ENABLED 98 | #define HAL_CORTEX_MODULE_ENABLED 99 | #define HAL_HSEM_MODULE_ENABLED 100 | 101 | /* ########################## Oscillator Values adaptation ####################*/ 102 | /** 103 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 104 | * This value is used by the RCC HAL module to compute the system frequency 105 | * (when HSE is used as system clock source, directly or through the PLL). 106 | */ 107 | #if !defined (HSE_VALUE) 108 | #define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ 109 | #endif /* HSE_VALUE */ 110 | 111 | #if !defined (HSE_STARTUP_TIMEOUT) 112 | #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ 113 | #endif /* HSE_STARTUP_TIMEOUT */ 114 | 115 | /** 116 | * @brief Internal oscillator (CSI) default value. 117 | * This value is the default CSI value after Reset. 118 | */ 119 | #if !defined (CSI_VALUE) 120 | #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ 121 | #endif /* CSI_VALUE */ 122 | 123 | /** 124 | * @brief Internal High Speed oscillator (HSI) value. 125 | * This value is used by the RCC HAL module to compute the system frequency 126 | * (when HSI is used as system clock source, directly or through the PLL). 127 | */ 128 | #if !defined (HSI_VALUE) 129 | #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ 130 | #endif /* HSI_VALUE */ 131 | 132 | /** 133 | * @brief External Low Speed oscillator (LSE) value. 134 | * This value is used by the UART, RTC HAL module to compute the system frequency 135 | */ 136 | #if !defined (LSE_VALUE) 137 | #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ 138 | #endif /* LSE_VALUE */ 139 | 140 | #if !defined (LSE_STARTUP_TIMEOUT) 141 | #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ 142 | #endif /* LSE_STARTUP_TIMEOUT */ 143 | 144 | #if !defined (LSI_VALUE) 145 | #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ 146 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 147 | The real value may vary depending on the variations 148 | in voltage and temperature.*/ 149 | 150 | /** 151 | * @brief External clock source for I2S peripheral 152 | * This value is used by the I2S HAL module to compute the I2S clock source 153 | * frequency, this source is inserted directly through I2S_CKIN pad. 154 | */ 155 | #if !defined (EXTERNAL_CLOCK_VALUE) 156 | #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ 157 | #endif /* EXTERNAL_CLOCK_VALUE */ 158 | 159 | /* Tip: To avoid modifying this file each time you need to use different HSE, 160 | === you can define the HSE value in your toolchain compiler preprocessor. */ 161 | 162 | /* ########################### System Configuration ######################### */ 163 | /** 164 | * @brief This is the HAL system configuration section 165 | */ 166 | #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ 167 | #define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ 168 | #define USE_RTOS 0U 169 | #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ 170 | #define USE_SPI_CRC 0U /*!< use CRC in SPI */ 171 | 172 | #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ 173 | #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ 174 | #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ 175 | #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ 176 | #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ 177 | #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ 178 | #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ 179 | #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ 180 | #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ 181 | #define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ 182 | #define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ 183 | #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ 184 | #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ 185 | #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ 186 | #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ 187 | #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ 188 | #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ 189 | #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ 190 | #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ 191 | #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ 192 | #define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ 193 | #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ 194 | #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ 195 | #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ 196 | #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ 197 | #define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ 198 | #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ 199 | #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ 200 | #define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ 201 | #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ 202 | #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ 203 | #define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ 204 | #define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ 205 | #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ 206 | #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ 207 | #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ 208 | #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ 209 | #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ 210 | #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ 211 | #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ 212 | #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ 213 | #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ 214 | #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ 215 | #define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ 216 | #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ 217 | #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ 218 | #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ 219 | #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ 220 | 221 | /* ########################### Ethernet Configuration ######################### */ 222 | #define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */ 223 | #define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */ 224 | 225 | #define ETH_MAC_ADDR0 ((uint8_t)0x02) 226 | #define ETH_MAC_ADDR1 ((uint8_t)0x00) 227 | #define ETH_MAC_ADDR2 ((uint8_t)0x00) 228 | #define ETH_MAC_ADDR3 ((uint8_t)0x00) 229 | #define ETH_MAC_ADDR4 ((uint8_t)0x00) 230 | #define ETH_MAC_ADDR5 ((uint8_t)0x00) 231 | 232 | /* ########################## Assert Selection ############################## */ 233 | /** 234 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 235 | * HAL drivers code 236 | */ 237 | /* #define USE_FULL_ASSERT 1U */ 238 | 239 | /* Includes ------------------------------------------------------------------*/ 240 | /** 241 | * @brief Include module's header file 242 | */ 243 | 244 | #ifdef HAL_RCC_MODULE_ENABLED 245 | #include "stm32h7xx_hal_rcc.h" 246 | #endif /* HAL_RCC_MODULE_ENABLED */ 247 | 248 | #ifdef HAL_GPIO_MODULE_ENABLED 249 | #include "stm32h7xx_hal_gpio.h" 250 | #endif /* HAL_GPIO_MODULE_ENABLED */ 251 | 252 | #ifdef HAL_DMA_MODULE_ENABLED 253 | #include "stm32h7xx_hal_dma.h" 254 | #endif /* HAL_DMA_MODULE_ENABLED */ 255 | 256 | #ifdef HAL_MDMA_MODULE_ENABLED 257 | #include "stm32h7xx_hal_mdma.h" 258 | #endif /* HAL_MDMA_MODULE_ENABLED */ 259 | 260 | #ifdef HAL_HASH_MODULE_ENABLED 261 | #include "stm32h7xx_hal_hash.h" 262 | #endif /* HAL_HASH_MODULE_ENABLED */ 263 | 264 | #ifdef HAL_DCMI_MODULE_ENABLED 265 | #include "stm32h7xx_hal_dcmi.h" 266 | #endif /* HAL_DCMI_MODULE_ENABLED */ 267 | 268 | #ifdef HAL_DMA2D_MODULE_ENABLED 269 | #include "stm32h7xx_hal_dma2d.h" 270 | #endif /* HAL_DMA2D_MODULE_ENABLED */ 271 | 272 | #ifdef HAL_DSI_MODULE_ENABLED 273 | #include "stm32h7xx_hal_dsi.h" 274 | #endif /* HAL_DSI_MODULE_ENABLED */ 275 | 276 | #ifdef HAL_DFSDM_MODULE_ENABLED 277 | #include "stm32h7xx_hal_dfsdm.h" 278 | #endif /* HAL_DFSDM_MODULE_ENABLED */ 279 | 280 | #ifdef HAL_ETH_MODULE_ENABLED 281 | #include "stm32h7xx_hal_eth.h" 282 | #endif /* HAL_ETH_MODULE_ENABLED */ 283 | 284 | #ifdef HAL_EXTI_MODULE_ENABLED 285 | #include "stm32h7xx_hal_exti.h" 286 | #endif /* HAL_EXTI_MODULE_ENABLED */ 287 | 288 | #ifdef HAL_CORTEX_MODULE_ENABLED 289 | #include "stm32h7xx_hal_cortex.h" 290 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 291 | 292 | #ifdef HAL_ADC_MODULE_ENABLED 293 | #include "stm32h7xx_hal_adc.h" 294 | #endif /* HAL_ADC_MODULE_ENABLED */ 295 | 296 | #ifdef HAL_FDCAN_MODULE_ENABLED 297 | #include "stm32h7xx_hal_fdcan.h" 298 | #endif /* HAL_FDCAN_MODULE_ENABLED */ 299 | 300 | #ifdef HAL_CEC_MODULE_ENABLED 301 | #include "stm32h7xx_hal_cec.h" 302 | #endif /* HAL_CEC_MODULE_ENABLED */ 303 | 304 | #ifdef HAL_COMP_MODULE_ENABLED 305 | #include "stm32h7xx_hal_comp.h" 306 | #endif /* HAL_COMP_MODULE_ENABLED */ 307 | 308 | #ifdef HAL_CORDIC_MODULE_ENABLED 309 | #include "stm32h7xx_hal_cordic.h" 310 | #endif /* HAL_CORDIC_MODULE_ENABLED */ 311 | 312 | #ifdef HAL_CRC_MODULE_ENABLED 313 | #include "stm32h7xx_hal_crc.h" 314 | #endif /* HAL_CRC_MODULE_ENABLED */ 315 | 316 | #ifdef HAL_CRYP_MODULE_ENABLED 317 | #include "stm32h7xx_hal_cryp.h" 318 | #endif /* HAL_CRYP_MODULE_ENABLED */ 319 | 320 | #ifdef HAL_DAC_MODULE_ENABLED 321 | #include "stm32h7xx_hal_dac.h" 322 | #endif /* HAL_DAC_MODULE_ENABLED */ 323 | 324 | #ifdef HAL_FLASH_MODULE_ENABLED 325 | #include "stm32h7xx_hal_flash.h" 326 | #endif /* HAL_FLASH_MODULE_ENABLED */ 327 | 328 | #ifdef HAL_FMAC_MODULE_ENABLED 329 | #include "stm32h7xx_hal_fmac.h" 330 | #endif /* HAL_FMAC_MODULE_ENABLED */ 331 | 332 | #ifdef HAL_GFXMMU_MODULE_ENABLED 333 | #include "stm32h7xx_hal_gfxmmu.h" 334 | #endif /* HAL_GFXMMU_MODULE_ENABLED */ 335 | 336 | #ifdef HAL_HRTIM_MODULE_ENABLED 337 | #include "stm32h7xx_hal_hrtim.h" 338 | #endif /* HAL_HRTIM_MODULE_ENABLED */ 339 | 340 | #ifdef HAL_HSEM_MODULE_ENABLED 341 | #include "stm32h7xx_hal_hsem.h" 342 | #endif /* HAL_HSEM_MODULE_ENABLED */ 343 | 344 | #ifdef HAL_SRAM_MODULE_ENABLED 345 | #include "stm32h7xx_hal_sram.h" 346 | #endif /* HAL_SRAM_MODULE_ENABLED */ 347 | 348 | #ifdef HAL_NOR_MODULE_ENABLED 349 | #include "stm32h7xx_hal_nor.h" 350 | #endif /* HAL_NOR_MODULE_ENABLED */ 351 | 352 | #ifdef HAL_NAND_MODULE_ENABLED 353 | #include "stm32h7xx_hal_nand.h" 354 | #endif /* HAL_NAND_MODULE_ENABLED */ 355 | 356 | #ifdef HAL_I2C_MODULE_ENABLED 357 | #include "stm32h7xx_hal_i2c.h" 358 | #endif /* HAL_I2C_MODULE_ENABLED */ 359 | 360 | #ifdef HAL_I2S_MODULE_ENABLED 361 | #include "stm32h7xx_hal_i2s.h" 362 | #endif /* HAL_I2S_MODULE_ENABLED */ 363 | 364 | #ifdef HAL_IWDG_MODULE_ENABLED 365 | #include "stm32h7xx_hal_iwdg.h" 366 | #endif /* HAL_IWDG_MODULE_ENABLED */ 367 | 368 | #ifdef HAL_JPEG_MODULE_ENABLED 369 | #include "stm32h7xx_hal_jpeg.h" 370 | #endif /* HAL_JPEG_MODULE_ENABLED */ 371 | 372 | #ifdef HAL_MDIOS_MODULE_ENABLED 373 | #include "stm32h7xx_hal_mdios.h" 374 | #endif /* HAL_MDIOS_MODULE_ENABLED */ 375 | 376 | #ifdef HAL_MMC_MODULE_ENABLED 377 | #include "stm32h7xx_hal_mmc.h" 378 | #endif /* HAL_MMC_MODULE_ENABLED */ 379 | 380 | #ifdef HAL_LPTIM_MODULE_ENABLED 381 | #include "stm32h7xx_hal_lptim.h" 382 | #endif /* HAL_LPTIM_MODULE_ENABLED */ 383 | 384 | #ifdef HAL_LTDC_MODULE_ENABLED 385 | #include "stm32h7xx_hal_ltdc.h" 386 | #endif /* HAL_LTDC_MODULE_ENABLED */ 387 | 388 | #ifdef HAL_OPAMP_MODULE_ENABLED 389 | #include "stm32h7xx_hal_opamp.h" 390 | #endif /* HAL_OPAMP_MODULE_ENABLED */ 391 | 392 | #ifdef HAL_OSPI_MODULE_ENABLED 393 | #include "stm32h7xx_hal_ospi.h" 394 | #endif /* HAL_OSPI_MODULE_ENABLED */ 395 | 396 | #ifdef HAL_OTFDEC_MODULE_ENABLED 397 | #include "stm32h7xx_hal_otfdec.h" 398 | #endif /* HAL_OTFDEC_MODULE_ENABLED */ 399 | 400 | #ifdef HAL_PWR_MODULE_ENABLED 401 | #include "stm32h7xx_hal_pwr.h" 402 | #endif /* HAL_PWR_MODULE_ENABLED */ 403 | 404 | #ifdef HAL_QSPI_MODULE_ENABLED 405 | #include "stm32h7xx_hal_qspi.h" 406 | #endif /* HAL_QSPI_MODULE_ENABLED */ 407 | 408 | #ifdef HAL_RAMECC_MODULE_ENABLED 409 | #include "stm32h7xx_hal_ramecc.h" 410 | #endif /* HAL_HCD_MODULE_ENABLED */ 411 | 412 | #ifdef HAL_RNG_MODULE_ENABLED 413 | #include "stm32h7xx_hal_rng.h" 414 | #endif /* HAL_RNG_MODULE_ENABLED */ 415 | 416 | #ifdef HAL_RTC_MODULE_ENABLED 417 | #include "stm32h7xx_hal_rtc.h" 418 | #endif /* HAL_RTC_MODULE_ENABLED */ 419 | 420 | #ifdef HAL_SAI_MODULE_ENABLED 421 | #include "stm32h7xx_hal_sai.h" 422 | #endif /* HAL_SAI_MODULE_ENABLED */ 423 | 424 | #ifdef HAL_SD_MODULE_ENABLED 425 | #include "stm32h7xx_hal_sd.h" 426 | #endif /* HAL_SD_MODULE_ENABLED */ 427 | 428 | #ifdef HAL_SDRAM_MODULE_ENABLED 429 | #include "stm32h7xx_hal_sdram.h" 430 | #endif /* HAL_SDRAM_MODULE_ENABLED */ 431 | 432 | #ifdef HAL_SPI_MODULE_ENABLED 433 | #include "stm32h7xx_hal_spi.h" 434 | #endif /* HAL_SPI_MODULE_ENABLED */ 435 | 436 | #ifdef HAL_SPDIFRX_MODULE_ENABLED 437 | #include "stm32h7xx_hal_spdifrx.h" 438 | #endif /* HAL_SPDIFRX_MODULE_ENABLED */ 439 | 440 | #ifdef HAL_SWPMI_MODULE_ENABLED 441 | #include "stm32h7xx_hal_swpmi.h" 442 | #endif /* HAL_SWPMI_MODULE_ENABLED */ 443 | 444 | #ifdef HAL_TIM_MODULE_ENABLED 445 | #include "stm32h7xx_hal_tim.h" 446 | #endif /* HAL_TIM_MODULE_ENABLED */ 447 | 448 | #ifdef HAL_UART_MODULE_ENABLED 449 | #include "stm32h7xx_hal_uart.h" 450 | #endif /* HAL_UART_MODULE_ENABLED */ 451 | 452 | #ifdef HAL_USART_MODULE_ENABLED 453 | #include "stm32h7xx_hal_usart.h" 454 | #endif /* HAL_USART_MODULE_ENABLED */ 455 | 456 | #ifdef HAL_IRDA_MODULE_ENABLED 457 | #include "stm32h7xx_hal_irda.h" 458 | #endif /* HAL_IRDA_MODULE_ENABLED */ 459 | 460 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 461 | #include "stm32h7xx_hal_smartcard.h" 462 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 463 | 464 | #ifdef HAL_SMBUS_MODULE_ENABLED 465 | #include "stm32h7xx_hal_smbus.h" 466 | #endif /* HAL_SMBUS_MODULE_ENABLED */ 467 | 468 | #ifdef HAL_WWDG_MODULE_ENABLED 469 | #include "stm32h7xx_hal_wwdg.h" 470 | #endif /* HAL_WWDG_MODULE_ENABLED */ 471 | 472 | #ifdef HAL_PCD_MODULE_ENABLED 473 | #include "stm32h7xx_hal_pcd.h" 474 | #endif /* HAL_PCD_MODULE_ENABLED */ 475 | 476 | #ifdef HAL_HCD_MODULE_ENABLED 477 | #include "stm32h7xx_hal_hcd.h" 478 | #endif /* HAL_HCD_MODULE_ENABLED */ 479 | 480 | #ifdef HAL_PSSI_MODULE_ENABLED 481 | #include "stm32h7xx_hal_pssi.h" 482 | #endif /* HAL_PSSI_MODULE_ENABLED */ 483 | 484 | #ifdef HAL_DTS_MODULE_ENABLED 485 | #include "stm32h7xx_hal_dts.h" 486 | #endif /* HAL_DTS_MODULE_ENABLED */ 487 | 488 | /* Exported macro ------------------------------------------------------------*/ 489 | #ifdef USE_FULL_ASSERT 490 | /** 491 | * @brief The assert_param macro is used for function's parameters check. 492 | * @param expr: If expr is false, it calls assert_failed function 493 | * which reports the name of the source file and the source 494 | * line number of the call that failed. 495 | * If expr is true, it returns no value. 496 | * @retval None 497 | */ 498 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 499 | /* Exported functions ------------------------------------------------------- */ 500 | void assert_failed(uint8_t* file, uint32_t line); 501 | #else 502 | #define assert_param(expr) ((void)0U) 503 | #endif /* USE_FULL_ASSERT */ 504 | 505 | #ifdef __cplusplus 506 | } 507 | #endif 508 | 509 | #endif /* __STM32H7xx_HAL_CONF_H */ 510 | 511 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 512 | -------------------------------------------------------------------------------- /startup_stm32h7b0xx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32h7b0xx.s 4 | * @author MCD Application Team 5 | * @brief STM32H7B0xx Devices vector table for GCC based toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | *

© Copyright (c) 2019 STMicroelectronics. 18 | * All rights reserved.

19 | * 20 | * This software component is licensed by ST under BSD 3-Clause license, 21 | * the "License"; You may not use this file except in compliance with the 22 | * License. You may obtain a copy of the License at: 23 | * opensource.org/licenses/BSD-3-Clause 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | .syntax unified 29 | .cpu cortex-m7 30 | .fpu softvfp 31 | .thumb 32 | 33 | .global g_pfnVectors 34 | .global Default_Handler 35 | 36 | /* start address for the initialization values of the .data section. 37 | defined in linker script */ 38 | .word _sidata 39 | /* start address for the .data section. defined in linker script */ 40 | .word _sdata 41 | /* end address for the .data section. defined in linker script */ 42 | .word _edata 43 | /* start address for the .bss section. defined in linker script */ 44 | .word _sbss 45 | /* end address for the .bss section. defined in linker script */ 46 | .word _ebss 47 | /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ 48 | 49 | /** 50 | * @brief This is the code that gets called when the processor first 51 | * starts execution following a reset event. Only the absolutely 52 | * necessary set is performed, after which the application 53 | * supplied main() routine is called. 54 | * @param None 55 | * @retval : None 56 | */ 57 | 58 | .section .text.Reset_Handler 59 | .weak Reset_Handler 60 | .type Reset_Handler, %function 61 | Reset_Handler: 62 | ldr sp, =_estack /* set stack pointer */ 63 | 64 | /* Call the clock system intitialization function.*/ 65 | bl SystemInit 66 | 67 | /* Copy the data segment initializers from flash to SRAM */ 68 | movs r1, #0 69 | b LoopCopyDataInit 70 | 71 | CopyDataInit: 72 | ldr r3, =_sidata 73 | ldr r3, [r3, r1] 74 | str r3, [r0, r1] 75 | adds r1, r1, #4 76 | 77 | LoopCopyDataInit: 78 | ldr r0, =_sdata 79 | ldr r3, =_edata 80 | adds r2, r0, r1 81 | cmp r2, r3 82 | bcc CopyDataInit 83 | ldr r2, =_sbss 84 | b LoopFillZerobss 85 | /* Zero fill the bss segment. */ 86 | FillZerobss: 87 | movs r3, #0 88 | str r3, [r2], #4 89 | 90 | LoopFillZerobss: 91 | ldr r3, = _ebss 92 | cmp r2, r3 93 | bcc FillZerobss 94 | 95 | /* Call static constructors */ 96 | bl __libc_init_array 97 | /* Call the application's entry point.*/ 98 | bl main 99 | bx lr 100 | .size Reset_Handler, .-Reset_Handler 101 | 102 | /** 103 | * @brief This is the code that gets called when the processor receives an 104 | * unexpected interrupt. This simply enters an infinite loop, preserving 105 | * the system state for examination by a debugger. 106 | * @param None 107 | * @retval None 108 | */ 109 | .section .text.Default_Handler,"ax",%progbits 110 | Default_Handler: 111 | Infinite_Loop: 112 | b Infinite_Loop 113 | .size Default_Handler, .-Default_Handler 114 | /****************************************************************************** 115 | * 116 | * The minimal vector table for a Cortex M. Note that the proper constructs 117 | * must be placed on this to ensure that it ends up at physical address 118 | * 0x0000.0000. 119 | * 120 | *******************************************************************************/ 121 | .section .isr_vector,"a",%progbits 122 | .type g_pfnVectors, %object 123 | .size g_pfnVectors, .-g_pfnVectors 124 | 125 | 126 | g_pfnVectors: 127 | .word _estack 128 | .word Reset_Handler 129 | 130 | .word NMI_Handler 131 | .word HardFault_Handler 132 | .word MemManage_Handler 133 | .word BusFault_Handler 134 | .word UsageFault_Handler 135 | .word 0 136 | .word 0 137 | .word 0 138 | .word 0 139 | .word SVC_Handler 140 | .word DebugMon_Handler 141 | .word 0 142 | .word PendSV_Handler 143 | .word SysTick_Handler 144 | 145 | /* External Interrupts */ 146 | .word WWDG_IRQHandler /* Window WatchDog */ 147 | .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ 148 | .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */ 149 | .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ 150 | .word FLASH_IRQHandler /* FLASH */ 151 | .word RCC_IRQHandler /* RCC */ 152 | .word EXTI0_IRQHandler /* EXTI Line0 */ 153 | .word EXTI1_IRQHandler /* EXTI Line1 */ 154 | .word EXTI2_IRQHandler /* EXTI Line2 */ 155 | .word EXTI3_IRQHandler /* EXTI Line3 */ 156 | .word EXTI4_IRQHandler /* EXTI Line4 */ 157 | .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ 158 | .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ 159 | .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ 160 | .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ 161 | .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ 162 | .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ 163 | .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ 164 | .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ 165 | .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ 166 | .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ 167 | .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ 168 | .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ 169 | .word EXTI9_5_IRQHandler /* External Line[9:5]s */ 170 | .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ 171 | .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ 172 | .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ 173 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 174 | .word TIM2_IRQHandler /* TIM2 */ 175 | .word TIM3_IRQHandler /* TIM3 */ 176 | .word TIM4_IRQHandler /* TIM4 */ 177 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 178 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 179 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 180 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 181 | .word SPI1_IRQHandler /* SPI1 */ 182 | .word SPI2_IRQHandler /* SPI2 */ 183 | .word USART1_IRQHandler /* USART1 */ 184 | .word USART2_IRQHandler /* USART2 */ 185 | .word USART3_IRQHandler /* USART3 */ 186 | .word EXTI15_10_IRQHandler /* External Line[15:10]s */ 187 | .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ 188 | .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */ 189 | .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ 190 | .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ 191 | .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ 192 | .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ 193 | .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ 194 | .word FMC_IRQHandler /* FMC */ 195 | .word SDMMC1_IRQHandler /* SDMMC1 */ 196 | .word TIM5_IRQHandler /* TIM5 */ 197 | .word SPI3_IRQHandler /* SPI3 */ 198 | .word UART4_IRQHandler /* UART4 */ 199 | .word UART5_IRQHandler /* UART5 */ 200 | .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ 201 | .word TIM7_IRQHandler /* TIM7 */ 202 | .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ 203 | .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ 204 | .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ 205 | .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ 206 | .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ 207 | .word 0 /* Reserved */ 208 | .word 0 /* Reserved */ 209 | .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ 210 | .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */ 211 | .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */ 212 | .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */ 213 | .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */ 214 | .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ 215 | .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ 216 | .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ 217 | .word USART6_IRQHandler /* USART6 */ 218 | .word I2C3_EV_IRQHandler /* I2C3 event */ 219 | .word I2C3_ER_IRQHandler /* I2C3 error */ 220 | .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ 221 | .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ 222 | .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ 223 | .word OTG_HS_IRQHandler /* USB OTG HS */ 224 | .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ 225 | .word CRYP_IRQHandler /* CRYP crypto global interrupt */ 226 | .word HASH_RNG_IRQHandler /* RNG, HASH */ 227 | .word FPU_IRQHandler /* FPU */ 228 | .word UART7_IRQHandler /* UART7 */ 229 | .word UART8_IRQHandler /* UART8 */ 230 | .word SPI4_IRQHandler /* SPI4 */ 231 | .word SPI5_IRQHandler /* SPI5 */ 232 | .word SPI6_IRQHandler /* SPI6 */ 233 | .word SAI1_IRQHandler /* SAI1 */ 234 | .word LTDC_IRQHandler /* LTDC */ 235 | .word LTDC_ER_IRQHandler /* LTDC error */ 236 | .word DMA2D_IRQHandler /* DMA2D */ 237 | .word SAI2_IRQHandler /* SAI2 */ 238 | .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ 239 | .word LPTIM1_IRQHandler /* LPTIM1 */ 240 | .word CEC_IRQHandler /* HDMI_CEC */ 241 | .word I2C4_EV_IRQHandler /* I2C4 Event */ 242 | .word I2C4_ER_IRQHandler /* I2C4 Error */ 243 | .word SPDIF_RX_IRQHandler /* SPDIF_RX */ 244 | .word 0 /* Reserved */ 245 | .word 0 /* Reserved */ 246 | .word 0 /* Reserved */ 247 | .word 0 /* Reserved */ 248 | .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ 249 | .word 0 /* Reserved */ 250 | .word 0 /* Reserved */ 251 | .word 0 /* Reserved */ 252 | .word 0 /* Reserved */ 253 | .word 0 /* Reserved */ 254 | .word 0 /* Reserved */ 255 | .word 0 /* Reserved */ 256 | .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ 257 | .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ 258 | .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ 259 | .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ 260 | .word 0 /* Reserved */ 261 | .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ 262 | .word TIM15_IRQHandler /* TIM15 global Interrupt */ 263 | .word TIM16_IRQHandler /* TIM16 global Interrupt */ 264 | .word TIM17_IRQHandler /* TIM17 global Interrupt */ 265 | .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ 266 | .word MDIOS_IRQHandler /* MDIOS global Interrupt */ 267 | .word JPEG_IRQHandler /* JPEG global Interrupt */ 268 | .word MDMA_IRQHandler /* MDMA global Interrupt */ 269 | .word 0 /* Reserved */ 270 | .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ 271 | .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ 272 | .word 0 /* Reserved */ 273 | .word DAC2_IRQHandler /* DAC2 global Interrupt */ 274 | .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ 275 | .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */ 276 | .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */ 277 | .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */ 278 | .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */ 279 | .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */ 280 | .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */ 281 | .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */ 282 | .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */ 283 | .word COMP_IRQHandler /* COMP global Interrupt */ 284 | .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ 285 | .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ 286 | .word UART9_IRQHandler /* UART9 global interrupt */ 287 | .word USART10_IRQHandler /* USART10 global interrupt */ 288 | .word LPUART1_IRQHandler /* LP UART1 interrupt */ 289 | .word 0 /* Reserved */ 290 | .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ 291 | .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ 292 | .word 0 /* Reserved */ 293 | .word DTS_IRQHandler /* DTS */ 294 | .word 0 /* Reserved */ 295 | .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ 296 | .word OCTOSPI2_IRQHandler /* OCTOSPI2 */ 297 | .word OTFDEC1_IRQHandler /* OTFDEC1 */ 298 | .word OTFDEC2_IRQHandler /* OTFDEC2 */ 299 | .word GFXMMU_IRQHandler /* GFXMMU */ 300 | .word BDMA1_IRQHandler /* BDMA1 */ 301 | 302 | /******************************************************************************* 303 | * 304 | * Provide weak aliases for each Exception handler to the Default_Handler. 305 | * As they are weak aliases, any function with the same name will override 306 | * this definition. 307 | * 308 | *******************************************************************************/ 309 | .weak NMI_Handler 310 | .thumb_set NMI_Handler,Default_Handler 311 | 312 | .weak HardFault_Handler 313 | .thumb_set HardFault_Handler,Default_Handler 314 | 315 | .weak MemManage_Handler 316 | .thumb_set MemManage_Handler,Default_Handler 317 | 318 | .weak BusFault_Handler 319 | .thumb_set BusFault_Handler,Default_Handler 320 | 321 | .weak UsageFault_Handler 322 | .thumb_set UsageFault_Handler,Default_Handler 323 | 324 | .weak SVC_Handler 325 | .thumb_set SVC_Handler,Default_Handler 326 | 327 | .weak DebugMon_Handler 328 | .thumb_set DebugMon_Handler,Default_Handler 329 | 330 | .weak PendSV_Handler 331 | .thumb_set PendSV_Handler,Default_Handler 332 | 333 | .weak SysTick_Handler 334 | .thumb_set SysTick_Handler,Default_Handler 335 | 336 | .weak WWDG_IRQHandler 337 | .thumb_set WWDG_IRQHandler,Default_Handler 338 | 339 | .weak PVD_PVM_IRQHandler 340 | .thumb_set PVD_PVM_IRQHandler,Default_Handler 341 | 342 | .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler 343 | .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler 344 | 345 | .weak RTC_WKUP_IRQHandler 346 | .thumb_set RTC_WKUP_IRQHandler,Default_Handler 347 | 348 | .weak FLASH_IRQHandler 349 | .thumb_set FLASH_IRQHandler,Default_Handler 350 | 351 | .weak RCC_IRQHandler 352 | .thumb_set RCC_IRQHandler,Default_Handler 353 | 354 | .weak EXTI0_IRQHandler 355 | .thumb_set EXTI0_IRQHandler,Default_Handler 356 | 357 | .weak EXTI1_IRQHandler 358 | .thumb_set EXTI1_IRQHandler,Default_Handler 359 | 360 | .weak EXTI2_IRQHandler 361 | .thumb_set EXTI2_IRQHandler,Default_Handler 362 | 363 | .weak EXTI3_IRQHandler 364 | .thumb_set EXTI3_IRQHandler,Default_Handler 365 | 366 | .weak EXTI4_IRQHandler 367 | .thumb_set EXTI4_IRQHandler,Default_Handler 368 | 369 | .weak DMA1_Stream0_IRQHandler 370 | .thumb_set DMA1_Stream0_IRQHandler,Default_Handler 371 | 372 | .weak DMA1_Stream1_IRQHandler 373 | .thumb_set DMA1_Stream1_IRQHandler,Default_Handler 374 | 375 | .weak DMA1_Stream2_IRQHandler 376 | .thumb_set DMA1_Stream2_IRQHandler,Default_Handler 377 | 378 | .weak DMA1_Stream3_IRQHandler 379 | .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 380 | 381 | .weak DMA1_Stream4_IRQHandler 382 | .thumb_set DMA1_Stream4_IRQHandler,Default_Handler 383 | 384 | .weak DMA1_Stream5_IRQHandler 385 | .thumb_set DMA1_Stream5_IRQHandler,Default_Handler 386 | 387 | .weak DMA1_Stream6_IRQHandler 388 | .thumb_set DMA1_Stream6_IRQHandler,Default_Handler 389 | 390 | .weak ADC_IRQHandler 391 | .thumb_set ADC_IRQHandler,Default_Handler 392 | 393 | .weak FDCAN1_IT0_IRQHandler 394 | .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler 395 | 396 | .weak FDCAN2_IT0_IRQHandler 397 | .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler 398 | 399 | .weak FDCAN1_IT1_IRQHandler 400 | .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler 401 | 402 | .weak FDCAN2_IT1_IRQHandler 403 | .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler 404 | 405 | .weak EXTI9_5_IRQHandler 406 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 407 | 408 | .weak TIM1_BRK_IRQHandler 409 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 410 | 411 | .weak TIM1_UP_IRQHandler 412 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 413 | 414 | .weak TIM1_TRG_COM_IRQHandler 415 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 416 | 417 | .weak TIM1_CC_IRQHandler 418 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 419 | 420 | .weak TIM2_IRQHandler 421 | .thumb_set TIM2_IRQHandler,Default_Handler 422 | 423 | .weak TIM3_IRQHandler 424 | .thumb_set TIM3_IRQHandler,Default_Handler 425 | 426 | .weak TIM4_IRQHandler 427 | .thumb_set TIM4_IRQHandler,Default_Handler 428 | 429 | .weak I2C1_EV_IRQHandler 430 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 431 | 432 | .weak I2C1_ER_IRQHandler 433 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 434 | 435 | .weak I2C2_EV_IRQHandler 436 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 437 | 438 | .weak I2C2_ER_IRQHandler 439 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 440 | 441 | .weak SPI1_IRQHandler 442 | .thumb_set SPI1_IRQHandler,Default_Handler 443 | 444 | .weak SPI2_IRQHandler 445 | .thumb_set SPI2_IRQHandler,Default_Handler 446 | 447 | .weak USART1_IRQHandler 448 | .thumb_set USART1_IRQHandler,Default_Handler 449 | 450 | .weak USART2_IRQHandler 451 | .thumb_set USART2_IRQHandler,Default_Handler 452 | 453 | .weak USART3_IRQHandler 454 | .thumb_set USART3_IRQHandler,Default_Handler 455 | 456 | .weak EXTI15_10_IRQHandler 457 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 458 | 459 | .weak RTC_Alarm_IRQHandler 460 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 461 | 462 | .weak DFSDM2_IRQHandler 463 | .thumb_set DFSDM2_IRQHandler,Default_Handler 464 | 465 | .weak TIM8_BRK_TIM12_IRQHandler 466 | .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler 467 | 468 | .weak TIM8_UP_TIM13_IRQHandler 469 | .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler 470 | 471 | .weak TIM8_TRG_COM_TIM14_IRQHandler 472 | .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler 473 | 474 | .weak TIM8_CC_IRQHandler 475 | .thumb_set TIM8_CC_IRQHandler,Default_Handler 476 | 477 | .weak DMA1_Stream7_IRQHandler 478 | .thumb_set DMA1_Stream7_IRQHandler,Default_Handler 479 | 480 | .weak FMC_IRQHandler 481 | .thumb_set FMC_IRQHandler,Default_Handler 482 | 483 | .weak SDMMC1_IRQHandler 484 | .thumb_set SDMMC1_IRQHandler,Default_Handler 485 | 486 | .weak TIM5_IRQHandler 487 | .thumb_set TIM5_IRQHandler,Default_Handler 488 | 489 | .weak SPI3_IRQHandler 490 | .thumb_set SPI3_IRQHandler,Default_Handler 491 | 492 | .weak UART4_IRQHandler 493 | .thumb_set UART4_IRQHandler,Default_Handler 494 | 495 | .weak UART5_IRQHandler 496 | .thumb_set UART5_IRQHandler,Default_Handler 497 | 498 | .weak TIM6_DAC_IRQHandler 499 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 500 | 501 | .weak TIM7_IRQHandler 502 | .thumb_set TIM7_IRQHandler,Default_Handler 503 | 504 | .weak DMA2_Stream0_IRQHandler 505 | .thumb_set DMA2_Stream0_IRQHandler,Default_Handler 506 | 507 | .weak DMA2_Stream1_IRQHandler 508 | .thumb_set DMA2_Stream1_IRQHandler,Default_Handler 509 | 510 | .weak DMA2_Stream2_IRQHandler 511 | .thumb_set DMA2_Stream2_IRQHandler,Default_Handler 512 | 513 | .weak DMA2_Stream3_IRQHandler 514 | .thumb_set DMA2_Stream3_IRQHandler,Default_Handler 515 | 516 | .weak DMA2_Stream4_IRQHandler 517 | .thumb_set DMA2_Stream4_IRQHandler,Default_Handler 518 | 519 | .weak FDCAN_CAL_IRQHandler 520 | .thumb_set FDCAN_CAL_IRQHandler,Default_Handler 521 | 522 | .weak DFSDM1_FLT4_IRQHandler 523 | .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler 524 | 525 | .weak DFSDM1_FLT5_IRQHandler 526 | .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler 527 | 528 | .weak DFSDM1_FLT6_IRQHandler 529 | .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler 530 | 531 | .weak DFSDM1_FLT7_IRQHandler 532 | .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler 533 | 534 | .weak DMA2_Stream5_IRQHandler 535 | .thumb_set DMA2_Stream5_IRQHandler,Default_Handler 536 | 537 | .weak DMA2_Stream6_IRQHandler 538 | .thumb_set DMA2_Stream6_IRQHandler,Default_Handler 539 | 540 | .weak DMA2_Stream7_IRQHandler 541 | .thumb_set DMA2_Stream7_IRQHandler,Default_Handler 542 | 543 | .weak USART6_IRQHandler 544 | .thumb_set USART6_IRQHandler,Default_Handler 545 | 546 | .weak I2C3_EV_IRQHandler 547 | .thumb_set I2C3_EV_IRQHandler,Default_Handler 548 | 549 | .weak I2C3_ER_IRQHandler 550 | .thumb_set I2C3_ER_IRQHandler,Default_Handler 551 | 552 | .weak OTG_HS_EP1_OUT_IRQHandler 553 | .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler 554 | 555 | .weak OTG_HS_EP1_IN_IRQHandler 556 | .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler 557 | 558 | .weak OTG_HS_WKUP_IRQHandler 559 | .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler 560 | 561 | .weak OTG_HS_IRQHandler 562 | .thumb_set OTG_HS_IRQHandler,Default_Handler 563 | 564 | .weak DCMI_PSSI_IRQHandler 565 | .thumb_set DCMI_PSSI_IRQHandler,Default_Handler 566 | 567 | .weak CRYP_IRQHandler 568 | .thumb_set CRYP_IRQHandler,Default_Handler 569 | 570 | .weak HASH_RNG_IRQHandler 571 | .thumb_set HASH_RNG_IRQHandler,Default_Handler 572 | 573 | .weak FPU_IRQHandler 574 | .thumb_set FPU_IRQHandler,Default_Handler 575 | 576 | .weak UART7_IRQHandler 577 | .thumb_set UART7_IRQHandler,Default_Handler 578 | 579 | .weak UART8_IRQHandler 580 | .thumb_set UART8_IRQHandler,Default_Handler 581 | 582 | .weak SPI4_IRQHandler 583 | .thumb_set SPI4_IRQHandler,Default_Handler 584 | 585 | .weak SPI5_IRQHandler 586 | .thumb_set SPI5_IRQHandler,Default_Handler 587 | 588 | .weak SPI6_IRQHandler 589 | .thumb_set SPI6_IRQHandler,Default_Handler 590 | 591 | .weak SAI1_IRQHandler 592 | .thumb_set SAI1_IRQHandler,Default_Handler 593 | 594 | .weak LTDC_IRQHandler 595 | .thumb_set LTDC_IRQHandler,Default_Handler 596 | 597 | .weak LTDC_ER_IRQHandler 598 | .thumb_set LTDC_ER_IRQHandler,Default_Handler 599 | 600 | .weak DMA2D_IRQHandler 601 | .thumb_set DMA2D_IRQHandler,Default_Handler 602 | 603 | .weak SAI2_IRQHandler 604 | .thumb_set SAI2_IRQHandler,Default_Handler 605 | 606 | .weak OCTOSPI1_IRQHandler 607 | .thumb_set OCTOSPI1_IRQHandler,Default_Handler 608 | 609 | .weak LPTIM1_IRQHandler 610 | .thumb_set LPTIM1_IRQHandler,Default_Handler 611 | 612 | .weak CEC_IRQHandler 613 | .thumb_set CEC_IRQHandler,Default_Handler 614 | 615 | .weak I2C4_EV_IRQHandler 616 | .thumb_set I2C4_EV_IRQHandler,Default_Handler 617 | 618 | .weak I2C4_ER_IRQHandler 619 | .thumb_set I2C4_ER_IRQHandler,Default_Handler 620 | 621 | .weak SPDIF_RX_IRQHandler 622 | .thumb_set SPDIF_RX_IRQHandler,Default_Handler 623 | 624 | .weak DMAMUX1_OVR_IRQHandler 625 | .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler 626 | 627 | .weak DFSDM1_FLT0_IRQHandler 628 | .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler 629 | 630 | .weak DFSDM1_FLT1_IRQHandler 631 | .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler 632 | 633 | .weak DFSDM1_FLT2_IRQHandler 634 | .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler 635 | 636 | .weak DFSDM1_FLT3_IRQHandler 637 | .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler 638 | 639 | .weak SWPMI1_IRQHandler 640 | .thumb_set SWPMI1_IRQHandler,Default_Handler 641 | 642 | .weak TIM15_IRQHandler 643 | .thumb_set TIM15_IRQHandler,Default_Handler 644 | 645 | .weak TIM16_IRQHandler 646 | .thumb_set TIM16_IRQHandler,Default_Handler 647 | 648 | .weak TIM17_IRQHandler 649 | .thumb_set TIM17_IRQHandler,Default_Handler 650 | 651 | .weak MDIOS_WKUP_IRQHandler 652 | .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler 653 | 654 | .weak MDIOS_IRQHandler 655 | .thumb_set MDIOS_IRQHandler,Default_Handler 656 | 657 | .weak JPEG_IRQHandler 658 | .thumb_set JPEG_IRQHandler,Default_Handler 659 | 660 | .weak MDMA_IRQHandler 661 | .thumb_set MDMA_IRQHandler,Default_Handler 662 | 663 | .weak SDMMC2_IRQHandler 664 | .thumb_set SDMMC2_IRQHandler,Default_Handler 665 | 666 | .weak HSEM1_IRQHandler 667 | .thumb_set HSEM1_IRQHandler,Default_Handler 668 | 669 | .weak DAC2_IRQHandler 670 | .thumb_set DAC2_IRQHandler,Default_Handler 671 | 672 | .weak DMAMUX2_OVR_IRQHandler 673 | .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler 674 | 675 | .weak BDMA2_Channel0_IRQHandler 676 | .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler 677 | 678 | .weak BDMA2_Channel1_IRQHandler 679 | .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler 680 | 681 | .weak BDMA2_Channel2_IRQHandler 682 | .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler 683 | 684 | .weak BDMA2_Channel3_IRQHandler 685 | .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler 686 | 687 | .weak BDMA2_Channel4_IRQHandler 688 | .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler 689 | 690 | .weak BDMA2_Channel5_IRQHandler 691 | .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler 692 | 693 | .weak BDMA2_Channel6_IRQHandler 694 | .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler 695 | 696 | .weak BDMA2_Channel7_IRQHandler 697 | .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler 698 | 699 | .weak COMP_IRQHandler 700 | .thumb_set COMP_IRQHandler,Default_Handler 701 | 702 | .weak LPTIM2_IRQHandler 703 | .thumb_set LPTIM2_IRQHandler,Default_Handler 704 | 705 | .weak LPTIM3_IRQHandler 706 | .thumb_set LPTIM3_IRQHandler,Default_Handler 707 | 708 | .weak LPTIM4_IRQHandler 709 | .thumb_set LPTIM4_IRQHandler,Default_Handler 710 | 711 | .weak LPTIM5_IRQHandler 712 | .thumb_set LPTIM5_IRQHandler,Default_Handler 713 | 714 | .weak UART9_IRQHandler 715 | .thumb_set UART9_IRQHandler,Default_Handler 716 | 717 | .weak USART10_IRQHandler 718 | .thumb_set USART10_IRQHandler,Default_Handler 719 | 720 | .weak LPUART1_IRQHandler 721 | .thumb_set LPUART1_IRQHandler,Default_Handler 722 | 723 | .weak CRS_IRQHandler 724 | .thumb_set CRS_IRQHandler,Default_Handler 725 | 726 | .weak ECC_IRQHandler 727 | .thumb_set ECC_IRQHandler,Default_Handler 728 | 729 | .weak DTS_IRQHandler 730 | .thumb_set DTS_IRQHandler,Default_Handler 731 | 732 | .weak WAKEUP_PIN_IRQHandler 733 | .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler 734 | 735 | .weak OCTOSPI2_IRQHandler 736 | .thumb_set OCTOSPI2_IRQHandler,Default_Handler 737 | 738 | .weak OTFDEC1_IRQHandler 739 | .thumb_set OTFDEC1_IRQHandler,Default_Handler 740 | 741 | .weak OTFDEC2_IRQHandler 742 | .thumb_set OTFDEC2_IRQHandler,Default_Handler 743 | 744 | .weak GFXMMU_IRQHandler 745 | .thumb_set GFXMMU_IRQHandler,Default_Handler 746 | 747 | .weak BDMA1_IRQHandler 748 | .thumb_set BDMA1_IRQHandler,Default_Handler 749 | 750 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 751 | 752 | --------------------------------------------------------------------------------