├── .DS_Store ├── .gitattributes ├── .gitignore ├── README.md ├── Report.pdf ├── Source ├── .DS_Store ├── Caches │ ├── .DS_Store │ ├── alu.sv │ ├── alu_fpga.sv │ ├── caches.sv │ ├── coherency_control.sv │ ├── control_unit.sv │ ├── datapath.sv │ ├── dcache.sv │ ├── exmem.sv │ ├── forward_unit.sv │ ├── hazard_unit.sv │ ├── icache.sv │ ├── idex.sv │ ├── ifid.sv │ ├── memory_control.sv │ ├── memwb.sv │ ├── multicore.sv │ ├── pc.sv │ ├── pipeline.sv │ ├── ram.sv │ ├── register_file.sv │ ├── register_file_fpga.sv │ ├── request_unit.sv │ ├── singlecycle.sv │ ├── system.sv │ ├── system_fpga.sv │ └── transcript ├── Multicore │ ├── .DS_Store │ ├── alu.sv │ ├── alu_fpga.sv │ ├── caches.sv │ ├── coherency_control.sv │ ├── control_unit.sv │ ├── datapath.sv │ ├── dcache.sv │ ├── exmem.sv │ ├── forward_unit.sv │ ├── hazard_unit.sv │ ├── icache.sv │ ├── idex.sv │ ├── ifid.sv │ ├── memory_control.sv │ ├── memwb.sv │ ├── multicore.sv │ ├── pc.sv │ ├── pipeline.sv │ ├── ram.sv │ ├── register_file.sv │ ├── register_file_fpga.sv │ ├── request_unit.sv │ ├── singlecycle.sv │ ├── system.sv │ ├── system_fpga.sv │ └── transcript ├── Pipeline │ ├── .DS_Store │ ├── alu.sv │ ├── control_unit.sv │ ├── datapath.sv │ ├── exmem.sv │ ├── forward_unit.sv │ ├── hazard_unit.sv │ ├── idex.sv │ ├── ifid.sv │ ├── memory_control.sv │ ├── memwb.sv │ ├── pipeline.sv │ ├── register_file.sv │ ├── singlecycle.sv │ └── system.sv └── asmFiles │ ├── .DS_Store │ ├── dual.llsc.asm │ ├── dual.mergesort.asm │ ├── example.asm │ ├── fib.asm │ ├── search.asm │ ├── subroutine_crc.asm │ ├── subroutine_div.asm │ ├── subroutine_mm.asm │ ├── test.branchjump1.asm │ ├── test.coherence1.asm │ ├── test.coherence2.asm │ ├── test.ldst1.asm │ ├── test.ldst2.asm │ ├── test.loadstore.asm │ └── test.rtype.asm └── Test ├── .DS_Store ├── FPGA ├── .DS_Store ├── alu_fpga.sv ├── register_file_fpga.sv └── system_fpga.sv └── Testbench ├── .DS_Store └── system_tb.sv /.DS_Store: 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