├── .vscode └── tasks.json ├── DOC ├── BLOCK_DIAGRAM │ ├── IFS_SA.drawio │ ├── arbiter.drawio │ └── fd.drawio └── PE.txt ├── IMG ├── CNN_SPEC.PNG ├── Conv_SIM.JPG ├── Conv_SIM_golden.png ├── Conv_layer.png ├── FC.JPG ├── FC_BRAM2.JPG ├── FC_BRAM_Addr.JPG ├── FC_Data_mover_timing_diagram.JPG ├── FC_SIM.JPG ├── MP_BRAM_Addr.JPG ├── MP_Block_digram.JPG ├── MP_SIM.JPG ├── Result_Writer.JPG ├── conv_white.JPG ├── golden_FC.JPG └── golden_MP.JPG ├── LICENSE ├── NOT_USE ├── NOT_USE_HW │ ├── ALU │ │ └── 8_bit_Multiplier │ │ │ ├── Adder │ │ │ ├── Full_adder.v │ │ │ └── Half_adder.v │ │ │ ├── Exact_4_to_2_Comp.v │ │ │ ├── Proposed_InExact_4_to_2_Comp.v │ │ │ ├── eight_bit_multiplier.v │ │ │ ├── eight_bit_multiplier_wallace.v │ │ │ └── tb_eight_bit_multiplier.v │ ├── Adder │ │ ├── Backup │ │ │ ├── CLA4.v │ │ │ ├── CLALogic.v │ │ │ ├── CLA_16.v │ │ │ ├── FullAdder.v │ │ │ └── GPFullAdder.v │ │ ├── CLA.v │ │ └── CLA_tb.v │ ├── BUF │ │ ├── ACC.v │ │ ├── Conv_Data_mover.v │ │ ├── SA_Data_mover.v │ │ ├── dff.v │ │ ├── dff_tb.v │ │ └── fifo.v │ └── etc │ │ ├── GEMM_TOP.v │ │ ├── PE_not_use.v │ │ ├── counter_notuse.v │ │ ├── rf.v │ │ ├── tri_state_buf.v │ │ └── tri_state_bus.v └── NOT_USE_SW │ ├── im2col.c │ ├── im2col.exe │ ├── im2col_v2.c │ ├── im2col_v2.exe │ ├── im2col_v3.c │ ├── main.c │ ├── main.exe │ ├── test.c │ ├── test.exe │ ├── test_2d_malloc.c │ ├── test_2d_malloc.exe │ └── test_pattern_sa.txt ├── README.md ├── RTL ├── AXI │ ├── AXI_to_MEM_buffer.v │ ├── axi_true_dpbram.v │ ├── myip_v1_0.v │ ├── myip_v1_0_S00_AXI.v │ └── myip_v1_0_tb.sv ├── Convolution │ ├── COUNTER │ │ ├── ACC_counter.v │ │ ├── Counter.v │ │ ├── Counter_v2.v │ │ ├── up_counter.v │ │ ├── up_counter_v2.v │ │ ├── up_counter_v3.v │ │ └── up_counter_v4.v │ ├── DATA_MOVER │ │ ├── Conv_Data_mover_v2.v │ │ ├── GLB.v │ │ ├── Ofmap_buffer.v │ │ ├── Ofmap_buffer_v2.v │ │ ├── SA_Data_mover_v2.v │ │ ├── Top_GLB.v │ │ ├── fifo_v2.v │ │ └── shift_buffer.v │ └── MMU │ │ ├── ACC_v2.v │ │ ├── GEMM.v │ │ ├── PE.v │ │ └── SA.v ├── Fully_Connected │ ├── data_mover_bram.v │ ├── fully_connected_core.v │ └── result_writer5.v ├── Max_Pooling │ ├── MP_core14 │ │ ├── Max_Pooling_core.v │ │ ├── Tb_Max_Pooling_core.v │ │ ├── data_mover_bram.v │ │ ├── tb_data_mover_bram.v │ │ └── true_dpbram.v │ └── MP_core7 │ │ ├── Max_Pooling_core.v │ │ ├── Tb_Max_Pooling_core.v │ │ ├── data_mover_bram.v │ │ ├── tb_data_mover_bram.v │ │ └── true_dpbram.v └── Mem │ └── true_dpbram.v ├── SIM ├── ACC_tb.v ├── PE_tb.v ├── SA_tb.v ├── acc_counter_tb.v ├── acc_v2_tb.v ├── counter_tb.v ├── data_mover_core7 │ ├── data_mover_bram.v │ ├── fully_connected_core.v │ ├── result_writer4.v │ ├── tb_data_mover_bram_7core.v │ ├── tb_result_writer4.v │ ├── test_file_core7 │ │ ├── ref_c_rand_input_node_7.txt │ │ ├── ref_c_rand_input_weight_7.txt │ │ └── ref_c_result_7.txt │ └── true_dpbram.v ├── fifo_tb.v ├── fifov2_tb.v ├── rf_tb.v ├── tb_Conv_Data_mover.v ├── tb_GEMM.v ├── tb_GEMM_2.v ├── tb_SA_Data_mover.v ├── tb_Top_GLB.v ├── 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