├── JFlashARM.log ├── JLinkLog.txt ├── JLinkSettings.ini ├── LICENSE.txt ├── Matlab ├── matlab仿真 │ ├── STM32_Voice - 123.txt │ ├── STM32_Voice.asv │ ├── STM32_Voice.m │ ├── dct_arg.c │ ├── hamm.c │ ├── hs_err_pid1932.log │ ├── mfcc_tem.c │ ├── speech_recog.asv │ ├── speech_recog.m │ ├── teat.asv │ ├── teat.m │ ├── tri_cen.c │ ├── tri_even.c │ ├── tri_odd.c │ ├── v1.c │ └── 备份 │ │ ├── MFCC Mel换算 三角滤波器.m │ │ ├── vad ultimate.m │ │ ├── vad 浊音FFT点数对比.m │ │ ├── vad 短时能量 帧移对比.m │ │ ├── vad 短时能量 短时绝对值 短时过零率 2.m │ │ ├── vad 短时能量 短时绝对值 短时过零率.m │ │ └── vad 短时能量 短时绝对值效果对比.m └── 语音样本 │ ├── 01234567989十百千万.wav │ ├── 12345678910 (1).wav │ ├── 12345678910.wav │ ├── 123456789十百千万 (1).wav │ ├── 123456789十百千万 (2).wav │ ├── 123456789十百千万 (3).wav │ ├── STM32 123.txt │ ├── STM32 456.txt │ ├── STM32 noise.txt │ ├── desktop.ini │ ├── 上下前后左右.wav │ ├── 开始暂停结束(1).wav │ ├── 开始暂停结束.wav │ ├── 开始暂停退出.wav │ ├── 语音命令.txt │ ├── 语音库样本 女 8KHz 16bit.wav │ ├── 语音库样本 男 8KHz 16bit.wav │ └── 语音库样本 男 8KHz 8bit.wav ├── Object ├── 语音识别.axf ├── 语音识别.fed ├── 语音识别.hex ├── 语音识别.htm ├── 语音识别.lnp ├── 语音识别.plg ├── 语音识别.sct └── 语音识别.tra ├── README.md ├── Src ├── APP │ ├── includes.h │ └── main.c ├── BSP │ ├── 00000000-00090000 24 dot font.h │ ├── 00090000 24 dot ascii font.h │ ├── 000C0000 16 dot font.h │ ├── ADC.C │ ├── ADC.H │ ├── BSP.c │ ├── BSP.c.orig │ ├── Flash.C │ ├── Flash.H │ ├── SDcard.c │ ├── SDcard.h │ ├── SPI.C │ ├── SPI.C.orig │ ├── SPI.H │ ├── TFTLCD.c │ ├── TFTLCD.c.orig │ ├── USART.C │ ├── USART.C.orig │ ├── USART.H │ ├── bsp.h │ ├── cr4_fft_1024_stm32.s │ ├── delay.c │ ├── delay.h │ ├── spiFlash.c │ ├── spiFlash.c.orig │ ├── spiFlash.h │ ├── spiFlashTable.h │ ├── stdint.h │ ├── tftlcd.h │ ├── touch_panel.c │ ├── touch_panel.c.orig │ ├── touch_panel.h │ └── unicode to gb2312.h ├── CM3_SYS │ ├── core_cm3.c │ └── core_cm3.h ├── FATFS │ ├── FATFS.C │ ├── FATFS.H │ ├── FS_Structure.h │ ├── Interface.C │ └── Interface.h ├── GUI │ ├── GUI.C │ └── GUI.H ├── Speech_Recog │ ├── DTW.C │ ├── DTW.H │ ├── MFCC.C │ ├── MFCC.H │ ├── MFCC_Arg.h │ ├── VAD.C │ └── VAD.H ├── StdPeriph_Driver │ ├── Startup │ │ ├── startup_stm32f10x_cl.s │ │ ├── startup_stm32f10x_hd.s │ │ ├── startup_stm32f10x_hd_vl.s │ │ ├── startup_stm32f10x_ld.s │ │ ├── startup_stm32f10x_ld_vl.s │ │ ├── startup_stm32f10x_md.s │ │ ├── startup_stm32f10x_md_vl.s │ │ └── startup_stm32f10x_xl.s │ ├── inc │ │ ├── misc.h │ │ ├── stm32f10x_adc.h │ │ ├── stm32f10x_bkp.h │ │ ├── stm32f10x_can.h │ │ ├── stm32f10x_cec.h │ │ ├── stm32f10x_crc.h │ │ ├── stm32f10x_dac.h │ │ ├── stm32f10x_dbgmcu.h │ │ ├── stm32f10x_dma.h │ │ ├── stm32f10x_exti.h │ │ ├── stm32f10x_flash.h │ │ ├── stm32f10x_fsmc.h │ │ ├── stm32f10x_gpio.h │ │ ├── stm32f10x_i2c.h │ │ ├── stm32f10x_iwdg.h │ │ ├── stm32f10x_pwr.h │ │ ├── stm32f10x_rcc.h │ │ ├── stm32f10x_rtc.h │ │ ├── stm32f10x_sdio.h │ │ ├── stm32f10x_spi.h │ │ ├── stm32f10x_tim.h │ │ ├── stm32f10x_usart.h │ │ └── stm32f10x_wwdg.h │ ├── src │ │ ├── misc.c │ │ ├── stm32f10x_adc.c │ │ ├── stm32f10x_bkp.c │ │ ├── stm32f10x_can.c │ │ ├── stm32f10x_cec.c │ │ ├── stm32f10x_crc.c │ │ ├── stm32f10x_dac.c │ │ ├── stm32f10x_dbgmcu.c │ │ ├── stm32f10x_dma.c │ │ ├── stm32f10x_exti.c │ │ ├── stm32f10x_flash.c │ │ ├── stm32f10x_fsmc.c │ │ ├── stm32f10x_gpio.c │ │ ├── stm32f10x_i2c.c │ │ ├── stm32f10x_iwdg.c │ │ ├── stm32f10x_pwr.c │ │ ├── stm32f10x_rcc.c │ │ ├── stm32f10x_rtc.c │ │ ├── stm32f10x_sdio.c │ │ ├── stm32f10x_spi.c │ │ ├── stm32f10x_tim.c │ │ ├── stm32f10x_usart.c │ │ └── stm32f10x_wwdg.c │ ├── stm32f10x.h │ ├── stm32f10x_conf.h │ ├── stm32f10x_it.c │ ├── stm32f10x_it.h │ ├── system_stm32f10x.c │ └── system_stm32f10x.h └── after-compile.bat ├── Voice_Rec.BAT ├── download.jflash ├── 基于STM32的孤立词语音识别.pdf ├── 语音识别.plg ├── 语音识别.uvgui.songjian ├── 语音识别.uvgui.宋健 ├── 语音识别.uvgui_SongJian.bak ├── 语音识别.uvgui_宋健.bak ├── 语音识别.uvopt ├── 语音识别.uvproj ├── 语音识别_Target 1.dep ├── 语音识别_Voice_Rec.dep ├── 语音识别_uvopt.bak └── 语音识别_uvproj.bak /JFlashARM.log: -------------------------------------------------------------------------------- 1 | 2 | * 2016-12-20, 00:39:51 3 | Target VCC failure. Please check target voltage. 4 | Wrong AHB ID (15:3). Expected 0x04770001 (Mask 0x0FFFFF0F), Found 0x00000000 5 | Failed to unsecure chip 6 | Failed to connect 7 | Could not erase sectors, not connected 8 | Failed to auto program target -------------------------------------------------------------------------------- /JLinkLog.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/JLinkLog.txt -------------------------------------------------------------------------------- /JLinkSettings.ini: -------------------------------------------------------------------------------- 1 | [BREAKPOINTS] 2 | ShowInfoWin = 1 3 | EnableFlashBP = 2 4 | BPDuringExecution = 0 5 | [CFI] 6 | CFISize = 0x00 7 | CFIAddr = 0x00 8 | [CPU] 9 | OverrideMemMap = 0 10 | AllowSimulation = 1 11 | ScriptFile="" 12 | [FLASH] 13 | MinNumBytesFlashDL = 64 14 | SkipProgOnCRCMatch = 1 15 | VerifyDownload = 1 16 | AllowCaching = 1 17 | EnableFlashDL = 2 18 | Override = 0 19 | Device="AD7160" 20 | [GENERAL] 21 | WorkRAMSize = 0x00 22 | WorkRAMAddr = 0x00 23 | [SWO] 24 | SWOLogFile="" 25 | [MEM] 26 | RdOverrideOrMask = 0x00 27 | RdOverrideAndMask = 0xFFFFFFFF 28 | RdOverrideAddr = 0xFFFFFFFF 29 | WrOverrideOrMask = 0x00 30 | WrOverrideAndMask = 0xFFFFFFFF 31 | WrOverrideAddr = 0xFFFFFFFF 32 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2016 Song Jian http://gk969.com/ 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Matlab/matlab仿真/STM32_Voice.asv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Matlab/matlab仿真/STM32_Voice.asv -------------------------------------------------------------------------------- /Matlab/matlab仿真/STM32_Voice.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Matlab/matlab仿真/STM32_Voice.m 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************************************************************* 2 | ; *** Scatter-Loading Description File generated by uVision *** 3 | ; ************************************************************* 4 | 5 | LR_IROM1 0x08000000 0x00030000 { ; load region size_region 6 | ER_IROM1 0x08000000 0x00030000 { ; load address = execution address 7 | *.o (RESET, +First) 8 | *(InRoot$$Sections) 9 | .ANY (+RO) 10 | } 11 | RW_IRAM1 0x20000000 0x00010000 { ; RW data 12 | .ANY (+RW +ZI) 13 | } 14 | } 15 | 16 | -------------------------------------------------------------------------------- /Object/语音识别.tra: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Object/语音识别.tra -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 基于STM32的孤立词语音识别 2 | 3 | 本设计研究孤立词语音识别系统及其在STM32嵌入式平台上的实现。识别流程是：预滤波、ADC、分帧、端点检测、预加重、加窗、特征提取、特征匹配。端点检测(VAD)采用短时幅度和短时过零率相结合。检测出有效语音后，根据人耳听觉感知特性,计算每帧语音的Mel频率倒谱系数(MFCC)。然后采用动态时间弯折(DTW)算法与特征模板相匹配,最终输出识别结果。先用Matlab对上述算法进行仿真，经多次试验得出算法中所需各系数的最优值。然后将算法移植到STM32嵌入式平台，移植过程中根据嵌入式平台存储空间相对较小、计算能力也相对较弱的实际情况，对算法进行优化。最终设计并制作出基于STM32的孤立词语音识别系统。 4 | 5 | #### 详细介绍： 6 | [基于STM32的孤立词语音识别.pdf](https://github.com/gk969/stm32-speech-recognition/blob/master/%E5%9F%BA%E4%BA%8ESTM32%E7%9A%84%E5%AD%A4%E7%AB%8B%E8%AF%8D%E8%AF%AD%E9%9F%B3%E8%AF%86%E5%88%AB.pdf) 7 | 8 | [http://gk969.com/stm32-speech-recognition/](http://gk969.com/stm32-speech-recognition/) 9 | -------------------------------------------------------------------------------- /Src/APP/includes.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * EXAMPLE CODE 4 | * 5 | * (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL 6 | * 7 | * All rights reserved. Protected by international copyright laws. 8 | * Knowledge of the source code may NOT be used to develop a similar product. 9 | * Please help us continue to provide the Embedded community with the finest 10 | * software available. Your honesty is greatly appreciated. 11 | ********************************************************************************************************* 12 | 13 | ********************************************************************************************************* 14 | */ 15 | 16 | #ifndef __INCLUDES_H__ 17 | #define __INCLUDES_H__ 18 | 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | 26 | #include "stm32f10x_conf.h" 27 | 28 | #include "stm32f10x.h" 29 | 30 | #include "bsp.h" 31 | #include "tftlcd.h" 32 | #include "touch_panel.h" 33 | #include "SPI.h" 34 | #include "spiFlash.h" 35 | #include "SDcard.h" 36 | #include "FATFS.H" 37 | #include "USART.H" 38 | //#include "delay.h" 39 | #include "ADC.h" 40 | 41 | #endif 42 | 43 | -------------------------------------------------------------------------------- /Src/APP/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/APP/main.c -------------------------------------------------------------------------------- /Src/BSP/ADC.C: -------------------------------------------------------------------------------- 1 | #include "stm32f10x_conf.h" 2 | #include "stm32f10x.h" 3 | #include "ADC.h" 4 | #include "USART.H" 5 | #include "delay.h" 6 | #include "TFTLCD.h" 7 | #include 8 | 9 | extern u16 VcBuf[]; 10 | 11 | void ADC_DMA_Init(void) 12 | { 13 | GPIO_InitTypeDef GPIO_InitStructure; 14 | ADC_InitTypeDef ADC_InitStructure; 15 | DMA_InitTypeDef DMA_InitStructure; 16 | 17 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; 18 | TIM_OCInitTypeDef TIM_OCInitStructure; 19 | 20 | RCC_ADCCLKConfig(RCC_PCLK2_Div8); 21 | 22 | /* Enable peripheral clocks ------------------------------------------------*/ 23 | /* Enable DMA1 clock */ 24 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); 25 | 26 | /* Enable ADC1 and GPIOC clock */ 27 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_TIM1, ENABLE); 28 | 29 | /* Configure PA.01 (ADC Channel1) as analog input -------------------------*/ 30 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; 31 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; 32 | GPIO_Init(GPIOA, &GPIO_InitStructure); 33 | 34 | /* TIM1 configuration ------------------------------------------------------*/ 35 | /* Time Base configuration */ 36 | TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); 37 | TIM_TimeBaseStructure.TIM_Period = 90; 38 | TIM_TimeBaseStructure.TIM_Prescaler = 100; 39 | TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; 40 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; 41 | TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); 42 | /* TIM1 channel1 configuration in PWM mode */ 43 | TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; 44 | TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; 45 | TIM_OCInitStructure.TIM_Pulse = 0x10; 46 | TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; 47 | TIM_OC1Init(TIM1, &TIM_OCInitStructure); 48 | 49 | /* TIM1 counter enable */ 50 | //TIM_Cmd(TIM1, ENABLE); 51 | /* TIM1 main Output Enable */ 52 | TIM_CtrlPWMOutputs(TIM1, ENABLE); 53 | 54 | /* DMA1 channel1 configuration ----------------------------------------------*/ 55 | DMA_DeInit(DMA1_Channel1); 56 | DMA_InitStructure.DMA_PeripheralBaseAddr =(u32)&(ADC1->DR); 57 | DMA_InitStructure.DMA_MemoryBaseAddr = (u32)&VcBuf; 58 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; 59 | DMA_InitStructure.DMA_BufferSize = VcBuf_Len; 60 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 61 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 62 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; 63 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; 64 | DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; 65 | DMA_InitStructure.DMA_Priority = DMA_Priority_High; 66 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 67 | DMA_Init(DMA1_Channel1, &DMA_InitStructure); 68 | 69 | /* Enable DMA1 channel1 */ 70 | DMA_Cmd(DMA1_Channel1, ENABLE); 71 | 72 | /* ADC1 configuration ------------------------------------------------------*/ 73 | ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; 74 | ADC_InitStructure.ADC_ScanConvMode = DISABLE; 75 | ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; 76 | ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; 77 | ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; 78 | ADC_InitStructure.ADC_NbrOfChannel = 1; 79 | ADC_Init(ADC1, &ADC_InitStructure); 80 | 81 | /* ADC1 regular channel1 configuration */ 82 | ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 1, ADC_SampleTime_55Cycles5); 83 | 84 | /* Enable ADC1 DMA */ 85 | ADC_DMACmd(ADC1, ENABLE); 86 | 87 | /* Enable ADC1 */ 88 | ADC_Cmd(ADC1, ENABLE); 89 | 90 | /* Enable ADC1 reset calibaration register */ 91 | ADC_ResetCalibration(ADC1); 92 | /* Check the end of ADC1 reset calibration register */ 93 | while(ADC_GetResetCalibrationStatus(ADC1)); 94 | 95 | /* Start ADC1 calibaration */ 96 | ADC_StartCalibration(ADC1); 97 | /* Check the end of ADC1 calibration */ 98 | while(ADC_GetCalibrationStatus(ADC1)); 99 | 100 | /* Start ADC1 Software Conversion */ 101 | ADC_SoftwareStartConvCmd(ADC1, ENABLE); 102 | 103 | } 104 | 105 | 106 | -------------------------------------------------------------------------------- /Src/BSP/ADC.H: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/ADC.H -------------------------------------------------------------------------------- /Src/BSP/BSP.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/BSP.c -------------------------------------------------------------------------------- /Src/BSP/BSP.c.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/BSP.c.orig -------------------------------------------------------------------------------- /Src/BSP/Flash.C: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/Flash.C -------------------------------------------------------------------------------- /Src/BSP/Flash.H: -------------------------------------------------------------------------------- 1 | #ifndef __FLASH_H 2 | #define __FLASH_H 3 | 4 | #include "MFCC.H" 5 | 6 | #define FLASH_PAGE_SIZE 2048 7 | 8 | #define Flash_Fail 3 9 | #define Flash_Success 0 10 | 11 | #define save_mask 12345 12 | 13 | #define size_per_ftr (4*1024) 14 | #define page_per_ftr (size_per_ftr/FLASH_PAGE_SIZE) 15 | #define ftr_per_comm 4 16 | #define size_per_comm (ftr_per_comm*size_per_ftr) 17 | #define comm_num 20 18 | #define ftr_total_size (size_per_comm*comm_num) 19 | #define ftr_end_addr 0x8080000 20 | #define ftr_start_addr (ftr_end_addr-ftr_total_size) 21 | 22 | u8 save_ftr_mdl(v_ftr_tag* ftr, u32 addr); 23 | 24 | #endif 25 | 26 | -------------------------------------------------------------------------------- /Src/BSP/SPI.C: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/SPI.C -------------------------------------------------------------------------------- /Src/BSP/SPI.C.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/SPI.C.orig -------------------------------------------------------------------------------- /Src/BSP/SPI.H: -------------------------------------------------------------------------------- 1 | #ifndef SPI_H 2 | #define SPI_H 3 | 4 | u8 SPI_Exchange_Data(SPI_TypeDef* SPIx, u8 Data); 5 | 6 | #endif 7 | -------------------------------------------------------------------------------- /Src/BSP/TFTLCD.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/TFTLCD.c -------------------------------------------------------------------------------- /Src/BSP/TFTLCD.c.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/TFTLCD.c.orig -------------------------------------------------------------------------------- /Src/BSP/USART.C: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/USART.C -------------------------------------------------------------------------------- /Src/BSP/USART.C.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/USART.C.orig -------------------------------------------------------------------------------- /Src/BSP/USART.H: -------------------------------------------------------------------------------- 1 | #ifndef USART_H 2 | #define USART_H 3 | 4 | void USART1_configuration(void); 5 | void USART_SendStr(USART_TypeDef* USARTx, uint8_t *Data); 6 | void USART_SendArray(USART_TypeDef* USARTx, uint8_t *Data ,u16 len); 7 | void UASRT_DMA_TXConfiguration(USART_TypeDef* USARTx,u8 *BufferSRC, u32 BufferSize); 8 | void USART1_printf (char *fmt, ...); 9 | 10 | #endif 11 | -------------------------------------------------------------------------------- /Src/BSP/bsp.h: -------------------------------------------------------------------------------- 1 | #if !defined( _BSP_H ) 2 | #define _BSP_H 3 | 4 | void USART1_configuration(void); 5 | void RCC_Configuration(void); 6 | void GPIO_Configuration(void); 7 | void NVIC_Configuration(void); 8 | void EXTI_Configuration(void); 9 | void BSP_Init(void); 10 | uint32_t OS_CPU_SysTickClkFreq (void); 11 | uint32_t BSP_CPU_ClkFreq (void); 12 | 13 | void tim2_start(void); 14 | u16 tim2_stop(void); 15 | 16 | 17 | void BSP_IntDisAll(void); 18 | 19 | #ifdef DEBUG 20 | void assert_failed(u8* file, u32 line) 21 | #endif 22 | 23 | 24 | 25 | 26 | /* 27 | ********************************************************************************************************* 28 | * INT DEFINES 29 | ********************************************************************************************************* 30 | */ 31 | 32 | #define BSP_INT_ID_WWDG 0 /* Window WatchDog Interrupt */ 33 | #define BSP_INT_ID_PVD 1 /* PVD through EXTI Line detection Interrupt */ 34 | #define BSP_INT_ID_TAMPER 2 /* Tamper Interrupt */ 35 | #define BSP_INT_ID_RTC 3 /* RTC global Interrupt */ 36 | #define BSP_INT_ID_FLASH 4 /* FLASH global Interrupt */ 37 | #define BSP_INT_ID_RCC 5 /* RCC global Interrupt */ 38 | #define BSP_INT_ID_EXTI0 6 /* EXTI Line0 Interrupt */ 39 | #define BSP_INT_ID_EXTI1 7 /* EXTI Line1 Interrupt */ 40 | #define BSP_INT_ID_EXTI2 8 /* EXTI Line2 Interrupt */ 41 | #define BSP_INT_ID_EXTI3 9 /* EXTI Line3 Interrupt */ 42 | #define BSP_INT_ID_EXTI4 10 /* EXTI Line4 Interrupt */ 43 | #define BSP_INT_ID_DMA1_CH1 11 /* DMA1 Channel 1 global Interrupt */ 44 | #define BSP_INT_ID_DMA1_CH2 12 /* DMA1 Channel 2 global Interrupt */ 45 | #define BSP_INT_ID_DMA1_CH3 13 /* DMA1 Channel 3 global Interrupt */ 46 | #define BSP_INT_ID_DMA1_CH4 14 /* DMA1 Channel 4 global Interrupt */ 47 | #define BSP_INT_ID_DMA1_CH5 15 /* DMA1 Channel 5 global Interrupt */ 48 | #define BSP_INT_ID_DMA1_CH6 16 /* DMA1 Channel 6 global Interrupt */ 49 | #define BSP_INT_ID_DMA1_CH7 17 /* DMA1 Channel 7 global Interrupt */ 50 | #define BSP_INT_ID_ADC1_2 18 /* ADC1 et ADC2 global Interrupt */ 51 | #define BSP_INT_ID_USB_HP_CAN_TX 19 /* USB High Priority or CAN TX Interrupts */ 52 | #define BSP_INT_ID_USB_LP_CAN_RX0 20 /* USB Low Priority or CAN RX0 Interrupts */ 53 | #define BSP_INT_ID_CAN_RX1 21 /* CAN RX1 Interrupt */ 54 | #define BSP_INT_ID_CAN_SCE 22 /* CAN SCE Interrupt */ 55 | #define BSP_INT_ID_EXTI9_5 23 /* External Line[9:5] Interrupts */ 56 | #define BSP_INT_ID_TIM1_BRK 24 /* TIM1 Break Interrupt */ 57 | #define BSP_INT_ID_TIM1_UP 25 /* TIM1 Update Interrupt */ 58 | #define BSP_INT_ID_TIM1_TRG_COM 26 /* TIM1 Trigger and Commutation Interrupt */ 59 | #define BSP_INT_ID_TIM1_CC 27 /* TIM1 Capture Compare Interrupt */ 60 | #define BSP_INT_ID_TIM2 28 /* TIM2 global Interrupt */ 61 | #define BSP_INT_ID_TIM3 29 /* TIM3 global Interrupt */ 62 | #define BSP_INT_ID_TIM4 30 /* TIM4 global Interrupt */ 63 | #define BSP_INT_ID_I2C1_EV 31 /* I2C1 Event Interrupt */ 64 | #define BSP_INT_ID_I2C1_ER 32 /* I2C1 Error Interrupt */ 65 | #define BSP_INT_ID_I2C2_EV 33 /* I2C2 Event Interrupt */ 66 | #define BSP_INT_ID_I2C2_ER 34 /* I2C2 Error Interrupt */ 67 | #define BSP_INT_ID_SPI1 35 /* SPI1 global Interrupt */ 68 | #define BSP_INT_ID_SPI2 36 /* SPI2 global Interrupt */ 69 | #define BSP_INT_ID_USART1 37 /* USART1 global Interrupt */ 70 | #define BSP_INT_ID_USART2 38 /* USART2 global Interrupt */ 71 | #define BSP_INT_ID_USART3 39 /* USART3 global Interrupt */ 72 | #define BSP_INT_ID_EXTI15_10 40 /* External Line[15:10] Interrupts */ 73 | #define BSP_INT_ID_RTCAlarm 41 /* RTC Alarm through EXTI Line Interrupt */ 74 | #define BSP_INT_ID_USBWakeUp 42 /* USB WakeUp from suspend through EXTI Line Interrupt */ 75 | #define BSP_INT_ID_TIM8_BRK 43 /* TIM8 Break Interrupt */ 76 | #define BSP_INT_ID_TIM8_UP 44 /* TIM8 Update Interrupt */ 77 | #define BSP_INT_ID_TIM8_TRG_COM 45 /* TIM8 Trigger and Commutation Interrupt */ 78 | #define BSP_INT_ID_TIM8_CC 46 /* TIM8 Capture Compare Interrupt */ 79 | #define BSP_INT_ID_ADC3 47 /* ADC3 global Interrupt */ 80 | #define BSP_INT_ID_FSMC 48 /* FSMC global Interrupt */ 81 | #define BSP_INT_ID_SDIO 49 /* SDIO global Interrupt */ 82 | #define BSP_INT_ID_TIM5 50 /* TIM5 global Interrupt */ 83 | #define BSP_INT_ID_SPI3 51 /* SPI3 global Interrupt */ 84 | #define BSP_INT_ID_UART4 52 /* UART4 global Interrupt */ 85 | #define BSP_INT_ID_UART5 53 /* UART5 global Interrupt */ 86 | #define BSP_INT_ID_TIM6 54 /* TIM6 global Interrupt */ 87 | #define BSP_INT_ID_TIM7 55 /* TIM7 global Interrupt */ 88 | #define BSP_INT_ID_DMA2_CH1 56 /* DMA2 Channel 1 global Interrupt */ 89 | #define BSP_INT_ID_DMA2_CH2 57 /* DMA2 Channel 2 global Interrupt */ 90 | #define BSP_INT_ID_DMA2_CH3 58 /* DMA2 Channel 3 global Interrupt */ 91 | #define BSP_INT_ID_DMA2_CH4_5 59 /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */ 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /Src/BSP/delay.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/delay.c -------------------------------------------------------------------------------- /Src/BSP/delay.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/delay.h -------------------------------------------------------------------------------- /Src/BSP/spiFlash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/spiFlash.c -------------------------------------------------------------------------------- /Src/BSP/spiFlash.c.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/BSP/spiFlash.c.orig -------------------------------------------------------------------------------- /Src/BSP/spiFlash.h: -------------------------------------------------------------------------------- 1 | #ifndef SPI_FLASH_H 2 | #define SPI_FLASH_H 3 | 4 | 5 | void spiFlashRead(u32 start_address,void *buffer, u32 length); 6 | void spiFlashSectorEarse(u32 Addr); 7 | void spiFlashPageProgram(u32 start_address, const void *buffer, u32 length); 8 | void spiFlashTest(u8 seed); 9 | 10 | u8 *getGB2312Font24Dot(const u8 *gb2312Code); 11 | void printGB2312Font24Dot(const u8 *gb2312Code); 12 | #endif 13 | -------------------------------------------------------------------------------- /Src/BSP/stdint.h: -------------------------------------------------------------------------------- 1 | /* Copyright (C) ARM Ltd., 1999 */ 2 | /* All rights reserved */ 3 | 4 | /* 5 | * RCS $Revision: 138251 $ 6 | * Checkin $Date: 2008-10-07 12:02:11 +0100 (Tue, 07 Oct 2008) $ 7 | * Revising $Author: agrant $ 8 | */ 9 | 10 | #ifndef __stdint_h 11 | #define __stdint_h 12 | 13 | #ifndef __STDINT_DECLS 14 | #define __STDINT_DECLS 15 | 16 | #undef __CLIBNS 17 | 18 | #ifdef __cplusplus 19 | namespace std { 20 | #define __CLIBNS std:: 21 | extern "C" { 22 | #else 23 | #define __CLIBNS 24 | #endif /* __cplusplus */ 25 | 26 | 27 | /* 28 | * 'signed' is redundant below, except for 'signed char' and if 29 | * the typedef is used to declare a bitfield. 30 | * '__int64' is used instead of 'long long' so that this header 31 | * can be used in --strict mode. 32 | */ 33 | 34 | /* 7.18.1.1 */ 35 | 36 | /* exact-width signed integer types */ 37 | typedef signed char int8_t; 38 | typedef signed short int int16_t; 39 | typedef signed int int32_t; 40 | typedef signed __int64 int64_t; 41 | 42 | /* exact-width unsigned integer types */ 43 | typedef unsigned char uint8_t; 44 | typedef unsigned short int uint16_t; 45 | typedef unsigned int uint32_t; 46 | typedef unsigned __int64 uint64_t; 47 | 48 | /* 7.18.1.2 */ 49 | 50 | /* smallest type of at least n bits */ 51 | /* minimum-width signed integer types */ 52 | typedef signed char int_least8_t; 53 | typedef signed short int int_least16_t; 54 | typedef signed int int_least32_t; 55 | typedef signed __int64 int_least64_t; 56 | 57 | /* minimum-width unsigned integer types */ 58 | typedef unsigned char uint_least8_t; 59 | typedef unsigned short int uint_least16_t; 60 | typedef unsigned int uint_least32_t; 61 | typedef unsigned __int64 uint_least64_t; 62 | 63 | /* 7.18.1.3 */ 64 | 65 | /* fastest minimum-width signed integer types */ 66 | typedef signed int int_fast8_t; 67 | typedef signed int int_fast16_t; 68 | typedef signed int int_fast32_t; 69 | typedef signed __int64 int_fast64_t; 70 | 71 | /* fastest minimum-width unsigned integer types */ 72 | typedef unsigned int uint_fast8_t; 73 | typedef unsigned int uint_fast16_t; 74 | typedef unsigned int uint_fast32_t; 75 | typedef unsigned __int64 uint_fast64_t; 76 | 77 | /* 7.18.1.4 integer types capable of holding object pointers */ 78 | typedef signed int intptr_t; 79 | typedef unsigned int uintptr_t; 80 | 81 | /* 7.18.1.5 greatest-width integer types */ 82 | typedef signed __int64 intmax_t; 83 | typedef unsigned __int64 uintmax_t; 84 | 85 | 86 | #if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) 87 | 88 | /* 7.18.2.1 */ 89 | 90 | /* minimum values of exact-width signed integer types */ 91 | #define INT8_MIN -128 92 | #define INT16_MIN -32768 93 | #define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ 94 | #define INT64_MIN __ESCAPE__(~0x7fffffffffffffffll) /* -9223372036854775808 is unsigned */ 95 | 96 | /* maximum values of exact-width signed integer types */ 97 | #define INT8_MAX 127 98 | #define INT16_MAX 32767 99 | #define INT32_MAX 2147483647 100 | #define INT64_MAX __ESCAPE__(9223372036854775807ll) 101 | 102 | /* maximum values of exact-width unsigned integer types */ 103 | #define UINT8_MAX 255 104 | #define UINT16_MAX 65535 105 | #define UINT32_MAX 4294967295u 106 | #define UINT64_MAX __ESCAPE__(18446744073709551615ull) 107 | 108 | /* 7.18.2.2 */ 109 | 110 | /* minimum values of minimum-width signed integer types */ 111 | #define INT_LEAST8_MIN -128 112 | #define INT_LEAST16_MIN -32768 113 | #define INT_LEAST32_MIN (~0x7fffffff) 114 | #define INT_LEAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) 115 | 116 | /* maximum values of minimum-width signed integer types */ 117 | #define INT_LEAST8_MAX 127 118 | #define INT_LEAST16_MAX 32767 119 | #define INT_LEAST32_MAX 2147483647 120 | #define INT_LEAST64_MAX __ESCAPE__(9223372036854775807ll) 121 | 122 | /* maximum values of minimum-width unsigned integer types */ 123 | #define UINT_LEAST8_MAX 255 124 | #define UINT_LEAST16_MAX 65535 125 | #define UINT_LEAST32_MAX 4294967295u 126 | #define UINT_LEAST64_MAX __ESCAPE__(18446744073709551615ull) 127 | 128 | /* 7.18.2.3 */ 129 | 130 | /* minimum values of fastest minimum-width signed integer types */ 131 | #define INT_FAST8_MIN (~0x7fffffff) 132 | #define INT_FAST16_MIN (~0x7fffffff) 133 | #define INT_FAST32_MIN (~0x7fffffff) 134 | #define INT_FAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) 135 | 136 | /* maximum values of fastest minimum-width signed integer types */ 137 | #define INT_FAST8_MAX 2147483647 138 | #define INT_FAST16_MAX 2147483647 139 | #define INT_FAST32_MAX 2147483647 140 | #define INT_FAST64_MAX __ESCAPE__(9223372036854775807ll) 141 | 142 | /* maximum values of fastest minimum-width unsigned integer types */ 143 | #define UINT_FAST8_MAX 4294967295u 144 | #define UINT_FAST16_MAX 4294967295u 145 | #define UINT_FAST32_MAX 4294967295u 146 | #define UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull) 147 | 148 | /* 7.18.2.4 */ 149 | 150 | /* minimum value of pointer-holding signed integer type */ 151 | #define INTPTR_MIN (~0x7fffffff) 152 | 153 | /* maximum value of pointer-holding signed integer type */ 154 | #define INTPTR_MAX 2147483647 155 | 156 | /* maximum value of pointer-holding unsigned integer type */ 157 | #define UINTPTR_MAX 4294967295u 158 | 159 | /* 7.18.2.5 */ 160 | 161 | /* minimum value of greatest-width signed integer type */ 162 | #define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) 163 | 164 | /* maximum value of greatest-width signed integer type */ 165 | #define INTMAX_MAX __ESCAPE__(9223372036854775807ll) 166 | 167 | /* maximum value of greatest-width unsigned integer type */ 168 | #define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) 169 | 170 | /* 7.18.3 */ 171 | 172 | /* limits of ptrdiff_t */ 173 | #define PTRDIFF_MIN (~0x7fffffff) 174 | #define PTRDIFF_MAX 2147483647 175 | 176 | /* limits of sig_atomic_t */ 177 | #define SIG_ATOMIC_MIN (~0x7fffffff) 178 | #define SIG_ATOMIC_MAX 2147483647 179 | 180 | /* limit of size_t */ 181 | #define SIZE_MAX 4294967295u 182 | 183 | /* limits of wchar_t */ 184 | /* NB we have to undef and redef because they're defined in both 185 | * stdint.h and wchar.h */ 186 | #undef WCHAR_MIN 187 | #undef WCHAR_MAX 188 | 189 | #if defined(__WCHAR32) 190 | #define WCHAR_MIN 0 191 | #define WCHAR_MAX 0xffffffffU 192 | #else 193 | #define WCHAR_MIN 0 194 | #define WCHAR_MAX 65535 195 | #endif 196 | 197 | /* limits of wint_t */ 198 | #define WINT_MIN (~0x7fffffff) 199 | #define WINT_MAX 2147483647 200 | 201 | #endif /* __STDC_LIMIT_MACROS */ 202 | 203 | #if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) 204 | 205 | /* 7.18.4.1 macros for minimum-width integer constants */ 206 | #define INT8_C(x) (x) 207 | #define INT16_C(x) (x) 208 | #define INT32_C(x) (x) 209 | #define INT64_C(x) __ESCAPE__(x ## ll) 210 | 211 | #define UINT8_C(x) (x ## u) 212 | #define UINT16_C(x) (x ## u) 213 | #define UINT32_C(x) (x ## u) 214 | #define UINT64_C(x) __ESCAPE__(x ## ull) 215 | 216 | /* 7.18.4.2 macros for greatest-width integer constants */ 217 | #define INTMAX_C(x) __ESCAPE__(x ## ll) 218 | #define UINTMAX_C(x) __ESCAPE__(x ## ull) 219 | 220 | #endif /* __STDC_CONSTANT_MACROS */ 221 | 222 | #ifdef __cplusplus 223 | } /* extern "C" */ 224 | } /* namespace std */ 225 | #endif /* __cplusplus */ 226 | #endif /* __STDINT_DECLS */ 227 | 228 | #ifdef __cplusplus 229 | #ifndef __STDINT_NO_EXPORTS 230 | using ::std::int8_t; 231 | using ::std::int16_t; 232 | using ::std::int32_t; 233 | using ::std::int64_t; 234 | using ::std::uint8_t; 235 | using ::std::uint16_t; 236 | using ::std::uint32_t; 237 | using ::std::uint64_t; 238 | using ::std::int_least8_t; 239 | using ::std::int_least16_t; 240 | using ::std::int_least32_t; 241 | using ::std::int_least64_t; 242 | using ::std::uint_least8_t; 243 | using ::std::uint_least16_t; 244 | using ::std::uint_least32_t; 245 | using ::std::uint_least64_t; 246 | using ::std::int_fast8_t; 247 | using ::std::int_fast16_t; 248 | using ::std::int_fast32_t; 249 | using ::std::int_fast64_t; 250 | using ::std::uint_fast8_t; 251 | using ::std::uint_fast16_t; 252 | using ::std::uint_fast32_t; 253 | using ::std::uint_fast64_t; 254 | using ::std::intptr_t; 255 | using ::std::uintptr_t; 256 | using ::std::intmax_t; 257 | using ::std::uintmax_t; 258 | #endif 259 | #endif /* __cplusplus */ 260 | 261 | #endif /* __stdint_h */ 262 | 263 | /* end of stdint.h */ 264 | 265 | 266 | -------------------------------------------------------------------------------- /Src/BSP/tftlcd.h: -------------------------------------------------------------------------------- 1 | #ifndef _LCDLCD_INCLUDED_ 2 | #define _LCDLCD_INCLUDED_ 3 | 4 | #include "stm32f10x.h" 5 | 6 | #define RED 0XF800 7 | #define GREEN 0X07E0 8 | #define BLUE 0X001F 9 | #define BRED 0XF81F 10 | #define GRED 0XFFE0 11 | #define GBLUE 0X07FF 12 | #define BLACK 0X0000 13 | #define WHITE 0XFFFF 14 | 15 | 16 | #define Bank1_LCD_D ((uint32_t)0x6C000800) //disp Data ADDR 17 | #define Bank1_LCD_C ((uint32_t)0x6C0007FE) //disp Reg ADDR 18 | 19 | #define LCD_WR_REG(index) *(__IO uint16_t *)(Bank1_LCD_C)=(index) 20 | #define LCD_WR_CMD(index,val) *(__IO uint16_t *)(Bank1_LCD_C)=index;*(__IO uint16_t *)(Bank1_LCD_D)=val 21 | #define LCD_WR_Data(val) *(__IO uint16_t *)(Bank1_LCD_D)=(val) 22 | 23 | #define LCD_AbovetoBelow() LCD_WR_CMD(0x0003,0x1030) 24 | #define LCD_BelowtoAbove() LCD_WR_CMD(0x0003,0x1010) 25 | 26 | #define CN_Width 24 27 | #define CN_Height 24 28 | #define Char_Width 12 29 | #define Char_Height 24 30 | 31 | #define COORD_240_320 0 32 | #define COORD_320_240 1 33 | 34 | extern u8 LCD_COORD; 35 | 36 | void LCD_Init(void); 37 | void LCD_Rst(void); 38 | void FSMC_LCD_Init(void); 39 | void LCD_Set_Disp_Window(u16 left,u16 top,u16 width,u16 height); 40 | void LCD_Set_Address(u16 left,u16 top); 41 | void LCD_Set_Coord(u8 coord); 42 | void LCD_Fill(u16 left,u16 top,u16 width,u16 height,u16 color); 43 | void LCD_DrawPoint(u16 left,u16 top,u16 color); 44 | void LCD_DrawLine(u16 x1, u16 y1, u16 x2, u16 y2,u16 color); 45 | void LCD_ShowChar(u16 left,u16 top,u8 char_data,u16 color); 46 | void LCD_ShowCN(u16 left,u16 top,u8* cn,u16 color); 47 | u16 RGB(u8 red,u8 green,u8 blue); 48 | 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /Src/BSP/touch_panel.c: -------------------------------------------------------------------------------- 1 | #include "stm32f10x_conf.h" 2 | #include "stm32f10x.h" 3 | #include "SPI.h" 4 | #include "touch_panel.h" 5 | #include "TFTLCD.H" 6 | 7 | #define DEBUG 8 | #ifdef DEBUG 9 | #define DBP(fmt,arg...) USART1_printf(fmt,##arg) 10 | #define DBPLN(fmt,arg...) USART1_printf_line(fmt,##arg) 11 | #define DBPH(src, len) USART1_print_hex(src, len) 12 | #else 13 | #define DBP(fmt,arg...) 14 | #define DBPLN(fmt,arg...) 15 | #define DBPH(src, len) 16 | #endif 17 | 18 | void touchPanelInit(){ 19 | GPIO_InitTypeDef GPIO_InitStructure; 20 | SPI_InitTypeDef SPI_InitStructure; 21 | 22 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1 | RCC_APB2Periph_GPIOF |RCC_APB2Periph_GPIOA, ENABLE); 23 | 24 | GPIO_InitStructure.GPIO_Pin = TSC_INT_PIN; 25 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 26 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 27 | GPIO_Init(TSC_INT_PORT, &GPIO_InitStructure); 28 | 29 | GPIO_InitStructure.GPIO_Pin = TSC_NSS_PIN; 30 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 31 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 32 | GPIO_Init(TSC_NSS_PORT, &GPIO_InitStructure); 33 | SELECT_TSC(false); 34 | 35 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 ; 36 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 37 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 38 | GPIO_Init(GPIOA, &GPIO_InitStructure); 39 | 40 | SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; 41 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master; 42 | SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; 43 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; 44 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; 45 | SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; 46 | SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16; 47 | SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; 48 | SPI_InitStructure.SPI_CRCPolynomial = 7; 49 | SPI_Init(TSC_SPI, &SPI_InitStructure); 50 | 51 | SPI_Cmd(TSC_SPI, ENABLE); 52 | } 53 | 54 | 55 | 56 | u8 touch_panel_read(u16 *X, u16 *Y) { 57 | u16 X_buffer[10], Y_buffer[10]; 58 | u32 X_temp, Y_temp; 59 | u16 i = 0; 60 | 61 | while(i < 10 && TSC_IN_TOUCH()) { 62 | SELECT_TSC(true); 63 | 64 | TSC_EXCHANGE_DATA(CMD_RDY); 65 | delay_us(6); 66 | 67 | X_temp = TSC_EXCHANGE_DATA(0); 68 | X_temp = X_temp << 8; 69 | X_temp |= TSC_EXCHANGE_DATA(0); 70 | X_temp >>= 3; 71 | 72 | TSC_EXCHANGE_DATA(CMD_RDX); 73 | delay_us(6); 74 | 75 | Y_temp = TSC_EXCHANGE_DATA(0); 76 | Y_temp = Y_temp << 8; 77 | Y_temp |= TSC_EXCHANGE_DATA(0); 78 | Y_temp >>= 3; 79 | 80 | SELECT_TSC(false); 81 | 82 | if(X_temp > 100 && X_temp < 4000 && Y_temp > 100 && Y_temp < 4000) { 83 | X_buffer[i] = X_temp; 84 | Y_buffer[i] = Y_temp; 85 | 86 | i++; 87 | 88 | } 89 | } 90 | 91 | if(i == 10) { 92 | for(i = 0; i < 9; i++) { 93 | if(X_buffer[i] > X_buffer[i + 1]) { 94 | X_temp = X_buffer[i]; 95 | X_buffer[i] = X_buffer[i + 1]; 96 | X_buffer[i + 1] = X_temp; 97 | } 98 | 99 | if(Y_buffer[i] > Y_buffer[i + 1]) { 100 | Y_temp = Y_buffer[i]; 101 | Y_buffer[i] = Y_buffer[i + 1]; 102 | Y_buffer[i + 1] = Y_temp; 103 | } 104 | } 105 | 106 | for(i = 8; i > 0; i--) { 107 | if(X_buffer[i] < X_buffer[i - 1]) { 108 | X_temp = X_buffer[i]; 109 | X_buffer[i] = X_buffer[i - 1]; 110 | X_buffer[i - 1] = X_temp; 111 | } 112 | 113 | if(Y_buffer[i] < Y_buffer[i - 1]) { 114 | Y_temp = Y_buffer[i]; 115 | Y_buffer[i] = Y_buffer[i - 1]; 116 | Y_buffer[i - 1] = Y_temp; 117 | } 118 | } 119 | 120 | X_temp = 0; 121 | Y_temp = 0; 122 | 123 | for(i = 1; i < 9; i++) { 124 | X_temp += X_buffer[i]; 125 | Y_temp += Y_buffer[i]; 126 | } 127 | 128 | X_temp /= 8; 129 | Y_temp /= 8; 130 | 131 | //DBPLN("x=%d, y=%d", X_temp, Y_temp); 132 | 133 | 134 | *X = 351-Y_temp*32/353; 135 | *Y = 257 - X_temp*24/355; 136 | 137 | DBPLN("left=%d, top=%d",*X, *Y); 138 | 139 | return 1; 140 | } else 141 | return 0; 142 | 143 | } 144 | 145 | -------------------------------------------------------------------------------- /Src/BSP/touch_panel.c.orig: -------------------------------------------------------------------------------- 1 | #include "stm32f10x_conf.h" 2 | #include "stm32f10x.h" 3 | #include "SPI.h" 4 | #include "touch_panel.h" 5 | #include "TFTLCD.H" 6 | 7 | u8 touch_panel_read(u16 *X,u16 *Y) 8 | { 9 | u16 X_buffer[10],Y_buffer[10]; 10 | u32 X_temp,Y_temp; 11 | u16 i=0; 12 | 13 | while(i<10&&touch) 14 | { 15 | Select_TSC(); 16 | 17 | 18 | SPI_Exchange_Data(SPI1, CMD_RDY); 19 | 20 | X_temp=SPI_Exchange_Data(SPI1, 0); 21 | X_temp=X_temp<<8; 22 | X_temp|=SPI_Exchange_Data(SPI1, 0); 23 | X_temp>>=3; 24 | 25 | SPI_Exchange_Data(SPI1, CMD_RDX); 26 | 27 | Y_temp=SPI_Exchange_Data(SPI1, 0); 28 | Y_temp=Y_temp<<8; 29 | Y_temp|=SPI_Exchange_Data(SPI1, 0); 30 | Y_temp>>=3; 31 | 32 | DisSelect_TSC(); 33 | 34 | if(X_temp>100&&X_temp<4000&&Y_temp>100&&Y_temp<4000) 35 | { 36 | X_buffer[i]=X_temp; 37 | Y_buffer[i]=Y_temp; 38 | 39 | i++; 40 | 41 | } 42 | } 43 | 44 | if(i==10) 45 | { 46 | for(i=0;i<9;i++) 47 | { 48 | if(X_buffer[i]>X_buffer[i+1]) 49 | { 50 | X_temp=X_buffer[i]; 51 | X_buffer[i]=X_buffer[i+1]; 52 | X_buffer[i+1]=X_temp; 53 | } 54 | if(Y_buffer[i]>Y_buffer[i+1]) 55 | { 56 | Y_temp=Y_buffer[i]; 57 | Y_buffer[i]=Y_buffer[i+1]; 58 | Y_buffer[i+1]=Y_temp; 59 | } 60 | } 61 | for(i=8;i>0;i--) 62 | { 63 | if(X_buffer[i]>> 18 | ;******************************************************************************* 19 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 20 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 21 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 22 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 23 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 24 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 25 | ;******************************************************************************* 26 | 27 | ; Amount of memory (in bytes) allocated for Stack 28 | ; Tailor this value to your application needs 29 | ; Stack Configuration 30 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 31 | ; 32 | 33 | Stack_Size EQU 0x00000400 34 | 35 | AREA STACK, NOINIT, READWRITE, ALIGN=3 36 | Stack_Mem SPACE Stack_Size 37 | __initial_sp 38 | 39 | 40 | ; Heap Configuration 41 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 42 | ; 43 | 44 | Heap_Size EQU 0x00000200 45 | 46 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 47 | __heap_base 48 | Heap_Mem SPACE Heap_Size 49 | __heap_limit 50 | 51 | PRESERVE8 52 | THUMB 53 | 54 | 55 | ; Vector Table Mapped to Address 0 at Reset 56 | AREA RESET, DATA, READONLY 57 | EXPORT __Vectors 58 | EXPORT __Vectors_End 59 | EXPORT __Vectors_Size 60 | 61 | __Vectors DCD __initial_sp ; Top of Stack 62 | DCD Reset_Handler ; Reset Handler 63 | DCD NMI_Handler ; NMI Handler 64 | DCD HardFault_Handler ; Hard Fault Handler 65 | DCD MemManage_Handler ; MPU Fault Handler 66 | DCD BusFault_Handler ; Bus Fault Handler 67 | DCD UsageFault_Handler ; Usage Fault Handler 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD 0 ; Reserved 71 | DCD 0 ; Reserved 72 | DCD SVC_Handler ; SVCall Handler 73 | DCD DebugMon_Handler ; Debug Monitor Handler 74 | DCD 0 ; Reserved 75 | DCD PendSV_Handler ; PendSV Handler 76 | DCD SysTick_Handler ; SysTick Handler 77 | 78 | ; External Interrupts 79 | DCD WWDG_IRQHandler ; Window Watchdog 80 | DCD PVD_IRQHandler ; PVD through EXTI Line detect 81 | DCD TAMPER_IRQHandler ; Tamper 82 | DCD RTC_IRQHandler ; RTC 83 | DCD FLASH_IRQHandler ; Flash 84 | DCD RCC_IRQHandler ; RCC 85 | DCD EXTI0_IRQHandler ; EXTI Line 0 86 | DCD EXTI1_IRQHandler ; EXTI Line 1 87 | DCD EXTI2_IRQHandler ; EXTI Line 2 88 | DCD EXTI3_IRQHandler ; EXTI Line 3 89 | DCD EXTI4_IRQHandler ; EXTI Line 4 90 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 91 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 92 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 93 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 94 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 95 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 96 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 97 | DCD ADC1_2_IRQHandler ; ADC1_2 98 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX 99 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 100 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1 101 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE 102 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 103 | DCD TIM1_BRK_IRQHandler ; TIM1 Break 104 | DCD TIM1_UP_IRQHandler ; TIM1 Update 105 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation 106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 107 | DCD TIM2_IRQHandler ; TIM2 108 | DCD TIM3_IRQHandler ; TIM3 109 | DCD 0 ; Reserved 110 | DCD I2C1_EV_IRQHandler ; I2C1 Event 111 | DCD I2C1_ER_IRQHandler ; I2C1 Error 112 | DCD 0 ; Reserved 113 | DCD 0 ; Reserved 114 | DCD SPI1_IRQHandler ; SPI1 115 | DCD 0 ; Reserved 116 | DCD USART1_IRQHandler ; USART1 117 | DCD USART2_IRQHandler ; USART2 118 | DCD 0 ; Reserved 119 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 120 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line 121 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend 122 | __Vectors_End 123 | 124 | __Vectors_Size EQU __Vectors_End - __Vectors 125 | 126 | AREA |.text|, CODE, READONLY 127 | 128 | ; Reset handler routine 129 | Reset_Handler PROC 130 | EXPORT Reset_Handler [WEAK] 131 | IMPORT __main 132 | IMPORT SystemInit 133 | LDR R0, =SystemInit 134 | BLX R0 135 | LDR R0, =__main 136 | BX R0 137 | ENDP 138 | 139 | ; Dummy Exception Handlers (infinite loops which can be modified) 140 | 141 | NMI_Handler PROC 142 | EXPORT NMI_Handler [WEAK] 143 | B . 144 | ENDP 145 | HardFault_Handler\ 146 | PROC 147 | EXPORT HardFault_Handler [WEAK] 148 | B . 149 | ENDP 150 | MemManage_Handler\ 151 | PROC 152 | EXPORT MemManage_Handler [WEAK] 153 | B . 154 | ENDP 155 | BusFault_Handler\ 156 | PROC 157 | EXPORT BusFault_Handler [WEAK] 158 | B . 159 | ENDP 160 | UsageFault_Handler\ 161 | PROC 162 | EXPORT UsageFault_Handler [WEAK] 163 | B . 164 | ENDP 165 | SVC_Handler PROC 166 | EXPORT SVC_Handler [WEAK] 167 | B . 168 | ENDP 169 | DebugMon_Handler\ 170 | PROC 171 | EXPORT DebugMon_Handler [WEAK] 172 | B . 173 | ENDP 174 | PendSV_Handler PROC 175 | EXPORT PendSV_Handler [WEAK] 176 | B . 177 | ENDP 178 | SysTick_Handler PROC 179 | EXPORT SysTick_Handler [WEAK] 180 | B . 181 | ENDP 182 | 183 | Default_Handler PROC 184 | 185 | EXPORT WWDG_IRQHandler [WEAK] 186 | EXPORT PVD_IRQHandler [WEAK] 187 | EXPORT TAMPER_IRQHandler [WEAK] 188 | EXPORT RTC_IRQHandler [WEAK] 189 | EXPORT FLASH_IRQHandler [WEAK] 190 | EXPORT RCC_IRQHandler [WEAK] 191 | EXPORT EXTI0_IRQHandler [WEAK] 192 | EXPORT EXTI1_IRQHandler [WEAK] 193 | EXPORT EXTI2_IRQHandler [WEAK] 194 | EXPORT EXTI3_IRQHandler [WEAK] 195 | EXPORT EXTI4_IRQHandler [WEAK] 196 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 197 | EXPORT DMA1_Channel2_IRQHandler [WEAK] 198 | EXPORT DMA1_Channel3_IRQHandler [WEAK] 199 | EXPORT DMA1_Channel4_IRQHandler [WEAK] 200 | EXPORT DMA1_Channel5_IRQHandler [WEAK] 201 | EXPORT DMA1_Channel6_IRQHandler [WEAK] 202 | EXPORT DMA1_Channel7_IRQHandler [WEAK] 203 | EXPORT ADC1_2_IRQHandler [WEAK] 204 | EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] 205 | EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] 206 | EXPORT CAN1_RX1_IRQHandler [WEAK] 207 | EXPORT CAN1_SCE_IRQHandler [WEAK] 208 | EXPORT EXTI9_5_IRQHandler [WEAK] 209 | EXPORT TIM1_BRK_IRQHandler [WEAK] 210 | EXPORT TIM1_UP_IRQHandler [WEAK] 211 | EXPORT TIM1_TRG_COM_IRQHandler [WEAK] 212 | EXPORT TIM1_CC_IRQHandler [WEAK] 213 | EXPORT TIM2_IRQHandler [WEAK] 214 | EXPORT TIM3_IRQHandler [WEAK] 215 | EXPORT I2C1_EV_IRQHandler [WEAK] 216 | EXPORT I2C1_ER_IRQHandler [WEAK] 217 | EXPORT SPI1_IRQHandler [WEAK] 218 | EXPORT USART1_IRQHandler [WEAK] 219 | EXPORT USART2_IRQHandler [WEAK] 220 | EXPORT EXTI15_10_IRQHandler [WEAK] 221 | EXPORT RTCAlarm_IRQHandler [WEAK] 222 | EXPORT USBWakeUp_IRQHandler [WEAK] 223 | 224 | WWDG_IRQHandler 225 | PVD_IRQHandler 226 | TAMPER_IRQHandler 227 | RTC_IRQHandler 228 | FLASH_IRQHandler 229 | RCC_IRQHandler 230 | EXTI0_IRQHandler 231 | EXTI1_IRQHandler 232 | EXTI2_IRQHandler 233 | EXTI3_IRQHandler 234 | EXTI4_IRQHandler 235 | DMA1_Channel1_IRQHandler 236 | DMA1_Channel2_IRQHandler 237 | DMA1_Channel3_IRQHandler 238 | DMA1_Channel4_IRQHandler 239 | DMA1_Channel5_IRQHandler 240 | DMA1_Channel6_IRQHandler 241 | DMA1_Channel7_IRQHandler 242 | ADC1_2_IRQHandler 243 | USB_HP_CAN1_TX_IRQHandler 244 | USB_LP_CAN1_RX0_IRQHandler 245 | CAN1_RX1_IRQHandler 246 | CAN1_SCE_IRQHandler 247 | EXTI9_5_IRQHandler 248 | TIM1_BRK_IRQHandler 249 | TIM1_UP_IRQHandler 250 | TIM1_TRG_COM_IRQHandler 251 | TIM1_CC_IRQHandler 252 | TIM2_IRQHandler 253 | TIM3_IRQHandler 254 | I2C1_EV_IRQHandler 255 | I2C1_ER_IRQHandler 256 | SPI1_IRQHandler 257 | USART1_IRQHandler 258 | USART2_IRQHandler 259 | EXTI15_10_IRQHandler 260 | RTCAlarm_IRQHandler 261 | USBWakeUp_IRQHandler 262 | 263 | B . 264 | 265 | ENDP 266 | 267 | ALIGN 268 | 269 | ;******************************************************************************* 270 | ; User Stack and Heap initialization 271 | ;******************************************************************************* 272 | IF :DEF:__MICROLIB 273 | 274 | EXPORT __initial_sp 275 | EXPORT __heap_base 276 | EXPORT __heap_limit 277 | 278 | ELSE 279 | 280 | IMPORT __use_two_region_memory 281 | EXPORT __user_initial_stackheap 282 | 283 | __user_initial_stackheap 284 | 285 | LDR R0, = Heap_Mem 286 | LDR R1, =(Stack_Mem + Stack_Size) 287 | LDR R2, = (Heap_Mem + Heap_Size) 288 | LDR R3, = Stack_Mem 289 | BX LR 290 | 291 | ALIGN 292 | 293 | ENDIF 294 | 295 | END 296 | 297 | ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** 298 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MISC_H 24 | #define __MISC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup MISC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup MISC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief NVIC Init Structure definition 47 | */ 48 | 49 | typedef struct 50 | { 51 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 52 | This parameter can be a value of @ref IRQn_Type 53 | (For the complete STM32 Devices IRQ Channels list, please 54 | refer to stm32f10x.h file) */ 55 | 56 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 57 | specified in NVIC_IRQChannel. This parameter can be a value 58 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 59 | 60 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 61 | in NVIC_IRQChannel. This parameter can be a value 62 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 63 | 64 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 65 | will be enabled or disabled. 66 | This parameter can be set either to ENABLE or DISABLE */ 67 | } NVIC_InitTypeDef; 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup NVIC_Priority_Table 74 | * @{ 75 | */ 76 | 77 | /** 78 | @code 79 | The table below gives the allowed values of the pre-emption priority and subpriority according 80 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function 81 | ============================================================================================================================ 82 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 83 | ============================================================================================================================ 84 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority 85 | | | | 4 bits for subpriority 86 | ---------------------------------------------------------------------------------------------------------------------------- 87 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority 88 | | | | 3 bits for subpriority 89 | ---------------------------------------------------------------------------------------------------------------------------- 90 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 91 | | | | 2 bits for subpriority 92 | ---------------------------------------------------------------------------------------------------------------------------- 93 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 94 | | | | 1 bits for subpriority 95 | ---------------------------------------------------------------------------------------------------------------------------- 96 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority 97 | | | | 0 bits for subpriority 98 | ============================================================================================================================ 99 | @endcode 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup MISC_Exported_Constants 107 | * @{ 108 | */ 109 | 110 | /** @defgroup Vector_Table_Base 111 | * @{ 112 | */ 113 | 114 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 115 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 116 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 117 | ((VECTTAB) == NVIC_VectTab_FLASH)) 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup System_Low_Power 123 | * @{ 124 | */ 125 | 126 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 127 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 128 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 129 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 130 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 131 | ((LP) == NVIC_LP_SLEEPONEXIT)) 132 | /** 133 | * @} 134 | */ 135 | 136 | /** @defgroup Preemption_Priority_Group 137 | * @{ 138 | */ 139 | 140 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 141 | 4 bits for subpriority */ 142 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 143 | 3 bits for subpriority */ 144 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 145 | 2 bits for subpriority */ 146 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 147 | 1 bits for subpriority */ 148 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 149 | 0 bits for subpriority */ 150 | 151 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 152 | ((GROUP) == NVIC_PriorityGroup_1) || \ 153 | ((GROUP) == NVIC_PriorityGroup_2) || \ 154 | ((GROUP) == NVIC_PriorityGroup_3) || \ 155 | ((GROUP) == NVIC_PriorityGroup_4)) 156 | 157 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 158 | 159 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 160 | 161 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /** @defgroup SysTick_clock_source 168 | * @{ 169 | */ 170 | 171 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 172 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 173 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 174 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** @defgroup MISC_Exported_Macros 184 | * @{ 185 | */ 186 | 187 | /** 188 | * @} 189 | */ 190 | 191 | /** @defgroup MISC_Exported_Functions 192 | * @{ 193 | */ 194 | 195 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 196 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 197 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 198 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 200 | 201 | #ifdef __cplusplus 202 | } 203 | #endif 204 | 205 | #endif /* __MISC_H */ 206 | 207 | /** 208 | * @} 209 | */ 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 220 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_bkp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the BKP firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_BKP_H 24 | #define __STM32F10x_BKP_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup BKP 38 | * @{ 39 | */ 40 | 41 | /** @defgroup BKP_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup BKP_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup Tamper_Pin_active_level 54 | * @{ 55 | */ 56 | 57 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 58 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 59 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ 60 | ((LEVEL) == BKP_TamperPinLevel_Low)) 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 66 | * @{ 67 | */ 68 | 69 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 70 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 71 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 72 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 73 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ 74 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ 75 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ 76 | ((SOURCE) == BKP_RTCOutputSource_Second)) 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @defgroup Data_Backup_Register 82 | * @{ 83 | */ 84 | 85 | #define BKP_DR1 ((uint16_t)0x0004) 86 | #define BKP_DR2 ((uint16_t)0x0008) 87 | #define BKP_DR3 ((uint16_t)0x000C) 88 | #define BKP_DR4 ((uint16_t)0x0010) 89 | #define BKP_DR5 ((uint16_t)0x0014) 90 | #define BKP_DR6 ((uint16_t)0x0018) 91 | #define BKP_DR7 ((uint16_t)0x001C) 92 | #define BKP_DR8 ((uint16_t)0x0020) 93 | #define BKP_DR9 ((uint16_t)0x0024) 94 | #define BKP_DR10 ((uint16_t)0x0028) 95 | #define BKP_DR11 ((uint16_t)0x0040) 96 | #define BKP_DR12 ((uint16_t)0x0044) 97 | #define BKP_DR13 ((uint16_t)0x0048) 98 | #define BKP_DR14 ((uint16_t)0x004C) 99 | #define BKP_DR15 ((uint16_t)0x0050) 100 | #define BKP_DR16 ((uint16_t)0x0054) 101 | #define BKP_DR17 ((uint16_t)0x0058) 102 | #define BKP_DR18 ((uint16_t)0x005C) 103 | #define BKP_DR19 ((uint16_t)0x0060) 104 | #define BKP_DR20 ((uint16_t)0x0064) 105 | #define BKP_DR21 ((uint16_t)0x0068) 106 | #define BKP_DR22 ((uint16_t)0x006C) 107 | #define BKP_DR23 ((uint16_t)0x0070) 108 | #define BKP_DR24 ((uint16_t)0x0074) 109 | #define BKP_DR25 ((uint16_t)0x0078) 110 | #define BKP_DR26 ((uint16_t)0x007C) 111 | #define BKP_DR27 ((uint16_t)0x0080) 112 | #define BKP_DR28 ((uint16_t)0x0084) 113 | #define BKP_DR29 ((uint16_t)0x0088) 114 | #define BKP_DR30 ((uint16_t)0x008C) 115 | #define BKP_DR31 ((uint16_t)0x0090) 116 | #define BKP_DR32 ((uint16_t)0x0094) 117 | #define BKP_DR33 ((uint16_t)0x0098) 118 | #define BKP_DR34 ((uint16_t)0x009C) 119 | #define BKP_DR35 ((uint16_t)0x00A0) 120 | #define BKP_DR36 ((uint16_t)0x00A4) 121 | #define BKP_DR37 ((uint16_t)0x00A8) 122 | #define BKP_DR38 ((uint16_t)0x00AC) 123 | #define BKP_DR39 ((uint16_t)0x00B0) 124 | #define BKP_DR40 ((uint16_t)0x00B4) 125 | #define BKP_DR41 ((uint16_t)0x00B8) 126 | #define BKP_DR42 ((uint16_t)0x00BC) 127 | 128 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ 129 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ 130 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ 131 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ 132 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ 133 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ 134 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ 135 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ 136 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ 137 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ 138 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ 139 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ 140 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ 141 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) 142 | 143 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** @defgroup BKP_Exported_Macros 153 | * @{ 154 | */ 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /** @defgroup BKP_Exported_Functions 161 | * @{ 162 | */ 163 | 164 | void BKP_DeInit(void); 165 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 166 | void BKP_TamperPinCmd(FunctionalState NewState); 167 | void BKP_ITConfig(FunctionalState NewState); 168 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 169 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 170 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 171 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 172 | FlagStatus BKP_GetFlagStatus(void); 173 | void BKP_ClearFlag(void); 174 | ITStatus BKP_GetITStatus(void); 175 | void BKP_ClearITPendingBit(void); 176 | 177 | #ifdef __cplusplus 178 | } 179 | #endif 180 | 181 | #endif /* __STM32F10x_BKP_H */ 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /** 191 | * @} 192 | */ 193 | 194 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 195 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CEC_H 24 | #define __STM32F10x_CEC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup CEC 38 | * @{ 39 | */ 40 | 41 | 42 | /** @defgroup CEC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief CEC Init structure definition 48 | */ 49 | typedef struct 50 | { 51 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 52 | This parameter can be a value of @ref CEC_BitTiming_Mode */ 53 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 54 | This parameter can be a value of @ref CEC_BitPeriod_Mode */ 55 | }CEC_InitTypeDef; 56 | 57 | /** 58 | * @} 59 | */ 60 | 61 | /** @defgroup CEC_Exported_Constants 62 | * @{ 63 | */ 64 | 65 | /** @defgroup CEC_BitTiming_Mode 66 | * @{ 67 | */ 68 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ 69 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ 70 | 71 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ 72 | ((MODE) == CEC_BitTimingErrFreeMode)) 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup CEC_BitPeriod_Mode 78 | * @{ 79 | */ 80 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ 81 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ 82 | 83 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ 84 | ((MODE) == CEC_BitPeriodFlexibleMode)) 85 | /** 86 | * @} 87 | */ 88 | 89 | 90 | /** @defgroup CEC_interrupts_definition 91 | * @{ 92 | */ 93 | #define CEC_IT_TERR CEC_CSR_TERR 94 | #define CEC_IT_TBTRF CEC_CSR_TBTRF 95 | #define CEC_IT_RERR CEC_CSR_RERR 96 | #define CEC_IT_RBTF CEC_CSR_RBTF 97 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ 98 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) 99 | /** 100 | * @} 101 | */ 102 | 103 | 104 | /** @defgroup CEC_Own_Addres 105 | * @{ 106 | */ 107 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 108 | /** 109 | * @} 110 | */ 111 | 112 | /** @defgroup CEC_Prescaler 113 | * @{ 114 | */ 115 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @defgroup CEC_flags_definition 122 | * @{ 123 | */ 124 | 125 | /** 126 | * @brief ESR register flags 127 | */ 128 | #define CEC_FLAG_BTE ((uint32_t)0x10010000) 129 | #define CEC_FLAG_BPE ((uint32_t)0x10020000) 130 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) 131 | #define CEC_FLAG_SBE ((uint32_t)0x10080000) 132 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000) 133 | #define CEC_FLAG_LINE ((uint32_t)0x10200000) 134 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) 135 | 136 | /** 137 | * @brief CSR register flags 138 | */ 139 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002) 140 | #define CEC_FLAG_TERR ((uint32_t)0x00000004) 141 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) 142 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010) 143 | #define CEC_FLAG_REOM ((uint32_t)0x00000020) 144 | #define CEC_FLAG_RERR ((uint32_t)0x00000040) 145 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080) 146 | 147 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) 148 | 149 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ 150 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ 151 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ 152 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ 153 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ 154 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ 155 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /** 162 | * @} 163 | */ 164 | 165 | /** @defgroup CEC_Exported_Macros 166 | * @{ 167 | */ 168 | 169 | /** 170 | * @} 171 | */ 172 | 173 | /** @defgroup CEC_Exported_Functions 174 | * @{ 175 | */ 176 | void CEC_DeInit(void); 177 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 178 | void CEC_Cmd(FunctionalState NewState); 179 | void CEC_ITConfig(FunctionalState NewState); 180 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 181 | void CEC_SetPrescaler(uint16_t CEC_Prescaler); 182 | void CEC_SendDataByte(uint8_t Data); 183 | uint8_t CEC_ReceiveDataByte(void); 184 | void CEC_StartOfMessage(void); 185 | void CEC_EndOfMessageCmd(FunctionalState NewState); 186 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); 187 | void CEC_ClearFlag(uint32_t CEC_FLAG); 188 | ITStatus CEC_GetITStatus(uint8_t CEC_IT); 189 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 190 | 191 | #ifdef __cplusplus 192 | } 193 | #endif 194 | 195 | #endif /* __STM32F10x_CEC_H */ 196 | 197 | /** 198 | * @} 199 | */ 200 | 201 | /** 202 | * @} 203 | */ 204 | 205 | /** 206 | * @} 207 | */ 208 | 209 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 210 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CRC_H 24 | #define __STM32F10x_CRC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup CRC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup CRC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup CRC_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** 54 | * @} 55 | */ 56 | 57 | /** @defgroup CRC_Exported_Macros 58 | * @{ 59 | */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup CRC_Exported_Functions 66 | * @{ 67 | */ 68 | 69 | void CRC_ResetDR(void); 70 | uint32_t CRC_CalcCRC(uint32_t Data); 71 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 72 | uint32_t CRC_GetCRC(void); 73 | void CRC_SetIDRegister(uint8_t IDValue); 74 | uint8_t CRC_GetIDRegister(void); 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif 79 | 80 | #endif /* __STM32F10x_CRC_H */ 81 | /** 82 | * @} 83 | */ 84 | 85 | /** 86 | * @} 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 94 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the DBGMCU 8 | * firmware library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_DBGMCU_H 24 | #define __STM32F10x_DBGMCU_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup DBGMCU 38 | * @{ 39 | */ 40 | 41 | /** @defgroup DBGMCU_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup DBGMCU_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 54 | #define DBGMCU_STOP ((uint32_t)0x00000002) 55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 56 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 57 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 58 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) 59 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) 60 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) 61 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) 62 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) 63 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 64 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 65 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) 66 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) 67 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) 68 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) 69 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 70 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) 71 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) 72 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) 73 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) 74 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) 75 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) 76 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) 77 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) 78 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) 79 | 80 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup DBGMCU_Exported_Macros 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup DBGMCU_Exported_Functions 94 | * @{ 95 | */ 96 | 97 | uint32_t DBGMCU_GetREVID(void); 98 | uint32_t DBGMCU_GetDEVID(void); 99 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 100 | 101 | #ifdef __cplusplus 102 | } 103 | #endif 104 | 105 | #endif /* __STM32F10x_DBGMCU_H */ 106 | /** 107 | * @} 108 | */ 109 | 110 | /** 111 | * @} 112 | */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 119 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the EXTI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_EXTI_H 24 | #define __STM32F10x_EXTI_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup EXTI 38 | * @{ 39 | */ 40 | 41 | /** @defgroup EXTI_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief EXTI mode enumeration 47 | */ 48 | 49 | typedef enum 50 | { 51 | EXTI_Mode_Interrupt = 0x00, 52 | EXTI_Mode_Event = 0x04 53 | }EXTIMode_TypeDef; 54 | 55 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 56 | 57 | /** 58 | * @brief EXTI Trigger enumeration 59 | */ 60 | 61 | typedef enum 62 | { 63 | EXTI_Trigger_Rising = 0x08, 64 | EXTI_Trigger_Falling = 0x0C, 65 | EXTI_Trigger_Rising_Falling = 0x10 66 | }EXTITrigger_TypeDef; 67 | 68 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 69 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 70 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 71 | /** 72 | * @brief EXTI Init Structure definition 73 | */ 74 | 75 | typedef struct 76 | { 77 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 78 | This parameter can be any combination of @ref EXTI_Lines */ 79 | 80 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 81 | This parameter can be a value of @ref EXTIMode_TypeDef */ 82 | 83 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 84 | This parameter can be a value of @ref EXTIMode_TypeDef */ 85 | 86 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 87 | This parameter can be set either to ENABLE or DISABLE */ 88 | }EXTI_InitTypeDef; 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup EXTI_Exported_Constants 95 | * @{ 96 | */ 97 | 98 | /** @defgroup EXTI_Lines 99 | * @{ 100 | */ 101 | 102 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ 103 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ 104 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ 105 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ 106 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ 107 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ 108 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ 109 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ 110 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ 111 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ 112 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ 113 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ 114 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ 115 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ 116 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ 117 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ 118 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ 119 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 120 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS 121 | Wakeup from suspend event */ 122 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 123 | 124 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) 125 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 126 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 127 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 128 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 129 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 130 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 131 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 132 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 133 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 134 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) 135 | 136 | 137 | /** 138 | * @} 139 | */ 140 | 141 | /** 142 | * @} 143 | */ 144 | 145 | /** @defgroup EXTI_Exported_Macros 146 | * @{ 147 | */ 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @defgroup EXTI_Exported_Functions 154 | * @{ 155 | */ 156 | 157 | void EXTI_DeInit(void); 158 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 159 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 160 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 161 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 162 | void EXTI_ClearFlag(uint32_t EXTI_Line); 163 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 164 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 165 | 166 | #ifdef __cplusplus 167 | } 168 | #endif 169 | 170 | #endif /* __STM32F10x_EXTI_H */ 171 | /** 172 | * @} 173 | */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 184 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_fsmc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/inc/stm32f10x_fsmc.h -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_IWDG_H 24 | #define __STM32F10x_IWDG_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup IWDG 38 | * @{ 39 | */ 40 | 41 | /** @defgroup IWDG_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup IWDG_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup IWDG_WriteAccess 54 | * @{ 55 | */ 56 | 57 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 58 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 59 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 60 | ((ACCESS) == IWDG_WriteAccess_Disable)) 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup IWDG_prescaler 66 | * @{ 67 | */ 68 | 69 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 70 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 71 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 72 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 73 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 74 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 75 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 76 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 77 | ((PRESCALER) == IWDG_Prescaler_8) || \ 78 | ((PRESCALER) == IWDG_Prescaler_16) || \ 79 | ((PRESCALER) == IWDG_Prescaler_32) || \ 80 | ((PRESCALER) == IWDG_Prescaler_64) || \ 81 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 82 | ((PRESCALER) == IWDG_Prescaler_256)) 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @defgroup IWDG_Flag 88 | * @{ 89 | */ 90 | 91 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 92 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 93 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 94 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 95 | /** 96 | * @} 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup IWDG_Exported_Macros 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup IWDG_Exported_Functions 112 | * @{ 113 | */ 114 | 115 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 116 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 117 | void IWDG_SetReload(uint16_t Reload); 118 | void IWDG_ReloadCounter(void); 119 | void IWDG_Enable(void); 120 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 121 | 122 | #ifdef __cplusplus 123 | } 124 | #endif 125 | 126 | #endif /* __STM32F10x_IWDG_H */ 127 | /** 128 | * @} 129 | */ 130 | 131 | /** 132 | * @} 133 | */ 134 | 135 | /** 136 | * @} 137 | */ 138 | 139 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 140 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_PWR_H 24 | #define __STM32F10x_PWR_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup PWR 38 | * @{ 39 | */ 40 | 41 | /** @defgroup PWR_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup PWR_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup PVD_detection_level 54 | * @{ 55 | */ 56 | 57 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 58 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 59 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 60 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 61 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 62 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 63 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 64 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 65 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ 66 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ 67 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ 68 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup Regulator_state_is_STOP_mode 74 | * @{ 75 | */ 76 | 77 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 78 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 79 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 80 | ((REGULATOR) == PWR_Regulator_LowPower)) 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup STOP_mode_entry 86 | * @{ 87 | */ 88 | 89 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 90 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 91 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 92 | 93 | /** 94 | * @} 95 | */ 96 | 97 | /** @defgroup PWR_Flag 98 | * @{ 99 | */ 100 | 101 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 102 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 103 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 104 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 105 | ((FLAG) == PWR_FLAG_PVDO)) 106 | 107 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 108 | /** 109 | * @} 110 | */ 111 | 112 | /** 113 | * @} 114 | */ 115 | 116 | /** @defgroup PWR_Exported_Macros 117 | * @{ 118 | */ 119 | 120 | /** 121 | * @} 122 | */ 123 | 124 | /** @defgroup PWR_Exported_Functions 125 | * @{ 126 | */ 127 | 128 | void PWR_DeInit(void); 129 | void PWR_BackupAccessCmd(FunctionalState NewState); 130 | void PWR_PVDCmd(FunctionalState NewState); 131 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 132 | void PWR_WakeUpPinCmd(FunctionalState NewState); 133 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 134 | void PWR_EnterSTANDBYMode(void); 135 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 136 | void PWR_ClearFlag(uint32_t PWR_FLAG); 137 | 138 | #ifdef __cplusplus 139 | } 140 | #endif 141 | 142 | #endif /* __STM32F10x_PWR_H */ 143 | /** 144 | * @} 145 | */ 146 | 147 | /** 148 | * @} 149 | */ 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 156 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_rtc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the RTC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_RTC_H 24 | #define __STM32F10x_RTC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup RTC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup RTC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup RTC_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup RTC_interrupts_define 54 | * @{ 55 | */ 56 | 57 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ 58 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ 59 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ 60 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) 61 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ 62 | ((IT) == RTC_IT_SEC)) 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup RTC_interrupts_flags 68 | * @{ 69 | */ 70 | 71 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ 72 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ 73 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ 74 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ 75 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ 76 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) 77 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ 78 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ 79 | ((FLAG) == RTC_FLAG_SEC)) 80 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | /** 87 | * @} 88 | */ 89 | 90 | /** @defgroup RTC_Exported_Macros 91 | * @{ 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @defgroup RTC_Exported_Functions 99 | * @{ 100 | */ 101 | 102 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 103 | void RTC_EnterConfigMode(void); 104 | void RTC_ExitConfigMode(void); 105 | uint32_t RTC_GetCounter(void); 106 | void RTC_SetCounter(uint32_t CounterValue); 107 | void RTC_SetPrescaler(uint32_t PrescalerValue); 108 | void RTC_SetAlarm(uint32_t AlarmValue); 109 | uint32_t RTC_GetDivider(void); 110 | void RTC_WaitForLastTask(void); 111 | void RTC_WaitForSynchro(void); 112 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 113 | void RTC_ClearFlag(uint16_t RTC_FLAG); 114 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 115 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 116 | 117 | #ifdef __cplusplus 118 | } 119 | #endif 120 | 121 | #endif /* __STM32F10x_RTC_H */ 122 | /** 123 | * @} 124 | */ 125 | 126 | /** 127 | * @} 128 | */ 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 135 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/inc/stm32f10x_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file contains all the functions prototypes for the WWDG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_WWDG_H 24 | #define __STM32F10x_WWDG_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup WWDG 38 | * @{ 39 | */ 40 | 41 | /** @defgroup WWDG_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup WWDG_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup WWDG_Prescaler 54 | * @{ 55 | */ 56 | 57 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 58 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 59 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 60 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 61 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 62 | ((PRESCALER) == WWDG_Prescaler_2) || \ 63 | ((PRESCALER) == WWDG_Prescaler_4) || \ 64 | ((PRESCALER) == WWDG_Prescaler_8)) 65 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 66 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup WWDG_Exported_Macros 77 | * @{ 78 | */ 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @defgroup WWDG_Exported_Functions 84 | * @{ 85 | */ 86 | 87 | void WWDG_DeInit(void); 88 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 89 | void WWDG_SetWindowValue(uint8_t WindowValue); 90 | void WWDG_EnableIT(void); 91 | void WWDG_SetCounter(uint8_t Counter); 92 | void WWDG_Enable(uint8_t Counter); 93 | FlagStatus WWDG_GetFlagStatus(void); 94 | void WWDG_ClearFlag(void); 95 | 96 | #ifdef __cplusplus 97 | } 98 | #endif 99 | 100 | #endif /* __STM32F10x_WWDG_H */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | /** 111 | * @} 112 | */ 113 | 114 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 115 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "misc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup MISC 30 | * @brief MISC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup MISC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup MISC_Private_Defines 43 | * @{ 44 | */ 45 | 46 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 47 | /** 48 | * @} 49 | */ 50 | 51 | /** @defgroup MISC_Private_Macros 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @defgroup MISC_Private_Variables 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup MISC_Private_FunctionPrototypes 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup MISC_Private_Functions 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @brief Configures the priority grouping: pre-emption priority and subpriority. 81 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 82 | * This parameter can be one of the following values: 83 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority 84 | * 4 bits for subpriority 85 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority 86 | * 3 bits for subpriority 87 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority 88 | * 2 bits for subpriority 89 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority 90 | * 1 bits for subpriority 91 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority 92 | * 0 bits for subpriority 93 | * @retval None 94 | */ 95 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 96 | { 97 | /* Check the parameters */ 98 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 99 | 100 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 101 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 102 | } 103 | 104 | /** 105 | * @brief Initializes the NVIC peripheral according to the specified 106 | * parameters in the NVIC_InitStruct. 107 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 108 | * the configuration information for the specified NVIC peripheral. 109 | * @retval None 110 | */ 111 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 112 | { 113 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 114 | 115 | /* Check the parameters */ 116 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 117 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 118 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 119 | 120 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 121 | { 122 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 123 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 124 | tmppre = (0x4 - tmppriority); 125 | tmpsub = tmpsub >> tmppriority; 126 | 127 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 128 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 129 | tmppriority = tmppriority << 0x04; 130 | 131 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 132 | 133 | /* Enable the Selected IRQ Channels --------------------------------------*/ 134 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 135 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 136 | } 137 | else 138 | { 139 | /* Disable the Selected IRQ Channels -------------------------------------*/ 140 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 141 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 142 | } 143 | } 144 | 145 | /** 146 | * @brief Sets the vector table location and Offset. 147 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 148 | * This parameter can be one of the following values: 149 | * @arg NVIC_VectTab_RAM 150 | * @arg NVIC_VectTab_FLASH 151 | * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. 152 | * @retval None 153 | */ 154 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 155 | { 156 | /* Check the parameters */ 157 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 158 | assert_param(IS_NVIC_OFFSET(Offset)); 159 | 160 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 161 | } 162 | 163 | /** 164 | * @brief Selects the condition for the system to enter low power mode. 165 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 166 | * This parameter can be one of the following values: 167 | * @arg NVIC_LP_SEVONPEND 168 | * @arg NVIC_LP_SLEEPDEEP 169 | * @arg NVIC_LP_SLEEPONEXIT 170 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 171 | * @retval None 172 | */ 173 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 174 | { 175 | /* Check the parameters */ 176 | assert_param(IS_NVIC_LP(LowPowerMode)); 177 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 178 | 179 | if (NewState != DISABLE) 180 | { 181 | SCB->SCR |= LowPowerMode; 182 | } 183 | else 184 | { 185 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 186 | } 187 | } 188 | 189 | /** 190 | * @brief Configures the SysTick clock source. 191 | * @param SysTick_CLKSource: specifies the SysTick clock source. 192 | * This parameter can be one of the following values: 193 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 194 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 195 | * @retval None 196 | */ 197 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 198 | { 199 | /* Check the parameters */ 200 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 201 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 202 | { 203 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 204 | } 205 | else 206 | { 207 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 208 | } 209 | } 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /** 220 | * @} 221 | */ 222 | 223 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 224 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_adc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_adc.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_bkp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the BKP firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_bkp.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup BKP 30 | * @brief BKP driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup BKP_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup BKP_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* ------------ BKP registers bit address in the alias region --------------- */ 47 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE) 48 | 49 | /* --- CR Register ----*/ 50 | 51 | /* Alias word address of TPAL bit */ 52 | #define CR_OFFSET (BKP_OFFSET + 0x30) 53 | #define TPAL_BitNumber 0x01 54 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 55 | 56 | /* Alias word address of TPE bit */ 57 | #define TPE_BitNumber 0x00 58 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) 59 | 60 | /* --- CSR Register ---*/ 61 | 62 | /* Alias word address of TPIE bit */ 63 | #define CSR_OFFSET (BKP_OFFSET + 0x34) 64 | #define TPIE_BitNumber 0x02 65 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) 66 | 67 | /* Alias word address of TIF bit */ 68 | #define TIF_BitNumber 0x09 69 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) 70 | 71 | /* Alias word address of TEF bit */ 72 | #define TEF_BitNumber 0x08 73 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) 74 | 75 | /* ---------------------- BKP registers bit mask ------------------------ */ 76 | 77 | /* RTCCR register bit mask */ 78 | #define RTCCR_CAL_Mask ((uint16_t)0xFF80) 79 | #define RTCCR_Mask ((uint16_t)0xFC7F) 80 | 81 | /* CSR register bit mask */ 82 | #define CSR_CTE_Set ((uint16_t)0x0001) 83 | #define CSR_CTI_Set ((uint16_t)0x0002) 84 | 85 | /** 86 | * @} 87 | */ 88 | 89 | 90 | /** @defgroup BKP_Private_Macros 91 | * @{ 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @defgroup BKP_Private_Variables 99 | * @{ 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup BKP_Private_FunctionPrototypes 107 | * @{ 108 | */ 109 | 110 | /** 111 | * @} 112 | */ 113 | 114 | /** @defgroup BKP_Private_Functions 115 | * @{ 116 | */ 117 | 118 | /** 119 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 120 | * @param None 121 | * @retval None 122 | */ 123 | void BKP_DeInit(void) 124 | { 125 | RCC_BackupResetCmd(ENABLE); 126 | RCC_BackupResetCmd(DISABLE); 127 | } 128 | 129 | /** 130 | * @brief Configures the Tamper Pin active level. 131 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 132 | * This parameter can be one of the following values: 133 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level 134 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level 135 | * @retval None 136 | */ 137 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 138 | { 139 | /* Check the parameters */ 140 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); 141 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; 142 | } 143 | 144 | /** 145 | * @brief Enables or disables the Tamper Pin activation. 146 | * @param NewState: new state of the Tamper Pin activation. 147 | * This parameter can be: ENABLE or DISABLE. 148 | * @retval None 149 | */ 150 | void BKP_TamperPinCmd(FunctionalState NewState) 151 | { 152 | /* Check the parameters */ 153 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 154 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; 155 | } 156 | 157 | /** 158 | * @brief Enables or disables the Tamper Pin Interrupt. 159 | * @param NewState: new state of the Tamper Pin Interrupt. 160 | * This parameter can be: ENABLE or DISABLE. 161 | * @retval None 162 | */ 163 | void BKP_ITConfig(FunctionalState NewState) 164 | { 165 | /* Check the parameters */ 166 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 167 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; 168 | } 169 | 170 | /** 171 | * @brief Select the RTC output source to output on the Tamper pin. 172 | * @param BKP_RTCOutputSource: specifies the RTC output source. 173 | * This parameter can be one of the following values: 174 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. 175 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency 176 | * divided by 64 on the Tamper pin. 177 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on 178 | * the Tamper pin. 179 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on 180 | * the Tamper pin. 181 | * @retval None 182 | */ 183 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 184 | { 185 | uint16_t tmpreg = 0; 186 | /* Check the parameters */ 187 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); 188 | tmpreg = BKP->RTCCR; 189 | /* Clear CCO, ASOE and ASOS bits */ 190 | tmpreg &= RTCCR_Mask; 191 | 192 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ 193 | tmpreg |= BKP_RTCOutputSource; 194 | /* Store the new value */ 195 | BKP->RTCCR = tmpreg; 196 | } 197 | 198 | /** 199 | * @brief Sets RTC Clock Calibration value. 200 | * @param CalibrationValue: specifies the RTC Clock Calibration value. 201 | * This parameter must be a number between 0 and 0x7F. 202 | * @retval None 203 | */ 204 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 205 | { 206 | uint16_t tmpreg = 0; 207 | /* Check the parameters */ 208 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); 209 | tmpreg = BKP->RTCCR; 210 | /* Clear CAL[6:0] bits */ 211 | tmpreg &= RTCCR_CAL_Mask; 212 | /* Set CAL[6:0] bits according to CalibrationValue value */ 213 | tmpreg |= CalibrationValue; 214 | /* Store the new value */ 215 | BKP->RTCCR = tmpreg; 216 | } 217 | 218 | /** 219 | * @brief Writes user data to the specified Data Backup Register. 220 | * @param BKP_DR: specifies the Data Backup Register. 221 | * This parameter can be BKP_DRx where x:[1, 42] 222 | * @param Data: data to write 223 | * @retval None 224 | */ 225 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 226 | { 227 | __IO uint32_t tmp = 0; 228 | 229 | /* Check the parameters */ 230 | assert_param(IS_BKP_DR(BKP_DR)); 231 | 232 | tmp = (uint32_t)BKP_BASE; 233 | tmp += BKP_DR; 234 | 235 | *(__IO uint32_t *) tmp = Data; 236 | } 237 | 238 | /** 239 | * @brief Reads data from the specified Data Backup Register. 240 | * @param BKP_DR: specifies the Data Backup Register. 241 | * This parameter can be BKP_DRx where x:[1, 42] 242 | * @retval The content of the specified Data Backup Register 243 | */ 244 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 245 | { 246 | __IO uint32_t tmp = 0; 247 | 248 | /* Check the parameters */ 249 | assert_param(IS_BKP_DR(BKP_DR)); 250 | 251 | tmp = (uint32_t)BKP_BASE; 252 | tmp += BKP_DR; 253 | 254 | return (*(__IO uint16_t *) tmp); 255 | } 256 | 257 | /** 258 | * @brief Checks whether the Tamper Pin Event flag is set or not. 259 | * @param None 260 | * @retval The new state of the Tamper Pin Event flag (SET or RESET). 261 | */ 262 | FlagStatus BKP_GetFlagStatus(void) 263 | { 264 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); 265 | } 266 | 267 | /** 268 | * @brief Clears Tamper Pin Event pending flag. 269 | * @param None 270 | * @retval None 271 | */ 272 | void BKP_ClearFlag(void) 273 | { 274 | /* Set CTE bit to clear Tamper Pin Event flag */ 275 | BKP->CSR |= CSR_CTE_Set; 276 | } 277 | 278 | /** 279 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 280 | * @param None 281 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET). 282 | */ 283 | ITStatus BKP_GetITStatus(void) 284 | { 285 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); 286 | } 287 | 288 | /** 289 | * @brief Clears Tamper Pin Interrupt pending bit. 290 | * @param None 291 | * @retval None 292 | */ 293 | void BKP_ClearITPendingBit(void) 294 | { 295 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ 296 | BKP->CSR |= CSR_CTI_Set; 297 | } 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | /** 308 | * @} 309 | */ 310 | 311 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 312 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_can.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_can.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_cec.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the CEC firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_cec.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup CEC 30 | * @brief CEC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup CEC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | 43 | /** @defgroup CEC_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* ------------ CEC registers bit address in the alias region ----------- */ 48 | #define CEC_OFFSET (CEC_BASE - PERIPH_BASE) 49 | 50 | /* --- CFGR Register ---*/ 51 | 52 | /* Alias word address of PE bit */ 53 | #define CFGR_OFFSET (CEC_OFFSET + 0x00) 54 | #define PE_BitNumber 0x00 55 | #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) 56 | 57 | /* Alias word address of IE bit */ 58 | #define IE_BitNumber 0x01 59 | #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of TSOM bit */ 64 | #define CSR_OFFSET (CEC_OFFSET + 0x10) 65 | #define TSOM_BitNumber 0x00 66 | #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) 67 | 68 | /* Alias word address of TEOM bit */ 69 | #define TEOM_BitNumber 0x01 70 | #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) 71 | 72 | #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ 73 | #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | 80 | /** @defgroup CEC_Private_Macros 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | 89 | /** @defgroup CEC_Private_Variables 90 | * @{ 91 | */ 92 | 93 | /** 94 | * @} 95 | */ 96 | 97 | 98 | /** @defgroup CEC_Private_FunctionPrototypes 99 | * @{ 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | 107 | /** @defgroup CEC_Private_Functions 108 | * @{ 109 | */ 110 | 111 | /** 112 | * @brief Deinitializes the CEC peripheral registers to their default reset 113 | * values. 114 | * @param None 115 | * @retval None 116 | */ 117 | void CEC_DeInit(void) 118 | { 119 | /* Enable CEC reset state */ 120 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); 121 | /* Release CEC from reset state */ 122 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 123 | } 124 | 125 | 126 | /** 127 | * @brief Initializes the CEC peripheral according to the specified 128 | * parameters in the CEC_InitStruct. 129 | * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that 130 | * contains the configuration information for the specified 131 | * CEC peripheral. 132 | * @retval None 133 | */ 134 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) 135 | { 136 | uint16_t tmpreg = 0; 137 | 138 | /* Check the parameters */ 139 | assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 140 | assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); 141 | 142 | /*---------------------------- CEC CFGR Configuration -----------------*/ 143 | /* Get the CEC CFGR value */ 144 | tmpreg = CEC->CFGR; 145 | 146 | /* Clear BTEM and BPEM bits */ 147 | tmpreg &= CFGR_CLEAR_Mask; 148 | 149 | /* Configure CEC: Bit Timing Error and Bit Period Error */ 150 | tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); 151 | 152 | /* Write to CEC CFGR register*/ 153 | CEC->CFGR = tmpreg; 154 | 155 | } 156 | 157 | /** 158 | * @brief Enables or disables the specified CEC peripheral. 159 | * @param NewState: new state of the CEC peripheral. 160 | * This parameter can be: ENABLE or DISABLE. 161 | * @retval None 162 | */ 163 | void CEC_Cmd(FunctionalState NewState) 164 | { 165 | /* Check the parameters */ 166 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 167 | 168 | *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; 169 | 170 | if(NewState == DISABLE) 171 | { 172 | /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ 173 | while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) 174 | { 175 | } 176 | } 177 | } 178 | 179 | /** 180 | * @brief Enables or disables the CEC interrupt. 181 | * @param NewState: new state of the CEC interrupt. 182 | * This parameter can be: ENABLE or DISABLE. 183 | * @retval None 184 | */ 185 | void CEC_ITConfig(FunctionalState NewState) 186 | { 187 | /* Check the parameters */ 188 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 189 | 190 | *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; 191 | } 192 | 193 | /** 194 | * @brief Defines the Own Address of the CEC device. 195 | * @param CEC_OwnAddress: The CEC own address 196 | * @retval None 197 | */ 198 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) 199 | { 200 | /* Check the parameters */ 201 | assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); 202 | 203 | /* Set the CEC own address */ 204 | CEC->OAR = CEC_OwnAddress; 205 | } 206 | 207 | /** 208 | * @brief Sets the CEC prescaler value. 209 | * @param CEC_Prescaler: CEC prescaler new value 210 | * @retval None 211 | */ 212 | void CEC_SetPrescaler(uint16_t CEC_Prescaler) 213 | { 214 | /* Check the parameters */ 215 | assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); 216 | 217 | /* Set the Prescaler value*/ 218 | CEC->PRES = CEC_Prescaler; 219 | } 220 | 221 | /** 222 | * @brief Transmits single data through the CEC peripheral. 223 | * @param Data: the data to transmit. 224 | * @retval None 225 | */ 226 | void CEC_SendDataByte(uint8_t Data) 227 | { 228 | /* Transmit Data */ 229 | CEC->TXD = Data ; 230 | } 231 | 232 | 233 | /** 234 | * @brief Returns the most recent received data by the CEC peripheral. 235 | * @param None 236 | * @retval The received data. 237 | */ 238 | uint8_t CEC_ReceiveDataByte(void) 239 | { 240 | /* Receive Data */ 241 | return (uint8_t)(CEC->RXD); 242 | } 243 | 244 | /** 245 | * @brief Starts a new message. 246 | * @param None 247 | * @retval None 248 | */ 249 | void CEC_StartOfMessage(void) 250 | { 251 | /* Starts of new message */ 252 | *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; 253 | } 254 | 255 | /** 256 | * @brief Transmits message with or without an EOM bit. 257 | * @param NewState: new state of the CEC Tx End Of Message. 258 | * This parameter can be: ENABLE or DISABLE. 259 | * @retval None 260 | */ 261 | void CEC_EndOfMessageCmd(FunctionalState NewState) 262 | { 263 | /* Check the parameters */ 264 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 265 | 266 | /* The data byte will be transmitted with or without an EOM bit*/ 267 | *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; 268 | } 269 | 270 | /** 271 | * @brief Gets the CEC flag status 272 | * @param CEC_FLAG: specifies the CEC flag to check. 273 | * This parameter can be one of the following values: 274 | * @arg CEC_FLAG_BTE: Bit Timing Error 275 | * @arg CEC_FLAG_BPE: Bit Period Error 276 | * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error 277 | * @arg CEC_FLAG_SBE: Start Bit Error 278 | * @arg CEC_FLAG_ACKE: Block Acknowledge Error 279 | * @arg CEC_FLAG_LINE: Line Error 280 | * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error 281 | * @arg CEC_FLAG_TEOM: Tx End Of Message 282 | * @arg CEC_FLAG_TERR: Tx Error 283 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 284 | * @arg CEC_FLAG_RSOM: Rx Start Of Message 285 | * @arg CEC_FLAG_REOM: Rx End Of Message 286 | * @arg CEC_FLAG_RERR: Rx Error 287 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 288 | * @retval The new state of CEC_FLAG (SET or RESET) 289 | */ 290 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 291 | { 292 | FlagStatus bitstatus = RESET; 293 | uint32_t cecreg = 0, cecbase = 0; 294 | 295 | /* Check the parameters */ 296 | assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); 297 | 298 | /* Get the CEC peripheral base address */ 299 | cecbase = (uint32_t)(CEC_BASE); 300 | 301 | /* Read flag register index */ 302 | cecreg = CEC_FLAG >> 28; 303 | 304 | /* Get bit[23:0] of the flag */ 305 | CEC_FLAG &= FLAG_Mask; 306 | 307 | if(cecreg != 0) 308 | { 309 | /* Flag in CEC ESR Register */ 310 | CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); 311 | 312 | /* Get the CEC ESR register address */ 313 | cecbase += 0xC; 314 | } 315 | else 316 | { 317 | /* Get the CEC CSR register address */ 318 | cecbase += 0x10; 319 | } 320 | 321 | if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) 322 | { 323 | /* CEC_FLAG is set */ 324 | bitstatus = SET; 325 | } 326 | else 327 | { 328 | /* CEC_FLAG is reset */ 329 | bitstatus = RESET; 330 | } 331 | 332 | /* Return the CEC_FLAG status */ 333 | return bitstatus; 334 | } 335 | 336 | /** 337 | * @brief Clears the CEC's pending flags. 338 | * @param CEC_FLAG: specifies the flag to clear. 339 | * This parameter can be any combination of the following values: 340 | * @arg CEC_FLAG_TERR: Tx Error 341 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 342 | * @arg CEC_FLAG_RSOM: Rx Start Of Message 343 | * @arg CEC_FLAG_REOM: Rx End Of Message 344 | * @arg CEC_FLAG_RERR: Rx Error 345 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 346 | * @retval None 347 | */ 348 | void CEC_ClearFlag(uint32_t CEC_FLAG) 349 | { 350 | uint32_t tmp = 0x0; 351 | 352 | /* Check the parameters */ 353 | assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); 354 | 355 | tmp = CEC->CSR & 0x2; 356 | 357 | /* Clear the selected CEC flags */ 358 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); 359 | } 360 | 361 | /** 362 | * @brief Checks whether the specified CEC interrupt has occurred or not. 363 | * @param CEC_IT: specifies the CEC interrupt source to check. 364 | * This parameter can be one of the following values: 365 | * @arg CEC_IT_TERR: Tx Error 366 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished 367 | * @arg CEC_IT_RERR: Rx Error 368 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished 369 | * @retval The new state of CEC_IT (SET or RESET). 370 | */ 371 | ITStatus CEC_GetITStatus(uint8_t CEC_IT) 372 | { 373 | ITStatus bitstatus = RESET; 374 | uint32_t enablestatus = 0; 375 | 376 | /* Check the parameters */ 377 | assert_param(IS_CEC_GET_IT(CEC_IT)); 378 | 379 | /* Get the CEC IT enable bit status */ 380 | enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; 381 | 382 | /* Check the status of the specified CEC interrupt */ 383 | if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) 384 | { 385 | /* CEC_IT is set */ 386 | bitstatus = SET; 387 | } 388 | else 389 | { 390 | /* CEC_IT is reset */ 391 | bitstatus = RESET; 392 | } 393 | /* Return the CEC_IT status */ 394 | return bitstatus; 395 | } 396 | 397 | /** 398 | * @brief Clears the CEC's interrupt pending bits. 399 | * @param CEC_IT: specifies the CEC interrupt pending bit to clear. 400 | * This parameter can be any combination of the following values: 401 | * @arg CEC_IT_TERR: Tx Error 402 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished 403 | * @arg CEC_IT_RERR: Rx Error 404 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished 405 | * @retval None 406 | */ 407 | void CEC_ClearITPendingBit(uint16_t CEC_IT) 408 | { 409 | uint32_t tmp = 0x0; 410 | 411 | /* Check the parameters */ 412 | assert_param(IS_CEC_GET_IT(CEC_IT)); 413 | 414 | tmp = CEC->CSR & 0x2; 415 | 416 | /* Clear the selected CEC interrupt pending bits */ 417 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); 418 | } 419 | 420 | /** 421 | * @} 422 | */ 423 | 424 | /** 425 | * @} 426 | */ 427 | 428 | /** 429 | * @} 430 | */ 431 | 432 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 433 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the CRC firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_crc.h" 23 | 24 | /** @addtogroup STM32F10x_StdPeriph_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup CRC 29 | * @brief CRC driver modules 30 | * @{ 31 | */ 32 | 33 | /** @defgroup CRC_Private_TypesDefinitions 34 | * @{ 35 | */ 36 | 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup CRC_Private_Defines 42 | * @{ 43 | */ 44 | 45 | /* CR register bit mask */ 46 | 47 | #define CR_RESET_Set ((uint32_t)0x00000001) 48 | 49 | /** 50 | * @} 51 | */ 52 | 53 | /** @defgroup CRC_Private_Macros 54 | * @{ 55 | */ 56 | 57 | /** 58 | * @} 59 | */ 60 | 61 | /** @defgroup CRC_Private_Variables 62 | * @{ 63 | */ 64 | 65 | /** 66 | * @} 67 | */ 68 | 69 | /** @defgroup CRC_Private_FunctionPrototypes 70 | * @{ 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup CRC_Private_Functions 78 | * @{ 79 | */ 80 | 81 | /** 82 | * @brief Resets the CRC Data register (DR). 83 | * @param None 84 | * @retval None 85 | */ 86 | void CRC_ResetDR(void) 87 | { 88 | /* Reset CRC generator */ 89 | CRC->CR = CR_RESET_Set; 90 | } 91 | 92 | /** 93 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 94 | * @param Data: data word(32-bit) to compute its CRC 95 | * @retval 32-bit CRC 96 | */ 97 | uint32_t CRC_CalcCRC(uint32_t Data) 98 | { 99 | CRC->DR = Data; 100 | 101 | return (CRC->DR); 102 | } 103 | 104 | /** 105 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 106 | * @param pBuffer: pointer to the buffer containing the data to be computed 107 | * @param BufferLength: length of the buffer to be computed 108 | * @retval 32-bit CRC 109 | */ 110 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 111 | { 112 | uint32_t index = 0; 113 | 114 | for(index = 0; index < BufferLength; index++) 115 | { 116 | CRC->DR = pBuffer[index]; 117 | } 118 | return (CRC->DR); 119 | } 120 | 121 | /** 122 | * @brief Returns the current CRC value. 123 | * @param None 124 | * @retval 32-bit CRC 125 | */ 126 | uint32_t CRC_GetCRC(void) 127 | { 128 | return (CRC->DR); 129 | } 130 | 131 | /** 132 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 133 | * @param IDValue: 8-bit value to be stored in the ID register 134 | * @retval None 135 | */ 136 | void CRC_SetIDRegister(uint8_t IDValue) 137 | { 138 | CRC->IDR = IDValue; 139 | } 140 | 141 | /** 142 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 143 | * @param None 144 | * @retval 8-bit value of the ID register 145 | */ 146 | uint8_t CRC_GetIDRegister(void) 147 | { 148 | return (CRC->IDR); 149 | } 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 164 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_dac.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_dac.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the DBGMCU firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_dbgmcu.h" 23 | 24 | /** @addtogroup STM32F10x_StdPeriph_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup DBGMCU 29 | * @brief DBGMCU driver modules 30 | * @{ 31 | */ 32 | 33 | /** @defgroup DBGMCU_Private_TypesDefinitions 34 | * @{ 35 | */ 36 | 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup DBGMCU_Private_Defines 42 | * @{ 43 | */ 44 | 45 | #define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup DBGMCU_Private_Macros 51 | * @{ 52 | */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup DBGMCU_Private_Variables 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup DBGMCU_Private_FunctionPrototypes 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup DBGMCU_Private_Functions 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @brief Returns the device revision identifier. 80 | * @param None 81 | * @retval Device revision identifier 82 | */ 83 | uint32_t DBGMCU_GetREVID(void) 84 | { 85 | return(DBGMCU->IDCODE >> 16); 86 | } 87 | 88 | /** 89 | * @brief Returns the device identifier. 90 | * @param None 91 | * @retval Device identifier 92 | */ 93 | uint32_t DBGMCU_GetDEVID(void) 94 | { 95 | return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); 96 | } 97 | 98 | /** 99 | * @brief Configures the specified peripheral and low power mode behavior 100 | * when the MCU under Debug mode. 101 | * @param DBGMCU_Periph: specifies the peripheral and low power mode. 102 | * This parameter can be any combination of the following values: 103 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode 104 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 105 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 106 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 107 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 108 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 109 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted 110 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 111 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted 112 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted 113 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted 114 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted 115 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted 116 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 117 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted 118 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted 119 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 120 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 121 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 122 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 123 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted 124 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted 125 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted 126 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted 127 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted 128 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 129 | * @param NewState: new state of the specified peripheral in Debug mode. 130 | * This parameter can be: ENABLE or DISABLE. 131 | * @retval None 132 | */ 133 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 134 | { 135 | /* Check the parameters */ 136 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 137 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 138 | 139 | if (NewState != DISABLE) 140 | { 141 | DBGMCU->CR |= DBGMCU_Periph; 142 | } 143 | else 144 | { 145 | DBGMCU->CR &= ~DBGMCU_Periph; 146 | } 147 | } 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** 154 | * @} 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 162 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_dma.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_dma.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_exti.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_exti.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_flash.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_fsmc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_fsmc.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_i2c.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_i2c.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the IWDG firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_iwdg.h" 23 | 24 | /** @addtogroup STM32F10x_StdPeriph_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup IWDG 29 | * @brief IWDG driver modules 30 | * @{ 31 | */ 32 | 33 | /** @defgroup IWDG_Private_TypesDefinitions 34 | * @{ 35 | */ 36 | 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup IWDG_Private_Defines 42 | * @{ 43 | */ 44 | 45 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 46 | 47 | /* KR register bit mask */ 48 | #define KR_KEY_Reload ((uint16_t)0xAAAA) 49 | #define KR_KEY_Enable ((uint16_t)0xCCCC) 50 | 51 | /** 52 | * @} 53 | */ 54 | 55 | /** @defgroup IWDG_Private_Macros 56 | * @{ 57 | */ 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /** @defgroup IWDG_Private_Variables 64 | * @{ 65 | */ 66 | 67 | /** 68 | * @} 69 | */ 70 | 71 | /** @defgroup IWDG_Private_FunctionPrototypes 72 | * @{ 73 | */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @defgroup IWDG_Private_Functions 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 85 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 86 | * This parameter can be one of the following values: 87 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 88 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 89 | * @retval None 90 | */ 91 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 92 | { 93 | /* Check the parameters */ 94 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 95 | IWDG->KR = IWDG_WriteAccess; 96 | } 97 | 98 | /** 99 | * @brief Sets IWDG Prescaler value. 100 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 101 | * This parameter can be one of the following values: 102 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 103 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 104 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 105 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 106 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 107 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 108 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 109 | * @retval None 110 | */ 111 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 112 | { 113 | /* Check the parameters */ 114 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 115 | IWDG->PR = IWDG_Prescaler; 116 | } 117 | 118 | /** 119 | * @brief Sets IWDG Reload value. 120 | * @param Reload: specifies the IWDG Reload value. 121 | * This parameter must be a number between 0 and 0x0FFF. 122 | * @retval None 123 | */ 124 | void IWDG_SetReload(uint16_t Reload) 125 | { 126 | /* Check the parameters */ 127 | assert_param(IS_IWDG_RELOAD(Reload)); 128 | IWDG->RLR = Reload; 129 | } 130 | 131 | /** 132 | * @brief Reloads IWDG counter with value defined in the reload register 133 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 134 | * @param None 135 | * @retval None 136 | */ 137 | void IWDG_ReloadCounter(void) 138 | { 139 | IWDG->KR = KR_KEY_Reload; 140 | } 141 | 142 | /** 143 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 144 | * @param None 145 | * @retval None 146 | */ 147 | void IWDG_Enable(void) 148 | { 149 | IWDG->KR = KR_KEY_Enable; 150 | } 151 | 152 | /** 153 | * @brief Checks whether the specified IWDG flag is set or not. 154 | * @param IWDG_FLAG: specifies the flag to check. 155 | * This parameter can be one of the following values: 156 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 157 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 158 | * @retval The new state of IWDG_FLAG (SET or RESET). 159 | */ 160 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 161 | { 162 | FlagStatus bitstatus = RESET; 163 | /* Check the parameters */ 164 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 165 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 166 | { 167 | bitstatus = SET; 168 | } 169 | else 170 | { 171 | bitstatus = RESET; 172 | } 173 | /* Return the flag status */ 174 | return bitstatus; 175 | } 176 | 177 | /** 178 | * @} 179 | */ 180 | 181 | /** 182 | * @} 183 | */ 184 | 185 | /** 186 | * @} 187 | */ 188 | 189 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 190 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_pwr.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the PWR firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_pwr.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup PWR 30 | * @brief PWR driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup PWR_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup PWR_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* --------- PWR registers bit address in the alias region ---------- */ 47 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 48 | 49 | /* --- CR Register ---*/ 50 | 51 | /* Alias word address of DBP bit */ 52 | #define CR_OFFSET (PWR_OFFSET + 0x00) 53 | #define DBP_BitNumber 0x08 54 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 55 | 56 | /* Alias word address of PVDE bit */ 57 | #define PVDE_BitNumber 0x04 58 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 59 | 60 | /* --- CSR Register ---*/ 61 | 62 | /* Alias word address of EWUP bit */ 63 | #define CSR_OFFSET (PWR_OFFSET + 0x04) 64 | #define EWUP_BitNumber 0x08 65 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 66 | 67 | /* ------------------ PWR registers bit mask ------------------------ */ 68 | 69 | /* CR register bit mask */ 70 | #define CR_PDDS_Set ((uint32_t)0x00000002) 71 | #define CR_DS_Mask ((uint32_t)0xFFFFFFFC) 72 | #define CR_CWUF_Set ((uint32_t)0x00000004) 73 | #define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) 74 | 75 | /* --------- Cortex System Control register bit mask ---------------- */ 76 | 77 | /* Cortex System Control register address */ 78 | #define SCB_SysCtrl ((uint32_t)0xE000ED10) 79 | 80 | /* SLEEPDEEP bit mask */ 81 | #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) 82 | #define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB) 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | /** @defgroup PWR_Private_Macros 89 | * @{ 90 | */ 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup PWR_Private_Variables 97 | * @{ 98 | */ 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** @defgroup PWR_Private_FunctionPrototypes 105 | * @{ 106 | */ 107 | 108 | /** 109 | * @} 110 | */ 111 | 112 | /** @defgroup PWR_Private_Functions 113 | * @{ 114 | */ 115 | 116 | /** 117 | * @brief Deinitializes the PWR peripheral registers to their default reset values. 118 | * @param None 119 | * @retval None 120 | */ 121 | void PWR_DeInit(void) 122 | { 123 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 124 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 125 | } 126 | 127 | /** 128 | * @brief Enables or disables access to the RTC and backup registers. 129 | * @param NewState: new state of the access to the RTC and backup registers. 130 | * This parameter can be: ENABLE or DISABLE. 131 | * @retval None 132 | */ 133 | void PWR_BackupAccessCmd(FunctionalState NewState) 134 | { 135 | /* Check the parameters */ 136 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 137 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 138 | } 139 | 140 | /** 141 | * @brief Enables or disables the Power Voltage Detector(PVD). 142 | * @param NewState: new state of the PVD. 143 | * This parameter can be: ENABLE or DISABLE. 144 | * @retval None 145 | */ 146 | void PWR_PVDCmd(FunctionalState NewState) 147 | { 148 | /* Check the parameters */ 149 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 150 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 151 | } 152 | 153 | /** 154 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 155 | * @param PWR_PVDLevel: specifies the PVD detection level 156 | * This parameter can be one of the following values: 157 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 158 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 159 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 160 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 161 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 162 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 163 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 164 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 165 | * @retval None 166 | */ 167 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 168 | { 169 | uint32_t tmpreg = 0; 170 | /* Check the parameters */ 171 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 172 | tmpreg = PWR->CR; 173 | /* Clear PLS[7:5] bits */ 174 | tmpreg &= CR_PLS_Mask; 175 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 176 | tmpreg |= PWR_PVDLevel; 177 | /* Store the new value */ 178 | PWR->CR = tmpreg; 179 | } 180 | 181 | /** 182 | * @brief Enables or disables the WakeUp Pin functionality. 183 | * @param NewState: new state of the WakeUp Pin functionality. 184 | * This parameter can be: ENABLE or DISABLE. 185 | * @retval None 186 | */ 187 | void PWR_WakeUpPinCmd(FunctionalState NewState) 188 | { 189 | /* Check the parameters */ 190 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 191 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 192 | } 193 | 194 | /** 195 | * @brief Enters STOP mode. 196 | * @param PWR_Regulator: specifies the regulator state in STOP mode. 197 | * This parameter can be one of the following values: 198 | * @arg PWR_Regulator_ON: STOP mode with regulator ON 199 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 200 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 201 | * This parameter can be one of the following values: 202 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 203 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 204 | * @retval None 205 | */ 206 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 207 | { 208 | uint32_t tmpreg = 0; 209 | /* Check the parameters */ 210 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 211 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 212 | 213 | /* Select the regulator state in STOP mode ---------------------------------*/ 214 | tmpreg = PWR->CR; 215 | /* Clear PDDS and LPDS bits */ 216 | tmpreg &= CR_DS_Mask; 217 | /* Set LPDS bit according to PWR_Regulator value */ 218 | tmpreg |= PWR_Regulator; 219 | /* Store the new value */ 220 | PWR->CR = tmpreg; 221 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 222 | *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; 223 | 224 | /* Select STOP mode entry --------------------------------------------------*/ 225 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 226 | { 227 | /* Request Wait For Interrupt */ 228 | __WFI(); 229 | } 230 | else 231 | { 232 | /* Request Wait For Event */ 233 | __WFE(); 234 | } 235 | 236 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ 237 | *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset; 238 | } 239 | 240 | /** 241 | * @brief Enters STANDBY mode. 242 | * @param None 243 | * @retval None 244 | */ 245 | void PWR_EnterSTANDBYMode(void) 246 | { 247 | /* Clear Wake-up flag */ 248 | PWR->CR |= CR_CWUF_Set; 249 | /* Select STANDBY mode */ 250 | PWR->CR |= CR_PDDS_Set; 251 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 252 | *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; 253 | /* This option is used to ensure that store operations are completed */ 254 | #if defined ( __CC_ARM ) 255 | __force_stores(); 256 | #endif 257 | /* Request Wait For Interrupt */ 258 | __WFI(); 259 | } 260 | 261 | /** 262 | * @brief Checks whether the specified PWR flag is set or not. 263 | * @param PWR_FLAG: specifies the flag to check. 264 | * This parameter can be one of the following values: 265 | * @arg PWR_FLAG_WU: Wake Up flag 266 | * @arg PWR_FLAG_SB: StandBy flag 267 | * @arg PWR_FLAG_PVDO: PVD Output 268 | * @retval The new state of PWR_FLAG (SET or RESET). 269 | */ 270 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 271 | { 272 | FlagStatus bitstatus = RESET; 273 | /* Check the parameters */ 274 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 275 | 276 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 277 | { 278 | bitstatus = SET; 279 | } 280 | else 281 | { 282 | bitstatus = RESET; 283 | } 284 | /* Return the flag status */ 285 | return bitstatus; 286 | } 287 | 288 | /** 289 | * @brief Clears the PWR's pending flags. 290 | * @param PWR_FLAG: specifies the flag to clear. 291 | * This parameter can be one of the following values: 292 | * @arg PWR_FLAG_WU: Wake Up flag 293 | * @arg PWR_FLAG_SB: StandBy flag 294 | * @retval None 295 | */ 296 | void PWR_ClearFlag(uint32_t PWR_FLAG) 297 | { 298 | /* Check the parameters */ 299 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 300 | 301 | PWR->CR |= PWR_FLAG << 2; 302 | } 303 | 304 | /** 305 | * @} 306 | */ 307 | 308 | /** 309 | * @} 310 | */ 311 | 312 | /** 313 | * @} 314 | */ 315 | 316 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 317 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_rcc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_rcc.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_rtc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_rtc.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_sdio.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_sdio.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_tim.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_tim.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_usart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/Src/StdPeriph_Driver/src/stm32f10x_usart.c -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/src/stm32f10x_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.c 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief This file provides all the WWDG firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_wwdg.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup WWDG 30 | * @brief WWDG driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup WWDG_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup WWDG_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* ----------- WWDG registers bit address in the alias region ----------- */ 47 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) 48 | 49 | /* Alias word address of EWI bit */ 50 | #define CFR_OFFSET (WWDG_OFFSET + 0x04) 51 | #define EWI_BitNumber 0x09 52 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) 53 | 54 | /* --------------------- WWDG registers bit mask ------------------------ */ 55 | 56 | /* CR register bit mask */ 57 | #define CR_WDGA_Set ((uint32_t)0x00000080) 58 | 59 | /* CFR register bit mask */ 60 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 61 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80) 62 | #define BIT_Mask ((uint8_t)0x7F) 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup WWDG_Private_Macros 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup WWDG_Private_Variables 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @defgroup WWDG_Private_FunctionPrototypes 85 | * @{ 86 | */ 87 | 88 | /** 89 | * @} 90 | */ 91 | 92 | /** @defgroup WWDG_Private_Functions 93 | * @{ 94 | */ 95 | 96 | /** 97 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 98 | * @param None 99 | * @retval None 100 | */ 101 | void WWDG_DeInit(void) 102 | { 103 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 105 | } 106 | 107 | /** 108 | * @brief Sets the WWDG Prescaler. 109 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 110 | * This parameter can be one of the following values: 111 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 112 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 113 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 114 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 115 | * @retval None 116 | */ 117 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 118 | { 119 | uint32_t tmpreg = 0; 120 | /* Check the parameters */ 121 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 122 | /* Clear WDGTB[1:0] bits */ 123 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask; 124 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 125 | tmpreg |= WWDG_Prescaler; 126 | /* Store the new value */ 127 | WWDG->CFR = tmpreg; 128 | } 129 | 130 | /** 131 | * @brief Sets the WWDG window value. 132 | * @param WindowValue: specifies the window value to be compared to the downcounter. 133 | * This parameter value must be lower than 0x80. 134 | * @retval None 135 | */ 136 | void WWDG_SetWindowValue(uint8_t WindowValue) 137 | { 138 | __IO uint32_t tmpreg = 0; 139 | 140 | /* Check the parameters */ 141 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 142 | /* Clear W[6:0] bits */ 143 | 144 | tmpreg = WWDG->CFR & CFR_W_Mask; 145 | 146 | /* Set W[6:0] bits according to WindowValue value */ 147 | tmpreg |= WindowValue & (uint32_t) BIT_Mask; 148 | 149 | /* Store the new value */ 150 | WWDG->CFR = tmpreg; 151 | } 152 | 153 | /** 154 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 155 | * @param None 156 | * @retval None 157 | */ 158 | void WWDG_EnableIT(void) 159 | { 160 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; 161 | } 162 | 163 | /** 164 | * @brief Sets the WWDG counter value. 165 | * @param Counter: specifies the watchdog counter value. 166 | * This parameter must be a number between 0x40 and 0x7F. 167 | * @retval None 168 | */ 169 | void WWDG_SetCounter(uint8_t Counter) 170 | { 171 | /* Check the parameters */ 172 | assert_param(IS_WWDG_COUNTER(Counter)); 173 | /* Write to T[6:0] bits to configure the counter value, no need to do 174 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 175 | WWDG->CR = Counter & BIT_Mask; 176 | } 177 | 178 | /** 179 | * @brief Enables WWDG and load the counter value. 180 | * @param Counter: specifies the watchdog counter value. 181 | * This parameter must be a number between 0x40 and 0x7F. 182 | * @retval None 183 | */ 184 | void WWDG_Enable(uint8_t Counter) 185 | { 186 | /* Check the parameters */ 187 | assert_param(IS_WWDG_COUNTER(Counter)); 188 | WWDG->CR = CR_WDGA_Set | Counter; 189 | } 190 | 191 | /** 192 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 193 | * @param None 194 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) 195 | */ 196 | FlagStatus WWDG_GetFlagStatus(void) 197 | { 198 | return (FlagStatus)(WWDG->SR); 199 | } 200 | 201 | /** 202 | * @brief Clears Early Wakeup interrupt flag. 203 | * @param None 204 | * @retval None 205 | */ 206 | void WWDG_ClearFlag(void) 207 | { 208 | WWDG->SR = (uint32_t)RESET; 209 | } 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /** 220 | * @} 221 | */ 222 | 223 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 224 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/Interrupt/stm32f10x_conf.h 4 | * @author MCD Application Team 5 | * @version V3.0.0 6 | * @date 04/06/2009 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2009 STMicroelectronics

19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F10x_CONF_H 23 | #define __STM32F10x_CONF_H 24 | 25 | #include 26 | #include 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | /* Uncomment the line below to enable peripheral header file inclusion */ 30 | #include "stm32f10x_adc.h" 31 | /* #include "stm32f10x_bkp.h" */ 32 | /* #include "stm32f10x_can.h" */ 33 | /* #include "stm32f10x_crc.h" */ 34 | /* #include "stm32f10x_dac.h" */ 35 | /* #include "stm32f10x_dbgmcu.h" */ 36 | #include "stm32f10x_dma.h" 37 | #include "stm32f10x_exti.h" 38 | #include "stm32f10x_flash.h"/**/ 39 | #include "stm32f10x_fsmc.h" 40 | #include "stm32f10x_gpio.h" 41 | /* #include "stm32f10x_i2c.h" */ 42 | /* #include "stm32f10x_iwdg.h" */ 43 | /* #include "stm32f10x_pwr.h" */ 44 | #include "stm32f10x_rcc.h" 45 | /* #include "stm32f10x_rtc.h" */ 46 | #include "stm32f10x_sdio.h" 47 | #include "stm32f10x_spi.h" 48 | #include "stm32f10x_tim.h" 49 | #include "stm32f10x_usart.h" 50 | /* #include "stm32f10x_wwdg.h" */ 51 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 52 | 53 | /* Exported types ------------------------------------------------------------*/ 54 | /* Exported constants --------------------------------------------------------*/ 55 | /* Uncomment the line below to expanse the "assert_param" macro in the 56 | Standard Peripheral Library drivers code */ 57 | /* #define USE_FULL_ASSERT 1 */ 58 | 59 | /* Exported macro ------------------------------------------------------------*/ 60 | #ifdef USE_FULL_ASSERT 61 | /** 62 | * @brief The assert_param macro is used for function's parameters check. 63 | * @param expr: If expr is false, it calls assert_failed function 64 | * which reports the name of the source file and the source 65 | * line number of the call that failed. 66 | * If expr is true, it returns no value. 67 | * @retval : None 68 | */ 69 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 70 | /* Exported functions ------------------------------------------------------- */ 71 | void assert_failed(uint8_t* file, uint32_t line); 72 | #else 73 | #define assert_param(expr) ((void)0) 74 | #endif /* USE_FULL_ASSERT */ 75 | 76 | #endif /* __STM32F10x_CONF_H */ 77 | 78 | /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ 79 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/stm32f10x_it.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_it.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.1 5 | * Date : 06/13/2008 6 | * Description : This file contains the headers of the interrupt handlers. 7 | ******************************************************************************** 8 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 9 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 10 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 11 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 12 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 13 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 14 | *******************************************************************************/ 15 | 16 | /* Define to prevent recursive inclusion -------------------------------------*/ 17 | #ifndef __STM32F10x_IT_H 18 | #define __STM32F10x_IT_H 19 | 20 | 21 | 22 | /* Exported types ------------------------------------------------------------*/ 23 | /* Exported constants --------------------------------------------------------*/ 24 | /* Exported macro ------------------------------------------------------------*/ 25 | /* Exported functions ------------------------------------------------------- */ 26 | 27 | void NMI_Handler(void) __attribute__ ((alias("NMIException"))); 28 | void HardFault_Handler(void) __attribute__ ((alias("HardFaultException"))); 29 | void MemManage_Handler(void) __attribute__ ((alias("MemManageException"))); 30 | void BusFault_Handler(void) __attribute__ ((alias("BusFaultException"))); 31 | void UsageFault_Handler(void) __attribute__ ((alias("UsageFaultException"))); 32 | void DebugMon_Handler(void) __attribute__ ((alias("DebugMonitor"))); 33 | void SVC_Handler(void) __attribute__ ((alias("SVCHandler"))); 34 | /* 35 | void PendSV_Handler(void) __attribute__ ((alias("PendSVC"))); 36 | void SysTick_Handler(void) __attribute__ ((alias("SysTickHandler"))); 37 | */ 38 | 39 | void NMIException(void); 40 | void HardFaultException(void); 41 | void MemManageException(void); 42 | void BusFaultException(void); 43 | void UsageFaultException(void); 44 | void DebugMonitor(void); 45 | void SVCHandler(void); 46 | void PendSVC(void); 47 | void SysTickHandler(void); 48 | void WWDG_IRQHandler(void); 49 | void PVD_IRQHandler(void); 50 | void TAMPER_IRQHandler(void); 51 | void RTC_IRQHandler(void); 52 | void FLASH_IRQHandler(void); 53 | void RCC_IRQHandler(void); 54 | void EXTI0_IRQHandler(void); 55 | void EXTI1_IRQHandler(void); 56 | void EXTI2_IRQHandler(void); 57 | void EXTI3_IRQHandler(void); 58 | void EXTI4_IRQHandler(void); 59 | void DMA1_Channel1_IRQHandler(void); 60 | void DMA1_Channel2_IRQHandler(void); 61 | void DMA1_Channel3_IRQHandler(void); 62 | void DMA1_Channel4_IRQHandler(void); 63 | void DMA1_Channel5_IRQHandler(void); 64 | void DMA1_Channel6_IRQHandler(void); 65 | void DMA1_Channel7_IRQHandler(void); 66 | void ADC1_2_IRQHandler(void); 67 | void USB_HP_CAN_TX_IRQHandler(void); 68 | void USB_LP_CAN_RX0_IRQHandler(void); 69 | void CAN_RX1_IRQHandler(void); 70 | void CAN_SCE_IRQHandler(void); 71 | void EXTI9_5_IRQHandler(void); 72 | void TIM1_BRK_IRQHandler(void); 73 | void TIM1_UP_IRQHandler(void); 74 | void TIM1_TRG_COM_IRQHandler(void); 75 | void TIM1_CC_IRQHandler(void); 76 | void TIM2_IRQHandler(void); 77 | void TIM3_IRQHandler(void); 78 | void TIM4_IRQHandler(void); 79 | void I2C1_EV_IRQHandler(void); 80 | void I2C1_ER_IRQHandler(void); 81 | void I2C2_EV_IRQHandler(void); 82 | void I2C2_ER_IRQHandler(void); 83 | void SPI1_IRQHandler(void); 84 | void SPI2_IRQHandler(void); 85 | void USART1_IRQHandler(void); 86 | void USART2_IRQHandler(void); 87 | void USART3_IRQHandler(void); 88 | void EXTI15_10_IRQHandler(void); 89 | void RTCAlarm_IRQHandler(void); 90 | void USBWakeUp_IRQHandler(void); 91 | void TIM8_BRK_IRQHandler(void); 92 | void TIM8_UP_IRQHandler(void); 93 | void TIM8_TRG_COM_IRQHandler(void); 94 | void TIM8_CC_IRQHandler(void); 95 | void ADC3_IRQHandler(void); 96 | void FSMC_IRQHandler(void); 97 | void SDIO_IRQHandler(void); 98 | void TIM5_IRQHandler(void); 99 | void SPI3_IRQHandler(void); 100 | void UART4_IRQHandler(void); 101 | void UART5_IRQHandler(void); 102 | void TIM6_IRQHandler(void); 103 | void TIM7_IRQHandler(void); 104 | void DMA2_Channel1_IRQHandler(void); 105 | void DMA2_Channel2_IRQHandler(void); 106 | void DMA2_Channel3_IRQHandler(void); 107 | void DMA2_Channel4_5_IRQHandler(void); 108 | 109 | #endif /* __STM32F10x_IT_H */ 110 | 111 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 112 | -------------------------------------------------------------------------------- /Src/StdPeriph_Driver/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.3.0 6 | * @date 04/16/2010 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * 10 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 11 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 12 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 13 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 14 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 15 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 16 | * 17 | *

© COPYRIGHT 2010 STMicroelectronics

18 | ****************************************************************************** 19 | */ 20 | 21 | /** @addtogroup CMSIS 22 | * @{ 23 | */ 24 | 25 | /** @addtogroup stm32f10x_system 26 | * @{ 27 | */ 28 | 29 | /** 30 | * @brief Define to prevent recursive inclusion 31 | */ 32 | #ifndef __SYSTEM_STM32F10X_H 33 | #define __SYSTEM_STM32F10X_H 34 | 35 | #ifdef __cplusplus 36 | extern "C" { 37 | #endif 38 | 39 | /** @addtogroup STM32F10x_System_Includes 40 | * @{ 41 | */ 42 | 43 | /** 44 | * @} 45 | */ 46 | 47 | 48 | /** @addtogroup STM32F10x_System_Exported_types 49 | * @{ 50 | */ 51 | 52 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @addtogroup STM32F10x_System_Exported_Constants 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32F10x_System_Exported_Macros 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32F10x_System_Exported_Functions 75 | * @{ 76 | */ 77 | 78 | extern void SystemInit(void); 79 | extern void SystemCoreClockUpdate(void); 80 | /** 81 | * @} 82 | */ 83 | 84 | #ifdef __cplusplus 85 | } 86 | #endif 87 | 88 | #endif /*__SYSTEM_STM32F10X_H */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 98 | -------------------------------------------------------------------------------- /Src/after-compile.bat: -------------------------------------------------------------------------------- 1 | cd D:\STM32\stm32-speech-recognition 2 | "C:\Program Files (x86)\SEGGER\JLinkARM_V434\JFlashARM.exe" -openprj"download.jflash" -open"Object\stm32-speech-recognition.hex",0x0 -auto -exit 3 | 4 | cd D:\STM32\stm32-speech-recognition\Src 5 | git add -A 6 | git commit -m "Auto" -------------------------------------------------------------------------------- /Voice_Rec.BAT: -------------------------------------------------------------------------------- 1 | SET PATH=G:\Keil\ARM\BIN40;C:\Python27\;C:\ProgramData\Oracle\Java\javapath;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;G:\Program Files\MATLAB\R2010a\runtime\win64;G:\Program Files\MATLAB\R2010a\bin;G:\Program Files (x86)\Altium Designer Winter 09\System;G:\Develop\android\adt-bundle-windows-x86_64\sdk;G:\Develop\android\adt-bundle-windows-x86_64\sdk\tools;G:\Develop\android\adt-bundle-windows-x86_64\sdk\platform-tools;C:\Program Files\Java\jre7\bin;G:\Develop\android\android-ndk-r12b;C:\Program Files (x86)\QuickTime\QTSystem\;G:\Program Files (x86)\Git\cmd;G:\Program Files (x86)\Git\bin;G:\Develop\android\android-ndk-r12b\toolchains\arm-linux-androideabi-4.6\prebuilt\windows-x86_64\bin;C:\Program Files\OpenVPN\bin;G:\Develop\android\apk-hack\dex2jar-2.0;G:\Develop\android\apk-hack;G:\Program Files\TortoiseGit\bin;C:\Program Files\Git\cmd;C:\Program Files\Git\mingw64\bin;C:\Program Files\Git\usr\bin;C:\Program Files (x86)\AllWinnertech\PhoenixSuit\ 2 | SET ARMCC41INC=G:\Keil\ARM\RV31\Inc 3 | SET ARMCC41LIB=G:\Keil\ARM\RV31\Lib 4 | SET CPU_TYPE=STM32F103VE 5 | SET CPU_VENDOR=STMicroelectronics 6 | SET UV2_TARGET=Voice_Rec 7 | SET CPU_CLOCK=0x007A1200 8 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\main._ip" 9 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\main.__i" 10 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\vad._ip" 11 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\vad.__i" 12 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\mfcc._ip" 13 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\mfcc.__i" 14 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\dtw._ip" 15 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\dtw.__i" 16 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\gui._ip" 17 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\gui.__i" 18 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\bsp._ip" 19 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\bsp.__i" 20 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\adc._ip" 21 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\adc.__i" 22 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\delay._ip" 23 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\delay.__i" 24 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\flash._ip" 25 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\flash.__i" 26 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\spi._ip" 27 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\spi.__i" 28 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\tftlcd._ip" 29 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\tftlcd.__i" 30 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\TOUCH_~1._IP" 31 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\touch_panel.__i" 32 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\usart._ip" 33 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\usart.__i" 34 | "G:\Keil\ARM\BIN40\ArmAsm" --Via ".\object\cr4_fft_1024_stm32._ia" 35 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\spiflash._ip" 36 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\spiflash.__i" 37 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\core_cm3._ip" 38 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\core_cm3.__i" 39 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST6D38~1._IP" 40 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_it.__i" 41 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\SYSTEM~1._IP" 42 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\system_stm32f10x.__i" 43 | "G:\Keil\ARM\BIN40\ArmAsm" --Via ".\object\startup_stm32f10x_hd._ia" 44 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\misc._ip" 45 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\misc.__i" 46 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STM32F~1._IP" 47 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_adc.__i" 48 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STM32F~2._IP" 49 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_bkp.__i" 50 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STM32F~3._IP" 51 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_can.__i" 52 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STM32F~4._IP" 53 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_cec.__i" 54 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST5AB7~1._IP" 55 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_crc.__i" 56 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST2535~1._IP" 57 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_dac.__i" 58 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STD305~1._IP" 59 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_dbgmcu.__i" 60 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST5E1A~1._IP" 61 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_dma.__i" 62 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST052E~1._IP" 63 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_exti.__i" 64 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST15B0~1._IP" 65 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_flash.__i" 66 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST3F06~1._IP" 67 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_fsmc.__i" 68 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST580F~1._IP" 69 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_gpio.__i" 70 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST6432~1._IP" 71 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_i2c.__i" 72 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STD0BB~1._IP" 73 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_iwdg.__i" 74 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STF203~1._IP" 75 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_pwr.__i" 76 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STF567~1._IP" 77 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_rcc.__i" 78 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST6860~1._IP" 79 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_rtc.__i" 80 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST57E8~1._IP" 81 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_sdio.__i" 82 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STF1E4~1._IP" 83 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_spi.__i" 84 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST3C1B~1._IP" 85 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_tim.__i" 86 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\STD4E2~1._IP" 87 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_usart.__i" 88 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\List\ST2680~1._IP" 89 | "G:\Keil\ARM\BIN40\ArmCC" --Via ".\object\stm32f10x_wwdg.__i" 90 | "G:\Keil\ARM\BIN40\ArmLink" --Via ".\Object\stm32-speech-recognition.lnp" 91 | -------------------------------------------------------------------------------- /download.jflash: -------------------------------------------------------------------------------- 1 | AppVersion = 43400 2 | [GENERAL] 3 | ConnectMode = 0 4 | CurrentFile = "Object\stm32-speech-recognition.hex" 5 | DataFileSAddr = 0x00000000 6 | GUIMode = 0 7 | HostName = "" 8 | TargetIF = 0 9 | USBPort = 0 10 | USBSerialNo = 0x00000000 11 | [JTAG] 12 | IRLen = 0 13 | MultipleTargets = 0 14 | NumDevices = 0 15 | Speed0 = 5 16 | Speed1 = 4000 17 | TAP_Number = 0 18 | UseAdaptive0 = 0 19 | UseAdaptive1 = 0 20 | UseMaxSpeed0 = 1 21 | UseMaxSpeed1 = 1 22 | [CPU] 23 | CheckCoreID = 1 24 | ChipName = "ST STM32F103VE" 25 | ClockSpeed = 0x00000000 26 | Core = 0x030000FF 27 | CoreID = 0x3BA00477 28 | CoreIDMask = 0xFFFFFFFF 29 | DeviceFamily = 0x00000003 30 | EndianMode = 0 31 | HasInternalFlash = 1 32 | InitStep0_Action = "Reset" 33 | InitStep0_Comment = "Reset and halt target" 34 | InitStep0_Value0 = 0x00000000 35 | InitStep0_Value1 = 0x00000000 36 | NumInitSteps = 1 37 | RAMAddr = 0x20000000 38 | RAMSize = 0x00010000 39 | ScriptFile = "" 40 | UseAutoSpeed = 0x00000000 41 | UseRAM = 1 42 | UseScriptFile = 0 43 | [FLASH] 44 | aSectorSel[256] = 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 45 | AutoDetect = 0 46 | BankName = "" 47 | BankSelMode = 1 48 | BaseAddr = 0x08000000 49 | CheckId = 0 50 | CustomRAMCode = "" 51 | DeviceName = "STM32F10xxE internal" 52 | EndBank = 255 53 | NumBanks = 1 54 | OrgNumBits = 32 55 | OrgNumChips = 1 56 | StartBank = 0 57 | UseCustomRAMCode = 0 58 | [PRODUCTION] 59 | AutoPerformsErase = 1 60 | AutoPerformsHardLock = 0 61 | AutoPerformsHardUnlock = 0 62 | AutoPerformsProgram = 1 63 | AutoPerformsSecure = 0 64 | AutoPerformsSoftLock = 0 65 | AutoPerformsSoftUnlock = 1 66 | AutoPerformsStartApp = 1 67 | AutoPerformsUnsecure = 0 68 | AutoPerformsVerify = 1 69 | Delay = 0x000001F4 70 | EraseType = 2 71 | ProgramSN = 0 72 | SNAddr = 0x00000000 73 | SNInc = 0x00000001 74 | Threshold = 0x00000BB8 75 | VerifyType = 1 76 | -------------------------------------------------------------------------------- /基于STM32的孤立词语音识别.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/基于STM32的孤立词语音识别.pdf -------------------------------------------------------------------------------- /语音识别.plg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/语音识别.plg -------------------------------------------------------------------------------- /语音识别_Target 1.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/语音识别_Target 1.dep -------------------------------------------------------------------------------- /语音识别_Voice_Rec.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gk969/stm32-speech-recognition/f4f03a967577c02a825f8ae00675015a9e6753e0/语音识别_Voice_Rec.dep --------------------------------------------------------------------------------