├── .github ├── FUNDING.yml └── workflows │ ├── build_package_melpa_basic.yml │ ├── build_package_melpa_stable.yml │ ├── build_straight.yml │ ├── build_straight_release_snapshot.yml │ ├── build_straight_snapshot.yml │ ├── elisp_check.yml │ └── melpazoid.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── test ├── files │ ├── common │ │ ├── axi_demux.sv │ │ ├── axi_test.sv │ │ ├── instances.sv │ │ ├── tb_program.sv │ │ ├── ucontroller.sv │ │ └── uvm_component.svh │ ├── github │ │ ├── tree_sitter_systemverilog_49.sv │ │ ├── verilog_ext_29.sv │ │ └── verilog_ts_mode_3.sv │ ├── prettify │ │ ├── pretty-declarations.sv │ │ └── pretty-expr.sv │ ├── ucontroller │ │ ├── rtl │ │ │ ├── alu.sv │ │ │ ├── bin2bcd.sv │ │ │ ├── cpu.sv │ │ │ ├── dma.sv │ │ │ ├── dma_arbiter.sv │ │ │ ├── dma_rx.sv │ │ │ ├── dma_tx.sv │ │ │ ├── fifo_wrapper.sv │ │ │ ├── global_pkg.sv │ │ │ ├── gp_ram.sv │ │ │ ├── ram.sv │ │ │ ├── ram_arbiter.sv │ │ │ ├── regs_ram.sv │ │ │ ├── sreg.sv │ │ │ ├── uart.sv │ │ │ ├── uart_rx.sv │ │ │ ├── uart_tx.sv │ │ │ └── ucontroller.sv │ │ └── tb │ │ │ ├── fifo_generator_0_sim_netlist.v │ │ │ ├── tb_alu.sv │ │ │ ├── tb_bin2bcd.sv │ │ │ ├── tb_clocks.sv │ │ │ ├── tb_cpu.sv │ │ │ ├── tb_dma.sv │ │ │ ├── tb_program.sv │ │ │ ├── tb_ram.sv │ │ │ ├── tb_top.sv │ │ │ └── tb_uart.sv │ └── veripool │ │ ├── indent_1.v │ │ ├── indent_2.v │ │ ├── indent_3.v │ │ ├── indent_4.v │ │ ├── indent_always_decl.v │ │ ├── indent_analog.v │ │ ├── indent_assert.v │ │ ├── indent_assert_else.v │ │ ├── indent_assert_property.v │ │ ├── indent_assignment.v │ │ ├── indent_attributes.v │ │ ├── indent_begin_clapp.v │ │ ├── indent_bracket.v │ │ ├── indent_case.v │ │ ├── indent_class.v │ │ ├── indent_class_pkg_nil.sv │ │ ├── indent_clocking.v │ │ ├── indent_clockingblock.v │ │ ├── indent_comments.v │ │ ├── indent_comments_bug1717.v │ │ ├── indent_connectmodule.v │ │ ├── indent_constraint.v │ │ ├── indent_constraint2.v │ │ ├── indent_constraint3.v │ │ ├── indent_covergroup.v │ │ ├── indent_covergroup_swan.v │ │ ├── indent_coverpoint.v │ │ ├── indent_decl-1.v │ │ ├── indent_decl.v │ │ ├── indent_decl_1760.sv │ │ ├── indent_directives.v │ │ ├── indent_double_curly.v │ │ ├── indent_dpi.v │ │ ├── indent_enum.v │ │ ├── indent_foreach.v │ │ ├── indent_fork_join_any.v │ │ ├── indent_formfeed.v │ │ ├── indent_function.v │ │ ├── indent_generate.v │ │ ├── indent_generate_bug1257.v │ │ ├── indent_generate_bug1404.sv │ │ ├── indent_generate_case.v │ │ ├── indent_generate_for.v │ │ ├── indent_generate_if.v │ │ ├── indent_genmod.v │ │ ├── indent_if.v │ │ ├── indent_if2.v │ │ ├── indent_ifdef.v │ │ ├── indent_ifdef_generate.v │ │ ├── indent_immediate_assertion.sv │ │ ├── indent_importfunction.v │ │ ├── indent_interface.v │ │ ├── indent_interface_class_bug1047.sv │ │ ├── indent_linefeed.v │ │ ├── indent_lineup_inlists.v │ │ ├── indent_lineup_mode_all.v │ │ ├── indent_lineup_mode_assignments.v │ │ ├── indent_lineup_mode_declarations.v │ │ ├── indent_lineup_mode_none.v │ │ ├── indent_list_nil_align_ports_custom_type.sv │ │ ├── indent_list_nil_continued_line.sv │ │ ├── indent_list_nil_generate_for.v │ │ ├── indent_list_nil_generate_for2.v │ │ ├── indent_list_nil_generate_if.v │ │ ├── indent_list_nil_generate_if2.v │ │ ├── indent_list_nil_if.sv │ │ ├── indent_list_nil_methods.sv │ │ ├── indent_list_nil_param_port_list.sv │ │ ├── indent_list_nil_params.v │ │ ├── indent_list_nil_params2.v │ │ ├── indent_list_nil_pkg_class.sv │ │ ├── indent_list_nil_report.sv │ │ ├── indent_list_nil_typedef_enum.sv │ │ ├── indent_macro_braces.v │ │ ├── indent_macro_comment.v │ │ ├── indent_macro_ignore_multiline.sv │ │ ├── indent_macro_ignore_regexp.sv │ │ ├── indent_mailbox.v │ │ ├── indent_modansi.v │ │ ├── indent_modeln.v │ │ ├── indent_modport.v │ │ ├── indent_named_assert.v │ │ ├── indent_ovm.v │ │ ├── indent_param.v │ │ ├── indent_param_1645.v │ │ ├── indent_preproc.v │ │ ├── indent_preproc_label.v │ │ ├── indent_property.v │ │ ├── indent_property_bug1817.v │ │ ├── indent_randcase.v │ │ ├── indent_random.v │ │ ├── indent_reftype.v │ │ ├── indent_rep_msg1188.v │ │ ├── indent_replicate.v │ │ ├── indent_replicate_bug955.sv │ │ ├── indent_sexp.sv │ │ ├── indent_streaming_op.v │ │ ├── indent_struct.v │ │ ├── indent_sv_interface_mp_bug636.sv │ │ ├── indent_task.v │ │ ├── indent_task_func_decl.sv │ │ ├── indent_typedef.sv │ │ ├── indent_typedef_enum.sv │ │ ├── indent_unique_case-1.v │ │ ├── indent_unique_case-2.v │ │ ├── indent_unique_case.v │ │ ├── indent_uvm.v │ │ ├── indent_virtual_class.sv │ │ └── indent_warren.v ├── ref │ ├── beautify │ │ ├── axi_demux.beauty.extra.sv │ │ ├── axi_demux.beauty.sv │ │ ├── axi_demux.no_comm_align.pretty.sv │ │ ├── axi_demux.pretty.sv │ │ ├── axi_test.beauty.extra.sv │ │ ├── axi_test.beauty.sv │ │ ├── axi_test.no_comm_align.pretty.sv │ │ ├── axi_test.pretty.sv │ │ ├── indent_1.no_comm_align.pretty.sv │ │ ├── indent_1.pretty.sv │ │ ├── indent_2.no_comm_align.pretty.sv │ │ ├── indent_2.pretty.sv │ │ ├── indent_3.no_comm_align.pretty.sv │ │ ├── indent_3.pretty.sv │ │ ├── indent_4.no_comm_align.pretty.sv │ │ ├── indent_4.pretty.sv │ │ ├── indent_always_decl.no_comm_align.pretty.sv │ │ ├── indent_always_decl.pretty.sv │ │ ├── indent_analog.no_comm_align.pretty.sv │ │ ├── indent_analog.pretty.sv │ │ ├── indent_assert.no_comm_align.pretty.sv │ │ ├── indent_assert.pretty.sv │ │ ├── indent_assert_else.no_comm_align.pretty.sv │ │ ├── indent_assert_else.pretty.sv │ │ ├── indent_assert_property.no_comm_align.pretty.sv │ │ ├── indent_assert_property.pretty.sv │ │ ├── indent_assignment.no_comm_align.pretty.sv │ │ ├── indent_assignment.pretty.sv │ │ ├── indent_attributes.no_comm_align.pretty.sv │ │ ├── indent_attributes.pretty.sv │ │ ├── indent_begin_clapp.no_comm_align.pretty.sv │ │ ├── indent_begin_clapp.pretty.sv │ │ ├── indent_bracket.no_comm_align.pretty.sv │ │ ├── indent_bracket.pretty.sv │ │ ├── indent_case.no_comm_align.pretty.sv │ │ ├── indent_case.pretty.sv │ │ ├── indent_class.no_comm_align.pretty.sv │ │ ├── indent_class.pretty.sv │ │ ├── indent_class_pkg_nil.no_comm_align.pretty.sv │ │ ├── indent_class_pkg_nil.pretty.sv │ │ ├── indent_clocking.no_comm_align.pretty.sv │ │ ├── indent_clocking.pretty.sv │ │ ├── indent_clockingblock.no_comm_align.pretty.sv │ │ ├── indent_clockingblock.pretty.sv │ │ ├── indent_comments.no_comm_align.pretty.sv │ │ ├── indent_comments.pretty.sv │ │ ├── indent_comments_bug1717.no_comm_align.pretty.sv │ │ ├── indent_comments_bug1717.pretty.sv │ │ ├── indent_connectmodule.no_comm_align.pretty.sv │ │ ├── indent_connectmodule.pretty.sv │ │ ├── indent_constraint.no_comm_align.pretty.sv │ │ ├── indent_constraint.pretty.sv │ │ ├── indent_constraint2.no_comm_align.pretty.sv │ │ ├── indent_constraint2.pretty.sv │ │ ├── indent_constraint3.no_comm_align.pretty.sv │ │ ├── indent_constraint3.pretty.sv │ │ ├── indent_covergroup.no_comm_align.pretty.sv │ │ ├── indent_covergroup.pretty.sv │ │ ├── indent_covergroup_swan.no_comm_align.pretty.sv │ │ ├── indent_covergroup_swan.pretty.sv │ │ ├── indent_coverpoint.no_comm_align.pretty.sv │ │ ├── indent_coverpoint.pretty.sv │ │ ├── indent_decl-1.no_comm_align.pretty.sv │ │ ├── indent_decl-1.pretty.sv │ │ ├── indent_decl.no_comm_align.pretty.sv │ │ ├── indent_decl.pretty.sv │ │ ├── indent_decl_1760.no_comm_align.pretty.sv │ │ ├── indent_decl_1760.pretty.sv │ │ ├── indent_directives.no_comm_align.pretty.sv │ │ ├── indent_directives.pretty.sv │ │ ├── indent_double_curly.no_comm_align.pretty.sv │ │ ├── indent_double_curly.pretty.sv │ │ ├── indent_dpi.no_comm_align.pretty.sv │ │ ├── indent_dpi.pretty.sv │ │ ├── indent_enum.no_comm_align.pretty.sv │ │ ├── indent_enum.pretty.sv │ │ ├── indent_foreach.no_comm_align.pretty.sv │ │ ├── indent_foreach.pretty.sv │ │ ├── indent_fork_join_any.no_comm_align.pretty.sv │ │ ├── indent_fork_join_any.pretty.sv │ │ ├── indent_formfeed.no_comm_align.pretty.sv │ │ ├── indent_formfeed.pretty.sv │ │ ├── indent_function.no_comm_align.pretty.sv │ │ ├── indent_function.pretty.sv │ │ ├── indent_generate.no_comm_align.pretty.sv │ │ ├── indent_generate.pretty.sv │ │ ├── indent_generate_bug1257.no_comm_align.pretty.sv │ │ ├── indent_generate_bug1257.pretty.sv │ │ ├── indent_generate_bug1404.no_comm_align.pretty.sv │ │ ├── indent_generate_bug1404.pretty.sv │ │ ├── indent_generate_case.no_comm_align.pretty.sv │ │ ├── indent_generate_case.pretty.sv │ │ ├── indent_generate_for.no_comm_align.pretty.sv │ │ ├── indent_generate_for.pretty.sv │ │ ├── indent_generate_if.no_comm_align.pretty.sv │ │ ├── indent_generate_if.pretty.sv │ │ ├── indent_genmod.no_comm_align.pretty.sv │ │ ├── indent_genmod.pretty.sv │ │ ├── indent_if.no_comm_align.pretty.sv │ │ ├── indent_if.pretty.sv │ │ ├── indent_if2.no_comm_align.pretty.sv │ │ ├── indent_if2.pretty.sv │ │ ├── indent_ifdef.no_comm_align.pretty.sv │ │ ├── indent_ifdef.pretty.sv │ │ ├── indent_ifdef_generate.no_comm_align.pretty.sv │ │ ├── indent_ifdef_generate.pretty.sv │ │ ├── indent_immediate_assertion.no_comm_align.pretty.sv │ │ ├── indent_immediate_assertion.pretty.sv │ │ ├── indent_importfunction.no_comm_align.pretty.sv │ │ ├── indent_importfunction.pretty.sv │ │ ├── indent_interface.no_comm_align.pretty.sv │ │ ├── indent_interface.pretty.sv │ │ ├── indent_interface_class_bug1047.no_comm_align.pretty.sv │ │ ├── indent_interface_class_bug1047.pretty.sv │ │ ├── indent_linefeed.no_comm_align.pretty.sv │ │ ├── indent_linefeed.pretty.sv │ │ ├── indent_lineup_inlists.no_comm_align.pretty.sv │ │ ├── indent_lineup_inlists.pretty.sv │ │ ├── indent_lineup_mode_all.no_comm_align.pretty.sv │ │ ├── indent_lineup_mode_all.pretty.sv │ │ ├── indent_lineup_mode_assignments.no_comm_align.pretty.sv │ │ ├── indent_lineup_mode_assignments.pretty.sv │ │ ├── indent_lineup_mode_declarations.no_comm_align.pretty.sv │ │ ├── indent_lineup_mode_declarations.pretty.sv │ │ ├── indent_lineup_mode_none.no_comm_align.pretty.sv │ │ ├── indent_lineup_mode_none.pretty.sv │ │ ├── indent_list_nil_align_ports_custom_type.no_comm_align.pretty.sv │ │ ├── indent_list_nil_align_ports_custom_type.pretty.sv │ │ ├── indent_list_nil_continued_line.no_comm_align.pretty.sv │ │ ├── indent_list_nil_continued_line.pretty.sv │ │ ├── indent_list_nil_generate_for.no_comm_align.pretty.sv │ │ ├── indent_list_nil_generate_for.pretty.sv │ │ ├── indent_list_nil_generate_for2.no_comm_align.pretty.sv │ │ ├── indent_list_nil_generate_for2.pretty.sv │ │ ├── indent_list_nil_generate_if.no_comm_align.pretty.sv │ │ ├── indent_list_nil_generate_if.pretty.sv │ │ ├── indent_list_nil_generate_if2.no_comm_align.pretty.sv │ │ ├── indent_list_nil_generate_if2.pretty.sv │ │ ├── indent_list_nil_if.no_comm_align.pretty.sv │ │ ├── indent_list_nil_if.pretty.sv │ │ ├── indent_list_nil_methods.no_comm_align.pretty.sv │ │ ├── indent_list_nil_methods.pretty.sv │ │ ├── indent_list_nil_param_port_list.no_comm_align.pretty.sv │ │ ├── indent_list_nil_param_port_list.pretty.sv │ │ ├── indent_list_nil_params.no_comm_align.pretty.sv │ │ ├── indent_list_nil_params.pretty.sv │ │ ├── indent_list_nil_params2.no_comm_align.pretty.sv │ │ ├── indent_list_nil_params2.pretty.sv │ │ ├── indent_list_nil_pkg_class.no_comm_align.pretty.sv │ │ ├── indent_list_nil_pkg_class.pretty.sv │ │ ├── indent_list_nil_report.no_comm_align.pretty.sv │ │ ├── indent_list_nil_report.pretty.sv │ │ ├── indent_list_nil_typedef_enum.no_comm_align.pretty.sv │ │ ├── indent_list_nil_typedef_enum.pretty.sv │ │ ├── indent_macro_braces.no_comm_align.pretty.sv │ │ ├── indent_macro_braces.pretty.sv │ │ ├── indent_macro_comment.no_comm_align.pretty.sv │ │ ├── indent_macro_comment.pretty.sv │ │ ├── indent_macro_ignore_multiline.no_comm_align.pretty.sv │ │ ├── indent_macro_ignore_multiline.pretty.sv │ │ ├── indent_macro_ignore_regexp.no_comm_align.pretty.sv │ │ ├── indent_macro_ignore_regexp.pretty.sv │ │ ├── indent_mailbox.no_comm_align.pretty.sv │ │ ├── indent_mailbox.pretty.sv │ │ ├── indent_modansi.no_comm_align.pretty.sv │ │ ├── indent_modansi.pretty.sv │ │ ├── indent_modeln.no_comm_align.pretty.sv │ │ ├── indent_modeln.pretty.sv │ │ ├── indent_modport.no_comm_align.pretty.sv │ │ ├── indent_modport.pretty.sv │ │ ├── indent_named_assert.no_comm_align.pretty.sv │ │ ├── indent_named_assert.pretty.sv │ │ ├── indent_ovm.no_comm_align.pretty.sv │ │ ├── indent_ovm.pretty.sv │ │ ├── indent_param.no_comm_align.pretty.sv │ │ ├── indent_param.pretty.sv │ │ ├── indent_param_1645.no_comm_align.pretty.sv │ │ ├── indent_param_1645.pretty.sv │ │ ├── indent_preproc.no_comm_align.pretty.sv │ │ ├── indent_preproc.pretty.sv │ │ ├── indent_preproc_label.no_comm_align.pretty.sv │ │ ├── indent_preproc_label.pretty.sv │ │ ├── indent_property.no_comm_align.pretty.sv │ │ ├── indent_property.pretty.sv │ │ ├── indent_property_bug1817.no_comm_align.pretty.sv │ │ ├── indent_property_bug1817.pretty.sv │ │ ├── indent_randcase.no_comm_align.pretty.sv │ │ ├── indent_randcase.pretty.sv │ │ ├── indent_random.no_comm_align.pretty.sv │ │ ├── indent_random.pretty.sv │ │ ├── indent_reftype.no_comm_align.pretty.sv │ │ ├── indent_reftype.pretty.sv │ │ ├── indent_rep_msg1188.no_comm_align.pretty.sv │ │ ├── indent_rep_msg1188.pretty.sv │ │ ├── indent_replicate.no_comm_align.pretty.sv │ │ ├── indent_replicate.pretty.sv │ │ ├── indent_replicate_bug955.no_comm_align.pretty.sv │ │ ├── indent_replicate_bug955.pretty.sv │ │ ├── indent_sexp.no_comm_align.pretty.sv │ │ ├── indent_sexp.pretty.sv │ │ ├── indent_streaming_op.no_comm_align.pretty.sv │ │ ├── indent_streaming_op.pretty.sv │ │ ├── indent_struct.no_comm_align.pretty.sv │ │ ├── indent_struct.pretty.sv │ │ ├── indent_sv_interface_mp_bug636.no_comm_align.pretty.sv │ │ ├── indent_sv_interface_mp_bug636.pretty.sv │ │ ├── indent_task.no_comm_align.pretty.sv │ │ ├── indent_task.pretty.sv │ │ ├── indent_task_func_decl.no_comm_align.pretty.sv │ │ ├── indent_task_func_decl.pretty.sv │ │ ├── indent_typedef.no_comm_align.pretty.sv │ │ ├── indent_typedef.pretty.sv │ │ ├── indent_typedef_enum.no_comm_align.pretty.sv │ │ ├── indent_typedef_enum.pretty.sv │ │ ├── indent_unique_case-1.no_comm_align.pretty.sv │ │ ├── indent_unique_case-1.pretty.sv │ │ ├── indent_unique_case-2.no_comm_align.pretty.sv │ │ ├── indent_unique_case-2.pretty.sv │ │ ├── indent_unique_case.no_comm_align.pretty.sv │ │ ├── indent_unique_case.pretty.sv │ │ ├── indent_uvm.no_comm_align.pretty.sv │ │ ├── indent_uvm.pretty.sv │ │ ├── indent_virtual_class.no_comm_align.pretty.sv │ │ ├── indent_virtual_class.pretty.sv │ │ ├── indent_warren.no_comm_align.pretty.sv │ │ ├── indent_warren.pretty.sv │ │ ├── instances.beauty.extra.sv │ │ ├── instances.beauty.sv │ │ ├── instances.no_comm_align.pretty.sv │ │ ├── instances.pretty.sv │ │ ├── misc.beauty.extra.sv │ │ ├── misc.beauty.sv │ │ ├── misc.no_comm_align.pretty.sv │ │ ├── misc.pretty.sv │ │ ├── pretty-declarations.no_comm_align.pretty.sv │ │ ├── pretty-declarations.pretty.sv │ │ ├── pretty-expr.no_comm_align.pretty.sv │ │ ├── pretty-expr.pretty.sv │ │ ├── tb_program.beauty.extra.sv │ │ ├── tb_program.beauty.sv │ │ ├── tb_program.no_comm_align.pretty.sv │ │ ├── tb_program.pretty.sv │ │ ├── tree_sitter_systemverilog_49.beauty.extra.sv │ │ ├── tree_sitter_systemverilog_49.beauty.sv │ │ ├── tree_sitter_systemverilog_49.no_comm_align.pretty.sv │ │ ├── tree_sitter_systemverilog_49.pretty.sv │ │ ├── ucontroller.beauty.extra.sv │ │ ├── ucontroller.beauty.sv │ │ ├── ucontroller.no_comm_align.pretty.sv │ │ ├── ucontroller.pretty.sv │ │ ├── uvm_component.beauty.extra.sv │ │ ├── uvm_component.beauty.sv │ │ ├── uvm_component.no_comm_align.pretty.sv │ │ ├── uvm_component.pretty.sv │ │ ├── verilog_ext_29.beauty.extra.sv │ │ ├── verilog_ext_29.beauty.sv │ │ ├── verilog_ext_29.no_comm_align.pretty.sv │ │ ├── verilog_ext_29.pretty.sv │ │ ├── verilog_ts_mode_3.beauty.extra.sv │ │ ├── verilog_ts_mode_3.beauty.sv │ │ ├── verilog_ts_mode_3.no_comm_align.pretty.sv │ │ └── verilog_ts_mode_3.pretty.sv │ ├── faceup │ │ ├── axi_demux.faceup │ │ ├── axi_test.faceup │ │ ├── instances.faceup │ │ ├── misc.faceup │ │ ├── tb_program.faceup │ │ ├── tree_sitter_systemverilog_49.faceup │ │ ├── ucontroller.faceup │ │ ├── uvm_component.faceup │ │ ├── verilog_ext_29.faceup │ │ └── verilog_ts_mode_3.faceup │ ├── imenu │ │ ├── axi_demux.simple.el │ │ ├── axi_demux.tree.el │ │ ├── axi_demux.tree.group.el │ │ ├── axi_test.simple.el │ │ ├── axi_test.tree.el │ │ ├── axi_test.tree.group.el │ │ ├── instances.simple.el │ │ ├── instances.tree.el │ │ ├── instances.tree.group.el │ │ ├── misc.simple.el │ │ ├── misc.tree.el │ │ ├── misc.tree.group.el │ │ ├── tb_program.simple.el │ │ ├── tb_program.tree.el │ │ ├── tb_program.tree.group.el │ │ ├── tree_sitter_systemverilog_49.simple.el │ │ ├── tree_sitter_systemverilog_49.tree.el │ │ ├── tree_sitter_systemverilog_49.tree.group.el │ │ ├── ucontroller.simple.el │ │ ├── ucontroller.tree.el │ │ ├── ucontroller.tree.group.el │ │ ├── uvm_component.simple.el │ │ ├── uvm_component.tree.el │ │ ├── uvm_component.tree.group.el │ │ ├── verilog_ext_29.simple.el │ │ ├── verilog_ext_29.tree.el │ │ ├── verilog_ext_29.tree.group.el │ │ ├── verilog_ts_mode_3.simple.el │ │ ├── verilog_ts_mode_3.tree.el │ │ └── verilog_ts_mode_3.tree.group.el │ ├── indent │ │ ├── axi_demux.sv │ │ ├── axi_test.sv │ │ ├── indent_1.v │ │ ├── indent_2.v │ │ ├── indent_3.v │ │ ├── indent_4.v │ │ ├── indent_always_decl.v │ │ ├── indent_analog.v │ │ ├── indent_assert.v │ │ ├── indent_assert_else.v │ │ ├── indent_assert_property.v │ │ ├── indent_assignment.v │ │ ├── indent_attributes.v │ │ ├── indent_begin_clapp.v │ │ ├── indent_bracket.v │ │ ├── indent_case.v │ │ ├── indent_class.v │ │ ├── indent_class_pkg_nil.sv │ │ ├── indent_clocking.v │ │ ├── indent_clockingblock.v │ │ ├── indent_comments.v │ │ ├── indent_comments_bug1717.v │ │ ├── indent_connectmodule.v │ │ ├── indent_constraint.v │ │ ├── indent_constraint2.v │ │ ├── indent_constraint3.v │ │ ├── indent_covergroup.v │ │ ├── indent_covergroup_swan.v │ │ ├── indent_coverpoint.v │ │ ├── indent_decl-1.v │ │ ├── indent_decl.v │ │ ├── indent_decl_1760.sv │ │ ├── indent_directives.v │ │ ├── indent_double_curly.v │ │ ├── indent_dpi.v │ │ ├── indent_enum.v │ │ ├── indent_foreach.v │ │ ├── indent_fork_join_any.v │ │ ├── indent_formfeed.v │ │ ├── indent_function.v │ │ ├── indent_generate.v │ │ ├── indent_generate_bug1257.v │ │ ├── indent_generate_bug1404.sv │ │ ├── indent_generate_case.v │ │ ├── indent_generate_for.v │ │ ├── indent_generate_if.v │ │ ├── indent_genmod.v │ │ ├── indent_if.v │ │ ├── indent_if2.v │ │ ├── indent_ifdef.v │ │ ├── indent_ifdef_generate.v │ │ ├── indent_immediate_assertion.sv │ │ ├── indent_importfunction.v │ │ ├── indent_interface.v │ │ ├── indent_interface_class_bug1047.sv │ │ ├── indent_linefeed.v │ │ ├── indent_lineup_inlists.v │ │ ├── indent_lineup_mode_all.v │ │ ├── indent_lineup_mode_assignments.v │ │ ├── indent_lineup_mode_declarations.v │ │ ├── indent_lineup_mode_none.v │ │ ├── indent_list_nil_align_ports_custom_type.sv │ │ ├── indent_list_nil_continued_line.sv │ │ ├── indent_list_nil_generate_for.v │ │ ├── indent_list_nil_generate_for2.v │ │ ├── indent_list_nil_generate_if.v │ │ ├── indent_list_nil_generate_if2.v │ │ ├── indent_list_nil_if.sv │ │ ├── indent_list_nil_methods.sv │ │ ├── indent_list_nil_param_port_list.sv │ │ ├── indent_list_nil_params.v │ │ ├── indent_list_nil_params2.v │ │ ├── indent_list_nil_pkg_class.sv │ │ ├── indent_list_nil_report.sv │ │ ├── indent_list_nil_typedef_enum.sv │ │ ├── indent_macro_braces.v │ │ ├── indent_macro_comment.v │ │ ├── indent_macro_ignore_multiline.sv │ │ ├── indent_macro_ignore_regexp.sv │ │ ├── indent_mailbox.v │ │ ├── indent_modansi.v │ │ ├── indent_modeln.v │ │ ├── indent_modport.v │ │ ├── indent_named_assert.v │ │ ├── indent_ovm.v │ │ ├── indent_param.v │ │ ├── indent_param_1645.v │ │ ├── indent_preproc.v │ │ ├── indent_preproc_label.v │ │ ├── indent_property.v │ │ ├── indent_property_bug1817.v │ │ ├── indent_randcase.v │ │ ├── indent_random.v │ │ ├── indent_reftype.v │ │ ├── indent_rep_msg1188.v │ │ ├── indent_replicate.v │ │ ├── indent_replicate_bug955.sv │ │ ├── indent_sexp.sv │ │ ├── indent_streaming_op.v │ │ ├── indent_struct.v │ │ ├── indent_sv_interface_mp_bug636.sv │ │ ├── indent_task.v │ │ ├── indent_task_func_decl.sv │ │ ├── indent_typedef.sv │ │ ├── indent_typedef_enum.sv │ │ ├── indent_unique_case-1.v │ │ ├── indent_unique_case-2.v │ │ ├── indent_unique_case.v │ │ ├── indent_uvm.v │ │ ├── indent_virtual_class.sv │ │ ├── indent_warren.v │ │ ├── instances.sv │ │ ├── misc.sv │ │ ├── tb_program.sv │ │ ├── tree_sitter_systemverilog_49.sv │ │ ├── ucontroller.sv │ │ ├── uvm_component.svh │ │ ├── verilog_ext_29.sv │ │ └── verilog_ts_mode_3.sv │ ├── navigation │ │ ├── axi_demux.block.bwd.el │ │ ├── axi_demux.block.fwd.el │ │ ├── axi_demux.inst.bwd.el │ │ ├── axi_demux.inst.fwd.el │ │ ├── axi_test.block.bwd.el │ │ ├── axi_test.block.fwd.el │ │ ├── axi_test.bwd.sexp.el │ │ ├── axi_test.class.bwd.el │ │ ├── axi_test.class.fwd.el │ │ ├── axi_test.defun.down.el │ │ ├── axi_test.defun.up.el │ │ ├── axi_test.fwd.sexp.el │ │ ├── axi_test.tf.bwd.el │ │ ├── axi_test.tf.fwd.el │ │ ├── instances.block.bwd.el │ │ ├── instances.block.fwd.el │ │ ├── instances.inst.bwd.el │ │ ├── instances.inst.fwd.el │ │ ├── misc.block.bwd.el │ │ ├── misc.block.fwd.el │ │ ├── tb_program.block.bwd.el │ │ ├── tb_program.block.fwd.el │ │ ├── tb_program.class.bwd.el │ │ ├── tb_program.class.fwd.el │ │ ├── tb_program.defun.down.el │ │ ├── tb_program.defun.up.el │ │ ├── tb_program.tf.bwd.el │ │ ├── tb_program.tf.fwd.el │ │ ├── tree_sitter_systemverilog_49.block.bwd.el │ │ ├── tree_sitter_systemverilog_49.block.fwd.el │ │ ├── ucontroller.block.bwd.el │ │ ├── ucontroller.block.fwd.el │ │ ├── ucontroller.inst.bwd.el │ │ ├── ucontroller.inst.fwd.el │ │ ├── uvm_component.block.bwd.el │ │ ├── uvm_component.block.fwd.el │ │ ├── uvm_component.bwd.sexp.el │ │ ├── uvm_component.class.bwd.el │ │ ├── uvm_component.class.fwd.el │ │ ├── uvm_component.defun.down.el │ │ ├── uvm_component.defun.up.el │ │ ├── uvm_component.fwd.sexp.el │ │ ├── uvm_component.tf.bwd.el │ │ ├── uvm_component.tf.fwd.el │ │ ├── verilog_ext_29.block.bwd.el │ │ ├── verilog_ext_29.block.fwd.el │ │ ├── verilog_ts_mode_3.block.bwd.el │ │ └── verilog_ts_mode_3.block.fwd.el │ └── utils │ │ ├── alu.identifier.el │ │ ├── axi_demux.identifier.el │ │ ├── axi_demux.mod.point.el │ │ ├── axi_test.block.at.point.el │ │ ├── axi_test.identifier.el │ │ ├── axi_test.mod.point.el │ │ ├── bin2bcd.identifier.el │ │ ├── cpu.identifier.el │ │ ├── dma.identifier.el │ │ ├── dma_arbiter.identifier.el │ │ ├── dma_rx.identifier.el │ │ ├── dma_tx.identifier.el │ │ ├── fifo_generator_0_sim_netlist.identifier.el │ │ ├── fifo_wrapper.identifier.el │ │ ├── global_pkg.identifier.el │ │ ├── gp_ram.identifier.el │ │ ├── indent_1.identifier.el │ │ ├── indent_2.identifier.el │ │ ├── indent_3.identifier.el │ │ ├── indent_4.identifier.el │ │ ├── indent_always_decl.identifier.el │ │ ├── indent_analog.identifier.el │ │ ├── indent_assert.identifier.el │ │ ├── indent_assert_else.identifier.el │ │ ├── indent_assert_property.identifier.el │ │ ├── indent_assignment.identifier.el │ │ ├── indent_attributes.identifier.el │ │ ├── indent_begin_clapp.identifier.el │ │ ├── indent_bracket.identifier.el │ │ ├── indent_case.identifier.el │ │ ├── indent_class.identifier.el │ │ ├── indent_class_pkg_nil.identifier.el │ │ ├── indent_clocking.identifier.el │ │ ├── indent_clockingblock.identifier.el │ │ ├── indent_comments.identifier.el │ │ ├── indent_comments_bug1717.identifier.el │ │ ├── indent_connectmodule.identifier.el │ │ ├── indent_constraint.identifier.el │ │ ├── indent_constraint2.identifier.el │ │ ├── indent_constraint3.identifier.el │ │ ├── indent_covergroup.identifier.el │ │ ├── indent_covergroup_swan.identifier.el │ │ ├── indent_coverpoint.identifier.el │ │ ├── indent_decl-1.identifier.el │ │ ├── indent_decl.identifier.el │ │ ├── indent_decl_1760.identifier.el │ │ ├── indent_directives.identifier.el │ │ ├── indent_double_curly.identifier.el │ │ ├── indent_dpi.identifier.el │ │ ├── indent_enum.identifier.el │ │ ├── indent_foreach.identifier.el │ │ ├── indent_fork_join_any.identifier.el │ │ ├── indent_formfeed.identifier.el │ │ ├── indent_function.identifier.el │ │ ├── indent_generate.identifier.el │ │ ├── indent_generate_bug1257.identifier.el │ │ ├── indent_generate_bug1404.identifier.el │ │ ├── indent_generate_case.identifier.el │ │ ├── indent_generate_for.identifier.el │ │ ├── indent_generate_if.identifier.el │ │ ├── indent_genmod.identifier.el │ │ ├── indent_if.identifier.el │ │ ├── indent_if2.identifier.el │ │ ├── indent_ifdef.identifier.el │ │ ├── indent_ifdef_generate.identifier.el │ │ ├── indent_immediate_assertion.identifier.el │ │ ├── indent_importfunction.identifier.el │ │ ├── indent_interface.identifier.el │ │ ├── indent_interface_class_bug1047.identifier.el │ │ ├── indent_linefeed.identifier.el │ │ ├── indent_lineup_inlists.identifier.el │ │ ├── indent_lineup_mode_all.identifier.el │ │ ├── indent_lineup_mode_assignments.identifier.el │ │ ├── indent_lineup_mode_declarations.identifier.el │ │ ├── indent_lineup_mode_none.identifier.el │ │ ├── indent_list_nil_align_ports_custom_type.identifier.el │ │ ├── indent_list_nil_continued_line.identifier.el │ │ ├── indent_list_nil_generate_for.identifier.el │ │ ├── indent_list_nil_generate_for2.identifier.el │ │ ├── indent_list_nil_generate_if.identifier.el │ │ ├── indent_list_nil_generate_if2.identifier.el │ │ ├── indent_list_nil_if.identifier.el │ │ ├── indent_list_nil_methods.identifier.el │ │ ├── indent_list_nil_param_port_list.identifier.el │ │ ├── indent_list_nil_params.identifier.el │ │ ├── indent_list_nil_params2.identifier.el │ │ ├── indent_list_nil_pkg_class.identifier.el │ │ ├── indent_list_nil_report.identifier.el │ │ ├── indent_list_nil_typedef_enum.identifier.el │ │ ├── indent_macro_braces.identifier.el │ │ ├── indent_macro_comment.identifier.el │ │ ├── indent_macro_ignore_multiline.identifier.el │ │ ├── indent_macro_ignore_regexp.identifier.el │ │ ├── indent_mailbox.identifier.el │ │ ├── indent_modansi.identifier.el │ │ ├── indent_modeln.identifier.el │ │ ├── indent_modport.identifier.el │ │ ├── indent_named_assert.identifier.el │ │ ├── indent_ovm.identifier.el │ │ ├── indent_param.identifier.el │ │ ├── indent_param_1645.identifier.el │ │ ├── indent_preproc.identifier.el │ │ ├── indent_preproc_label.identifier.el │ │ ├── indent_property.identifier.el │ │ ├── indent_property_bug1817.identifier.el │ │ ├── indent_randcase.identifier.el │ │ ├── indent_random.identifier.el │ │ ├── indent_reftype.identifier.el │ │ ├── indent_rep_msg1188.identifier.el │ │ ├── indent_replicate.identifier.el │ │ ├── indent_replicate_bug955.identifier.el │ │ ├── indent_sexp.identifier.el │ │ ├── indent_streaming_op.identifier.el │ │ ├── indent_struct.identifier.el │ │ ├── indent_sv_interface_mp_bug636.identifier.el │ │ ├── indent_task.identifier.el │ │ ├── indent_task_func_decl.identifier.el │ │ ├── indent_typedef.identifier.el │ │ ├── indent_typedef_enum.identifier.el │ │ ├── indent_unique_case-1.identifier.el │ │ ├── indent_unique_case-2.identifier.el │ │ ├── indent_unique_case.identifier.el │ │ ├── indent_uvm.identifier.el │ │ ├── indent_virtual_class.identifier.el │ │ ├── indent_warren.identifier.el │ │ ├── instances.block.at.point.el │ │ ├── instances.identifier.el │ │ ├── instances.inst.point.el │ │ ├── instances.mod.point.el │ │ ├── misc.identifier.el │ │ ├── ram.identifier.el │ │ ├── ram_arbiter.identifier.el │ │ ├── regs_ram.identifier.el │ │ ├── sreg.identifier.el │ │ ├── tb_alu.identifier.el │ │ ├── tb_bin2bcd.identifier.el │ │ ├── tb_clocks.identifier.el │ │ ├── tb_cpu.identifier.el │ │ ├── tb_dma.identifier.el │ │ ├── tb_program.block.at.point.el │ │ ├── tb_program.identifier.el │ │ ├── tb_program.mod.point.el │ │ ├── tb_ram.identifier.el │ │ ├── tb_top.identifier.el │ │ ├── tb_uart.identifier.el │ │ ├── uart.identifier.el │ │ ├── uart_rx.identifier.el │ │ ├── uart_tx.identifier.el │ │ ├── ucontroller.block.at.point.el │ │ ├── ucontroller.identifier.el │ │ ├── ucontroller.inst.point.el │ │ ├── ucontroller.mod.point.el │ │ ├── uvm_component.block.at.point.el │ │ ├── uvm_component.identifier.el │ │ └── uvm_component.mod.point.el └── src │ ├── verilog-ts-mode-test-beautify.el │ ├── verilog-ts-mode-test-faceup.el │ ├── verilog-ts-mode-test-imenu.el │ ├── verilog-ts-mode-test-indent.el │ ├── verilog-ts-mode-test-navigation.el │ ├── verilog-ts-mode-test-setup-package-test.el │ ├── verilog-ts-mode-test-setup-package.el │ ├── verilog-ts-mode-test-setup-straight.el │ ├── verilog-ts-mode-test-utils.el │ └── verilog-ts-mode-test.el └── verilog-ts-mode.el /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | github: gmlarumbe 2 | -------------------------------------------------------------------------------- /.github/workflows/build_package_melpa_basic.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/build_package_melpa_basic.yml -------------------------------------------------------------------------------- /.github/workflows/build_package_melpa_stable.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/build_package_melpa_stable.yml -------------------------------------------------------------------------------- /.github/workflows/build_straight.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/build_straight.yml -------------------------------------------------------------------------------- /.github/workflows/build_straight_release_snapshot.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/build_straight_release_snapshot.yml -------------------------------------------------------------------------------- /.github/workflows/build_straight_snapshot.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/build_straight_snapshot.yml -------------------------------------------------------------------------------- /.github/workflows/elisp_check.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/elisp_check.yml -------------------------------------------------------------------------------- /.github/workflows/melpazoid.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.github/workflows/melpazoid.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.elc 2 | test/dump 3 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/.gitmodules -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/README.md -------------------------------------------------------------------------------- /test/files/common/axi_demux.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/common/axi_demux.sv -------------------------------------------------------------------------------- /test/files/common/axi_test.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/common/axi_test.sv -------------------------------------------------------------------------------- /test/files/common/instances.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/common/instances.sv -------------------------------------------------------------------------------- /test/files/common/tb_program.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/common/tb_program.sv -------------------------------------------------------------------------------- /test/files/common/ucontroller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/common/ucontroller.sv -------------------------------------------------------------------------------- /test/files/common/uvm_component.svh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/common/uvm_component.svh -------------------------------------------------------------------------------- /test/files/github/tree_sitter_systemverilog_49.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/github/tree_sitter_systemverilog_49.sv -------------------------------------------------------------------------------- /test/files/github/verilog_ext_29.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/github/verilog_ext_29.sv -------------------------------------------------------------------------------- /test/files/github/verilog_ts_mode_3.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/github/verilog_ts_mode_3.sv -------------------------------------------------------------------------------- /test/files/prettify/pretty-declarations.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/prettify/pretty-declarations.sv -------------------------------------------------------------------------------- /test/files/prettify/pretty-expr.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/prettify/pretty-expr.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/alu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/alu.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/bin2bcd.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/bin2bcd.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/cpu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/cpu.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/dma.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/dma.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/dma_arbiter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/dma_arbiter.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/dma_rx.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/dma_rx.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/dma_tx.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/dma_tx.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/fifo_wrapper.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/fifo_wrapper.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/global_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/global_pkg.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/gp_ram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/gp_ram.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/ram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/ram.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/ram_arbiter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/ram_arbiter.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/regs_ram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/regs_ram.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/sreg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/sreg.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/uart.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/uart.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/uart_rx.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/uart_rx.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/uart_tx.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/uart_tx.sv -------------------------------------------------------------------------------- /test/files/ucontroller/rtl/ucontroller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/rtl/ucontroller.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/fifo_generator_0_sim_netlist.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/fifo_generator_0_sim_netlist.v -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_alu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_alu.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_bin2bcd.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_bin2bcd.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_clocks.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_clocks.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_cpu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_cpu.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_dma.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_dma.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_program.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_program.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_ram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_ram.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_top.sv -------------------------------------------------------------------------------- /test/files/ucontroller/tb/tb_uart.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/ucontroller/tb/tb_uart.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_1.v -------------------------------------------------------------------------------- /test/files/veripool/indent_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_3.v -------------------------------------------------------------------------------- /test/files/veripool/indent_4.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_4.v -------------------------------------------------------------------------------- /test/files/veripool/indent_always_decl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_always_decl.v -------------------------------------------------------------------------------- /test/files/veripool/indent_analog.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_analog.v -------------------------------------------------------------------------------- /test/files/veripool/indent_assert.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_assert.v -------------------------------------------------------------------------------- /test/files/veripool/indent_assert_else.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_assert_else.v -------------------------------------------------------------------------------- /test/files/veripool/indent_assert_property.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_assert_property.v -------------------------------------------------------------------------------- /test/files/veripool/indent_assignment.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_assignment.v -------------------------------------------------------------------------------- /test/files/veripool/indent_attributes.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_attributes.v -------------------------------------------------------------------------------- /test/files/veripool/indent_begin_clapp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_begin_clapp.v -------------------------------------------------------------------------------- /test/files/veripool/indent_bracket.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_bracket.v -------------------------------------------------------------------------------- /test/files/veripool/indent_case.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_case.v -------------------------------------------------------------------------------- /test/files/veripool/indent_class.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_class.v -------------------------------------------------------------------------------- /test/files/veripool/indent_class_pkg_nil.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_class_pkg_nil.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_clocking.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_clocking.v -------------------------------------------------------------------------------- /test/files/veripool/indent_clockingblock.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_clockingblock.v -------------------------------------------------------------------------------- /test/files/veripool/indent_comments.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_comments.v -------------------------------------------------------------------------------- /test/files/veripool/indent_comments_bug1717.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_comments_bug1717.v -------------------------------------------------------------------------------- /test/files/veripool/indent_connectmodule.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_connectmodule.v -------------------------------------------------------------------------------- /test/files/veripool/indent_constraint.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_constraint.v -------------------------------------------------------------------------------- /test/files/veripool/indent_constraint2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_constraint2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_constraint3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_constraint3.v -------------------------------------------------------------------------------- /test/files/veripool/indent_covergroup.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_covergroup.v -------------------------------------------------------------------------------- /test/files/veripool/indent_covergroup_swan.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_covergroup_swan.v -------------------------------------------------------------------------------- /test/files/veripool/indent_coverpoint.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_coverpoint.v -------------------------------------------------------------------------------- /test/files/veripool/indent_decl-1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_decl-1.v -------------------------------------------------------------------------------- /test/files/veripool/indent_decl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_decl.v -------------------------------------------------------------------------------- /test/files/veripool/indent_decl_1760.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_decl_1760.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_directives.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_directives.v -------------------------------------------------------------------------------- /test/files/veripool/indent_double_curly.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_double_curly.v -------------------------------------------------------------------------------- /test/files/veripool/indent_dpi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_dpi.v -------------------------------------------------------------------------------- /test/files/veripool/indent_enum.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_enum.v -------------------------------------------------------------------------------- /test/files/veripool/indent_foreach.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_foreach.v -------------------------------------------------------------------------------- /test/files/veripool/indent_fork_join_any.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_fork_join_any.v -------------------------------------------------------------------------------- /test/files/veripool/indent_formfeed.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_formfeed.v -------------------------------------------------------------------------------- /test/files/veripool/indent_function.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_function.v -------------------------------------------------------------------------------- /test/files/veripool/indent_generate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_generate.v -------------------------------------------------------------------------------- /test/files/veripool/indent_generate_bug1257.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_generate_bug1257.v -------------------------------------------------------------------------------- /test/files/veripool/indent_generate_bug1404.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_generate_bug1404.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_generate_case.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_generate_case.v -------------------------------------------------------------------------------- /test/files/veripool/indent_generate_for.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_generate_for.v -------------------------------------------------------------------------------- /test/files/veripool/indent_generate_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_generate_if.v -------------------------------------------------------------------------------- /test/files/veripool/indent_genmod.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_genmod.v -------------------------------------------------------------------------------- /test/files/veripool/indent_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_if.v -------------------------------------------------------------------------------- /test/files/veripool/indent_if2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_if2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_ifdef.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_ifdef.v -------------------------------------------------------------------------------- /test/files/veripool/indent_ifdef_generate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_ifdef_generate.v -------------------------------------------------------------------------------- /test/files/veripool/indent_immediate_assertion.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_immediate_assertion.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_importfunction.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_importfunction.v -------------------------------------------------------------------------------- /test/files/veripool/indent_interface.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_interface.v -------------------------------------------------------------------------------- /test/files/veripool/indent_interface_class_bug1047.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_interface_class_bug1047.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_linefeed.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_linefeed.v -------------------------------------------------------------------------------- /test/files/veripool/indent_lineup_inlists.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_lineup_inlists.v -------------------------------------------------------------------------------- /test/files/veripool/indent_lineup_mode_all.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_lineup_mode_all.v -------------------------------------------------------------------------------- /test/files/veripool/indent_lineup_mode_assignments.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_lineup_mode_assignments.v -------------------------------------------------------------------------------- /test/files/veripool/indent_lineup_mode_declarations.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_lineup_mode_declarations.v -------------------------------------------------------------------------------- /test/files/veripool/indent_lineup_mode_none.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_lineup_mode_none.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_align_ports_custom_type.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_align_ports_custom_type.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_continued_line.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_continued_line.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_generate_for.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_generate_for.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_generate_for2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_generate_for2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_generate_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_generate_if.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_generate_if2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_generate_if2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_if.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_if.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_methods.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_methods.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_param_port_list.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_param_port_list.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_params.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_params.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_params2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_params2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_pkg_class.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_pkg_class.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_report.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_report.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_list_nil_typedef_enum.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_list_nil_typedef_enum.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_macro_braces.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_macro_braces.v -------------------------------------------------------------------------------- /test/files/veripool/indent_macro_comment.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_macro_comment.v -------------------------------------------------------------------------------- /test/files/veripool/indent_macro_ignore_multiline.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_macro_ignore_multiline.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_macro_ignore_regexp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_macro_ignore_regexp.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_mailbox.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_mailbox.v -------------------------------------------------------------------------------- /test/files/veripool/indent_modansi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_modansi.v -------------------------------------------------------------------------------- /test/files/veripool/indent_modeln.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_modeln.v -------------------------------------------------------------------------------- /test/files/veripool/indent_modport.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_modport.v -------------------------------------------------------------------------------- /test/files/veripool/indent_named_assert.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_named_assert.v -------------------------------------------------------------------------------- /test/files/veripool/indent_ovm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_ovm.v -------------------------------------------------------------------------------- /test/files/veripool/indent_param.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_param.v -------------------------------------------------------------------------------- /test/files/veripool/indent_param_1645.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_param_1645.v -------------------------------------------------------------------------------- /test/files/veripool/indent_preproc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_preproc.v -------------------------------------------------------------------------------- /test/files/veripool/indent_preproc_label.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_preproc_label.v -------------------------------------------------------------------------------- /test/files/veripool/indent_property.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_property.v -------------------------------------------------------------------------------- /test/files/veripool/indent_property_bug1817.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_property_bug1817.v -------------------------------------------------------------------------------- /test/files/veripool/indent_randcase.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_randcase.v -------------------------------------------------------------------------------- /test/files/veripool/indent_random.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_random.v -------------------------------------------------------------------------------- /test/files/veripool/indent_reftype.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_reftype.v -------------------------------------------------------------------------------- /test/files/veripool/indent_rep_msg1188.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_rep_msg1188.v -------------------------------------------------------------------------------- /test/files/veripool/indent_replicate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_replicate.v -------------------------------------------------------------------------------- /test/files/veripool/indent_replicate_bug955.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_replicate_bug955.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_sexp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_sexp.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_streaming_op.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_streaming_op.v -------------------------------------------------------------------------------- /test/files/veripool/indent_struct.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_struct.v -------------------------------------------------------------------------------- /test/files/veripool/indent_sv_interface_mp_bug636.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_sv_interface_mp_bug636.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_task.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_task.v -------------------------------------------------------------------------------- /test/files/veripool/indent_task_func_decl.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_task_func_decl.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_typedef.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_typedef.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_typedef_enum.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_typedef_enum.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_unique_case-1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_unique_case-1.v -------------------------------------------------------------------------------- /test/files/veripool/indent_unique_case-2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_unique_case-2.v -------------------------------------------------------------------------------- /test/files/veripool/indent_unique_case.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_unique_case.v -------------------------------------------------------------------------------- /test/files/veripool/indent_uvm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_uvm.v -------------------------------------------------------------------------------- /test/files/veripool/indent_virtual_class.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_virtual_class.sv -------------------------------------------------------------------------------- /test/files/veripool/indent_warren.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/files/veripool/indent_warren.v -------------------------------------------------------------------------------- /test/ref/beautify/axi_demux.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_demux.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_demux.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_demux.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_demux.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_demux.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_demux.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_demux.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_test.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_test.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_test.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_test.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_test.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_test.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/axi_test.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/axi_test.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_1.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_1.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_1.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_1.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_3.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_3.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_3.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_3.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_4.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_4.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_4.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_4.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_always_decl.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_always_decl.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_always_decl.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_always_decl.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_analog.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_analog.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_analog.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_analog.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assert.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assert.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assert.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assert.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assert_else.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assert_else.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assert_else.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assert_else.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assert_property.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assert_property.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assert_property.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assert_property.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assignment.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assignment.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_assignment.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_assignment.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_attributes.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_attributes.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_attributes.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_attributes.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_begin_clapp.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_begin_clapp.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_begin_clapp.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_begin_clapp.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_bracket.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_bracket.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_bracket.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_bracket.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_case.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_case.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_case.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_case.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_class.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_class.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_class.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_class.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_class_pkg_nil.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_class_pkg_nil.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_class_pkg_nil.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_class_pkg_nil.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_clocking.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_clocking.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_clocking.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_clocking.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_clockingblock.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_clockingblock.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_clockingblock.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_clockingblock.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_comments.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_comments.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_comments.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_comments.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_comments_bug1717.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_comments_bug1717.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_comments_bug1717.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_comments_bug1717.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_connectmodule.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_connectmodule.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_connectmodule.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_connectmodule.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_constraint.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_constraint.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_constraint.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_constraint.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_constraint2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_constraint2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_constraint2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_constraint2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_constraint3.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_constraint3.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_constraint3.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_constraint3.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_covergroup.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_covergroup.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_covergroup.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_covergroup.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_covergroup_swan.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_covergroup_swan.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_covergroup_swan.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_covergroup_swan.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_coverpoint.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_coverpoint.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_coverpoint.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_coverpoint.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_decl-1.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_decl-1.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_decl-1.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_decl-1.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_decl.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_decl.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_decl.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_decl.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_decl_1760.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_decl_1760.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_decl_1760.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_decl_1760.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_directives.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_directives.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_directives.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_directives.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_double_curly.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_double_curly.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_double_curly.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_double_curly.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_dpi.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_dpi.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_dpi.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_dpi.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_enum.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_enum.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_enum.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_enum.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_foreach.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_foreach.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_foreach.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_foreach.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_fork_join_any.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_fork_join_any.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_fork_join_any.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_fork_join_any.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_formfeed.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_formfeed.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_formfeed.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_formfeed.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_function.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_function.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_function.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_function.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_bug1257.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_bug1257.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_bug1257.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_bug1257.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_bug1404.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_bug1404.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_bug1404.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_bug1404.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_case.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_case.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_case.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_case.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_for.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_for.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_for.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_for.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_if.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_if.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_generate_if.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_generate_if.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_genmod.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_genmod.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_genmod.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_genmod.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_if.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_if.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_if.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_if.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_if2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_if2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_if2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_if2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_ifdef.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_ifdef.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_ifdef.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_ifdef.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_ifdef_generate.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_ifdef_generate.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_ifdef_generate.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_ifdef_generate.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_immediate_assertion.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_immediate_assertion.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_immediate_assertion.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_immediate_assertion.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_importfunction.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_importfunction.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_importfunction.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_importfunction.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_interface.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_interface.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_interface.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_interface.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_interface_class_bug1047.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_interface_class_bug1047.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_linefeed.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_linefeed.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_linefeed.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_linefeed.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_inlists.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_inlists.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_inlists.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_inlists.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_mode_all.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_mode_all.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_mode_all.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_mode_all.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_mode_assignments.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_mode_assignments.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_mode_declarations.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_mode_declarations.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_mode_none.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_mode_none.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_lineup_mode_none.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_lineup_mode_none.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_align_ports_custom_type.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_align_ports_custom_type.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_continued_line.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_continued_line.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_for.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_for.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_for.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_for.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_for2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_for2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_for2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_for2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_if.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_if.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_if.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_if.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_if2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_if2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_generate_if2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_generate_if2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_if.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_if.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_if.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_if.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_methods.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_methods.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_methods.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_methods.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_param_port_list.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_param_port_list.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_params.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_params.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_params.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_params.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_params2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_params2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_params2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_params2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_pkg_class.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_pkg_class.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_pkg_class.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_pkg_class.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_report.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_report.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_report.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_report.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_typedef_enum.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_typedef_enum.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_list_nil_typedef_enum.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_list_nil_typedef_enum.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_braces.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_braces.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_braces.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_braces.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_comment.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_comment.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_comment.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_comment.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_ignore_multiline.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_ignore_multiline.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_ignore_multiline.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_ignore_multiline.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_ignore_regexp.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_ignore_regexp.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_macro_ignore_regexp.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_macro_ignore_regexp.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_mailbox.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_mailbox.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_mailbox.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_mailbox.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_modansi.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_modansi.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_modansi.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_modansi.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_modeln.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_modeln.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_modeln.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_modeln.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_modport.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_modport.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_modport.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_modport.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_named_assert.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_named_assert.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_named_assert.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_named_assert.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_ovm.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_ovm.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_ovm.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_ovm.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_param.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_param.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_param.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_param.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_param_1645.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_param_1645.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_param_1645.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_param_1645.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_preproc.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_preproc.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_preproc.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_preproc.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_preproc_label.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_preproc_label.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_preproc_label.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_preproc_label.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_property.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_property.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_property.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_property.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_property_bug1817.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_property_bug1817.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_property_bug1817.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_property_bug1817.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_randcase.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_randcase.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_randcase.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_randcase.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_random.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_random.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_random.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_random.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_reftype.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_reftype.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_reftype.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_reftype.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_rep_msg1188.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_rep_msg1188.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_rep_msg1188.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_rep_msg1188.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_replicate.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_replicate.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_replicate.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_replicate.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_replicate_bug955.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_replicate_bug955.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_replicate_bug955.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_replicate_bug955.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_sexp.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_sexp.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_sexp.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_sexp.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_streaming_op.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_streaming_op.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_streaming_op.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_streaming_op.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_struct.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_struct.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_struct.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_struct.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_sv_interface_mp_bug636.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_sv_interface_mp_bug636.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_sv_interface_mp_bug636.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_sv_interface_mp_bug636.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_task.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_task.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_task.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_task.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_task_func_decl.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_task_func_decl.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_task_func_decl.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_task_func_decl.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_typedef.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_typedef.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_typedef.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_typedef.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_typedef_enum.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_typedef_enum.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_typedef_enum.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_typedef_enum.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_unique_case-1.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_unique_case-1.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_unique_case-1.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_unique_case-1.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_unique_case-2.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_unique_case-2.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_unique_case-2.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_unique_case-2.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_unique_case.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_unique_case.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_unique_case.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_unique_case.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_uvm.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_uvm.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_uvm.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_uvm.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_virtual_class.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_virtual_class.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_virtual_class.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_virtual_class.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_warren.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_warren.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/indent_warren.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/indent_warren.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/instances.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/instances.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/instances.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/instances.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/instances.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/instances.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/instances.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/instances.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/misc.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/misc.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/misc.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/misc.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/misc.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/misc.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/misc.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/misc.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/pretty-declarations.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/pretty-declarations.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/pretty-declarations.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/pretty-declarations.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/pretty-expr.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/pretty-expr.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/pretty-expr.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/pretty-expr.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/tb_program.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tb_program.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/tb_program.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tb_program.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/tb_program.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tb_program.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/tb_program.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tb_program.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/tree_sitter_systemverilog_49.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tree_sitter_systemverilog_49.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/tree_sitter_systemverilog_49.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tree_sitter_systemverilog_49.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/tree_sitter_systemverilog_49.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/tree_sitter_systemverilog_49.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/ucontroller.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/ucontroller.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/ucontroller.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/ucontroller.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/ucontroller.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/ucontroller.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/ucontroller.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/ucontroller.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/uvm_component.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/uvm_component.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/uvm_component.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/uvm_component.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/uvm_component.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/uvm_component.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/uvm_component.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/uvm_component.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ext_29.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ext_29.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ext_29.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ext_29.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ext_29.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ext_29.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ext_29.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ext_29.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ts_mode_3.beauty.extra.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ts_mode_3.beauty.extra.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ts_mode_3.beauty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ts_mode_3.beauty.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ts_mode_3.no_comm_align.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ts_mode_3.no_comm_align.pretty.sv -------------------------------------------------------------------------------- /test/ref/beautify/verilog_ts_mode_3.pretty.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/beautify/verilog_ts_mode_3.pretty.sv -------------------------------------------------------------------------------- /test/ref/faceup/axi_demux.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/axi_demux.faceup -------------------------------------------------------------------------------- /test/ref/faceup/axi_test.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/axi_test.faceup -------------------------------------------------------------------------------- /test/ref/faceup/instances.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/instances.faceup -------------------------------------------------------------------------------- /test/ref/faceup/misc.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/misc.faceup -------------------------------------------------------------------------------- /test/ref/faceup/tb_program.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/tb_program.faceup -------------------------------------------------------------------------------- /test/ref/faceup/tree_sitter_systemverilog_49.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/tree_sitter_systemverilog_49.faceup -------------------------------------------------------------------------------- /test/ref/faceup/ucontroller.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/ucontroller.faceup -------------------------------------------------------------------------------- /test/ref/faceup/uvm_component.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/uvm_component.faceup -------------------------------------------------------------------------------- /test/ref/faceup/verilog_ext_29.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/verilog_ext_29.faceup -------------------------------------------------------------------------------- /test/ref/faceup/verilog_ts_mode_3.faceup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/faceup/verilog_ts_mode_3.faceup -------------------------------------------------------------------------------- /test/ref/imenu/axi_demux.simple.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/axi_demux.simple.el -------------------------------------------------------------------------------- /test/ref/imenu/axi_demux.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/axi_demux.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/axi_demux.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/axi_demux.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/axi_test.simple.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/axi_test.simple.el -------------------------------------------------------------------------------- /test/ref/imenu/axi_test.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/axi_test.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/axi_test.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/axi_test.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/instances.simple.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/instances.simple.el -------------------------------------------------------------------------------- /test/ref/imenu/instances.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/instances.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/instances.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/instances.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/misc.simple.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/imenu/misc.tree.el: -------------------------------------------------------------------------------- 1 | (("foo" . 86)) 2 | -------------------------------------------------------------------------------- /test/ref/imenu/misc.tree.group.el: -------------------------------------------------------------------------------- 1 | (("foo" . 86)) 2 | -------------------------------------------------------------------------------- /test/ref/imenu/tb_program.simple.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/tb_program.simple.el -------------------------------------------------------------------------------- /test/ref/imenu/tb_program.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/tb_program.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/tb_program.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/tb_program.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/tree_sitter_systemverilog_49.simple.el: -------------------------------------------------------------------------------- 1 | (("Always" 2 | ("a" . #))) 3 | -------------------------------------------------------------------------------- /test/ref/imenu/tree_sitter_systemverilog_49.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/tree_sitter_systemverilog_49.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/tree_sitter_systemverilog_49.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/tree_sitter_systemverilog_49.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/ucontroller.simple.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/ucontroller.simple.el -------------------------------------------------------------------------------- /test/ref/imenu/ucontroller.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/ucontroller.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/ucontroller.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/ucontroller.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/uvm_component.simple.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/uvm_component.simple.el -------------------------------------------------------------------------------- /test/ref/imenu/uvm_component.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/uvm_component.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/uvm_component.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/uvm_component.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/verilog_ext_29.simple.el: -------------------------------------------------------------------------------- 1 | (("Instance" 2 | ("foo_module" . #))) 3 | -------------------------------------------------------------------------------- /test/ref/imenu/verilog_ext_29.tree.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/verilog_ext_29.tree.el -------------------------------------------------------------------------------- /test/ref/imenu/verilog_ext_29.tree.group.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/imenu/verilog_ext_29.tree.group.el -------------------------------------------------------------------------------- /test/ref/imenu/verilog_ts_mode_3.simple.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/imenu/verilog_ts_mode_3.tree.el: -------------------------------------------------------------------------------- 1 | (("foo" . 86)) 2 | -------------------------------------------------------------------------------- /test/ref/imenu/verilog_ts_mode_3.tree.group.el: -------------------------------------------------------------------------------- 1 | (("foo" . 86)) 2 | -------------------------------------------------------------------------------- /test/ref/indent/axi_demux.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/axi_demux.sv -------------------------------------------------------------------------------- /test/ref/indent/axi_test.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/axi_test.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_1.v -------------------------------------------------------------------------------- /test/ref/indent/indent_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_3.v -------------------------------------------------------------------------------- /test/ref/indent/indent_4.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_4.v -------------------------------------------------------------------------------- /test/ref/indent/indent_always_decl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_always_decl.v -------------------------------------------------------------------------------- /test/ref/indent/indent_analog.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_analog.v -------------------------------------------------------------------------------- /test/ref/indent/indent_assert.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_assert.v -------------------------------------------------------------------------------- /test/ref/indent/indent_assert_else.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_assert_else.v -------------------------------------------------------------------------------- /test/ref/indent/indent_assert_property.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_assert_property.v -------------------------------------------------------------------------------- /test/ref/indent/indent_assignment.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_assignment.v -------------------------------------------------------------------------------- /test/ref/indent/indent_attributes.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_attributes.v -------------------------------------------------------------------------------- /test/ref/indent/indent_begin_clapp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_begin_clapp.v -------------------------------------------------------------------------------- /test/ref/indent/indent_bracket.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_bracket.v -------------------------------------------------------------------------------- /test/ref/indent/indent_case.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_case.v -------------------------------------------------------------------------------- /test/ref/indent/indent_class.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_class.v -------------------------------------------------------------------------------- /test/ref/indent/indent_class_pkg_nil.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_class_pkg_nil.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_clocking.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_clocking.v -------------------------------------------------------------------------------- /test/ref/indent/indent_clockingblock.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_clockingblock.v -------------------------------------------------------------------------------- /test/ref/indent/indent_comments.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_comments.v -------------------------------------------------------------------------------- /test/ref/indent/indent_comments_bug1717.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_comments_bug1717.v -------------------------------------------------------------------------------- /test/ref/indent/indent_connectmodule.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_connectmodule.v -------------------------------------------------------------------------------- /test/ref/indent/indent_constraint.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_constraint.v -------------------------------------------------------------------------------- /test/ref/indent/indent_constraint2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_constraint2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_constraint3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_constraint3.v -------------------------------------------------------------------------------- /test/ref/indent/indent_covergroup.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_covergroup.v -------------------------------------------------------------------------------- /test/ref/indent/indent_covergroup_swan.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_covergroup_swan.v -------------------------------------------------------------------------------- /test/ref/indent/indent_coverpoint.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_coverpoint.v -------------------------------------------------------------------------------- /test/ref/indent/indent_decl-1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_decl-1.v -------------------------------------------------------------------------------- /test/ref/indent/indent_decl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_decl.v -------------------------------------------------------------------------------- /test/ref/indent/indent_decl_1760.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_decl_1760.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_directives.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_directives.v -------------------------------------------------------------------------------- /test/ref/indent/indent_double_curly.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_double_curly.v -------------------------------------------------------------------------------- /test/ref/indent/indent_dpi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_dpi.v -------------------------------------------------------------------------------- /test/ref/indent/indent_enum.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_enum.v -------------------------------------------------------------------------------- /test/ref/indent/indent_foreach.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_foreach.v -------------------------------------------------------------------------------- /test/ref/indent/indent_fork_join_any.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_fork_join_any.v -------------------------------------------------------------------------------- /test/ref/indent/indent_formfeed.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_formfeed.v -------------------------------------------------------------------------------- /test/ref/indent/indent_function.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_function.v -------------------------------------------------------------------------------- /test/ref/indent/indent_generate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_generate.v -------------------------------------------------------------------------------- /test/ref/indent/indent_generate_bug1257.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_generate_bug1257.v -------------------------------------------------------------------------------- /test/ref/indent/indent_generate_bug1404.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_generate_bug1404.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_generate_case.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_generate_case.v -------------------------------------------------------------------------------- /test/ref/indent/indent_generate_for.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_generate_for.v -------------------------------------------------------------------------------- /test/ref/indent/indent_generate_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_generate_if.v -------------------------------------------------------------------------------- /test/ref/indent/indent_genmod.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_genmod.v -------------------------------------------------------------------------------- /test/ref/indent/indent_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_if.v -------------------------------------------------------------------------------- /test/ref/indent/indent_if2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_if2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_ifdef.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_ifdef.v -------------------------------------------------------------------------------- /test/ref/indent/indent_ifdef_generate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_ifdef_generate.v -------------------------------------------------------------------------------- /test/ref/indent/indent_immediate_assertion.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_immediate_assertion.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_importfunction.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_importfunction.v -------------------------------------------------------------------------------- /test/ref/indent/indent_interface.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_interface.v -------------------------------------------------------------------------------- /test/ref/indent/indent_interface_class_bug1047.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_interface_class_bug1047.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_linefeed.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_linefeed.v -------------------------------------------------------------------------------- /test/ref/indent/indent_lineup_inlists.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_lineup_inlists.v -------------------------------------------------------------------------------- /test/ref/indent/indent_lineup_mode_all.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_lineup_mode_all.v -------------------------------------------------------------------------------- /test/ref/indent/indent_lineup_mode_assignments.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_lineup_mode_assignments.v -------------------------------------------------------------------------------- /test/ref/indent/indent_lineup_mode_declarations.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_lineup_mode_declarations.v -------------------------------------------------------------------------------- /test/ref/indent/indent_lineup_mode_none.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_lineup_mode_none.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_align_ports_custom_type.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_align_ports_custom_type.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_continued_line.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_continued_line.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_generate_for.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_generate_for.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_generate_for2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_generate_for2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_generate_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_generate_if.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_generate_if2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_generate_if2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_if.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_if.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_methods.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_methods.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_param_port_list.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_param_port_list.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_params.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_params.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_params2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_params2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_pkg_class.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_pkg_class.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_report.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_report.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_list_nil_typedef_enum.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_list_nil_typedef_enum.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_macro_braces.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_macro_braces.v -------------------------------------------------------------------------------- /test/ref/indent/indent_macro_comment.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_macro_comment.v -------------------------------------------------------------------------------- /test/ref/indent/indent_macro_ignore_multiline.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_macro_ignore_multiline.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_macro_ignore_regexp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_macro_ignore_regexp.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_mailbox.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_mailbox.v -------------------------------------------------------------------------------- /test/ref/indent/indent_modansi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_modansi.v -------------------------------------------------------------------------------- /test/ref/indent/indent_modeln.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_modeln.v -------------------------------------------------------------------------------- /test/ref/indent/indent_modport.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_modport.v -------------------------------------------------------------------------------- /test/ref/indent/indent_named_assert.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_named_assert.v -------------------------------------------------------------------------------- /test/ref/indent/indent_ovm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_ovm.v -------------------------------------------------------------------------------- /test/ref/indent/indent_param.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_param.v -------------------------------------------------------------------------------- /test/ref/indent/indent_param_1645.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_param_1645.v -------------------------------------------------------------------------------- /test/ref/indent/indent_preproc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_preproc.v -------------------------------------------------------------------------------- /test/ref/indent/indent_preproc_label.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_preproc_label.v -------------------------------------------------------------------------------- /test/ref/indent/indent_property.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_property.v -------------------------------------------------------------------------------- /test/ref/indent/indent_property_bug1817.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_property_bug1817.v -------------------------------------------------------------------------------- /test/ref/indent/indent_randcase.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_randcase.v -------------------------------------------------------------------------------- /test/ref/indent/indent_random.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_random.v -------------------------------------------------------------------------------- /test/ref/indent/indent_reftype.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_reftype.v -------------------------------------------------------------------------------- /test/ref/indent/indent_rep_msg1188.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_rep_msg1188.v -------------------------------------------------------------------------------- /test/ref/indent/indent_replicate.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_replicate.v -------------------------------------------------------------------------------- /test/ref/indent/indent_replicate_bug955.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_replicate_bug955.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_sexp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_sexp.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_streaming_op.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_streaming_op.v -------------------------------------------------------------------------------- /test/ref/indent/indent_struct.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_struct.v -------------------------------------------------------------------------------- /test/ref/indent/indent_sv_interface_mp_bug636.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_sv_interface_mp_bug636.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_task.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_task.v -------------------------------------------------------------------------------- /test/ref/indent/indent_task_func_decl.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_task_func_decl.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_typedef.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_typedef.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_typedef_enum.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_typedef_enum.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_unique_case-1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_unique_case-1.v -------------------------------------------------------------------------------- /test/ref/indent/indent_unique_case-2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_unique_case-2.v -------------------------------------------------------------------------------- /test/ref/indent/indent_unique_case.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_unique_case.v -------------------------------------------------------------------------------- /test/ref/indent/indent_uvm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_uvm.v -------------------------------------------------------------------------------- /test/ref/indent/indent_virtual_class.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_virtual_class.sv -------------------------------------------------------------------------------- /test/ref/indent/indent_warren.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/indent_warren.v -------------------------------------------------------------------------------- /test/ref/indent/instances.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/instances.sv -------------------------------------------------------------------------------- /test/ref/indent/misc.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/misc.sv -------------------------------------------------------------------------------- /test/ref/indent/tb_program.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/tb_program.sv -------------------------------------------------------------------------------- /test/ref/indent/tree_sitter_systemverilog_49.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/tree_sitter_systemverilog_49.sv -------------------------------------------------------------------------------- /test/ref/indent/ucontroller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/ucontroller.sv -------------------------------------------------------------------------------- /test/ref/indent/uvm_component.svh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/uvm_component.svh -------------------------------------------------------------------------------- /test/ref/indent/verilog_ext_29.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/verilog_ext_29.sv -------------------------------------------------------------------------------- /test/ref/indent/verilog_ts_mode_3.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/indent/verilog_ts_mode_3.sv -------------------------------------------------------------------------------- /test/ref/navigation/axi_demux.block.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_demux.block.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_demux.block.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_demux.block.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_demux.inst.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_demux.inst.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_demux.inst.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_demux.inst.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.block.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.block.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.block.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.block.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.bwd.sexp.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.bwd.sexp.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.class.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.class.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.class.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.class.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.defun.down.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.defun.down.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.defun.up.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.defun.up.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.fwd.sexp.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.fwd.sexp.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.tf.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.tf.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/axi_test.tf.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/axi_test.tf.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/instances.block.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/instances.block.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/instances.block.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/instances.block.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/instances.inst.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/instances.inst.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/instances.inst.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/instances.inst.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/misc.block.bwd.el: -------------------------------------------------------------------------------- 1 | (86) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/misc.block.fwd.el: -------------------------------------------------------------------------------- 1 | (86) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.block.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/tb_program.block.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.block.fwd.el: -------------------------------------------------------------------------------- 1 | (1613 1871 3477 3547 4002 4319 4535) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.class.bwd.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.class.fwd.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.defun.down.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/tb_program.defun.down.el -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.defun.up.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/tb_program.defun.up.el -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.tf.bwd.el: -------------------------------------------------------------------------------- 1 | (3799 3547 3477 1871) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/tb_program.tf.fwd.el: -------------------------------------------------------------------------------- 1 | (1871 3477 3547 3799) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/tree_sitter_systemverilog_49.block.bwd.el: -------------------------------------------------------------------------------- 1 | (56 44 1) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/tree_sitter_systemverilog_49.block.fwd.el: -------------------------------------------------------------------------------- 1 | (56) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/ucontroller.block.bwd.el: -------------------------------------------------------------------------------- 1 | (4597 4127 3759 3209 3007 2335 834) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/ucontroller.block.fwd.el: -------------------------------------------------------------------------------- 1 | (2335 3007 3209 3759 4127 4597) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/ucontroller.inst.bwd.el: -------------------------------------------------------------------------------- 1 | (4597 4127 3759 3209 3007 2335) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/ucontroller.inst.fwd.el: -------------------------------------------------------------------------------- 1 | (2335 3007 3209 3759 4127 4597) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.block.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.block.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.block.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.block.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.bwd.sexp.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.bwd.sexp.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.class.bwd.el: -------------------------------------------------------------------------------- 1 | (1828) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.class.fwd.el: -------------------------------------------------------------------------------- 1 | (1828) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.defun.down.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.defun.down.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.defun.up.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.defun.up.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.fwd.sexp.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.fwd.sexp.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.tf.bwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.tf.bwd.el -------------------------------------------------------------------------------- /test/ref/navigation/uvm_component.tf.fwd.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/navigation/uvm_component.tf.fwd.el -------------------------------------------------------------------------------- /test/ref/navigation/verilog_ext_29.block.bwd.el: -------------------------------------------------------------------------------- 1 | (14 1) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/verilog_ext_29.block.fwd.el: -------------------------------------------------------------------------------- 1 | (14) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/verilog_ts_mode_3.block.bwd.el: -------------------------------------------------------------------------------- 1 | (86) 2 | -------------------------------------------------------------------------------- /test/ref/navigation/verilog_ts_mode_3.block.fwd.el: -------------------------------------------------------------------------------- 1 | (86) 2 | -------------------------------------------------------------------------------- /test/ref/utils/alu.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/alu.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/axi_demux.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/axi_demux.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/axi_demux.mod.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/axi_demux.mod.point.el -------------------------------------------------------------------------------- /test/ref/utils/axi_test.block.at.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/axi_test.block.at.point.el -------------------------------------------------------------------------------- /test/ref/utils/axi_test.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/axi_test.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/axi_test.mod.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/axi_test.mod.point.el -------------------------------------------------------------------------------- /test/ref/utils/bin2bcd.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/bin2bcd.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/cpu.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/cpu.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/dma.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/dma.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/dma_arbiter.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/dma_arbiter.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/dma_rx.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/dma_rx.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/dma_tx.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/dma_tx.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/fifo_generator_0_sim_netlist.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/fifo_generator_0_sim_netlist.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/fifo_wrapper.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/fifo_wrapper.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/global_pkg.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/global_pkg.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/gp_ram.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/gp_ram.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_1.identifier.el: -------------------------------------------------------------------------------- 1 | (("foo" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_2.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_2.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_3.identifier.el: -------------------------------------------------------------------------------- 1 | (("junk" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_4.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_4.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_always_decl.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_always_decl.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_analog.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_analog.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_assert.identifier.el: -------------------------------------------------------------------------------- 1 | (("whatever2" "reg [31:0]") 2 | ("assert_test" "module_declaration")) 3 | -------------------------------------------------------------------------------- /test/ref/utils/indent_assert_else.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_assert_else.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_assert_property.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_assert_property.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_assignment.identifier.el: -------------------------------------------------------------------------------- 1 | (("m" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_attributes.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_attributes.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_begin_clapp.identifier.el: -------------------------------------------------------------------------------- 1 | (("x" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_bracket.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_bracket.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_case.identifier.el: -------------------------------------------------------------------------------- 1 | (("testcaseindent" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_class.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_class.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_class_pkg_nil.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_class_pkg_nil.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_clocking.identifier.el: -------------------------------------------------------------------------------- 1 | (("t" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_clockingblock.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_clockingblock.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_comments.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_comments.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_comments_bug1717.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_comments_bug1717.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_connectmodule.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_connectmodule.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_constraint.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_constraint.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_constraint2.identifier.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/utils/indent_constraint3.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_constraint3.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_covergroup.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_covergroup.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_covergroup_swan.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_covergroup_swan.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_coverpoint.identifier.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/utils/indent_decl-1.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_decl-1.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_decl.identifier.el: -------------------------------------------------------------------------------- 1 | (("foo" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_decl_1760.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_decl_1760.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_directives.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_directives.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_double_curly.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_dpi.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_dpi.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_enum.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_enum.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_foreach.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_foreach.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_fork_join_any.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_fork_join_any.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_formfeed.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_formfeed.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_function.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_function.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_generate.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_generate.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_generate_bug1257.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_generate_bug1257.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_generate_bug1404.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_generate_bug1404.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_generate_case.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_generate_case.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_generate_for.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_generate_for.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_generate_if.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_generate_if.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_genmod.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_genmod.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_if.identifier.el: -------------------------------------------------------------------------------- 1 | (("foo" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_if2.identifier.el: -------------------------------------------------------------------------------- 1 | (("foo" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_ifdef.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_ifdef_generate.identifier.el: -------------------------------------------------------------------------------- 1 | (("m" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_immediate_assertion.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_immediate_assertion.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_importfunction.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_importfunction.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_interface.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_interface.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_interface_class_bug1047.identifier.el: -------------------------------------------------------------------------------- 1 | (("ic" "interface_class_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_linefeed.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_linefeed.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_lineup_inlists.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_lineup_inlists.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_lineup_mode_all.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_lineup_mode_assignments.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_lineup_mode_declarations.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_lineup_mode_none.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_align_ports_custom_type.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_align_ports_custom_type.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_continued_line.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_continued_line.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_generate_for.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_generate_for.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_generate_for2.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_generate_for2.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_generate_if.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_generate_if.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_generate_if2.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_generate_if2.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_if.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_if.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_methods.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_methods.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_param_port_list.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_param_port_list.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_params.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_params.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_params2.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_params2.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_pkg_class.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_pkg_class.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_report.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_report.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_list_nil_typedef_enum.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_list_nil_typedef_enum.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_macro_braces.identifier.el: -------------------------------------------------------------------------------- 1 | (("m" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_macro_comment.identifier.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/utils/indent_macro_ignore_multiline.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_macro_ignore_multiline.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_macro_ignore_regexp.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_macro_ignore_regexp.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_mailbox.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_mailbox.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_modansi.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_modansi.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_modeln.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_modeln.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_modport.identifier.el: -------------------------------------------------------------------------------- 1 | (("a" "logic") 2 | ("foo" "interface_declaration")) 3 | -------------------------------------------------------------------------------- /test/ref/utils/indent_named_assert.identifier.el: -------------------------------------------------------------------------------- 1 | (("foo" "logic") 2 | ("test" "module_declaration")) 3 | -------------------------------------------------------------------------------- /test/ref/utils/indent_ovm.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_ovm.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_param.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_param.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_param_1645.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_param_1645.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_preproc.identifier.el: -------------------------------------------------------------------------------- 1 | nil -------------------------------------------------------------------------------- /test/ref/utils/indent_preproc_label.identifier.el: -------------------------------------------------------------------------------- 1 | (("m" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_property.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_property.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_property_bug1817.identifier.el: -------------------------------------------------------------------------------- 1 | (("test" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_randcase.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_randcase.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_random.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_random.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_reftype.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_reftype.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_rep_msg1188.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_rep_msg1188.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_replicate.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_replicate.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_replicate_bug955.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_replicate_bug955.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_sexp.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_sexp.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_streaming_op.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_streaming_op.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_struct.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_struct.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_sv_interface_mp_bug636.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_sv_interface_mp_bug636.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_task.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_task.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_task_func_decl.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_task_func_decl.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_typedef.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_typedef.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_typedef_enum.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_typedef_enum.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_unique_case-1.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_unique_case-1.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_unique_case-2.identifier.el: -------------------------------------------------------------------------------- 1 | (("testmod" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_unique_case.identifier.el: -------------------------------------------------------------------------------- 1 | (("foo" "module_declaration")) 2 | -------------------------------------------------------------------------------- /test/ref/utils/indent_uvm.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_uvm.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_virtual_class.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/indent_virtual_class.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/indent_warren.identifier.el: -------------------------------------------------------------------------------- 1 | (("y" "reg") 2 | ("x" "module_declaration")) 3 | -------------------------------------------------------------------------------- /test/ref/utils/instances.block.at.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/instances.block.at.point.el -------------------------------------------------------------------------------- /test/ref/utils/instances.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/instances.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/instances.inst.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/instances.inst.point.el -------------------------------------------------------------------------------- /test/ref/utils/instances.mod.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/instances.mod.point.el -------------------------------------------------------------------------------- /test/ref/utils/misc.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/misc.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/ram.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/ram.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/ram_arbiter.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/ram_arbiter.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/regs_ram.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/regs_ram.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/sreg.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/sreg.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_alu.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_alu.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_bin2bcd.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_bin2bcd.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_clocks.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_clocks.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_cpu.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_cpu.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_dma.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_dma.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_program.block.at.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_program.block.at.point.el -------------------------------------------------------------------------------- /test/ref/utils/tb_program.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_program.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_program.mod.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_program.mod.point.el -------------------------------------------------------------------------------- /test/ref/utils/tb_ram.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_ram.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_top.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_top.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/tb_uart.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/tb_uart.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/uart.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/uart.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/uart_rx.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/uart_rx.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/uart_tx.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/uart_tx.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/ucontroller.block.at.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/ucontroller.block.at.point.el -------------------------------------------------------------------------------- /test/ref/utils/ucontroller.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/ucontroller.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/ucontroller.inst.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/ucontroller.inst.point.el -------------------------------------------------------------------------------- /test/ref/utils/ucontroller.mod.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/ucontroller.mod.point.el -------------------------------------------------------------------------------- /test/ref/utils/uvm_component.block.at.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/uvm_component.block.at.point.el -------------------------------------------------------------------------------- /test/ref/utils/uvm_component.identifier.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/uvm_component.identifier.el -------------------------------------------------------------------------------- /test/ref/utils/uvm_component.mod.point.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/ref/utils/uvm_component.mod.point.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-beautify.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-beautify.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-faceup.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-faceup.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-imenu.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-imenu.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-indent.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-indent.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-navigation.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-navigation.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-setup-package-test.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-setup-package-test.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-setup-package.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-setup-package.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-setup-straight.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-setup-straight.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test-utils.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test-utils.el -------------------------------------------------------------------------------- /test/src/verilog-ts-mode-test.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/test/src/verilog-ts-mode-test.el -------------------------------------------------------------------------------- /verilog-ts-mode.el: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gmlarumbe/verilog-ts-mode/HEAD/verilog-ts-mode.el --------------------------------------------------------------------------------