├── .gitignore ├── AddedExtensionProjectTemplates ├── LiteX │ ├── AssemblyInfo.cs │ ├── LiteX.csproj │ ├── LiteX.ico │ ├── LiteX.vstemplate │ ├── ProjectTemplate.csproj │ └── Properties │ │ └── AssemblyInfo.cs ├── ProjectTemplate-LiteX │ ├── AssemblyInfo.cs │ ├── ProjectTemplate-LiteX.csproj │ ├── ProjectTemplate-LiteX.ico │ ├── ProjectTemplate-LiteX.vstemplate │ ├── ProjectTemplate.csproj │ └── Properties │ │ └── AssemblyInfo.cs └── Verilog Project │ ├── App.config │ ├── Makefile │ ├── Makefile-iCEBreaker.mk │ ├── Program.cs │ ├── ProjectTemplate.csproj │ ├── Properties │ └── AssemblyInfo.cs │ ├── README.md │ ├── Verilog Project.csproj │ ├── Verilog Project.sln │ ├── Verilog.ico │ ├── Verilog.vstemplate │ ├── VerilogProjectTemplate.csproj.new │ ├── _not_used_Makefile-ULX3S-12F.mk │ ├── blinky.json │ ├── boards │ ├── icebreaker │ │ ├── README.md │ │ ├── icebreaker.pcf │ │ └── main.mk │ ├── orangecrab │ │ ├── Makefile │ │ ├── blink.v │ │ ├── orangecrab_r0.1.pcf │ │ └── orangecrab_r0.2.pcf │ ├── tinyfpga_bx │ │ ├── Makefile │ │ ├── TinyFPGA_B.v │ │ └── pins.pcf │ └── ulx3s │ │ ├── Makefile-ULX3S-12F.mk │ │ ├── Makefile-ULX3S-25F.mk │ │ ├── Makefile-ULX3S-45F.mk │ │ ├── Makefile-ULX3S-85F.mk │ │ └── ulx3s_v20.lpf │ ├── dtest.bat │ ├── images │ └── export_template.png │ ├── top.v │ ├── top.ys │ ├── top_icebreaker.v │ ├── ulx3s.ys │ ├── ulx3s_empty.config │ └── ulx3s_v20.lpf ├── BraceMatching ├── BraceMatchingTagger.cs └── BraceMatchingTaggerProvider.cs ├── CODE_OF_CONDUCT.md ├── Classification ├── ClassificationFormat.cs ├── ClassificationType.cs └── VerilogClassifier.cs ├── CodeMap1.dgml ├── CommentHelper └── CommentHelper.cs ├── Completion ├── CompletionController.cs └── CompletionSource.cs ├── CppProperties.json ├── EditorClassifier ├── EditorClassifier1.cs ├── EditorClassifier1ClassificationDefinition.cs ├── EditorClassifier1Format.cs └── EditorClassifier1Provider.cs ├── Example-Projects └── Verilog45 │ ├── Verilog45.sln │ └── Verilog45 │ ├── Makefile │ ├── Makefile-iCEBreaker.mk │ ├── Program.cs │ ├── Verilog45.csproj │ ├── boards │ ├── icebreaker │ │ └── icebreaker.pcf │ └── ulx3s │ │ ├── Makefile-ULX3S-12F.mk │ │ ├── Makefile-ULX3S-45F.mk │ │ └── Makefile-ULX3S-85F.mk │ ├── top.v │ ├── top.ys │ ├── top_icebreaker.v │ └── ulx3s_v20.lpf ├── Extensions └── StringExtensions.cs ├── Globals ├── BufferAttributes.cs ├── OutputWindow.cs ├── Parsing.cs ├── PerfMon.cs ├── VerilogContext.cs ├── VerilogGlobals.cs ├── VerilogHelperFunctions.cs ├── VerilogParseState.cs └── VerilogToken.cs ├── Highlighting ├── HighlightWordFormatDefinition.cs ├── HighlightWordTag.cs ├── HighlightWordTagger.cs └── HighlightWordTaggerProvider.cs ├── Intellisense ├── QuickInfoController.cs ├── QuickInfoControllerProvider.cs └── VerilogQuickInfoSource.cs ├── LICENSE.md ├── LatticeDiscussion.md ├── Lattice_securelyfitz.md ├── Outline ├── CSharpOutliningTagger.cs ├── CSharpOutliningTaggerProvider.cs ├── SnapshotParser.cs └── TextRegion.cs ├── Outlining ├── OutliningTagger.cs └── OutliningTaggerProvider.cs ├── ProjectTemplates └── Verilog Project.zip ├── Properties └── AssemblyInfo.cs ├── README.md ├── RELEASE_NOTES.md ├── Reference_Services ├── Example.ReferenceService.png ├── Overview.xml ├── Reference.Services.Interfaces │ ├── AssemblyInfo.cs │ ├── IMyGlobalService.cs │ ├── IMyLocalService.cs │ ├── Reference.Services.Interfaces.csproj │ └── packages.config ├── Reference.Services.sln └── Reference.Services │ ├── ClientPackage.cs │ ├── GlobalSuppressions.cs │ ├── Guids.cs │ ├── HelperFunctions.cs │ ├── MyGlobalService.cs │ ├── MyLocalService.cs │ ├── PkgCmd.vsct │ ├── PkgCmdId.cs │ ├── Properties │ └── AssemblyInfo.cs │ ├── Reference.Services.csproj │ ├── ServicesPackage.cs │ ├── VSPackage.resx │ ├── packages.config │ └── source.extension.vsixmanifest ├── Tagger ├── BraceMatchingTagger.cs ├── BraceMatchingTaggerProvider.cs ├── OutliningTagger.cs └── OutliningTaggerProvider.cs ├── TestFiles ├── EmptyFile.v ├── JanGray.v ├── StopWatch.v ├── anothertest - Copy.v ├── anothertest.v ├── asterisk_issue_16.v ├── bracketest.v ├── comma.v ├── const.v ├── current_bracket_issue.v ├── debug.log ├── declaration_text.v ├── din _test3.v ├── din_test.v ├── din_test2.v ├── din_test4.v ├── file1.v ├── file2.v ├── issue10.v ├── issue12.v ├── issue16.v ├── issue21.v ├── issue21_mini.v ├── mini_test - Copy.v ├── mini_test.v ├── module_name.v ├── new_test.v ├── otherfile.verilog ├── picorv32.v ├── picorv32.v.txt ├── primitives_test.v ├── test - bigfile.v ├── test.v ├── test2.v ├── testfile-1K.v ├── testfile-4K.v ├── testfile-5K.v ├── vert_bar.v └── wiretest.verilog ├── VerilogCallStackEvents.dgml ├── VerilogLanguage.csproj ├── VerilogLanguage.csproj.user ├── VerilogLanguage.vsct ├── VerilogLanguageExtension.sln ├── VerilogToken ├── VerilogTokenTag.cs ├── VerilogTokenTagProvider.cs ├── VerilogTokenTagger.cs └── VerilogTokenTypes.cs ├── VerilogTokenTag.cs ├── VerilogTokenTypes.cs ├── examples └── ColorfulEditor │ ├── .vs │ └── ColorfulEditor │ │ └── v15 │ │ ├── .suo │ │ └── Server │ │ └── sqlite3 │ │ ├── db.lock │ │ ├── storage.ide │ │ ├── storage.ide-shm │ │ └── storage.ide-wal │ ├── ColorfulEditor.sln │ ├── ColorfulEditor │ ├── Colorful.cs │ ├── ColorfulClassifier.cs │ ├── ColorfulClassifierProvider.cs │ ├── ColorfulCompletionSource.cs │ ├── ColorfulCompletionSourceProvider.cs │ ├── ColorfulEditor.csproj │ ├── ColorfulKeywords.cs │ ├── ColorfulOleCommandTarget.cs │ ├── ColorfulTextViewCreationListener.cs │ ├── ColorfulTokenizer.cs │ ├── License.txt │ ├── Properties │ │ └── AssemblyInfo.cs │ ├── Sample.colorful │ ├── packages.config │ └── source.extension.vsixmanifest │ └── packages │ ├── Microsoft.VSSDK.BuildTools.15.7.104 │ ├── Microsoft.VSSDK.BuildTools.15.7.104.nupkg │ ├── build │ │ ├── Microsoft.VSSDK.BuildTools.props │ │ └── Microsoft.VSSDK.BuildTools.targets │ └── tools │ │ └── vssdk │ │ ├── Microsoft.VisualStudio.ExtensionEngine.dll │ │ ├── Microsoft.VisualStudio.Sdk.BuildTasks.15.0.dll │ │ ├── Microsoft.VisualStudio.Sdk.BuildTasks.dll │ │ ├── Microsoft.VisualStudio.Sdk.Common.targets │ │ ├── Microsoft.VisualStudio.Setup.Common.dll │ │ ├── Microsoft.VisualStudio.Threading.dll │ │ ├── Microsoft.VisualStudio.Validation.dll │ │ ├── Microsoft.VsSDK.Cpp.Overrides.targets │ │ ├── Microsoft.VsSDK.Cpp.targets │ │ ├── Microsoft.VsSDK.targets │ │ ├── Newtonsoft.Json.dll │ │ ├── PkgDefMgmt.dll │ │ ├── ProjectItemsSchema.xml │ │ ├── bin │ │ ├── ConvertCTCToVSCT.pl │ │ ├── CreatePkgDef.exe │ │ ├── CreatePkgDef.exe.config │ │ ├── DebugSamples.dll │ │ ├── Microsoft.VSDebugger.Native.targets │ │ ├── Microsoft.VSDebugger.targets │ │ ├── RegPkg.exe │ │ ├── RegPkg.exe.config │ │ ├── RegRiched20.exe │ │ ├── SetEngineLogMode.cmd │ │ ├── VSCT.exe │ │ ├── VSCTCompress.dll │ │ ├── VSCTLibrary.dll │ │ ├── lib │ │ │ ├── Microsoft.VisualStudio.Shell.Framework.dll │ │ │ └── Microsoft.VisualStudio.Shell.Immutable.10.0.dll │ │ └── vsdconfigtool.exe │ │ ├── inc │ │ ├── AppIDCmdUsed.vsct │ │ ├── EmulatorCmdUsed.vsct │ │ ├── KnownImageIds.vsct │ │ ├── Menus.vsct │ │ ├── MnuHelpIds.h │ │ ├── RazorCmdId.h │ │ ├── RazorCmdUsed.vsct │ │ ├── RazorGuids.h │ │ ├── SharedCmdDef.vsct │ │ ├── SharedCmdPlace.vsct │ │ ├── ShellCmdDef.vsct │ │ ├── ShellCmdPlace.vsct │ │ ├── VsDbgCmd.h │ │ ├── VsDbgCmdPlace.vsct │ │ ├── VsDbgCmdUsed.vsct │ │ ├── editids.h │ │ ├── sccmnid.h │ │ ├── sharedids.h │ │ ├── stdidcmd.h │ │ ├── venusids.h │ │ ├── venusmenu.vsct │ │ ├── virtkeys.h │ │ ├── vsdebugguids.h │ │ ├── vsshlids.h │ │ └── wbids.h │ │ ├── offreg.dll │ │ └── schemas │ │ ├── PackageLanguagePackManifestSchema.xsd │ │ ├── PackageManifestSchema.Assets.xsd │ │ ├── PackageManifestSchema.Dependencies.xsd │ │ ├── PackageManifestSchema.Installation.xsd │ │ ├── PackageManifestSchema.Installer.xsd │ │ ├── PackageManifestSchema.Metadata.xsd │ │ ├── PackageManifestSchema.Prerequisites.xsd │ │ ├── PackageManifestSchema.xsd │ │ └── VSIXManifestSchema.xsd │ ├── Microsoft.VisualStudio.CoreUtility.15.0.26201 │ ├── Microsoft.VisualStudio.CoreUtility.15.0.26201.nupkg │ └── lib │ │ └── net45 │ │ ├── Microsoft.VisualStudio.CoreUtility.dll │ │ └── microsoft.visualstudio.coreutility.xml │ ├── Microsoft.VisualStudio.Text.Data.15.0.26201 │ ├── Microsoft.VisualStudio.Text.Data.15.0.26201.nupkg │ └── lib │ │ └── net45 │ │ ├── Microsoft.VisualStudio.Text.Data.dll │ │ └── microsoft.visualstudio.text.data.xml │ ├── Microsoft.VisualStudio.Text.Logic.15.0.26201 │ ├── Microsoft.VisualStudio.Text.Logic.15.0.26201.nupkg │ └── lib │ │ └── net45 │ │ ├── Microsoft.VisualStudio.Text.Logic.dll │ │ └── microsoft.visualstudio.text.logic.xml │ ├── Microsoft.VisualStudio.Text.UI.15.0.26201 │ ├── Microsoft.VisualStudio.Text.UI.15.0.26201.nupkg │ └── lib │ │ └── net45 │ │ ├── Microsoft.VisualStudio.Text.UI.dll │ │ └── microsoft.visualstudio.text.ui.xml │ └── Microsoft.VisualStudio.Text.UI.Wpf.15.0.26201 │ ├── Microsoft.VisualStudio.Text.UI.Wpf.15.0.26201.nupkg │ └── lib │ └── net45 │ ├── Microsoft.VisualStudio.Text.UI.Wpf.dll │ └── microsoft.visualstudio.text.ui.wpf.xml ├── images ├── CallStackEvents.png ├── CodeMap.png ├── InstallFailed.png ├── Installer14.png ├── KeywordHoverTextExample.png ├── UpdateAvailable.PNG ├── VSIX_installer_open_with.png ├── Verilog-Extension-Disabled.png ├── Verilog-Tools-Options-Colors.png ├── Verilog_New_Project.PNG ├── VisualStudio-Automatic-Extension-Install-RestorePoint.png ├── VisualStudio-Automatic-Extension-Install.png ├── VisualStudio-ExtensionsAndUpdates.png ├── VisualStudio-Installer-Workloads-VSIX.png ├── VisualStudio-Installer.png ├── VisualStudio-Missing-Extension-Development.png ├── VisualStudio2019-Automatic-Extension-References-Not-Found.png ├── VisualStudio2019-F5-Debug-Fail.png ├── art-color-table.png ├── export_template.png ├── vsix_explorer_install.png ├── vsix_install_process.png ├── vsix_open_always.png └── vsix_vs_not_listed.png ├── packages.config ├── releases ├── README.md ├── VerilogLanguage_v0.1.1.vsix ├── VerilogLanguage_v0.1.2.vsix ├── VerilogLanguage_v0.1.4.vsix ├── VerilogLanguage_v0.2.0.vsix ├── VerilogLanguage_v0.2.1.vsix ├── VerilogLanguage_v0.3.0.vsix ├── VerilogLanguage_v0.3.1.vsix ├── VerilogLanguage_v0.3.3.vsix ├── VerilogLanguage_v0.3.4.01.vsix ├── VerilogLanguage_v0.3.4.02.vsix └── VerilogLanguage_v0.3.4.36.vsix └── source.extension.vsixmanifest /.gitignore: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # This .gitignore file was automatically created by Microsoft(R) Visual Studio. 3 | ################################################################################ 4 | 5 | /.vs 6 | /bin 7 | /obj 8 | /packages 9 | /examples/ColorfulEditor/.vs/ColorfulEditor/v16 10 | /examples/ColorfulEditor/ColorfulEditor/bin/Debug 11 | /examples/ColorfulEditor/ColorfulEditor/obj/Release 12 | /examples/ColorfulEditor/ColorfulEditor/obj/Debug 13 | /Reference_Services/Reference.Services/bin/Debug 14 | /Reference_Services/Reference.Services/obj/Debug 15 | /Reference_Services/Reference.Services.Interfaces/bin/Debug 16 | /Reference_Services/Reference.Services.Interfaces/obj/Debug 17 | /Reference_Services/.vs/Reference.Services 18 | /Reference_Services/packages 19 | /TestFiles/.vs 20 | /Reference_Services/Reference.Services.Interfaces/obj/Release 21 | /Reference_Services/Reference.Services/obj/Release/Reference.Services.csprojAssemblyReference.cache 22 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/LiteX/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("$projectname$")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("$registeredorganization$")] 12 | [assembly: AssemblyProduct("$projectname$")] 13 | [assembly: AssemblyCopyright("Copyright © $registeredorganization$ $year$")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("$guid1$")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/LiteX/LiteX.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/AddedExtensionProjectTemplates/LiteX/LiteX.ico -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/LiteX/LiteX.vstemplate: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | LiteX 5 | LiteX 6 | LiteX.ico 7 | CSharp 8 | csharp 9 | 2.0 10 | 1000 11 | ff94b951-990b-4017-934e-7039ad0e75ce 12 | true 13 | LiteX 14 | true 15 | 16 | 17 | 18 | AssemblyInfo.cs 19 | Class1.cs 20 | 21 | 22 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/LiteX/ProjectTemplate.csproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Debug 5 | AnyCPU 6 | 8.0.30703 7 | 2.0 8 | $guid1$ 9 | Library 10 | Properties 11 | $safeprojectname$ 12 | $safeprojectname$ 13 | v$targetframeworkversion$ 14 | 512 15 | 16 | 17 | true 18 | full 19 | false 20 | bin\Debug\ 21 | DEBUG;TRACE 22 | prompt 23 | 4 24 | 25 | 26 | pdbonly 27 | true 28 | bin\Release\ 29 | TRACE 30 | prompt 31 | 4 32 | 33 | 34 | 35 | $if$ ($targetframeworkversion$ >= 3.5) 36 | 37 | 38 | 39 | $endif$ 40 | $if$ ($targetframeworkversion$ >= 4.0) 41 | 42 | $endif$ 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/LiteX/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("LiteX")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("gojimmypi")] 12 | [assembly: AssemblyProduct("LiteX")] 13 | [assembly: AssemblyCopyright("Copyright © gojimmypi 2020")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("6617f99c-dcd6-4487-9b97-0c31b7f22b07")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/ProjectTemplate-LiteX/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("$projectname$")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("$registeredorganization$")] 12 | [assembly: AssemblyProduct("$projectname$")] 13 | [assembly: AssemblyCopyright("Copyright © $registeredorganization$ $year$")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("$guid1$")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/ProjectTemplate-LiteX/ProjectTemplate-LiteX.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/AddedExtensionProjectTemplates/ProjectTemplate-LiteX/ProjectTemplate-LiteX.ico -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/ProjectTemplate-LiteX/ProjectTemplate-LiteX.vstemplate: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | ProjectTemplate-LiteX 5 | ProjectTemplate-LiteX 6 | ProjectTemplate-LiteX.ico 7 | CSharp 8 | csharp 9 | 2.0 10 | 1000 11 | 33b1ec0d-037a-4007-a14b-f399b2bb4720 12 | true 13 | ProjectTemplate-LiteX 14 | true 15 | 16 | 17 | 18 | 19 | build\vs-build.bat 20 | build\vs-clean.bat 21 | build\vs-prog.bat 22 | 23 | 24 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/ProjectTemplate-LiteX/ProjectTemplate.csproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | bin\ 5 | 6 | 7 | bin\ 8 | 9 | 10 | bin\ 11 | 12 | 13 | bin\ 14 | 15 | 16 | bin\ 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 52 | 53 | 54 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/ProjectTemplate-LiteX/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("ProjectTemplate-LiteX")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("gojimmypi")] 12 | [assembly: AssemblyProduct("ProjectTemplate-LiteX")] 13 | [assembly: AssemblyCopyright("Copyright © gojimmypi 2020")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("e6656cd1-0025-448f-8d9d-d9ed5278440c")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/App.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/Makefile-iCEBreaker.mk: -------------------------------------------------------------------------------- 1 | 2 | PROJ := top_icebreaker 3 | PIN_DEF := boards/icebreaker/icebreaker.pcf 4 | DEVICE := up5k 5 | 6 | 7 | all: $(PROJ).rpt $(PROJ).bin 8 | 9 | %.blif: %.v $(ADD_SRC) $(ADD_DEPS) 10 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top $(PROJ) -blif $@' $< $(ADD_SRC) 11 | 12 | %.json: %.v $(ADD_SRC) $(ADD_DEPS) 13 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top $(PROJ) -json $@' $< $(ADD_SRC) 14 | 15 | ifeq ($(USE_ARACHNEPNR),) 16 | %.asc: $(PIN_DEF) %.json 17 | nextpnr-ice40 --$(DEVICE) $(if $(PACKAGE),--package $(PACKAGE)) $(if $(FREQ),--freq $(FREQ)) --json $(filter-out $<,$^) --pcf $< --asc $@ 18 | else 19 | %.asc: $(PIN_DEF) %.blif 20 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) $(if $(PACKAGE),-P $(PACKAGE)) -o $@ -p $^ 21 | endif 22 | 23 | 24 | %.bin: %.asc 25 | icepack $< $@ 26 | 27 | %.rpt: %.asc 28 | icetime $(if $(FREQ),-c $(FREQ)) -d $(DEVICE) -mtr $@ $< 29 | 30 | %_tb: %_tb.v %.v 31 | iverilog -g2012 -o $@ $^ 32 | 33 | %_tb.vcd: %_tb 34 | vvp -N $< +vcd=$@ 35 | 36 | %_syn.v: %.blif 37 | yosys -p 'read_blif -wideports $^; write_verilog $@' 38 | 39 | %_syntb: %_tb.v %_syn.v 40 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 41 | 42 | %_syntb.vcd: %_syntb 43 | vvp -N $< +vcd=$@ 44 | 45 | prog: $(PROJ).bin 46 | /mnt/c/workspace/ulx3s-toolchain/bin/iceprog.exe $< 47 | 48 | sudo-prog: $(PROJ).bin 49 | @echo 'Executing prog as root!!!' 50 | sudo iceprog $< 51 | 52 | clean: 53 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 54 | 55 | .SECONDARY: 56 | .PHONY: all prog clean 57 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/Program.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using System.Threading.Tasks; 6 | 7 | namespace ConsoleApp2 8 | { 9 | class Program 10 | { 11 | static void Main(string[] args) 12 | { 13 | } 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("Verilog.Properties")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("")] 12 | [assembly: AssemblyProduct("Verilog.Properties")] 13 | [assembly: AssemblyCopyright("Copyright © 2020")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("73ca9bd9-0af7-4746-bdb3-d6a9372da3b0")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | [assembly: AssemblyVersion("1.0.0.0")] 33 | [assembly: AssemblyFileVersion("1.0.0.0")] 34 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/Verilog.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/AddedExtensionProjectTemplates/Verilog Project/Verilog.ico -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/Verilog.vstemplate: -------------------------------------------------------------------------------- 1 |  2 | 6 | 7 | 8 | Verilog Project 9 | Project for syntesizing FPGA bitstreams 10 | Verilog.ico 11 | CSharp 12 | Verilog 13 | Verilog 14 | Windows 15 | 100 16 | b021d0f2-465e-4c93-b15d-44d21ac594c4 17 | true 18 | Verilog 19 | Other 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | boards\icebreaker\icebreaker.pcf 32 | boards\icebreaker\main.mk 33 | boards\icebreaker\README.md 34 | 35 | boards\orangecrab\blink.v 36 | boards\orangecrab\Makefile 37 | boards\orangecrab\orangecrab_r0.1.pcf 38 | boards\orangecrab\orangecrab_r0.2.pcf 39 | 40 | boards\tinyfpga_bx\Makefile 41 | boards\tinyfpga_bx\pins.pcf 42 | boards\tinyfpga_bx\TinyFPGA_B.v 43 | 44 | boards\ulx3s\Makefile-ULX3S-12F.mk 45 | boards\ulx3s\Makefile-ULX3S-25F.mk 46 | boards\ulx3s\Makefile-ULX3S-45F.mk 47 | boards\ulx3s\Makefile-ULX3S-85F.mk 48 | boards\ulx3s\ulx3s_v20.lpf 49 | 50 | 51 | 52 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/_not_used_Makefile-ULX3S-12F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/icebreaker/README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | See: https://github.com/icebreaker-fpga/icebreaker-examples -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/icebreaker/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # PMOD 2 47 | set_io -nowarn P2_1 27 48 | set_io -nowarn P2_2 25 49 | set_io -nowarn P2_3 21 50 | set_io -nowarn P2_4 19 51 | set_io -nowarn P2_7 26 52 | set_io -nowarn P2_8 23 53 | set_io -nowarn P2_9 20 54 | set_io -nowarn P2_10 18 55 | 56 | # LEDs and Buttons (PMOD 2) 57 | set_io -nowarn LED1 26 58 | set_io -nowarn LED2 27 59 | set_io -nowarn LED3 25 60 | set_io -nowarn LED4 23 61 | set_io -nowarn LED5 21 62 | set_io -nowarn BTN1 20 63 | set_io -nowarn BTN2 19 64 | set_io -nowarn BTN3 18 65 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/icebreaker/main.mk: -------------------------------------------------------------------------------- 1 | PROJ = top_icebreaker 2 | 3 | all: $(PROJ).rpt $(PROJ).bin 4 | 5 | $(PROJ).json: $(PROJ).v 6 | yosys -ql $(PROJ).yslog -p 'synth_ice40 -top top_icebreaker -json $@' $< 7 | 8 | $(PROJ).asc: $(PROJ).json boards/icebreaker/icebreaker.pcf 9 | nextpnr-ice40 -ql $(PROJ).nplog --up5k --package sg48 --freq 12 --asc $@ --pcf boards/icebreaker/icebreaker.pcf --json $< 10 | 11 | $(PROJ).bin: $(PROJ).asc 12 | icepack $< $@ 13 | 14 | $(PROJ).rpt: $(PROJ).asc 15 | icetime -d up5k -c 12 -mtr $@ $< 16 | 17 | $(PROJ)_tb: $(PROJ)_tb.v $(PROJ).v 18 | iverilog -o $@ $^ 19 | 20 | $(PROJ)_tb.vcd: $(PROJ)_tb 21 | vvp -N $< +vcd=$@ 22 | 23 | $(PROJ)_syn.v: $(PROJ).json 24 | yosys -p 'read_json $^; write_verilog $@' 25 | 26 | $(PROJ)_syntb: $(PROJ)_tb.v $(PROJ)_syn.v 27 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 28 | 29 | $(PROJ)_syntb.vcd: $(PROJ)_syntb 30 | vvp -N $< +vcd=$@ 31 | 32 | prog: $(PROJ).bin 33 | iceprog $< 34 | 35 | sudo-prog: $(PROJ).bin 36 | @echo 'Executing prog as root!!!' 37 | sudo iceprog $< 38 | 39 | clean: 40 | rm -f $(PROJ).yslog $(PROJ).nplog $(PROJ).json $(PROJ).asc $(PROJ).rpt $(PROJ).bin 41 | rm -f $(PROJ)_tb $(PROJ)_tb.vcd $(PROJ)_syn.v $(PROJ)_syntb $(PROJ)_syntb.vcd 42 | 43 | .SECONDARY: 44 | .PHONY: all prog clean -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/orangecrab/Makefile: -------------------------------------------------------------------------------- 1 | PROJ=blink 2 | 3 | # `r0.1` or `r0.2` 4 | VERSION:=r0.2 5 | 6 | all: ${PROJ}.dfu 7 | 8 | dfu: ${PROJ}.dfu 9 | dfu-util -D $< 10 | 11 | 12 | %.json: %.v 13 | yosys -p "synth_ecp5 -json $@" $< 14 | 15 | %_out.config: %.json 16 | nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf orangecrab_${VERSION}.pcf 17 | 18 | %.bit: %_out.config 19 | ecppack --compress --freq 38.8 --input $< --bit $@ 20 | 21 | %.dfu : %.bit 22 | cp $< $@ 23 | dfu-suffix -v 1209 -p 5af0 -a $@ 24 | 25 | clean: 26 | rm -f ${PROJ}.svf ${PROJ}.bit ${PROJ}.config ${PROJ}.json ${PROJ}.dfu 27 | 28 | .PHONY: prog clean 29 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/orangecrab/blink.v: -------------------------------------------------------------------------------- 1 | /* Copyright 2020 Gregory Davill */ 2 | 3 | /* 4 | * Blink a LED on the OrangeCrab using verilog 5 | */ 6 | 7 | module top ( 8 | input CLK, 9 | 10 | output LED1, 11 | output LED2, 12 | output LED3 13 | ); 14 | reg [26:0] counter = 0; 15 | 16 | always @(posedge CLK) begin 17 | counter <= counter + 1; 18 | end 19 | 20 | assign LED1 = ~counter[24]; 21 | assign LED2 = ~counter[25]; 22 | assign LED3 = 1; 23 | 24 | 25 | endmodule -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/orangecrab/orangecrab_r0.1.pcf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "CLK" SITE "A9"; 2 | IOBUF PORT "CLK" IO_TYPE=LVCMOS33; 3 | 4 | LOCATE COMP "LED1" SITE "T17"; 5 | LOCATE COMP "LED2" SITE "V17"; 6 | LOCATE COMP "LED3" SITE "J3"; 7 | 8 | IOBUF PORT "LED1" IO_TYPE=LVCMOS33; 9 | IOBUF PORT "LED2" IO_TYPE=LVCMOS33; 10 | IOBUF PORT "LED3" IO_TYPE=LVCMOS33; -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/orangecrab/orangecrab_r0.2.pcf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "CLK" SITE "A9"; 2 | IOBUF PORT "CLK" IO_TYPE=LVCMOS33; 3 | 4 | LOCATE COMP "LED1" SITE "K4"; 5 | LOCATE COMP "LED2" SITE "M3"; 6 | LOCATE COMP "LED3" SITE "J3"; 7 | 8 | IOBUF PORT "LED1" IO_TYPE=LVCMOS33; 9 | IOBUF PORT "LED2" IO_TYPE=LVCMOS33; 10 | IOBUF PORT "LED3" IO_TYPE=LVCMOS33; -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/tinyfpga_bx/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile 2 | # 3 | # The following license is from the icestorm project and specifically applies to this file only: 4 | # 5 | # Permission to use, copy, modify, and/or distribute this software for any 6 | # purpose with or without fee is hereby granted, provided that the above 7 | # copyright notice and this permission notice appear in all copies. 8 | # 9 | # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 | # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 | # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 | # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 | # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 | # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 | # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 | 17 | PROJ = TinyFPGA_B 18 | 19 | PIN_DEF = pins.pcf 20 | DEVICE = lp8k 21 | 22 | all: $(PROJ).rpt $(PROJ).bin 23 | 24 | %.blif: %.v 25 | yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $< 26 | 27 | %.asc: $(PIN_DEF) %.blif 28 | arachne-pnr -d 8k -P cm81 -o $@ -p $^ 29 | 30 | %.bin: %.asc 31 | icepack $< $@ 32 | 33 | %.rpt: %.asc 34 | icetime -d $(DEVICE) -mtr $@ $< 35 | 36 | %_tb: %_tb.v %.v 37 | iverilog -o $@ $^ 38 | 39 | %_tb.vcd: %_tb 40 | vvp -N $< +vcd=$@ 41 | 42 | %_syn.v: %.blif 43 | yosys -p 'read_blif -wideports $^; write_verilog $@' 44 | 45 | %_syntb: %_tb.v %_syn.v 46 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 47 | 48 | %_syntb.vcd: %_syntb 49 | vvp -N $< +vcd=$@ 50 | 51 | prog: $(PROJ).bin 52 | iceprog $< 53 | 54 | sudo-prog: $(PROJ).bin 55 | @echo 'Executing prog as root!!!' 56 | sudo iceprog $< 57 | 58 | clean: 59 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin 60 | 61 | .SECONDARY: 62 | .PHONY: all prog clean 63 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/tinyfpga_bx/pins.pcf: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Family & Device: iCE40LP8K 3 | # Package: CM81 4 | ############################################################################### 5 | 6 | set_io pin_1 A2 7 | set_io pin_2 A1 8 | set_io pin_3 B1 9 | set_io pin_4 C2 10 | set_io pin_5 C1 11 | set_io pin_6 D2 12 | set_io pin_7 D1 13 | set_io pin_8 E2 14 | set_io pin_9 E1 15 | set_io pin_10 G2 16 | set_io pin_11 H1 17 | set_io pin_12 J1 18 | set_io pin_13 H2 19 | set_io pin_14 H9 20 | set_io pin_15 D9 21 | set_io pin_16 D8 22 | set_io pin_17 C9 23 | set_io pin_18 A9 24 | set_io pin_19 B8 25 | set_io pin_20 A8 26 | set_io pin_21 B7 27 | set_io pin_22 A7 28 | set_io pin_23 B6 29 | set_io pin_24 A6 30 | set_io pin_25 G1 31 | set_io pin_26 J3 32 | set_io pin_27 J4 33 | set_io pin_28 H4 34 | set_io pin_29_miso H7 35 | set_io pin_30_cs F7 36 | set_io pin_31_mosi H5 37 | set_io pin_32_sck G7 38 | set_io pin_33 J8 39 | set_io pin_34 G9 40 | set_io pin_35 J9 41 | set_io pin_36 E8 42 | set_io pin_37 J2 43 | set_io pin_led B3 44 | set_io pin_usbp B4 45 | set_io pin_usbn A4 46 | set_io pin_pu A3 47 | set_io pin_clk B2 48 | 49 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/ulx3s/Makefile-ULX3S-12F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --12k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/ulx3s/Makefile-ULX3S-25F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --25k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/ulx3s/Makefile-ULX3S-45F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --45k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/boards/ulx3s/Makefile-ULX3S-85F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/fujprog/build/fujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/dtest.bat: -------------------------------------------------------------------------------- 1 | echo off 2 | IF EXIST "%windir%\Sysnative\wsl.exe" ( 3 | echo "Using Sysnative\wsl" 4 | ) ELSE ( 5 | IF EXIST "%windir%\System32\wsl.exe" ( 6 | echo "Using System32\wsl" 7 | ) ELSE ( 8 | echo " WSL Not found!" 9 | ) 10 | ) 11 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/images/export_template.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/AddedExtensionProjectTemplates/Verilog Project/images/export_template.png -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/top.v: -------------------------------------------------------------------------------- 1 | module top(input clk_25mhz, 2 | input [6:0] btn, 3 | output [7:0] led, 4 | output wifi_gpio0); 5 | 6 | wire i_clk; 7 | 8 | // Tie GPIO0, keep board from rebooting 9 | assign wifi_gpio0 = 1'b1; 10 | assign i_clk= clk_25mhz; 11 | reg [7:0] o_led; 12 | assign led= o_led; 13 | 14 | localparam ctr_width = 32; 15 | reg [ctr_width-1:0] ctr = 0; 16 | 17 | always @(posedge i_clk) begin 18 | ctr <= ctr + 1; 19 | o_led[7] <= 1; 20 | o_led[6] <= btn[1]; 21 | o_led[5:0] <= ctr[23:18]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/top.ys: -------------------------------------------------------------------------------- 1 | read_verilog top.v 2 | synth_ecp5 -json top.json 3 | -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/top_icebreaker.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // Attach 7 segment display PMOD to Icebreaker PMOD1A port. 4 | 5 | module top_icebreaker( 6 | input CLK, 7 | output P1A1, 8 | output P1A2, 9 | output P1A3, 10 | output P1A4, 11 | output P1A7, 12 | output P1A8, 13 | output P1A9, 14 | output P1A10 15 | ); 16 | 17 | // Wiring external pins. 18 | reg [6:0] seg_pins_n; 19 | reg digit_sel; 20 | assign {P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1} = seg_pins_n; 21 | assign P1A10 = digit_sel; 22 | 23 | // counter increments at CLK = 12 MHz. 24 | // ones digit increments at ~6Hz. 25 | // display refreshes at 375 KHz. 26 | reg [29:0] counter; 27 | wire [3:0] ones = counter[21+:4]; 28 | wire [3:0] tens = counter[25+:4]; 29 | wire [2:0] display_state = counter[2+:3]; 30 | 31 | reg [6:0] ones_segments; 32 | reg [6:0] tens_segments; 33 | 34 | digit_to_segments ones2segs(CLK, ones, ones_segments); 35 | digit_to_segments tens2segs(CLK, tens, tens_segments); 36 | 37 | always @(posedge CLK) begin 38 | counter <= counter + 1; 39 | 40 | // Switch seg_pins_n off during digit_sel transitions 41 | // to prevent flicker. Each digit has 25% duty cycle. 42 | case (display_state) 43 | 0, 1: seg_pins_n <= ~ones_segments; 44 | 2: seg_pins_n <= ~0; 45 | 3: digit_sel <= 0; 46 | 4, 5: seg_pins_n <= ~tens_segments; 47 | 6: seg_pins_n <= ~0; 48 | 7: digit_sel <= 1; 49 | endcase 50 | end 51 | 52 | endmodule // top 53 | 54 | // Get the segments to illuminate to display a single hex digit. 55 | // N.B., This is positive logic. Display needs negative. 56 | module digit_to_segments(input clk, 57 | input [3:0] digit, 58 | output reg[6:0] segments 59 | ); 60 | always @(posedge clk) 61 | case (digit) 62 | 0: segments <= 7'b0111111; 63 | 1: segments <= 7'b0000110; 64 | 2: segments <= 7'b1011011; 65 | 3: segments <= 7'b1001111; 66 | 4: segments <= 7'b1100110; 67 | 5: segments <= 7'b1101101; 68 | 6: segments <= 7'b1111101; 69 | 7: segments <= 7'b0000111; 70 | 8: segments <= 7'b1111111; 71 | 9: segments <= 7'b1101111; 72 | 4'hA: segments <= 7'b1110111; 73 | 4'hB: segments <= 7'b1111100; 74 | 4'hC: segments <= 7'b0111001; 75 | 4'hD: segments <= 7'b1011110; 76 | 4'hE: segments <= 7'b1111001; 77 | 4'hF: segments <= 7'b1110001; 78 | endcase 79 | 80 | endmodule -------------------------------------------------------------------------------- /AddedExtensionProjectTemplates/Verilog Project/ulx3s.ys: -------------------------------------------------------------------------------- 1 | read_verilog top.v 2 | synth_ecp5 -noccu2 -nomux -nodram -json ulx3s.json -------------------------------------------------------------------------------- /BraceMatching/BraceMatchingTaggerProvider.cs: -------------------------------------------------------------------------------- 1 | // adapted from https://github.com/madskristensen/ExtensibilityTools 2 | 3 | using System.ComponentModel.Composition; 4 | using Microsoft.VisualStudio.Text; 5 | using Microsoft.VisualStudio.Text.Editor; 6 | using Microsoft.VisualStudio.Text.Tagging; 7 | using Microsoft.VisualStudio.Utilities; 8 | 9 | namespace VerilogLanguage.BraceMatching 10 | { 11 | [Export(typeof(IViewTaggerProvider))] 12 | [ContentType("verilog")] 13 | [TagType(typeof(TextMarkerTag))] 14 | class BraceMatchingTaggerProvider : IViewTaggerProvider 15 | { 16 | // Step 2: Implement the CreateTagger method to instantiate a BraceMatchingTagger. 17 | public ITagger CreateTagger(ITextView textView, ITextBuffer buffer) where T : ITag 18 | { 19 | if (textView == null) 20 | return null; 21 | 22 | //provide highlighting only on the top-level buffer 23 | if (textView.TextBuffer != buffer) 24 | return null; 25 | 26 | return new BraceMatchingTagger(textView, buffer) as ITagger; 27 | } 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /CppProperties.json: -------------------------------------------------------------------------------- 1 | { 2 | "configurations": [ 3 | { 4 | "inheritEnvironments": [ 5 | "msvc_x86" 6 | ], 7 | "name": "x86-Debug", 8 | "includePath": [ 9 | "${env.INCLUDE}", 10 | "${workspaceRoot}\\**" 11 | ], 12 | "defines": [ 13 | "WIN32", 14 | "_DEBUG", 15 | "UNICODE", 16 | "_UNICODE" 17 | ], 18 | "intelliSenseMode": "windows-msvc-x86" 19 | } 20 | ] 21 | } -------------------------------------------------------------------------------- /EditorClassifier/EditorClassifier1.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using Microsoft.VisualStudio.Text; 4 | using Microsoft.VisualStudio.Text.Classification; 5 | 6 | namespace VerilogLanguage 7 | { 8 | /// 9 | /// Classifier that classifies all text as an instance of the "EditorClassifier1" classification type. 10 | /// 11 | internal class EditorClassifier1 : IClassifier 12 | { 13 | /// 14 | /// Classification type. 15 | /// 16 | private readonly IClassificationType classificationType; 17 | 18 | /// 19 | /// Initializes a new instance of the class. 20 | /// 21 | /// Classification registry. 22 | internal EditorClassifier1(IClassificationTypeRegistryService registry) 23 | { 24 | this.classificationType = registry.GetClassificationType("EditorClassifier1"); 25 | } 26 | 27 | #region IClassifier 28 | 29 | #pragma warning disable 67 30 | 31 | /// 32 | /// An event that occurs when the classification of a span of text has changed. 33 | /// 34 | /// 35 | /// This event gets raised if a non-text change would affect the classification in some way, 36 | /// for example typing /* would cause the classification to change in C# without directly 37 | /// affecting the span. 38 | /// 39 | public event EventHandler ClassificationChanged; 40 | 41 | #pragma warning restore 67 42 | 43 | /// 44 | /// Gets all the objects that intersect with the given range of text. 45 | /// 46 | /// 47 | /// This method scans the given SnapshotSpan for potential matches for this classification. 48 | /// In this instance, it classifies everything and returns each span as a new ClassificationSpan. 49 | /// 50 | /// The span currently being classified. 51 | /// A list of ClassificationSpans that represent spans identified to be of this classification. 52 | public IList GetClassificationSpans(SnapshotSpan span) 53 | { 54 | var result = new List() 55 | { 56 | new ClassificationSpan(new SnapshotSpan(span.Snapshot, new Span(span.Start, span.Length)), this.classificationType) 57 | }; 58 | 59 | return result; 60 | } 61 | 62 | #endregion 63 | } 64 | } 65 | -------------------------------------------------------------------------------- /EditorClassifier/EditorClassifier1ClassificationDefinition.cs: -------------------------------------------------------------------------------- 1 | using System.ComponentModel.Composition; 2 | using Microsoft.VisualStudio.Text.Classification; 3 | using Microsoft.VisualStudio.Utilities; 4 | 5 | namespace VerilogLanguage 6 | { 7 | /// 8 | /// Classification type definition export for EditorClassifier1 9 | /// 10 | internal static class EditorClassifier1ClassificationDefinition 11 | { 12 | // This disables "The field is never used" compiler's warning. Justification: the field is used by MEF. 13 | #pragma warning disable 169 14 | 15 | /// 16 | /// Defines the "EditorClassifier1" classification type. 17 | /// 18 | [Export(typeof(ClassificationTypeDefinition))] 19 | [Name("EditorClassifier1")] 20 | [BaseDefinition("code")] 21 | private static ClassificationTypeDefinition typeDefinition; 22 | 23 | #pragma warning restore 169 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /EditorClassifier/EditorClassifier1Format.cs: -------------------------------------------------------------------------------- 1 | using System.ComponentModel.Composition; 2 | using System.Windows.Media; 3 | using Microsoft.VisualStudio.Text.Classification; 4 | using Microsoft.VisualStudio.Utilities; 5 | 6 | namespace VerilogLanguage 7 | { 8 | /// 9 | /// Defines an editor format for the EditorClassifier1 type that has a purple background 10 | /// and is underlined. 11 | /// 12 | [Export(typeof(EditorFormatDefinition))] 13 | [ClassificationType(ClassificationTypeNames = "EditorClassifier1")] 14 | [Name("EditorClassifier1")] 15 | [UserVisible(true)] // This should be visible to the end user 16 | [Order(Before = Priority.Default)] // Set the priority to be after the default classifiers 17 | internal sealed class EditorClassifier1Format : ClassificationFormatDefinition 18 | { 19 | /// 20 | /// Initializes a new instance of the class. 21 | /// 22 | public EditorClassifier1Format() 23 | { 24 | this.DisplayName = "EditorClassifier1"; // Human readable version of the name 25 | //this.BackgroundColor = Colors.BlueViolet; 26 | //this.TextDecorations = System.Windows.TextDecorations.Underline; 27 | } 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /EditorClassifier/EditorClassifier1Provider.cs: -------------------------------------------------------------------------------- 1 | using System.ComponentModel.Composition; 2 | using Microsoft.VisualStudio.Text; 3 | using Microsoft.VisualStudio.Text.Classification; 4 | using Microsoft.VisualStudio.Utilities; 5 | 6 | namespace VerilogLanguage 7 | { 8 | /// 9 | /// Classifier provider. It adds the classifier to the set of classifiers. 10 | /// 11 | [Export(typeof(IClassifierProvider))] 12 | [ContentType("text")] // This classifier applies to all text files. 13 | internal class EditorClassifier1Provider : IClassifierProvider 14 | { 15 | // Disable "Field is never assigned to..." compiler's warning. Justification: the field is assigned by MEF. 16 | #pragma warning disable 649 17 | 18 | /// 19 | /// Classification registry to be used for getting a reference 20 | /// to the custom classification type later. 21 | /// 22 | [Import] 23 | private IClassificationTypeRegistryService classificationRegistry; 24 | 25 | #pragma warning restore 649 26 | 27 | #region IClassifierProvider 28 | 29 | /// 30 | /// Gets a classifier for the given text buffer. 31 | /// 32 | /// The to classify. 33 | /// A classifier for the text buffer, or null if the provider cannot do so in its current state. 34 | public IClassifier GetClassifier(ITextBuffer buffer) 35 | { 36 | return buffer.Properties.GetOrCreateSingletonProperty(creator: () => new EditorClassifier1(this.classificationRegistry)); 37 | } 38 | 39 | #endregion 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.30128.74 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Verilog45", "Verilog45\Verilog45.csproj", "{C32098DE-768D-4521-8C70-119A087D9407}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|Any CPU = Debug|Any CPU 11 | iCEBreaker Deploy|Any CPU = iCEBreaker Deploy|Any CPU 12 | Release|Any CPU = Release|Any CPU 13 | ULX3S 12F Deploy|Any CPU = ULX3S 12F Deploy|Any CPU 14 | ULX3S 45F Deploy|Any CPU = ULX3S 45F Deploy|Any CPU 15 | ULX3S 85F Deploy|Any CPU = ULX3S 85F Deploy|Any CPU 16 | EndGlobalSection 17 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 18 | {C32098DE-768D-4521-8C70-119A087D9407}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 19 | {C32098DE-768D-4521-8C70-119A087D9407}.Debug|Any CPU.Build.0 = Debug|Any CPU 20 | {C32098DE-768D-4521-8C70-119A087D9407}.iCEBreaker Deploy|Any CPU.ActiveCfg = iCEBreaker Deploy|Any CPU 21 | {C32098DE-768D-4521-8C70-119A087D9407}.iCEBreaker Deploy|Any CPU.Build.0 = iCEBreaker Deploy|Any CPU 22 | {C32098DE-768D-4521-8C70-119A087D9407}.Release|Any CPU.ActiveCfg = Release|Any CPU 23 | {C32098DE-768D-4521-8C70-119A087D9407}.Release|Any CPU.Build.0 = Release|Any CPU 24 | {C32098DE-768D-4521-8C70-119A087D9407}.ULX3S 12F Deploy|Any CPU.ActiveCfg = ULX3S 12F Deploy|Any CPU 25 | {C32098DE-768D-4521-8C70-119A087D9407}.ULX3S 12F Deploy|Any CPU.Build.0 = ULX3S 12F Deploy|Any CPU 26 | {C32098DE-768D-4521-8C70-119A087D9407}.ULX3S 45F Deploy|Any CPU.ActiveCfg = ULX3S 45F Deploy|Any CPU 27 | {C32098DE-768D-4521-8C70-119A087D9407}.ULX3S 45F Deploy|Any CPU.Build.0 = ULX3S 45F Deploy|Any CPU 28 | {C32098DE-768D-4521-8C70-119A087D9407}.ULX3S 85F Deploy|Any CPU.ActiveCfg = ULX3S 85F Deploy|Any CPU 29 | {C32098DE-768D-4521-8C70-119A087D9407}.ULX3S 85F Deploy|Any CPU.Build.0 = ULX3S 85F Deploy|Any CPU 30 | EndGlobalSection 31 | GlobalSection(SolutionProperties) = preSolution 32 | HideSolutionNode = FALSE 33 | EndGlobalSection 34 | GlobalSection(ExtensibilityGlobals) = postSolution 35 | SolutionGuid = {6C8E8D00-D428-4AEA-B233-9E5D7C56185B} 36 | EndGlobalSection 37 | EndGlobal 38 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/Makefile-iCEBreaker.mk: -------------------------------------------------------------------------------- 1 | 2 | PROJ := top_icebreaker 3 | PIN_DEF := boards/icebreaker/icebreaker.pcf 4 | DEVICE := up5k 5 | 6 | 7 | all: $(PROJ).rpt $(PROJ).bin 8 | 9 | %.blif: %.v $(ADD_SRC) $(ADD_DEPS) 10 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top $(PROJ) -blif $@' $< $(ADD_SRC) 11 | 12 | %.json: %.v $(ADD_SRC) $(ADD_DEPS) 13 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top $(PROJ) -json $@' $< $(ADD_SRC) 14 | 15 | ifeq ($(USE_ARACHNEPNR),) 16 | %.asc: $(PIN_DEF) %.json 17 | nextpnr-ice40 --$(DEVICE) $(if $(PACKAGE),--package $(PACKAGE)) $(if $(FREQ),--freq $(FREQ)) --json $(filter-out $<,$^) --pcf $< --asc $@ 18 | else 19 | %.asc: $(PIN_DEF) %.blif 20 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) $(if $(PACKAGE),-P $(PACKAGE)) -o $@ -p $^ 21 | endif 22 | 23 | 24 | %.bin: %.asc 25 | icepack $< $@ 26 | 27 | %.rpt: %.asc 28 | icetime $(if $(FREQ),-c $(FREQ)) -d $(DEVICE) -mtr $@ $< 29 | 30 | %_tb: %_tb.v %.v 31 | iverilog -g2012 -o $@ $^ 32 | 33 | %_tb.vcd: %_tb 34 | vvp -N $< +vcd=$@ 35 | 36 | %_syn.v: %.blif 37 | yosys -p 'read_blif -wideports $^; write_verilog $@' 38 | 39 | %_syntb: %_tb.v %_syn.v 40 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 41 | 42 | %_syntb.vcd: %_syntb 43 | vvp -N $< +vcd=$@ 44 | 45 | prog: $(PROJ).bin 46 | /mnt/c/workspace/ulx3s-toolchain/bin/iceprog.exe $< 47 | 48 | sudo-prog: $(PROJ).bin 49 | @echo 'Executing prog as root!!!' 50 | sudo iceprog $< 51 | 52 | clean: 53 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 54 | 55 | .SECONDARY: 56 | .PHONY: all prog clean 57 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/Program.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using System.Threading.Tasks; 6 | 7 | namespace ConsoleApp2 8 | { 9 | class Program 10 | { 11 | static void Main(string[] args) 12 | { 13 | } 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/boards/icebreaker/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # PMOD 2 47 | set_io -nowarn P2_1 27 48 | set_io -nowarn P2_2 25 49 | set_io -nowarn P2_3 21 50 | set_io -nowarn P2_4 19 51 | set_io -nowarn P2_7 26 52 | set_io -nowarn P2_8 23 53 | set_io -nowarn P2_9 20 54 | set_io -nowarn P2_10 18 55 | 56 | # LEDs and Buttons (PMOD 2) 57 | set_io -nowarn LED1 26 58 | set_io -nowarn LED2 27 59 | set_io -nowarn LED3 25 60 | set_io -nowarn LED4 23 61 | set_io -nowarn LED5 21 62 | set_io -nowarn BTN1 20 63 | set_io -nowarn BTN2 19 64 | set_io -nowarn BTN3 18 65 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/boards/ulx3s/Makefile-ULX3S-12F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/boards/ulx3s/Makefile-ULX3S-45F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/boards/ulx3s/Makefile-ULX3S-85F.mk: -------------------------------------------------------------------------------- 1 | .PHONY: all 2 | .DELETE_ON_ERROR: 3 | TOPMOD := top 4 | VLOGFIL := $(TOPMOD).v 5 | VCDFILE := $(TOPMOD).vcd 6 | SIMPROG := $(TOPMOD)_tb 7 | RPTFILE := $(TOPMOD).rpt 8 | BINFILE := $(TOPMOD).bin 9 | SIMFILE := $(SIMPROG).cpp 10 | VDIRFB := ./obj_dir 11 | #COSIMS := uartsim.cpp 12 | all: $(VCDFILE) 13 | 14 | GCC := g++ 15 | CFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB) 16 | # 17 | # Modern versions of Verilator and C++ may require an -faligned-new flag 18 | # CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB) 19 | 20 | VERILATOR=verilator 21 | VFLAGS := -O3 -MMD --trace -Wall 22 | 23 | ## Find the directory containing the Verilog sources. This is given from 24 | ## calling: "verilator -V" and finding the VERILATOR_ROOT output line from 25 | ## within it. From this VERILATOR_ROOT value, we can find all the components 26 | ## we need here--in particular, the verilator include directory 27 | VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"') 28 | ## 29 | ## The directory containing the verilator includes 30 | VINC := $(VERILATOR_ROOT)/include 31 | 32 | $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 33 | $(VERILATOR) $(VFLAGS) -cc $(VLOGFIL) 34 | 35 | $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp 36 | make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk 37 | 38 | $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS) 39 | $(GCC) $(CFLAGS) $(VINC)/verilated.cpp \ 40 | $(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS) \ 41 | $(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG) 42 | 43 | test: $(VCDFILE) 44 | 45 | $(VCDFILE): $(SIMPROG) 46 | ./$(SIMPROG) 47 | 48 | ## 49 | .PHONY: clean 50 | clean: 51 | rm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) top/ $(BINFILE) $(RPTFILE) 52 | rm -rf top.json ulx3s_out.config ulx3s.bit 53 | 54 | ## 55 | ## Find all of the Verilog dependencies and submodules 56 | ## 57 | DEPS := $(wildcard $(VDIRFB)/*.d) 58 | 59 | ## Include any of these submodules in the Makefile 60 | ## ... but only if we are not building the "clean" target 61 | ## which would (oops) try to build those dependencies again 62 | ## 63 | ifneq ($(MAKECMDGOALS),clean) 64 | ifneq ($(DEPS),) 65 | include $(DEPS) 66 | endif 67 | endif 68 | 69 | 70 | ulx3s.bit: ulx3s_out.config 71 | ecppack ulx3s_out.config ulx3s.bit 72 | 73 | ulx3s_out.config: top.json 74 | nextpnr-ecp5 --85k --json top.json --lpf ulx3s_v20.lpf --textcfg ulx3s_out.config 75 | 76 | top.json: top.ys top.v 77 | yosys top.ys 78 | 79 | prog: ulx3s.bit 80 | /mnt/c/workspace/ulx3s-examples/bin/ujprog.exe ulx3s.bit 81 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/top.v: -------------------------------------------------------------------------------- 1 | module top(input clk_25mhz, 2 | input [6:0] btn, 3 | output [7:0] led, 4 | output wifi_gpio0); 5 | 6 | wire i_clk; 7 | 8 | // Tie GPIO0, keep board from rebooting 9 | assign wifi_gpio0 = 1'b1; 10 | assign i_clk= clk_25mhz; 11 | reg [7:0] o_led; 12 | assign led= o_led; 13 | 14 | localparam ctr_width = 32; 15 | reg [ctr_width-1:0] ctr = 0; 16 | 17 | always @(posedge i_clk) begin 18 | ctr <= ctr + 1; 19 | o_led[7] <= 1; 20 | o_led[6] <= btn[1]; 21 | o_led[5:0] <= ctr[23:18]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/top.ys: -------------------------------------------------------------------------------- 1 | read_verilog top.v 2 | synth_ecp5 -json top.json 3 | -------------------------------------------------------------------------------- /Example-Projects/Verilog45/Verilog45/top_icebreaker.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // Attach 7 segment display PMOD to Icebreaker PMOD1A port. 4 | 5 | module top_icebreaker( 6 | input CLK, 7 | output P1A1, 8 | output P1A2, 9 | output P1A3, 10 | output P1A4, 11 | output P1A7, 12 | output P1A8, 13 | output P1A9, 14 | output P1A10 15 | ); 16 | 17 | // Wiring external pins. 18 | reg [6:0] seg_pins_n; 19 | reg digit_sel; 20 | assign {P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1} = seg_pins_n; 21 | assign P1A10 = digit_sel; 22 | 23 | // counter increments at CLK = 12 MHz. 24 | // ones digit increments at ~6Hz. 25 | // display refreshes at 375 KHz. 26 | reg [29:0] counter; 27 | wire [3:0] ones = counter[21+:4]; 28 | wire [3:0] tens = counter[25+:4]; 29 | wire [2:0] display_state = counter[2+:3]; 30 | 31 | reg [6:0] ones_segments; 32 | reg [6:0] tens_segments; 33 | 34 | digit_to_segments ones2segs(CLK, ones, ones_segments); 35 | digit_to_segments tens2segs(CLK, tens, tens_segments); 36 | 37 | always @(posedge CLK) begin 38 | counter <= counter + 1; 39 | 40 | // Switch seg_pins_n off during digit_sel transitions 41 | // to prevent flicker. Each digit has 25% duty cycle. 42 | case (display_state) 43 | 0, 1: seg_pins_n <= ~ones_segments; 44 | 2: seg_pins_n <= ~0; 45 | 3: digit_sel <= 0; 46 | 4, 5: seg_pins_n <= ~tens_segments; 47 | 6: seg_pins_n <= ~0; 48 | 7: digit_sel <= 1; 49 | endcase 50 | end 51 | 52 | endmodule // top 53 | 54 | // Get the segments to illuminate to display a single hex digit. 55 | // N.B., This is positive logic. Display needs negative. 56 | module digit_to_segments(input clk, 57 | input [3:0] digit, 58 | output reg[6:0] segments 59 | ); 60 | always @(posedge clk) 61 | case (digit) 62 | 0: segments <= 7'b0111111; 63 | 1: segments <= 7'b0000110; 64 | 2: segments <= 7'b1011011; 65 | 3: segments <= 7'b1001111; 66 | 4: segments <= 7'b1100110; 67 | 5: segments <= 7'b1101101; 68 | 6: segments <= 7'b1111101; 69 | 7: segments <= 7'b0000111; 70 | 8: segments <= 7'b1111111; 71 | 9: segments <= 7'b1101111; 72 | 4'hA: segments <= 7'b1110111; 73 | 4'hB: segments <= 7'b1111100; 74 | 4'hC: segments <= 7'b0111001; 75 | 4'hD: segments <= 7'b1011110; 76 | 4'hE: segments <= 7'b1111001; 77 | 4'hF: segments <= 7'b1110001; 78 | endcase 79 | 80 | endmodule -------------------------------------------------------------------------------- /Globals/PerfMon.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using System.Threading.Tasks; 6 | 7 | namespace VerilogLanguage 8 | { 9 | public static partial class VerilogGlobals 10 | { 11 | 12 | public static class PerfMon 13 | { 14 | public static int VerilogTokenTag_Count = 0; 15 | public static int VerilogTokenTagger_Count = 0; 16 | public static int CommandFilter_QueryStatus_Count = 0; 17 | public static int VerilogTokenTagger_IsOpenBlockComment_Count = 0; 18 | 19 | private static void init() 20 | { 21 | } 22 | } 23 | 24 | } 25 | 26 | } 27 | -------------------------------------------------------------------------------- /Globals/VerilogContext.cs: -------------------------------------------------------------------------------- 1 |  2 | using System; 3 | using System.Collections.Generic; 4 | using System.Linq; 5 | using System.Text; 6 | using System.Threading.Tasks; 7 | namespace VerilogLanguage 8 | { 9 | public static partial class VerilogGlobals 10 | { 11 | public enum VerilogTokenContextType 12 | { 13 | Undetermined, 14 | DoubleQuoteOpen, 15 | SquareBracketOpen, 16 | SquareBracketClose, 17 | SquareBracketContents, 18 | RoundBracketOpen, 19 | RoundBracketClose, 20 | RoundBracketContents, 21 | SquigglyBracketOpen, 22 | SquigglyBracketClose, 23 | SquigglyBracketContents, 24 | AlwaysAt, 25 | Comment, 26 | Text 27 | } 28 | 29 | /// 30 | /// VerilogTokenContextType - given a string, determine if is this a bracket or regular text 31 | /// 32 | /// 33 | /// 34 | private static VerilogTokenContextType VerilogTokenContextFromString(string s) 35 | { 36 | switch (s) 37 | { 38 | case null: 39 | return VerilogTokenContextType.Undetermined; // short circuit exit 40 | 41 | case "": // nothing to do for empty string 42 | case "\t": // nor tabs 43 | return VerilogTokenContextType.Text; // short circuit exit to avoid string operation 44 | 45 | default: 46 | switch (s.Substring(0, 1)) // given the first chart of the string, determine the context 47 | { 48 | case "[": 49 | return VerilogTokenContextType.SquareBracketOpen; 50 | 51 | case "]": 52 | return VerilogTokenContextType.SquareBracketClose; 53 | 54 | case "(": 55 | return VerilogTokenContextType.RoundBracketOpen; 56 | 57 | case ")": 58 | return VerilogTokenContextType.RoundBracketClose; 59 | 60 | case "{": 61 | return VerilogTokenContextType.SquigglyBracketOpen; 62 | 63 | case "}": 64 | return VerilogTokenContextType.SquigglyBracketClose; 65 | 66 | case "@": 67 | return VerilogTokenContextType.AlwaysAt; 68 | 69 | default: 70 | return VerilogTokenContextType.Text; 71 | 72 | } 73 | } 74 | } 75 | 76 | } // partial class VerilogGlobals 77 | } 78 | -------------------------------------------------------------------------------- /Highlighting/HighlightWordFormatDefinition.cs: -------------------------------------------------------------------------------- 1 | using System.ComponentModel.Composition; 2 | using Microsoft.VisualStudio.Text.Classification; 3 | using Microsoft.VisualStudio.Utilities; 4 | using System.Windows.Media; 5 | 6 | // Code based on Walkthrough: Highlighting Text 7 | // See: https://docs.microsoft.com/en-us/visualstudio/extensibility/walkthrough-highlighting-text?view=vs-2015 8 | 9 | namespace VerilogLanguage.Highlighting 10 | { 11 | // Step #5: Create a second class that inherits from MarkerFormatDefinition, 12 | // and name it HighlightWordFormatDefinition. In order to use this format definition for your tag, 13 | // you must export it with the following attributes: 14 | // 15 | // NameAttribute: tags use this to reference this format 16 | // UserVisibleAttribute: this causes the format to appear in the UI 17 | 18 | [Export(typeof(EditorFormatDefinition))] 19 | [Name("MarkerFormatDefinition/HighlightWordFormatDefinition")] 20 | [UserVisible(true)] 21 | internal class HighlightWordFormatDefinition : MarkerFormatDefinition 22 | { 23 | // the single word higlight that occurs when typing. called once at Visual Studio launch time. 24 | // this controls the color of all selected words in the document. 25 | // currently commented out to use the default Visual Studio colorization 26 | public HighlightWordFormatDefinition() 27 | { 28 | // this.ForegroundColor = Colors.DarkBlue; 29 | // this.DisplayName = "Highlight Word"; 30 | // this.ZOrder = 5; 31 | } 32 | } 33 | 34 | } 35 | -------------------------------------------------------------------------------- /Highlighting/HighlightWordTag.cs: -------------------------------------------------------------------------------- 1 | using Microsoft.VisualStudio.Text.Tagging; 2 | 3 | // Code based on Walkthrough: Highlighting Text 4 | // See: https://docs.microsoft.com/en-us/visualstudio/extensibility/walkthrough-highlighting-text?view=vs-2015 5 | 6 | namespace VerilogLanguage.Highlighting 7 | { 8 | // Step #4: Create a class that inherits from TextMarkerTag and name it HighlightWordTag 9 | internal class HighlightWordTag : TextMarkerTag 10 | { 11 | public HighlightWordTag() : base("MarkerFormatDefinition/HighlightWordFormatDefinition") { 12 | // 13 | } 14 | } 15 | 16 | 17 | } 18 | -------------------------------------------------------------------------------- /Highlighting/HighlightWordTaggerProvider.cs: -------------------------------------------------------------------------------- 1 | using System.ComponentModel.Composition; 2 | using Microsoft.VisualStudio.Text; 3 | using Microsoft.VisualStudio.Text.Editor; 4 | using Microsoft.VisualStudio.Text.Operations; 5 | using Microsoft.VisualStudio.Text.Tagging; 6 | using Microsoft.VisualStudio.Utilities; 7 | 8 | // Code based on Walkthrough: Highlighting Text 9 | // See: https://docs.microsoft.com/en-us/visualstudio/extensibility/walkthrough-highlighting-text?view=vs-2015 10 | 11 | 12 | namespace VerilogLanguage.Highlighting 13 | { 14 | // Creating a Tagger Provider 15 | 16 | // Create a class named HighlightWordTaggerProvider that implements IViewTaggerProvider, 17 | // and export it with a ContentTypeAttribute of "text" and a TagTypeAttribute of TextMarkerTag. 18 | [Export(typeof(IViewTaggerProvider))] 19 | [ContentType("verilog")] 20 | [TagType(typeof(TextMarkerTag))] 21 | internal class HighlightWordTaggerProvider : IViewTaggerProvider 22 | { 23 | // Step 2: You must import two editor services, the ITextSearchService and the ITextStructureNavigatorSelectorService, to instantiate the tagger. 24 | [Import] 25 | internal ITextSearchService TextSearchService { get; set; } 26 | 27 | [Import] 28 | internal ITextStructureNavigatorSelectorService TextStructureNavigatorSelector { get; set; } 29 | // Step 3: Implement the CreateTagger method to return an instance of HighlightWordTagger. 30 | public ITagger CreateTagger(ITextView textView, ITextBuffer buffer) where T : ITag 31 | { 32 | //provide highlighting only on the top buffer  33 | if (textView.TextBuffer != buffer) 34 | return null; 35 | 36 | string thisFile = VerilogLanguage.VerilogGlobals.GetDocumentPath(textView.TextSnapshot); 37 | 38 | // TODO - do we really want to reparse here?? 39 | // this appears to be the only place called when first opening a file. (?) 40 | // 41 | // keywords: onload initialize startup 42 | // 43 | VerilogGlobals.ParseStatusController.Init(thisFile); 44 | 45 | //lock (VerilogGlobals.ParseStatus[thisFile]) 46 | //{ 47 | // // VerilogGlobals.NeedReparse = true; 48 | // VerilogGlobals.ParseStatus[thisFile].NeedReparse = true; 49 | //} 50 | // VerilogGlobals.ParseStatus_NeedReparse_SetValue(thisFile, true); 51 | VerilogGlobals.ParseStatusController.NeedReparse_SetValue(thisFile, true); 52 | 53 | VerilogGlobals.Reparse(buffer,thisFile); // parse the buffer at file load time 54 | 55 | ITextStructureNavigator textStructureNavigator = 56 | TextStructureNavigatorSelector.GetTextStructureNavigator(buffer); 57 | 58 | return new HighlightWordTagger(textView, buffer, TextSearchService, textStructureNavigator) as ITagger; 59 | } 60 | } 61 | } 62 | -------------------------------------------------------------------------------- /Intellisense/QuickInfoControllerProvider.cs: -------------------------------------------------------------------------------- 1 | //*************************************************************************** 2 | // 3 | // Copyright (c) Microsoft Corporation. All rights reserved. 4 | // This code is licensed under the Visual Studio SDK license terms. 5 | // THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | // ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | // IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | // PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | // 10 | //*************************************************************************** 11 | 12 | using System.Collections.Generic; 13 | using System.ComponentModel.Composition; 14 | using Microsoft.VisualStudio.Language.Intellisense; 15 | using Microsoft.VisualStudio.Text; 16 | using Microsoft.VisualStudio.Text.Editor; 17 | using Microsoft.VisualStudio.Utilities; 18 | using VerilogLanguage; 19 | 20 | namespace VSLTK.Intellisense 21 | { 22 | #region IIntellisenseControllerProvider 23 | 24 | [Export(typeof(IIntellisenseControllerProvider))] 25 | [Name("Template QuickInfo Controller")] 26 | [ContentType("verilog")] 27 | internal class TemplateQuickInfoControllerProvider : IIntellisenseControllerProvider 28 | { 29 | #region Asset Imports 30 | 31 | [Import] 32 | internal IQuickInfoBroker QuickInfoBroker { get; set; } 33 | 34 | #endregion 35 | 36 | #region IIntellisenseControllerFactory Members 37 | 38 | public IIntellisenseController TryCreateIntellisenseController(ITextView textView, 39 | IList subjectBuffers) 40 | { 41 | VerilogGlobals.TheView = textView; 42 | return new TemplateQuickInfoController(textView, subjectBuffers, this); 43 | } 44 | 45 | #endregion 46 | 47 | } 48 | 49 | #endregion 50 | } -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 gojimmypi 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /Outline/CSharpOutliningTaggerProvider.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using Microsoft.VisualStudio.Utilities; 6 | using Microsoft.VisualStudio.Text.Tagging; 7 | using System.ComponentModel.Composition; 8 | using Microsoft.VisualStudio.Text; 9 | using Microsoft.VisualStudio.Text.Classification; 10 | using Microsoft.VisualStudio.Text.Projection; 11 | using Microsoft.VisualStudio.Text.Editor; 12 | 13 | 14 | namespace CSharpOutline 15 | { 16 | [Export(typeof(ITaggerProvider))] 17 | [TagType(typeof(IOutliningRegionTag))] 18 | [ContentType("CSharp")] 19 | [ContentType("Razor.C#")] 20 | internal sealed class CSOutliningTaggerProvider : ITaggerProvider 21 | { 22 | [Import] 23 | IClassifierAggregatorService classifierAggregator = null; 24 | [Import] 25 | IEditorOptionsFactoryService factory = null; 26 | 27 | public ITagger CreateTagger(ITextBuffer buffer) where T : ITag 28 | { 29 | //no outlining for projection buffers 30 | if (buffer is IProjectionBuffer) return null; 31 | 32 | IClassifier classifier = classifierAggregator.GetClassifier(buffer); 33 | IEditorOptions editorOptions = factory.GetOptions(buffer); 34 | //var spans = c.GetClassificationSpans(new SnapshotSpan(buffer.CurrentSnapshot, 0, buffer.CurrentSnapshot.Length)); 35 | //create a single tagger for each buffer. 36 | 37 | return buffer.Properties.GetOrCreateSingletonProperty>(() => new CSharpOutliningTagger(buffer, classifier, editorOptions) as ITagger); 38 | } 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /Outline/SnapshotParser.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using Microsoft.VisualStudio.Text; 6 | using Microsoft.VisualStudio.Text.Classification; 7 | 8 | namespace CSharpOutline 9 | { 10 | /// 11 | /// sequential parser for ITextSnapshot 12 | /// 13 | class SnapshotParser 14 | { 15 | private ITextSnapshot Snapshot; 16 | public SnapshotPoint CurrentPoint { get; private set; } 17 | //public ITextSnapshotLine CurrentLine { get { return CurrentPoint.GetContainingLine(); } } 18 | //classifier 19 | private IClassifier Classifier; 20 | private IList ClassificationSpans; 21 | /// 22 | /// A dictionary (span start => span) 23 | /// 24 | private Dictionary SpanIndex = new Dictionary(); 25 | 26 | public ClassificationSpan CurrentSpan {get; private set;} 27 | 28 | public SnapshotParser(ITextSnapshot snapshot, IClassifier classifier) 29 | { 30 | Snapshot = snapshot; 31 | Classifier = classifier; 32 | ClassificationSpans = Classifier.GetClassificationSpans(new SnapshotSpan(Snapshot, 0, snapshot.Length)); 33 | foreach (ClassificationSpan s in ClassificationSpans) 34 | SpanIndex.Add(s.Span.Start.Position, s); 35 | 36 | CurrentPoint = Snapshot.GetLineFromLineNumber(0).Start; 37 | if (SpanIndex.ContainsKey(0)) 38 | CurrentSpan = SpanIndex[0]; 39 | } 40 | 41 | /// 42 | /// Moves forward by one char or one classification span 43 | /// 44 | /// true, if moved 45 | public bool MoveNext() 46 | { 47 | if (!AtEnd()) 48 | { 49 | CurrentPoint = CurrentSpan != null ? CurrentSpan.Span.End : CurrentPoint + 1; 50 | 51 | if (SpanIndex.ContainsKey(CurrentPoint.Position)) 52 | CurrentSpan = SpanIndex[CurrentPoint.Position]; 53 | else 54 | CurrentSpan = null; 55 | return true; 56 | } 57 | return false; 58 | } 59 | 60 | public bool AtEnd() 61 | { 62 | return CurrentPoint.Position >= Snapshot.Length; 63 | } 64 | 65 | /*public string PeekString(int chars) 66 | { 67 | string currentText = CurrentLine.GetText(); 68 | int startIndex = CurrentPoint - CurrentLine.Start; 69 | 70 | if (startIndex >= currentText.Length) return ""; 71 | if (startIndex + chars < currentText.Length) 72 | return currentText.Substring(startIndex, chars); 73 | else 74 | return currentText.Substring(startIndex); 75 | }*/ 76 | } 77 | } 78 | -------------------------------------------------------------------------------- /Outlining/OutliningTaggerProvider.cs: -------------------------------------------------------------------------------- 1 | using System; 2 | using System.Collections.Generic; 3 | using System.Linq; 4 | using System.Text; 5 | using System.ComponentModel.Composition; 6 | using Microsoft.VisualStudio.Text.Outlining; 7 | using Microsoft.VisualStudio.Text.Tagging; 8 | using Microsoft.VisualStudio.Utilities; 9 | using Microsoft.VisualStudio.Text; 10 | 11 | namespace VerilogLanguage.Outlining 12 | { 13 | // this is code is based on the Walkthrough: Outlining (Implementing a Tagger Provider) 14 | // See: https://docs.microsoft.com/en-us/visualstudio/extensibility/walkthrough-outlining?view=vs-2015 15 | 16 | // You must export a tagger provider for your tagger. The tagger provider creates an OutliningTagger 17 | // for a buffer of the "verilog" content type, or else returns an OutliningTagger if the buffer already has one. 18 | 19 | // Step #1: Create a class named OutliningTaggerProvider that implements ITaggerProvider, 20 | // and export it with the ContentType and TagType attributes. 21 | [Export(typeof(ITaggerProvider))] 22 | [TagType(typeof(IOutliningRegionTag))] 23 | [ContentType("verilog")] 24 | internal sealed class OutliningTaggerProvider : ITaggerProvider 25 | { 26 | // Step #2: Implement the CreateTagger method by adding an OutliningTagger to the properties of the buffer. 27 | public ITagger CreateTagger(ITextBuffer buffer) where T : ITag 28 | { 29 | //create a single tagger for each buffer. 30 | Func> sc = delegate () { return new OutliningTagger(buffer) as ITagger; }; 31 | return buffer.Properties.GetOrCreateSingletonProperty>(sc); 32 | } 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /ProjectTemplates/Verilog Project.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/ProjectTemplates/Verilog Project.zip -------------------------------------------------------------------------------- /Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | //*************************************************************************** 2 | // 3 | // Copyright (c) Microsoft Corporation. All rights reserved. 4 | // This code is licensed under the Visual Studio SDK license terms. 5 | // THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | // ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | // IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | // PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | // 10 | //*************************************************************************** 11 | 12 | using System.Reflection; 13 | using System.Runtime.CompilerServices; 14 | using System.Runtime.InteropServices; 15 | 16 | // General Information about an assembly is controlled through the following 17 | // set of attributes. Change these attribute values to modify the information 18 | // associated with an assembly. 19 | [assembly: AssemblyTitle("VerilogLanguage")] 20 | [assembly: AssemblyDescription("Visual Studio Extension for FPGA Verilog Syntax Highlighting")] 21 | [assembly: AssemblyConfiguration("")] 22 | [assembly: AssemblyCompany("gojimmypi")] 23 | [assembly: AssemblyProduct("VerilogLanguage")] 24 | [assembly: AssemblyCopyright("Copyright © gojimmypi")] 25 | [assembly: AssemblyTrademark("gojimmypi")] 26 | [assembly: AssemblyCulture("")] 27 | 28 | // Setting ComVisible to false makes the types in this assembly not visible 29 | // to COM components. If you need to access a type in this assembly from 30 | // COM, set the ComVisible attribute to true on that type. 31 | [assembly: ComVisible(false)] 32 | 33 | // Version information for an assembly consists of the following four values: 34 | // 35 | // Major Version 36 | // Minor Version 37 | // Build Number 38 | // Revision 39 | // 40 | // You can specify all the values or you can default the Build and Revision Numbers 41 | // by using the '*' as shown below: 42 | // [assembly: AssemblyVersion("1.0.*")] 43 | [assembly: AssemblyVersion("0.3.4.36")] // next release will be "0.3.5.*" 44 | // commented the next line per https://stackoverflow.com/questions/356543/can-i-automatically-increment-the-file-build-version-when-using-visual-studio 45 | //[assembly: AssemblyFileVersion("0.3.3.*")] 46 | [assembly: Guid("8E6636E9-EDBC-432F-BA96-85A8AE62D178")] 47 | 48 | -------------------------------------------------------------------------------- /RELEASE_NOTES.md: -------------------------------------------------------------------------------- 1 | # Verilog Language Extension Release Notes 2 | 3 | -------------------------------------------------------------------------------- /Reference_Services/Example.ReferenceService.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/Reference_Services/Example.ReferenceService.png -------------------------------------------------------------------------------- /Reference_Services/Reference.Services.Interfaces/AssemblyInfo.cs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/Reference_Services/Reference.Services.Interfaces/AssemblyInfo.cs -------------------------------------------------------------------------------- /Reference_Services/Reference.Services.Interfaces/IMyGlobalService.cs: -------------------------------------------------------------------------------- 1 | /*************************************************************************** 2 | 3 | Copyright (c) Microsoft Corporation. All rights reserved. 4 | This code is licensed under the Visual Studio SDK license terms. 5 | THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | 10 | ***************************************************************************/ 11 | 12 | using System; 13 | using System.Runtime.InteropServices; 14 | 15 | namespace Microsoft.Samples.VisualStudio.Services.Interfaces 16 | { 17 | /// 18 | /// This is the interface that will be implemented by the global service exposed 19 | /// by the package defined in Reference.Services. 20 | /// Notice that we have to define this interface as COM visible so that 21 | /// it will be possible to query for it from the native version of IServiceProvider. 22 | /// 23 | [Guid("ba9fe7a3-e216-424e-87f9-dee001228d03")] 24 | [ComVisible(true)] 25 | public interface IMyGlobalService 26 | { 27 | void GlobalServiceFunction(); 28 | int CallLocalService(); 29 | } 30 | 31 | /// 32 | /// The goal of this interface is actually just to define a Type (or Guid from the native 33 | /// client's point of view) that will be used to identify the service. 34 | /// In theory, we could use the interface defined above, but it is a good practice to always 35 | /// define a new type as the service's identifier because a service can expose different interfaces. 36 | /// 37 | [Guid("fafafdfb-60f3-47e4-b38c-1bae05b44240")] 38 | public interface SMyGlobalService 39 | { 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services.Interfaces/IMyLocalService.cs: -------------------------------------------------------------------------------- 1 | /*************************************************************************** 2 | 3 | Copyright (c) Microsoft Corporation. All rights reserved. 4 | This code is licensed under the Visual Studio SDK license terms. 5 | THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | 10 | ***************************************************************************/ 11 | 12 | using System; 13 | using System.Runtime.InteropServices; 14 | 15 | namespace Microsoft.Samples.VisualStudio.Services.Interfaces 16 | { 17 | /// 18 | /// This is the interface implemented by the local service. 19 | /// Notice that we have to define this interface as COM visible so that 20 | /// it will be possible to query for it from the native version of IServiceProvider. 21 | /// 22 | [Guid("04079195-ce4d-4683-aec3-e2f2be23b934")] 23 | [ComVisible(true)] 24 | public interface IMyLocalService 25 | { 26 | int LocalServiceFunction(); 27 | } 28 | 29 | /// 30 | /// This interface is used to define the Type or Guid that identifies the service. 31 | /// It is not strictly required because our service will implement only one interface, 32 | /// but in case of services that implement multiple interfaces it is good practice to define 33 | /// a different type to identify the service itself. 34 | /// 35 | [Guid("ed840427-1df8-4d3a-85eb-38847fba93f4")] 36 | public interface SMyLocalService 37 | { 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services.Interfaces/packages.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio 15 4 | VisualStudioVersion = 15.0.26403.7 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Solution Items", "Solution Items", "{ACEAC5F0-12BD-4517-BCD8-599149C3E864}" 7 | ProjectSection(SolutionItems) = preProject 8 | Overview.xml = Overview.xml 9 | Services.jpg = Services.jpg 10 | EndProjectSection 11 | EndProject 12 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Reference.Services", "Reference.Services\Reference.Services.csproj", "{8C8961FC-C381-46DD-AC05-4A1F56E27CA8}" 13 | EndProject 14 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Reference.Services.Interfaces", "Reference.Services.Interfaces\Reference.Services.Interfaces.csproj", "{1EB3810E-0CA2-4A7B-A9CD-A74388E2ABA9}" 15 | EndProject 16 | Global 17 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 18 | Debug|Any CPU = Debug|Any CPU 19 | Release|Any CPU = Release|Any CPU 20 | EndGlobalSection 21 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 22 | {8C8961FC-C381-46DD-AC05-4A1F56E27CA8}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 23 | {8C8961FC-C381-46DD-AC05-4A1F56E27CA8}.Debug|Any CPU.Build.0 = Debug|Any CPU 24 | {8C8961FC-C381-46DD-AC05-4A1F56E27CA8}.Release|Any CPU.ActiveCfg = Release|Any CPU 25 | {8C8961FC-C381-46DD-AC05-4A1F56E27CA8}.Release|Any CPU.Build.0 = Release|Any CPU 26 | {1EB3810E-0CA2-4A7B-A9CD-A74388E2ABA9}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 27 | {1EB3810E-0CA2-4A7B-A9CD-A74388E2ABA9}.Debug|Any CPU.Build.0 = Debug|Any CPU 28 | {1EB3810E-0CA2-4A7B-A9CD-A74388E2ABA9}.Release|Any CPU.ActiveCfg = Release|Any CPU 29 | {1EB3810E-0CA2-4A7B-A9CD-A74388E2ABA9}.Release|Any CPU.Build.0 = Release|Any CPU 30 | EndGlobalSection 31 | GlobalSection(SolutionProperties) = preSolution 32 | HideSolutionNode = FALSE 33 | EndGlobalSection 34 | EndGlobal 35 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/GlobalSuppressions.cs: -------------------------------------------------------------------------------- 1 | /*************************************************************************** 2 | 3 | Copyright (c) Microsoft Corporation. All rights reserved. 4 | THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 5 | ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 6 | IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 7 | PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 8 | 9 | ***************************************************************************/ 10 | [assembly: System.Diagnostics.CodeAnalysis.SuppressMessage("Microsoft.Design", "CA2210:AssembliesShouldHaveValidStrongNames")] 11 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/Guids.cs: -------------------------------------------------------------------------------- 1 | /*************************************************************************** 2 | 3 | Copyright (c) Microsoft Corporation. All rights reserved. 4 | This code is licensed under the Visual Studio SDK license terms. 5 | THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | 10 | ***************************************************************************/ 11 | 12 | using System; 13 | 14 | namespace Microsoft.Samples.VisualStudio.Services 15 | { 16 | /// 17 | /// This class is used only to expose the list of Guids used by this package. 18 | /// This list of guids must match the set of Guids used inside the VSCT file. 19 | /// 20 | internal static class GuidsList 21 | { 22 | public const string guidClientPkgString = "DF3ED918-375F-45B2-BAC0-2C31A0A8DA57"; 23 | public const string guidClientCmdSetString = "36A0B180-F23F-4D96-A1A0-5928B6F7497D"; 24 | 25 | public const string guidSevicesPkgString = "d695001c-f46a-407b-a1c9-54c35ef8ce87"; 26 | 27 | // Now define the list of guids as public static members. 28 | [System.Diagnostics.CodeAnalysis.SuppressMessage("Microsoft.Performance", "CA1823:AvoidUnusedPrivateFields")] 29 | public static readonly Guid guidClientPkg = new Guid(guidClientPkgString); 30 | public static readonly Guid guidClientCmdSet = new Guid(guidClientCmdSetString); 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/MyLocalService.cs: -------------------------------------------------------------------------------- 1 | /*************************************************************************** 2 | 3 | Copyright (c) Microsoft Corporation. All rights reserved. 4 | This code is licensed under the Visual Studio SDK license terms. 5 | THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | 10 | ***************************************************************************/ 11 | 12 | using System; 13 | using System.Diagnostics; 14 | using Microsoft.VisualStudio.Shell; 15 | using Microsoft.VisualStudio.Shell.Interop; 16 | using Microsoft.Samples.VisualStudio.Services.Interfaces; 17 | 18 | namespace Microsoft.Samples.VisualStudio.Services 19 | { 20 | /// 21 | /// This is the class that implements the local service. It implements IMyLocalService 22 | /// because this is the interface that we want to use, but it also implements the empty 23 | /// interface SMyLocalService in order to notify the service creator that it actually 24 | /// implements this service. 25 | /// 26 | public class MyLocalService : IMyLocalService, SMyLocalService 27 | { 28 | // Store a reference to the service provider that will be used to access the shell's services 29 | private IServiceProvider provider; 30 | /// 31 | /// Public constructor of this service. This will use a reference to a service provider to 32 | /// access the services provided by the shell. 33 | /// 34 | public MyLocalService(IServiceProvider sp) 35 | { 36 | Debug.WriteLine("Constructing a new instance of MyLocalService"); 37 | provider = sp; 38 | } 39 | #region IMyLocalService Members 40 | [System.Diagnostics.CodeAnalysis.SuppressMessage("Microsoft.Globalization", "CA1303:DoNotPassLiteralsAsLocalizedParameters", MessageId = "Microsoft.Samples.VisualStudio.Services.HelperFunctions.WriteOnOutputWindow(System.IServiceProvider,System.String)")] 41 | public int LocalServiceFunction() 42 | { 43 | string outputText = " ======================================\n" + 44 | "\tLocalServiceFunction called.\n" + 45 | " ======================================\n"; 46 | HelperFunctions.WriteOnOutputWindow(provider, outputText); 47 | return 0; 48 | } 49 | #endregion 50 | } 51 | } 52 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/PkgCmdId.cs: -------------------------------------------------------------------------------- 1 | /*************************************************************************** 2 | 3 | Copyright (c) Microsoft Corporation. All rights reserved. 4 | This code is licensed under the Visual Studio SDK license terms. 5 | THIS CODE IS PROVIDED *AS IS* WITHOUT WARRANTY OF 6 | ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING ANY 7 | IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR 8 | PURPOSE, MERCHANTABILITY, OR NON-INFRINGEMENT. 9 | 10 | ***************************************************************************/ 11 | 12 | using System; 13 | 14 | namespace Microsoft.Samples.VisualStudio.Services 15 | { 16 | /// 17 | /// This class is used to expose the list of the IDs of the commands implemented 18 | /// by the client package. This list of IDs must match the set of IDs defined inside the 19 | /// Buttons section of the VSCT file. 20 | /// 21 | static class ClientPkgCmdIDList 22 | { 23 | // Define the list a set of public static members. 24 | public const int cmdidClientGetGlobalService = 0x2001; 25 | public const int cmdidClientGetLocalService = 0x2002; 26 | public const int cmdidClientGetLocalUsingGlobal = 0x2003; 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/Reference_Services/Reference.Services/Properties/AssemblyInfo.cs -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/ServicesPackage.cs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/Reference_Services/Reference.Services/ServicesPackage.cs -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/packages.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /Reference_Services/Reference.Services/source.extension.vsixmanifest: -------------------------------------------------------------------------------- 1 |  2 | 11 | 12 | 13 | 14 | 15 | VSSDK reference services CSharp sample 16 | VSSDK Reference services C# sample. Adds three menu buttons to the 'Tools' menu 17 | Resources\Product.ico 18 | ..\Services.jpg 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Tagger/BraceMatchingTaggerProvider.cs: -------------------------------------------------------------------------------- 1 | // adapted from https://github.com/madskristensen/ExtensibilityTools 2 | 3 | using System.ComponentModel.Composition; 4 | using Microsoft.VisualStudio.Text; 5 | using Microsoft.VisualStudio.Text.Editor; 6 | using Microsoft.VisualStudio.Text.Tagging; 7 | using Microsoft.VisualStudio.Utilities; 8 | 9 | namespace VerilogLanguage.BraceMatching 10 | { 11 | [Export(typeof(IViewTaggerProvider))] 12 | [ContentType("verilog")] 13 | [TagType(typeof(TextMarkerTag))] 14 | class BraceMatchingTaggerProvider : IViewTaggerProvider 15 | { 16 | // Step 2: Implement the CreateTagger method to instantiate a BraceMatchingTagger. 17 | public ITagger CreateTagger(ITextView textView, ITextBuffer buffer) where T : ITag 18 | { 19 | if (textView == null) 20 | return null; 21 | 22 | //provide highlighting only on the top-level buffer 23 | if (textView.TextBuffer != buffer) 24 | return null; 25 | 26 | return new BraceMatchingTagger(textView, buffer) as ITagger; 27 | } 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /Tagger/OutliningTaggerProvider.cs: -------------------------------------------------------------------------------- 1 | // adapted from https://github.com/madskristensen/ExtensibilityTools 2 | 3 | using System.ComponentModel.Composition; 4 | using Microsoft.VisualStudio.Text; 5 | using Microsoft.VisualStudio.Text.Tagging; 6 | using Microsoft.VisualStudio.Utilities; 7 | 8 | namespace VerilogLanguage 9 | { 10 | [Export(typeof(ITaggerProvider))] 11 | [TagType(typeof(IOutliningRegionTag))] 12 | [ContentType("verilog")] 13 | internal sealed class OutliningTaggerProvider : ITaggerProvider 14 | { 15 | public ITagger CreateTagger(ITextBuffer buffer) where T : ITag 16 | { 17 | //if (!ExtensibilityToolsPackage.Options.PkgdefEnableOutlining) 18 | // return null; 19 | 20 | return buffer.Properties.GetOrCreateSingletonProperty(() => new OutliningTagger(buffer)) as ITagger; 21 | } 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /TestFiles/EmptyFile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/TestFiles/EmptyFile.v -------------------------------------------------------------------------------- /TestFiles/JanGray.v: -------------------------------------------------------------------------------- 1 | // see https://twitter.com/jangray/status/1158094604681396225?s=20 2 | 3 | logic q = 0; 4 | always_ff @(posedge clk) q <= ~q; // 0 1 0 1 0 1 ... 5 | wire inv_q = ~q; // 1 0 1 0 1 0 ... 6 | logic oops = ~q; // 1 1 1 1 1 1 ... 7 | 8 | It's new to SV. V doesn't have 'logic'. 9 | 10 | 11 | 12 | Requires semantic analysis. 13 | logic ok = 0; // OK constant 0 14 | logic also_ok = ~ok; // OK constant 1 15 | 16 | logic ok2 = 0; // OK, initially 0 17 | always ... ok2 = ...; // subsequently changes 18 | logic oops = ~ok2; // surprise, it's a constant 1, highlight this 19 | -------------------------------------------------------------------------------- /TestFiles/asterisk_issue_16.v: -------------------------------------------------------------------------------- 1 | module picorv32 #( 2 | parameter [ 0:0] ENABLE_IRQ = 0 3 | ) 4 | 5 | localparam rf = 4/ENABLE_IRQ /* */ 6 | wire a = rf*4; 7 | 8 | // see also file: issue16.v 9 | 10 | 11 | -------------------------------------------------------------------------------- /TestFiles/bracketest.v: -------------------------------------------------------------------------------- 1 | [][] 2 | module ulx3s_passthru_wifi 3 | output wire [7:0] led, 4 | input wire [6:0] btn, 5 | input wire [1:4] sw, 6 | 7 | -------------------------------------------------------------------------------- /TestFiles/comma.v: -------------------------------------------------------------------------------- 1 | // after 2 | 3 | module my_din ( 4 | 5 | input [7:0] din 6 | ); 7 | localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; 8 | input clk; 9 | LATCHED_IRQ = 0; 10 | output reg trap, 11 | 12 | input clk2, clk4; 13 | output trapdd; 14 | endmodule 15 | 16 | // add32.v verilog 32 bit adder (Verilog 2001 style) 17 | module adder(input [31:0] a); // carry-out 18 | parameter d=2; 19 | localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; 20 | localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS; 21 | 22 | localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; 23 | input [35:0] TRACE_IRQ3; = {4'b 1000, 32'b 0}; 24 | 25 | endmodule // adder -------------------------------------------------------------------------------- /TestFiles/const.v: -------------------------------------------------------------------------------- 1 | module my_din( 2 | // parameter [31:0] MASKED_IRQ = 32'h0000_0000, 3 | parameter [31:0] LATCHED_IRQ = 32'h 0001_0000, 4 | input test 5 | ) 6 | din == 0 ; 7 | parameter [31:0] LATCHED_IRQ2 = 32'h fff4_ffff; 8 | LATCHED_IRQ = 1; 9 | endmodule -------------------------------------------------------------------------------- /TestFiles/current_bracket_issue.v: -------------------------------------------------------------------------------- 1 | module ulx3s_passthru_wifi( 2 | input wire [1:1] k2, k3; 3 | input wire [1:1] kh1, 4 | wire [1:0] S_prog_in; 5 | ) 6 | kh1 7 | ulx3s_passthru_wifi(); 8 | wire [1:0] S_prog_ins; 9 | -------------------------------------------------------------------------------- /TestFiles/debug.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/TestFiles/debug.log -------------------------------------------------------------------------------- /TestFiles/declaration_text.v: -------------------------------------------------------------------------------- 1 | // sample from https://stackoverflow.com/questions/2341824/syntax-for-using-an-array-of-wires-as-input 2 | 3 | // 8-bit wire ports: 4 | module wow(); 5 | output wire [7:0] r, 6 | input wire [7:0] x, 7 | input wire [7:0] y 8 | 9 | // 1-bit wide by 8-bit deep wire arrays 10 | wire rbit [7:0]; 11 | wire onebit [7:0]; 12 | wire twocomp [7:0]; 13 | 14 | // wire declarations 15 | wire [7:0] rbit; 16 | wire [7:0] onebit; 17 | wire [7:0] twocomp; 18 | endmodule 19 | -------------------------------------------------------------------------------- /TestFiles/din _test3.v: -------------------------------------------------------------------------------- 1 | module my_din( 2 | parameter [31:0] MASKED_IRQ = 32'H 0000_0000, 3 | parameter [5:5] WOWWOW = 32'o ff, 4 | parameter [6:6] WOWWOWw = 32'b ff, 5 | output reg [31:0] mem_addr, 6 | parameter [31:0] LATCHED_IR, 7 | wire mywire, 8 | input test 9 | ) 10 | reg a,b; 11 | wire go = |{a, b}; input clk, resetn, 12 | output reg trap, 13 | localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; 14 | localparam integer irq_timer = 0; 15 | localparam integer irq_ebreak = 1; 16 | parameter integer irq_buserror = 2; 17 | din == 0 ; 18 | parameter [31:0] LATCHED_IRQ2 = 32'h fff4_ffff; 19 | parameter [31:0] LATCHED_IRQ3 = 32'h fff4_ffff; 20 | LATCHED_IRQ = 1; 21 | endmodule 22 | 23 | module myff_din ( 24 | parameter [31:0] MASKED_IRQz = 32'h0000_0000, 25 | parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff; 26 | input [7:0] din 27 | ); 28 | din[7:0] == 0; 29 | din =1; 30 | LATCHED_IRQ = 1; 31 | endmodule 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /TestFiles/din_test.v: -------------------------------------------------------------------------------- 1 | module my_din ( 2 | input [7:0] din 3 | ); 4 | din[7:0] == 0; 5 | din=1; 6 | endmodule 7 | -------------------------------------------------------------------------------- /TestFiles/din_test2.v: -------------------------------------------------------------------------------- 1 | module my_din ( 2 | input [7:0] din 3 | ); 4 | 5 | din[7:0] == 0; 6 | din = 1; 7 | endmodule 8 | -------------------------------------------------------------------------------- /TestFiles/din_test4.v: -------------------------------------------------------------------------------- 1 | // before 2 | module my_din ( 3 | parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, 4 | parameter [31:0] LATCHED_IRQ2 = 32'hffff_ffff, 5 | localparam [31:0] LATCHED_IRQ4 = 32'hffff_ffff, 6 | 7 | 8 | localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; 9 | 10 | //input [7:0] dinx, 11 | input [7:0] din 12 | ); 13 | reg a,b; 14 | wire go = |{a, b}; 15 | input clk; 16 | LATCHED_IRQ = 0; 17 | input clk2, 18 | output trapdd, 19 | endmodule -------------------------------------------------------------------------------- /TestFiles/file1.v: -------------------------------------------------------------------------------- 1 | module picorv32 #( 2 | parameter [0:0] ENABLE_COUNTERS = 1, // this text tis red due to trailing comma 3 | ) 4 | parameter [ 0:0] ENABLE_COUNTERS2 = 1; 5 | 6 | -------------------------------------------------------------------------------- /TestFiles/file2.v: -------------------------------------------------------------------------------- 1 | wire [5:5] var2; 2 | var1; // this is file 2 3 | var3; [] 4 | This is a (()) 5 | wow this is cool. 6 | [[[[]]]] 7 | -------------------------------------------------------------------------------- /TestFiles/issue10.v: -------------------------------------------------------------------------------- 1 | input wire d1; 2 | 3 | module wow( 4 | input wire a 5 | ); 6 | 7 | parameter d1 = 24; 8 | localparam ctr_max = 2**(ctr_width) - 1; // TODO these are not actually valid in module declaration 9 | a = a + 1; 10 | endmodule 11 | 12 | module wow2( 13 | input wire a2 14 | ); 15 | 16 | parameter d1 = 24; 17 | localparam ctr_max = 2**(ctr_width) - 1; // TODO these are not actually valid in module declaration 18 | localparam f5 = 5; 19 | parameter f6 = ctr_width + 4 + 7; 20 | a = a + 1; 21 | endmodule 22 | 23 | // BCD (Binary Coded Decimal) counter 24 | module bcd8_increment ( 25 | input [7:0] din, 26 | output reg [7:0] unsigned dout 27 | ); 28 | localparam ctr_width = 24; 29 | localparam d1 = 5; 30 | parameter d = 45; 31 | d = d + 1; 32 | always @* begin 33 | case (1'b1) 34 | din[7:0] == 8'h 99: 35 | dout = 0; 36 | din[3:0] == 4'h 9: 37 | dout = {din[7:4] + 4'd 1, 4'h 0}; 38 | default: 39 | dout = {din[7:4], din[3:0] + 4'd 1}; 40 | endcase 41 | end 42 | d = d + 1; 43 | din = 5; 44 | endmodule 45 | -------------------------------------------------------------------------------- /TestFiles/issue12.v: -------------------------------------------------------------------------------- 1 | /// after 2 | 3 | module test(wire cl) 4 | wire abc; 5 | wire unsigned xyz; 6 | wire signed xyzzy; 7 | endmodule 8 | -------------------------------------------------------------------------------- /TestFiles/issue16.v: -------------------------------------------------------------------------------- 1 | module picorv32 #( 2 | parameter [ 0:0] ENABLE_IRQ = 0 3 | ) 4 | 5 | localparam rf = 4/ENABLE_IRQ /* */ 6 | wire a = rf*4; 7 | -------------------------------------------------------------------------------- /TestFiles/issue21.v: -------------------------------------------------------------------------------- 1 | // from picorv32.v line 531 2 | module demo( 3 | localparam [31:0] LATCHED_IRQ5 = 32'hffff_0000; 4 | ) 5 | reg [31:0] mem_rdata_q; 6 | wire [31:0] mem_rdata_latched = 32'hffff_ffff ; 7 | localparam [31:0] LATCHED_IRQ5 = 32'hffff_ffff, 8 | assign S_prog_out = S_prog_in == 2'b10 ? 2'b01 : S_prog_in == 2'b01 ? 2'b10 : 2'b11; 9 | case (mem_rdata_latched[15:13]) 10 | 3'b110: begin // C.SWSP 11 | // issue #21 - mem_rdata_latched should be colorized in next line (note space after single quote fixes) 12 | {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4 'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; 13 | mem_rdata_q[14:12] <= 3'b 010; 14 | end 15 | reg a = mem_rdata_latched; 16 | 17 | endmodule -------------------------------------------------------------------------------- /TestFiles/issue21_mini.v: -------------------------------------------------------------------------------- 1 | module demo( 2 | inout v = 8 'h f_05, 3 | inout a = 8'h f_05, 4 | inout b = 8 'hf_05, 5 | inout c = 8 'h f_05, 6 | inout bb = 3 7 | ) 8 | v = 1; 9 | endmodule 10 | -------------------------------------------------------------------------------- /TestFiles/mini_test - Copy.v: -------------------------------------------------------------------------------- 1 | /* 2 | R_progn[(7)]; 3 | input [7:0] J2_AD_PORT; 4 | assign[1:1 5 | other leds leds 6 | ]; 7 | */ 8 | assign 9 | assign 10 | 11 | this is text 12 | 13 | R_progn[(7)]; 14 | input [7:0] J2_AD_PORT; 15 | assign[1:1 16 | other leds leds 17 | ]; 18 | */ 19 | assign 20 | assign 21 | /* 22 | this is text 23 | */ 24 | /* 25 | R_progn[(7)]; 26 | input [7:0] J2_AD_PORT; 27 | assign[1:1 28 | other leds leds 29 | ]; 30 | */ 31 | assign 32 | assign 33 | /* 34 | this is text 35 | */ 36 | /* 37 | R_progn[(7)]; 38 | input [7:0] J2_AD_PORT; 39 | assign[1:1 40 | other leds leds 41 | ]; 42 | */ 43 | assign 44 | assign 45 | /* 46 | this is text 47 | */ 48 | /* 49 | R_progn[(7)]; 50 | input [7:0] J2_AD_PORT; 51 | assign[1:1 52 | other leds leds 53 | ]; 54 | */ 55 | assign 56 | assign 57 | /* 58 | this is text 59 | */ 60 | /* 61 | R_progn[(7)]; 62 | input [7:0] J2_AD_PORT; 63 | assign[1:1 64 | other leds leds 65 | ]; 66 | */ 67 | assign 68 | assign 69 | /* 70 | this is text 71 | */ 72 | /* 73 | R_progn[(7)]; 74 | input [7:0] J2_AD_PORT; 75 | assign[1:1 76 | other leds leds 77 | ]; 78 | */ 79 | assign 80 | assign 81 | /* 82 | this is text 83 | */ 84 | /* 85 | R_progn[(7)]; 86 | input [7:0] J2_AD_PORT; 87 | assign[1:1 88 | other leds leds 89 | ]; 90 | */ 91 | assign 92 | assign 93 | /* 94 | this is text 95 | */ 96 | -------------------------------------------------------------------------------- /TestFiles/mini_test.v: -------------------------------------------------------------------------------- 1 | // Listing 1.1 2 | module eq1 3 | // I/O ports 4 | ( 5 | input wire k1, h1, i1, 6 | output wire eq 7 | ); 8 | 9 | // signal declaration 10 | wire p02, p1; 11 | 12 | // body 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | // product terms 16 | assign p0 = ~k1 & ~i1; 17 | assign p1 = i0 & i1; 18 | [] 19 | [] 20 | // this is a tes 21 | wire er3; 22 | wire k1; 23 | // test 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /TestFiles/module_name.v: -------------------------------------------------------------------------------- 1 | // After 2 | 3 | module other2( 4 | reg clk); 5 | 6 | wire a; 7 | endmodule 8 | 9 | module top(reg clk); 10 | other2 myOther(clk); 11 | myOther 12 | endmodule 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /TestFiles/new_test.v: -------------------------------------------------------------------------------- 1 | input wire [1:1] k1, h1 2 | -------------------------------------------------------------------------------- /TestFiles/otherfile.verilog: -------------------------------------------------------------------------------- 1 | assign -------------------------------------------------------------------------------- /TestFiles/primitives_test.v: -------------------------------------------------------------------------------- 1 | // Listing 1.1 2 | module eq1 3 | // I/O ports 4 | ( 5 | input wire k1, h1, i1, 6 | output wire eq 7 | ); 8 | and 9 | nand 10 | or 11 | not nor xor 12 | xnor 13 | 14 | other text xnornot tandor 15 | 16 | // signal declaration 17 | wire p02, p1; 18 | p02 = p02 and p1; 19 | 20 | 21 | 22 | 23 | // body 24 | // sum of two product terms 25 | assign eq = p0 | p1; 26 | // product terms 27 | assign p0 = ~k1 & ~i1; 28 | assign p1 = i0 & i1; 29 | [] 30 | [] 31 | // this is a tes 32 | wire er3; 33 | wire k1; 34 | // test 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /TestFiles/test2.v: -------------------------------------------------------------------------------- 1 | // Listing 1.1 2 | module global 3 | // I/O ports 4 | ( 5 | input wire k1, h1, i1, 6 | output wire eq 7 | ); 8 | 9 | // signal declaration 10 | wire p02, p1; 11 | 12 | // body 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | // product terms 16 | assign p0 = ~ i0 & ~i1; 17 | assign p1 = i0 & i1; 18 | 19 | endmodule 20 | 21 | module global2 22 | // I/O ports 23 | ( 24 | input wire k1, h1, i1, 25 | output wire eq 26 | ); 27 | 28 | // signal declaration 29 | wire p02, p1; 30 | 31 | // body 32 | // sum of two product terms 33 | assign eq = p0 | p1; 34 | // product terms 35 | assign p0 = ~ i0 & ~i1; 36 | assign p1 = i0 & i1; 37 | 38 | endmodule -------------------------------------------------------------------------------- /TestFiles/testfile-1K.v: -------------------------------------------------------------------------------- 1 | // Listing 1.1 2 | module eq1 3 | // I/O ports 4 | ( 5 | input wire k1, h1, i1, 6 | output wire eq 7 | ); 8 | 9 | // signal declaration 10 | wire p02, p1; 11 | 12 | // body 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | // product terms 16 | assign p0 = ~k1 & ~i1; 17 | assign p1 = i0 & i1; 18 | [] 19 | [] 20 | // this is a tes 21 | wire er3; 22 | wire k1; 23 | // test 24 | the5k; 25 | endmodule 26 | -------------------------------------------------------------------------------- /TestFiles/testfile-5K.v: -------------------------------------------------------------------------------- 1 | // Listing 1.1 2 | module eq1 3 | // I/O ports 4 | ( 5 | input wire k1, h1, i1, 6 | output wire eq 7 | ); 8 | 9 | // signal declaration 10 | wire p02, p1; 11 | 12 | // body 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | // product terms 16 | assign p0 = ~k1 & ~i1; 17 | assign p1 = i0 & i1; 18 | [] 19 | [] 20 | // this is a tes 21 | wire er3; 22 | wire k1; 23 | // test 24 | 25 | endmodule 26 | // Listing 1.1 27 | module eq1 28 | // I/O ports 29 | ( 30 | input wire k1, h1, i1, 31 | output wire eq 32 | ); 33 | 34 | // signal declaration 35 | wire p02, p1; 36 | 37 | // body 38 | // sum of two product terms 39 | assign eq = p0 | p1; 40 | // product terms 41 | assign p0 = ~k1 & ~i1; 42 | assign p1 = i0 & i1; 43 | [] 44 | [] 45 | // this is a tes 46 | wire er3; 47 | wire k1; 48 | // test 49 | 50 | endmodule 51 | // Listing 1.1 52 | module eq1 53 | // I/O ports 54 | ( 55 | input wire k1, h1, i1, 56 | output wire eq 57 | ); 58 | 59 | // signal declaration 60 | wire p02, p1; 61 | 62 | // body 63 | // sum of two product terms 64 | assign eq = p0 | p1; 65 | // product terms 66 | assign p0 = ~k1 & ~i1; 67 | assign p1 = i0 & i1; 68 | [] 69 | [] 70 | // this is a tes 71 | wire er3; 72 | wire k1; 73 | // test 74 | 75 | endmodule 76 | // Listing 1.1 77 | module eq1 78 | // I/O ports 79 | ( 80 | input wire k1, h1, i1, 81 | output wire eq 82 | ); 83 | 84 | // signal declaration 85 | wire p02, p1; 86 | wire the5k; // 87 | // body 88 | // sum of two product terms 89 | assign eq = p0 | p1; 90 | this is a test; 91 | // this is a test 92 | wow this /* is a comment */ [[[]]] 93 | // product terms 94 | assign p0 = ~k1 & ~i1; 95 | assign p1 = i0 & i1; 96 | [] 97 | [] 98 | // this is a tes 99 | wire er3; 100 | wire k1; 101 | // test 102 | 103 | endmodule 104 | // Listing 1.1 105 | module eq1 106 | // I/O ports 107 | ( 108 | input wire k1, h1, i1, 109 | output wire eq 110 | ); 111 | 112 | // signal declaration 113 | wire p02, p1; 114 | 115 | // body 116 | // sum of two product terms 117 | assign eq = p0 | p1; 118 | // product terms 119 | assign p0 = ~k1 & ~i1; 120 | assign p1 = i0 & i1; 121 | [] 122 | [] 123 | // this is a tes 124 | wire er3; 125 | wire k1; 126 | // test 127 | 128 | endmodule 129 | -------------------------------------------------------------------------------- /TestFiles/vert_bar.v: -------------------------------------------------------------------------------- 1 | module my_din( 2 | input test 3 | ) 4 | reg a = | 1; 5 | reg b; 6 | reg [0:0] goa = {a, b}; 7 | 8 | input clk, resetn, 9 | 10 | endmodule 11 | 12 | module myff_din ( 13 | input test 14 | ); 15 | LATCHED_IRQ = 1; 16 | endmodule 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /TestFiles/wiretest.verilog: -------------------------------------------------------------------------------- 1 | // 8-bit wire ports: 2 | output wire [7:0] r, 3 | input wire [7:0] x, 4 | input wire [7:0] y 5 | 6 | // 1-bit wide by 8-bit deep wire arrays 7 | wire rbit [7:0]; 8 | wire onebit [7:0]; 9 | wire twocomp [7:0]; 10 | 11 | // wire declarations 12 | wire [7:0] rbit; 13 | wire [7:0] onebit; 14 | wire [7:0] twocomp; -------------------------------------------------------------------------------- /VerilogLanguage.csproj.user: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | ShowAllFiles 5 | 6 | -------------------------------------------------------------------------------- /VerilogLanguage.vsct: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | 8 | 9 | TestMenu 10 | TestMenu 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /VerilogLanguageExtension.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.30011.22 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "VerilogLanguage", "VerilogLanguage.csproj", "{F091221E-FD10-41A7-AAC4-C9359178BDB1}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|Any CPU = Debug|Any CPU 11 | Release|Any CPU = Release|Any CPU 12 | EndGlobalSection 13 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 14 | {F091221E-FD10-41A7-AAC4-C9359178BDB1}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 15 | {F091221E-FD10-41A7-AAC4-C9359178BDB1}.Debug|Any CPU.Build.0 = Debug|Any CPU 16 | {F091221E-FD10-41A7-AAC4-C9359178BDB1}.Release|Any CPU.ActiveCfg = Release|Any CPU 17 | {F091221E-FD10-41A7-AAC4-C9359178BDB1}.Release|Any CPU.Build.0 = Release|Any CPU 18 | EndGlobalSection 19 | GlobalSection(SolutionProperties) = preSolution 20 | HideSolutionNode = FALSE 21 | EndGlobalSection 22 | GlobalSection(ExtensibilityGlobals) = postSolution 23 | SolutionGuid = {63A107C7-D336-4F68-AA9B-67E8459AFFC0} 24 | EndGlobalSection 25 | EndGlobal 26 | -------------------------------------------------------------------------------- /VerilogToken/VerilogTokenTag.cs: -------------------------------------------------------------------------------- 1 | //*************************************************************************** 2 | // 3 | // MIT License 4 | // 5 | // Copyright(c) 2019 gojimmypi 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in all 15 | // copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //*************************************************************************** 26 | 27 | namespace VerilogLanguage.VerilogToken 28 | { 29 | using System; 30 | using System.Collections.Generic; 31 | using System.ComponentModel.Composition; 32 | using Microsoft.VisualStudio.Text; 33 | using Microsoft.VisualStudio.Text.Classification; 34 | using Microsoft.VisualStudio.Text.Editor; 35 | using Microsoft.VisualStudio.Text.Tagging; 36 | using Microsoft.VisualStudio.Utilities; 37 | using CommentHelper; 38 | 39 | 40 | public class VerilogTokenTag : ITag 41 | { 42 | public VerilogTokenTypes type { get; private set; } 43 | 44 | public VerilogTokenTag(VerilogTokenTypes type) 45 | { 46 | VerilogGlobals.PerfMon.VerilogTokenTag_Count++; 47 | this.type = type; 48 | } 49 | } 50 | 51 | } 52 | -------------------------------------------------------------------------------- /VerilogTokenTag.cs: -------------------------------------------------------------------------------- 1 | // moved to directory. this file saves for ease of history browsing only -------------------------------------------------------------------------------- /VerilogTokenTypes.cs: -------------------------------------------------------------------------------- 1 | // moved to directory. this file saves for ease of history browsing only -------------------------------------------------------------------------------- /examples/ColorfulEditor/.vs/ColorfulEditor/v15/.suo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/.vs/ColorfulEditor/v15/.suo -------------------------------------------------------------------------------- /examples/ColorfulEditor/.vs/ColorfulEditor/v15/Server/sqlite3/db.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/.vs/ColorfulEditor/v15/Server/sqlite3/db.lock -------------------------------------------------------------------------------- /examples/ColorfulEditor/.vs/ColorfulEditor/v15/Server/sqlite3/storage.ide-shm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/.vs/ColorfulEditor/v15/Server/sqlite3/storage.ide-shm -------------------------------------------------------------------------------- /examples/ColorfulEditor/.vs/ColorfulEditor/v15/Server/sqlite3/storage.ide-wal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/.vs/ColorfulEditor/v15/Server/sqlite3/storage.ide-wal -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio 15 4 | VisualStudioVersion = 15.0.27703.2000 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "ColorfulEditor", "ColorfulEditor\ColorfulEditor.csproj", "{C1DF3D1C-DAA8-4E71-A27A-1DDAB57161E7}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|Any CPU = Debug|Any CPU 11 | Release|Any CPU = Release|Any CPU 12 | EndGlobalSection 13 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 14 | {C1DF3D1C-DAA8-4E71-A27A-1DDAB57161E7}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 15 | {C1DF3D1C-DAA8-4E71-A27A-1DDAB57161E7}.Debug|Any CPU.Build.0 = Debug|Any CPU 16 | {C1DF3D1C-DAA8-4E71-A27A-1DDAB57161E7}.Release|Any CPU.ActiveCfg = Release|Any CPU 17 | {C1DF3D1C-DAA8-4E71-A27A-1DDAB57161E7}.Release|Any CPU.Build.0 = Release|Any CPU 18 | EndGlobalSection 19 | GlobalSection(SolutionProperties) = preSolution 20 | HideSolutionNode = FALSE 21 | EndGlobalSection 22 | GlobalSection(ExtensibilityGlobals) = postSolution 23 | SolutionGuid = {05A5861B-E06E-4823-9509-E813982E7E33} 24 | EndGlobalSection 25 | EndGlobal 26 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/Colorful.cs: -------------------------------------------------------------------------------- 1 | // Copyright © 2018 Transeric Solutions. All rights reserved. 2 | // Author: Eric David Lynch 3 | // License: https://www.codeproject.com/info/cpol10.aspx 4 | using System.ComponentModel.Composition; 5 | using Microsoft.VisualStudio.Utilities; 6 | 7 | namespace ColorfulEditor 8 | { 9 | /// 10 | /// A class to associate the ".colorful" file extension with the content type definition 11 | /// for the "Colorful" language. 12 | /// 13 | internal static class Colorful 14 | { 15 | #region Constants 16 | /// 17 | /// The name of the content type for the "Colorful" language. 18 | /// 19 | internal const string ContentType = nameof(Colorful); 20 | 21 | /// 22 | /// The file extension for files containing the "Colorful" language. 23 | /// 24 | internal const string FileExtension = ".colorful"; 25 | #endregion // Constants 26 | 27 | #region Managed Extensibility Framework (MEF) Fields 28 | /// 29 | /// The content type definition for the "Colorful" language, which is based on 30 | /// the pre-defined Visual Studio content type "code". 31 | /// 32 | [Export] 33 | [Name(ContentType)] 34 | [BaseDefinition("code")] 35 | internal static ContentTypeDefinition ContentTypeDefinition = null; 36 | 37 | /// 38 | /// The mapping of the ".colorful" file extension to the content type definition for the "Colorful" language. 39 | /// 40 | [Export] 41 | [Name(ContentType + nameof(FileExtensionToContentTypeDefinition))] 42 | [ContentType(ContentType)] 43 | [FileExtension(FileExtension)] 44 | internal static FileExtensionToContentTypeDefinition FileExtensionToContentTypeDefinition = null; 45 | #endregion // Managed Extensibility Framework (MEF) Fields 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/ColorfulClassifierProvider.cs: -------------------------------------------------------------------------------- 1 | // Copyright © 2018 Transeric Solutions. All rights reserved. 2 | // Author: Eric David Lynch 3 | // License: https://www.codeproject.com/info/cpol10.aspx 4 | using System.ComponentModel.Composition; 5 | using Microsoft.VisualStudio.Language.StandardClassification; 6 | using Microsoft.VisualStudio.Text; 7 | using Microsoft.VisualStudio.Text.Classification; 8 | using Microsoft.VisualStudio.Utilities; 9 | 10 | namespace ColorfulEditor 11 | { 12 | /// 13 | /// A factory for for the content type . 14 | /// 15 | [Export(typeof(IClassifierProvider))] 16 | [Name(nameof(ColorfulClassifierProvider))] 17 | [ContentType(Colorful.ContentType)] 18 | internal sealed class ColorfulClassifierProvider : IClassifierProvider 19 | { 20 | #region Managed Extensibility Framework (MEF) Fields 21 | // Import a registry of classifications types 22 | [Import] 23 | private IClassificationTypeRegistryService classificationRegistry = null; 24 | 25 | // Import the standard classification types 26 | [Import] 27 | private IStandardClassificationService classifications = null; 28 | #endregion // Managed Extensibility Framework (MEF) Fields 29 | 30 | #region Public methods 31 | /// 32 | /// Gets a classifier for the specified text buffer. 33 | /// 34 | /// The to classify. 35 | /// A classifier for the text buffer, or null if the provider cannot do so in its current state. 36 | public IClassifier GetClassifier(ITextBuffer buffer) => 37 | buffer.Properties.GetOrCreateSingletonProperty(() => 38 | new ColorfulClassifier(buffer, classifications, classificationRegistry)); 39 | #endregion // Public methods 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/ColorfulCompletionSourceProvider.cs: -------------------------------------------------------------------------------- 1 | // Copyright © 2018 Transeric Solutions. All rights reserved. 2 | // Author: Eric David Lynch 3 | // License: https://www.codeproject.com/info/cpol10.aspx 4 | using System.ComponentModel.Composition; 5 | using Microsoft.VisualStudio.Language.Intellisense; 6 | using Microsoft.VisualStudio.Text; 7 | using Microsoft.VisualStudio.Text.Operations; 8 | using Microsoft.VisualStudio.Utilities; 9 | 10 | namespace ColorfulEditor 11 | { 12 | /// 13 | /// A factory for for the "Colorful" language. 14 | /// 15 | /// 16 | /// Adapted from https://docs.microsoft.com/en-us/visualstudio/extensibility/walkthrough-displaying-statement-completion. 17 | /// 18 | [Export(typeof(ICompletionSourceProvider))] 19 | [Name(nameof(ColorfulCompletionSourceProvider))] 20 | [ContentType(Colorful.ContentType)] 21 | internal class ColorfulCompletionSourceProvider : ICompletionSourceProvider 22 | { 23 | #region Managed Extensibility Framework (MEF) Fields 24 | // Import the service that caches ITextStructureNavigator objects based on content type 25 | [Import] 26 | private ITextStructureNavigatorSelectorService navigatorService = null; 27 | #endregion // Managed Extensibility Framework (MEF) Fields 28 | 29 | #region Public methods 30 | /// 31 | /// Try to create a completion source for the specified text buffer. 32 | /// 33 | /// The text buffer for which a completion source is created. 34 | /// The completion source that was created for the specified text buffer. 35 | public ICompletionSource TryCreateCompletionSource(ITextBuffer textBuffer) => 36 | new ColorfulCompletionSource(textBuffer, navigatorService); 37 | #endregion // Public methods 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/ColorfulKeywords.cs: -------------------------------------------------------------------------------- 1 | // Copyright © 2018 Transeric Solutions. All rights reserved. 2 | // Author: Eric David Lynch 3 | // License: https://www.codeproject.com/info/cpol10.aspx 4 | using System; 5 | using System.Collections.Generic; 6 | using System.Collections.ObjectModel; 7 | 8 | namespace ColorfulEditor 9 | { 10 | /// 11 | /// The keywords for the "Colorful" language. 12 | /// 13 | internal static class ColorfulKeywords 14 | { 15 | #region Private data 16 | // Adapted from https://en.wikipedia.org/wiki/List_of_colors:_A–F 17 | private static readonly List keywords = new List 18 | { 19 | "Amaranth", "Amber", "Amethyst", "Apricot", "Aquamarine", "Azure", "Beige", "Black", 20 | "Blue", "Blush", "Bronze", "Brown", "Burgundy", "Byzantium", "Carmine", "Cerise", 21 | "Cerulean", "Champagne", "Chartreuse", "Chocolate", "Cobalt", "Coffee", "Copper", 22 | "Coral", "Crimson", "Cyan", "Emerald", "Erin", "Gold", "Gray", "Green", "Harlequin", 23 | "Indigo", "Ivory", "Jade", "Lavender", "Lemon", "Lilac", "Lime", "Magenta", "Maroon", 24 | "Mauve", "Navy", "Ocher", "Olive", "Orange", "Orchid", "Peach", "Pear", "Periwinkle", 25 | "Pink", "Plum", "Puce", "Purple", "Raspberry", "Red", "Rose", "Ruby", "Salmon", 26 | "Sangria", "Sapphire", "Scarlet", "Silver", "Tan", "Taupe", "Teal", "Turquoise", 27 | "Violet", "Viridian", "White", "Yellow" 28 | }; 29 | 30 | private static readonly HashSet keywordSet = new HashSet( 31 | keywords, StringComparer.OrdinalIgnoreCase); 32 | #endregion // Private data 33 | 34 | #region Properties 35 | /// 36 | /// Gets the list of all keywords (in alphabetic order). 37 | /// 38 | internal static IReadOnlyList All { get; } = 39 | new ReadOnlyCollection(keywords); 40 | #endregion // Properties 41 | 42 | #region Internal methods 43 | /// 44 | /// Gets value indicating if the specified word is a keyword. 45 | /// 46 | /// The word to test. 47 | /// True, if the word is a keyword; otherwise, false. 48 | internal static bool Contains(string word) => 49 | keywordSet.Contains(word); 50 | #endregion // Internal methods 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/ColorfulTextViewCreationListener.cs: -------------------------------------------------------------------------------- 1 | // Copyright © 2018 Transeric Solutions. All rights reserved. 2 | // Author: Eric David Lynch 3 | // License: https://www.codeproject.com/info/cpol10.aspx 4 | using System.ComponentModel.Composition; 5 | using Microsoft.VisualStudio.Editor; 6 | using Microsoft.VisualStudio.Language.Intellisense; 7 | using Microsoft.VisualStudio.Shell; 8 | using Microsoft.VisualStudio.Text.Editor; 9 | using Microsoft.VisualStudio.TextManager.Interop; 10 | using Microsoft.VisualStudio.Utilities; 11 | 12 | namespace ColorfulEditor 13 | { 14 | /// 15 | /// A class to listen for the creation of text views for "Colorful" content. 16 | /// 17 | /// 18 | /// Adapted from https://docs.microsoft.com/en-us/visualstudio/extensibility/walkthrough-displaying-statement-completion. 19 | /// 20 | [Export(typeof(IVsTextViewCreationListener))] 21 | [Name(nameof(ColorfulTextViewCreationListener))] 22 | [ContentType(Colorful.ContentType)] 23 | [TextViewRole(PredefinedTextViewRoles.Editable)] 24 | public class ColorfulTextViewCreationListener : IVsTextViewCreationListener 25 | { 26 | #region Managed Extensibility Framework (MEF) Fields 27 | // Import an adapter to map between legacy TextManager code and editor code 28 | [Import] 29 | private IVsEditorAdaptersFactoryService adapterService = null; 30 | 31 | // Import the central completion broker responsible for IntelliSense completion 32 | [Import] 33 | private ICompletionBroker completionBroker = null; 34 | 35 | // Import the central Visual Studio service provider 36 | [Import] 37 | private SVsServiceProvider serviceProvider = null; 38 | #endregion // Managed Extensibility Framework (MEF) Fields 39 | 40 | #region Public methods 41 | /// 42 | /// Invoked after a has been created and initialized. 43 | /// 44 | /// The that was created and initialized. 45 | public void VsTextViewCreated(IVsTextView vsTextView) 46 | { 47 | // Get the WPF text view for the specified text view adapter 48 | ITextView textView = adapterService.GetWpfTextView(vsTextView); 49 | 50 | // Create a target for OLE commands for the specified text view adapter 51 | textView.Properties.GetOrCreateSingletonProperty(() => 52 | new ColorfulOleCommandTarget(vsTextView, textView, 53 | completionBroker, serviceProvider)); 54 | } 55 | #endregion // Public methods 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/License.txt: -------------------------------------------------------------------------------- 1 | Copyright © 2018 Transeric Solutions. All rights reserved. 2 | Author: Eric David Lynch 3 | License: https://www.codeproject.com/info/cpol10.aspx 4 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | // Copyright © 2018 Transeric Solutions. All rights reserved. 2 | // Author: Eric David Lynch (based on auto-generated code) 3 | // License: https://www.codeproject.com/info/cpol10.aspx 4 | using System.Reflection; 5 | using System.Runtime.InteropServices; 6 | 7 | // General Information about an assembly is controlled through the following 8 | // set of attributes. Change these attribute values to modify the information 9 | // associated with an assembly. 10 | [assembly: AssemblyTitle("Colorful Editor")] 11 | [assembly: AssemblyDescription("A demonstration of Visual Studio extensibility for editors, using the fictitious \"Colorful\" language.")] 12 | [assembly: AssemblyConfiguration("")] 13 | [assembly: AssemblyCompany("Transeric Solutions")] 14 | [assembly: AssemblyProduct("Colorful Editor")] 15 | [assembly: AssemblyCopyright("Copyright © 2018 Transeric Solutions. All rights reserved.")] 16 | [assembly: AssemblyTrademark("")] 17 | [assembly: AssemblyCulture("")] 18 | 19 | // Setting ComVisible to false makes the types in this assembly not visible 20 | // to COM components. If you need to access a type in this assembly from 21 | // COM, set the ComVisible attribute to true on that type. 22 | [assembly: ComVisible(false)] 23 | 24 | // Version information for an assembly consists of the following four values: 25 | // 26 | // Major Version 27 | // Minor Version 28 | // Build Number 29 | // Revision 30 | // 31 | // You can specify all the values or you can default the Build and Revision Numbers 32 | // by using the '*' as shown below: 33 | // [assembly: AssemblyVersion("1.0.*")] 34 | [assembly: AssemblyVersion("1.0.0.0")] 35 | [assembly: AssemblyFileVersion("1.0.0.0")] 36 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/Sample.colorful: -------------------------------------------------------------------------------- 1 | Roses are red, 2 | violets are blue, // This is a comment 3 | and this is 22 4 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/packages.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/ColorfulEditor/source.extension.vsixmanifest: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | Colorful Editor 6 | A demonstration of Visual Studio extensibility for editors, using the fictitious "Colorful" language. 7 | License.txt 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/Microsoft.VSSDK.BuildTools.15.7.104.nupkg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/Microsoft.VSSDK.BuildTools.15.7.104.nupkg -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/build/Microsoft.VSSDK.BuildTools.props: -------------------------------------------------------------------------------- 1 | 2 | 3 | $(MSBuildThisFileDirectory)..\ 4 | $(ThisPackageDirectory)\tools 5 | $(VSToolsPath)\VSSDK 6 | $(VsSDKInstall)\inc 7 | $(VsSDKInstall)\bin 8 | 9 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/build/Microsoft.VSSDK.BuildTools.targets: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | System.Environment.SetEnvironmentVariable("VsSDKToolsPath", System.IO.Path.GetFullPath(ProjectDirectory + @"\..\tools\VSSDK\bin"),EnvironmentVariableTarget.Process); 10 | System.Environment.SetEnvironmentVariable("VsSDKSchemaDir", System.IO.Path.GetFullPath(ProjectDirectory + @"\..\tools\VSSDK\schemas"),EnvironmentVariableTarget.Process); 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/Microsoft.VisualStudio.ExtensionEngine.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/Microsoft.VisualStudio.ExtensionEngine.dll -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 |  2 | 12 | 13 | 14 | 18 | 19 | <_BuiltProjectOutputGroupOutput Include="$(OutDir)$(TargetName)$(TargetExt)" /> 20 | 21 | 22 | 23 | 24 | 28 | 29 | <_DebugSymbolsProjectOutputGroupOutput Include="$(OutDir)$(TargetName).pdb" /> 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/Microsoft.VsSDK.Cpp.targets: -------------------------------------------------------------------------------- 1 |  2 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | $(BeforeResourceCompileTargets); 22 | VSCTCompile 23 | 24 | 25 | $(AfterBuildLinkTargets); 26 | IsolatedShellFiles; 27 | RegisterStubTarget; 28 | _VsixCleanRecordFileWrites 29 | 30 | 31 | 32 | 35 | 36 | 37 | 38 | 39 | 40 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 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| 12 | 13 | 15 | 17 | 18 | 19 | 20 | 21 | 22 | 24 | 25 | 26 | 27 | $(CleanDependsOn);CleanVsdbgConfigContract 28 | 29 | 30 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/bin/Microsoft.VSDebugger.targets: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | $(OutputPath)$(TargetName).vsdconfig 9 | Link 10 | CopyFilesToOutputDirectory 11 | 12 | 13 | 19 | 20 | 22 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | $(BuiltProjectOutputGroupDependsOn);AddVsdbgConfigFileToOutputGroup 36 | 37 | 38 | 40 | 41 | 42 | 43 | $(CleanDependsOn);CleanVsdbgConfigFile 44 | 45 | 46 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/bin/RegPkg.exe: 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13 | #define guidRazorCmdSet { 0x5289d302, 0x2432, 0x4761, { 0x8c, 0x45, 0x5, 0x1c, 0x64, 0xbd, 0x0, 0xc4 } } 14 | 15 | #define guidVsDebugPresentationIcon { 0x271f465f, 0x409, 0x4cbc, { 0x95, 0xf6, 0x56, 0x30, 0x85, 0x77, 0xdc, 0xe6 } } 16 | 17 | // Guid of our icons for toolbar buttons 18 | #define guidRazorToolbarIcons {0xC760F489, 0xE2D2, 0x4D20, {0xB5, 0x9B, 0xAD, 0x53, 0x65, 0xF2, 0xF8, 0xD9 } } 19 | 20 | // Guid of the App Thumbnail icon 21 | #define guidAppThumbnailIcon { 0xa879711, 0xd2f9, 0x4312, { 0x93, 0x12, 0xf7, 0xd7, 0x3c, 0xb6, 0x6a, 0x9 } } 22 | 23 | // This must match values in HubExtensions/UIConstants.cs 24 | // and intellitrace/Includes/PackageGuids.h 25 | #define guidIntelliTraceHubExtensionCmdSet { 0x11A58127, 0xDD59, 0x4506, { 0x83, 0x9B, 0xF6, 0xF6, 0x27, 0x61, 0x15, 0x21 } } 26 | 27 | // 28 | ///////////////////////////////////////////////////////////////////////////// 29 | 30 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/inc/editids.h: -------------------------------------------------------------------------------- 1 | // 2 | // editids.h 3 | // NOTE this file is superseded and defines moved to vsshlids.h 4 | // 5 | #ifndef _EDITIDS_H_ 6 | #define _EDITIDS_H_ 7 | 8 | 9 | #include "virtkeys.h" 10 | #include "stdidcmd.h" 11 | #include "vsshlids.h" 12 | #include "sharedids.h" 13 | #endif //_EDITIDS_H_ -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/offreg.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/offreg.dll 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For VS 2010, use 1.0.0 40 | 41 | 42 | 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/schemas/PackageManifestSchema.Assets.xsd: -------------------------------------------------------------------------------- 1 |  2 | 6 | 7 | 8 | This schema is used for installing extensions to Visual Studio. 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | The range of Visual Studio versions that this asset should be loaded for e.g. [15.0,16.0). Does not apply to assets of type ToolboxControl or VsPackage. 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/schemas/PackageManifestSchema.Dependencies.xsd: -------------------------------------------------------------------------------- 1 |  2 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | The Author element is the person or company creating the extension. 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | The Author element is the person or company creating the extension. 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/schemas/PackageManifestSchema.Installer.xsd: -------------------------------------------------------------------------------- 1 |  2 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/schemas/PackageManifestSchema.Prerequisites.xsd: -------------------------------------------------------------------------------- 1 |  2 | 6 | 7 | 8 | 9 | 10 | 11 | This schema is used for installing extensions to Visual Studio. 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /examples/ColorfulEditor/packages/Microsoft.VSSDK.BuildTools.15.7.104/tools/vssdk/schemas/PackageManifestSchema.xsd: -------------------------------------------------------------------------------- 1 |  2 | 8 | 9 | 10 | This schema is used for installing extensions to Visual Studio. 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | The Version attribute is the version of the VSIX file. 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/releases/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Language Extension - Prior Releases 2 | 3 | Because you never know, you might need that someday. 4 | 5 | Downloads available for prior versions of vsix exentions: 6 | 7 | [Version 0.3.3](./VerilogLanguage_v0.3.3.vsix) - various fixes to highlighting. See [tweets](https://twitter.com/gojimmypi/status/1213116109467136000?s=20). 8 | 9 | Version 0.3.2 - development versions only 10 | 11 | [Version 0.3.1](./VerilogLanguage_v0.3.1.vsix) 12 | 13 | [Version 0.2.0](./VerilogLanguage_v0.2.0.vsix) - First introduction of colorized brackets and variable definition hover text. This release does not handle larger files well. 14 | 15 | [Version 0.1.4](./VerilogLanguage_v0.1.4.vsix) 16 | 17 | [Version 0.1.2](./VerilogLanguage_v0.1.2.vsix) 18 | 19 | [Version 0.1.1](./VerilogLanguage_v0.1.1.vsix) - Initial release 20 | -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.1.1.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.1.1.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.1.2.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.1.2.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.1.4.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.1.4.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.2.0.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.2.0.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.2.1.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.2.1.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.3.0.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.3.0.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.3.1.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.3.1.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.3.3.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.3.3.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.3.4.01.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.3.4.01.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.3.4.02.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.3.4.02.vsix -------------------------------------------------------------------------------- /releases/VerilogLanguage_v0.3.4.36.vsix: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gojimmypi/VerilogLanguageExtension/1e2fec63c53009f5ce2152102da3f63ce4b9da95/releases/VerilogLanguage_v0.3.4.36.vsix -------------------------------------------------------------------------------- /source.extension.vsixmanifest: -------------------------------------------------------------------------------- 1 |  2 | 12 | 13 | 14 | 15 | 16 | VerilogLanguage 17 | Verilog Extension for Visual Studio. (classifier extension). Implements the Verilog Language Extension allowing user-definable keyword colorization. Useful for FPGA development. 18 | https://github.com/gojimmypi/VerilogLanguageExtension 19 | LICENSE.md 20 | https://github.com/gojimmypi/VerilogLanguageExtension/blob/master/README.md#installation 21 | https://github.com/gojimmypi/VerilogLanguageExtension/blob/master/releases/README.md 22 | Verilog keyword syntax highlight extension FPGA HDL 23 | true 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | --------------------------------------------------------------------------------