├── benchmarks ├── fpu2 │ ├── adder │ │ ├── stim_z │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ └── test_bench_tb.v │ ├── double_adder │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ └── test_bench_tb.v │ ├── double_to_float │ │ ├── test_bench │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ ├── test_bench_tb.v │ │ └── test_bench.v │ ├── double_divider │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ └── test_bench_tb.v │ ├── double_multiplier │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ └── test_bench_tb.v │ ├── double_to_long │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ ├── test_bench_tb.v │ │ └── test_bench.v │ ├── float_to_double │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ ├── test_bench_tb.v │ │ └── test_bench.v │ ├── long_to_double │ │ ├── file_reader.v │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ ├── test_bench_tb.v │ │ └── test_bench.v │ ├── .gitignore │ ├── divider │ │ ├── .gitignore │ │ ├── c_test │ │ │ ├── Makefile │ │ │ └── test.cpp │ │ └── test_bench_tb.v │ ├── multiplier │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ └── test_bench_tb.v │ ├── float_to_int │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ ├── test_bench_tb.v │ │ └── test_bench.v │ ├── int_to_float │ │ ├── .gitignore │ │ ├── c_test │ │ │ └── test.cpp │ │ ├── test_bench_tb.v │ │ └── test_bench.v │ └── COPYING.txt ├── yarvi │ ├── XuLA2 │ │ ├── .gitignore │ │ ├── XuLA2_lx25.bit │ │ ├── xula2.ucf │ │ ├── Makefile │ │ ├── xula2.prj │ │ ├── fpga_project.mk │ │ └── xula2.ut │ ├── shared │ │ ├── input.txt │ │ ├── crt0.c │ │ ├── initregs.txt │ │ └── Makefile.common │ ├── BeMicroCV-A9 │ │ ├── BeMicroCVA9.qpf │ │ ├── BeMicroCVA9.sdc │ │ └── BeMicroCVA9.cdf │ ├── Makefile │ ├── BeMicroCV │ │ ├── bemicrocv.qpf │ │ ├── bemicrocv.cdf │ │ ├── bemicrocv.sdc │ │ └── test_yarvi.v │ ├── README.md │ ├── sw │ │ └── Makefile │ └── ISSUES ├── xcrypto-ref │ ├── flow │ │ ├── verilator │ │ │ └── .gitignore │ │ ├── gtkwave │ │ │ ├── filter-instr-result.txt │ │ │ └── filter-pack-width.txt │ │ ├── yosys │ │ │ ├── proofs.sby │ │ │ ├── adder.ys │ │ │ ├── prep_ise_model.ys │ │ │ ├── write-smt-tb.ys │ │ │ └── write-verilog.ys │ │ ├── icarus │ │ │ ├── manifest.cmd │ │ │ └── integration.cmd │ │ └── benchmarks │ │ │ ├── mpn_plot_perf.py │ │ │ └── Makefile │ ├── docs │ │ ├── diagrams │ │ │ ├── cop-mem-if-1.png │ │ │ ├── cop-mem-if-2.png │ │ │ ├── cpu-cop-if-1.png │ │ │ ├── cpu-cop-if-2.png │ │ │ ├── cop-block-diagram.png │ │ │ ├── cop-mem-if-1.wd │ │ │ ├── cop-mem-if-2.wd │ │ │ ├── top-level-fsm.dot │ │ │ ├── cpu-cop-if-2.wd │ │ │ ├── cpu-cop-if-1.wd │ │ │ └── formal-flow.dot │ │ └── Makefile │ ├── examples │ │ ├── mpn │ │ │ └── Makefile │ │ ├── sha2 │ │ │ └── Makefile │ │ ├── prince │ │ │ └── Makefile │ │ ├── keccakp-400 │ │ │ └── Makefile │ │ ├── helloworld │ │ │ └── Makefile │ │ ├── keccakp-1600 │ │ │ └── Makefile │ │ ├── integration-test │ │ │ ├── Makefile │ │ │ ├── copmv.x.S │ │ │ └── integration-test.c │ │ ├── aes-test │ │ │ └── Makefile │ │ └── common │ │ │ └── linker.ld │ ├── verif │ │ ├── unit │ │ │ ├── 40-sbox.S │ │ │ ├── 00-mvcop.S │ │ │ ├── 01-cmov.S │ │ │ ├── 38-aes-sub.S │ │ │ ├── 15-gather-b.S │ │ │ ├── 17-gather-h.S │ │ │ ├── 16-scatter-b.S │ │ │ ├── 18-scatter-h.S │ │ │ ├── 02-li.S │ │ │ ├── 19-random.S │ │ │ ├── 04-ins-ext.S │ │ │ ├── Makefile │ │ │ ├── 41-sha3.S │ │ │ ├── 31-equ-mp.S │ │ │ ├── 32-ltu-mp.S │ │ │ ├── 33-gtu-mp.S │ │ │ ├── 08-load.S │ │ │ ├── 12-store-w.S │ │ │ ├── 13-store-h.S │ │ │ ├── 10-load-h.S │ │ │ ├── 14-store-b.S │ │ │ ├── 11-load-b.S │ │ │ ├── 20-add2-mp.S │ │ │ ├── 28-sub2-mp.S │ │ │ ├── 22-slli-mp.S │ │ │ ├── 25-srli-mp.S │ │ │ └── 39-aes-mix.S │ │ └── formal │ │ │ ├── fml_chk_instr_gpr2xcr.v │ │ │ ├── fml_chk_instr_xcr2gpr.v │ │ │ ├── fml_chk_instr_ld_hiu.v │ │ │ ├── fml_chk_instr_ld_liu.v │ │ │ ├── fml_chk_correct_invalid_opcode_response.v │ │ │ ├── fml_chk_instr_macc_1.v │ │ │ ├── fml_chk_instr_cmov_f.v │ │ │ ├── fml_chk_instr_cmov_t.v │ │ │ ├── fml_chk_instr_madd_2.v │ │ │ ├── fml_chk_instr_msub_2.v │ │ │ ├── fml_chk_instr_macc_2.v │ │ │ ├── fml_chk_instr_madd_3.v │ │ │ ├── fml_chk_instr_msub_3.v │ │ │ ├── fml_chk_instr_msll_i.v │ │ │ ├── fml_chk_instr_msrl_i.v │ │ │ ├── fml_chk_instr_mix_l.v │ │ │ ├── fml_chk_instr_mix_h.v │ │ │ ├── fml_chk_instr_ext.v │ │ │ ├── fml_chk_instr_mmul_3.v │ │ │ ├── fml_chk_instr_rngsamp.v │ │ │ ├── fml_chk_instr_mequ.v │ │ │ ├── fml_chk_instr_rngtest.v │ │ │ ├── fml_chk_instr_bop.v │ │ │ ├── fml_chk_instr_rngseed.v │ │ │ ├── fml_chk_no_reg_write_if_invalid_op.v │ │ │ ├── fml_chk_instr_msll.v │ │ │ ├── fml_chk_instr_msrl.v │ │ │ ├── fml_chk_correct_result_encodings.v │ │ │ ├── fml_chk_instr_mgte.v │ │ │ ├── fml_chk_instr_mlte.v │ │ │ ├── fml_chk_instr_pperm_w.v │ │ │ ├── fml_chk_instr_lut.v │ │ │ ├── fml_chk_instr_pperm_b0.v │ │ │ ├── fml_chk_instr_pperm_b3.v │ │ │ ├── fml_chk_instr_pperm_h0.v │ │ │ ├── fml_chk_instr_pperm_h1.v │ │ │ ├── fml_chk_instr_pperm_b1.v │ │ │ ├── fml_chk_instr_pperm_b2.v │ │ │ ├── fml_chk_instr_ins.v │ │ │ ├── fml_chk_instr_aessub_dec.v │ │ │ ├── fml_chk_instr_padd.v │ │ │ ├── fml_chk_instr_psub.v │ │ │ ├── fml_chk_instr_aessub_enc.v │ │ │ ├── fml_chk_instr_prot.v │ │ │ ├── fml_chk_instr_psll.v │ │ │ ├── fml_chk_instr_psrl.v │ │ │ ├── fml_chk_instr_aessub_decrot.v │ │ │ └── fml_chk_instr_aessub_encrot.v │ ├── .gitignore │ └── .gitmodules ├── fpu │ ├── FPU.pdf │ ├── test_vectors │ │ ├── pg.exe │ │ ├── mkall_fcmp.bat │ │ ├── pg-src │ │ │ └── README │ │ └── README │ └── verilog │ │ ├── div_r2.v │ │ ├── mul_r2.v │ │ └── check_all.sh ├── 472-mips-pipelined │ ├── .gitignore │ ├── annot-alu.json │ ├── testbench.v │ ├── annot-mux3.json │ ├── annot-reg32.json │ ├── annot-rom32.json │ ├── annot-alu_ctl.json │ ├── alu_stub.v │ ├── mux3.v │ ├── annot-control_pipeline.json │ ├── annot-reg_file.json │ ├── mem32-stub.v │ ├── test.fq │ └── mux2.v ├── crypto_cores │ ├── sha_core │ │ └── trunk │ │ │ ├── doc │ │ │ ├── Secure Hash Algorithm IP Core.doc │ │ │ └── Secure Hash Algorithm IP Core.pdf │ │ │ └── src │ │ │ └── mirdef.h │ └── RSA4096 │ │ └── ModExp2 │ │ ├── _parameter.v │ │ ├── mul_add.v │ │ ├── compile.txt │ │ └── mem_stubs.v └── README.md ├── test ├── .gitignore ├── secverilog │ ├── test2.v │ ├── test-secverilog.sh │ ├── secverilog.fun │ └── secverilog.v ├── verilog │ ├── pos │ │ ├── tr-test-10.v │ │ ├── simple01.v │ │ ├── tr-test-0.v │ │ ├── annot-tr-test-1.json │ │ ├── annot-tr-test-9.json │ │ ├── annot-merge-02.json │ │ ├── annot-merge03.json │ │ ├── annot-tr-test-10.json │ │ ├── tr-test-4.v │ │ ├── combine02.v │ │ ├── tr-test-9.v │ │ ├── tr-test-1.v │ │ ├── tr-test-5.v │ │ ├── annot-tr-test-2.json │ │ ├── annot-tr-test-3.json │ │ ├── annot-tr-test-4.json │ │ ├── annot-tr-test-5.json │ │ ├── annot-tr-test-6.json │ │ ├── tr-test-2.v │ │ ├── merge04-1.v │ │ ├── tr-test-8.v │ │ ├── annot-secverilog-01.json │ │ ├── secverilog-01.v │ │ ├── combine01.v │ │ ├── tr-test-3.v │ │ ├── annot-merge04-1.json │ │ ├── tr-test-11.v │ │ ├── tr-test-6.v │ │ ├── annot-merge04.json │ │ ├── annot-tr-test-11.json │ │ ├── merge-01.v │ │ ├── merge04.v │ │ ├── merge03.v │ │ ├── merge-02.v │ │ └── tr-test-7.v │ └── neg │ │ ├── annot-neg-test-1.json │ │ ├── neg-test-1.v │ │ ├── annot-secverilog-neg-01.json │ │ ├── neg-test-11.v │ │ ├── annot-neg-merge-01.json │ │ ├── annot-neg-test-5.json │ │ ├── annot-tp.json │ │ ├── annot-secverilog-neg-02.json │ │ ├── secverilog-neg-01.v │ │ ├── annot-neg-test-11.json │ │ ├── neg-test-0.v │ │ ├── annot-neg-test-2.json │ │ ├── neg-test-4.v │ │ ├── tp.v │ │ ├── neg-test-5.v │ │ ├── neg-merge-01.v │ │ ├── neg-test-2.v │ │ ├── neg-test-3.v │ │ └── synth.v ├── abduction │ └── pos │ │ ├── abduction-07.v │ │ ├── abduction-01.v │ │ ├── abduction-02.v │ │ ├── abduction-03.v │ │ ├── abduction-04.v │ │ ├── abduction-05.v │ │ └── abduction-06.v └── test.v ├── .ignore ├── iverilog-parser ├── ivlpp │ └── .gitignore ├── version_tag.h ├── check.conf ├── README.md ├── version_base.h ├── elab_sig_analog.cc ├── PModport.cc ├── lexor_keyword.h └── PClass.cc ├── ChangeLog.md ├── .hspec ├── app └── Main.hs ├── .gitmodules ├── examples ├── verilog │ ├── mod1.v │ ├── annot-stall.json │ └── modular.v ├── minimal.pl ├── yarvi-minimal.pl └── fp │ ├── test02.fq │ ├── test01.fq │ └── Test.hs ├── scripts ├── linprog │ ├── README.md │ ├── .gitignore │ ├── requirements.txt │ ├── config.py │ ├── Makefile │ └── testing.py ├── tag_equals ├── eqs.py ├── get_average.sh ├── line_count.sh └── remove_comments.sh ├── .ghci ├── stack.yaml ├── iodine ├── src └── Iodine │ ├── Types.hs │ └── Abduction │ └── Utils.hs ├── .gitignore ├── LICENSE └── t /benchmarks/fpu2/adder/stim_z: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /test/.gitignore: -------------------------------------------------------------------------------- 1 | a.out 2 | -------------------------------------------------------------------------------- /.ignore: -------------------------------------------------------------------------------- 1 | /liquid-fixpoint/ 2 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_adder/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_float/test_bench: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /iverilog-parser/ivlpp/.gitignore: -------------------------------------------------------------------------------- 1 | ivlpp 2 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_divider/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_multiplier/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_float/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_long/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_double/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/fpu2/long_to_double/file_reader.v: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/.gitignore: -------------------------------------------------------------------------------- 1 | /VHDL_Lib 2 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/verilator/.gitignore: -------------------------------------------------------------------------------- 1 | obj_dir/ 2 | -------------------------------------------------------------------------------- /benchmarks/yarvi/shared/input.txt: -------------------------------------------------------------------------------- 1 | aw1729 2 | arrr 3 | -------------------------------------------------------------------------------- /ChangeLog.md: -------------------------------------------------------------------------------- 1 | # Changelog for verylog-hs 2 | 3 | ## Unreleased changes 4 | -------------------------------------------------------------------------------- /.hspec: -------------------------------------------------------------------------------- 1 | --fail-fast 2 | --failure-report=.test-report.txt 3 | --print-cpu-time 4 | -------------------------------------------------------------------------------- /benchmarks/fpu2/adder/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV-A9/BeMicroCVA9.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "BeMicroCVA9" 2 | -------------------------------------------------------------------------------- /benchmarks/fpu2/.gitignore: -------------------------------------------------------------------------------- 1 | */c_test/test 2 | 3 | /Chips-* 4 | venv/ 5 | 6 | *.z3 7 | -------------------------------------------------------------------------------- /benchmarks/fpu2/divider/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/multiplier/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_adder/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_divider/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_float/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_long/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_double/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_int/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/int_to_float/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu2/long_to_double/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /benchmarks/fpu/FPU.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/fpu/FPU.pdf -------------------------------------------------------------------------------- /benchmarks/fpu2/double_multiplier/.gitignore: -------------------------------------------------------------------------------- 1 | stim_a 2 | stim_b 3 | resp_z 4 | test_bench_tb 5 | -------------------------------------------------------------------------------- /iverilog-parser/version_tag.h: -------------------------------------------------------------------------------- 1 | #ifndef VERSION_TAG 2 | #define VERSION_TAG "v10_2" 3 | #endif 4 | -------------------------------------------------------------------------------- /iverilog-parser/check.conf: -------------------------------------------------------------------------------- 1 | functor:cprop 2 | functor:nodangle 3 | -t:dll 4 | flag:DLL=tgt-vvp/vvp.tgt 5 | -------------------------------------------------------------------------------- /benchmarks/yarvi/Makefile: -------------------------------------------------------------------------------- 1 | status: 2 | $(MAKE) -s -C sim testall 3 | 4 | fpgademo: 5 | $(MAKE) -C BeMicroCV-A9 6 | -------------------------------------------------------------------------------- /benchmarks/fpu/test_vectors/pg.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/fpu/test_vectors/pg.exe -------------------------------------------------------------------------------- /app/Main.hs: -------------------------------------------------------------------------------- 1 | module Main where 2 | 3 | import qualified Iodine.Runner as R (main) 4 | 5 | main :: IO () 6 | main = R.main 7 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/XuLA2_lx25.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/yarvi/XuLA2/XuLA2_lx25.bit -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/.gitignore: -------------------------------------------------------------------------------- 1 | pipelined/* 2 | tmp* 3 | work* 4 | transcript 5 | *.bak 6 | *.mti 7 | *.mpf 8 | *.wlf 9 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "liquid-fixpoint"] 2 | path = liquid-fixpoint 3 | url = https://github.com/gokhankici/liquid-fixpoint.git 4 | -------------------------------------------------------------------------------- /benchmarks/yarvi/shared/crt0.c: -------------------------------------------------------------------------------- 1 | extern int main() __attribute__((noreturn)); 2 | 3 | int _start(void) 4 | { 5 | return main(); 6 | } 7 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cop-mem-if-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/xcrypto-ref/docs/diagrams/cop-mem-if-1.png -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cop-mem-if-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/xcrypto-ref/docs/diagrams/cop-mem-if-2.png -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cpu-cop-if-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/xcrypto-ref/docs/diagrams/cpu-cop-if-1.png -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cpu-cop-if-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/xcrypto-ref/docs/diagrams/cpu-cop-if-2.png -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cop-block-diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/xcrypto-ref/docs/diagrams/cop-block-diagram.png -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV/bemicrocv.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "13.0" 2 | DATE = "21:56:43 October 20, 2013" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "bemicrocv" 7 | -------------------------------------------------------------------------------- /benchmarks/fpu2/divider/c_test/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all clean 2 | 3 | all: test 4 | 5 | test: test.cpp 6 | g++ -Wall -O2 -o $@ $< 7 | 8 | clean: 9 | rm -f test 10 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/gtkwave/filter-instr-result.txt: -------------------------------------------------------------------------------- 1 | 000 SUCCESS 2 | 001 ABORT 3 | 010 BAD_INS 4 | 100 BAD_LAD 5 | 101 BAD_SAD 6 | 110 LD_ERR 7 | 111 ST_ERR 8 | 9 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/gtkwave/filter-pack-width.txt: -------------------------------------------------------------------------------- 1 | 000 PW_1 2 | 001 PW_2 3 | 010 PW_4 4 | 011 PW_8 5 | 100 PW_16 6 | 101 PW_INVALID 7 | 110 PW_INVALID 8 | 111 PW_INVALID 9 | -------------------------------------------------------------------------------- /benchmarks/crypto_cores/sha_core/trunk/doc/Secure Hash Algorithm IP Core.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/crypto_cores/sha_core/trunk/doc/Secure Hash Algorithm IP Core.doc -------------------------------------------------------------------------------- /benchmarks/crypto_cores/sha_core/trunk/doc/Secure Hash Algorithm IP Core.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gokhankici/iodine/HEAD/benchmarks/crypto_cores/sha_core/trunk/doc/Secure Hash Algorithm IP Core.pdf -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/mpn/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TEST_NAME=mpn 3 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 4 | $(TGT_DIR)/boot.o \ 5 | $(LIBSCARV_A) 6 | 7 | include ../common/common.mk 8 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/sha2/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | TEST_NAME=sha2 4 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 5 | $(TGT_DIR)/boot.o \ 6 | $(LIBSCARV_A) 7 | 8 | include ../common/common.mk 9 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/prince/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | TEST_NAME=prince 4 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 5 | $(TGT_DIR)/boot.o \ 6 | $(LIBSCARV_A) 7 | 8 | include ../common/common.mk 9 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/keccakp-400/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TEST_NAME=keccakp-400 3 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 4 | $(TGT_DIR)/boot.o \ 5 | $(LIBSCARV_A) 6 | 7 | include ../common/common.mk 8 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/helloworld/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | TEST_NAME=helloworld 4 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 5 | $(TGT_DIR)/boot.o \ 6 | $(LIBSCARV_A) 7 | 8 | include ../common/common.mk 9 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/keccakp-1600/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TEST_NAME=keccakp-1600 3 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 4 | $(TGT_DIR)/boot.o \ 5 | $(LIBSCARV_A) 6 | 7 | include ../common/common.mk 8 | -------------------------------------------------------------------------------- /test/secverilog/test2.v: -------------------------------------------------------------------------------- 1 | module test(); 2 | 3 | reg {L} public, x; 4 | reg {H} secret; 5 | reg {LH x} y; 6 | 7 | always @(*) 8 | if (x == 1) y <= secret; 9 | else public <= y; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/integration-test/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TEST_NAME=integration-test 3 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 4 | $(TGT_DIR)/copmv.o \ 5 | $(TGT_DIR)/boot.o 6 | 7 | include ../common/common.mk 8 | -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV-A9/BeMicroCVA9.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name CLK_24MHZ -period 41.666 [get_ports {CLK_24MHZ}] 2 | create_clock -name DDR3_CLK_50MHZ -period 20 [get_ports {DDR3_CLK_50MHZ}] 3 | 4 | derive_pll_clocks 5 | derive_clock_uncertainty 6 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/xula2.ucf: -------------------------------------------------------------------------------- 1 | net fpgaClk_i loc=a9; # 12 MHz input clock. 2 | #Created by Constraints Editor (xc6slx25-ftg256-2) - 2015/01/04 3 | NET "fpgaClk_i" TNM_NET = fpgaClk_i; 4 | TIMESPEC TS_fpgaClk_i = PERIOD "fpgaClk_i" 12 MHz HIGH 50%; 5 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/40-sbox.S: -------------------------------------------------------------------------------- 1 | 2 | xc.ld.liu c0, 0x3210 3 | xc.ld.hiu c0, 0x7654 4 | xc.ld.liu c1, 0xBA98 5 | xc.ld.hiu c1, 0xFEDC 6 | 7 | xc.ld.liu c2, 0x981A 8 | xc.ld.hiu c2, 0x32D0 9 | 10 | xc.lut c3, c2, c0, c1 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /examples/verilog/mod1.v: -------------------------------------------------------------------------------- 1 | module mod1(clk); 2 | input clk; 3 | reg a; // source 4 | reg b; 5 | reg c; // sink 6 | 7 | always @(posedge clk) 8 | b <= a + 2; 9 | 10 | always @(posedge clk) 11 | c <= b * 4; 12 | endmodule 13 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-10.v: -------------------------------------------------------------------------------- 1 | module test(clk, i1, i2, o); 2 | input wire clk, i1, i2; 3 | output reg o; 4 | reg cond; 5 | 6 | always @(posedge clk) 7 | if (cond) 8 | o <= i1; 9 | else 10 | o <= i2; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/Makefile: -------------------------------------------------------------------------------- 1 | RVPATH= 2 | RVPREFIX=$(RVPATH)riscv64-unknown-elf- 3 | 4 | run: load 5 | python xula2.py 6 | 7 | load: xula2_lx25.bit 8 | xsload.py --fpga xula2_lx25.bit 9 | touch load 10 | 11 | xula2_lx25.bit: xula2-lx25 12 | 13 | include fpga_project.mk 14 | -------------------------------------------------------------------------------- /examples/minimal.pl: -------------------------------------------------------------------------------- 1 | %-- definitions 2 | register(if_inst). 3 | register(ex_inst). 4 | register(wb_res). 5 | register(regs). 6 | 7 | %-- links 8 | asn(if_inst, ex_inst). 9 | link(ex_inst, regs, wb_res). 10 | 11 | %-- tag source and sink 12 | source(if_inst). 13 | sink(wb_res). 14 | -------------------------------------------------------------------------------- /test/verilog/pos/simple01.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; // @annot{taint_sink(y)} 5 | 6 | always @(posedge clk) begin 7 | y <= x; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-0.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; // @annot{taint_sink(y)} 5 | 6 | always @(posedge clk) begin 7 | y <= x; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-1.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "z" 13 | ] 14 | } 15 | ] 16 | } 17 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-9.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "a" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "r" 13 | ] 14 | } 15 | ] 16 | } 17 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-neg-test-1.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "y" 13 | ] 14 | } 15 | ] 16 | } 17 | -------------------------------------------------------------------------------- /scripts/linprog/README.md: -------------------------------------------------------------------------------- 1 | # Installation 2 | 3 | ```sh 4 | mkvirtualenv --python=`which python3.6` linprog 5 | workon linprog 6 | add2virtualenv $HOME/libs/cplex_studio129/cplex/python/3.6/x86-64_linux 7 | add2virtualenv $HOME/libs/z3/bin/python 8 | pip3 install -r requirements.txt 9 | ``` 10 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/integration-test/copmv.x.S: -------------------------------------------------------------------------------- 1 | 2 | 3 | .global __move_to_cop 4 | __move_to_cop: # Move GPR a0 to CPR c0 5 | xc.gpr2xcr c0, a0 6 | ret 7 | 8 | .global __move_to_gpr 9 | __move_to_gpr: # Move CPR c0 to GPR a0 10 | xc.xcr2gpr a0, c0 11 | ret 12 | -------------------------------------------------------------------------------- /scripts/linprog/.gitignore: -------------------------------------------------------------------------------- 1 | # Byte-compiled / optimized / DLL files 2 | __pycache__/ 3 | *.py[cod] 4 | *$py.class 5 | 6 | /.venv 7 | /outputs/ 8 | 9 | # cplex files 10 | *.lp 11 | cplex.dot 12 | cplex.pdf 13 | cplex.png 14 | 15 | graph.dot 16 | graph.pdf 17 | 18 | /output 19 | /*.json 20 | 21 | /notes 22 | -------------------------------------------------------------------------------- /scripts/tag_equals: -------------------------------------------------------------------------------- 1 | #!/bin/zsh 2 | 3 | if [[ $# -ne 1 ]]; then 4 | echo "usage: ${0:h} " 5 | exit 1 6 | fi 7 | 8 | THIS_DIR=${0:A:h} 9 | FILENAME=$1 10 | 11 | # cat .liquid/.${FILENAME:t:r}.pl.fqout | $THIS_DIR/eqs.py | fzf 12 | cat .liquid/.${FILENAME:t:r}.pl.fqout | sort | uniq | fzf -e 13 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-07.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | // @annot{taint_source(a)} 3 | // @annot{taint_sink(d)} 4 | 5 | input clk; 6 | 7 | reg a,b,c,d; 8 | 9 | always @(posedge clk) begin 10 | b <= a + d; 11 | c <= b; 12 | d <= c; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-merge-02.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "opa", 7 | "opb" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "out" 14 | ] 15 | } 16 | ] 17 | } 18 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-merge03.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "opa", 7 | "opb" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "out" 14 | ] 15 | } 16 | ] 17 | } 18 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-10.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "i1", 7 | "i2" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "o" 14 | ] 15 | } 16 | ] 17 | } 18 | -------------------------------------------------------------------------------- /.ghci: -------------------------------------------------------------------------------- 1 | :set -fwarn-unused-binds -fwarn-unused-imports -fwarn-orphans 2 | :set -isrc:test:app-fp 3 | 4 | :def docs_ const $ return $ unlines [":!stack haddock"] 5 | :def docs const $ return $ unlines [":!stack haddock --open"] 6 | :def test const $ return $ unlines ["Test.main"] 7 | 8 | :set prompt "\ESC[34mλ> \ESC[m" 9 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-1.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; // @annot{taint_sink(y)} 5 | 6 | reg Stall; 7 | 8 | always @(posedge clk) begin 9 | if (Stall) 10 | y <= y; 11 | else 12 | y <= x; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/00-mvcop.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c3, t2 8 | xc.gpr2xcr c6, a3 9 | xc.gpr2xcr c5, t4 10 | xc.gpr2xcr c9, a5 11 | 12 | xc.xcr2gpr a1, c1 13 | xc.xcr2gpr t2, c3 14 | xc.xcr2gpr a3, c6 15 | xc.xcr2gpr t4, c5 16 | xc.xcr2gpr a5, c9 17 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-4.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk, slow; 3 | reg slow; // @annot{sanitize(slow)} 4 | reg x; // @annot{taint_source(x)} 5 | reg y; // @annot{taint_sink(y)} 6 | 7 | always @(posedge clk) 8 | y <= x; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-01.v: -------------------------------------------------------------------------------- 1 | module test(clk, slow, x); 2 | // @annot{taint_source(x)} 3 | // @annot{taint_sink(y)} 4 | 5 | input clk, slow, x; 6 | reg y; 7 | 8 | always @(posedge clk) 9 | if (slow == 1) begin 10 | y <= y; 11 | end else begin 12 | y <= x; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /scripts/eqs.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import sys 4 | 5 | s = set() 6 | 7 | for l in sys.stdin: 8 | l = l.replace("(", "") 9 | l = l.replace(")", "") 10 | ws = l.strip().split() 11 | 12 | for w in ws: 13 | if w.startswith("VLT_"): 14 | s.add(w[4:]) 15 | 16 | for w in sorted(s): 17 | print w 18 | -------------------------------------------------------------------------------- /scripts/linprog/requirements.txt: -------------------------------------------------------------------------------- 1 | attrs==19.1.0 2 | decorator==4.4.0 3 | entrypoints==0.3 4 | flake8==3.7.7 5 | jsonschema==3.0.1 6 | mccabe==0.6.1 7 | networkx==2.3 8 | pudb==2019.1 9 | pycodestyle==2.5.0 10 | pydot==1.4.1 11 | pyflakes==2.1.1 12 | Pygments==2.4.2 13 | pyparsing==2.4.0 14 | pyrsistent==0.15.2 15 | six==1.12.0 16 | urwid==2.0.1 17 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-alu.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "a", 7 | "b", 8 | "ctl" 9 | ] 10 | }, 11 | { 12 | "type": "sink", 13 | "variables": [ 14 | "result", 15 | "zero" 16 | ] 17 | } 18 | ] 19 | } 20 | -------------------------------------------------------------------------------- /benchmarks/fpu2/adder/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | int main() 6 | { 7 | float f = 1.0; 8 | unsigned int a, b, i; 9 | 10 | while(1){ 11 | cin >> a; 12 | cin >> b; 13 | f = *(float*)&a + *(float*)&b; 14 | i = *(int*)&f; 15 | cout << i << endl; 16 | } 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /test/verilog/pos/combine02.v: -------------------------------------------------------------------------------- 1 | module test(clk, y, z); 2 | input wire clk; 3 | input wire y; // @annot{taint_source(y)} 4 | output reg z; // @annot{taint_sink(z)} 5 | 6 | reg x; 7 | 8 | wire a; 9 | assign a = x; 10 | 11 | always @(posedge clk) 12 | x <= y; 13 | 14 | always @(posedge clk) 15 | z <= a; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 10ns / 100ps 2 | 3 | module proj4_testbench; 4 | reg clk, reset; 5 | 6 | mips_pipeline p1(clk, reset); 7 | 8 | always 9 | #5 clk = ~clk; 10 | 11 | initial begin 12 | clk = 1'b0; 13 | reset = 1'b0; #10; 14 | reset = 1'b1; #10; 15 | reset = 1'b0; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /benchmarks/fpu2/multiplier/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | int main() 6 | { 7 | float f = 1.0; 8 | unsigned int a, b, i; 9 | 10 | while(1){ 11 | cin >> a; 12 | cin >> b; 13 | f = *(float*)&a * *(float*)&b; 14 | i = *(int*)&f; 15 | cout << i << endl; 16 | } 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /test/secverilog/test-secverilog.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | SCRIPT="$HOME/apps/SecVerilog-1.0/Examples/secverilog" 4 | 5 | NAME='secverilog' 6 | Z3_FILE="$NAME.z3" 7 | FUN_FILE="$NAME.fun" 8 | VER_FILE="$NAME.v" 9 | 10 | echo "running: rm -f a.out $Z3_FILE && $SCRIPT -F $FUN_FILE -z $VER_FILE" 11 | 12 | rm -f a.out "$Z3_FILE" && "$SCRIPT" -F "$FUN_FILE" "$VER_FILE" 13 | -------------------------------------------------------------------------------- /benchmarks/fpu2/divider/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | int main() 6 | { 7 | float f = 1.0; 8 | unsigned int a, b, i; 9 | 10 | while(1){ 11 | cin >> a; 12 | cin >> b; 13 | f = *(float*)&a / *(float*)&b; 14 | i = *(int*)&f; 15 | cout << i << endl << flush; 16 | } 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_int/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | using namespace std; 5 | 6 | int main() 7 | { 8 | float f = 1.0; 9 | unsigned int i; 10 | uint32_t a; 11 | 12 | while(1){ 13 | cin >> a; 14 | f = *(float*)&a; 15 | i = (int)f; 16 | cout << i << endl; 17 | } 18 | 19 | return 0; 20 | } 21 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-9.v: -------------------------------------------------------------------------------- 1 | module test(clk, a, b, ar, o); 2 | input clk, a, b; 3 | output o; 4 | input wire ar; 5 | 6 | // @annot{taint_source(a)} 7 | // @annot{taint_sink(r)} 8 | 9 | wire c; 10 | reg r; 11 | 12 | assign c = a & b; 13 | 14 | always @(posedge clk) begin 15 | r <= c; 16 | end 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_long/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | using namespace std; 5 | 6 | int main() 7 | { 8 | double f = 1.0; 9 | uint64_t i; 10 | uint64_t a; 11 | 12 | while(1){ 13 | cin >> a; 14 | f = *(double*)&a; 15 | i = (uint64_t)f; 16 | cout << i << endl; 17 | } 18 | 19 | return 0; 20 | } 21 | -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV/bemicrocv.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 32-bit Version 13.1.3 Build 178 02/12/2014 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CEFA2F23) Path("") File("bemicrocv.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-1.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; 5 | reg z; // @annot{taint_sink(z)} 6 | 7 | always @(posedge clk) begin 8 | y <= x; 9 | end 10 | 11 | always @(posedge clk) begin 12 | z <= y; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_adder/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | int main() 6 | { 7 | double f = 1.0; 8 | unsigned long int a, b, i; 9 | 10 | while(1){ 11 | cin >> a; 12 | cin >> b; 13 | f = *(double*)&a + *(double*)&b; 14 | i = *(unsigned long int*)&f; 15 | cout << i << endl; 16 | } 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_divider/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | int main() 6 | { 7 | double f = 1.0; 8 | unsigned long int a, b, i; 9 | 10 | while(1){ 11 | cin >> a; 12 | cin >> b; 13 | f = *(double*)&a / *(double*)&b; 14 | i = *(unsigned long int*)&f; 15 | cout << i << endl; 16 | } 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/.gitignore: -------------------------------------------------------------------------------- 1 | *.vim 2 | *.swp 3 | *.swo 4 | *.~ 5 | *.pyc 6 | 7 | component.xml 8 | 9 | xgui/ 10 | 11 | docs/*.aux 12 | docs/*.bbl 13 | docs/*.blg 14 | docs/*.log 15 | docs/*.toc 16 | docs/*.pdf 17 | docs/*.out 18 | docs/*.bcf 19 | docs/*.run.xml 20 | docs/*.bak 21 | 22 | docs/diagrams/*.eps 23 | docs/diagrams/*.pdf 24 | 25 | 26 | work/* 27 | 28 | rename.sh 29 | -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV/bemicrocv.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name "clk_50" -period 20.000ns [get_ports {clk_50}] 2 | create_clock -name "clk_24" -period 41.667ns [get_ports {clk_24}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /stack.yaml: -------------------------------------------------------------------------------- 1 | resolver: lts-10.5 2 | 3 | packages: 4 | - . 5 | - ./liquid-fixpoint 6 | 7 | extra-deps: 8 | - dotgen-0.4.2 9 | - fgl-visualize-0.1.0.1 10 | - located-base-0.1.1.1 11 | - megaparsec-7.0.4 12 | - parser-combinators-1.0.1 13 | - hspec-2.7.0 14 | - QuickCheck-2.12.6.1 15 | - hspec-core-2.7.0 16 | - hspec-discover-2.7.0 17 | - yaml-0.11.0.0 18 | - libyaml-0.1.1.0 19 | 20 | 21 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-5.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk, slow; 3 | reg slow; // @annot{sanitize(slow)} 4 | reg x; // @annot{taint_source(x)} 5 | reg y; 6 | reg z; // @annot{taint_sink(z)} 7 | 8 | always @(posedge clk) begin 9 | y <= x; 10 | z <= y; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /benchmarks/crypto_cores/RSA4096/ModExp2/_parameter.v: -------------------------------------------------------------------------------- 1 | // common header file 2 | `ifndef __parameter_ 3 | `define __parameter_ 4 | 5 | `define DATA_WIDTH 64 6 | `define ADDR_WIDTH 6 7 | `define TOTAL_ADDR (2 ** `ADDR_WIDTH) 8 | `define TOTAL_BITS `DATA_WIDTH * `TOTAL_ADDR 9 | 10 | `define DATA_WIDTH32 32 11 | `define ADDR_WIDTH32 7 12 | `define TOTAL_ADDR32 (2 ** `ADDR_WIDTH32) 13 | 14 | `endif -------------------------------------------------------------------------------- /benchmarks/fpu2/double_multiplier/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | int main() 6 | { 7 | double f = 1.0; 8 | long unsigned int a, b, i; 9 | 10 | while(1){ 11 | cin >> a; 12 | cin >> b; 13 | f = *(double*)&a * *(double*)&b; 14 | i = *(long unsigned int*)&f; 15 | cout << i << endl; 16 | } 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /benchmarks/fpu/test_vectors/mkall_fcmp.bat: -------------------------------------------------------------------------------- 1 | 2 | 3 | rem -------------------- fcmp 4 | 5 | pg -q -r 0 -fcmp -p 0 -o fcmp/fcmp_pat0.hex 6 | 7 | pg -q -r 0 -fcmp -p 1 -o fcmp/fcmp_pat1.hex 8 | 9 | pg -q -r 0 -fcmp -p 2 -o fcmp/fcmp_pat2.hex 10 | 11 | pg -q -r 0 -fcmp -n 199990 -ll -o fcmp/fcmp_lg.hex 12 | 13 | pg -q -r 0 -fcmp -n 199990 -o fcmp/fcmp_sm.hex 14 | 15 | -------------------------------------------------------------------------------- /benchmarks/fpu2/int_to_float/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | using namespace std; 5 | 6 | int main() 7 | { 8 | float f = 1.0; 9 | unsigned int i; 10 | int32_t b; 11 | uint32_t a; 12 | 13 | while(1){ 14 | cin >> a; 15 | b = a; 16 | f = float(b); 17 | i = *(int*)&f; 18 | cout << i << endl; 19 | } 20 | 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-2.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "y" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "slow" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-3.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "z" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "slow" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-4.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "y" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "slow" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-5.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "z" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "slow" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-6.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "y" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "slow" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-2.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk, slow; 3 | reg slow; // @annot{sanitize(slow)} 4 | reg x; // @annot{taint_source(x)} 5 | reg y; // @annot{taint_sink(y)} 6 | 7 | always @(posedge clk) 8 | if (slow == 1) 9 | x <= x; 10 | else 11 | y <= x; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /benchmarks/fpu2/long_to_double/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | using namespace std; 5 | 6 | int main() 7 | { 8 | double f = 1.0; 9 | uint64_t i; 10 | int64_t b; 11 | uint64_t a; 12 | 13 | while(1){ 14 | cin >> a; 15 | b = a; 16 | f = double(b); 17 | i = *(uint64_t*)&f; 18 | cout << i << endl; 19 | } 20 | 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/merge04-1.v: -------------------------------------------------------------------------------- 1 | module test(clk, in1, in2, in3, out); 2 | input wire clk, in1, in2, in3; 3 | output reg out; 4 | 5 | reg in1_r, in2_r, in3_r; 6 | 7 | always @(posedge clk) begin 8 | in1_r <= in1; 9 | in2_r <= in2; 10 | in3_r <= in3; 11 | if (in3_r) 12 | out <= in1_r; 13 | else 14 | out <= in1_r + in2_r; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-mux3.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "y" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "y" 13 | ] 14 | }, 15 | { 16 | "type": "always_eq", 17 | "variables": [ 18 | "sel" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-secverilog-neg-01.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "in" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "out" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "in" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /test/secverilog/secverilog.fun: -------------------------------------------------------------------------------- 1 | ; ZL(0)=L, ZL(n > 0)=H 2 | (declare-fun ZL (Int) Label) 3 | (assert (= (ZL 0) LOW)) 4 | (assert (= (ZL 1) HIGH)) 5 | (assert (= (ZL 2) HIGH)) 6 | (assert (= (ZL 3) HIGH)) 7 | (assert (= (ZL 4) HIGH)) 8 | (assert (= (ZL 5) HIGH)) 9 | (assert (= (ZL 6) HIGH)) 10 | 11 | ; LH(0)=L, LH(1)=H 12 | (declare-fun LH (Int) Label) 13 | (assert (= (LH 0) LOW)) 14 | (assert (= (LH 1) HIGH)) 15 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-reg32.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "d_out" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "d_out" 13 | ] 14 | }, 15 | { 16 | "type": "always_eq", 17 | "variables": [ 18 | "reset" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_float/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | using namespace std; 5 | 6 | int main() 7 | { 8 | double f = 1.0; 9 | float i; 10 | uint64_t a; 11 | uint32_t z; 12 | 13 | while(1){ 14 | cin >> a; 15 | f = *(double*)&a; 16 | i = (float)f; 17 | z = *(uint32_t*)&i; 18 | cout << z << endl; 19 | } 20 | 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-rom32.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "data_out" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "data_out" 13 | ] 14 | }, 15 | { 16 | "type": "always_eq", 17 | "variables": [ 18 | "address" 19 | ] 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_double/c_test/test.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | using namespace std; 5 | 6 | int main() 7 | { 8 | uint32_t a; 9 | float b; 10 | double f = 1.0; 11 | uint64_t i; 12 | 13 | while(1){ 14 | cin >> a; 15 | b = *(float*)&a; 16 | f = (double)b; 17 | i = *(uint64_t*)&f; 18 | cout << i << endl; 19 | } 20 | 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-8.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; // @annot{taint_sink(y)} 5 | 6 | reg a,b; 7 | 8 | always @(posedge clk) begin 9 | if (a) 10 | b <= 1; 11 | else 12 | b <= 1; 13 | end 14 | 15 | always @(posedge clk) begin 16 | y <= x + b; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /iodine: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import os.path as p 4 | import subprocess 5 | import sys 6 | 7 | THIS_DIR = p.realpath(p.dirname(__file__)) 8 | IVERILOG_DIR = p.join(THIS_DIR, "iverilog-parser") 9 | 10 | r = subprocess.run(["stack", "exec", "iodine", "--", 11 | "--iverilog-dir", IVERILOG_DIR] + 12 | sys.argv[1:], 13 | cwd=THIS_DIR) 14 | sys.exit(r.returncode) 15 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/01-cmov.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c0, x0 7 | xc.gpr2xcr c1, x1 8 | xc.gpr2xcr c2, x2 9 | xc.gpr2xcr c3, x3 10 | 11 | xc.cmov.t c4, c0, c1 12 | xc.cmov.t c5, c1, c2 13 | xc.cmov.t c6, c2, c3 14 | xc.cmov.t c7, c3, c4 15 | 16 | xc.xcr2gpr x0, c4 17 | xc.xcr2gpr x1, c5 18 | xc.xcr2gpr x2, c6 19 | xc.xcr2gpr x3, c7 20 | 21 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-02.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | // @annot{taint_source(x)} 3 | // @annot{taint_sink(z)} 4 | 5 | input clk, slow; 6 | reg x; 7 | reg y; 8 | reg z; 9 | 10 | always @(posedge clk) 11 | if (slow == 1) 12 | x <= x; 13 | else 14 | y <= x; 15 | 16 | always @(posedge clk) 17 | z <= y; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV-A9/BeMicroCVA9.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 64-Bit Version 15.0.2 Build 153 07/15/2015 SJ Full Version */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CEFA9F23) Path("output_files/") File("BeMicroCVA9.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/yosys/proofs.sby: -------------------------------------------------------------------------------- 1 | 2 | [options] 3 | mode bmc 4 | depth 3 5 | 6 | [engines] 7 | smtbmc z3 8 | 9 | [script] 10 | read_verilog -formal -I../../ ../../../verif/model/model_ise.v 11 | read_verilog -formal -I../../ ../../../verif/model/model_checks.v 12 | read_verilog -formal -I../../ ../../../rtl/coprocessor/* 13 | read_verilog -formal -I../../ ../../../verif/tb/tb_formal.v 14 | prep -flatten -top tb_formal 15 | 16 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-secverilog-01.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "in" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "out" 13 | ] 14 | }, 15 | { 16 | "type": "initial_eq", 17 | "variables": [ 18 | "in", 19 | "out", 20 | "sec" 21 | ] 22 | } 23 | ] 24 | } 25 | -------------------------------------------------------------------------------- /test/verilog/pos/secverilog-01.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | 4 | // {L} 5 | // @annot{taint_source(in)} 6 | // @annot{sanitize(in)} 7 | reg in; 8 | 9 | // {L} 10 | // @annot{taint_sink(out)} 11 | // @annot{sanitize(out)} 12 | reg out; 13 | 14 | // {H} 15 | // @annot{sanitize(sec)} 16 | reg sec; 17 | 18 | always @(posedge(clk)) begin 19 | out <= in+sec; 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /test/verilog/pos/combine01.v: -------------------------------------------------------------------------------- 1 | module test(clk, i, o); 2 | input wire clk; 3 | input wire i; // @annot{taint_source(i)} 4 | output reg o; // @annot{taint_sink(o)} 5 | 6 | reg x; 7 | 8 | wire a1 = x + 1; 9 | wire b1 = x + 2; 10 | 11 | always @(posedge clk) 12 | x <= x + 1; 13 | 14 | always @(posedge clk) begin 15 | if (a1 > 0) 16 | o <= b1; 17 | else 18 | o <= 0; 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-alu_ctl.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "ALUOperation" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "ALUOperation" 13 | ] 14 | }, 15 | { 16 | "type": "always_eq", 17 | "variables": [ 18 | "ALUOp", 19 | "Funct" 20 | ] 21 | } 22 | ] 23 | } 24 | -------------------------------------------------------------------------------- /scripts/linprog/config.py: -------------------------------------------------------------------------------- 1 | import os.path as p 2 | 3 | DEBUG = False 4 | 5 | LINPROG_DIR = p.realpath(p.dirname(__file__)) 6 | PROJECT_ROOT = p.realpath(p.join(LINPROG_DIR, "../../")) 7 | BENCHMARK_DIR = p.join(PROJECT_ROOT, "benchmarks") 8 | SCHEMA_FILE = p.join(PROJECT_ROOT, "annotation-schema.json") 9 | IODINE_SCRIPT = p.join(PROJECT_ROOT, "iodine") 10 | ABDUCTION_OUTPUT = p.join(PROJECT_ROOT, "cplex.json") 11 | TMP_ANNOTFILE = "annot-last.json" 12 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-11.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; // @annot{taint_source(y)} 5 | reg z; // @annot{taint_sink(z)} 6 | 7 | // @annot{sanitize_glob(x)} 8 | 9 | // @annot{sanitize(z)} 10 | // @annot{assert_eq(z)} 11 | 12 | always @(posedge clk) begin 13 | z <= x + y; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-3.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk, slow; 3 | reg slow; // @annot{sanitize(slow)} 4 | reg x; // @annot{taint_source(x)} 5 | reg y; 6 | reg z; // @annot{taint_sink(z)} 7 | 8 | always @(posedge clk) 9 | if (slow == 1) 10 | x <= x; 11 | else 12 | y <= x; 13 | 14 | always @(posedge clk) 15 | z <= y; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /benchmarks/yarvi/shared/initregs.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000001 3 | 00810000 4 | 00000003 5 | 00000004 6 | 00000005 7 | 00000006 8 | 00000007 9 | 00000008 10 | 00000009 11 | 0000000a 12 | 0000000b 13 | 0000000c 14 | 0000000d 15 | 0000000e 16 | 0000000f 17 | 00000010 18 | 00000011 19 | 00000012 20 | 00000013 21 | 00000014 22 | 00000015 23 | 00000016 24 | 00000017 25 | 00000018 26 | 00000019 27 | 0000001a 28 | 0000001b 29 | 0000001c 30 | 0000001d 31 | 0000001e 32 | 0000001f 33 | -------------------------------------------------------------------------------- /scripts/linprog/Makefile: -------------------------------------------------------------------------------- 1 | PY_FILES = $(wildcard *.py) 2 | JQ_TYPES = always_eq initial_eq 3 | 4 | lint: 5 | flake8 $(PY_FILES) 6 | 7 | $(JQ_TYPES): %: 8 | cat annot-last.json | jq '.annotations | map(select(.type == "$@") | .variables) | add | sort' 9 | 10 | pairs: 11 | cat annot-last.json | jq '.qualifiers | map(select(.type == "pairs") | .variables) | .[]' 12 | 13 | freeze: 14 | pip freeze > requirements.txt 15 | 16 | .PHONY: lint freeze $(JQ_TYPES) 17 | .SILENT: 18 | -------------------------------------------------------------------------------- /benchmarks/yarvi/README.md: -------------------------------------------------------------------------------- 1 | # YARVI - Yet Another RISC-V Implementation # 2 | 3 | Here is a very simple RISC-V RV32I implementation. The point is 4 | clearity and correctness, not performance (that will follow). 5 | 6 | The included example has been tested mostly against the wonderful $149 7 | Arrow BeMicro CV A9, but the core itself is completely vendor neutral. 8 | 9 | [![tip for next commit](http://prime4commit.com/projects/274.svg)](http://prime4commit.com/projects/274) 10 | -------------------------------------------------------------------------------- /iverilog-parser/README.md: -------------------------------------------------------------------------------- 1 | # Verilog -> Iodine IR 2 | 3 | Transforms Verilog into Iodine intermediate representation. The implementation 4 | is based on [Icarus Verilog](https://github.com/steveicarus/iverilog). 5 | 6 | ## Dependencies 7 | 8 | * g++ 9 | * make 10 | * flex 11 | * bison 12 | * zsh 13 | 14 | Tested on Ubuntu 18.10, *might work* on a Mac. 15 | 16 | ## Instructions 17 | 18 | ```sh 19 | $> make 20 | $> ./ivl.sh [args to ivl ... ] 21 | ``` 22 | -------------------------------------------------------------------------------- /benchmarks/fpu2/adder/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #2000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/divider/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #2000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/aes-test/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TEST_NAME=aes-test 3 | OBJECTS = $(TGT_DIR)/$(TEST_NAME).o \ 4 | $(TGT_DIR)/boot.o \ 5 | $(LIBSCARV_A) 6 | 7 | CONF += -DCONF_AES_PRECOMP_RC 8 | CONF += -DCONF_AES_PRECOMP_RK 9 | CONF += -DCONF_AES_PRECOMP_SBOX 10 | CONF += -DCONF_AES_PRECOMP_MULX 11 | CONF += -DCONF_AES_ENABLE_ENC 12 | CONF += -DCONF_AES_ENABLE_DEC 13 | 14 | CFLAGS += $(CONF) 15 | include ../common/common.mk 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/get_average.sh: -------------------------------------------------------------------------------- 1 | #!/bin/zsh 2 | 3 | THIS_DIR=${0:A:h} 4 | 5 | if [[ $# -ne 2 ]]; then 6 | echo "usage: $0 " 7 | exit 1 8 | fi 9 | 10 | $THIS_DIR/../run-tests \ 11 | --no-save --no-output \ 12 | --single $1 --time --times $2 2>&1 | \ 13 | \ 14 | sed --unbuffered --silent 's/^Time taken: \([0-9]\+\) .*/\1/p' | \ 15 | tee /dev/tty | \ 16 | \ 17 | awk '{sum += $1; n += 1;} END {if(n>0){ printf("%d runs, ave: %.1f\n", n, sum/n); }}' 18 | 19 | 20 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_adder/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #8000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_divider/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #4000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_float/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #500000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_long/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #500000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_int/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #500000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/int_to_float/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #1000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/long_to_double/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #1000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/multiplier/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #1000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-neg-merge-01.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "opa", 7 | "opb" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "out" 14 | ] 15 | } 16 | ], 17 | "qualifiers": [ 18 | { 19 | "type": "implies", 20 | "lhs": "x", 21 | "rhs": [ 22 | "opb", 23 | "opa" 24 | ] 25 | } 26 | ] 27 | } 28 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-merge04-1.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "in1", 7 | "in2", 8 | "in3" 9 | ] 10 | }, 11 | { 12 | "type": "sink", 13 | "variables": [ 14 | "out" 15 | ] 16 | } 17 | ], 18 | "qualifiers": [ 19 | { 20 | "type": "pairs", 21 | "variables": [ 22 | "in1_r", 23 | "in2_r" 24 | ] 25 | } 26 | ] 27 | } 28 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-11.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; // @annot{taint_source(x)} 4 | reg y; // @annot{taint_source(y)} 5 | reg z; // @annot{taint_sink(z)} 6 | 7 | // @annot{sanitize_glob(x)} 8 | // @annot{sanitize_glob(y)} 9 | 10 | // @annot{sanitize(z)} 11 | // @annot{assert_eq(z)} 12 | 13 | always @(posedge clk) begin 14 | z <= x + y; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_multiplier/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #1000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_double/test_bench_tb.v: -------------------------------------------------------------------------------- 1 | module test_bench_tb; 2 | reg clk; 3 | reg rst; 4 | 5 | initial 6 | begin 7 | rst <= 1'b1; 8 | #50 rst <= 1'b0; 9 | end 10 | 11 | 12 | initial 13 | begin 14 | #1000000 $finish; 15 | end 16 | 17 | 18 | initial 19 | begin 20 | clk <= 1'b0; 21 | while (1) begin 22 | #5 clk <= ~clk; 23 | end 24 | end 25 | 26 | test_bench uut( 27 | .clk(clk), 28 | .rst(rst)); 29 | endmodule 30 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "external/riscv-opcodes"] 2 | path = external/riscv-opcodes 3 | url = https://github.com/scarv/riscv-opcodes.git 4 | [submodule "external/picorv32"] 5 | path = external/picorv32 6 | url = https://github.com/cliffordwolf/picorv32.git 7 | [submodule "external/libscarv"] 8 | path = external/libscarv 9 | url = https://github.com/scarv/libscarv.git 10 | [submodule "external/texmf"] 11 | path = external/texmf 12 | url = https://github.com/scarv/texmf.git 13 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/38-aes-sub.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0x00ab 7 | xc.ld.liu c0, 0x5312 8 | xc.ld.hiu c1, 0x5657 9 | xc.ld.liu c1, 0xfffe 10 | 11 | xc.aessub.enc c2, c0, c1 12 | xc.xcr2gpr a0, c2 13 | 14 | xc.aessub.dec c3, c2, c2 15 | xc.xcr2gpr a0, c3 16 | 17 | xc.aessub.decrot c2, c0, c1 18 | xc.xcr2gpr a0, c2 19 | 20 | xc.aessub.encrot c2, c0, c1 21 | xc.xcr2gpr a0, c2 22 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/alu_stub.v: -------------------------------------------------------------------------------- 1 | module alu_stub(ctl, a, b, result, zero); 2 | // inputs are the source: 3 | // @annot{taint_source(ctl)} 4 | input [2:0] ctl; 5 | input [31:0] a, b; 6 | 7 | // outputs are the sink: 8 | // @annot{taint_sink(result)} @annot{taint_sink(zero)} 9 | output [31:0] result; 10 | output zero; 11 | 12 | reg [31:0] result; 13 | reg zero; 14 | 15 | always @(*) begin 16 | result = ctl + a + b; 17 | end 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /examples/verilog/annot-stall.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "IF_instr" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "WB_ALUOut" 13 | ] 14 | }, 15 | { 16 | "type": "always_eq", 17 | "variables": [ 18 | "IF_instr" 19 | ] 20 | }, 21 | { 22 | "type": "initial_eq", 23 | "variables": [ 24 | "Stall" 25 | ] 26 | } 27 | ] 28 | } 29 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/15-gather-b.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.gather.b c2, c1, a1 11 | xc.gather.b c2, c1, a1 12 | xc.gather.b c2, c1, a1 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.gather.b c3, c1, a1 19 | xc.gather.b c2, c2, a1 20 | xc.gather.b c1, c1, a1 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/17-gather-h.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.gather.h c2, c1, a1 11 | xc.gather.h c2, c1, a1 12 | xc.gather.h c2, c1, a1 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.gather.h c3, c1, a1 19 | xc.gather.h c2, c2, a1 20 | xc.gather.h c1, c1, a1 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/16-scatter-b.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.scatter.b c2, c1, a1 11 | xc.scatter.b c2, c1, a1 12 | xc.scatter.b c2, c1, a1 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.scatter.b c3, c1, a1 19 | xc.scatter.b c2, c2, a1 20 | xc.scatter.b c1, c1, a1 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/18-scatter-h.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.scatter.h c2, c1, a1 11 | xc.scatter.h c2, c1, a1 12 | xc.scatter.h c2, c1, a1 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.scatter.h c3, c1, a1 19 | xc.scatter.h c2, c2, a1 20 | xc.scatter.h c1, c1, a1 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/xula2.prj: -------------------------------------------------------------------------------- 1 | vhdl XESS "VHDL_Lib/Common.vhd" 2 | vhdl XESS "VHDL_Lib/SyncToClk.vhd" 3 | vhdl XESS "VHDL_Lib/ClkGen.vhd" 4 | vhdl work "VHDL_Lib/Board_Packages/XuLA2.vhd" 5 | vhdl XESS "VHDL_Lib/Misc.vhd" 6 | vhdl XESS "VHDL_Lib/HostIo.vhd" 7 | vhdl XESS "VHDL_Lib/fifo.vhd" 8 | vhdl XESS "VHDL_Lib/Delay.vhd" 9 | vhdl XESS "VHDL_Lib/HostIoComm.vhd" 10 | verilog work "../shared/yarvi.v" 11 | verilog work "../shared/yarvi_soc.v" 12 | verilog work "axi_uart.v" 13 | verilog work "../shared/htif.v" 14 | verilog work "xula2.v" 15 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-6.v: -------------------------------------------------------------------------------- 1 | module test(clk, slow); 2 | input clk, slow; 3 | reg slow; // @annot{sanitize(slow)} 4 | reg x; // @annot{taint_source(x)} 5 | // reg y; 6 | // reg z; 7 | reg y; // @annot{taint_sink(y)} 8 | 9 | always @(posedge clk) 10 | if (slow) 11 | y <= y; 12 | else 13 | y <= x; 14 | 15 | // always @(*) 16 | // z = y; 17 | 18 | // always @(posedge clk) 19 | // t <= z; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/yosys/adder.ys: -------------------------------------------------------------------------------- 1 | 2 | # Read the design 3 | read_verilog -formal ../../rtl/coprocessor/scarv_cop_palu_adder.v 4 | 5 | # Dump pre-synthesis schematic to file 6 | show -format svg -prefix ../../work/adder-schematic-bhav 7 | 8 | # Processes / generates into netlist 9 | proc ; 10 | 11 | # generic synthsis 12 | synth; 13 | 14 | # Dump post-synthesis schematic to file 15 | show -format svg -prefix ../../work/adder-schematic-synth 16 | 17 | # Dump SMT2 model 18 | write_smt2 -wires ../../work/adder.smt2 19 | 20 | # Print stats 21 | stat -width; 22 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_gpr2xcr.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_gpr2xcr) 14 | 15 | // 16 | // gpr2xcr 17 | // 18 | `VTX_CHECK_INSTR_BEGIN(gpr2xcr) 19 | `VTX_ASSERT_CRD_VALUE_IS(vtx_instr_rs1) 20 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 21 | `VTX_ASSERT_WEN_IS_CLEAR 22 | `VTX_CHECK_INSTR_END(gpr2xcr) 23 | 24 | `VTX_CHECKER_MODULE_END 25 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-neg-test-5.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x", 7 | "y" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "out" 14 | ] 15 | }, 16 | { 17 | "type": "always_eq", 18 | "variables": [ 19 | "in_eq" 20 | ] 21 | }, 22 | { 23 | "type": "initial_eq", 24 | "variables": [ 25 | "cond1", 26 | "cond2", 27 | "x", 28 | "y" 29 | ] 30 | } 31 | ] 32 | } 33 | -------------------------------------------------------------------------------- /examples/yarvi-minimal.pl: -------------------------------------------------------------------------------- 1 | %-- definitions 2 | register(if_inst). 3 | register(dec_inst). 4 | register(ex_inst). 5 | register(dec_rsa). 6 | register(dec_rsb). 7 | register(ex_res). 8 | register(regs). 9 | register(wb_res). 10 | 11 | 12 | %-- if stage 13 | asn(if_inst, dec_inst). 14 | link(ex_inst, regs, dec_rsa). 15 | link(ex_inst, regs, dec_rsb). 16 | 17 | %-- dec stage 18 | asn(dec_inst, ex_inst). 19 | link(dec_rsa, dec_rsb, ex_res). 20 | 21 | %-- ex stage 22 | link(ex_inst, ex_res, wb_res). 23 | 24 | %-- wb stage 25 | 26 | %-- tag source and sink 27 | source(if_inst). 28 | sink(wb_res). 29 | -------------------------------------------------------------------------------- /benchmarks/fpu/test_vectors/pg-src/README: -------------------------------------------------------------------------------- 1 | 2 | Building PG 3 | =========== 4 | 5 | To build the floating point test pattern generator, you first need 6 | to get a copy of the SoftFloat library from: 7 | 8 | http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html 9 | 10 | Once installed, change directory to SoftFloat-2a/softfloat/bits32, 11 | copy the included source file to this directory and compile 12 | using a command like: 13 | 14 | gcc -I386-Win32-gcc -opg.exe fptpg.c softfloat.c 15 | 16 | This build has been tested on SPARC Solaris systems and WIndows NT 17 | with cygwin and gcc. 18 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cop-mem-if-1.wd: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'g_clk' , wave: 'p.............'}, 3 | {name: 'cop_mem_cen ', wave: '010.110.10.110'}, 4 | {name: 'cop_mem_wen ', wave: 'x0x.0..x10.11.'}, 5 | {name: 'cop_mem_addr ', wave: 'x3x.4..x5x.3.x'}, 6 | {name: 'cop_mem_wdata', wave: 'x......x5x.3.x'}, 7 | {name: 'cop_mem_ben ', wave: 'x......x5x.3.x'}, 8 | {name: 'cop_mem_rdata', wave: 'x.3x..4x.....x'}, 9 | {name: 'cop_mem_stall', wave: '0....10.....10'}, 10 | {name: 'cop_mem_error', wave: '0.............'}, 11 | ], 12 | head:{ 13 | tick:0, 14 | },} 15 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cop-mem-if-2.wd: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'g_clk' , wave: 'p.............'}, 3 | {name: 'cop_mem_cen ', wave: '011.11.011110.'}, 4 | {name: 'cop_mem_wen ', wave: 'x00.11.010.10.'}, 5 | {name: 'cop_mem_addr ', wave: 'x34.53.x2345x.'}, 6 | {name: 'cop_mem_wdata', wave: 'x...53.x2xx5x.'}, 7 | {name: 'cop_mem_ben ', wave: 'x...53.x2xx5x.'}, 8 | {name: 'cop_mem_rdata', wave: 'x.3x4x.x.x34xx'}, 9 | {name: 'cop_mem_stall', wave: '0..10.10......'}, 10 | {name: 'cop_mem_error', wave: '0.............'}, 11 | ], 12 | head:{ 13 | tick:0, 14 | },} 15 | -------------------------------------------------------------------------------- /benchmarks/yarvi/sw/Makefile: -------------------------------------------------------------------------------- 1 | # clone and install https://github.com/thotypous/alterajtaguart.git somewhere 2 | # and point to the relevant locations 3 | ALTERAJTAGUART_LIB=$(PWD)/../../alterajtaguart/software 4 | ALTERAJTAGUART_INCLUDE=$(PWD)/../../alterajtaguart/software 5 | 6 | CXX=g++ 7 | CC=$(CXX) 8 | CXXFLAGS=-O2 -Wall -I$(ALTERAJTAGUART_INCLUDE) 9 | LDFLAGS=-L$(ALTERAJTAGUART_LIB) -Wl,-rpath=$(ALTERAJTAGUART_LIB) 10 | LDLIBS=-ljtag_atlantic -ljtag_client 11 | 12 | all: htif-jtag htif-serial 13 | 14 | htif-jtag: htif-jtag.o $(ALTERAJTAGUART_LIB)/common.o 15 | 16 | htif-serial: htif-serial.o 17 | -------------------------------------------------------------------------------- /iverilog-parser/version_base.h: -------------------------------------------------------------------------------- 1 | #ifndef VERSION 2 | /* 3 | * Edit this definition in version_base.in to define the base version 4 | * number for the compiled result. 5 | */ 6 | # define VERSION_MAJOR 10 7 | # define VERSION_MINOR 2 8 | 9 | /* 10 | * This will be appended to the version. Use this to mark development 11 | * versions and the like. 12 | */ 13 | # define VERSION_EXTRA " (stable)" 14 | 15 | # define VERSION_STRINGIFY(x) #x 16 | # define VERSION_STR(a,b,extra) VERSION_STRINGIFY(a.b) extra 17 | 18 | #define VERSION VERSION_STR(VERSION_MAJOR,VERSION_MINOR,VERSION_EXTRA) 19 | #endif 20 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/02-li.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c0, x0 7 | xc.gpr2xcr c1, x1 8 | xc.gpr2xcr c2, x2 9 | xc.gpr2xcr c3, x3 10 | 11 | xc.ld.liu c4, 0x1 12 | xc.ld.hiu c4, 0x1 13 | 14 | xc.ld.hiu c5, 0x1 15 | xc.ld.liu c5, 0x1 16 | 17 | xc.ld.liu c5, 0x10 18 | xc.ld.hiu c5, 0x10 19 | 20 | xc.ld.hiu c6, 0xf0f0 21 | xc.ld.liu c6, 0xf0f0 22 | 23 | xc.ld.hiu c7, 0xFFFF 24 | xc.ld.liu c7, 0xFFFF 25 | 26 | xc.xcr2gpr x0, c4 27 | xc.xcr2gpr x1, c5 28 | xc.xcr2gpr x2, c6 29 | xc.xcr2gpr x3, c7 30 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/fpga_project.mk: -------------------------------------------------------------------------------- 1 | DIR_SPACES := $(subst /, ,$(CURDIR)) 2 | DIR_NAME := $(word $(words $(DIR_SPACES)), $(DIR_SPACES)) 3 | PROJECT := $(DIR_NAME) 4 | 5 | all: xula2-lx25 #xula2-lx9 6 | 7 | .PHONY: clean 8 | 9 | xula2-lx9: BRD=lx9 10 | xula2-lx9: 11 | make -f fpga_project_rules.mk PROJECT=$(PROJECT) PART=xc6s$(BRD)-2-ftg256 BRD=$(BRD) $(PROJECT)_$(BRD).bit 12 | 13 | xula2-lx25: BRD=lx25 14 | xula2-lx25: 15 | make -f fpga_project_rules.mk PROJECT=$(PROJECT) PART=xc6s$(BRD)-2-ftg256 BRD=$(BRD) $(PROJECT)_$(BRD).bit 16 | 17 | clean: 18 | make -f fpga_project_rules.mk clean 19 | -------------------------------------------------------------------------------- /benchmarks/crypto_cores/sha_core/trunk/src/mirdef.h: -------------------------------------------------------------------------------- 1 | /* 2 | * MIRACL compiler/hardware definitions - mirdef.h 3 | * Copyright (c) 1988-2002 Shamus Software Ltd. 4 | */ 5 | #define MR_COMBA 6 6 | #define MR_LITTLE_ENDIAN 7 | #define MIRACL 32 8 | #define mr_utype int 9 | #define MR_IBITS 32 10 | #define MR_LBITS 32 11 | #define mr_unsign32 unsigned int 12 | #define mr_dltype __int64 13 | #define mr_unsign64 unsigned __int64 14 | #define MR_STRIPPED_DOWN 15 | #define MAXBASE ((mr_small)1<<(MIRACL-1)) 16 | #define MR_BITSINCHAR 8 17 | 18 | #define MR_NO_FILE_IO 19 | #define NULL ((void *)0) 20 | 21 | 22 | -------------------------------------------------------------------------------- /src/Iodine/Types.hs: -------------------------------------------------------------------------------- 1 | module Iodine.Types where 2 | 3 | import Iodine.Language.Types 4 | import Iodine.Solver.FP.Types 5 | 6 | import qualified Data.ByteString.Lazy as B 7 | import Data.Sequence 8 | 9 | type ABS a = Seq (AlwaysBlockA a) 10 | type States = (St, AnnotSt) 11 | 12 | type Qualifiers a = Seq (FPQualifierA a) 13 | 14 | type ParseInput = ((FilePath, String), B.ByteString) 15 | type ParseOutput = (States, Qualifiers Id) 16 | 17 | type Intermediary = IntermediaryA Id 18 | type IntermediaryA a = (ABS a, IntermediaryASt a) 19 | type IntermediaryASt a = (AnnotStA a, Qualifiers a) 20 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-tp.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "in1", 7 | "in2" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "out" 14 | ] 15 | } 16 | ], 17 | "qualifiers": [ 18 | { 19 | "type": "implies", 20 | "lhs": "temp1", 21 | "rhs": [ 22 | "in2", 23 | "in1" 24 | ] 25 | }, 26 | { 27 | "type": "pairs", 28 | "variables": [ 29 | "temp1", 30 | "fast" 31 | ] 32 | } 33 | ] 34 | } 35 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/yosys/prep_ise_model.ys: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Prepares the ISE model for use with the formal flow by performing some 4 | # basic synthesis / lowering on it. 5 | # 6 | # Useful as the model takes a long time to synthesis like this, so doing it 7 | # once and then sharing the prepped file is useful. 8 | # 9 | 10 | # Read in the design 11 | read_verilog -I../../work/ ../../verif/model/model_ise.v 12 | 13 | # Lower processes/tasks/functions to netlist level 14 | proc 15 | 16 | # Basic optimisation loop 17 | opt 18 | 19 | # Write out the synthesised verilog 20 | write_verilog ../../work/model_ise_prep.v 21 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-merge04.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "in1", 7 | "in2", 8 | "in3" 9 | ] 10 | }, 11 | { 12 | "type": "sink", 13 | "variables": [ 14 | "out" 15 | ] 16 | } 17 | ], 18 | "qualifiers": [ 19 | { 20 | "type": "pairs", 21 | "variables": [ 22 | "in1_r2", 23 | "in2_r2" 24 | ] 25 | }, 26 | { 27 | "type": "pairs", 28 | "variables": [ 29 | "in2_r", 30 | "in1_r" 31 | ] 32 | } 33 | ] 34 | } 35 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/mux3.v: -------------------------------------------------------------------------------- 1 | module mux3(sel, a, b, c, y); 2 | // @annot{taint_source(y)} 3 | // @annot{taint_sink(y)} 4 | 5 | // @annot{sanitize_glob(sel)} 6 | // @annot{taint_eq(a)} 7 | // @annot{taint_eq(b)} 8 | // @annot{taint_eq(c)} 9 | parameter bitwidth=32; 10 | 11 | input [1:0] sel; 12 | input [bitwidth-1:0] a, b, c; 13 | output [bitwidth-1:0] y; 14 | reg [bitwidth-1:0] y; 15 | 16 | always @(*) begin 17 | case (sel) 18 | 2'b00 : y = a; 19 | 2'b01 : y = b; 20 | 2'b10 : y = c; 21 | endcase 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/yosys/write-smt-tb.ys: -------------------------------------------------------------------------------- 1 | 2 | # Read in the design 3 | read_verilog -formal -I../../work/ -I../../verif/formal \ 4 | ../../rtl/coprocessor/*; 5 | 6 | # Top level formal testbench. 7 | read_verilog -formal -I../../work/ -I../../rtl/coprocessor \ 8 | ../../verif/formal/*.v; 9 | 10 | read_verilog -formal -I../../work/ -I../../verif/formal \ 11 | ../../verif/tb/tb_formal.v; 12 | 13 | # Get setup to use the yosys_tb as the top module. The -nordff flag stops 14 | # the memory_dff command (run as part of prep) from merging flipflops into 15 | # memory read ports. 16 | prep -top tb_formal; 17 | 18 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-03.v: -------------------------------------------------------------------------------- 1 | module test(clk, in1, in2, out); 2 | // @annot{taint_source(in1)} 3 | // @annot{taint_source(in2)} 4 | // @annot{taint_sink(out)} 5 | 6 | // @annot{sanitize(cond)} 7 | // @annot{sanitize_glob(in2)} 8 | 9 | input clk, in1, in2; 10 | output out; 11 | 12 | reg out, cond, in1_1; 13 | 14 | always @(posedge clk) 15 | in1_1 <= in1; 16 | 17 | always @(posedge clk) 18 | cond <= in2; 19 | 20 | always @(posedge clk) 21 | if (cond) begin 22 | out <= 0; 23 | end else begin 24 | out <= in1_1; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-secverilog-neg-02.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "in", 7 | "wallclock" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "out" 14 | ] 15 | }, 16 | { 17 | "type": "always_eq", 18 | "variables": [ 19 | "in" 20 | ] 21 | }, 22 | { 23 | "type": "initial_eq", 24 | "variables": [ 25 | "in", 26 | "inH", 27 | "out", 28 | "state", 29 | "wallclock" 30 | ] 31 | } 32 | ] 33 | } 34 | -------------------------------------------------------------------------------- /test/verilog/neg/secverilog-neg-01.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | 4 | // {H} 5 | // @annot{taint_source(in)} 6 | // @annot{sanitize(in)} 7 | reg in; 8 | 9 | // {H} 10 | // @annot{taint_sink(out)} 11 | reg out; 12 | 13 | // if you enable the following annotation, it passes 14 | // otherwise, it fails 15 | // @annot-not{sanitize(slow)} 16 | reg slow; 17 | 18 | // {H} 19 | reg tmp; 20 | 21 | always @(posedge(clk)) begin 22 | if (slow) begin 23 | tmp <= in; 24 | out <= tmp; 25 | end 26 | else 27 | out <= in; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-neg-test-11.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x", 7 | "y" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "z" 14 | ] 15 | }, 16 | { 17 | "type": "assert_eq", 18 | "variables": [ 19 | "z" 20 | ] 21 | }, 22 | { 23 | "type": "always_eq", 24 | "variables": [ 25 | "x" 26 | ] 27 | }, 28 | { 29 | "type": "initial_eq", 30 | "variables": [ 31 | "z" 32 | ] 33 | } 34 | ] 35 | } 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/19-random.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.rngseed c1 11 | xc.rngsamp c2 12 | xc.rngsamp c3 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.rngsamp c2 19 | xc.rngseed c1 20 | xc.rngsamp c3 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.rngtest x2 27 | xc.rngtest x1 28 | xc.rngtest x3 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-control_pipeline.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "ALUSrc", 7 | "Branch", 8 | "Jump", 9 | "MemRead", 10 | "MemWrite", 11 | "MemtoReg", 12 | "RegDst", 13 | "RegWrite" 14 | ] 15 | }, 16 | { 17 | "type": "sink", 18 | "variables": [ 19 | "ALUSrc", 20 | "Branch", 21 | "Jump", 22 | "MemRead", 23 | "MemWrite", 24 | "MemtoReg", 25 | "RegDst", 26 | "RegWrite" 27 | ] 28 | } 29 | ] 30 | } 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_xcr2gpr.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_xcr2gpr) 14 | 15 | // 16 | // xcr2gpr 17 | // 18 | `VTX_CHECK_INSTR_BEGIN(xcr2gpr) 19 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 20 | `VTX_ASSERT_WEN_IS_SET 21 | `VTX_ASSERT_WDATA_IS(vtx_cprs_pre[dec_arg_crs1]) 22 | `VTX_ASSERT_WADDR_IS(dec_arg_rd ) 23 | `VTX_CHECK_INSTR_END(xcr2gpr) 24 | 25 | `VTX_CHECKER_MODULE_END 26 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-0.v: -------------------------------------------------------------------------------- 1 | // module example(clk, in1, in2, out); 2 | module example(clk, out); 3 | input wire clk; 4 | // input wire [3:0] in1, in2; 5 | reg [3:0] in1, in2; 6 | output reg [3:0] out; 7 | wire fast; 8 | reg [3:0] temp; 9 | 10 | // @annot{taint_source(in1)} 11 | // @annot{taint_source(in2)} 12 | // @annot{taint_sink(out)} 13 | 14 | always @(posedge clk) begin 15 | temp <= in1 + in2; 16 | end 17 | 18 | assign fast = (in1 | in2) == 0; 19 | 20 | always @(posedge clk) begin 21 | if (fast) 22 | out <= 0; 23 | else 24 | out <= temp; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /benchmarks/fpu/verilog/div_r2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module div_r2(clk, opa, opb, quo, rem); 4 | input clk; 5 | input [49:0] opa; 6 | input [23:0] opb; 7 | output [49:0] quo, rem; 8 | 9 | // @annot{taint_source(opa)} 10 | // @annot{taint_source(opb)} 11 | 12 | // @annot{taint_sink(quo)} 13 | // @annot{taint_sink(rem)} 14 | 15 | reg [49:0] quo, rem, quo1, remainder; 16 | 17 | always @(posedge clk) 18 | quo1 <= #1 opa / opb; 19 | 20 | always @(posedge clk) 21 | quo <= #1 quo1; 22 | 23 | always @(posedge clk) 24 | remainder <= #1 opa % opb; 25 | 26 | always @(posedge clk) 27 | rem <= #1 remainder; 28 | 29 | endmodule 30 | 31 | 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/Makefile: -------------------------------------------------------------------------------- 1 | SOURCES = implementation.tex 2 | TARGETS = $(patsubst %.tex, %.pdf, ${SOURCES}) 3 | 4 | DIA_IN = $(shell find -name "*.dot") 5 | DIA_OUT = $(DIA_IN:%.dot=%.eps) 6 | 7 | 8 | ${TARGETS} : $(DIA_OUT) 9 | ${TARGETS} : %.pdf : %.tex 10 | @pdflatex ${*}.tex 11 | @biber ${*} 12 | @pdflatex ${*}.tex 13 | @biber ${*} 14 | @pdflatex ${*}.tex 15 | 16 | all : ${TARGETS} 17 | 18 | diagrams: $(DIA_OUT) 19 | diagrams/%.eps : diagrams/%.dot 20 | dot -Tps $< > $@ 21 | 22 | clean : 23 | @rm -f *.aux *.bbl *.bcf *.blg *.log *.out *.pdf *.version *.xml *.toc *.bak 24 | spotless : clean 25 | @rm -f *.pdf 26 | -------------------------------------------------------------------------------- /test/verilog/neg/annot-neg-test-2.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x" 7 | ] 8 | }, 9 | { 10 | "type": "sink", 11 | "variables": [ 12 | "y" 13 | ] 14 | }, 15 | { 16 | "type": "always_eq", 17 | "variables": [ 18 | "x" 19 | ] 20 | }, 21 | { 22 | "type": "initial_eq", 23 | "variables": [ 24 | "Stall" 25 | ] 26 | }, 27 | { 28 | "type": "initial_eq", 29 | "variables": [ 30 | "val" 31 | ], 32 | "module": "reg_file" 33 | } 34 | ] 35 | } 36 | -------------------------------------------------------------------------------- /test/verilog/pos/annot-tr-test-11.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "x", 7 | "y" 8 | ] 9 | }, 10 | { 11 | "type": "sink", 12 | "variables": [ 13 | "z" 14 | ] 15 | }, 16 | { 17 | "type": "assert_eq", 18 | "variables": [ 19 | "z" 20 | ] 21 | }, 22 | { 23 | "type": "always_eq", 24 | "variables": [ 25 | "x", 26 | "y" 27 | ] 28 | }, 29 | { 30 | "type": "initial_eq", 31 | "variables": [ 32 | "z" 33 | ] 34 | } 35 | ] 36 | } 37 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_ld_hiu.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_ld_hiu) 14 | 15 | wire [15:0] ld_hi_imm = {dec_arg_imm11,dec_arg_imm5}; 16 | 17 | // 18 | // ld_hi 19 | // 20 | `VTX_CHECK_INSTR_BEGIN(ld_hiu) 21 | `VTX_ASSERT_CRD_VALUE_IS({ld_hi_imm,vtx_crd_val_pre[15: 0]}) 22 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 23 | `VTX_ASSERT_WEN_IS_CLEAR 24 | `VTX_CHECK_INSTR_END(ld_hiu) 25 | 26 | `VTX_CHECKER_MODULE_END 27 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_ld_liu.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_ld_liu) 14 | 15 | wire [15:0] ld_li_imm = {dec_arg_imm11,dec_arg_imm5}; 16 | 17 | // 18 | // ld_li 19 | // 20 | `VTX_CHECK_INSTR_BEGIN(ld_liu) 21 | `VTX_ASSERT_CRD_VALUE_IS({vtx_crd_val_pre[31:16],ld_li_imm}) 22 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 23 | `VTX_ASSERT_WEN_IS_CLEAR 24 | `VTX_CHECK_INSTR_END(ld_liu) 25 | 26 | `VTX_CHECKER_MODULE_END 27 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/04-ins-ext.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c0, x0 7 | xc.gpr2xcr c1, x1 8 | xc.gpr2xcr c2, x2 9 | xc.gpr2xcr c3, x3 10 | 11 | xc.ld.liu c4, 0x1234 12 | xc.ld.hiu c4, 0x567a 13 | 14 | xc.ld.hiu c5, 0 15 | xc.ld.liu c5, 0 16 | 17 | xc.ext c5, c4, 2, 4 18 | 19 | xc.ld.liu c6, 0xFF00 20 | xc.ld.hiu c6, 0x0000 21 | xc.ext c7, c6, 4, 8 22 | 23 | xc.ld.hiu c8, 0 24 | xc.ld.liu c8, 0 25 | xc.ins c8, c7, 4, 8 26 | 27 | xc.xcr2gpr x0, c4 28 | xc.xcr2gpr x1, c5 29 | xc.xcr2gpr x2, c6 30 | xc.xcr2gpr x3, c7 31 | xc.xcr2gpr x3, c8 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/Makefile: -------------------------------------------------------------------------------- 1 | 2 | OUT_DIR ?= $(XC_WORK)/unit 3 | 4 | INPUTS ?= $(shell find -name "*.S") 5 | OUTPUTS ?= $(addprefix $(OUT_DIR)/, $(INPUTS:%.S=%.hex)) 6 | 7 | AS = $(XC_HOME)/work/riscv-binutils-gdb/build/gas/as-new 8 | OBJDUMP = $(XC_HOME)/work/riscv-binutils-gdb/build/binutils/objdump 9 | 10 | all: $(OUTPUTS) 11 | 12 | $(OUT_DIR)/%.o : %.S 13 | @mkdir -p $(OUT_DIR) 14 | $(AS) -march=rv32ix -o $@ $< 15 | 16 | $(OUT_DIR)/%.hex : $(OUT_DIR)/%.o 17 | $(OBJDUMP) -D -j.text $< | grep -P ":\t" > $@ 18 | sed -i 's/ .*$///' $@ 19 | sed -i 's/^.*:\t//' $@ 20 | 21 | clean: 22 | rm -rf $(OUTPUTS) 23 | -------------------------------------------------------------------------------- /scripts/line_count.sh: -------------------------------------------------------------------------------- 1 | #!/bin/zsh 2 | 3 | if [[ $# -ne 1 ]]; then 4 | echo "usage $0 " >&2 5 | exit 1 6 | fi 7 | 8 | FILENAME="$1" 9 | 10 | THIS_DIR="${0:A:h}" 11 | 12 | # ------------------------------------------------------------------------------ 13 | 14 | echo "number of lines:" 15 | 16 | pushd ${FILENAME:h} 17 | ${THIS_DIR}/remove_comments.sh ${FILENAME:t} | wc -l 18 | popd 19 | 20 | # ------------------------------------------------------------------------------ 21 | 22 | echo "number of annots:" 23 | 24 | grep '@annot{' $FILENAME | wc -l 25 | 26 | # ------------------------------------------------------------------------------ 27 | 28 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/annot-reg_file.json: -------------------------------------------------------------------------------- 1 | { 2 | "annotations": [ 3 | { 4 | "type": "source", 5 | "variables": [ 6 | "RN1", 7 | "RN2", 8 | "WN", 9 | "WD", 10 | "RegWrite" 11 | ] 12 | }, 13 | { 14 | "type": "sink", 15 | "variables": [ 16 | "RD1", 17 | "RD2" 18 | ] 19 | }, 20 | { 21 | "type": "always_eq", 22 | "variables": [ 23 | "RN1", 24 | "RN2", 25 | "WN", 26 | "RegWrite" 27 | ] 28 | }, 29 | { 30 | "type": "initial_eq", 31 | "variables": [ 32 | "file_array" 33 | ] 34 | } 35 | ] 36 | } 37 | -------------------------------------------------------------------------------- /examples/fp/test02.fq: -------------------------------------------------------------------------------- 1 | qualif Bla(x:int, y:int) : (x = y) 2 | 3 | bind 1 x : {v: int | true } 4 | bind 2 y : {v: int | true } 5 | 6 | 7 | constraint: 8 | env [1] 9 | lhs {v : int | x=1 || x=2} 10 | rhs {v : int | $inv0[arg1_0 := x]} 11 | id 1 tag [] 12 | 13 | constraint: 14 | env [2] 15 | lhs {v : int | y=1 || y=2} 16 | rhs {v : int | $inv1[arg1_1 := y]} 17 | id 2 tag [] 18 | 19 | constraint: 20 | env [1;2] 21 | lhs {v : int | [$inv0[arg1_0 := x]; $inv1[arg1_1 := y]]} 22 | rhs {v : int | x=y} 23 | id 3 tag [] 24 | 25 | wf: 26 | env [] 27 | reft {arg1_0 : int | $inv0 } 28 | 29 | wf: 30 | env [] 31 | reft {arg1_1 : int | $inv1 } 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/41-sha3.S: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | xc.sha3.xy a2, t0, t1, 0 6 | xc.sha3.xy a2, t0, t1, 1 7 | xc.sha3.xy a2, t0, t1, 2 8 | xc.sha3.xy a2, t0, t1, 3 9 | 10 | xc.sha3.x1 a2, t0, t1, 0 11 | xc.sha3.x1 a2, t0, t1, 1 12 | xc.sha3.x1 a2, t0, t1, 2 13 | xc.sha3.x1 a2, t0, t1, 3 14 | 15 | xc.sha3.x2 a2, t0, t1, 0 16 | xc.sha3.x2 a2, t0, t1, 1 17 | xc.sha3.x2 a2, t0, t1, 2 18 | xc.sha3.x2 a2, t0, t1, 3 19 | 20 | xc.sha3.x4 a2, t0, t1, 0 21 | xc.sha3.x4 a2, t0, t1, 1 22 | xc.sha3.x4 a2, t0, t1, 2 23 | xc.sha3.x4 a2, t0, t1, 3 24 | 25 | xc.sha3.yx a2, t0, t1, 0 26 | xc.sha3.yx a2, t0, t1, 1 27 | xc.sha3.yx a2, t0, t1, 2 28 | xc.sha3.yx a2, t0, t1, 3 29 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/common/linker.ld: -------------------------------------------------------------------------------- 1 | 2 | SECTIONS { 3 | /* Trampoline for getting to the reset handler */ 4 | .text 0xC0000000 : { *(.text.boot_vector) } 5 | 6 | /* Trampoline for getting to the interrupt handler */ 7 | .text 0xC0000010 : { *(.text.irq_vector) } 8 | 9 | /* Pass and Fail addresses */ 10 | .text : { *(.text.__fail) } 11 | .text : { *(.text.__pass) } 12 | 13 | /* The rest of the program code goes here */ 14 | .text : { *(.text.*) } 15 | .data : { *(.data) } 16 | .bss : { *(.bss ) } 17 | 18 | /* Don't include the .comment section anywhere */ 19 | /DISCARD/ : { *(.comment) } 20 | } 21 | 22 | 23 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-4.v: -------------------------------------------------------------------------------- 1 | module test(clk, x); 2 | input clk; 3 | input x; 4 | 5 | // @annot{sanitize(ex_res)} 6 | // @annot{taint_source(ex_inst)} 7 | reg ex_inst; 8 | 9 | reg ex_ld_res; 10 | 11 | // @annot{sanitize(ex_res)} 12 | reg ex_res; 13 | 14 | // @annot{sanitize(wb_wbv, ex_wbv)} 15 | // @annot{taint_sink(wb_wbv)} 16 | reg wb_wbv, ex_wbv; 17 | 18 | always @(*) 19 | ex_ld_res[1:0] = x; 20 | 21 | always @(*) 22 | ex_ld_res[2:0] = x; 23 | 24 | always @(*) ex_wbv = ex_inst[0] == 0 ? ex_ld_res : ex_res; 25 | 26 | always @(posedge clk) begin 27 | wb_wbv <= ex_wbv; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/examples/integration-test/integration-test.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | 4 | #include "common.h" 5 | 6 | extern void __move_to_cop(uint32_t a); 7 | extern uint32_t __move_to_gpr(); 8 | 9 | int main() { 10 | 11 | int sum = 0; 12 | 13 | for(int i = 0; i < 20; i ++) { 14 | 15 | int original = sum; 16 | 17 | __move_to_cop(sum); 18 | 19 | sum += i; 20 | 21 | int new = __move_to_gpr(); 22 | 23 | if((original + i) != sum) { 24 | __fail(); 25 | } 26 | 27 | if(new != original) { 28 | __fail(); 29 | } 30 | 31 | } 32 | 33 | __pass(); 34 | } 35 | -------------------------------------------------------------------------------- /benchmarks/yarvi/XuLA2/xula2.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullNone 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullNone 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:JtagClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/yosys/write-verilog.ys: -------------------------------------------------------------------------------- 1 | 2 | # Read in the design 3 | read_verilog -I../../work/ ../../rtl/coprocessor/* 4 | read_verilog ../../external/picorv32/picorv32.v 5 | read_verilog -I../../work/ ../../rtl/integration/* 6 | 7 | # Synthesise processes ready for SCC check. 8 | proc 9 | 10 | # Check that there are no logic loops in the design early on. 11 | tee -o ../../work/logic-loops.rpt check -assert 12 | 13 | # Generic yosys synthesis command 14 | synth -top scarv_prv_xcrypt_top 15 | 16 | # Print some statistics out 17 | tee -o ../../work/synth-statistics.rpt stat -width 18 | 19 | # Write out the synthesised verilog 20 | write_verilog ../../work/scarv_cop_top.v 21 | -------------------------------------------------------------------------------- /scripts/remove_comments.sh: -------------------------------------------------------------------------------- 1 | #!/bin/zsh 2 | 3 | zparseopts -D -E -- \ 4 | -trailing=TRAILING 5 | 6 | if [[ $# -ne 1 ]]; then 7 | echo "usage $0 " >&2 8 | exit 1 9 | fi 10 | 11 | FILENAME="$1" 12 | 13 | THIS_DIR="${0:A:h}" 14 | 15 | IVLPP="$THIS_DIR/../../iverilog-parser/ivlpp/ivlpp" 16 | 17 | preproc() { 18 | # if [[ which ivlpp &>/dev/null ]]; then 19 | # ivlpp $1 20 | # else 21 | # cat $1 22 | # fi 23 | cat $1 24 | } 25 | 26 | preproc $FILENAME | \ 27 | sed -e '/^[[:space:]]*\/\//d' $FILENAME | \ 28 | sed -r ':a; s%(.*)/\*.*\*/%\1%; ta; /\/\*/ !b; N; ba' | \ 29 | sed '/^[[:space:]]*$/d' | \ 30 | { [[ -n "$TRAILING" ]] && sed -e 's/[[:space:]]*\/\/.*$//' || cat } 31 | 32 | -------------------------------------------------------------------------------- /benchmarks/crypto_cores/RSA4096/ModExp2/mul_add.v: -------------------------------------------------------------------------------- 1 | // (multiplication, addition) component for MonPro 2 | `include "_parameter.v" 3 | 4 | module mul_add 5 | ( 6 | input clk, 7 | input [`DATA_WIDTH - 1 : 0] x, 8 | input [`DATA_WIDTH - 1 : 0] y, 9 | input [`DATA_WIDTH - 1 : 0] z, 10 | input [`DATA_WIDTH - 1 : 0] last_c, 11 | output [`DATA_WIDTH - 1 : 0] s, // lower output 12 | output [`DATA_WIDTH - 1 : 0] c // higher output 13 | ); 14 | 15 | // Declare input and output registers 16 | wire [2 * `DATA_WIDTH - 1 : 0] mult_out; 17 | assign mult_out = x * y + z + last_c; 18 | assign s = mult_out[`DATA_WIDTH - 1 : 0]; 19 | assign c = mult_out[2 * `DATA_WIDTH - 1 : `DATA_WIDTH]; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /examples/verilog/modular.v: -------------------------------------------------------------------------------- 1 | module modular(clk); 2 | input clk, slow; 3 | reg slow; // @annot{sanitize(v_slow)} 4 | reg x; // @annot{taint_source(v_x)} 5 | reg y; 6 | reg z; // @annot{taint_sink(v_y)} 7 | reg a; 8 | reg b; 9 | 10 | always @(posedge clk) 11 | if (slow == 1) 12 | y <= x; 13 | else 14 | z <= x; 15 | 16 | always @(posedge clk) 17 | if (slow) 18 | z <= y; 19 | 20 | other OTHER(clk); 21 | 22 | endmodule 23 | 24 | module other(clk); 25 | input clk; 26 | reg a; 27 | reg b; 28 | 29 | always @(posedge clk) 30 | a <= b; 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/top-level-fsm.dot: -------------------------------------------------------------------------------- 1 | 2 | digraph G { 3 | 4 | IDLE [label="FSM_IDLE"]; 5 | WAITING [label="FSM_WAITING"]; 6 | EXECUTING [label="FSM_EXECUTING"]; 7 | FINISHED [label="FSM_FINISHED"]; 8 | 9 | 10 | IDLE -> WAITING [label="always"]; 11 | 12 | WAITING -> FINISHED[label="single-cycle instr"]; 13 | WAITING -> EXECUTING[label="multi-cycle instr"]; 14 | WAITING -> WAITING[label="no instr"]; 15 | 16 | EXECUTING -> FINISHED[label="Execution complete"]; 17 | EXECUTING -> EXECUTING[label="Executing / stalled"]; 18 | 19 | FINISHED -> WAITING[label="Instruction retired"]; 20 | FINISHED -> FINISHED[label="Waiting for CPU"]; 21 | 22 | } 23 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_correct_invalid_opcode_response.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_common.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(correct_invalid_opcode_response) 15 | 16 | // 17 | // Check that we always correctly get a BAD_INS result on an invalid opcode. 18 | // 19 | `VTX_CHECK_BEGIN(correct_invalid_opcode_response) 20 | if(dec_invalid_opcode) begin 21 | `VTX_ASSERT(vtx_instr_result == SCARV_COP_INSN_BAD_INS); 22 | end 23 | `VTX_CHECK_END(correct_invalid_opcode_response) 24 | 25 | `VTX_CHECKER_MODULE_END 26 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-04.v: -------------------------------------------------------------------------------- 1 | module test(clk, in, a, out); 2 | // @annot{taint_source(in)} 3 | // @annot{taint_source(a)} 4 | 5 | // @annot{taint_sink(out)} 6 | 7 | // @annot{sanitize(cond1)} 8 | // @annot{sanitize(cond2)} 9 | // @annot{sanitize_glob(a)} 10 | 11 | input clk, in, a; 12 | output out; 13 | 14 | reg out; 15 | 16 | reg in_1, cond1, cond2; 17 | 18 | always @(posedge clk) begin 19 | in_1 <= in; 20 | cond1 <= (a & 1'hF) == 1'h0; 21 | cond2 <= (a & 1'hF) == 1'hA; 22 | end 23 | 24 | always @(posedge clk) 25 | if (cond1 && cond2) begin 26 | out <= 0; 27 | end else begin 28 | out <= in_1; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_macc_1.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_macc_1) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // macc_1 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(macc_1) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = `CRDM + `CRS1; 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(macc_1) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_cmov_f.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_cmov_f) 14 | 15 | // 16 | // cmov_f 17 | // 18 | `VTX_CHECK_INSTR_BEGIN(cmov_f) 19 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 20 | `VTX_ASSERT_WEN_IS_CLEAR 21 | 22 | if(vtx_crs2_val_pre == 0) begin 23 | `VTX_ASSERT_CRD_VALUE_IS(vtx_crs1_val_pre) 24 | end else begin 25 | `VTX_ASSERT_CRD_VALUE_IS(vtx_crd_val_pre) 26 | end 27 | 28 | `VTX_CHECK_INSTR_END(cmov_f) 29 | 30 | `VTX_CHECKER_MODULE_END(instr_cmov_f) 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_cmov_t.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_cmov_t) 14 | 15 | // 16 | // cmov_t 17 | // 18 | `VTX_CHECK_INSTR_BEGIN(cmov_t) 19 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 20 | `VTX_ASSERT_WEN_IS_CLEAR 21 | 22 | if(vtx_crs2_val_pre != 0) begin 23 | `VTX_ASSERT_CRD_VALUE_IS(vtx_crs1_val_pre) 24 | end else begin 25 | `VTX_ASSERT_CRD_VALUE_IS(vtx_crd_val_pre) 26 | end 27 | 28 | `VTX_CHECK_INSTR_END(cmov_t) 29 | 30 | `VTX_CHECKER_MODULE_END(instr_cmov_t) 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_madd_2.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_madd_2) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // madd_2 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(madd_2) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = (`CRS1 + `CRS2); 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(madd_2) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_msub_2.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_msub_2) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // msub_2 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(msub_2) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = (`CRS1 - `CRS2); 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(msub_2) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_macc_2.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_macc_2) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // macc_2 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(macc_2) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = (`CRDM + `CRS1) + `CRS2; 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(macc_2) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_madd_3.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_madd_3) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // madd_3 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(madd_3) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = (`CRS1 + `CRS2) + `CRS3; 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(madd_3) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/31-equ-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0x1111 7 | xc.ld.liu c0, 0x1111 8 | xc.ld.hiu c1, 0x2222 9 | xc.ld.liu c1, 0x2222 10 | xc.ld.hiu c2, 0x0000 11 | xc.ld.liu c2, 0x0000 12 | xc.ld.hiu c3, 0x3333 13 | xc.ld.liu c3, 0x3333 14 | 15 | xc.mequ x0 , x0, c0, c3 16 | xc.mequ x1 , x1, c1, c1 17 | xc.mequ x2 , x9, c2, c1 18 | xc.mequ x3 , x0, c3, c2 19 | xc.mequ x4 , x4, c0, c0 20 | xc.mequ x5 , x3, c1, c2 21 | xc.mequ x16, x2, c2, c3 22 | xc.mequ x15, x1, c3, c3 23 | 24 | xc.xcr2gpr x16, c0 25 | xc.xcr2gpr x16, c1 26 | xc.xcr2gpr x16, c2 27 | xc.xcr2gpr x16, c3 28 | xc.xcr2gpr x16, c4 29 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/32-ltu-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0x1111 7 | xc.ld.liu c0, 0x1111 8 | xc.ld.hiu c1, 0x2222 9 | xc.ld.liu c1, 0x2222 10 | xc.ld.hiu c2, 0x0000 11 | xc.ld.liu c2, 0x0000 12 | xc.ld.hiu c3, 0x3333 13 | xc.ld.liu c3, 0x3333 14 | 15 | xc.mlte x0 , x0, c0, c3 16 | xc.mlte x1 , x1, c1, c0 17 | xc.mlte x2 , x9, c2, c1 18 | xc.mlte x3 , x0, c3, c2 19 | xc.mlte x4 , x4, c0, c1 20 | xc.mlte x5 , x3, c1, c2 21 | xc.mlte x16, x2, c2, c3 22 | xc.mlte x15, x1, c3, c0 23 | 24 | xc.xcr2gpr x16, c0 25 | xc.xcr2gpr x16, c1 26 | xc.xcr2gpr x16, c2 27 | xc.xcr2gpr x16, c3 28 | xc.xcr2gpr x16, c4 29 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/33-gtu-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0x1111 7 | xc.ld.liu c0, 0x1111 8 | xc.ld.hiu c1, 0x2222 9 | xc.ld.liu c1, 0x2222 10 | xc.ld.hiu c2, 0x0000 11 | xc.ld.liu c2, 0x0000 12 | xc.ld.hiu c3, 0x3333 13 | xc.ld.liu c3, 0x3333 14 | 15 | xc.mgte x0 , x0, c0, c3 16 | xc.mgte x1 , x1, c1, c0 17 | xc.mgte x2 , x9, c2, c1 18 | xc.mgte x3 , x0, c3, c2 19 | xc.mgte x4 , x4, c0, c1 20 | xc.mgte x5 , x3, c1, c2 21 | xc.mgte x16, x2, c2, c3 22 | xc.mgte x15, x1, c3, c0 23 | 24 | xc.xcr2gpr x16, c0 25 | xc.xcr2gpr x16, c1 26 | xc.xcr2gpr x16, c2 27 | xc.xcr2gpr x16, c3 28 | xc.xcr2gpr x16, c4 29 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_msub_3.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_msub_3) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // msub_3 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(msub_3) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = (`CRS1 - `CRS2) - `CRS3[0]; 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(msub_3) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/yarvi/shared/Makefile.common: -------------------------------------------------------------------------------- 1 | # Adjust to match your RISC-V toolchain 2 | RVPATH=/opt/rv32/bin/ 3 | RVPREFIX=$(RVPATH)riscv32-unknown-elf- 4 | CC=$(RVPREFIX)gcc -std=gnu99 -m32 -O 5 | 6 | %.txt: % 7 | $(RVPREFIX)objcopy -O binary $^ mem.bin 8 | (dd if=/dev/zero bs=256 count=1 2>/dev/null;cat mem.bin)|hexdump -ve '"%08x\n"' >mem.hex 9 | cut -c1-2 mem.hex > mem3.txt 10 | cut -c3-4 mem.hex > mem2.txt 11 | cut -c5-6 mem.hex > mem1.txt 12 | cut -c7-8 mem.hex > mem0.txt 13 | cp $(COMMON)/initregs.txt . 14 | 15 | %.riscv: $(COMMON)crt0.o %.o 16 | $(RVPREFIX)ld -T$(COMMON)yarvi.ld -melf32lriscv -o $@ $^ 17 | 18 | %.bin: %.riscv 19 | $(RVPREFIX)objcopy -O binary $^ $@ 20 | 21 | %.riscv.dis: %.riscv 22 | $(RVPREFIX)objdump -d $^ > $@ 23 | -------------------------------------------------------------------------------- /test/verilog/neg/tp.v: -------------------------------------------------------------------------------- 1 | module test(clk, in1, in2, out); 2 | input wire clk; 3 | input wire [1:0] in1; 4 | input wire [1:0] in2; 5 | output reg [1:0] out = 2; 6 | wire fast; 7 | reg [1:0] temp1 = 3; 8 | 9 | // @annot{taint_source(in1)} 10 | // @annot{taint_source(in2)} 11 | // @annot{taint_sink(out)} 12 | 13 | // @annot{qualifierImp(temp1, [in1, in2])} 14 | // @annot{qualifierPairs([temp1, fast])} 15 | 16 | assign fast = (in1 | in2) == 0; 17 | 18 | always @ (posedge clk) begin 19 | temp1 <= in1 + in2; 20 | end 21 | 22 | always @ (posedge clk) begin 23 | if (fast) 24 | out <= 0; 25 | else 26 | out <= temp1; 27 | end 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_msll_i.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_msll_i) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // msll_i 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(msll_i) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = {`CRS2 , `CRS1} << dec_arg_cmshamt; 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(msll_i) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_msrl_i.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_msrl_i) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // msrl_i 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(msrl_i) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = {`CRS2 , `CRS1} >> dec_arg_cmshamt; 26 | 27 | `VTX_ASSERT_CRDM_VALUE_IS(value) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(msrl_i) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/icarus/manifest.cmd: -------------------------------------------------------------------------------- 1 | +incdir+$(XC_HOME)/rtl/coprocessor 2 | +incdir+$(XC_HOME)/verif/formal 3 | $(XC_HOME)/rtl/coprocessor/scarv_cop_aes_sbox.v 4 | $(XC_HOME)/rtl/coprocessor/scarv_cop_aes.v 5 | $(XC_HOME)/rtl/coprocessor/scarv_cop_cprs.v 6 | $(XC_HOME)/rtl/coprocessor/scarv_cop_idecode.v 7 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu.v 8 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu_adder.v 9 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu_shifter.v 10 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu_multiplier.v 11 | $(XC_HOME)/rtl/coprocessor/scarv_cop_malu.v 12 | $(XC_HOME)/rtl/coprocessor/scarv_cop_rng.v 13 | $(XC_HOME)/rtl/coprocessor/scarv_cop_mem.v 14 | $(XC_HOME)/rtl/coprocessor/scarv_cop_top.v 15 | $(XC_HOME)/verif/tb/tb_scarv_cop_top.v 16 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/mem32-stub.v: -------------------------------------------------------------------------------- 1 | module mem32(clk, mem_read, mem_write, address, data_in, data_out); 2 | // Sources: 3 | // @annot{sanitize_glob(mem_read)} 4 | // @annot{taint_eq(mem_write)} 5 | // @annot{taint_eq(address)} 6 | // @annot{taint_eq(data_in)} 7 | // Sinks: 8 | // @annot{taint_source(data_out)} 9 | // @annot{taint_sink(data_out)} 10 | 11 | input clk, mem_read, mem_write; 12 | input [31:0] address, data_in; 13 | output [31:0] data_out; 14 | reg [31:0] data_out; 15 | 16 | reg [31:0] mem_array [0:31]; 17 | 18 | always @(posedge clk) begin 19 | if (mem_read == 1'b1) 20 | data_out <= mem_array[address]; 21 | else 22 | data_out <= 32'hxxxxxxxx; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cpu-cop-if-2.wd: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'g_clk' , wave: 'p.......|......'}, 3 | ["Request", 4 | {name: 'cpu_insn_req', wave: '01.110..|.1110.'}, 5 | {name: 'cpu_insn_enc', wave: 'x3.45x..|.345x.',}, 6 | {name: 'cpu_rs1' , wave: 'x3.45x..|.345x.',}, 7 | {name: 'cop_insn_ack', wave: '0.1110..|1.110.'}, 8 | ], 9 | ["Response", 10 | {name: 'cop_insn_rsp', wave: '0.1011.0|..1110'}, 11 | {name: 'cop_wen' , wave: 'x.0x11.x|..011x'}, 12 | {name: 'cop_waddr' , wave: 'x...45.x|..x45x'}, 13 | {name: 'cop_wdata' , wave: 'x...45.x|..x45x'}, 14 | {name: 'cop_result ', wave: 'x...45.x|..x45x'}, 15 | {name: 'cop_insn_ack', wave: '01...010|..1110'}, 16 | ], 17 | ], 18 | head:{ 19 | tick:0, 20 | },} 21 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .stack-work/ 2 | .stack-work-profile/ 3 | /iodine.cabal 4 | configuration.sh 5 | .*.pl 6 | .*.preproc.v 7 | .*.smt2 8 | .log* 9 | flycheck_* 10 | 11 | /*.prof 12 | /*.prof.html 13 | 14 | .liquid/ 15 | .*.fq 16 | 17 | [._]*.s[a-v][a-z] 18 | [._]*.sw[a-p] 19 | [._]s[a-v][a-z] 20 | [._]sw[a-p] 21 | Session.vim 22 | .netrwhist 23 | *~ 24 | tags 25 | *~ 26 | \#*\# 27 | /.emacs.desktop 28 | /.emacs.desktop.lock 29 | *.elc 30 | auto-save-list 31 | tramp 32 | .\#* 33 | .org-id-locations 34 | *_archive 35 | *_flymake.* 36 | /eshell/history 37 | /eshell/lastdir 38 | /elpa/ 39 | *.rel 40 | /auto/ 41 | .cask/ 42 | dist/ 43 | flycheck_*.el 44 | /server/ 45 | .projectile 46 | .dir-locals.el 47 | 48 | /.test-report.txt 49 | 50 | *.annot 51 | 52 | cplex.json 53 | 54 | .vscode/ 55 | -------------------------------------------------------------------------------- /scripts/linprog/testing.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from utils import parse_cplex_input 4 | 5 | 6 | parsed = parse_cplex_input("cplex.json") 7 | g = parsed["graph"] 8 | names = parsed["names"] 9 | inv_names = parsed["inv_names"] 10 | is_reg = parsed["is_reg"] 11 | must_eq = parsed["must_eq"] 12 | 13 | 14 | def is_direct_edge(u, v): 15 | for _, data in g.get_edge_data(u, v).items(): 16 | t = data["type"] 17 | if t == "Direct": 18 | return True 19 | return False 20 | 21 | 22 | def is_implicit_edge(u, v): 23 | for _, data in g.get_edge_data(u, v).items(): 24 | t = data["type"] 25 | if t == "Implicit": 26 | return True 27 | return False 28 | 29 | 30 | for n in must_eq: 31 | print(names[n]) 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/cpu-cop-if-1.wd: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'g_clk' , wave: 'p...|....|......'}, 3 | ["Request", 4 | {name: 'cpu_insn_req', wave: '01.0|.10.|.10...'}, 5 | {name: 'cpu_insn_enc', wave: 'x3.x|.4x.|.5x...',}, 6 | {name: 'cpu_rs1' , wave: 'x3.x|.4x.|.5x...',}, 7 | {name: 'cop_insn_ack', wave: '0.10|1.0.|1.0...'}, 8 | ], 9 | ["Response", 10 | {name: 'cop_insn_rsp', wave: '0.10|..10|...1.0'}, 11 | {name: 'cop_wen' , wave: 'x.0x|..1x|...1.x'}, 12 | {name: 'cop_waddr' , wave: 'x...|..4x|...5.x'}, 13 | {name: 'cop_wdata' , wave: 'x...|..4x|...5.x'}, 14 | {name: 'cop_result ', wave: 'x...|..4x|...5.x'}, 15 | {name: 'cop_insn_ack', wave: '01..|....|0...10'}, 16 | ], 17 | ], 18 | head:{ 19 | tick:0, 20 | },} 21 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-5.v: -------------------------------------------------------------------------------- 1 | module test(clk, in_eq, in_neq); 2 | input clk, in_eq, in_neq; 3 | 4 | // @annot{taint_source(x)} 5 | // @annot{taint_source(y)} 6 | // @annot{taint_sink(out)} 7 | 8 | // @annot{sanitize_glob(in_eq)} 9 | 10 | reg x; // @annot{sanitize(x)} 11 | reg y; // @annot{sanitize(y)} 12 | reg out; 13 | 14 | reg cond1; // @annot{sanitize(cond1)} 15 | reg cond2; // @annot{sanitize(cond2)} 16 | 17 | always @(posedge clk) begin 18 | cond1 <= in_neq; 19 | cond2 <= in_eq; 20 | 21 | x <= in_eq; 22 | y <= in_eq; 23 | end 24 | 25 | always @(posedge clk) begin 26 | out <= 0; 27 | 28 | if (cond1) 29 | out <= x; 30 | 31 | if (cond2) 32 | out <= y; 33 | 34 | end 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /test/verilog/pos/merge-01.v: -------------------------------------------------------------------------------- 1 | module test(clk, opa, opb, fast, out); 2 | input wire clk; 3 | // @annot{taint_source(opa)} 4 | // @annot{taint_source(opb)} 5 | input wire [31:0] opa, opb; 6 | input wire fast; 7 | 8 | // @annot{taint_sink(out)} 9 | output reg [31:0] out; 10 | 11 | reg r; 12 | reg opa_r, opb_r; 13 | 14 | always @(posedge clk) begin 15 | opa_r <= opa; 16 | opb_r <= opa; 17 | end 18 | 19 | assign wa = opa_r[31]; 20 | assign wb = opb_r[31]; 21 | assign cond = (wa | wb) == 0; 22 | 23 | always @(posedge clk) begin 24 | r <= opa_r + opb_r; 25 | end 26 | 27 | always @(posedge clk) begin 28 | if (cond) 29 | out <= 0; 30 | else 31 | out <= r; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /test/verilog/pos/merge04.v: -------------------------------------------------------------------------------- 1 | module test(clk, in1, in2, in3, out); 2 | input wire clk, in1, in2, in3; 3 | output reg out; 4 | 5 | reg in1_r, in2_r, in3_r; 6 | reg in1_r2, in2_r2, in3_r2; 7 | reg out_tmp; 8 | 9 | always @(posedge clk) 10 | in1_r <= in1; 11 | 12 | always @(posedge clk) 13 | in2_r <= in2; 14 | 15 | always @(posedge clk) 16 | in3_r <= in3; 17 | 18 | always @(posedge clk) 19 | in1_r2 <= in1_r; 20 | 21 | always @(posedge clk) 22 | in2_r2 <= in2_r; 23 | 24 | always @(posedge clk) 25 | in3_r2 <= in3_r; 26 | 27 | always @(*) 28 | if (in3_r2) 29 | out_tmp = in1_r2; 30 | else 31 | out_tmp = in1_r2 + in2_r2; 32 | 33 | always @(posedge clk) 34 | out <= out_tmp; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /test/verilog/pos/merge03.v: -------------------------------------------------------------------------------- 1 | module test(clk, sel, opa, opb, out); 2 | input wire clk, sel; 3 | // @annot{taint_source(opa)} 4 | // @annot{taint_source(opb)} 5 | input wire [31:0] opa, opb; 6 | 7 | // @annot{taint_sink(out)} 8 | output reg [31:0] out; 9 | 10 | // @annot{qualifierPairs([opa_r, opb_r])} 11 | // @annot{qualifierPairs([r1, r2])} 12 | 13 | reg opa_r, opb_r; 14 | 15 | always @(posedge clk) 16 | opa_r <= opa; 17 | 18 | always @(posedge clk) 19 | opb_r <= opb; 20 | 21 | reg r1,r2; 22 | 23 | always @(*) 24 | r1 = opa_r + opb_r; 25 | 26 | always @(*) 27 | r2 = opa_r - opb_r; 28 | 29 | always @(posedge clk) 30 | if (sel) 31 | out <= r1; 32 | else 33 | out <= r2; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-05.v: -------------------------------------------------------------------------------- 1 | module test(clk, flag1, flag2, flag3, flag4, in, out); 2 | 3 | // @annot{taint_source(flag1)} 4 | // @annot{taint_source(flag2)} 5 | // @annot{taint_source(flag3)} 6 | // @annot{taint_source(flag4)} 7 | // @annot{taint_source(in)} 8 | 9 | // @annot{taint_sink(out)} 10 | 11 | // @annot{sanitize_glob(cond)} 12 | 13 | input clk, flag1, flag2, flag3, flag4, in; 14 | output out; 15 | 16 | reg out; 17 | 18 | reg cond, tmp; 19 | 20 | always @(posedge clk) 21 | cond <= flag1 + flag2 + flag3 + flag4; 22 | 23 | always @(posedge clk) 24 | tmp <= in; 25 | 26 | always @(posedge clk) 27 | if (cond) begin 28 | out <= 0; 29 | end else begin 30 | out <= tmp; 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /examples/fp/test01.fq: -------------------------------------------------------------------------------- 1 | qualif Bla(x:int, y:int) : (x = y) 2 | 3 | bind 1 x : {v: int | true } 4 | bind 2 y : {v: int | true } 5 | bind 4 arg2 : {v: int | true } 6 | bind 5 xo : {v: int | v=Map_select f x } 7 | bind 6 yo : {v: int | v=Map_select f y } 8 | bind 7 f : {v : Map_t Int Int | true} 9 | 10 | 11 | constraint: 12 | env [1;2] 13 | lhs {v : int | [x=y]} 14 | rhs {v : int | $inv0[arg1 := x][arg2 := y]} 15 | id 1 tag [] 16 | 17 | constraint: 18 | env [1;2;5;6;7] 19 | lhs {v : int | $inv0[arg1 := x][arg2 := y]} 20 | rhs {v : int | $inv0[arg1 := xo][arg2 := yo]} 21 | id 2 tag [] 22 | 23 | constraint: 24 | env [1;2] 25 | lhs {v : int | $inv0[arg1 := x][arg2 := y]} 26 | rhs {v : int | x=y} 27 | id 3 tag [] 28 | 29 | wf: 30 | env [4] 31 | reft {arg1 : int | $inv0 } 32 | -------------------------------------------------------------------------------- /benchmarks/fpu/verilog/mul_r2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module mul_r2(clk, opa, opb, prod); 4 | input clk; 5 | input [23:0] opa, opb; 6 | output [47:0] prod; 7 | 8 | // @annot{taint_source(opa)} 9 | // @annot{taint_source(opb)} 10 | 11 | // @annot{taint_sink(rewrite_prod)} 12 | 13 | // -------------------------------------------------------------------------------- 14 | // REWRITE 15 | // -------------------------------------------------------------------------------- 16 | reg [47:0] rewrite_prod; 17 | always @(*) begin 18 | rewrite_prod = prod; 19 | end 20 | // -------------------------------------------------------------------------------- 21 | 22 | reg [47:0] prod1, prod; 23 | 24 | always @(posedge clk) 25 | prod1 <= #1 opa * opb; 26 | 27 | always @(posedge clk) 28 | prod <= #1 prod1; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-merge-01.v: -------------------------------------------------------------------------------- 1 | module test(clk, opa, opb, fast, out); 2 | input wire clk; 3 | // @annot{taint_source(opa)} 4 | // @annot{taint_source(opb)} 5 | input wire [31:0] opa, opb; 6 | input wire fast; 7 | 8 | // @annot{taint_sink(out)} 9 | output reg [31:0] out; 10 | 11 | // @annot{qualifierImp(x,[opa,opb])} 12 | 13 | reg x, y; 14 | 15 | assign w1a = opa[31]; 16 | assign w1b = opb[31]; 17 | 18 | assign w2a = opa[30]; 19 | assign w2b = opb[30]; 20 | 21 | always @(*) begin 22 | if(fast) 23 | x = w1a; 24 | else 25 | x = w1b; 26 | end 27 | 28 | always @(posedge clk) begin 29 | if(w2a | w2b) 30 | y <= 0; 31 | else 32 | y <= x; 33 | end 34 | 35 | always @(posedge clk) 36 | out <= y; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /examples/fp/Test.hs: -------------------------------------------------------------------------------- 1 | module Test where 2 | 3 | {-@ inv0 :: cl:Int -> xl:Int -> yl:Int -> 4 | cr:Int -> xr:Int -> yr:Int -> 5 | {v:Bool | v <=> (cl == cr && yl == yr)} @-} 6 | inv0 :: Int -> Int -> Int -> Int -> Int -> Int -> Bool 7 | inv0 cl 0 0 cr 0 0 = cl == cr -- initial state 8 | inv0 cl xl yl cr xr yr = 9 | (inv0 cl 1 0 cr 1 0) || -- tag reset 10 | (let cl' = cl 11 | cr' = cr 12 | xl' = xl 13 | xr' = xr 14 | yl' = if cl >= 1 then xl else yl 15 | yr' = if cr >= 1 then xr else yr 16 | in inv0 cl' xl' yl' cr' xr' yr') -- transition relation 17 | 18 | inv0_prop :: Int -> Int -> Int -> Int -> Int -> Int -> Bool 19 | inv0_prop cl xl yl cr xr yr = 20 | if inv0 cl xl yl cr xr yr && yl > 0 && yr <= 0 21 | then error "inv0_prop fail" 22 | else True 23 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/benchmarks/mpn_plot_perf.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | print("Running performance analysis...") 4 | print("Out dir : %s" % out_dir) 5 | print("Architecture: %s" % arch) 6 | 7 | import os 8 | import sys 9 | import csv 10 | 11 | csv_records = [] 12 | csv_path = os.path.join(out_dir,"mpn-performance-%s.csv" % arch) 13 | 14 | for record in performance: 15 | func, lx,ly,instr_s,instr_e,cycle_s,cycle_e = record 16 | 17 | cycles = cycle_e - cycle_s 18 | instrs = instr_e - instr_s 19 | 20 | csv_records.append ( 21 | [arch, func, lx, ly, cycles, instrs] 22 | ) 23 | 24 | with open(csv_path, 'w') as fh: 25 | 26 | writer = csv.writer(fh, delimiter = ',',quotechar="\"") 27 | 28 | for row in csv_records: 29 | writer.writerow(row) 30 | 31 | print("Written results to %s" % csv_path) 32 | 33 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_mix_l.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_mix_l) 15 | 16 | wire [31:0] rotated = ({`CRS1,`CRS1} >> dec_arg_rtamt); 17 | 18 | wire [31:0] lmix_result = 19 | (( `CRS2) & rotated ) | 20 | ((~`CRS2) & vtx_crd_val_pre) ; 21 | 22 | // 23 | // mix_l 24 | // 25 | `VTX_CHECK_INSTR_BEGIN(mix_l) 26 | 27 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 28 | `VTX_ASSERT_CRD_VALUE_IS(lmix_result) 29 | 30 | // Never causes writeback to GPRS 31 | `VTX_ASSERT_WEN_IS_CLEAR 32 | 33 | `VTX_CHECK_INSTR_END(mix_l) 34 | 35 | `VTX_CHECKER_MODULE_END 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/docs/diagrams/formal-flow.dot: -------------------------------------------------------------------------------- 1 | 2 | digraph G { 3 | 4 | gen [shape=record;label="Generated RTL"]; 5 | rtl [shape=record;label="Co-processor\nRTL Source"]; 6 | tb [shape=record;label="Formal Testbench"]; 7 | props [shape=record;label="Property\nContexts 0..N"]; 8 | 9 | gen -> yosys 10 | rtl -> yosys 11 | tb -> yosys 12 | props -> yosys 13 | 14 | yosys [label="Yosys"]; 15 | 16 | yosys -> smt2 17 | 18 | smt2 [shape=record;label="SMT2 Representation"]; 19 | 20 | smt2 -> solver 21 | 22 | solver [label="Boolector"]; 23 | 24 | solver -> trace [label="Fail"]; 25 | solver -> pass [label="Pass"]; 26 | 27 | trace [shape=record;label="Counter-example\nVCD Trace"]; 28 | pass [shape=diamond;label="Proven to depth N"]; 29 | 30 | } 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_mix_h.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_mix_h) 15 | 16 | wire [31:0] rotated = ({`CRS1,`CRS1} >> (16+dec_arg_rtamt)); 17 | 18 | wire [31:0] hmix_result = 19 | (( `CRS2) & rotated ) | 20 | ((~`CRS2) & vtx_crd_val_pre) ; 21 | 22 | // 23 | // mix_h 24 | // 25 | `VTX_CHECK_INSTR_BEGIN(mix_h) 26 | 27 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 28 | `VTX_ASSERT_CRD_VALUE_IS(hmix_result) 29 | 30 | // Never causes writeback to GPRS 31 | `VTX_ASSERT_WEN_IS_CLEAR 32 | 33 | `VTX_CHECK_INSTR_END(mix_h) 34 | 35 | `VTX_CHECKER_MODULE_END 36 | -------------------------------------------------------------------------------- /test/verilog/pos/merge-02.v: -------------------------------------------------------------------------------- 1 | module test(clk, opa, opb, out); 2 | input wire clk; 3 | // @annot{taint_source(opa)} 4 | // @annot{taint_source(opb)} 5 | input wire [31:0] opa, opb; 6 | 7 | // @annot{taint_sink(out)} 8 | output reg [31:0] out; 9 | 10 | reg opa_r, opb_r; 11 | reg sticky; 12 | reg y; 13 | 14 | always @(posedge clk) 15 | opa_r <= opa; 16 | 17 | always @(posedge clk) 18 | opb_r <= opb; 19 | 20 | assign signa = opa_r[31]; 21 | assign signb = opb_r[31]; 22 | 23 | always @(*) begin 24 | sticky = opa_r + opb_r; 25 | end 26 | 27 | always @(*) begin 28 | case({signa, signb}) 29 | 2'b00: y = 0; 30 | 2'b01: y = sticky; 31 | default: y = ! sticky; 32 | endcase 33 | end 34 | 35 | always @(posedge clk) 36 | out <= y; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_ext.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_ext) 15 | 16 | wire [ 4:0] ext_begin = {dec_arg_cs,1'b0}; 17 | wire [ 4:0] ext_len = {dec_arg_cl,1'b0}; 18 | wire [31:0] ext_mask = 32'hFFFF_FFFF >> (32-ext_len); 19 | wire [31:0] ext_result= (`CRS1 >> ext_begin) & ext_mask; 20 | 21 | // 22 | // ext 23 | // 24 | `VTX_CHECK_INSTR_BEGIN(ext) 25 | 26 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 27 | `VTX_ASSERT_CRD_VALUE_IS(ext_result) 28 | 29 | // Never causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_CLEAR 31 | 32 | `VTX_CHECK_INSTR_END(ext) 33 | 34 | `VTX_CHECKER_MODULE_END 35 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_mmul_3.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_mmul_3) 15 | 16 | reg [63:0] value; 17 | 18 | // Assume only this instruction is ever run. 19 | always @(posedge `VTX_CLK_NAME) if(vtx_valid) assume(dec_mmul_3); 20 | 21 | // 22 | // mmul_3 23 | // 24 | `VTX_CHECK_INSTR_BEGIN(mmul_3) 25 | 26 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 27 | 28 | value = (`CRS1 * `CRS2) + `CRS3; 29 | 30 | `VTX_ASSERT(vtx_crd1_val_post == value[31:0]); 31 | 32 | // Never causes writeback to GPRS 33 | `VTX_ASSERT_WEN_IS_CLEAR 34 | 35 | `VTX_CHECK_INSTR_END(mmul_3) 36 | 37 | `VTX_CHECKER_MODULE_END 38 | 39 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_rngsamp.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_rngsamp) 14 | 15 | // 16 | // rngsamp 17 | // 18 | // Checks that the most recent sample of the COP RNG is written to the 19 | // correct register. 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(rngsamp) 22 | 23 | // Value of destination register post instruction should be the same 24 | // as the most recent 32-bit random sample. 25 | `VTX_ASSERT_CRD_VALUE_IS(vtx_rand_sample); 26 | 27 | // Always succeeds 28 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 29 | 30 | // Never writes to GPRS 31 | `VTX_ASSERT_WEN_IS_CLEAR 32 | 33 | `VTX_CHECK_INSTR_END(rngsamp) 34 | 35 | `VTX_CHECKER_MODULE_END 36 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_mequ.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_mequ) 15 | 16 | reg value; 17 | 18 | 19 | // 20 | // mequ 21 | // 22 | `VTX_CHECK_INSTR_BEGIN(mequ) 23 | 24 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 25 | 26 | value = (`CRS2 == `CRS3) && vtx_instr_rs1; 27 | 28 | // Always causes writeback to GPRS 29 | `VTX_ASSERT_WEN_IS_SET 30 | 31 | // Writeback to the correct GPR 32 | `VTX_ASSERT_WADDR_IS(dec_arg_rd); 33 | 34 | // WDATA is the single bit compare result zero padded to 32-bits. 35 | `VTX_ASSERT_WDATA_IS({31'b0,value}); 36 | 37 | `VTX_CHECK_INSTR_END(mequ) 38 | 39 | `VTX_CHECKER_MODULE_END 40 | 41 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/icarus/integration.cmd: -------------------------------------------------------------------------------- 1 | +incdir+$(XC_HOME)/rtl/coprocessor 2 | $(XC_HOME)/rtl/coprocessor/scarv_cop_aes_sbox.v 3 | $(XC_HOME)/rtl/coprocessor/scarv_cop_aes.v 4 | $(XC_HOME)/rtl/coprocessor/scarv_cop_cprs.v 5 | $(XC_HOME)/rtl/coprocessor/scarv_cop_idecode.v 6 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu.v 7 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu_adder.v 8 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu_shifter.v 9 | $(XC_HOME)/rtl/coprocessor/scarv_cop_palu_multiplier.v 10 | $(XC_HOME)/rtl/coprocessor/scarv_cop_malu.v 11 | $(XC_HOME)/rtl/coprocessor/scarv_cop_rng.v 12 | $(XC_HOME)/rtl/coprocessor/scarv_cop_mem.v 13 | $(XC_HOME)/rtl/coprocessor/scarv_cop_top.v 14 | $(XC_HOME)/rtl/integration/scarv_integ_prv_pcpi2cop.v 15 | $(XC_HOME)/rtl/integration/scarv_prv_xcrypt_top.v 16 | $(XC_HOME)/external/picorv32/picorv32.v 17 | $(XC_HOME)/verif/tb/axi_sram.v 18 | $(XC_HOME)/verif/tb/tb_integration.v 19 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_rngtest.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_rngtest) 14 | 15 | // 16 | // rngtest 17 | // 18 | // Checks that the RNG reports its entropy health correctly. 19 | // 20 | `VTX_CHECK_INSTR_BEGIN(rngtest) 21 | 22 | // Always succeeds 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | // Returns either 32'b1 or 32'b0 26 | `VTX_ASSERT(vtx_instr_wdata == 32'b0 || 27 | vtx_instr_wdata == 32'b1); 28 | 29 | // Returns either 32'b1 or 32'b0 30 | `VTX_ASSERT_WADDR_IS(dec_arg_rd) 31 | 32 | // Never writes to GPRS 33 | `VTX_ASSERT_WEN_IS_SET 34 | 35 | `VTX_CHECK_INSTR_END(rngtest) 36 | 37 | `VTX_CHECKER_MODULE_END 38 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-2.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | reg x; 4 | reg y; 5 | 6 | // @annot{taint_source(x)} 7 | // @annot{taint_sink(y)} 8 | 9 | // @annot{sanitize_glob(x)} 10 | // @annot{sanitize(Stall)} 11 | 12 | reg Stall; 13 | 14 | always @(posedge clk) begin 15 | if (Stall) 16 | y <= y; 17 | else 18 | y <= x + 1; 19 | end 20 | 21 | wire Stall_wire; 22 | 23 | // @annot{sanitize_mod(reg_file, val)} 24 | reg_file REG_FILE(clk, 0, Stall_wire); 25 | 26 | always @(*) begin 27 | Stall = Stall_wire; 28 | end 29 | 30 | endmodule 31 | 32 | module reg_file(clk, regNo, val); 33 | input wire clk; 34 | input wire regNo; 35 | output reg val; 36 | 37 | // 10 x 32-bit registers 38 | reg [31:0] reg_array [9:0]; 39 | 40 | always @(posedge clk ) begin 41 | val <= reg_array[regNo]; 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_bop.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_bop) 15 | 16 | wire [31:0] bop_result; 17 | 18 | genvar i; 19 | generate for(i=0; i < 32; i = i + 1) begin 20 | 21 | wire [2:0] bop_index = {`CRD[i], `CRS1[i],`CRS2[i]}; 22 | 23 | assign bop_result[i] = dec_arg_lut8[bop_index]; 24 | 25 | end endgenerate 26 | 27 | // 28 | // bop 29 | // 30 | `VTX_CHECK_INSTR_BEGIN(bop) 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | `VTX_ASSERT_CRD_VALUE_IS(bop_result) 34 | 35 | // Never causes writeback to GPRS 36 | `VTX_ASSERT_WEN_IS_CLEAR 37 | 38 | `VTX_CHECK_INSTR_END(bop) 39 | 40 | `VTX_CHECKER_MODULE_END 41 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_rngseed.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_rngseed) 14 | 15 | // 16 | // rngseed 17 | // 18 | // rngseed is a difficult one to verify without knowing or modeling 19 | // the randomness algorithm underneath it. 20 | // 21 | // We settle here for making sure the simple side effects of the instruction 22 | // are kept too. 23 | // 24 | `VTX_CHECK_INSTR_BEGIN(rngseed) 25 | 26 | // No change to CRD register vlaue. 27 | `VTX_ASSERT_CRD_VALUE_IS(`CRD) 28 | 29 | // Always succeeds 30 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 31 | 32 | // Never writes to GPRS 33 | `VTX_ASSERT_WEN_IS_CLEAR 34 | 35 | `VTX_CHECK_INSTR_END(rngseed) 36 | 37 | `VTX_CHECKER_MODULE_END 38 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_no_reg_write_if_invalid_op.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | // 14 | // Check that XCR values never change on an invalid opcode. 15 | // 16 | `VTX_CHECKER_MODULE_BEGIN(no_reg_write_if_invalid_op) 17 | 18 | genvar i; 19 | generate for(i = 0; i < 16; i = i + 1) begin 20 | 21 | // 22 | // For each CPR register: 23 | // If the decoded instruction is invalid, assert no XCR register 24 | // changed. 25 | // 26 | `VTX_CHECK_BEGIN(no_reg_write_if_op_invalid) 27 | 28 | if(dec_invalid_opcode) begin 29 | 30 | `VTX_ASSERT(vtx_cprs_pre[i] == vtx_cprs_post[i]); 31 | 32 | end 33 | 34 | `VTX_CHECK_END(no_reg_write_if_op_invalid) 35 | 36 | end endgenerate 37 | 38 | `VTX_CHECKER_MODULE_END 39 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_msll.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_msll) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // msll 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(msll) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = {`CRS2 , `CRS1} << `CRS3; 26 | 27 | if(`CRS3 >= 64) begin 28 | 29 | // Give zero if shift amount greater than doubleword width. 30 | `VTX_ASSERT_CRDM_VALUE_IS(64'b0) 31 | 32 | end else begin 33 | 34 | `VTX_ASSERT_CRDM_VALUE_IS(value) 35 | 36 | end 37 | 38 | // Never causes writeback to GPRS 39 | `VTX_ASSERT_WEN_IS_CLEAR 40 | 41 | `VTX_CHECK_INSTR_END(msll) 42 | 43 | `VTX_CHECKER_MODULE_END 44 | 45 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_msrl.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_msrl) 15 | 16 | reg [63:0] value; 17 | 18 | // 19 | // msrl 20 | // 21 | `VTX_CHECK_INSTR_BEGIN(msrl) 22 | 23 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 24 | 25 | value = {`CRS2 , `CRS1} >> `CRS3; 26 | 27 | if(`CRS3 >= 64) begin 28 | 29 | // Give zero if shift amount greater than doubleword width. 30 | `VTX_ASSERT_CRDM_VALUE_IS(64'b0) 31 | 32 | end else begin 33 | 34 | `VTX_ASSERT_CRDM_VALUE_IS(value) 35 | 36 | end 37 | 38 | // Never causes writeback to GPRS 39 | `VTX_ASSERT_WEN_IS_CLEAR 40 | 41 | `VTX_CHECK_INSTR_END(msrl) 42 | 43 | `VTX_CHECKER_MODULE_END 44 | 45 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/flow/benchmarks/Makefile: -------------------------------------------------------------------------------- 1 | 2 | BWORK = $(XC_HOME)/work/benchmarks 3 | SREC_DIR = $(XC_HOME)/work/examples 4 | BLIB = $(XC_HOME)/flow/benchmarks/XCBenchmark.py 5 | 6 | BENCHMARKS = mpn aes-test prince sha2 keccakp-1600 keccakp-400 7 | 8 | BMARK_SRECS = $(addsuffix .srec,$(addprefix $(SREC_DIR)/,$(BENCHMARKS))) 9 | BMARK_STDOUT= $(addsuffix .py,$(addprefix $(BWORK)/,$(BENCHMARKS))) 10 | BMARK_RESULT= $(addsuffix .txt,$(addprefix $(BWORK)/results-,$(BENCHMARKS))) 11 | 12 | $(BWORK)/%.py : $(SREC_DIR)/%.srec 13 | $(VERILATOR_SIM) +TIMEOUT=4000000 \ 14 | +PASS_ADDR=0xC000001C +FAIL_ADDR=0xC0000010 \ 15 | +IMEM=$< \ 16 | +STDOUT=$@ 17 | 18 | $(BWORK)/results-%.txt : $(BWORK)/%.py $(BLIB) 19 | env PATH=$(PATH):$(XC_HOME)/flow/benchmarks \ 20 | python3 $< > $@ 21 | 22 | all: $(BWORK) $(BMARK_STDOUT) $(BMARK_RESULT) 23 | 24 | $(BWORK): 25 | mkdir -p $(BWORK) 26 | 27 | clean: 28 | rm -rf $(BWORK) 29 | -------------------------------------------------------------------------------- /test/verilog/neg/neg-test-3.v: -------------------------------------------------------------------------------- 1 | module test(clk); 2 | input clk; 3 | 4 | // @annot{taint_source(ex_inst)} 5 | // @annot{taint_sink(wb_wbv)} 6 | 7 | reg ex_inst; 8 | reg ex_ld_res; 9 | reg ex_res; 10 | reg wb_wbv, ex_wbv; 11 | reg not_eq, cond, not_eq0, not_eq1; 12 | 13 | always @(posedge clk) begin 14 | not_eq0 <= ex_inst + 1; 15 | not_eq1 <= ex_inst + 2; 16 | 17 | if (cond) 18 | not_eq <= not_eq0; 19 | else 20 | not_eq <= not_eq1; 21 | end 22 | 23 | reg foo1,foo2; 24 | 25 | always @(posedge clk) 26 | if (cond) 27 | ex_res <= ex_inst + 1; 28 | else 29 | ex_res <= ex_inst + 2; 30 | 31 | always @(posedge clk) 32 | ex_ld_res <= not_eq; 33 | 34 | always @(posedge clk) 35 | ex_wbv <= ex_inst[0] == 0 ? ex_ld_res : ex_res; 36 | 37 | always @(posedge clk) begin 38 | wb_wbv <= ex_wbv; 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /benchmarks/README.md: -------------------------------------------------------------------------------- 1 | # Benchmarks 2 | 3 | ## Constant Time 4 | 5 | ### MIPS Pipeline 6 | 7 | - [Source code](472-mips-pipelined) 8 | 9 | ### RISC-V Pipeline 10 | 11 | - [Source code](yarvi/shared) 12 | - [Reference](https://github.com/tommythorn/yarvi) 13 | 14 | ### SHA-256 15 | 16 | - [Source code](crypto_cores/sha_core/trunk/rtl/sha256.v) 17 | - [Reference](https://opencores.org/project/sha_core) 18 | 19 | ### FPU 20 | 21 | - [Source code](fpu/verilog) 22 | - [Reference](https://github.com/monajalal/fpga_mc/tree/master/fpu) 23 | 24 | ### ALU 25 | 26 | - [Source code](xcrypto-ref/rtl/coprocessor/scarv_cop_palu.v) 27 | - [Reference](https://github.com/scarv/xcrypto-ref) 28 | 29 | ## Non Constant Time 30 | 31 | ### FPU 32 | 33 | - [Source code](fpu2/divider/divider.v) 34 | - [Reference](https://github.com/dawsonjon/fpu) 35 | 36 | ### RSA 37 | 38 | - [Source code](crypto_cores/RSA4096/ModExp2/ModExp.v) 39 | - [Reference](https://github.com/fatestudio/RSA4096) 40 | -------------------------------------------------------------------------------- /test/abduction/pos/abduction-06.v: -------------------------------------------------------------------------------- 1 | module test(clk, in1, in2, in3, out); 2 | // @annot{taint_source(in1)} 3 | // @annot{taint_source(in2)} 4 | // @annot{taint_source(in3)} 5 | 6 | // @annot{taint_sink(out)} 7 | 8 | // @annot{sanitize(tmp1)} 9 | // @annot{sanitize(cond)} 10 | // @annot{sanitize(tmp2)} 11 | 12 | // @annot{sanitize_glob(in2)} 13 | // @annot{sanitize_glob(in3)} 14 | 15 | input clk, in1, in2, in3; 16 | output out; 17 | 18 | reg out; 19 | reg in1_1, in1_2, tmp1, tmp2, cond; 20 | 21 | always @(posedge clk) begin 22 | in1_1 <= in1; 23 | in1_2 <= in1_1; 24 | tmp1 <= in2 + 1; 25 | cond <= in3 & 1'hF; 26 | end 27 | 28 | always @(posedge clk) 29 | if (cond) 30 | tmp2 <= 0; 31 | else 32 | tmp2 <= tmp1; 33 | 34 | always @(posedge clk) 35 | if (tmp2) 36 | out <= 0; 37 | else 38 | out <= in1_2; 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_correct_result_encodings.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(correct_result_encodings) 14 | 15 | // 16 | // Check we only ever get the right result encodings from instructions. 17 | // 18 | `VTX_CHECK_BEGIN(correct_result_encodings) 19 | `VTX_ASSERT( 20 | vtx_instr_result == SCARV_COP_INSN_SUCCESS || 21 | vtx_instr_result == SCARV_COP_INSN_ABORT || 22 | vtx_instr_result == SCARV_COP_INSN_BAD_INS || 23 | vtx_instr_result == SCARV_COP_INSN_BAD_LAD || 24 | vtx_instr_result == SCARV_COP_INSN_BAD_SAD || 25 | vtx_instr_result == SCARV_COP_INSN_LD_ERR || 26 | vtx_instr_result == SCARV_COP_INSN_ST_ERR 27 | ); 28 | `VTX_CHECK_END(correct_result_encodings) 29 | 30 | `VTX_CHECKER_MODULE_END 31 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_mgte.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_mgte) 15 | 16 | reg value; 17 | 18 | 19 | // 20 | // mgte 21 | // 22 | `VTX_CHECK_INSTR_BEGIN(mgte) 23 | 24 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 25 | 26 | value = ((`CRS2 == `CRS3) && vtx_instr_rs1) || 27 | (`CRS2 > `CRS3) ; 28 | 29 | // Always causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_SET 31 | 32 | // Writeback to the correct GPR 33 | `VTX_ASSERT_WADDR_IS(dec_arg_rd); 34 | 35 | // WDATA is the single bit compare result zero padded to 32-bits. 36 | `VTX_ASSERT_WDATA_IS({31'b0,value}); 37 | 38 | `VTX_CHECK_INSTR_END(mgte) 39 | 40 | `VTX_CHECKER_MODULE_END 41 | 42 | 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_mlte.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_mlte) 15 | 16 | reg value; 17 | 18 | 19 | // 20 | // mlte 21 | // 22 | `VTX_CHECK_INSTR_BEGIN(mlte) 23 | 24 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 25 | 26 | value = ((`CRS2 == `CRS3) && vtx_instr_rs1) || 27 | (`CRS2 < `CRS3) ; 28 | 29 | // Always causes writeback to GPRS 30 | `VTX_ASSERT_WEN_IS_SET 31 | 32 | // Writeback to the correct GPR 33 | `VTX_ASSERT_WADDR_IS(dec_arg_rd); 34 | 35 | // WDATA is the single bit compare result zero padded to 32-bits. 36 | `VTX_ASSERT_WDATA_IS({31'b0,value}); 37 | 38 | `VTX_CHECK_INSTR_END(mlte) 39 | 40 | `VTX_CHECKER_MODULE_END 41 | 42 | 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_w.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_w) 15 | 16 | wire [7:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[31:24]; 19 | assign split[2] = `CRS1[23:16]; 20 | assign split[1] = `CRS1[15: 8]; 21 | assign split[0] = `CRS1[ 7: 0]; 22 | 23 | wire [31:0] pperm_w_result = { 24 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0] 25 | }; 26 | 27 | // 28 | // pperm_w 29 | // 30 | `VTX_CHECK_INSTR_BEGIN(pperm_w) 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | `VTX_ASSERT_CRD_VALUE_IS(pperm_w_result) 34 | 35 | // Never causes writeback to GPRS 36 | `VTX_ASSERT_WEN_IS_CLEAR 37 | 38 | `VTX_CHECK_INSTR_END(pperm_w) 39 | 40 | `VTX_CHECKER_MODULE_END 41 | -------------------------------------------------------------------------------- /benchmarks/fpu/verilog/check_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/zsh 2 | 3 | function blue() { print -P "%F{blue}%B$1%b%f" } 4 | function green() { print -P "%F{green}%B$1%b%f" } 5 | function red() { print -P "%F{red}%B$1%b%f" } 6 | 7 | MODULES=( pre_norm pre_norm_fmul add_sub27 mul_r2 div_r2 post_norm ) 8 | 9 | for m in ${MODULES[@]}; do 10 | f="${m}.v" 11 | if [[ ! -f "$f" ]]; then 12 | red "$f does not exists, aborting ..." 13 | exit 1 14 | fi 15 | 16 | blue "################################################################################" 17 | blue "testing $f" 18 | blue "################################################################################" 19 | 20 | verylog -M $m $f $@ 21 | 22 | if [[ $? -ne 0 ]]; then 23 | red "running $f failed !" 24 | exit 1 25 | fi 26 | done 27 | 28 | green "################################################################################" 29 | green "ALL TESTS PASSED !!!" 30 | green "################################################################################" 31 | 32 | -------------------------------------------------------------------------------- /src/Iodine/Abduction/Utils.hs: -------------------------------------------------------------------------------- 1 | module Iodine.Abduction.Utils where 2 | 3 | import Iodine.Utils 4 | 5 | import Control.Monad.State.Lazy 6 | import qualified Data.Sequence as SQ 7 | import System.Random 8 | 9 | import Debug.Trace 10 | 11 | -- | Generate a random value in the monadic context. 12 | randM :: (Random a, MonadIO m) => m a 13 | randM = liftIO randomIO 14 | 15 | -- | Run one of the actions randomly and return the result. 16 | chooseM :: MonadIO m => m a -> m a -> m a 17 | chooseM = ifM randM 18 | 19 | -- | Pick a random element from the given sequence. 20 | -- The sequence must be non empty, otherwise this throws an error. 21 | randomSample :: MonadIO m => SQ.Seq a -> m a 22 | randomSample sq = 23 | if SQ.length sq == 0 24 | then error "randomSample is called with an empty sequence !" 25 | else (SQ.index sq) . (`mod` (SQ.length sq)) <$> randM 26 | 27 | debug :: String -> a -> a 28 | debug = trace 29 | 30 | debugM :: MonadIO m => String -> m () 31 | debugM = traceM 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/08-load.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.ld.w c1, 0(a1) 11 | xc.ld.w c2, 4(a1) 12 | xc.ld.w c3,16(a1) 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.ld.w c1, 0(a1) 19 | xc.ld.w c2, 4(a1) 20 | xc.ld.w c3,16(a1) 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.ld.w c1, 0(a1) 27 | xc.ld.w c2, 4(a1) 28 | xc.ld.w c3,16(a1) 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | 34 | xc.ld.w c1, 0(a1) 35 | xc.ld.w c2, 4(a1) 36 | xc.ld.w c3,16(a1) 37 | 38 | xc.xcr2gpr a1, c1 39 | xc.xcr2gpr a2, c2 40 | xc.xcr2gpr a3, c3 41 | 42 | xc.ld.w c1, 0(a1) 43 | xc.ld.w c2, 4(a1) 44 | xc.ld.w c3,16(a1) 45 | 46 | xc.xcr2gpr a1, c1 47 | xc.xcr2gpr a2, c2 48 | xc.xcr2gpr a3, c3 49 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/test.fq: -------------------------------------------------------------------------------- 1 | qualif Eq1(v : int, x as (VL_ . $1) : int, y as (VR_ . $1) : int): ((x = y)) // (line 0, column 0) 2 | qualif Eq2(v : int, x as (VLP_ . $1) : int, y as (VRP_ . $1) : int): ((x = y)) // (line 0, column 0) 3 | 4 | 5 | bind 1 VL_y : {v : int | []} 6 | bind 2 VR_y : {v : int | []} 7 | bind 3 VLP_y : {v : int | []} 8 | bind 4 VRP_y : {v : int | []} 9 | bind 5 VLT_y : {v : int | []} 10 | bind 6 VRT_y : {v : int | []} 11 | bind 7 VLTP_y : {v : int | []} 12 | bind 8 VRTP_y : {v : int | []} 13 | 14 | bind 100 zero : {v : int | [(v = 0)]} 15 | bind 200 one : {v : int | [(v = 1)]} 16 | 17 | constraint: 18 | env [3; 4] 19 | lhs {v##1 : int | []} 20 | rhs {v##1 : int | [$inv0[VRP_y:=VLP_y][VLTP_y:=zero][VRTP_y:=zero][v:=v##1]]} 21 | id 1 tag [] 22 | 23 | constraint: 24 | env [1;2;3;4] 25 | lhs {v##5 : int | [$inv0[VLP_y:=VL_y][VRP_y:=VR_y]]} 26 | rhs {v##5 : int | [(VR_y = VL_y)]} 27 | id 5 tag [] 28 | 29 | wf: 30 | env [1;2;3;4] 31 | reft {v : int | [$inv0]} 32 | 33 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/12-store-w.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.st.w c1, 0(a1) 11 | xc.st.w c2, 4(a1) 12 | xc.st.w c3,16(a1) 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.st.w c1, 0(a1) 19 | xc.st.w c2, 4(a1) 20 | xc.st.w c3,16(a1) 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.st.w c1, 0(a1) 27 | xc.st.w c2, 4(a1) 28 | xc.st.w c3,16(a1) 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | 34 | xc.st.w c1, 0(a1) 35 | xc.st.w c2, 4(a1) 36 | xc.st.w c3,16(a1) 37 | 38 | xc.xcr2gpr a1, c1 39 | xc.xcr2gpr a2, c2 40 | xc.xcr2gpr a3, c3 41 | 42 | xc.st.w c1, 0(a1) 43 | xc.st.w c2, 4(a1) 44 | xc.st.w c3,16(a1) 45 | 46 | xc.xcr2gpr a1, c1 47 | xc.xcr2gpr a2, c2 48 | xc.xcr2gpr a3, c3 49 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_int/test_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench(clk, rst); 2 | input clk; 3 | input rst; 4 | wire [31:0] wire_39069600; 5 | wire wire_39069600_stb; 6 | wire wire_39069600_ack; 7 | wire [31:0] wire_39795168; 8 | wire wire_39795168_stb; 9 | wire wire_39795168_ack; 10 | file_reader_a file_reader_a_39796104( 11 | .clk(clk), 12 | .rst(rst), 13 | .output_z(wire_39069600), 14 | .output_z_stb(wire_39069600_stb), 15 | .output_z_ack(wire_39069600_ack)); 16 | file_writer file_writer_39028208( 17 | .clk(clk), 18 | .rst(rst), 19 | .input_a(wire_39795168), 20 | .input_a_stb(wire_39795168_stb), 21 | .input_a_ack(wire_39795168_ack)); 22 | float_to_int float_to_int_39759952( 23 | .clk(clk), 24 | .rst(rst), 25 | .input_a(wire_39069600), 26 | .input_a_stb(wire_39069600_stb), 27 | .input_a_ack(wire_39069600_ack), 28 | .output_z(wire_39795168), 29 | .output_z_stb(wire_39795168_stb), 30 | .output_z_ack(wire_39795168_ack)); 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/fpu2/int_to_float/test_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench(clk, rst); 2 | input clk; 3 | input rst; 4 | wire [31:0] wire_39069600; 5 | wire wire_39069600_stb; 6 | wire wire_39069600_ack; 7 | wire [31:0] wire_39795168; 8 | wire wire_39795168_stb; 9 | wire wire_39795168_ack; 10 | file_reader_a file_reader_a_39796104( 11 | .clk(clk), 12 | .rst(rst), 13 | .output_z(wire_39069600), 14 | .output_z_stb(wire_39069600_stb), 15 | .output_z_ack(wire_39069600_ack)); 16 | file_writer file_writer_39028208( 17 | .clk(clk), 18 | .rst(rst), 19 | .input_a(wire_39795168), 20 | .input_a_stb(wire_39795168_stb), 21 | .input_a_ack(wire_39795168_ack)); 22 | int_to_float int_to_float_39759952( 23 | .clk(clk), 24 | .rst(rst), 25 | .input_a(wire_39069600), 26 | .input_a_stb(wire_39069600_stb), 27 | .input_a_ack(wire_39069600_ack), 28 | .output_z(wire_39795168), 29 | .output_z_stb(wire_39795168_stb), 30 | .output_z_ack(wire_39795168_ack)); 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_long/test_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench(clk, rst); 2 | input clk; 3 | input rst; 4 | wire [63:0] wire_39069600; 5 | wire wire_39069600_stb; 6 | wire wire_39069600_ack; 7 | wire [63:0] wire_39795168; 8 | wire wire_39795168_stb; 9 | wire wire_39795168_ack; 10 | file_reader_a file_reader_a_39796104( 11 | .clk(clk), 12 | .rst(rst), 13 | .output_z(wire_39069600), 14 | .output_z_stb(wire_39069600_stb), 15 | .output_z_ack(wire_39069600_ack)); 16 | file_writer file_writer_39028208( 17 | .clk(clk), 18 | .rst(rst), 19 | .input_a(wire_39795168), 20 | .input_a_stb(wire_39795168_stb), 21 | .input_a_ack(wire_39795168_ack)); 22 | double_to_long float_to_int_39759952( 23 | .clk(clk), 24 | .rst(rst), 25 | .input_a(wire_39069600), 26 | .input_a_stb(wire_39069600_stb), 27 | .input_a_ack(wire_39069600_ack), 28 | .output_z(wire_39795168), 29 | .output_z_stb(wire_39795168_stb), 30 | .output_z_ack(wire_39795168_ack)); 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/fpu2/long_to_double/test_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench(clk, rst); 2 | input clk; 3 | input rst; 4 | wire [63:0] wire_39069600; 5 | wire wire_39069600_stb; 6 | wire wire_39069600_ack; 7 | wire [63:0] wire_39795168; 8 | wire wire_39795168_stb; 9 | wire wire_39795168_ack; 10 | file_reader_a file_reader_a_39796104( 11 | .clk(clk), 12 | .rst(rst), 13 | .output_z(wire_39069600), 14 | .output_z_stb(wire_39069600_stb), 15 | .output_z_ack(wire_39069600_ack)); 16 | file_writer file_writer_39028208( 17 | .clk(clk), 18 | .rst(rst), 19 | .input_a(wire_39795168), 20 | .input_a_stb(wire_39795168_stb), 21 | .input_a_ack(wire_39795168_ack)); 22 | long_to_double int_to_float_39759952( 23 | .clk(clk), 24 | .rst(rst), 25 | .input_a(wire_39069600), 26 | .input_a_stb(wire_39069600_stb), 27 | .input_a_ack(wire_39069600_ack), 28 | .output_z(wire_39795168), 29 | .output_z_stb(wire_39795168_stb), 30 | .output_z_ack(wire_39795168_ack)); 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_lut.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_lut) 15 | 16 | wire [63:0] lut_flat = {`CRS3, `CRS2}; 17 | wire [3:0] lut[15:0]; 18 | wire [31:0] lut_result; 19 | 20 | genvar i; 21 | generate for(i = 0; i < 16; i = i + 1) begin 22 | 23 | assign lut[i] = lut_flat[(4*i)+3:4*i]; 24 | 25 | if(i < 8) begin 26 | assign lut_result[(4*i)+3:4*i] = lut[`CRS1[(4*i)+3:4*i]]; 27 | end 28 | 29 | end endgenerate 30 | 31 | // 32 | // lut 33 | // 34 | `VTX_CHECK_INSTR_BEGIN(lut) 35 | 36 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 37 | `VTX_ASSERT_CRD_VALUE_IS(lut_result) 38 | 39 | // Never causes writeback to GPRS 40 | `VTX_ASSERT_WEN_IS_CLEAR 41 | 42 | `VTX_CHECK_INSTR_END(lut) 43 | 44 | `VTX_CHECKER_MODULE_END 45 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_b0.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_b0) 15 | 16 | wire [1:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[ 7: 6]; 19 | assign split[2] = `CRS1[ 5: 4]; 20 | assign split[1] = `CRS1[ 3: 2]; 21 | assign split[0] = `CRS1[ 1: 0]; 22 | 23 | wire [31:0] pperm_b0_result = { 24 | `CRS1[31: 8], 25 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0] 26 | }; 27 | 28 | // 29 | // pperm_b0 30 | // 31 | `VTX_CHECK_INSTR_BEGIN(pperm_b0) 32 | 33 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 34 | `VTX_ASSERT_CRD_VALUE_IS(pperm_b0_result) 35 | 36 | // Never causes writeback to GPRS 37 | `VTX_ASSERT_WEN_IS_CLEAR 38 | 39 | `VTX_CHECK_INSTR_END(pperm_b0) 40 | 41 | `VTX_CHECKER_MODULE_END 42 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_b3.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_b3) 15 | 16 | wire [1:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[31:30]; 19 | assign split[2] = `CRS1[29:28]; 20 | assign split[1] = `CRS1[27:26]; 21 | assign split[0] = `CRS1[25:24]; 22 | 23 | wire [31:0] pperm_b3_result = { 24 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0], 25 | `CRS1[23: 0] 26 | }; 27 | 28 | // 29 | // pperm_b3 30 | // 31 | `VTX_CHECK_INSTR_BEGIN(pperm_b3) 32 | 33 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 34 | `VTX_ASSERT_CRD_VALUE_IS(pperm_b3_result) 35 | 36 | // Never causes writeback to GPRS 37 | `VTX_ASSERT_WEN_IS_CLEAR 38 | 39 | `VTX_CHECK_INSTR_END(pperm_b3) 40 | 41 | `VTX_CHECKER_MODULE_END 42 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_h0.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_h0) 15 | 16 | wire [3:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[15:12]; 19 | assign split[2] = `CRS1[11: 8]; 20 | assign split[1] = `CRS1[ 7: 4]; 21 | assign split[0] = `CRS1[ 3: 0]; 22 | 23 | wire [31:0] pperm_h0_result = { 24 | `CRS1[31:16], 25 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0] 26 | }; 27 | 28 | // 29 | // pperm_h0 30 | // 31 | `VTX_CHECK_INSTR_BEGIN(pperm_h0) 32 | 33 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 34 | `VTX_ASSERT_CRD_VALUE_IS(pperm_h0_result) 35 | 36 | // Never causes writeback to GPRS 37 | `VTX_ASSERT_WEN_IS_CLEAR 38 | 39 | `VTX_CHECK_INSTR_END(pperm_h0) 40 | 41 | `VTX_CHECKER_MODULE_END 42 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_h1.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_h1) 15 | 16 | wire [3:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[31:28]; 19 | assign split[2] = `CRS1[27:24]; 20 | assign split[1] = `CRS1[23:20]; 21 | assign split[0] = `CRS1[19:16]; 22 | 23 | wire [31:0] pperm_h1_result = { 24 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0], 25 | `CRS1[15: 0] 26 | }; 27 | 28 | // 29 | // pperm_h1 30 | // 31 | `VTX_CHECK_INSTR_BEGIN(pperm_h1) 32 | 33 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 34 | `VTX_ASSERT_CRD_VALUE_IS(pperm_h1_result) 35 | 36 | // Never causes writeback to GPRS 37 | `VTX_ASSERT_WEN_IS_CLEAR 38 | 39 | `VTX_CHECK_INSTR_END(pperm_h1) 40 | 41 | `VTX_CHECKER_MODULE_END 42 | -------------------------------------------------------------------------------- /benchmarks/crypto_cores/RSA4096/ModExp2/compile.txt: -------------------------------------------------------------------------------- 1 | How I compile ModExp project: 2 | Settings - ModExp 3 | 4 | Compilation Process Settings 5 | 1. Early timeing estimate mode 6 | Realistic (average case) 7 | 8 | 2. Physical Synthesis Optimizations 9 | yes 10 | yes 11 | Extra 12 | yes 13 | yes 14 | yes 15 | yes 16 | 17 | 3. EDA Tool Settings 18 | Design Entry / Synthesis: ViewDraw 19 | Simulation: ModelSim-Altera 20 | Formal Verification: None (Conformal not work for Cyclone 2) 21 | Board-Level: 22 | Timing: STAMP 23 | Symbol: ViewDraw 24 | Signal Integrity: IBIS (HSPICE not work for Cyclone 2) 25 | Boundary Scan: BSDL 26 | 27 | 4. Analysis & Synthesis 28 | Optimization Tecnique: Speed 29 | Timing-Driven Synthesis: yes 30 | Power-Up Don't Care: yes 31 | Perform WYSIWYG primitive resynthesis: yes 32 | PowerPlay: Normal compilation 33 | 34 | 5. Verilog HDL Input: 35 | Verilog - 2001 36 | 37 | 6. Fitter Settings: 38 | yes 39 | yes 40 | Normal compilation 41 | Standard Fit 42 | 43 | 44 | 45 | 46 | 47 | 48 | -------------------------------------------------------------------------------- /benchmarks/fpu2/double_to_float/test_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench(clk, rst); 2 | input clk; 3 | input rst; 4 | wire [63:0] wire_39069600; 5 | wire wire_39069600_stb; 6 | wire wire_39069600_ack; 7 | wire [31:0] wire_39795168; 8 | wire wire_39795168_stb; 9 | wire wire_39795168_ack; 10 | file_reader_a file_reader_a_39796104( 11 | .clk(clk), 12 | .rst(rst), 13 | .output_z(wire_39069600), 14 | .output_z_stb(wire_39069600_stb), 15 | .output_z_ack(wire_39069600_ack)); 16 | file_writer file_writer_39028208( 17 | .clk(clk), 18 | .rst(rst), 19 | .input_a(wire_39795168), 20 | .input_a_stb(wire_39795168_stb), 21 | .input_a_ack(wire_39795168_ack)); 22 | double_to_float float_to_int_39759952( 23 | .clk(clk), 24 | .rst(rst), 25 | .input_a(wire_39069600), 26 | .input_a_stb(wire_39069600_stb), 27 | .input_a_ack(wire_39069600_ack), 28 | .output_z(wire_39795168), 29 | .output_z_stb(wire_39795168_stb), 30 | .output_z_ack(wire_39795168_ack)); 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/fpu2/float_to_double/test_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench(clk, rst); 2 | input clk; 3 | input rst; 4 | wire [31:0] wire_39069600; 5 | wire wire_39069600_stb; 6 | wire wire_39069600_ack; 7 | wire [63:0] wire_39795168; 8 | wire wire_39795168_stb; 9 | wire wire_39795168_ack; 10 | file_reader_a file_reader_a_39796104( 11 | .clk(clk), 12 | .rst(rst), 13 | .output_z(wire_39069600), 14 | .output_z_stb(wire_39069600_stb), 15 | .output_z_ack(wire_39069600_ack)); 16 | file_writer file_writer_39028208( 17 | .clk(clk), 18 | .rst(rst), 19 | .input_a(wire_39795168), 20 | .input_a_stb(wire_39795168_stb), 21 | .input_a_ack(wire_39795168_ack)); 22 | float_to_double int_to_float_39759952( 23 | .clk(clk), 24 | .rst(rst), 25 | .input_a(wire_39069600), 26 | .input_a_stb(wire_39069600_stb), 27 | .input_a_ack(wire_39069600_ack), 28 | .output_z(wire_39795168), 29 | .output_z_stb(wire_39795168_stb), 30 | .output_z_ack(wire_39795168_ack)); 31 | endmodule 32 | -------------------------------------------------------------------------------- /benchmarks/yarvi/BeMicroCV/test_yarvi.v: -------------------------------------------------------------------------------- 1 | // ----------------------------------------------------------------------- 2 | // 3 | // Copyright 2014 Tommy Thorn - All Rights Reserved 4 | // 5 | // This program is free software; you can redistribute it and/or modify 6 | // it under the terms of the GNU General Public License as published by 7 | // the Free Software Foundation, Inc., 53 Temple Place Ste 330, 8 | // Bostom MA 02111-1307, USA; either version 2 of the License, or 9 | // (at your option) any later version; incorporated herein by reference. 10 | // 11 | // ----------------------------------------------------------------------- 12 | 13 | `timescale 1ns/10ps 14 | 15 | module test(); 16 | reg clock, reset = 1; 17 | 18 | always #5 clock = ~clock; 19 | 20 | wire [29:0] address; 21 | wire [31:0] writedata; 22 | wire writeenable; 23 | 24 | bemicrocv bemicrocv(.clk_50(clock)); 25 | 26 | initial begin 27 | #12 28 | reset = 0; 29 | end 30 | initial 31 | clock = 1; 32 | endmodule 33 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_b1.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_b1) 15 | 16 | wire [1:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[15:14]; 19 | assign split[2] = `CRS1[13:12]; 20 | assign split[1] = `CRS1[11:10]; 21 | assign split[0] = `CRS1[ 9: 8]; 22 | 23 | wire [31:0] pperm_b1_result = { 24 | `CRS1[31:16], 25 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0], 26 | `CRS1[ 7: 0] 27 | }; 28 | 29 | // 30 | // pperm_b1 31 | // 32 | `VTX_CHECK_INSTR_BEGIN(pperm_b1) 33 | 34 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 35 | `VTX_ASSERT_CRD_VALUE_IS(pperm_b1_result) 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(pperm_b1) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_pperm_b2.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_pperm_b2) 15 | 16 | wire [1:0] split[3:0]; 17 | 18 | assign split[3] = `CRS1[23:22]; 19 | assign split[2] = `CRS1[21:20]; 20 | assign split[1] = `CRS1[19:18]; 21 | assign split[0] = `CRS1[17:16]; 22 | 23 | wire [31:0] pperm_b2_result = { 24 | `CRS1[31:24], 25 | split[dec_arg_b3], split[dec_arg_b2], split[dec_arg_b1], split[dec_arg_b0], 26 | `CRS1[15: 0] 27 | }; 28 | 29 | // 30 | // pperm_b2 31 | // 32 | `VTX_CHECK_INSTR_BEGIN(pperm_b2) 33 | 34 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 35 | `VTX_ASSERT_CRD_VALUE_IS(pperm_b2_result) 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(pperm_b2) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright 2018 Rami Gokhan Kici 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 4 | 5 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 8 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_ins.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_ins) 15 | 16 | wire [ 4:0] ins_begin = {dec_arg_cs,1'b0}; 17 | wire [ 4:0] ins_len = {dec_arg_cl,1'b0}; 18 | 19 | wire [31:0] ins_mask = (32'hFFFF_FFFF >> (32-ins_len)); 20 | wire [31:0] ins_mask_sh = ins_mask << ins_begin; 21 | wire [31:0] to_insert = (`CRS1 & ins_mask) << ins_begin; 22 | 23 | wire [31:0] ins_result = 24 | (to_insert) | 25 | (vtx_crd_val_pre & ~(ins_mask_sh)); 26 | 27 | 28 | // 29 | // ins 30 | // 31 | `VTX_CHECK_INSTR_BEGIN(ins) 32 | 33 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 34 | `VTX_ASSERT_CRD_VALUE_IS(ins_result) 35 | 36 | // Never causes writeback to GPRS 37 | `VTX_ASSERT_WEN_IS_CLEAR 38 | 39 | `VTX_CHECK_INSTR_END(ins) 40 | 41 | `VTX_CHECKER_MODULE_END 42 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/13-store-h.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.st.h c1,(0), 0(a1) 11 | xc.st.h c2,(0), 4(a1) 12 | xc.st.h c3,(0),16(a1) 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.st.h c1,(1), 0(a1) 19 | xc.st.h c2,(1), 4(a1) 20 | xc.st.h c3,(1),16(a1) 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.st.h c1,(0),10(a1) 27 | xc.st.h c2,(0),14(a1) 28 | xc.st.h c3,(0),16(a1) 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | 34 | xc.st.h c1,(1), 0(a1) 35 | xc.st.h c2,(1), 4(a1) 36 | xc.st.h c3,(1),16(a1) 37 | 38 | xc.xcr2gpr a1, c1 39 | xc.xcr2gpr a2, c2 40 | xc.xcr2gpr a3, c3 41 | 42 | xc.st.h c1,(1), 0(a1) 43 | xc.st.h c2,(1), 4(a1) 44 | xc.st.h c3,(1),16(a1) 45 | 46 | xc.xcr2gpr a1, c1 47 | xc.xcr2gpr a2, c2 48 | xc.xcr2gpr a3, c3 49 | -------------------------------------------------------------------------------- /test/verilog/neg/synth.v: -------------------------------------------------------------------------------- 1 | /* Generated by Yosys 0.7+601 (git sha1 626b5552, clang 6.0.0 -fPIC -Os) */ 2 | 3 | (* src = "neg-test-0.v:2" *) 4 | module example(clk, out); 5 | (* src = "neg-test-0.v:20" *) 6 | wire [3:0] _0_; 7 | (* src = "neg-test-0.v:14" *) 8 | wire [3:0] _1_; 9 | (* src = "neg-test-0.v:18" *) 10 | wire [31:0] _2_; 11 | (* src = "neg-test-0.v:3" *) 12 | input clk; 13 | (* src = "neg-test-0.v:7" *) 14 | wire fast; 15 | (* src = "neg-test-0.v:5" *) 16 | wire [3:0] in1; 17 | (* src = "neg-test-0.v:5" *) 18 | wire [3:0] in2; 19 | (* src = "neg-test-0.v:6" *) 20 | output [3:0] out; 21 | reg [3:0] out; 22 | (* src = "neg-test-0.v:8" *) 23 | reg [3:0] temp; 24 | assign _1_ = in1 + (* src = "neg-test-0.v:15" *) in2; 25 | assign fast = ! (* src = "neg-test-0.v:18" *) _2_; 26 | assign _2_ = in1 | (* src = "neg-test-0.v:18" *) in2; 27 | always @(posedge clk) 28 | out <= _0_; 29 | always @(posedge clk) 30 | temp <= _1_; 31 | assign _0_ = fast ? (* src = "neg-test-0.v:21" *) 4'h0 : temp; 32 | endmodule 33 | -------------------------------------------------------------------------------- /benchmarks/crypto_cores/RSA4096/ModExp2/mem_stubs.v: -------------------------------------------------------------------------------- 1 | `include "_parameter.v" 2 | 3 | module r_mem ( 4 | input [`ADDR_WIDTH32 - 1 : 0] address, 5 | input clock, 6 | input [`DATA_WIDTH32 - 1 : 0] qi, 7 | output [`DATA_WIDTH32 - 1 : 0] q); 8 | 9 | assign q = qi + address; 10 | 11 | endmodule 12 | 13 | 14 | module n_mem ( 15 | input [`ADDR_WIDTH32 - 1 : 0] address, 16 | input clock, 17 | input [`DATA_WIDTH32 - 1 : 0] data, 18 | input [`DATA_WIDTH32 - 1 : 0] qi, 19 | output [`DATA_WIDTH32 - 1 : 0] q); 20 | 21 | assign q = data + qi + address; 22 | 23 | endmodule 24 | 25 | module t_mem ( 26 | input [`ADDR_WIDTH32 - 1 : 0] address, 27 | input clock, 28 | input [`DATA_WIDTH32 - 1 : 0] qi, 29 | output [`DATA_WIDTH32 - 1 : 0] q); 30 | 31 | assign q = qi + address; 32 | 33 | endmodule 34 | 35 | module nprime0_mem ( 36 | input [1 : 0] address, 37 | input clock, 38 | input [`DATA_WIDTH32 - 1 : 0] data, 39 | input [`DATA_WIDTH32 - 1 : 0] qi, 40 | output [`DATA_WIDTH32 - 1 : 0] q); 41 | 42 | assign q = data + qi + address; 43 | 44 | endmodule -------------------------------------------------------------------------------- /iverilog-parser/elab_sig_analog.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2008 Stephen Williams (steve@icarus.com) 3 | * 4 | * This source code is free software; you can redistribute it 5 | * and/or modify it in source code form under the terms of the GNU 6 | * General Public License as published by the Free Software 7 | * Foundation; either version 2 of the License, or (at your option) 8 | * any later version. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 18 | */ 19 | 20 | # include "config.h" 21 | 22 | # include "AStatement.h" 23 | 24 | # include 25 | # include 26 | 27 | -------------------------------------------------------------------------------- /test/test.v: -------------------------------------------------------------------------------- 1 | module test(a, b, o); 2 | // @annot{taint_source(a)} 3 | // @annot{taint_source(b)} 4 | // @annot{taint_sink(o)} 5 | 6 | input wire [ 4:0] a; 7 | input wire [26:0] b; 8 | output reg o; 9 | 10 | always @(*) 11 | case(a) 12 | 00: o = 0; 13 | 01: o = b[0]; 14 | default: o = |b[01:0]; 15 | // 02: o = |b[01:0]; 16 | // 03: o = |b[02:0]; 17 | // 04: o = |b[03:0]; 18 | // 05: o = |b[04:0]; 19 | // 06: o = |b[05:0]; 20 | // 07: o = |b[06:0]; 21 | // 08: o = |b[07:0]; 22 | // 09: o = |b[08:0]; 23 | // 10: o = |b[09:0]; 24 | // 11: o = |b[10:0]; 25 | // 12: o = |b[11:0]; 26 | // 13: o = |b[12:0]; 27 | // 14: o = |b[13:0]; 28 | // 15: o = |b[14:0]; 29 | // 16: o = |b[15:0]; 30 | // 17: o = |b[16:0]; 31 | // 18: o = |b[17:0]; 32 | // 19: o = |b[18:0]; 33 | // 20: o = |b[19:0]; 34 | // 21: o = |b[20:0]; 35 | // 22: o = |b[21:0]; 36 | // 23: o = |b[22:0]; 37 | // 24: o = |b[23:0]; 38 | // 25: o = |b[24:0]; 39 | // 26: o = |b[25:0]; 40 | // 27: o = |b[26:0]; 41 | endcase 42 | 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/10-load-h.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.ld.hu c1,(0), 0(a1) 11 | xc.ld.hu c2,(0), 4(a1) 12 | xc.ld.hu c3,(0),16(a1) 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.ld.hu c1,(1), 0(a1) 19 | xc.ld.hu c2,(1), 4(a1) 20 | xc.ld.hu c3,(1),16(a1) 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.ld.hu c1,(0),10(a1) 27 | xc.ld.hu c2,(0),14(a1) 28 | xc.ld.hu c3,(0),16(a1) 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | 34 | xc.ld.hu c1,(1), 0(a1) 35 | xc.ld.hu c2,(1), 4(a1) 36 | xc.ld.hu c3,(1),16(a1) 37 | 38 | xc.xcr2gpr a1, c1 39 | xc.xcr2gpr a2, c2 40 | xc.xcr2gpr a3, c3 41 | 42 | xc.ld.hu c1,(1), 0(a1) 43 | xc.ld.hu c2,(1), 4(a1) 44 | xc.ld.hu c3,(1),16(a1) 45 | 46 | xc.xcr2gpr a1, c1 47 | xc.xcr2gpr a2, c2 48 | xc.xcr2gpr a3, c3 49 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/14-store-b.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.st.b c1,(0,0), 0(a1) 11 | xc.st.b c2,(0,1), 4(a1) 12 | xc.st.b c3,(1,0),16(a1) 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.st.b c1,(1,1), 0(a1) 19 | xc.st.b c2,(1,0), 4(a1) 20 | xc.st.b c3,(1,1),16(a1) 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.st.b c1,(0,0),10(a1) 27 | xc.st.b c2,(0,1),14(a1) 28 | xc.st.b c3,(0,0),16(a1) 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | 34 | xc.st.b c1,(1,1), 0(a1) 35 | xc.st.b c2,(1,0), 4(a1) 36 | xc.st.b c3,(1,1),16(a1) 37 | 38 | xc.xcr2gpr a1, c1 39 | xc.xcr2gpr a2, c2 40 | xc.xcr2gpr a3, c3 41 | 42 | xc.st.b c1,(1,0), 0(a1) 43 | xc.st.b c2,(1,1), 4(a1) 44 | xc.st.b c3,(1,0),16(a1) 45 | 46 | xc.xcr2gpr a1, c1 47 | xc.xcr2gpr a2, c2 48 | xc.xcr2gpr a3, c3 49 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/11-load-b.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.gpr2xcr c1, a1 7 | xc.gpr2xcr c2, a2 8 | xc.gpr2xcr c3, a3 9 | 10 | xc.ld.bu c1,(0,0), 0(a1) 11 | xc.ld.bu c2,(0,1), 4(a1) 12 | xc.ld.bu c3,(1,0),16(a1) 13 | 14 | xc.xcr2gpr a1, c1 15 | xc.xcr2gpr a2, c2 16 | xc.xcr2gpr a3, c3 17 | 18 | xc.ld.bu c1,(1,1), 0(a1) 19 | xc.ld.bu c2,(1,0), 4(a1) 20 | xc.ld.bu c3,(1,1),16(a1) 21 | 22 | xc.xcr2gpr a1, c1 23 | xc.xcr2gpr a2, c2 24 | xc.xcr2gpr a3, c3 25 | 26 | xc.ld.bu c1,(0,0),10(a1) 27 | xc.ld.bu c2,(0,1),14(a1) 28 | xc.ld.bu c3,(0,0),16(a1) 29 | 30 | xc.xcr2gpr a1, c1 31 | xc.xcr2gpr a2, c2 32 | xc.xcr2gpr a3, c3 33 | 34 | xc.ld.bu c1,(1,1), 0(a1) 35 | xc.ld.bu c2,(1,0), 4(a1) 36 | xc.ld.bu c3,(1,1),16(a1) 37 | 38 | xc.xcr2gpr a1, c1 39 | xc.xcr2gpr a2, c2 40 | xc.xcr2gpr a3, c3 41 | 42 | xc.ld.bu c1,(1,0), 0(a1) 43 | xc.ld.bu c2,(1,1), 4(a1) 44 | xc.ld.bu c3,(1,0),16(a1) 45 | 46 | xc.xcr2gpr a1, c1 47 | xc.xcr2gpr a2, c2 48 | xc.xcr2gpr a3, c3 49 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/20-add2-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0xF4F3 7 | xc.ld.liu c0, 0xF2F1 8 | xc.ld.hiu c1, 0x1111 9 | xc.ld.liu c1, 0x1111 10 | xc.ld.hiu c9, 0xFFFF 11 | xc.ld.liu c9, 0xFFFF 12 | 13 | xc.madd.2 (c2,c3), c0, c1 14 | xc.madd.2 (c4,c5), c1, c0 15 | xc.madd.2 (c6,c7), c9, c1 16 | xc.madd.2 (c8,c9), c0, c9 17 | 18 | xc.xcr2gpr x1, c0 19 | xc.xcr2gpr x1, c1 20 | xc.xcr2gpr x1, c2 21 | xc.xcr2gpr x1, c3 22 | xc.xcr2gpr x1, c4 23 | xc.xcr2gpr x1, c5 24 | xc.xcr2gpr x1, c6 25 | xc.xcr2gpr x1, c7 26 | xc.xcr2gpr x1, c8 27 | xc.xcr2gpr x1, c9 28 | 29 | xc.madd.2 (c2,c3), c4, c1 30 | xc.madd.2 (c4,c5), c3, c2 31 | xc.madd.2 (c6,c7), c2, c3 32 | xc.madd.2 (c8,c9), c1, c4 33 | 34 | xc.xcr2gpr x1, c0 35 | xc.xcr2gpr x1, c1 36 | xc.xcr2gpr x1, c2 37 | xc.xcr2gpr x1, c3 38 | xc.xcr2gpr x1, c4 39 | xc.xcr2gpr x1, c5 40 | xc.xcr2gpr x1, c6 41 | xc.xcr2gpr x1, c7 42 | xc.xcr2gpr x1, c8 43 | xc.xcr2gpr x1, c9 44 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/28-sub2-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0xF4F3 7 | xc.ld.liu c0, 0xF2F1 8 | xc.ld.hiu c1, 0x1111 9 | xc.ld.liu c1, 0x1111 10 | xc.ld.hiu c9, 0xFFFF 11 | xc.ld.liu c9, 0xFFFF 12 | 13 | xc.msub.2 (c2,c3), c0, c1 14 | xc.msub.2 (c4,c5), c1, c0 15 | xc.msub.2 (c6,c7), c9, c1 16 | xc.msub.2 (c8,c9), c0, c9 17 | 18 | xc.xcr2gpr x1, c0 19 | xc.xcr2gpr x1, c1 20 | xc.xcr2gpr x1, c2 21 | xc.xcr2gpr x1, c3 22 | xc.xcr2gpr x1, c4 23 | xc.xcr2gpr x1, c5 24 | xc.xcr2gpr x1, c6 25 | xc.xcr2gpr x1, c7 26 | xc.xcr2gpr x1, c8 27 | xc.xcr2gpr x1, c9 28 | 29 | xc.msub.2 (c2,c3), c4, c1 30 | xc.msub.2 (c4,c5), c3, c2 31 | xc.msub.2 (c6,c7), c2, c3 32 | xc.msub.2 (c8,c9), c1, c4 33 | 34 | xc.xcr2gpr x1, c0 35 | xc.xcr2gpr x1, c1 36 | xc.xcr2gpr x1, c2 37 | xc.xcr2gpr x1, c3 38 | xc.xcr2gpr x1, c4 39 | xc.xcr2gpr x1, c5 40 | xc.xcr2gpr x1, c6 41 | xc.xcr2gpr x1, c7 42 | xc.xcr2gpr x1, c8 43 | xc.xcr2gpr x1, c9 44 | -------------------------------------------------------------------------------- /iverilog-parser/PModport.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015 Stephen Williams (steve@icarus.com) 3 | * 4 | * This source code is free software; you can redistribute it 5 | * and/or modify it in source code form under the terms of the GNU 6 | * General Public License as published by the Free Software 7 | * Foundation; either version 2 of the License, or (at your option) 8 | * any later version. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 18 | */ 19 | 20 | # include "config.h" 21 | 22 | # include "PModport.h" 23 | 24 | PModport::PModport(perm_string n) 25 | : name_(n) 26 | { 27 | } 28 | 29 | PModport::~PModport() 30 | { 31 | } 32 | -------------------------------------------------------------------------------- /iverilog-parser/lexor_keyword.h: -------------------------------------------------------------------------------- 1 | #ifndef IVL_lexor_keyword_H 2 | #define IVL_lexor_keyword_H 3 | /* 4 | * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com) 5 | * 6 | * This source code is free software; you can redistribute it 7 | * and/or modify it in source code form under the terms of the GNU 8 | * General Public License as published by the Free Software 9 | * Foundation; either version 2 of the License, or (at your option) 10 | * any later version. 11 | * 12 | * This program is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program; if not, write to the Free Software 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 | */ 21 | 22 | extern int lexor_keyword_code (const char*str, unsigned len); 23 | 24 | #endif /* IVL_lexor_keyword_H */ 25 | -------------------------------------------------------------------------------- /iverilog-parser/PClass.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012 Stephen Williams (steve@icarus.com) 3 | * 4 | * This source code is free software; you can redistribute it 5 | * and/or modify it in source code form under the terms of the GNU 6 | * General Public License as published by the Free Software 7 | * Foundation; either version 2 of the License, or (at your option) 8 | * any later version. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 18 | */ 19 | 20 | # include "PClass.h" 21 | 22 | PClass::PClass(perm_string name, LexicalScope*parent) 23 | : PScopeExtra(name, parent), type(0) 24 | { 25 | } 26 | 27 | 28 | PClass::~PClass() 29 | { 30 | } 31 | -------------------------------------------------------------------------------- /test/verilog/pos/tr-test-7.v: -------------------------------------------------------------------------------- 1 | // this example currently does not go through 2 | // since our transition relation does not guarantee that 3 | // always blocks 2 & 3 execute in lock step 4 | 5 | module test(clk); 6 | input wire clk; 7 | wire choice; 8 | reg x; 9 | reg y; 10 | reg z; 11 | reg t; 12 | 13 | // @annot{taint_source(x)} 14 | // @annot{taint_sink(t)} 15 | 16 | // @annot{sanitize_glob(x)} 17 | // @annot{sanitize(y,z,t)} 18 | 19 | // @annot{sanitize_mod(reg_file, val)} 20 | reg_file REG_FILE(clk, 0, choice); 21 | 22 | always @(posedge clk) //id 1 23 | if (choice) 24 | t <= y; 25 | else 26 | t <= z; 27 | 28 | always @(posedge clk) //id 2 29 | y <= x * 2; 30 | 31 | always @(posedge clk) //id 3 32 | z <= x * 3; 33 | 34 | endmodule 35 | 36 | module reg_file(clk, regNo, val); 37 | input wire clk; 38 | input wire regNo; 39 | output reg val; 40 | 41 | // 10 x 32-bit registers 42 | reg [31:0] reg_array [9:0]; 43 | 44 | always @(posedge clk ) begin 45 | val <= reg_array[regNo]; 46 | end 47 | endmodule -------------------------------------------------------------------------------- /benchmarks/yarvi/ISSUES: -------------------------------------------------------------------------------- 1 | THIS IS A BIT OUT OF DATE 2 | 3 | Issues/todos: 4 | 5 | #-1 Add support for stalling and convert to an Avalon master, 6 | initially without caches. 7 | 8 | #? Switch to 64-bit 9 | 10 | #0 Interrupt support (mostly done, but untested). 11 | 12 | #? Raise interrupts on RX full and TX empty. 13 | 14 | #2 Add caches 15 | 16 | - First a virtual 8 KiB directly mapped L1D$ and L1I$ (being 17 | directly mapped and no bigger than the page size guarantees no 18 | cache aliases, see. page 446 of H&P, ** 3rd ** edition. 19 | 20 | #4 Virtual Memory: ITLB/DTLB + sw filler support. 21 | 22 | Trap on TLB misses and define a set of CSRs to 23 | - access the missed address in a format to make page traversal efficient 24 | - read and write the TLB 25 | 26 | Initially a simple directly mapped TLB will suffice and avoid 27 | having to deal with (p)LRU. 28 | 29 | #? Trap illegal instruction and CSR accesses (unpriviledged too). 30 | 31 | #5 Traps: instruction {misalignment, address, illegal, priviledged}, 32 | fp disabled, {load,store} {misalignment, fault}. 33 | 34 | -------------------------------------------------------------------------------- /t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import sys 4 | import os 5 | import subprocess 6 | 7 | def run_tests(test_args, stack_args=[], build_args=[]): 8 | PACKAGE_NAME = "iodine" 9 | EXE_NAME = "iodine" 10 | TEST_NAME = "iodine-test" 11 | 12 | exe_comp = "{}:{}".format(PACKAGE_NAME, EXE_NAME) 13 | test_comp = "{}:test:{}".format(PACKAGE_NAME, TEST_NAME) 14 | 15 | def add_quotes(s): 16 | i = s.find(" ") 17 | if i < 0: 18 | return s 19 | else: 20 | return '"{}"'.format(s) 21 | 22 | args = " ".join([add_quotes(a) for a in test_args]) 23 | 24 | cmd = [ "stack" ] + stack_args + \ 25 | [ "build" ] + build_args + \ 26 | [ exe_comp, test_comp, "--test-arguments", args ] 27 | 28 | try: 29 | return subprocess.run(cmd).returncode 30 | except KeyboardInterrupt: 31 | return 1 32 | 33 | if __name__ == "__main__": 34 | if os.getenv("PROFILE"): 35 | rc = run_tests(sys.argv[1:], stack_args=["--profile", "--work-dir", ".stack-work-profile"]) 36 | else: 37 | rc = run_tests(sys.argv[1:]) 38 | sys.exit(rc) 39 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_aessub_dec.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_aessub_dec) 14 | 15 | // AES Inverse sbox function. 16 | `include "fml_aes_aux.vh" 17 | 18 | wire [7:0] t0 = sbox_inv(`CRS1[ 7: 0]); 19 | wire [7:0] t1 = sbox_inv(`CRS2[15: 8]); 20 | wire [7:0] t2 = sbox_inv(`CRS1[23:16]); 21 | wire [7:0] t3 = sbox_inv(`CRS2[31:24]); 22 | 23 | wire [31:0] aes_subdec_expected = {t3,t2,t1,t0}; 24 | 25 | // 26 | // aes_sub_dec 27 | // 28 | `VTX_CHECK_INSTR_BEGIN(aessub_dec) 29 | 30 | // Value of destination register post instruction should be the same 31 | // as the most recent 32-bit random sample. 32 | `VTX_ASSERT_CRD_VALUE_IS(aes_subdec_expected); 33 | 34 | // Always succeeds 35 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 36 | 37 | // Never writes to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(aes_sub_dec) 41 | 42 | `VTX_CHECKER_MODULE_END(instr_aessub_dec) 43 | -------------------------------------------------------------------------------- /benchmarks/472-mips-pipelined/mux2.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // Title : 2-1 multiplexer 3 | // Project : ECE 313 - Computer Organization 4 | //----------------------------------------------------------------------------- 5 | // File : mux2.v 6 | // Author : John Nestor 7 | // Organization : Lafayette College 8 | // 9 | // Created : October 2002 10 | // Last modified : 7 January 2005 11 | //----------------------------------------------------------------------------- 12 | // Description : 13 | // Parameterized 2-1 mux used in the implementations of the MIPS processor 14 | // subset described in Ch. 5-6 of "Computer Organization and Design, 3rd ed." 15 | // by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e). 16 | // 17 | //----------------------------------------------------------------------------- 18 | 19 | module mux2( sel, a, b, y ); 20 | parameter bitwidth=32; 21 | 22 | input sel; 23 | input [bitwidth-1:0] a, b; 24 | output [bitwidth-1:0] y; 25 | 26 | assign y = sel ? b : a; 27 | endmodule 28 | -------------------------------------------------------------------------------- /benchmarks/fpu2/COPYING.txt: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012 Jonathan P Dawson 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in 11 | all copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | THE SOFTWARE. 20 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_padd.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_padd) 15 | 16 | // Pack width of the instruction 17 | wire [2:0] pw = `VTX_INSTR_PACK_WIDTH; 18 | 19 | // Compute expected result into register called "result". See 20 | // `verif/formal/fml_pack_widths.vh` for macro definition. 21 | `PACK_WIDTH_ARITH_OPERATION_RESULT(+,0) 22 | 23 | // 24 | // padd 25 | // 26 | `VTX_CHECK_INSTR_BEGIN(padd) 27 | 28 | // Correct pack width encoding value or instruction gives in bad 29 | // opcode result. 30 | `VTX_ASSERT_PACK_WIDTH_CORRECT 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | if(vtx_instr_result == SCARV_COP_INSN_SUCCESS) begin 34 | `VTX_ASSERT_CRD_VALUE_IS(result) 35 | end 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(padd) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_psub.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_psub) 15 | 16 | // Pack width of the instruction 17 | wire [2:0] pw = `VTX_INSTR_PACK_WIDTH; 18 | 19 | // Compute expected result into register called "result". See 20 | // `verif/formal/fml_pack_widths.vh` for macro definition. 21 | `PACK_WIDTH_ARITH_OPERATION_RESULT(-,0) 22 | 23 | // 24 | // psub 25 | // 26 | `VTX_CHECK_INSTR_BEGIN(psub) 27 | 28 | // Correct pack width encoding value or instruction gives in bad 29 | // opcode result. 30 | `VTX_ASSERT_PACK_WIDTH_CORRECT 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | if(vtx_instr_result == SCARV_COP_INSN_SUCCESS) begin 34 | `VTX_ASSERT_CRD_VALUE_IS(result) 35 | end 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(psub) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_aessub_enc.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_aessub_enc) 14 | 15 | // AES Inverse sbox function. 16 | `include "fml_aes_aux.vh" 17 | 18 | wire [7:0] t0 = sbox_fwd(`CRS1[ 7: 0]); 19 | wire [7:0] t1 = sbox_fwd(`CRS2[15: 8]); 20 | wire [7:0] t2 = sbox_fwd(`CRS1[23:16]); 21 | wire [7:0] t3 = sbox_fwd(`CRS2[31:24]); 22 | 23 | wire [31:0] aes_subenc_expected = {t3,t2,t1,t0}; 24 | 25 | // 26 | // aes_sub_enc 27 | // 28 | `VTX_CHECK_INSTR_BEGIN(aessub_enc) 29 | 30 | // Value of destination register post instruction should be the same 31 | // as the most recent 32-bit random sample. 32 | `VTX_ASSERT_CRD_VALUE_IS(aes_subenc_expected); 33 | 34 | // Always succeeds 35 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 36 | 37 | // Never writes to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(aes_sub_enc) 41 | 42 | `VTX_CHECKER_MODULE_END(instr_aessub_enc) 43 | 44 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_prot.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_prot) 15 | 16 | // Pack width of the instruction 17 | wire [2:0] pw = `VTX_INSTR_PACK_WIDTH; 18 | 19 | // Compute expected result into register called "result". See 20 | // `verif/formal/fml_pack_widths.vh` for macro definition. 21 | `PACK_WIDTH_ROTATE_RIGHT_OPERATION(`CRS2[4:0]) 22 | 23 | // 24 | // prot 25 | // 26 | `VTX_CHECK_INSTR_BEGIN(prot) 27 | 28 | // Correct pack width encoding value or instruction gives in bad 29 | // opcode result. 30 | `VTX_ASSERT_PACK_WIDTH_CORRECT 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | if(vtx_instr_result == SCARV_COP_INSN_SUCCESS) begin 34 | `VTX_ASSERT_CRD_VALUE_IS(result) 35 | end 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(prot) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_psll.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_psll) 15 | 16 | // Pack width of the instruction 17 | wire [2:0] pw = `VTX_INSTR_PACK_WIDTH; 18 | 19 | // Compute expected result into register called "result". See 20 | // `verif/formal/fml_pack_widths.vh` for macro definition. 21 | `PACK_WIDTH_SHIFT_OPERATION_RESULT(<<,`CRS2[4:0]) 22 | 23 | // 24 | // psll 25 | // 26 | `VTX_CHECK_INSTR_BEGIN(psll) 27 | 28 | // Correct pack width encoding value or instruction gives in bad 29 | // opcode result. 30 | `VTX_ASSERT_PACK_WIDTH_CORRECT 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | if(vtx_instr_result == SCARV_COP_INSN_SUCCESS) begin 34 | `VTX_ASSERT_CRD_VALUE_IS(result) 35 | end 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(psll) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_psrl.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | `include "fml_pack_widths.vh" 13 | 14 | `VTX_CHECKER_MODULE_BEGIN(instr_psrl) 15 | 16 | // Pack width of the instruction 17 | wire [2:0] pw = `VTX_INSTR_PACK_WIDTH; 18 | 19 | // Compute expected result into register called "result". See 20 | // `verif/formal/fml_pack_widths.vh` for macro definition. 21 | `PACK_WIDTH_SHIFT_OPERATION_RESULT(>>,`CRS2[4:0]) 22 | 23 | // 24 | // psrl 25 | // 26 | `VTX_CHECK_INSTR_BEGIN(psrl) 27 | 28 | // Correct pack width encoding value or instruction gives in bad 29 | // opcode result. 30 | `VTX_ASSERT_PACK_WIDTH_CORRECT 31 | 32 | // Result comes from the PACK_WIDTH_ARITH_OPERATION_RESULT macro. 33 | if(vtx_instr_result == SCARV_COP_INSN_SUCCESS) begin 34 | `VTX_ASSERT_CRD_VALUE_IS(result) 35 | end 36 | 37 | // Never causes writeback to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(psrl) 41 | 42 | `VTX_CHECKER_MODULE_END 43 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/22-slli-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0xF4F3 7 | xc.ld.liu c0, 0xF2F1 8 | xc.ld.hiu c1, 0x1111 9 | xc.ld.liu c1, 0x1111 10 | xc.ld.hiu c9, 0xFFFF 11 | xc.ld.liu c9, 0xFFFF 12 | 13 | xc.xcr2gpr x1, c0 14 | xc.xcr2gpr x1, c1 15 | 16 | xc.msll.i (c2,c3), c0, c1, 1 17 | xc.xcr2gpr x1, c2 18 | xc.xcr2gpr x1, c3 19 | 20 | xc.msll.i (c4,c5), c1, c0, 2 21 | xc.xcr2gpr x1, c4 22 | xc.xcr2gpr x1, c5 23 | 24 | xc.msll.i (c6,c7), c9, c1, 4 25 | xc.xcr2gpr x1, c6 26 | xc.xcr2gpr x1, c7 27 | 28 | xc.msll.i (c8,c9), c0, c9, 8 29 | xc.xcr2gpr x1, c8 30 | xc.xcr2gpr x1, c9 31 | 32 | xc.msll.i (c2,c3), c0, c1, 3 33 | xc.msll.i (c4,c5), c1, c0, 5 34 | xc.msll.i (c6,c7), c9, c1, 12 35 | xc.msll.i (c8,c9), c0, c9, 15 36 | 37 | xc.xcr2gpr x1, c0 38 | xc.xcr2gpr x1, c1 39 | xc.xcr2gpr x1, c2 40 | xc.xcr2gpr x1, c3 41 | xc.xcr2gpr x1, c4 42 | xc.xcr2gpr x1, c5 43 | xc.xcr2gpr x1, c6 44 | xc.xcr2gpr x1, c7 45 | xc.xcr2gpr x1, c8 46 | xc.xcr2gpr x1, c9 47 | 48 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/25-srli-mp.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0xF4F3 7 | xc.ld.liu c0, 0xF2F1 8 | xc.ld.hiu c1, 0x1111 9 | xc.ld.liu c1, 0x1111 10 | xc.ld.hiu c9, 0xFFFF 11 | xc.ld.liu c9, 0xFFFF 12 | 13 | xc.xcr2gpr x1, c0 14 | xc.xcr2gpr x1, c1 15 | 16 | xc.msrl.i (c2,c3), c0, c1, 1 17 | xc.xcr2gpr x1, c2 18 | xc.xcr2gpr x1, c3 19 | 20 | xc.msrl.i (c4,c5), c1, c0, 2 21 | xc.xcr2gpr x1, c4 22 | xc.xcr2gpr x1, c5 23 | 24 | xc.msrl.i (c6,c7), c9, c1, 4 25 | xc.xcr2gpr x1, c6 26 | xc.xcr2gpr x1, c7 27 | 28 | xc.msrl.i (c8,c9), c0, c9, 8 29 | xc.xcr2gpr x1, c8 30 | xc.xcr2gpr x1, c9 31 | 32 | xc.msrl.i (c2,c3), c0, c1, 3 33 | xc.msrl.i (c4,c5), c1, c0, 5 34 | xc.msrl.i (c6,c7), c9, c1, 12 35 | xc.msrl.i (c8,c9), c0, c9, 15 36 | 37 | xc.xcr2gpr x1, c0 38 | xc.xcr2gpr x1, c1 39 | xc.xcr2gpr x1, c2 40 | xc.xcr2gpr x1, c3 41 | xc.xcr2gpr x1, c4 42 | xc.xcr2gpr x1, c5 43 | xc.xcr2gpr x1, c6 44 | xc.xcr2gpr x1, c7 45 | xc.xcr2gpr x1, c8 46 | xc.xcr2gpr x1, c9 47 | 48 | -------------------------------------------------------------------------------- /test/secverilog/secverilog.v: -------------------------------------------------------------------------------- 1 | module bug(clk, in, out); 2 | 3 | input wire {L} clk; 4 | input wire[1:0] {L} in; 5 | output reg[63:0] {L} out; 6 | 7 | reg[63:0] {L} wallclock; 8 | 9 | // state = 0 ==> read input 10 | // state = 1 ==> compute step 1 11 | // state = 2 ==> compute step 2 12 | reg[1:0] {ZL state} state = 0; // ZL(0)=L, ZL(n>0)=H 13 | 14 | reg[31:0] {H} secret; 15 | reg[1:0] {H} inH; 16 | 17 | always @(posedge clk) begin 18 | wallclock <= wallclock + 1; 19 | 20 | case (state) 21 | 0: begin 22 | inH <= in; 23 | if (in[0] == 0) begin 24 | out <= 0; 25 | state <= 1; 26 | end else begin 27 | out <= wallclock; 28 | state <= 0; 29 | end 30 | end 31 | 1: begin 32 | if (secret == 0 || inH == 0) begin 33 | state <= 2; 34 | secret <= 0; 35 | end else begin 36 | state <= 3; 37 | end 38 | end 39 | 2: begin // pc = ZL state 40 | state <= 0; 41 | end 42 | 3: begin // pc = ZL state 43 | state <= 4; 44 | end 45 | 4: begin // pc = ZL state 46 | state <= 0; 47 | end 48 | endcase 49 | end 50 | 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /benchmarks/fpu/test_vectors/README: -------------------------------------------------------------------------------- 1 | 2 | Test Vectors 3 | ============ 4 | 5 | To make all the test vectors you need a program called 'pg'. 6 | The included 'pg' is a Windows executable, build on a NT 7 | system. If you need to compile your own 'pg' see the README 8 | file in pg-src directory. 9 | 10 | The script 'mkall' builds all test vectors and places them 11 | in to the proper directories. 12 | 13 | The script 'mkall_cfmp' builds all test vectors for FP compare 14 | and places them in to the proper directories. 15 | 16 | There are currently two types of tests: 17 | 18 | 1) Directed Test. This test, test a specific funstional unit 19 | and a specific rounding mode. They are located in the 20 | directories rtne, rtzero, rup and rdown (Which represent 21 | the different rounding modes). 22 | 23 | 2) Completely Random Tests. Here the operation type and rounding 24 | mode are randomly selected and may change every cycle. This 25 | tests are located in the combo directory. 26 | 27 | There are currently 14,808,684 FPU test vectors and 600,188 FP 28 | compare test vectors! 29 | 30 | WARNING: You need about 480Mb of disk space to build all test 31 | vectors !!! -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_aessub_decrot.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_aessub_decrot) 14 | 15 | // AES Inverse sbox function. 16 | `include "fml_aes_aux.vh" 17 | 18 | wire [7:0] t0_in = `CRS1[ 7: 0]; 19 | wire [7:0] t1_in = `CRS2[15: 8]; 20 | wire [7:0] t2_in = `CRS1[23:16]; 21 | wire [7:0] t3_in = `CRS2[31:24]; 22 | 23 | wire [7:0] t0 = sbox_inv(t0_in); 24 | wire [7:0] t1 = sbox_inv(t1_in); 25 | wire [7:0] t2 = sbox_inv(t2_in); 26 | wire [7:0] t3 = sbox_inv(t3_in); 27 | 28 | wire [31:0] aes_subdec_rot_expected = {t2,t1,t0,t3}; 29 | 30 | // 31 | // aes_sub_decrot 32 | // 33 | `VTX_CHECK_INSTR_BEGIN(aessub_decrot) 34 | 35 | `VTX_ASSERT_CRD_VALUE_IS(aes_subdec_rot_expected); 36 | 37 | // Always succeeds 38 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 39 | 40 | // Never writes to GPRS 41 | `VTX_ASSERT_WEN_IS_CLEAR 42 | 43 | `VTX_CHECK_INSTR_END(aes_sub_decrot) 44 | 45 | `VTX_CHECKER_MODULE_END(instr_aessub_decrot) 46 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/formal/fml_chk_instr_aessub_encrot.v: -------------------------------------------------------------------------------- 1 | // 2 | // SCARV Project 3 | // 4 | // University of Bristol 5 | // 6 | // RISC-V Cryptographic Instruction Set Extension 7 | // 8 | // Reference Implementation 9 | // 10 | // 11 | 12 | 13 | `VTX_CHECKER_MODULE_BEGIN(instr_aessub_encrot) 14 | 15 | // AES Inverse sbox function. 16 | `include "fml_aes_aux.vh" 17 | 18 | wire [7:0] t0 = sbox_fwd(`CRS1[ 7: 0]); 19 | wire [7:0] t1 = sbox_fwd(`CRS2[15: 8]); 20 | wire [7:0] t2 = sbox_fwd(`CRS1[23:16]); 21 | wire [7:0] t3 = sbox_fwd(`CRS2[31:24]); 22 | 23 | wire [31:0] aes_subenc_rot_expected = {t2,t1,t0,t3}; 24 | 25 | // 26 | // aes_sub_encrot 27 | // 28 | `VTX_CHECK_INSTR_BEGIN(aessub_encrot) 29 | 30 | // Value of destination register post instruction should be the same 31 | // as the most recent 32-bit random sample. 32 | `VTX_ASSERT_CRD_VALUE_IS(aes_subenc_rot_expected); 33 | 34 | // Always succeeds 35 | `VTX_ASSERT_RESULT_IS(SCARV_COP_INSN_SUCCESS) 36 | 37 | // Never writes to GPRS 38 | `VTX_ASSERT_WEN_IS_CLEAR 39 | 40 | `VTX_CHECK_INSTR_END(aes_sub_encrot) 41 | 42 | `VTX_CHECKER_MODULE_END(instr_aessub_encrot) 43 | 44 | 45 | -------------------------------------------------------------------------------- /benchmarks/xcrypto-ref/verif/unit/39-aes-mix.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | 4 | test_start: 5 | 6 | xc.ld.hiu c0, 0x4553 7 | xc.ld.liu c0, 0x13db 8 | xc.ld.hiu c1, 0x4553 9 | xc.ld.liu c1, 0x13db 10 | 11 | xc.aesmix.enc c2, c0, c1 12 | xc.xcr2gpr a0, c2 13 | 14 | xc.aesmix.dec c3, c2, c2 15 | xc.xcr2gpr a0, c3 16 | 17 | xc.ld.hiu c0, 0x0101 18 | xc.ld.liu c0, 0x0101 19 | xc.ld.hiu c1, 0x0101 20 | xc.ld.liu c1, 0x0101 21 | 22 | xc.aesmix.enc c2, c0, c1 23 | xc.xcr2gpr a0, c2 24 | 25 | xc.aesmix.dec c3, c2, c2 26 | xc.xcr2gpr a0, c3 27 | 28 | xc.ld.hiu c0, 0xc6c6 29 | xc.ld.liu c0, 0xc6c6 30 | xc.ld.hiu c1, 0xc6c6 31 | xc.ld.liu c1, 0xc6c6 32 | 33 | xc.aesmix.enc c2, c0, c1 34 | xc.xcr2gpr a0, c2 35 | 36 | xc.aesmix.dec c3, c2, c2 37 | xc.xcr2gpr a0, c3 38 | 39 | xc.ld.hiu c0, 0xd5d4 40 | xc.ld.liu c0, 0xd4d4 41 | xc.ld.hiu c1, 0xd5d4 42 | xc.ld.liu c1, 0xd4d4 43 | 44 | xc.aesmix.enc c2, c0, c1 45 | xc.xcr2gpr a0, c2 46 | 47 | xc.aesmix.dec c3, c2, c2 48 | xc.xcr2gpr a0, c3 49 | --------------------------------------------------------------------------------