├── docs ├── sim │ ├── spice.rst │ ├── ngspice.rst │ └── spectre.rst ├── python-api ├── analog │ ├── bag.rst │ ├── new.rst │ ├── fasoc.rst │ ├── magic.rst │ ├── klayout.rst │ └── virtuoso.rst ├── contents │ ├── cell-index.rst │ └── libraries │ │ ├── sky130_fd_io │ │ ├── sky130_fd_pr │ │ ├── sky130_fd_sc_hd │ │ ├── sky130_fd_sc_hs │ │ ├── sky130_fd_sc_ls │ │ ├── sky130_fd_sc_ms │ │ ├── sky130_fd_sc_hdll │ │ └── Makefile ├── digital │ ├── new.rst │ ├── innovus.rst │ └── openroad.rst ├── _ext │ └── skywater_pdk ├── common.inc ├── verification │ ├── drc │ │ ├── magic.rst │ │ ├── calibre.rst │ │ └── klayout.rst │ ├── lvs │ │ ├── magic.rst │ │ ├── calibre.rst │ │ └── klayout.rst │ ├── pex │ │ ├── magic.rst │ │ ├── calibre.rst │ │ └── klayout.rst │ ├── drc.rst │ ├── pex.rst │ └── lvs.rst ├── rules │ ├── periphery.rst │ ├── periphery │ │ ├── p045-pad_dotdash.csv │ │ ├── p049-hvpoly_dotdash.csv │ │ ├── p024-hvtr_dotdash.csv │ │ ├── p043-indm_dotdash.csv │ │ ├── p047-hvi_dotdash.csv │ │ ├── p023-hvtp_dotdash.csv │ │ ├── p055-ulvt-_dotdash.csv │ │ ├── p044-m5_dotdash.csv │ │ ├── p032-npc_dotdash.csv │ │ ├── p022-pwbm_dotdash.csv │ │ ├── p057-rfdiode_dotdash_dotdash.csv │ │ ├── p022-pwdem_dotdash.csv │ │ ├── p027-tunm_dotdash.csv │ │ ├── p045-rdl_dotdash.csv │ │ ├── p030-varac_dotdash.csv │ │ ├── p055-uhvi_dotdash_dotdash.csv │ │ ├── p035-li_dotdash_dotdash.csv │ │ ├── p025-ncm_dotdash.csv │ │ ├── p035-ct_dotdash.csv │ │ ├── p024-lvtn_dotdash.csv │ │ ├── p031-photo_dotdash.csv │ │ ├── p036-capm_dotdash.csv │ │ ├── p020-dnwell_dotdash.csv │ │ ├── p047-hvnwell_dotdash.csv │ │ ├── p044-via4_dotdash.csv │ │ ├── p049-hvntm_dotdash.csv │ │ ├── p052-extd_dotdash.csv │ │ ├── p056-pwres_dotdash_dotdash.csv │ │ ├── p043-nsm_dotdash.csv │ │ ├── p051-depmos_dotdash.csv │ │ ├── p032-n_psd_dotdash.csv │ │ ├── p050-denmos_dotdash.csv │ │ ├── p021-nwell_dotdash.csv │ │ ├── p042-via3_dotdash.csv │ │ ├── p048-hvdifftap_dotdash.csv │ │ ├── p055-vhvi_dotdash_dotdash.csv │ │ ├── p026-difftap_dotdash.csv │ │ ├── p029-rpm_dotdash.csv │ │ ├── p028-poly_dotdash.csv │ │ ├── p046-mf_dotdash.csv │ │ ├── p039-via_dotdash.csv │ │ ├── p041-via2_dotdash.csv │ │ ├── p044-m4_dotdash.csv │ │ ├── p040-m2_dotdash.csv │ │ └── p038-m1_dotdash.csv │ ├── assumptions │ │ ├── 01-general.csv │ │ ├── 10-vpp-capacitor.csv │ │ ├── 09-polyimide.csv │ │ ├── 08-hv.csv │ │ └── 05-laser-fuse.csv │ ├── layers │ │ ├── table-f2b-mask-key.rst │ │ ├── table-c4a-layer-description.csv │ │ ├── table-f2a-lvs-print.py │ │ ├── table-f2b-mask-print.py │ │ └── table-f2a-lvs-key.rst │ ├── summary │ │ ├── table-f5-device-connectivity.csv │ │ ├── table-f3b-font-end-high-voltage.csv │ │ ├── table-f4-key.rst │ │ ├── table-f3d-back-end-high-S8Tx.csv │ │ ├── table-f3c-back-end-high-S8Dx.csv │ │ ├── table-f4-connectivity-of-drawn-and-mask.csv │ │ └── table-f3a-font-end-low-voltage.csv │ ├── wlcsp.rst │ ├── hv │ │ ├── table-2-key.rst │ │ ├── table-1-key.rst │ │ ├── table-2.csv │ │ └── table-1.csv │ ├── rcx │ │ ├── capacitance-fringe-upward.tsv │ │ ├── capacitance-fringe-downward.tsv │ │ ├── capacitance-parallel.tsv │ │ ├── resistance-values.tsv │ │ └── table-rcx-all-print.py │ ├── antenna │ │ ├── definitions.csv │ │ ├── table-Ia-antenna-rules-s8d.csv │ │ ├── table-Ib-antenna-rules-s8tnv-5r.csv │ │ ├── table-Ic-antenna-rules-s8tm.csv │ │ ├── table-Ie-antenna-rules-s8p.csv │ │ └── table-Ig-antenna-rules-s8p12.csv │ ├── device-details │ │ ├── special_sonosfet │ │ │ ├── special_sonosfet-table0.rst │ │ │ ├── special_sonosfet-table1.rst │ │ │ └── index.rst │ │ ├── pfet_01v8 │ │ │ ├── pfet_01v8-table1.rst │ │ │ ├── index.rst │ │ │ └── pfet_01v8-table0.rst │ │ ├── pfet_01v8_hvt │ │ │ ├── pfet_01v8_hvt-table1.rst │ │ │ ├── index.rst │ │ │ └── pfet_01v8_hvt-table0.rst │ │ ├── pfet_01v8_lvt │ │ │ ├── pfet_01v8_lvt-table1.rst │ │ │ ├── index.rst │ │ │ └── pfet_01v8_lvt-table0.rst │ │ ├── nfet_01v8_lvt │ │ │ ├── nfet_01v8_lvt-table1.rst │ │ │ ├── index.rst │ │ │ └── nfet_01v8_lvt-table0.rst │ │ ├── pfet_g5v0d10v5 │ │ │ ├── pfet_g5v0d10v5-table1.rst │ │ │ ├── index.rst │ │ │ └── pfet_g5v0d10v5-table0.rst │ │ ├── cap_mim │ │ │ ├── cap_mim-table0.rst │ │ │ └── index.rst │ │ ├── nfet_g5v0d10v5 │ │ │ ├── index.rst │ │ │ └── nfet_g5v0d10v5-table0.rst │ │ ├── special_sram │ │ │ ├── special_sram-table0.rst │ │ │ ├── special_sram-table1.rst │ │ │ ├── special_sram-table2.rst │ │ │ └── index.rst │ │ ├── nfet_20v0_zvt │ │ │ └── index.rst │ │ ├── nfet_01v8 │ │ │ ├── index.rst │ │ │ └── nfet_01v8-table0.rst │ │ ├── pfet_g5v0d16v0 │ │ │ ├── index.rst │ │ │ └── pfet_g5v0d16v0-table0.rst │ │ ├── nfet_g11v0d16v0 │ │ │ ├── index.rst │ │ │ └── nfet_g11v0d16v0-table0.rst │ │ ├── nfet_20v0_nvt │ │ │ └── index.rst │ │ ├── diodes │ │ │ └── diodes-table0.rst │ │ ├── nfet_20v0 │ │ │ └── index.rst │ │ ├── pfet_20v0 │ │ │ ├── index.rst │ │ │ └── pfet_20v0-table0.rst │ │ ├── nfet_20v0_iso │ │ │ └── index.rst │ │ ├── nfet_05v0_nvt │ │ │ └── index.rst │ │ ├── nfet_03v3_nvt │ │ │ └── index.rst │ │ ├── cap_var │ │ │ ├── cap_var-table0.rst │ │ │ └── index.rst │ │ ├── pnp_05v0 │ │ │ ├── pnp_05v0-table0.rst │ │ │ └── index.rst │ │ ├── esd_nfet │ │ │ ├── esd_nfet-table0.rst │ │ │ └── index.rst │ │ ├── npn_05v0 │ │ │ ├── index.rst │ │ │ └── npn_05v0-table0.rst │ │ └── nfet_03v3_nvt-and-nfet_05v0_nvt │ │ │ └── nfet_03v3_nvt-and-nfet_05v0_nvt-table0.rst │ ├── errors.rst │ ├── masks.rst │ ├── background.rst │ ├── summary.rst │ ├── masks.csv │ ├── device-details.py │ ├── layers.rst │ └── wlcsp │ │ └── amkor.csv ├── _static │ ├── logo │ │ ├── um_logo.png │ │ ├── auc_logo.png │ │ ├── ucsc_logo.png │ │ ├── ucsd_logo.png │ │ ├── google-logo.png │ │ ├── antmicro_logo.png │ │ ├── efabless_logo.png │ │ ├── skywater-logo.png │ │ └── osu_logo.svg │ ├── SkyWater_logo.jpg │ ├── favicon │ │ ├── favicon.ico │ │ ├── favicon-16x16.png │ │ ├── favicon-32x32.png │ │ ├── mstile-150x150.png │ │ ├── apple-touch-icon.png │ │ ├── android-chrome-144x144.png │ │ ├── apple-touch-icon-precomposed.png │ │ ├── browserconfig.xml │ │ ├── site.webmanifest │ │ ├── html_code.html │ │ └── safari-pinned-tab.svg │ ├── skywater-favicon.png │ ├── skywater-pdk-logo.png │ ├── skywater-pdk-logo-top.png │ └── extra.css ├── references.rst ├── contents.rst ├── digital.rst ├── refs.bib ├── analog.rst ├── requirements.txt ├── rules.rst ├── sim.rst ├── license_header.txt ├── _templates │ └── relbar.html ├── environment.yml ├── status.rst ├── contributing.rst ├── verification.rst ├── index.rst ├── versioning.rst └── fixup-headers.py ├── scripts ├── python-skywater-pdk │ ├── docs │ │ ├── index.rst │ │ └── skywater_pdk.rst │ ├── skywater_pdk │ │ └── __init__.py │ └── README.rst └── make │ └── git.mk ├── .github ├── PULL_REQUEST_TEMPLATE.md ├── ISSUE_TEMPLATE.md ├── dependabot.yml ├── workflows │ ├── labeler.yml │ └── manage-labels.yml ├── kokoro │ ├── continuous.cfg │ ├── presubmit.cfg │ ├── steps │ │ ├── auth.sh │ │ ├── hostsetup.sh │ │ ├── git.sh │ │ └── hostinfo.sh │ └── run.sh └── travis │ ├── git-check.sh │ └── common.sh ├── requirements.txt ├── AUTHORS ├── environment.yml ├── .travis.yml └── .readthedocs.yml /docs/sim/spice.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/python-api: -------------------------------------------------------------------------------- 1 | ../scripts/python-skywater-pdk/docs/ -------------------------------------------------------------------------------- /docs/analog/bag.rst: -------------------------------------------------------------------------------- 1 | TODO: analog/bag 2 | ================ 3 | -------------------------------------------------------------------------------- /docs/analog/new.rst: -------------------------------------------------------------------------------- 1 | TODO: analog/new 2 | ================ 3 | -------------------------------------------------------------------------------- /docs/contents/cell-index.rst: -------------------------------------------------------------------------------- 1 | .. cross_index:: libraries/* 2 | -------------------------------------------------------------------------------- /docs/analog/fasoc.rst: -------------------------------------------------------------------------------- 1 | TODO: analog/fasoc 2 | ================== 3 | -------------------------------------------------------------------------------- /docs/analog/magic.rst: -------------------------------------------------------------------------------- 1 | TODO: analog/magic 2 | ================== 3 | -------------------------------------------------------------------------------- /docs/digital/new.rst: -------------------------------------------------------------------------------- 1 | TODO: digital/new 2 | ================= 3 | -------------------------------------------------------------------------------- /docs/sim/ngspice.rst: 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-------------------------------------------------------------------------------- 1 | TODO: analog/virtuoso 2 | ===================== 3 | -------------------------------------------------------------------------------- /docs/common.inc: -------------------------------------------------------------------------------- 1 | .. |current-status| replace:: **Experimental Preview** 2 | -------------------------------------------------------------------------------- /docs/contents/libraries/sky130_fd_io: -------------------------------------------------------------------------------- 1 | ../../../libraries/sky130_fd_io/latest -------------------------------------------------------------------------------- /docs/contents/libraries/sky130_fd_pr: -------------------------------------------------------------------------------- 1 | ../../../libraries/sky130_fd_pr/latest -------------------------------------------------------------------------------- /docs/digital/innovus.rst: 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/docs/contents/libraries/sky130_fd_sc_ms: -------------------------------------------------------------------------------- 1 | ../../../libraries/sky130_fd_sc_ms/latest -------------------------------------------------------------------------------- /docs/digital/openroad.rst: -------------------------------------------------------------------------------- 1 | TODO: digital/openroad 2 | ====================== 3 | -------------------------------------------------------------------------------- /docs/contents/libraries/sky130_fd_sc_hdll: -------------------------------------------------------------------------------- 1 | ../../../libraries/sky130_fd_sc_hdll/latest -------------------------------------------------------------------------------- /docs/verification/drc/magic.rst: -------------------------------------------------------------------------------- 1 | TODO: verification/drc/magic 2 | ============================ 3 | -------------------------------------------------------------------------------- /docs/verification/lvs/magic.rst: -------------------------------------------------------------------------------- 1 | TODO: verification/lvs/magic 2 | ============================ 3 | -------------------------------------------------------------------------------- /docs/verification/pex/magic.rst: -------------------------------------------------------------------------------- 1 | TODO: verification/pex/magic 2 | ============================ 3 | -------------------------------------------------------------------------------- /docs/verification/drc/calibre.rst: -------------------------------------------------------------------------------- 1 | TODO: verification/drc/calibre 2 | ============================== 3 | -------------------------------------------------------------------------------- /docs/verification/drc/klayout.rst: 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-------------------------------------------------------------------------------- /docs/verification/pex/klayout.rst: -------------------------------------------------------------------------------- 1 | TODO: verification/pex/klayout 2 | ============================== 3 | -------------------------------------------------------------------------------- /docs/rules/periphery.rst: -------------------------------------------------------------------------------- 1 | Periphery Rules 2 | =============== 3 | 4 | .. include:: periphery-rules.rst 5 | -------------------------------------------------------------------------------- /docs/_static/logo/um_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/google/skywater-pdk/HEAD/docs/_static/logo/um_logo.png -------------------------------------------------------------------------------- /docs/_static/SkyWater_logo.jpg: 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References 4 | ########## 5 | 6 | .. bibliography:: 7 | :notcited: 8 | :labelprefix: R 9 | -------------------------------------------------------------------------------- /docs/_static/favicon/android-chrome-144x144.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/google/skywater-pdk/HEAD/docs/_static/favicon/android-chrome-144x144.png -------------------------------------------------------------------------------- /docs/_static/favicon/apple-touch-icon-precomposed.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/google/skywater-pdk/HEAD/docs/_static/favicon/apple-touch-icon-precomposed.png -------------------------------------------------------------------------------- /docs/rules/periphery/p045-pad_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (pad.2),Min spacing of pad:dg to pad:dg,,1.270,µm 3 | (pad.3),Max area of hugePad NOT top_metal,,30000,µm² 4 | -------------------------------------------------------------------------------- /docs/rules/assumptions/01-general.csv: -------------------------------------------------------------------------------- 1 | Parameter,,Units,Value,,Variable name 2 | Space to Draw,, ,S8,, 3 | Grid Size - Drawn,,um,0.005,,GSF 4 | Approximate Scale Factor for R32 data,,,0.3,,sfr32 5 | -------------------------------------------------------------------------------- /docs/contents/libraries/Makefile: -------------------------------------------------------------------------------- 1 | update: 2 | for i in ../../../libraries/*; do \ 3 | if [ ! -d $$i ]; then continue; fi; \ 4 | ln -sf -T $$i/latest $$(basename $$i); \ 5 | done 6 | git add * 7 | -------------------------------------------------------------------------------- /docs/rules/periphery/p049-hvpoly_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvpoly.13),Min width of poly over diff inside Hvi,P,0.500,µm 3 | (hvpoly.14),(poly and diff) cannot straddle Hvi,,, 4 | -------------------------------------------------------------------------------- /scripts/python-skywater-pdk/docs/index.rst: -------------------------------------------------------------------------------- 1 | SkyWater PDK Python API 2 | ======================= 3 | 4 | TODO: Add documentation here 5 | 6 | .. toctree:: 7 | :hidden: 8 | 9 | skywater_pdk 10 | -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | Fixes # 2 | 3 | > It's a good idea to open an issue first for discussion. 4 | 5 | - [ ] Tests pass 6 | - [ ] Appropriate changes to README are included in PR -------------------------------------------------------------------------------- /docs/contents.rst: -------------------------------------------------------------------------------- 1 | PDK Contents 2 | ============ 3 | 4 | .. toctree:: 5 | :name: pdk-contents 6 | :maxdepth: 4 7 | 8 | Libraries 9 | File Types 10 | -------------------------------------------------------------------------------- /docs/verification/drc.rst: -------------------------------------------------------------------------------- 1 | Design Rule Verification 2 | ======================== 3 | 4 | .. toctree:: 5 | 6 | With Mentor Calibre 7 | With Magic 8 | With KLayout 9 | -------------------------------------------------------------------------------- /docs/verification/pex.rst: -------------------------------------------------------------------------------- 1 | Parasitics Extraction (PEX) 2 | =========================== 3 | 4 | .. toctree:: 5 | 6 | With Mentor Calibre 7 | With Magic 8 | With KLayout 9 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | ## Expected Behavior 2 | 3 | 4 | ## Actual Behavior 5 | 6 | 7 | ## Steps to Reproduce the Problem 8 | 9 | 1. 10 | 1. 11 | 1. 12 | 13 | ## Specifications 14 | 15 | - Version: 16 | - Platform: -------------------------------------------------------------------------------- /docs/rules/periphery/p024-hvtr_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvtr.1),Min width of hvtr,,0.380,µm 3 | (hvtr.2),Min spacing between hvtp to hvtr,,0.380,µm 4 | (hvtr.3),Min enclosure of pfet by hvtr,P,0.180,µm 5 | -------------------------------------------------------------------------------- /docs/verification/lvs.rst: -------------------------------------------------------------------------------- 1 | Layout verse Schematic (LVS) Verification 2 | ========================================= 3 | 4 | .. toctree:: 5 | 6 | With Mentor Calibre 7 | With Magic 8 | With KLayout 9 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | flake8 2 | wavedrom 3 | 4 | # rst_include tool as GitHub doesn't support `.. include::` when rendering 5 | # previews. 6 | rst_include 7 | 8 | # The Python API for the SkyWater PDK. 9 | -e scripts/python-skywater-pdk 10 | -------------------------------------------------------------------------------- /docs/digital.rst: -------------------------------------------------------------------------------- 1 | Digital Design 2 | ============== 3 | 4 | .. toctree:: 5 | :caption: Digital Design 6 | :name: digital 7 | 8 | With Cadence Innovus 9 | With OpenROAD 10 | With your design flow? 11 | -------------------------------------------------------------------------------- /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | # Set update schedule for GitHub Actions 2 | version: 2 3 | updates: 4 | 5 | - package-ecosystem: "github-actions" 6 | directory: "/" 7 | schedule: 8 | # Check for updates to GitHub Actions every weekday 9 | interval: "daily" 10 | -------------------------------------------------------------------------------- /docs/refs.bib: -------------------------------------------------------------------------------- 1 | @Online{SkyWaterPDKIntro_Edwards21, 2 | author = {Edwards, Tim}, 3 | title = {{Introduction to the SkyWater PDK: The New Age of Open Source Silicon}}, 4 | url = {https://isn.ucsd.edu/courses/beng207/lectures/Tim_Edwards_2021_slides.pdf}, 5 | year = {2021}, 6 | } 7 | -------------------------------------------------------------------------------- /.github/workflows/labeler.yml: -------------------------------------------------------------------------------- 1 | name: "Pull Request Labeler" 2 | on: 3 | - pull_request_target 4 | 5 | jobs: 6 | triage: 7 | runs-on: ubuntu-latest 8 | steps: 9 | - uses: actions/labeler@main 10 | with: 11 | repo-token: "${{ secrets.GITHUB_TOKEN }}" 12 | -------------------------------------------------------------------------------- /docs/rules/layers/table-f2b-mask-key.rst: -------------------------------------------------------------------------------- 1 | Explanation of symbols: 2 | 3 | * ``-`` = Layer not created for the device 4 | * ``+`` = Layer allowed to overlap 5 | * ``C`` = CREATED 6 | * ``nr`` = next revision 7 | 8 | .. rubric:: Footnotes 9 | 10 | .. [#fb1] For RCX information 11 | -------------------------------------------------------------------------------- /.github/kokoro/continuous.cfg: -------------------------------------------------------------------------------- 1 | # Format: kokoro/config/proto/build.proto 2 | 3 | build_file: "skywater-pdk/.github/kokoro/run.sh" 4 | 5 | env_vars { 6 | key: "KOKORO_TYPE" 7 | value: "continuous" 8 | } 9 | 10 | env_vars { 11 | key: "KOKORO_DIR" 12 | value: "skywater-pdk" 13 | } 14 | -------------------------------------------------------------------------------- /.github/kokoro/presubmit.cfg: -------------------------------------------------------------------------------- 1 | # Format: kokoro/config/proto/build.proto 2 | 3 | build_file: "skywater-pdk/.github/kokoro/run.sh" 4 | 5 | env_vars { 6 | key: "KOKORO_TYPE" 7 | value: "presubmit" 8 | } 9 | 10 | env_vars { 11 | key: "KOKORO_DIR" 12 | value: "skywater-pdk" 13 | } 14 | -------------------------------------------------------------------------------- /docs/rules/periphery/p043-indm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (indm.1),Min width of top_indmMetal,,N/A,N/A 3 | (indm.2),Min spacing between two top_indmMetal,,N/A,N/A 4 | (indm.3),top_padVia must be enclosed by top_indmMetal by atleast,,N/A,N/A 5 | (indm.4),Min area of top_indmMetal,,N/A,N/A 6 | -------------------------------------------------------------------------------- /docs/_static/favicon/browserconfig.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | #00aba9 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /docs/rules/periphery/p047-hvi_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvi.1),Min width of Hvi,P,0.600,µm 3 | (hvi.2a),Min spacing of Hvi to Hvi,P,0.700,µm 4 | (hvi.2b),Manual merge if space is below minimum,,, 5 | (hvi.4),Hvi must not overlap tunm,,, 6 | (hvi.5),Min space between hvi and nwell (exclude coincident edges),,0.700,µm 7 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f5-device-connectivity.csv: -------------------------------------------------------------------------------- 1 | Devices,LVS,Latch up,,Soft,,,,,,,,,,,,, 2 | Transistors,open,open,,open,,,,,,,,,,,,, 3 | resistor,open,open,,open,,,,,,,,,,,,, 4 | diode,open,open,,open,,,,,,,,,,,,, 5 | pnp,open,open,,open,,,,,,,,,,,,, 6 | Inductor,open,short,,open,,,,,,,,,,,,, 7 | capacitors,open,open,,open,,,,,,,,,,,,, 8 | -------------------------------------------------------------------------------- /docs/rules/periphery/p023-hvtp_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvtp.1),Min width of hvtp,,0.380,µm 3 | (hvtp.2),Min spacing between hvtp to hvtp,,0.380,µm 4 | (hvtp.3),Min enclosure of pfet by hvtp,P,0.180,µm 5 | (hvtp.4),Min spacing between pfet and hvtp,P,0.180,µm 6 | (hvtp.5),Min area of hvtp,,0.265,µm² 7 | (hvtp.6),Min area of hvtp Holes,,0.265,µm² 8 | -------------------------------------------------------------------------------- /docs/rules/wlcsp.rst: -------------------------------------------------------------------------------- 1 | WLCSP Rules 2 | =========== 3 | 4 | .. TODO: These should be formatted in the same way the periphery rules are. 5 | 6 | .. csv-table:: Amkor WLCSP 7 | :file: wlcsp/amkor.csv 8 | :header-rows: 1 9 | :stub-columns: 1 10 | 11 | .. csv-table:: DECA WLCSP 12 | :file: wlcsp/deca.csv 13 | :header-rows: 1 14 | :stub-columns: 1 15 | -------------------------------------------------------------------------------- /docs/_static/favicon/site.webmanifest: -------------------------------------------------------------------------------- 1 | { 2 | "name": "", 3 | "short_name": "", 4 | "icons": [ 5 | { 6 | "src": "/_static/favicon/android-chrome-144x144.png", 7 | "sizes": "144x144", 8 | "type": "image/png" 9 | } 10 | ], 11 | "theme_color": "#ffffff", 12 | "background_color": "#ffffff" 13 | } 14 | -------------------------------------------------------------------------------- /docs/rules/periphery/p055-ulvt-_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (ulvt-.1),":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA, 3 | (ulvt-.2),":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA, 4 | (ulvt-.3),:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA, 5 | -------------------------------------------------------------------------------- /docs/rules/hv/table-2-key.rst: -------------------------------------------------------------------------------- 1 | .. rubric:: Footnotes 2 | 3 | .. [#f8] Resistors tagged with text ""vhv_block"" serve as VHV propagation stopper and it is the duty of the designer to ensure that the resistor can support the required voltage drop. Otherwise components in VHV nets need to be tagged with vhvi:dg layer 4 | .. [#f9] If only source or drain is tagged with vhvi:dg layers. 5 | -------------------------------------------------------------------------------- /docs/rules/periphery/p044-m5_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (m5.1),Min width of met5,,1.600,µm 3 | (m5.2),Min spacing between two met5,,1.600,µm 4 | (m5.3),via4 must be enclosed by met5 by atleast,,0.310,µm 5 | (m5.4),"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000,µm² 6 | -------------------------------------------------------------------------------- /docs/rules/rcx/capacitance-fringe-upward.tsv: -------------------------------------------------------------------------------- 1 | Interlayer fringe capacitance (upward direction) (aF/um) Local interconnect Metal1 Metal2 Metal3 Metal4 Metal5 2 | Poly 25.138 16.691 11.166 9.18 6.3505 6.4903 3 | Local interconnect 34.7 21.739 15.078 10.141 7.6366 4 | Metal1 48.193 26.676 16.421 12.017 5 | Metal2 44.432 22.332 15.693 6 | Metal3 42.643 27.836 7 | Metal4 46.976 8 | -------------------------------------------------------------------------------- /docs/analog.rst: -------------------------------------------------------------------------------- 1 | Analog Design 2 | ============= 3 | 4 | .. toctree:: 5 | :caption: Analog Design 6 | :name: analog 7 | 8 | With Cadence Virtuoso 9 | With MAGIC 10 | With Klayout 11 | With Berkeley Analog Generator (BAG) 12 | With FASoC 13 | With your design flow? 14 | -------------------------------------------------------------------------------- /docs/rules/antenna/definitions.csv: -------------------------------------------------------------------------------- 1 | Symbol,Explanation,Unit 2 | PI,Perimeter of Interconnect,um 3 | FLT,Final Layer thickness,um 4 | W,Width of MOS Transistor,um 5 | L,Length of MOS Transistor,um 6 | A,Area of MOS Transistor gate (= W x L),um2 7 | CA,Area of contact or via,um2 8 | SW,Sidewall area (= PI x FLT),um2 9 | EA,"Etched area (= CA for horizontal, = SW for vertical areas)",um2 10 | -------------------------------------------------------------------------------- /docs/rules/rcx/capacitance-fringe-downward.tsv: -------------------------------------------------------------------------------- 1 | Interlayer fringe capacitance (downward direction) (aF/um) Poly Local interconnect Metal1 Metal2 Metal3 Metal4 2 | Local interconnect 51.846 3 | Metal1 46.724 59.496 4 | Metal2 41.222 46.277 67.045 5 | Metal3 43.531 46.708 54.814 69.846 6 | Metal4 38.105 39.709 42.563 46.382 70.522 7 | Metal5 39.908 41.147 43.188 45.592 54.152 82.819 8 | -------------------------------------------------------------------------------- /docs/rules/rcx/capacitance-parallel.tsv: -------------------------------------------------------------------------------- 1 | Interlayer parallel plate capacitance (aF/um^2) Local interconnect Metal1 Metal2 Metal3 Metal4 Metal5 2 | Poly 94.1644 44.8056 24.4968 16.0552 10.0131 7.2085 3 | Local interconnect 114.1970 37.5647 20.7915 11.6705 8.0265 4 | Metal1 133.8610 34.5350 15.0275 9.4789 5 | Metal2 86.1861 20.3321 11.3410 6 | Metal3 84.0346 19.6269 7 | Metal4 68.3252 8 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sonosfet/special_sonosfet-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 1 3 | :stub-columns: 1 4 | 5 | 6 | * - MODEL CORNERS (\*.cor) 7 | - Programmed 8 | - Erased 9 | 10 | * - Beginning of Life 11 | - sonos\_bol\_p 12 | - sonos\_bol\_e 13 | 14 | * - End of Life 15 | - sonos\_eol\_p 16 | - sonos\_eol\_e 17 | 18 | -------------------------------------------------------------------------------- /docs/rules/errors.rst: -------------------------------------------------------------------------------- 1 | Error Messages 2 | ============== 3 | 4 | The :download:`messages.csv file <./errors.csv>` provides a raw description for many of 5 | the automated DRC rules that are checked by SkyWater as part of the acceptance 6 | criteria for GDS data. 7 | 8 | .. csv-table:: Table - Error Messages 9 | :file: errors.csv 10 | :header-rows: 1 11 | :stub-columns: 1 12 | :widths: 10, 10, 80 13 | -------------------------------------------------------------------------------- /docs/rules/periphery/p032-npc_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (npc.1),Min width of NPC,,0.270,µm 3 | (npc.2),Min spacing of NPC to NPC,,0.270,µm 4 | (npc.3),Manual merge if less than minimum,,, 5 | (npc.4),Spacing (no overlap) of NPC to Gate,,0.090,µm 6 | (npc.5),Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095,µm 7 | -------------------------------------------------------------------------------- /docs/rules/assumptions/10-vpp-capacitor.csv: -------------------------------------------------------------------------------- 1 | Layer / Design rule,CD,,space,,Comment 2 | Min width of capacitor:dg,4.38,,,,VppWidth 3 | Max width of unit capacitor:dg,8.58,,,,VppMaxWidth 4 | Min spacing between two capacitor:dg ,1.5,,,,VppSpc 5 | Min spacing of capacitor:dg to li1 or met1 or met2 or nwell,1.5,,,,VppOtherSPc 6 | Min enclosure of capacitor by nwell,1.5,,,,VppNwmEnc 7 | Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc 8 | -------------------------------------------------------------------------------- /docs/rules/periphery/p022-pwbm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (pwbm.1),Min width of pwbm.dg,,N/A,N/A 3 | (pwbm.2),Min spacing between two pwbm.dg inside UHVI,,N/A,N/A 4 | (pwbm.3),Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A,N/A 5 | (pwbm.4),dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A,N/A 6 | (pwbm.5),Min Space between two pwbm holes inside UHVI,,N/A,N/A 7 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f3b-font-end-high-voltage.csv: -------------------------------------------------------------------------------- 1 | Layer,CD,nwell,,diff,,tap,,poly,,lvom,,Manual,,,,, 2 | Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,merge ?,,,,, 3 | hnwell,0.840,2.000,X,X,X,X,X,X,X,X,X,Yes,,,,, 4 | hvi,0.600,0.700,-,0.180,0.180,0.180,0.180,-,-,0.700,X,Yes,,,,, 5 | hdiff,0.290,0.430,0.330,0.300,X,X,X,X,X,X,X,-,,,,, 6 | htap,0.150,0.430,0.330,,-,0.270,X,X,X,X,X,-,,,,, 7 | HV poly,0.500,-,-,0.075,-,0.055,-,0.210,X,-,-,-,,,,, 8 | -------------------------------------------------------------------------------- /docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (rfdiode.1.-),Only 90 degrees allowed for :drc_tag:`areaid.re`,,, 3 | (rfdiode.2.-),:drc_tag:`areaid.re` must be coincident with nwell for the rf nwell diode,,, 4 | (rfdiode.3.-),":drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode 5 | Allowed PNP layout 6 | Layout: pnppar 7 | Allowed NPN layout 8 | Layout: npnpar1x1",,, 9 | -------------------------------------------------------------------------------- /docs/rules/masks.rst: -------------------------------------------------------------------------------- 1 | Masks 2 | ===== 3 | 4 | The :download:`masks.csv file <./masks.csv>` provides a raw information for the 5 | mask layers (name, acronym, usage) currently used found on 130nm processes at 6 | SkyWater. 7 | 8 | The masks which are used on the SKY130 technology node (that this PDK supports) 9 | are marked. 10 | 11 | .. csv-table:: Table - Masks 12 | :file: masks.csv 13 | :header-rows: 1 14 | :stub-columns: 1 15 | :widths: 70, 20, 10 16 | -------------------------------------------------------------------------------- /docs/rules/periphery/p022-pwdem_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (pwdem.1),Min width of pwdem.dg,,N/A,N/A 3 | (pwdem.2),Min spacing between two pwdem.dg inside UHVI on same net,,N/A,N/A 4 | (pwdem.3),Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A,N/A 5 | (pwdem.4),pwdem.dg must be enclosed by UHVI,,N/A,N/A 6 | (pwdem.5),pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A,N/A 7 | (pwdem.6),Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A,N/A 8 | -------------------------------------------------------------------------------- /.github/workflows/manage-labels.yml: -------------------------------------------------------------------------------- 1 | name: Manage Labels 2 | 3 | on: push 4 | 5 | jobs: 6 | labeler: 7 | runs-on: ubuntu-latest 8 | steps: 9 | - 10 | name: Checkout 11 | uses: actions/checkout@v3 12 | - 13 | name: Run Labeler 14 | if: success() 15 | uses: crazy-max/ghaction-github-labeler@v4.0.0 16 | with: 17 | yaml_file: .github/labels.yml 18 | env: 19 | GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} 20 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | git+https://github.com/SymbiFlow/sphinx_symbiflow_theme.git#egg=sphinx-symbiflow-theme 2 | 3 | docutils 4 | sphinx 5 | sphinx-autobuild 6 | sphinxcontrib-bibtex 7 | 8 | # Verilog domain 9 | sphinx-verilog-domain 10 | # Verilog diagrams using Yosys + netlistsvg 11 | sphinxcontrib-hdl-diagrams 12 | 13 | # Module diagrams 14 | #git+https://github.com/SymbiFlow/symbolator.git#egg=symbolator 15 | 16 | # pycairo 17 | # vext.gi 18 | 19 | restructuredtext-lint 20 | rstdoc 21 | 22 | tabulate 23 | -------------------------------------------------------------------------------- /docs/rules/periphery/p027-tunm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (tunm.1),Min width of tunm,,0.410,µm 3 | (tunm.2),Min spacing of tunm to tunm,,0.500,µm 4 | (tunm.3),Extension of tunm beyond (poly and diff),,0.095, 5 | (tunm.4),Min spacing of tunm to (poly and diff) outside tunm,,0.095,µm 6 | (tunm.5),(poly and diff) may not straddle tunm,,, 7 | (tunm.6a),Tunm outside deep n-well is not allowed,TC,, 8 | (tunm.7),Min tunm area,,0.672,µm² 9 | (tunm.8),tunm must be enclosed by :drc_tag:`areaid.ce`,,, 10 | -------------------------------------------------------------------------------- /docs/rules.rst: -------------------------------------------------------------------------------- 1 | SkyWater SKY130 Process Design Rules 2 | ==================================== 3 | 4 | .. toctree:: 5 | :caption: Process Design Rules 6 | :name: rules 7 | :maxdepth: 2 8 | 9 | rules/background 10 | rules/masks 11 | 12 | rules/assumptions 13 | 14 | rules/layers 15 | 16 | rules/summary 17 | 18 | rules/periphery 19 | rules/wlcsp 20 | rules/hv 21 | 22 | rules/antenna 23 | 24 | rules/rcx 25 | 26 | rules/device-details 27 | 28 | rules/errors 29 | -------------------------------------------------------------------------------- /docs/rules/rcx/resistance-values.tsv: -------------------------------------------------------------------------------- 1 | Layer Resistivity (mohms/sq) 2 | Poly 48200 3 | Local interconnect 12800 4 | Metal1 125 5 | Metal2 125 6 | Metal3 47 7 | Metal4 47 8 | Metal5 29 9 | Deep nwell 2200000 10 | Pwell (in deep nwell) 3050000 11 | Nwell 1700000 12 | N-diffusion 120000 13 | P-diffusion 197000 14 | HV N-diffusion 114000 15 | HV P-diffusion 191000 16 | XHR poly resistor 319800 17 | UHR poly resistor 2000000 18 | LICON contact 15000 19 | MCON contact 152000 20 | VIA 4500 21 | VIA2 3410 22 | VIA3 3410 23 | VIA4 380 24 | -------------------------------------------------------------------------------- /docs/sim.rst: -------------------------------------------------------------------------------- 1 | Simulation 2 | ========== 3 | 4 | .. toctree:: 5 | :caption: Simulation 6 | :name: sim 7 | 8 | With Cadence Spectre 9 | With ngspice 10 | With your design flow? 11 | 12 | .. todo:: 13 | 14 | The SkyWater SKY130 PDK provides simulation two types of simulation models. 15 | :term:`Spectre models` for usage with :term:`Cadence Spectre` and 16 | :term:`Spice models` which are compatible with popular open source spice 17 | simulators like :term:`ngspice`. 18 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8/pfet_01v8-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - Stages 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - EDR 13 | - 14 | - 15 | 16 | * - 17 | - 18 | - 19 | - TT 20 | - FF 21 | - SS 22 | - NOM 23 | - MIN 24 | - MAX 25 | 26 | * - FO = 1 27 | - 143 28 | - ps 29 | - 30 | - 31 | - 32 | - 31.8 33 | - 24.7 34 | - 44.1 35 | 36 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8_hvt/pfet_01v8_hvt-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - Stages 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - EDR 13 | - 14 | - 15 | 16 | * - 17 | - 18 | - 19 | - TT 20 | - FF 21 | - SS 22 | - NOM 23 | - MIN 24 | - MAX 25 | 26 | * - FO = 1 27 | - 143 28 | - ps 29 | - 30 | - 31 | - 32 | - 38 33 | - 29.3 34 | - 52.1 35 | 36 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8_lvt/pfet_01v8_lvt-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - Stages 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - EDR 13 | - 14 | - 15 | 16 | * - 17 | - 18 | - 19 | - TT 20 | - FF 21 | - SS 22 | - NOM 23 | - MIN 24 | - MAX 25 | 26 | * - FO = 1 27 | - 99 28 | - ps 29 | - 30 | - 31 | - 32 | - 43.4 33 | - 35.9 34 | - 54.8 35 | 36 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_01v8_lvt/nfet_01v8_lvt-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - Stages 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - EDR 13 | - 14 | - 15 | 16 | * - 17 | - 18 | - 19 | - TT 20 | - FF 21 | - SS 22 | - NOM 23 | - MIN 24 | - MAX 25 | 26 | * - FO = 1 27 | - 143 28 | - ps 29 | - 30 | - 31 | - 32 | - 28.61 33 | - 21.96 34 | - 39.15 35 | 36 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_g5v0d10v5/pfet_g5v0d10v5-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - Stages 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - EDR 13 | - 14 | - 15 | 16 | * - 17 | - 18 | - 19 | - TT 20 | - FF 21 | - SS 22 | - NOM 23 | - MIN 24 | - MAX 25 | 26 | * - FO = 1 27 | - 79 28 | - ps 29 | - 30 | - 31 | - 32 | - 53.87 33 | - 46.68 34 | - 62.83 35 | 36 | -------------------------------------------------------------------------------- /docs/rules/periphery/p045-rdl_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (rdl.1),Min width of rdl,,10,µm 3 | (rdl.2),Min spacing between two rdl,,10,µm 4 | (rdl.3),"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750,µm 5 | (rdl.4),Min spacing between rdl and outer edge of the seal ring,,15.000,µm 6 | (rdl.5),(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,, 7 | (rdl.6),"Min spacing of rdl to pad, except rdl interacting with bump",,19.660,µm 8 | -------------------------------------------------------------------------------- /docs/rules/background.rst: -------------------------------------------------------------------------------- 1 | Background 2 | ========== 3 | 4 | SKY130 is a mature 180nm-130nm hybrid technology developed by Cypress Semiconductor that has been used for many production parts. SKY130 is now available as a foundry technology through SkyWater Technology Foundry. 5 | 6 | The technology is the 8th generation SONOS technology node (130nm). 7 | 8 | The technology stack consists of; 9 | 10 | - 5 levels of metal (`p` - penta) 11 | - Inductor or Inductor-Capable (`i`) 12 | - Poly resistor (`r`) 13 | - SONOS shrunken cell (`s`) 14 | - Supports 10V regulated supply (`10R`) 15 | 16 | -------------------------------------------------------------------------------- /AUTHORS: -------------------------------------------------------------------------------- 1 | # This is the list of SkyWater PDK's significant contributors. 2 | # 3 | # This does not necessarily list everyone who has contributed code, 4 | # especially since many employees of one corporation may be contributing. 5 | # To see the full list of contributors, see the revision history in 6 | # source control. 7 | 8 | # Companies 9 | Google LLC 10 | SkyWater Technology Foundry 11 | efabless corporation 12 | 13 | # Individuals 14 | tansell@google.com, me@mith.ro (Tim 'mithro' Ansell) 15 | kevin.kelley@skywatertechnology.com, kevin.kelly@skywater.tools (Kevin Kelley) 16 | tim@efabless.com (Tim Edwards) 17 | -------------------------------------------------------------------------------- /docs/rules/periphery/p030-varac_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (varac.1),Min channel length (poly width) of Var_channel,,0.180,µm 3 | (varac.2),Min channel width (tap width) of Var_channel,,1.000,µm 4 | (varac.3),Min spacing between hvtp to Var_channel,,0.180,µm 5 | (varac.4),Min spacing of licon on tap to Var_channel,,0.250,µm 6 | (varac.5),Min enclosure of poly overlapping Var_channel by nwell,,0.150,µm 7 | (varac.6),Min spacing between VaracTap and difftap,,0.270,µm 8 | (varac.7),Nwell overlapping Var_channel must not overlap P+ diff,,, 9 | (varac.8),Min enclosure of Var_channel by hvtp,,0.255,µm 10 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f4-key.rst: -------------------------------------------------------------------------------- 1 | .. rubric:: Footnotes 2 | 3 | .. [#f1] All layers drawn except pmm which is created as cpmm:mask over bond pads or converted into cpbo:mask. 4 | .. [#f2] Entries in this table show the layer (or combination of layers) that act as connecting layers listed in the row/column headings. An X indicates that there is no direct connection between these layers. N/A is entered along the diagonal. Over is entered along layers contacted by overlapping. A layer is always connected to itself. 5 | .. [#f3] (Met5 AND pad AND rdl) should have one of the following sizes for LVS to work with WLCSP option: 60x60, 50x70, 60x80, and 80x80 6 | -------------------------------------------------------------------------------- /docs/license_header.txt: -------------------------------------------------------------------------------- 1 | Copyright 2020 SkyWater PDK Authors 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | https://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | 15 | SPDX-License-Identifier: Apache-2.0 16 | -------------------------------------------------------------------------------- /docs/rules/hv/table-1-key.rst: -------------------------------------------------------------------------------- 1 | .. rubric:: Footnotes 2 | 3 | .. [#f1] Deep N-Wells, N-Wells and P-Wells cannot be used as routing layers. 4 | .. [#f2] No hv rule checks for this device. 5 | .. [#f3] For N+ and P+ diffusion resistors and diodes, rule hv.diff.1 (spacing to unrelated diff) needs to be checked. 6 | .. [#f4] Need to be checked for hv.poly.1, hv.poly.2, hv.poly.3, hv.poly.4. Needs technology approval for use of hv.X.3. 7 | .. [#f5] The hv property is localized to the hvgate and its extensions. 8 | .. [#f6] Interconnect and contacts propagate hv, and are hv devices internal to the CAD flow only. 9 | .. [#f7] "N/A" implies that there are no special hv rules for these layers. 10 | -------------------------------------------------------------------------------- /docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (uhvi.1.-),diff/tap can not straddle UHVI,,N/A,N/A 3 | (uhvi.2.-),poly can not straddle UHVI,,N/A,N/A 4 | (uhvi.3.-),pwbm.dg must be enclosed by UHVI (exempt inside :drc_tag:`areaid.lw`),,N/A,N/A 5 | (uhvi.4.-),dnw.dg can not straddle UHVI,,N/A,N/A 6 | (uhvi.5.-),UHVI must enclose :drc_tag:`areaid.ext`,,N/A,N/A 7 | (uhvi.6.-),UHVI must enclose dnwell,,N/A,N/A 8 | (uhvi.7.-),natfet.dg must be enclosed by UHVI layer by at least,,N/A,N/A 9 | (uhvi.8.-),Minimum width of natfet.dg,,N/A,N/A 10 | (uhvi.9.-),Minimum Space spacing of natfet.dg,,N/A,N/A 11 | (uhvi.10.-),natfet.dg layer is not allowed,,N/A,N/A 12 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f3d-back-end-high-S8Tx.csv: -------------------------------------------------------------------------------- 1 | Layer,CD,licon,,li1,,mcon,,metal1,,via,,metal2,,via2,,metal3, 2 | Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc 3 | li1,0.170,undefined,0.000,0.170,X,X,X,X,X,X,X,X,X,X,X,X,X 4 | mcon,0.170,-,-,-,0.000,0.190,X,X,X,X,X,X,X,X,X,X,X 5 | metal1,0.140,-,-,-,-,-,0.03/ 0.06,0.140,X,X,X,X,X,X,X,X,X 6 | via,0.150,-,-,-,-,-,-,-,0.055 / 0.085,0.170,X,X,X,X,X,X,X 7 | metal2,0.140,-,-,-,-,-,-,-,-,-,0.055,0.140,X,X,X,X,X 8 | via2,0.280,-,-,-,-,-,-,-,-,-,-,-,0.190,1.200,X,X,X 9 | metal3,2.500,-,-,-,-,-,-,-,-,-,-,-,-,-,0.310,2.500,X 10 | ,All enclosures in tables are nominal and do not apply to butting edges or corners.,,,,,,,,,,,,,,,, 11 | -------------------------------------------------------------------------------- /docs/_static/favicon/html_code.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f3c-back-end-high-S8Dx.csv: -------------------------------------------------------------------------------- 1 | Layer,CD,licon,,li1,,mcon,,metal1,,via,,metal2,,via2,,metal3, 2 | Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc 3 | li1,0.170,undefined,0.000,0.170,X,X,X,X,X,X,X,X,X,X,X,X,X 4 | mcon,0.170,-,-,-,0.000,0.190,X,X,X,X,X,X,X,X,X,X,X 5 | metal1,0.140,-,-,-,-,-,0.03/ 0.06,0.140,X,X,X,X,X,X,X,X,X 6 | via,0.150,-,-,-,-,-,-,-,0.055 / 0.085,0.170,X,X,X,X,X,X,X 7 | metal2,0.140,-,-,-,-,-,-,-,-,-,0.055 / 0.085,0.140,X,X,X,X,X 8 | via2,0.280,-,-,-,-,-,-,-,-,-,-,-,0.040,0.280,X,X,X 9 | metal3,0.360,-,-,-,-,-,-,-,-,-,-,-,-,-,0.045 / 0.07,0.360,X 10 | ,All enclosures in tables are nominal and do not apply to butting edges or corners.,,,,,,,,,,,,,,,, 11 | -------------------------------------------------------------------------------- /docs/rules/periphery/p035-li_dotdash_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (li.1.-),Width of LI (except for li.1a),P,0.170,µm 3 | (li.1a.-),Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140,µm 4 | (li.2.-),Max ratio of length to width of LI without licon or mcon,NC,10.000,µm 5 | (li.3.-),Spacing of LI to LI (except for li.3a),P,0.170,µm 6 | (li.3a.-),Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140,µm 7 | (li.5.-),Enclosure of licon by one of two adjacent LI sides,P,0.080,µm 8 | (li.6.-),Min area of LI,P,0.0561,µm² 9 | (li.7.-),"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290,µm 10 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f4-connectivity-of-drawn-and-mask.csv: -------------------------------------------------------------------------------- 1 | ,Deep N Well,N Well,Diff,Tap,Poly,Li1,Capm,Met1,Met2,Met3,Met4,Met5,rdl,,,, 2 | Deep N Well,N/A,,,,,,,,,,,,,,,, 3 | N Well,Over,N/A,,,,,,,,,,,,,,, 4 | Diff,X,X,N/A,,,,,,,,,,,,,, 5 | Tap,X,Over,X,N/A,,,,,,,,,,,,, 6 | Poly,X,X,X,X,N/A,,,,,,,,,,,, 7 | Li1,X,X,Licon1,Licon1,Licon1 AND Npc,N/A,,,,,,,,,,, 8 | Capm,X,X,X,X,X,X,N/A,,,,,,,,,, 9 | Met1,X,X,X,X,X,Mcon,X,N/A,,,,,,,,, 10 | Met2,X,X,X,X,X,X,X,Via,N/A,,,,,,,, 11 | Met3,X,X,X,X,X,X,Via2,X,Via2,N/A,,,,,,, 12 | Met4,X,X,X,X,X,X,X,X,X,Via3,N/A,,,,,, 13 | Met5,X,X,X,X,X,X,X,X,X,X,Via4,N/A,,,,, 14 | rdl,X,X,X,X,X,X,X,X,X,X,X,(pad AND pmm) for s8pir/s8pr2-10r flows [#f1]_ ,N/A,,,, 15 | bump,X,X,X,X,X,X,X,X,X,X,X,X,pi2 AND ubm,,,, 16 | -------------------------------------------------------------------------------- /docs/rules/hv/table-2.csv: -------------------------------------------------------------------------------- 1 | Node Type,Originates VHV?,Propagates VHV?,Requires tagging with vhvi:dg (flags if not tagged when required) 2 | Deep N-Well,No,N/A,N/A 3 | P-Well,No,N/A,N/A 4 | P-Well Resistor,No,No [#f8]_ ,Yes 5 | N-Well,No,N/A,N/A 6 | LV Diffusion,No,Yes,Yes 7 | Diffusion Resistor,No,No [#f8]_ ,Yes 8 | HV Diffusion,No,Yes,Yes 9 | VHV ESD Diffusion,No,No,Yes 10 | VHVSourceDrain,Yes,No [#f9]_ ,Yes 11 | Diodes,No,Yes,Yes 12 | Poly,No,N/A,N/A 13 | Poly Resistor,No,No [#f8]_ ,Yes 14 | VHVPoly,Yes,Yes,Yes 15 | GATE,No,N/A,N/A 16 | de_pFET_gate,No,N/A,N/A 17 | de_nFET_gate,No,N/A,N/A 18 | Licon1,No,Yes,No 19 | Li1,No,Yes,No 20 | Mcon,No,Yes,No 21 | Met1,No,Yes,No 22 | Via,No,Yes,No 23 | Met2,No,Yes,No 24 | via2,No,Yes,No 25 | Met3,No,Yes,No 26 | -------------------------------------------------------------------------------- /docs/rules/periphery/p025-ncm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (ncm.X.2),Ncm overlapping areaid:ce is checked for core rules only,,, 3 | (ncm.X.3),Ncm overlapping core cannot overlap N+diff in periphery,TC,, 4 | (ncm.1),Width of ncm,,0.380,µm 5 | (ncm.2a),Spacing of ncm to ncm,,0.380,µm 6 | (ncm.2b),Manual merge ncm if space is below minimum,,, 7 | (ncm.3),Min enclosure of P+diff by Ncm,P,0.180,µm 8 | (ncm.4),Min enclosure of P+diff within (areaid:ed AndNot areaid:de) by Ncm,P,0.180,µm 9 | (ncm.5),"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230,µm 10 | (ncm.6),"Min space, no overlap, between ncm and nfet",P,0.200,µm 11 | (ncm.7),Min area of ncm,,0.265,µm² 12 | (ncm.8),Min area of ncm Holes,,0.265,µm² 13 | -------------------------------------------------------------------------------- /docs/rules/periphery/p035-ct_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (ct.1),Min and max L and W of mcon,DNF,0.170,µm 3 | (ct.2),Spacing of mcon to mcon,DNF,0.190,µm 4 | (ct.3),Only min. square mcons are allowed except die seal ring where mcons are…,,0.170*L, 5 | (ct.4),Mcon must be enclosed by LI by at least …,P,0.000,µm 6 | (ct.irdrop.1),"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2,µm 7 | (ct.irdrop.2),"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.3,µm 8 | (ct.irdrop.3),"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.7,µm 9 | -------------------------------------------------------------------------------- /docs/rules/periphery/p024-lvtn_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (lvtn.1a),Min width of lvtn,,0.380,µm 3 | (lvtn.2),Min space lvtn to lvtn,,0.380,µm 4 | (lvtn.3a),Min spacing of lvtn to gate. Rule exempted inside UHVI.,P,0.180,µm 5 | (lvtn.3b),Min spacing of lvtn to pfet along the S/D direction,P,0.235,µm 6 | (lvtn.4b),Min enclosure of gate by lvtn. Rule exempted inside UHVI.,P,0.180,µm 7 | (lvtn.9),"Min spacing, no overlap, between lvtn and hvtp",,0.380,µm 8 | (lvtn.10),Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380,µm 9 | (lvtn.12),Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380,µm 10 | (lvtn.13),Min area of lvtn,,0.265,µm² 11 | (lvtn.14),Min area of lvtn Holes,,0.265,µm² 12 | -------------------------------------------------------------------------------- /docs/rules/summary/table-f3a-font-end-low-voltage.csv: -------------------------------------------------------------------------------- 1 | Layer,CD,nwell,,diff,,tap,,n/psdm,,poly,,npc,,licon,Manual,, 2 | Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,merge ?,, 3 | nwell,0.840,1.270,X,X,X,X,X,X,X,X,X,X,X,X,Yes,, 4 | diff,0.150,0.340,0.180,0.270,X,X,X,X,X,X,X,X,X,X,-,, 5 | tap,0.150,0.130,0.180,0.270,-,0.270,X,X,X,X,X,X,X,X,-,, 6 | n/psdm,0.380,-,-,0.130,0.130,0.130,0.130,0.380,X,X,X,X,X,X,Yes,, 7 | poly on diff,0.150,-,-,-,-,0.300,-,-,-,0.210,X,X,X,X,-,, 8 | poly on field,0.150,-,-,0.075,-,0.055,-,-,-,0.210,X,X,X,X,-,, 9 | npc,0.270,-,-,-,-,-,-,-,-,0.090,X,0.270,X,X,Yes,, 10 | licon,0.170,-,-,-,0.04/ 0.06,-,0.000,-,-,0.055,-,0.090,-,0.170,-,, 11 | poly_licon,0.170,-,-,0.190,illegal,0.190,illegal,-,-,-,0.080,-,0.100,0.170,-,, 12 | -------------------------------------------------------------------------------- /scripts/python-skywater-pdk/skywater_pdk/__init__.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # 3 | # Copyright 2020 SkyWater PDK Authors 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # SPDX-License-Identifier: Apache-2.0 18 | -------------------------------------------------------------------------------- /docs/rules/hv/table-1.csv: -------------------------------------------------------------------------------- 1 | Node Type,Originates HV?,Propagates HV?,Becomes HV? (when HV Propagates to this node),Notes 2 | Deep N-Well,No,N/A,N/A,"[#f1]_ [#f7]_" 3 | P-Well,No,N/A,N/A,"[#f1]_ [#f7]_" 4 | P-Well Resistor,No,No,Yes,[#f2]_ 5 | N-Well,No,N/A,N/A,"[#f1]_ [#f7]_" 6 | waffle_chip,No,Yes,Yes, 7 | P+ Diffusion,No,Yes,Yes, 8 | N+ Diffusion Resistor,No,No,Yes,[#f3]_ 9 | P+ Diffusion Resistor,No,No,Yes,[#f3]_ 10 | HV Diffusion,Yes,Yes,Yes, 11 | Diodes,No,Yes,Yes,[#f3]_ 12 | Poly,No,Yes,Yes, 13 | Poly Resistor,No,No,Yes,[#f4]_ 14 | GATE,No,No,No, 15 | HvFET_gate (GATE abutting hv Diff),No,No,Yes,[#f5]_ 16 | Licon1,No,Yes,N/A,[#f6]_ 17 | Li1,No,Yes,N/A,[#f6]_ 18 | Mcon,No,Yes,N/A,[#f6]_ 19 | Met1,No,Yes,N/A,[#f6]_ 20 | Via,No,Yes,N/A,[#f6]_ 21 | Met2,No,Yes,N/A,[#f6]_ 22 | -------------------------------------------------------------------------------- /docs/rules/periphery/p031-photo_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (photo.1),Rules dnwell.3 and nwell.5 are exempted for photoDiode,,, 3 | (photo.2),Min/Max width of photoDiode,,3.000,µm 4 | (photo.3),Min spacing between photoDiode,,5.000,µm 5 | (photo.4),Min spacing between photoDiode and deep nwell,,5.300,µm 6 | (photo.5),photoDiode edges must be coincident with :drc_tag:`areaid.po`,,, 7 | (photo.6),photoDiode must be enclosed by dnwell ring,,, 8 | (photo.7),photoDiode must be enclosed by p+ tap ring,,, 9 | (photo.8),Min/Max width of nwell inside photoDiode,,0.840,µm 10 | (photo.9),Min/Max enclosure of nwell by photoDiode,,1.080,µm 11 | (photo.10),Min/Max width of tap inside photoDiode,,0.410,µm 12 | (photo.11),Min/Max enclosure of tap by nwell inside photoDiode,,0.215,µm 13 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sonosfet/special_sonosfet-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 1 3 | :stub-columns: 1 4 | 5 | 6 | * - Condition 7 | - :math:`V_G` 8 | - :math:`V_D` 9 | - :math:`V_B` 10 | - :math:`V_S` 11 | - :math:`V_{WL}` 12 | - Pulse 13 | 14 | * - Read 15 | - 0 16 | - +1.1 17 | - 0 18 | - 0 19 | - +1.8 20 | - n/a 21 | 22 | * - Program 23 | - +6.7 24 | - -3.8 25 | - -3.8 26 | - -38 27 | - Float 28 | - 2 ms 29 | 30 | * - Erase 31 | - -3.8 32 | - +6.7 33 | - +6.7 34 | - +6.7 35 | - Float 36 | - 6 ms 37 | 38 | * - VT meas 39 | - :math:`I_D = 2.05`\ µA 40 | - +1.1 41 | - 0 42 | - 0 43 | - +1.8 44 | - n/a 45 | 46 | -------------------------------------------------------------------------------- /docs/rules/layers/table-c4a-layer-description.csv: -------------------------------------------------------------------------------- 1 | waffle_chip ,icfb ver 5.0,icfb ver 5.1 2 | drawing ,dg,drw 3 | pin ,pn,pin 4 | boundary ,by,bnd 5 | net ,nt,net 6 | res ,rs,res 7 | label ,ll,lbl 8 | cut ,ct,cut 9 | short ,st,sho 10 | pin ,pn,pin 11 | gate ,ge,gat 12 | probe ,pe,pro 13 | blockage ,be,blo 14 | model ,ml,mod 15 | optionX (X = 1…n),oX (X = 1..n),opt*(X=1..n) 16 | fuse ,fe,fus 17 | mask ,mk,mas* 18 | maskAdd ,md,mas* 19 | maskDrop ,mp,mas* 20 | waffleAdd1 ,w1,waffleAdd1 21 | waffleAdd2 ,w2,waffleAdd2 22 | waffleDrop ,wp,waf 23 | error ,er,err 24 | warning ,wg,wng 25 | dummy ,dy,dmy 26 | -------------------------------------------------------------------------------- /docs/rules/periphery/p036-capm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (capm.1),Min width of capm,,N/A,N/A 3 | (capm.2a),Min spacing of capm to capm,,N/A,N/A 4 | (capm.2b),Minimum spacing of capacitor bottom_plate to bottom plate,,N/A,N/A 5 | (capm.3),Minimum enclosure of capm (top_plate) by met2,,N/A,N/A 6 | (capm.4),Min enclosure of via2 by capm,,N/A,N/A 7 | (capm.5),Min spacing between capm and via2,,N/A,N/A 8 | (capm.6),Maximum Aspect Ratio (Length/Width),,N/A,N/A 9 | (capm.7),Only rectangular capacitors are allowed,,N/A,N/A 10 | (capm.8),"Min space, no overlap, between via and capm",,N/A,N/A 11 | (capm.10),"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A,N/A 12 | (capm.11),Min spacing between capm to (met2 not overlapping capm),,N/A,N/A 13 | (capm.12),Max area of capm (um^2),,N/A,N/A 14 | -------------------------------------------------------------------------------- /docs/rules/periphery/p020-dnwell_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (dnwell.2),Min width of deep nwell,,3.000,µm 3 | (dnwell.3),Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300,µm 4 | (dnwell.3a),Min spacing between deep nwells on same net inside UHVI.,,N/A,N/A 5 | (dnwell.3b),Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A,N/A 6 | (dnwell.3c),Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A,N/A 7 | (dnwell.3d),Min spacing between deep-nwells inside UHVI on different nets,,N/A,N/A 8 | (dnwell.4),Dnwell can not overlap pnp:dg,,, 9 | (dnwell.5),P+_diff can not straddle Dnwell,,, 10 | (dnwell.6),RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,, 11 | (dnwell.7),Dnwell can not straddle areaid:substratecut,,, 12 | -------------------------------------------------------------------------------- /docs/rules/assumptions/09-polyimide.csv: -------------------------------------------------------------------------------- 1 | Layer / Design rule,CD,,space,,Comment 2 | Enclosure of fuses by polyimide,12,,,,PimFuseEnc 3 | Enclosure of bondpad by polyimide (YUY-165),0.5,,,,PimPadEnc 4 | "Enclosure of pad:dg by PBO inside inductor capture pad, with DECA online monitoring",4.5,,,,PBOPadEnc 5 | Enclosure of pad:dg by PBO per standard DECA rules,7.5,,,,PBOPadEncDECA 6 | DECA PBO drawn-to-final process bias per side,0.5,,,,PBOProcBiasPerSide 7 | Polyimide CD tolerance,1,,,,PimCD_tol 8 | Min Pim width over pad openings,87,,,,PimOverPad_CD 9 | Polyimide slope (001-87400),,5.3,,,I_polyimide_slope 10 | Enclosure of polyimide by polymer tolerance,,7.7,,,Po_po_tol 11 | Min/Max enclosure of pad.dg inside M5RDL by pmm,0,,,,pmmM5RDLpadEnc 12 | Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc 13 | Enclosure of laser targets in the die by polyimide,30,,,,PimLaserEnc 14 | -------------------------------------------------------------------------------- /docs/_templates/relbar.html: -------------------------------------------------------------------------------- 1 | {% extends '!relbar.html' %} 2 | 3 | {%- block extralinks -%} 4 | {{ super() }} 5 | 6 |
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    • 11 | 12 | 13 | {%- endblock -%} 14 | -------------------------------------------------------------------------------- /docs/rules/periphery/p047-hvnwell_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvnwell.8),Min space between HV_nwell and any nwell on different nets,,2.000,µm 3 | (hvnwell.9),(Nwell overlapping hvi) must be enclosed by hvi,,, 4 | (hvnwell.10),"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,, 5 | (hvnwell.11),"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"", ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,, 6 | -------------------------------------------------------------------------------- /docs/_static/extra.css: -------------------------------------------------------------------------------- 1 | img.align-center { 2 | display: block; 3 | } 4 | 5 | span.lib-process { 6 | color: green; 7 | } 8 | 9 | span.lib-src { 10 | color: purple; 11 | } 12 | 13 | span.lib-type { 14 | color: orange; 15 | } 16 | 17 | span.lib-name { 18 | color: blue; 19 | } 20 | 21 | span.drc-rule { 22 | font-family: monospace; 23 | white-space: pre; 24 | display: inline-block; 25 | } 26 | 27 | span.drc-tag { 28 | font-family: monospace; 29 | white-space: pre; 30 | display: inline-block; 31 | } 32 | 33 | span.drc-flag { 34 | font-family: monospace; 35 | white-space: pre; 36 | display: inline-block; 37 | } 38 | 39 | span.layer { 40 | font-family: monospace; 41 | white-space: pre; 42 | display: inline-block; 43 | } 44 | 45 | .page-content table thead th { 46 | position: sticky !important; 47 | top: 0; 48 | z-index: 2; 49 | background-color: #fff; 50 | box-shadow: 0 1px 1px -1px rgba(0, 0, 0, 0.4); 51 | } 52 | -------------------------------------------------------------------------------- /docs/rules/periphery/p044-via4_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (via4.1),Min and max L and W of via4,,0.800,µm 3 | (via4.2),Spacing of via4 to via4,,0.800,µm 4 | (via4.3),Only min. square via4s are allowed except die seal ring where via4s are (Via4 CD)*L,,0.8*L, 5 | (via4.4),Via4 must be enclosed by Met4 by at least …,,0.190,µm 6 | (via4.irdrop.1),"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm 7 | (via4.irdrop.2),"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2,µm 8 | (via4.irdrop.3),"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.5,µm 9 | (via4.irdrop.4),"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8,µm 10 | -------------------------------------------------------------------------------- /docs/rules/periphery/p049-hvntm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvntm.X.1),Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC,,, 3 | (hvntm.1),Width of hvntm,P,0.700,µm 4 | (hvntm.2),Spacing of hvntm to hvntm,P,0.700,µm 5 | (hvntm.3),Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntm,P,0.185,µm 6 | (hvntm.4),"Space, no overlap, between n+_diff outside Hvi and hvntm",P,0.185,µm 7 | (hvntm.5),"Space, no overlap, between p+_diff and hvntm",P DE,0.185,µm 8 | (hvntm.6a),"Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)",P,0.185,µm 9 | (hvntm.6b),"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000,µm 10 | (hvntm.7),hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000, 11 | (hvntm.9),Hvntm must not overlap :drc_tag:`areaid.ce`,,, 12 | (hvntm.10),Hvntm must overlap hvi,,, 13 | -------------------------------------------------------------------------------- /environment.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2020 SkyWater PDK Authors 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # https://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | # 15 | # SPDX-License-Identifier: Apache-2.0 16 | name: skywater-pdk-scripts 17 | channels: 18 | - litex-hub 19 | - defaults 20 | dependencies: 21 | - python=3.8 22 | - pip 23 | - yosys 24 | - netlistsvg 25 | - iverilog 26 | # Packages installed from PyPI 27 | - pip: 28 | - -r requirements.txt 29 | -------------------------------------------------------------------------------- /docs/environment.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2020 SkyWater PDK Authors 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # https://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | # 15 | # SPDX-License-Identifier: Apache-2.0 16 | name: skywater-pdk-docs 17 | channels: 18 | - symbiflow 19 | - defaults 20 | dependencies: 21 | - python=3.8 22 | - pip 23 | - netlistsvg 24 | # Packages installed from PyPI 25 | - pip: 26 | - -r requirements.txt 27 | - ../scripts/python-skywater-pdk 28 | -------------------------------------------------------------------------------- /docs/rules/assumptions/08-hv.csv: -------------------------------------------------------------------------------- 1 | Layer / Design rule,CD,,space,,Comment 2 | Min HVNwell to any nwell space,,,2,,HVNwell_Nwell_SP 3 | Min HVDiff width,0.29,,,,HVDiff_CD 4 | Min HVDiff space,,,0.3,,HVDiff_SP 5 | Min HV Pmos gate width,0.5,,,,HVP_gate_CD 6 | Min space between HV poly,,,0.28,,HVPoly_SP 7 | Min HV Nmos gate width,0.37,,,,HVPoly_CD 8 | HV P+ Diff enclosure by Nwell,0.33,,,,HVPdiff_nwell_enc 9 | HV N+ diff space to Nwell,,,0.43,,HVNdiff_nwell_SP 10 | HV N+ tap enclosure by Nwell,0.33,,,,HVNtap_nwell_enc 11 | HV P+tap space to Nwell,,,0.43,,HVPtap_nwell_SP 12 | Photoresist tilted implant penetration,0.02,,,,HVPrPenetration 13 | Photoresist tilted implant blocking distance,0.013,,,,HVPrBlocking 14 | Min size of HVTip,0.1,,,,HVTipMinSize 15 | Extra CD tol for HVNTM to match Ram7 process,0.015,,,,HVNTMExtraCdTol 16 | Min HVDiff resistor width,0.29,,,,HVDiff_Res_CD 17 | High voltage n+-n+ or p+-p+,,,0.3,,HVDPTS15 18 | HV MOSFET channel length,0.5,,,,HVPCD 19 | -------------------------------------------------------------------------------- /docs/rules/periphery/p052-extd_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (extd.1),Difftap cannot straddle areaid:en,,, 3 | (extd.2),DiffTap must have 2 or 3 coincident edges with areaid:en if enclosed by areaid:en,,, 4 | (extd.3),Poly must not be entirely overlapping difftap in areaid:en,,, 5 | (extd.4),"Only cell name ""s8rf_n20vhv1*"" is a valid cell name for n20vhv1 device (Check in LVS as invalid device)",,N/A,N/A 6 | (extd.5),"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device (Check in LVS as invalid device)",,N/A,N/A 7 | (extd.6),"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device (Check in LVS as invalid device)",,N/A,N/A 8 | (extd.7),"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device (Check in LVS as invalid device)",,N/A,N/A 9 | (extd.8),"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device (Check in LVS as invalid device)",,N/A,N/A 10 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2020 SkyWater PDK Authors 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # https://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | # 15 | # SPDX-License-Identifier: Apache-2.0 16 | 17 | language: minimal 18 | 19 | git: 20 | submodules: false 21 | depth: false 22 | 23 | install: 24 | - git describe 25 | - make env 26 | 27 | script: 28 | - source .github/travis/common.sh 29 | - rm -f README.rst && make README.rst 30 | - .github/travis/git-check.sh 31 | -------------------------------------------------------------------------------- /docs/rules/assumptions/05-laser-fuse.csv: -------------------------------------------------------------------------------- 1 | ,,,Value (um),,Variable name 2 | Min. spac. of laser spot to diffused junction to ensure jct integrity,,,0.6,,XLASJUN 3 | Max. width of a metal fuse line that can be removed reliably,,,0.8,,FSW 4 | Min. L of met. fuse at which damage doesn't extend beyond ends,,,6.605,,FSLE 5 | Max. extension of met2 beyond fuse boundary,,,0.005,,FEXT 6 | Min. distance between laser spot and active junction,,,0.545,,LASJCT 7 | Standard contact bottom CD,,,0.09,, 8 | Positioning tolerance of laser spot (3 s),,,0.3,,LASMA 9 | Nominal effective laser spot diameter,,,3.5,,LASSPT 10 | Max. increase in spot diameter at max. distance from focus (3 s),,,0.9,,LASCDTOL 11 | Fuse melting radius,,,3.6,,MELTRAD 12 | Melting related crack size in ILD,,,0.36,,FUSECRACK 13 | Min space between fuse and any feature not connected to it,,,0.2,,MinFuseSpace 14 | Space between fuse and any unrelated layer,,,0.5,,SP_fuse_to_unrelated 15 | DC offset in some fuse rules,,,0.87,,LASDC1 16 | -------------------------------------------------------------------------------- /docs/rules/periphery/p056-pwres_dotdash_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (pwres.1.-),Pwell resistor has to be enclosed by the res layer,NC,, 3 | (pwres.2.-),Min/Max width of pwell resistor,,2.650,µm 4 | (pwres.3.-),Min length of pwell resistor,,26.500,µm 5 | (pwres.4.-),Max length of pwell resistor,,265.00,µm 6 | (pwres.5.-),Min/Max spacing of tap inside the pwell resistor to nwell,,0.220,µm 7 | (pwres.6.-),Min/Max width of tap inside the pwell resistor,,0.530,µm 8 | (pwres.7a.-),Every pwres_terminal must enclose 12 licon1,,, 9 | (pwres.7b.-),Every pwres_terminal must enclose 12 mcons if routed through metal1,,, 10 | (pwres.8.-),Diff or poly is not allowed in the pwell resistor.,,, 11 | (pwres.9.-),Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,, 12 | (pwres.10.-),The res layer must abut pwres_terminal on opposite and parallel edges,,, 13 | (pwres.11.-),The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,, 14 | -------------------------------------------------------------------------------- /scripts/python-skywater-pdk/docs/skywater_pdk.rst: -------------------------------------------------------------------------------- 1 | skywater\_pdk package 2 | ===================== 3 | 4 | Submodules 5 | ---------- 6 | 7 | skywater\_pdk.base module 8 | ------------------------- 9 | 10 | .. automodule:: skywater_pdk.base 11 | :members: 12 | :undoc-members: 13 | :show-inheritance: 14 | 15 | skywater\_pdk.corners module 16 | ---------------------------- 17 | 18 | .. automodule:: skywater_pdk.corners 19 | :members: 20 | :undoc-members: 21 | :show-inheritance: 22 | 23 | skywater\_pdk.sizes module 24 | --------------------------- 25 | 26 | .. automodule:: skywater_pdk.sizes 27 | :members: 28 | :undoc-members: 29 | :show-inheritance: 30 | 31 | skywater\_pdk.utils module 32 | -------------------------- 33 | 34 | .. automodule:: skywater_pdk.utils 35 | :members: 36 | :undoc-members: 37 | :show-inheritance: 38 | 39 | 40 | Module contents 41 | --------------- 42 | 43 | .. automodule:: skywater_pdk 44 | :members: 45 | :undoc-members: 46 | :show-inheritance: 47 | -------------------------------------------------------------------------------- /docs/rules/device-details/cap_mim/cap_mim-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 1 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - NOM 8 | - LSL 9 | - USL 10 | - Units 11 | - Description 12 | 13 | * - CMIMA 14 | - 2 15 | - 1.8 16 | - 2.2 17 | - fF/µm\ :sup:`2` 18 | - MiM cap area capacitance 19 | 20 | * - CMIMP 21 | - 0.19 22 | - 0.11 23 | - 0.27 24 | - fF/µm 25 | - MiM cap periphery capacitance 26 | 27 | * - RSCAPM 28 | - 5.8 29 | - 4.8 30 | - 6.8 31 | - Ω/□ 32 | - MiM top plate sheet resistance 33 | 34 | * - CMIM2A 35 | - 2 36 | - 1.8 37 | - 2.2 38 | - fF/µm\ :sup:`2` 39 | - MiM2 cap area capacitance 40 | 41 | * - CMIM2P 42 | - 0.19 43 | - 0.11 44 | - 0.27 45 | - fF/µm 46 | - MiM2 cap periphery capacitance 47 | 48 | * - RSCAPM 49 | - 5.8 50 | - 4.8 51 | - 6.8 52 | - Ω/sq 53 | - MiM2 top plate sheet resistance 54 | 55 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_g5v0d10v5/index.rst: -------------------------------------------------------------------------------- 1 | 5.0V/10.5V NMOS FET 2 | ------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__nfet_g5v0d10v5` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to 11.0V 13 | - :math:`V_{GS} = 0` to 5.5V 14 | - :math:`V_{BS} = 0` to -5.5V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs 20 | 21 | 22 | .. include:: nfet_g5v0d10v5-table0.rst 23 | 24 | 25 | 26 | The symbols of the :model:`sky130_fd_pr__nfet_g5v0d10v5` (5.0/10.5 V NMOS FET) is shown below: 27 | 28 | |symbol-nfet_g5v0d10v5| 29 | 30 | The cross-section of the 5.0/10.5 V NMOS FET is shown below. 31 | 32 | |cross-section-nfet_g5v0d10v5| 33 | 34 | .. |symbol-nfet_g5v0d10v5| image:: symbol-nfet_g5v0d10v5.svg 35 | .. |cross-section-nfet_g5v0d10v5| image:: cross-section-nfet_g5v0d10v5.svg 36 | 37 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sram/special_sram-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNPAS 31 | - 0.14/0.15 32 | - V 33 | - 0.68 34 | - 0.52 35 | - 0.846 36 | - 0.846 37 | - 0.515 38 | - 0.669 39 | - 0.498 40 | - 0.839 41 | 42 | * - IDSNPAS 43 | - 0.14/0.15 44 | - µA 45 | - 0.0702 46 | - 0.0948 47 | - 0.0471 48 | - 0.0943 49 | - 0.0473 50 | - 68.2 51 | - 45.5 52 | - 90.8 53 | 54 | * - ILKNPAS 55 | - 0.14/0.15 56 | - LOG A 57 | - Max = -8.0 58 | - -9.73 59 | - -12.33 60 | - -9.1 61 | - 62 | - 63 | - 64 | - 65 | 66 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sram/special_sram-table1.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNLTC 31 | - 0.21/0.15 32 | - V 33 | - 0.715 34 | - 0.574 35 | - 0.856 36 | - 0.856 37 | - 0.575 38 | - 0.709 39 | - 0.567 40 | - 0.851 41 | 42 | * - IDSNLTC 43 | - 0.21/0.15 44 | - µA 45 | - 0.091 46 | - 0.1197 47 | - 0.0616 48 | - 0.1192 49 | - 0.0618 50 | - 87.9 51 | - 60.2 52 | - 115.5 53 | 54 | * - ILKNLTC 55 | - 0.21/0.15 56 | - LOG A 57 | - Max = -7.8 58 | - -9.45 59 | - -11.65 60 | - -8.90 61 | - 62 | - 63 | - 64 | - 65 | 66 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_20v0_zvt/index.rst: -------------------------------------------------------------------------------- 1 | 20V zero-VT NMOS FET 2 | -------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__nfet_20v0_zvt` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to +22V 13 | - :math:`V_{GS} = 0` to 5.5V 14 | - :math:`V_{BS} = 0` to -2.0V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The 20V NMOS zero-VT FET has p-well and all Vt implants blocked to achieve a zero VT. 20 | 21 | Major model output parameters are shown below and compared against the EDR (e-test) specs 22 | 23 | 24 | .. include:: nfet_20v0_zvt-table0.rst 25 | 26 | 27 | 28 | The symbol of the :model:`sky130_fd_pr__nfet_20v0_zvt` (20V NMOS zero-VT FET) is still under development. 29 | 30 | The cross-section of the 20V NMOS zero-VT FET is shown below. 31 | 32 | |cross-section-nfet_20v0_zvt| 33 | 34 | .. |cross-section-nfet_20v0_zvt| image:: cross-section-nfet_20v0_zvt.svg 35 | 36 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sram/special_sram-table2.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXPLTC 31 | - 0.14/0.15 32 | - V 33 | - -0.918 34 | - -0.761 35 | - -1.085 36 | - -0.747 37 | - -1.089 38 | - -0.905 39 | - -1.080 40 | - -0.732 41 | 42 | * - IDSPLTC 43 | - 0.14/0.15 44 | - µA 45 | - 0.0208 46 | - 0.0306 47 | - 0.0113 48 | - 0.0304 49 | - 0.0113 50 | - 19.9 51 | - 10.7 52 | - 29.1 53 | 54 | * - ILKPLTC 55 | - 0.14/0.15 56 | - LOG A 57 | - Max = -7.3 58 | - -9.860 59 | - -13.31 60 | - -8.880 61 | - 62 | - 63 | - 64 | - 65 | 66 | -------------------------------------------------------------------------------- /docs/rules/periphery/p043-nsm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (nsm.1),Min. width of nsm,,3.000,µm 3 | (nsm.2),Min. spacing of nsm to nsm,,4.000,µm 4 | (nsm.3),"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl`",AL,1.000,µm 5 | (nsm.3a),"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*"" (b) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm 6 | (nsm.3b),"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm 7 | -------------------------------------------------------------------------------- /docs/rules/rcx/table-rcx-all-print.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import csv 4 | import os 5 | import pprint 6 | import sys 7 | 8 | __dir__ = os.path.dirname(os.path.abspath(__file__)) 9 | 10 | TSV_FILE = os.path.join(__dir__, "rcx-all.tsv") 11 | 12 | 13 | def main(arg): 14 | rows = [] 15 | with open(TSV_FILE, newline='') as csvfile: 16 | reader = csv.reader(csvfile, delimiter='\t') 17 | for r in reader: 18 | rows.append(list(c.strip() for c in r)) 19 | 20 | rowlen = max(len(r) for r in rows) 21 | for r in rows: 22 | while len(r) < rowlen: 23 | r.append('') 24 | 25 | clen = [0] * rowlen 26 | for i, _ in enumerate(clen): 27 | clen[i] = max(len(r[i]) for r in rows) 28 | 29 | for r in rows: 30 | for i, m in enumerate(clen): 31 | r[i] = r[i].ljust(m) 32 | 33 | rows.insert(1, ['-'*m for m in clen]) 34 | 35 | for r in rows: 36 | print("|", " | ".join(r), "|") 37 | 38 | return 0 39 | 40 | 41 | if __name__ == "__main__": 42 | sys.exit(main(sys.argv)) 43 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_01v8/index.rst: -------------------------------------------------------------------------------- 1 | 1.8V NMOS FET 2 | ------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__nfet_01v8` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to 1.95V 13 | - :math:`V_{GS} = 0` to 1.95V 14 | - :math:`V_{BS} = +0.3` to -1.95V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs. 20 | 21 | 22 | .. include:: nfet_01v8-table0.rst 23 | 24 | 25 | 26 | The symbol of the :model:`sky130_fd_pr__nfet_01v8` (1.8V NMOS FET) is shown below: 27 | 28 | |symbol-nfet_01v8| 29 | 30 | The cross-section of the NMOS FET is shown below: 31 | 32 | |cross-section-nfet_01v8| 33 | 34 | The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well 35 | 36 | .. |symbol-nfet_01v8| image:: symbol-nfet_01v8.svg 37 | .. |cross-section-nfet_01v8| image:: cross-section-nfet_01v8.svg 38 | 39 | -------------------------------------------------------------------------------- /docs/rules/layers/table-f2a-lvs-print.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import csv 4 | import os 5 | import pprint 6 | import sys 7 | 8 | __dir__ = os.path.dirname(os.path.abspath(__file__)) 9 | 10 | TSV_FILE = os.path.join(__dir__, "table-f2a-lvs.tsv") 11 | 12 | 13 | def main(arg): 14 | rows = [] 15 | with open(TSV_FILE, newline='') as csvfile: 16 | reader = csv.reader(csvfile, delimiter='\t') 17 | for r in reader: 18 | rows.append(list(c.strip() for c in r)) 19 | 20 | rowlen = max(len(r) for r in rows) 21 | for r in rows: 22 | while len(r) < rowlen: 23 | r.append('') 24 | 25 | clen = [0] * rowlen 26 | for i, _ in enumerate(clen): 27 | clen[i] = max(len(r[i]) for r in rows) 28 | 29 | for r in rows: 30 | for i, m in enumerate(clen): 31 | r[i] = r[i].ljust(m) 32 | 33 | rows.insert(1, ['-'*m for m in clen]) 34 | 35 | for r in rows: 36 | print("|", " | ".join(r), "|") 37 | 38 | return 0 39 | 40 | 41 | if __name__ == "__main__": 42 | sys.exit(main(sys.argv)) 43 | -------------------------------------------------------------------------------- /docs/rules/layers/table-f2b-mask-print.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import csv 4 | import os 5 | import pprint 6 | import sys 7 | 8 | __dir__ = os.path.dirname(os.path.abspath(__file__)) 9 | 10 | TSV_FILE = os.path.join(__dir__, "table-f2b-mask.tsv") 11 | 12 | 13 | def main(arg): 14 | rows = [] 15 | with open(TSV_FILE, newline='') as csvfile: 16 | reader = csv.reader(csvfile, delimiter='\t') 17 | for r in reader: 18 | rows.append(list(c.strip() for c in r)) 19 | 20 | rowlen = max(len(r) for r in rows) 21 | for r in rows: 22 | while len(r) < rowlen: 23 | r.append('') 24 | 25 | clen = [0] * rowlen 26 | for i, _ in enumerate(clen): 27 | clen[i] = max(len(r[i]) for r in rows) 28 | 29 | for r in rows: 30 | for i, m in enumerate(clen): 31 | r[i] = r[i].ljust(m) 32 | 33 | rows.insert(1, ['-'*m for m in clen]) 34 | 35 | for r in rows: 36 | print("|", " | ".join(r), "|") 37 | 38 | return 0 39 | 40 | 41 | if __name__ == "__main__": 42 | sys.exit(main(sys.argv)) 43 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8/index.rst: -------------------------------------------------------------------------------- 1 | 1.8V PMOS FET 2 | ------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__pfet_01v8` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to -1.95V 13 | - :math:`V_{GS} = 0` to -1.95V 14 | - :math:`V_{BS} = -0.1` to +1.95V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs. 20 | 21 | 22 | .. include:: pfet_01v8-table0.rst 23 | 24 | 25 | 26 | Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8` device combinations: 27 | 28 | 29 | .. include:: pfet_01v8-table1.rst 30 | 31 | 32 | 33 | The symbol of the :model:`sky130_fd_pr__pfet_01v8` (1.8V PMOS FET) is shown below: 34 | 35 | |symbol-pfet_01v8| 36 | 37 | The cross-section of the PMOS FET is shown below: 38 | 39 | |cross-section-pfet_01v8| 40 | 41 | .. |symbol-pfet_01v8| image:: symbol-pfet_01v8.svg 42 | .. |cross-section-pfet_01v8| image:: cross-section-pfet_01v8.svg 43 | 44 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_g5v0d16v0/index.rst: -------------------------------------------------------------------------------- 1 | 10V/16V PMOS FET 2 | ---------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__pfet_g5v0d16v0` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to -16V (\ :math:`V_{GS} = 0`\ ) 13 | - :math:`V_{DS} = 0` to -10V (\ :math:`V_{GS} < 0`\ ) 14 | - :math:`V_{GS} = 0` to -5.5V 15 | - :math:`V_{BS} = 0` to +2.0V 16 | 17 | Details 18 | ~~~~~~~ 19 | 20 | Major model output parameters are shown below and compared against the EDR (e-test) specs 21 | 22 | 23 | .. include:: pfet_g5v0d16v0-table0.rst 24 | 25 | 26 | 27 | The symbol of the :model:`sky130_fd_pr__pfet_g5v0d16v0` (10V/16V PMOS FET) is shown below: 28 | 29 | |symbol-pfet_g5v0d16v0| 30 | 31 | The cross-section of the 10V/16V PMOS FET is shown below. 32 | 33 | |cross-section-pfet_g5v0d16v0| 34 | 35 | .. |symbol-pfet_g5v0d16v0| image:: symbol-pfet_g5v0d16v0.svg 36 | .. |cross-section-pfet_g5v0d16v0| image:: cross-section-pfet_g5v0d16v0.svg 37 | 38 | -------------------------------------------------------------------------------- /docs/rules/periphery/p051-depmos_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (depmos.1),Min width of de_pFet_gate,,1.050,µm 3 | (depmos.2),Min width of de_pFet_source not overlapping poly,,0.280,µm 4 | (depmos.3),Min width of de_pFet_source overlapping poly,,0.920,µm 5 | (depmos.4),Min width of the de_pFet_drain,,0.170,µm 6 | (depmos.5),Min/Max extension of de_pFet_source beyond nwell,,0.260, 7 | (depmos.6),Min/Max spacing between de_pFet_drain and de_pFet_source,,1.190,µm 8 | (depmos.7),Min channel width for de_pFet_gate,,5.000,µm 9 | (depmos.8),90 degree angles are not permitted for nwell hole overlapping de_pFET_drain,,, 10 | (depmos.9a),"All bevels on nwell hole are 45 degree, 0.43 µm from corners",NC,,µm 11 | (depmos.9b),"All bevels on de_pFet_drain are 45 degree, 0.05 µm from corners",NC,,µm 12 | (depmos.10),Min enclosure of de_pFet_drain by nwell hole,,0.860,µm 13 | (depmos.11),Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660,µm 14 | (depmos.12),de_pFet_source must be enclosed by psdm by,,0.130,µm 15 | (depmos.13),pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A,N/A 16 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_g11v0d16v0/index.rst: -------------------------------------------------------------------------------- 1 | 11V/16V NMOS FET 2 | ---------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__nfet_g5v0d16v0` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to +16V (\ :math:`V_{GS} = 0`\ ) 13 | - :math:`V_{DS} = 0` to +11V (\ :math:`V_{GS} > 0`\ ) 14 | - :math:`V_{GS} = 0` to 5.5V 15 | - :math:`V_{BS} = 0` to -2.0V 16 | 17 | Details 18 | ~~~~~~~ 19 | 20 | Major model output parameters are shown below and compared against the EDR (e-test) specs 21 | 22 | 23 | .. include:: nfet_g11v0d16v0-table0.rst 24 | 25 | 26 | 27 | The symbol of the :model:`sky130_fd_pr__nfet_g5v0d16v0` (11V/16V NMOS FET) is shown below: 28 | 29 | |symbol-nfet_g11v0d16v0| 30 | 31 | The cross-section of the 11V/16VV NMOS FET is shown below. 32 | 33 | |cross-section-nfet_g11v0d16v0| 34 | 35 | .. |symbol-nfet_g11v0d16v0| image:: symbol-nfet_g11v0d16v0.svg 36 | .. |cross-section-nfet_g11v0d16v0| image:: cross-section-nfet_g11v0d16v0.svg 37 | 38 | -------------------------------------------------------------------------------- /docs/rules/periphery/p032-n_psd_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (n/ psd.1),Width of nsdm(psdm),P,0.380,µm 3 | (n/ psd.2),Spacing of nsdm(psdm) to nsdm(psdm),P,0.380,µm 4 | (n/ psd.3),Manual merge if less than minimum,,, 5 | (n/ psd.5a),"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125,µm 6 | (n/ psd.5b),"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125,µm 7 | (n/ psd.6),Enclosure of diff/tap butting edge by nsdm (psdm),,0.000,µm 8 | (n/ psd.7),Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130,µm 9 | (n/ psd.8),Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,, 10 | (n/ psd.9),"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for 11 | - diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows 12 | - diff rings around the die at min total L>1000 um and W=0.3 um 13 | - gated_npn 14 | - :drc_tag:`areaid.zer`.",DE,, 15 | (n/ psd.10a),Min area of Nsdm,,0.265,µm² 16 | (n/ psd.10b),Min area of Psdm,,0.255,µm² 17 | (n/ psd.11),Min area of n/psdmHoles,,0.265,µm² 18 | -------------------------------------------------------------------------------- /docs/rules/periphery/p050-denmos_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (denmos.1),Min width of de_nFet_gate,,1.055,µm 3 | (denmos.2),Min width of de_nFet_source not overlapping poly,,0.280,µm 4 | (denmos.3),Min width of de_nFet_source overlapping poly,,0.925,µm 5 | (denmos.4),Min width of the de_nFet_drain,,0.170,µm 6 | (denmos.5),Min/Max extension of de_nFet_source over nwell,,0.225, 7 | (denmos.6),Min/Max spacing between de_nFet_drain and de_nFet_source,,1.585,µm 8 | (denmos.7),Min channel width for de_nFet_gate,,5.000,µm 9 | (denmos.8),90 degree angles are not permitted for nwell overlapping de_nFET_drain,,, 10 | (denmos.9a),"All bevels on nwell are 45 degree, 0.43 µm from corners",NC,,µm 11 | (denmos.9b),"All bevels on de_nFet_drain are 45 degree, 0.05 µm from corners",NC,,µm 12 | (denmos.10),Min enclosure of de_nFet_drain by nwell,,0.660,µm 13 | (denmos.11),Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860,µm 14 | (denmos.12),Min spacing between nwells overlapping de_nFET_drain,,2.400,µm 15 | (denmos.13),de_nFet_source must be enclosed by nsdm by,,0.130,µm 16 | (denmos.14),nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A,N/A 17 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_20v0_nvt/index.rst: -------------------------------------------------------------------------------- 1 | 20V native NMOS FET 2 | ------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__nfet_20v0_nvt` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to +22V 13 | - :math:`V_{GS} = 0` to 5.5V 14 | - :math:`V_{BS} = 0` to -2.0V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The 20V native NMOS FET is similar to the 20V isolated NMOS FET, but has all Vt implants blocked to achieve a very low VT. 20 | 21 | Major model output parameters are shown below and compared against the EDR (e-test) specs 22 | 23 | 24 | .. include:: nfet_20v0_nvt-table0.rst 25 | 26 | 27 | 28 | The symbol of the :model:`sky130_fd_pr__nfet_20v0_nvt` (20V native NMOS FET) shown below. 29 | 30 | |symbol-nfet_20v0_nvt| 31 | 32 | The cross-section of the 20V native NMOS FET is shown below. 33 | 34 | |cross-section-nfet_20v0_nvt| 35 | 36 | .. |symbol-nfet_20v0_nvt| image:: symbol-nfet_20v0_nvt.svg 37 | .. |cross-section-nfet_20v0_nvt| image:: cross-section-nfet_20v0_nvt.svg 38 | 39 | -------------------------------------------------------------------------------- /docs/rules/device-details/diodes/diodes-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - NOM 8 | - LSL 9 | - USL 10 | - Units 11 | - Description 12 | 13 | * - BVN 14 | - 11.7 15 | - 10.7 16 | - 14.0 17 | - V 18 | - N+ breakdown voltage 19 | 20 | * - BVNH 21 | - 12.7 22 | - 11.7 23 | - 14.0 24 | - V 25 | - HV N+ breakdown voltage 26 | 27 | * - BVNE 28 | - 11 29 | - 9.5 30 | - 14.5 31 | - V 32 | - N+ peripheral breakdown voltage 33 | 34 | * - BVNEH 35 | - 12.2 36 | - 11.5 37 | - 14.5 38 | - V 39 | - HV N+ peripheral breakdown voltage 40 | 41 | * - BVP 42 | - 12.2 43 | - 10.2 44 | - 14.5 45 | - V 46 | - P+ breakdown voltage 47 | 48 | * - BVPH 49 | - 12 50 | - 11.2 51 | - 14.5 52 | - V 53 | - HV P+ breakdown voltage 54 | 55 | * - BVPE 56 | - 10.5 57 | - 9 58 | - 14.5 59 | - V 60 | - P+ peripheral breakdown voltage 61 | 62 | * - BVPEH 63 | - 11.6 64 | - 11.2 65 | - 14.5 66 | - V 67 | - HV P+ peripheral breakdown voltage 68 | 69 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_20v0/index.rst: -------------------------------------------------------------------------------- 1 | 20V NMOS FET 2 | ------------ 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__nfet_20v0` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to +22V 13 | - :math:`V_{GS} = 0` to 5.5V 14 | - :math:`V_{BS} = 0` to -2.0V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences: 20 | 21 | - Longer drift region 22 | - Longer poly gate 23 | - Larger W/L 24 | - Devices placed in pairs (drain in center, sources on outside) 25 | 26 | Major model output parameters are shown below and compared against the EDR (e-test) specs 27 | 28 | 29 | .. include:: nfet_20v0-table0.rst 30 | 31 | 32 | 33 | The symbol of the :model:`sky130_fd_pr__nfet_20v0` (20V NMOS FET) is shown below. 34 | 35 | |symbol-nfet_20v0| 36 | 37 | The cross-section of the 20V NMOS FET is shown below. 38 | 39 | |cross-section-nfet_20v0| 40 | 41 | .. |symbol-nfet_20v0| image:: symbol-nfet_20v0.svg 42 | .. |cross-section-nfet_20v0| image:: cross-section-nfet_20v0.svg 43 | 44 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_20v0/index.rst: -------------------------------------------------------------------------------- 1 | 20V PMOS FET 2 | ------------ 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__pfet_20v0` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to -22V 13 | - :math:`V_{GS} = 0` to -5.5V 14 | - :math:`V_{BS} = 0` to +2.0V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences: 20 | 21 | - Longer drift region 22 | - Longer poly gate 23 | - Larger W/L 24 | - Devices placed in pairs (drain in middle, sources on outside) 25 | 26 | Major model output parameters are shown below and compared against the EDR (e-test) specs 27 | 28 | 29 | .. include:: pfet_20v0-table0.rst 30 | 31 | 32 | 33 | The symbol of the :model:`sky130_fd_pr__pfet_20v0` (20V PMOS FET) is shown below. 34 | 35 | |symbol-pfet_20v0| 36 | 37 | The cross-section of the 20V PMOS FET is shown below. 38 | 39 | |cross-section-pfet_20v0| 40 | 41 | .. |symbol-pfet_20v0| image:: symbol-pfet_20v0.svg 42 | .. |cross-section-pfet_20v0| image:: cross-section-pfet_20v0.svg 43 | 44 | -------------------------------------------------------------------------------- /docs/rules/summary.rst: -------------------------------------------------------------------------------- 1 | Summary of Key Periphery Rules 2 | ============================== 3 | 4 | .. csv-table:: Table F3a: Front end layers (Low Voltage Devices) 5 | :file: summary/table-f3a-font-end-low-voltage.csv 6 | :header-rows: 1 7 | :stub-columns: 1 8 | 9 | .. csv-table:: Table F3b: Front end layers (High Voltage Devices) 10 | :file: summary/table-f3b-font-end-high-voltage.csv 11 | :header-rows: 1 12 | :stub-columns: 1 13 | 14 | Manual merge means that features below min. space should be manually merged by drawing. 15 | 16 | .. csv-table:: Table F3c: Back end layers for S8D* flow 17 | :file: summary/table-f3c-back-end-high-S8Dx.csv 18 | :header-rows: 1 19 | :stub-columns: 1 20 | 21 | .. csv-table:: Table F3d: Back end layers for S8T* flow 22 | :file: summary/table-f3d-back-end-high-S8Tx.csv 23 | :header-rows: 1 24 | :stub-columns: 1 25 | 26 | .. csv-table:: Table F4: Connectivity of Drawn and Mask Layers [#f1]_ 27 | :file: summary/table-f4-connectivity-of-drawn-and-mask.csv 28 | :header-rows: 1 29 | :stub-columns: 1 30 | 31 | .. include:: summary/table-f4-key.rst 32 | 33 | .. csv-table:: Table F5: Device Connectivity Table 34 | :file: summary/table-f5-device-connectivity.csv 35 | :header-rows: 1 36 | :stub-columns: 1 37 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_20v0_iso/index.rst: -------------------------------------------------------------------------------- 1 | 20V isolated NMOS FET 2 | --------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` 8 | - Model Name: :model:`sky130_fd_pr__nfet_20v0_iso` 9 | 10 | Operating Voltages where SPICE models are valid, subject to SOA limitations: 11 | 12 | - :math:`V_{DS} = 0` to +22V 13 | - :math:`V_{GS} = 0` to 5.5V 14 | - :math:`V_{BS} = 0` to -2.0V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground). 20 | 21 | Major model output parameters are shown below and compared against the EDR (e-test) specs 22 | 23 | 24 | .. include:: nfet_20v0_iso-table0.rst 25 | 26 | 27 | 28 | The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below. 29 | 30 | |symbol-nfet_20v0_iso| 31 | 32 | The cross-section of the 20V isolated NMOS FET is shown below. 33 | 34 | |cross-section-nfet_20v0_iso| 35 | 36 | .. |symbol-nfet_20v0_iso| image:: symbol-nfet_20v0_iso.svg 37 | .. |cross-section-nfet_20v0_iso| image:: cross-section-nfet_20v0_iso.svg 38 | 39 | -------------------------------------------------------------------------------- /docs/rules/periphery/p021-nwell_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (nwell.1),Width of nwell,,0.840,µm 3 | (nwell.2a),Spacing between two n-wells,,1.270,µm 4 | (nwell.2b),Manual merge wells if less than minimum,,, 5 | (nwell.4),All n-wells will contain metal-contacted tap (rule checks only for licon on tap) . Rule exempted from high voltage cells inside UHVI,,, 6 | (nwell.5),"Deep nwell must be enclosed by nwell by atleast... Exempted inside UHVI or :drc_tag:`areaid.lw` 7 | Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)",TC,0.400,µm 8 | (nwell.5a),min enclosure of nwell by dnwell inside UHVI,,N/A,N/A 9 | (nwell.5b),nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A,N/A 10 | (nwell.6),Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030,µm 11 | (nwell.7),"Min spacing between nwell and deep nwell on separate nets 12 | Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on. 13 | waffle_chip",TC,4.500,µm 14 | -------------------------------------------------------------------------------- /.github/kokoro/steps/auth.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright 2020 Regents of the University of California 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # 18 | # SPDX-License-Identifier: Apache-2.0 19 | 20 | set -e 21 | 22 | echo 23 | echo "========================================" 24 | echo "Setting up authentication" 25 | echo "----------------------------------------" 26 | ( 27 | cd $KOKORO_ARTIFACTS_DIR 28 | ls -l 29 | # Run the GOB cookie daemon to allow cloning from 30 | # foss-eda-tools.googlesource.com 31 | git clone https://gerrit.googlesource.com/gcompute-tools \ 32 | $KOKORO_ARTIFACTS_DIR/gcompute-tools 33 | $KOKORO_ARTIFACTS_DIR/gcompute-tools/git-cookie-authdaemon 34 | ) 35 | echo "----------------------------------------" 36 | -------------------------------------------------------------------------------- /docs/rules/masks.csv: -------------------------------------------------------------------------------- 1 | Mask,Acronym,Used in SKY130 2 | Field Oxide,FOM,X 3 | Deep N-Well,DNM,X 4 | P-Well Block Mask,PWBM, 5 | P-Well Drain Extended ,PWDEM, 6 | N-Well*,NWM,X 7 | High Vt PCh*,HVTPM,X 8 | Low Vt Nch*,LVTNM,X 9 | HLow VT PCh Radio*,HVTRM,X 10 | N-Core Implant,NCM, 11 | Tunnel Mask,TUNM,X 12 | ONO Mask,ONOM,X 13 | Low Voltage Oxide,LVOM,X 14 | Resistor Protect,RPM,X 15 | Poly 1,P1M,X 16 | N-tip Implant,NTM,X 17 | High Volt. N-tip,HVNTM,X 18 | Lightly Doped N-tip,LDNTM,X 19 | Nitride Poly Cut,NPCM,X 20 | P+ Implant,PSDM,X 21 | N+ Implant,NSDM,X 22 | Local Intr Cont.1,LICM1,X 23 | Local Intrcnct 1,LI1M,X 24 | Contact,CTM1,X 25 | Open Frame Mask,OFM, 26 | Metal 1,MM1,X 27 | Via,VIM,X 28 | Capacitor MiM,CAPM, 29 | Metal 2,MM2,X 30 | Via 2-TNV,VIM2, 31 | Via 2-S8TM,VIM2, 32 | Via 2-PLM,VIM2,X 33 | Metal 3-TLM,MM3, 34 | Metal 3-S8TM,MM3, 35 | Metal 3-PLM,MM3,X 36 | Pad Via,VIPDM, 37 | Via3-PLM,VIM3,X 38 | Inductor-TLM,INDM, 39 | Metal 4,MM4,X 40 | Via4,VIM4,X 41 | Metal 5,MM5,X 42 | Nitride Seal Mask,NSM,X 43 | Pad (scribe protect),PDM,X 44 | Pad (scribe unprotect),PDM, 45 | Polyimide,PMM, 46 | Polyimide_ExtFab,PMM[E], 47 | Pad&Polyimide_ExtFab,PDMM[E], 48 | DECA PBO,PBO,X 49 | Cu Inductor/Redist.,CU1M,X 50 | Polyimide 2 (2),PMM2,X 51 | Under Bump Metal,UBM, 52 | Bumps,BUMP, 53 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_g5v0d10v5/index.rst: -------------------------------------------------------------------------------- 1 | 5.0V/10.5V PMOS FET 2 | ------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__pfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to -11.0V 13 | - :math:`V_{GS} = 0` to -5.5V 14 | - :math:`V_{BS} = 0` to +5.5V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs 20 | 21 | 22 | .. include:: pfet_g5v0d10v5-table0.rst 23 | 24 | 25 | 26 | Inverter gate delays are shown below: 27 | 28 | 29 | .. include:: pfet_g5v0d10v5-table1.rst 30 | 31 | 32 | 33 | The symbols of the :model:`sky130_fd_pr__pfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` (5.0V/10.5V PMOS FET) are shown below: 34 | 35 | |symbol-pfet_g5v0d10v5| |symbol-esd_pfet_g5v0d10v5| 36 | 37 | The cross-section of the 5.0V PMOS FET is shown below. 38 | 39 | |cross-section-pfet_g5v0d10v5| 40 | 41 | .. |symbol-pfet_g5v0d10v5| image:: symbol-pfet_g5v0d10v5.svg 42 | .. |symbol-esd_pfet_g5v0d10v5| image:: symbol-esd_pfet_g5v0d10v5.svg 43 | .. |cross-section-pfet_g5v0d10v5| image:: cross-section-pfet_g5v0d10v5.svg 44 | 45 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8_hvt/index.rst: -------------------------------------------------------------------------------- 1 | 1.8V high-VT PMOS FET 2 | --------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__pfet_01v8_hvt` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to -1.95V 13 | - :math:`V_{GS} = 0` to -1.95V 14 | - :math:`V_{BS} = -0.1` to +1.95V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs 20 | 21 | 22 | .. include:: pfet_01v8_hvt-table0.rst 23 | 24 | 25 | 26 | Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8_hvt` device combinations: 27 | 28 | 29 | .. include:: pfet_01v8_hvt-table1.rst 30 | 31 | 32 | 33 | The symbol of the :model:`sky130_fd_pr__pfet_01v8_hvt` (1.8V high-VT PMOS FET) is shown below: 34 | 35 | |symbol-pfet_01v8_hvt| 36 | 37 | The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the higher :math:`V_T`) 38 | 39 | |cross-section-pfet_01v8_hvt| 40 | 41 | .. |symbol-pfet_01v8_hvt| image:: symbol-pfet_01v8_hvt.svg 42 | .. |cross-section-pfet_01v8_hvt| image:: cross-section-pfet_01v8_hvt.svg 43 | 44 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8_lvt/index.rst: -------------------------------------------------------------------------------- 1 | 1.8V low-VT PMOS FET 2 | -------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to -1.95V 13 | - :math:`V_{GS} = 0` to -1.95V 14 | - :math:`V_{BS} = -0.1` to +1.95V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs 20 | 21 | 22 | .. include:: pfet_01v8_lvt-table0.rst 23 | 24 | 25 | 26 | Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations: 27 | 28 | 29 | .. include:: pfet_01v8_lvt-table1.rst 30 | 31 | 32 | 33 | The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below: 34 | 35 | |symbol-pfet_01v8_lvt| 36 | 37 | The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the lower :math:`V_T`) 38 | 39 | |cross-section-pfet_01v8_lvt| 40 | 41 | .. |symbol-pfet_01v8_lvt| image:: symbol-pfet_01v8_lvt.svg 42 | .. |cross-section-pfet_01v8_lvt| image:: cross-section-pfet_01v8_lvt.svg 43 | 44 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_01v8_lvt/index.rst: -------------------------------------------------------------------------------- 1 | 1.8V low-VT NMOS FET 2 | -------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__nfet_01v8_lvt` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to 1.95V 13 | - :math:`V_{GS} = 0` to 1.95V 14 | - :math:`V_{BS} = +0.3` to -1.95V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | Major model output parameters are shown below and compared against the EDR (e-test) specs. 20 | 21 | 22 | .. include:: nfet_01v8_lvt-table0.rst 23 | 24 | 25 | 26 | Inverter Gate Delays using :model:`sky130_fd_pr__nfet_01v8_lvt`/:model:`sky130_fd_pr__pfet_01v8` device combinations: 27 | 28 | 29 | .. include:: nfet_01v8_lvt-table1.rst 30 | 31 | 32 | 33 | The symbol of the :model:`sky130_fd_pr__nfet_01v8_lvt` (1.8V low-VT NMOS FET) is shown below: 34 | 35 | |symbol-nfet_01v8_lvt| 36 | 37 | The cross-section of the low-VT NMOS FET is shown below. The cross-section is identical to the std NMOS FET except for the :math:`V_T` adjust implants (to achieve the lower :math:`V_T`) 38 | 39 | |cross-section-nfet_01v8_lvt| 40 | 41 | .. |symbol-nfet_01v8_lvt| image:: symbol-nfet_01v8_lvt.svg 42 | .. |cross-section-nfet_01v8_lvt| image:: cross-section-nfet_01v8_lvt.svg 43 | 44 | -------------------------------------------------------------------------------- /scripts/python-skywater-pdk/README.rst: -------------------------------------------------------------------------------- 1 | skywater-pdk Python Module 2 | ========================== 3 | 4 | This Python module is a small library for working with the files found inside 5 | the SkyWater PDK. 6 | 7 | It includes tools for decoding things like file names into human readable 8 | descriptions. 9 | 10 | It also includes tools for combining files together. 11 | 12 | License 13 | ======= 14 | 15 | Like the SkyWater Open Source PDK, the SkyWater Python Module is released under 16 | the 17 | `Apache 2.0 license `_. 18 | 19 | The copyright details (which should also be found at the top of every file) are; 20 | 21 | :: 22 | 23 | Copyright 2020 SkyWater PDK Authors 24 | 25 | Licensed under the Apache License, Version 2.0 (the "License"); 26 | you may not use this file except in compliance with the License. 27 | You may obtain a copy of the License at 28 | 29 | http://www.apache.org/licenses/LICENSE-2.0 30 | 31 | Unless required by applicable law or agreed to in writing, software 32 | distributed under the License is distributed on an "AS IS" BASIS, 33 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 34 | See the License for the specific language governing permissions and 35 | limitations under the License. 36 | 37 | 38 | -------------------------------------------------------------------------------- /docs/rules/periphery/p042-via3_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (via3.1),Min and max L and W of via3 (except for rule via3.1a),AL,0.200,µm 3 | (via3.1a),Two sizes of square via3 allowed inside :drc_tag:`areaid.mt`: 0.200um and 0.800um,AL,, 4 | (via3.2),Spacing of via3 to via3,AL,0.200,µm 5 | (via3.3),Only min. square via3s are allowed except die seal ring where via3s are (Via3 CD)*L,,0.2*L, 6 | (via3.4),Via3 must be enclosed by Met3 by at least …,AL,0.060,µm 7 | (via3.5),Via3 must be enclosed by Met3 on one of two adjacent sides by at least …,AL,0.090,µm 8 | (via3.11),Min and max L and W of via3,CU,0.210,µm 9 | (via3.12),Min spacing between via2's,CU,0.180,µm 10 | (via3.13),Via3 must be enclosed by Met3 by at least …,CU,0.055,µm 11 | (via3.14),Min spacing between via3 rows,CU,0.350,µm 12 | (via3.irdrop.1),"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm 13 | (via3.irdrop.2),"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6,µm 14 | (via3.irdrop.3),"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8,µm 15 | (via3.irdrop.4),"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9,µm 16 | -------------------------------------------------------------------------------- /docs/status.rst: -------------------------------------------------------------------------------- 1 | .. include:: common.inc 2 | 3 | Current Status -- |current-status| 4 | ================================== 5 | 6 | .. current_status_text 7 | 8 | .. warning:: 9 | Google and SkyWater are currently treating the current content as an **experimental preview** / **alpha release**. 10 | 11 | While the SKY130 process node and the PDK from which this open source release was derived have been used to create many designs that have been successfully manufactured commercially in significant quantities, the open source PDK is not intended to be used for production settings at this current time. It *should* be usable for doing test chips and initial design verification (but this is not guaranteed). 12 | 13 | Google, SkyWater and our partners are currently doing internal validation and test designs, including silicon validation or the released data and plan to publish these results. 14 | 15 | The PDK will be tagged with a production version when ready to do production design, see the ":ref:`Versioning Information`" section for a full description of the version numbering scheme. 16 | 17 | To get notified about future new releases of the PDK, and other important news, please sign up on the 18 | `skywater-pdk-announce mailing list `_ 19 | [`join link `_]. 20 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2020 SkyWater PDK Authors 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # https://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | # 15 | # SPDX-License-Identifier: Apache-2.0 16 | 17 | # .readthedocs.yml 18 | # Read the Docs configuration file 19 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 20 | 21 | # Required 22 | version: 2 23 | 24 | # Build documentation in the docs/ directory with Sphinx 25 | sphinx: 26 | configuration: docs/conf.py 27 | 28 | conda: 29 | environment: docs/environment.yml 30 | 31 | submodules: 32 | include: 33 | - libraries/sky130_fd_io/latest 34 | - libraries/sky130_fd_sc_hd/latest 35 | - libraries/sky130_fd_sc_hdll/latest 36 | - libraries/sky130_fd_sc_hs/latest 37 | - libraries/sky130_fd_sc_ls/latest 38 | - libraries/sky130_fd_sc_ms/latest 39 | recursive: false 40 | 41 | formats: 42 | - pdf 43 | -------------------------------------------------------------------------------- /docs/contributing.rst: -------------------------------------------------------------------------------- 1 | How to Contribute 2 | ================= 3 | 4 | We'd love to accept your patches and contributions to this project. 5 | There are just a few small guidelines you need to follow. 6 | 7 | Contributor License Agreement 8 | ----------------------------- 9 | 10 | Contributions to this project must be accompanied by a Contributor 11 | License Agreement. You (or your employer) retain the copyright to your 12 | contribution; this simply gives us permission to use and redistribute 13 | your contributions as part of the project. Head over to 14 | https://cla.developers.google.com/ to see your current agreements on 15 | file or to sign a new one. 16 | 17 | You generally only need to submit a CLA once, so if you've already 18 | submitted one (even if it was for a different project), you probably 19 | don't need to do it again. 20 | 21 | Code reviews 22 | ------------ 23 | 24 | All submissions, including submissions by project members, require 25 | review. We use GitHub pull requests for this purpose. Consult `GitHub 26 | Help `__ for more 27 | information on using pull requests. 28 | 29 | Community Guidelines 30 | -------------------- 31 | 32 | This project follows `Google's Open Source Community 33 | Guidelines `__. 34 | 35 | .. include:: code-of-conduct.rst 36 | :start-after: community_guidelines_text 37 | -------------------------------------------------------------------------------- /docs/rules/antenna/table-Ia-antenna-rules-s8d.csv: -------------------------------------------------------------------------------- 1 | ,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,, 2 | (ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus 3 | ,,,,,, 4 | .poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a 5 | .licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a 6 | .li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a 7 | .mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a 8 | .met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200 9 | .via.1,Via (via area/gate area),Horizontal,,6,36,n/a 10 | .met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200 11 | .pad.1,pad (via2 area/gate area),Horizontal,,6,36,n/a 12 | .indm.1,INDM (met3 perimeter area/gate area),Vertical,4.000,400,400,2200 13 | .ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,, 14 | Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,, 15 | ,,,,,, 16 | "Max length of Poly (approx, assumes min width)",,135,,n/a,, 17 | Max number of Licons,,103,,n/a,, 18 | "Max length of LI (approx, assumes min width)",,370,,2620,, 19 | Max number of Mcon,,103,,726,, 20 | "Max length of Met1 (approx, assumes min width)",,570,,4280,, 21 | Max number of Via,,266,,1866,, 22 | "Max length of Met2 (approx, assumes min width)",,570,,4280,, 23 | Max number of pad via,,4,,29,, 24 | "Max length of Met3 (approx, assumes min width)",,45,,370,, 25 | -------------------------------------------------------------------------------- /.github/travis/git-check.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # Copyright 2020 SkyWater PDK Authors 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # https://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | # SPDX-License-Identifier: Apache-2.0 17 | 18 | set -e 19 | 20 | source .github/travis/common.sh 21 | 22 | # Output any changes in the repository 23 | # ------------------------------------------------------------------------ 24 | start_section git-status "Current git status" 25 | 26 | git diff 27 | 28 | $SPACER 29 | 30 | git status 31 | 32 | end_section git-status 33 | 34 | # Check there are not changes in the repository 35 | # ------------------------------------------------------------------------ 36 | start_section git-check "Checking git repository isn't dirty" 37 | 38 | ( 39 | . "$(git --exec-path)/git-sh-setup" 40 | 41 | require_clean_work_tree "continue" "Please include the changes in your commits." 42 | ) 43 | 44 | end_section git-check 45 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_05v0_nvt/index.rst: -------------------------------------------------------------------------------- 1 | 5.0V native NMOS FET 2 | -------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_05v0_nvt` 8 | - Model Name: :model:`sky130_fd_pr__nfet_05v0_nvt` 9 | 10 | Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_05v0_nvt` 11 | 12 | - :math:`V_{DS} = 0` to 5.5V 13 | - :math:`V_{GS} = 0` to 5.5V 14 | - :math:`V_{BS} = +0.3` to -5.5V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The native device is constructed by blocking out all VT implants. 20 | 21 | The model and EDR (e-test) parameters are compared below. 22 | 23 | The 5V device has minimum gate length of 0.9 µm. 24 | 25 | 26 | .. include:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/nfet_03v3_nvt-and-nfet_05v0_nvt-table0.rst 27 | 28 | 29 | The symbols for the :model:`sky130_fd_pr__nfet_05v0_nvt` devices are shown below. 30 | 31 | |symbol-nfet_05v0_nvt| 32 | 33 | The cross-section of the native devices is shown below. 34 | 35 | .. note:: The only differences between the :model:`sky130_fd_pr__nfet_03v3_nvt` and :model:`sky130_fd_pr__nfet_05v0_nvt` devices are the minimum gate length and the VDS requirements. 36 | 37 | |cross-section-nfet_05v0_nvt| 38 | 39 | .. |symbol-nfet_05v0_nvt| image:: symbol-nfet_05v0_nvt.svg 40 | .. |cross-section-nfet_05v0_nvt| image:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/cross-section-nfet_03v3_nvt-and-nfet_05v0_nvt.svg 41 | 42 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_03v3_nvt/index.rst: -------------------------------------------------------------------------------- 1 | 3.0V native NMOS FET 2 | -------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__nfet_03v3_nvt` 9 | 10 | Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_03v3_nvt` 11 | 12 | - :math:`V_{DS} = 0` to 3.3V 13 | - :math:`V_{GS} = 0` to 3.3V 14 | - :math:`V_{BS} = 0` to -3.3V 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The native device is constructed by blocking out all VT implants. 20 | 21 | The model and EDR (e-test) parameters are compared below. Note that the minimum gate length for 3V operation is 0.5 µm. 22 | 23 | 24 | .. include:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/nfet_03v3_nvt-and-nfet_05v0_nvt-table0.rst 25 | 26 | 27 | 28 | The symbols for the :model:`sky130_fd_pr__nfet_03v3_nvt` devices are shown below. 29 | 30 | |symbol-nfet_0v3v3_nvt| 31 | 32 | The cross-section of the native devices is shown below. 33 | 34 | 35 | |cross-section-nfet_03v3_nvt| 36 | 37 | .. |symbol-nfet_0v3v3_nvt| image:: symbol-nfet_03v3_nvt.svg 38 | .. |cross-section-nfet_03v3_nvt| image:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/cross-section-nfet_03v3_nvt-and-nfet_05v0_nvt.svg 39 | 40 | .. note:: The only differences between the :model:`sky130_fd_pr__nfet_03v3_nvt` and :model:`sky130_fd_pr__nfet_05v0_nvt` devices are the minimum gate length and the VDS requirements. 41 | -------------------------------------------------------------------------------- /docs/verification.rst: -------------------------------------------------------------------------------- 1 | Physical & Design Verification 2 | ============================== 3 | 4 | .. toctree:: 5 | :caption: Physical & Design Verification 6 | :name: verification 7 | 8 | Automated Design Rule (DRC) Checking 9 | - With Mentor Calibre 10 | - With MAGIC 11 | - With Klayout 12 | Layout Versus Schematic (LVS) Checking 13 | - With Mentor Calibre 14 | - With netgen 15 | Parasitic Extraction (PEX) 16 | - With Calibre xRC 17 | - With MAGIC 18 | 19 | 20 | .. todo:: 21 | The SkyWater SKY130 PDK provides automated physical and design rule checking decks. 22 | 23 | These verification rules provide; 24 | 25 | * :term:`Design Rule Checking` (:term:`DRC`) against rules described in the 26 | :ref:`SkyWater SKY130 Process Design Rules` documentation. 27 | 28 | .. warning:: 29 | 30 | There are some design rules which can not be verified with these decks. 31 | They are clearly marked in the :ref:`SkyWater SKY130 Process Design Rules` 32 | documentation and should be manually verified by the designer. 33 | 34 | * :term:`Layout Verse Schematic` (:term`LVS`) Verification 35 | * :term:`Parasitic Extraction` (:term:`PEX`) 36 | 37 | TODO: Calibre Decks 38 | ------------------- 39 | 40 | Put stuff here. 41 | 42 | TODO: MAGIC Decks 43 | ----------------- 44 | 45 | Put stuff here. 46 | 47 | -------------------------------------------------------------------------------- /docs/rules/device-details/cap_mim/index.rst: -------------------------------------------------------------------------------- 1 | MiM capacitors 2 | -------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__cap_mim_m3__base`, :cell:`sky130_fd_pr__cap_mim_m4__base` 8 | - Model Names: :model:`sky130_fd_pr__model__cap_mim`, :model:`sky130_fd_pr__cap_mim_m4` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`|V_{c0} – V_{c1}| = 0` to 5.0V 13 | 14 | Details 15 | ~~~~~~~ 16 | 17 | The MiM capacitor is constructed using a thin dielectric over metal, followed by a thin conductor layer on top of the dielectric. There are two possible constructions: 18 | 19 | - CAPM over Metal-3 20 | - CAP2M over Metal-4 21 | 22 | The constructions are identical, and the capacitors may be stacked to maximize total capacitance. 23 | 24 | Electrical specs are listed below: 25 | 26 | 27 | .. include:: cap_mim-table0.rst 28 | 29 | 30 | 31 | The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate. 32 | 33 | |symbol-cap_mim| 34 | 35 | Cell name 36 | 37 | M \* W \* L 38 | 39 | Calc capacitance 40 | 41 | The cross-section of the “stacked” MiM capacitor is shown below: 42 | 43 | |cross-section-cap_mim| 44 | 45 | .. |symbol-cap_mim| image:: symbol-cap_mim.svg 46 | .. |cross-section-cap_mim| image:: cross-section-cap_mim.svg 47 | 48 | -------------------------------------------------------------------------------- /docs/rules/device-details/cap_var/cap_var-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 1 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - NOM 8 | - LSL 9 | - USL 10 | - Units 11 | - Description 12 | 13 | * - VC\_CMAX\_5\_5 14 | - 20.26 15 | - 18.91 16 | - 21.52 17 | - pF 18 | - PLOWVT based varactor 5/5 in accumulation 19 | 20 | * - VC\_CMAX\_5\_P5 21 | - 10.17 22 | - 9.21 23 | - 11.12 24 | - pF 25 | - PLOWVT based varactor 5/5 in inversion 26 | 27 | * - VC\_CMIN\_5\_5 28 | - 2.058 29 | - 1.863 30 | - 2.262 31 | - pF 32 | - PLOWVT based varactor 5/0.5 in accumulation 33 | 34 | * - VC\_CMIN\_5\_P5 35 | - 1.9 36 | - 1.725 37 | - 2.087 38 | - pF 39 | - PLOWVT based varactor 5/0.5 in inversion 40 | 41 | * - VC2\_CMAX\_5\_5 42 | - 20.37 43 | - 19.02 44 | - 21.68 45 | - pF 46 | - PHIGHVT based varactor 5/5 in accumulation 47 | 48 | * - VC2\_CMAX\_5\_P5 49 | - 10.2 50 | - 9.24 51 | - 11.18 52 | - pF 53 | - PHIGHVT based varactor 5/5 in inversion 54 | 55 | * - VC2\_CMIN\_5\_5 56 | - 4.197 57 | - 3.95 58 | - 4.453 59 | - pF 60 | - PHIGHVT based varactor 5/0.5 in accumulation 61 | 62 | * - VC2\_CMIN\_5\_P5 63 | - 2.762 64 | - 2.537 65 | - 2.999 66 | - pF 67 | - PHIGHVT based varactor 5/0.5 in inversion 68 | 69 | -------------------------------------------------------------------------------- /docs/rules/periphery/p048-hvdifftap_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (hvdifftap.14),"Min width of diff inside Hvi, except HV Pdiff resistors (difftap.14a)",P,0.290,µm 3 | (hvdifftap.14a),"Min width of diff inside Hvi, HV Pdiff resistors only",P,0.150,µm 4 | (hvdifftap.15a),Min space of Hdiff to Hdiff,P,0.300,µm 5 | (hvdifftap.15b),Min space of n+diff to non-abutting p+tap inside Hvi,P,0.370,µm 6 | (hvdifftap.16),Min width tap butting diff on one or two sides inside Hvi (rule exempted inside UHVI),,0.700,µm 7 | (hvdifftap.17),P+ Hdiff or Pdiff inside areaid:hvnwell must be enclosed by Hv_nwell by at least ….[Rule exempted inside UHVI],DE NE,0.330,µm 8 | (hvdifftap.18),Spacing of N+ diff to HV_nwell (rule exempted inside UHVI),DE NE,0.430,µm 9 | (hvdifftap.19),N+ Htap must be enclosed by Hv_nwell by at least …Rule exempted inside UHVI.,NE,0.330,µm 10 | (hvdifftap.20),Spacing of P+ tap to HV_nwell (Exempted for p+tap butting pwell.rs; rule exempted inside UHVI),,0.430,µm 11 | (hvdifftap.21),Diff or tap cannot straddle Hvi,P,, 12 | (hvdifftap.22),Min enclosure of Hdiff or Htap by Hvi. Rule exempted inside UHVI.,P,0.180,µm 13 | (hvdifftap.23),Space between diff or tap outside Hvi and Hvi,P,0.180,µm 14 | (hvdifftap.24),Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),DE NE,0.430,µm 15 | (hvdifftap.25),Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070,µm 16 | (hvdifftap.26),Min spacing between pwbm to difftap outside UHVI,,N/A,N/A 17 | -------------------------------------------------------------------------------- /docs/rules/antenna/table-Ib-antenna-rules-s8tnv-5r.csv: -------------------------------------------------------------------------------- 1 | Table Ib. Antenna rules (S8TNV-5R),,,,,, 2 | ,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,, 3 | (ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus 4 | ,,,,,, 5 | .poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a 6 | .licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a 7 | .li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a 8 | .mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a 9 | .met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200 10 | .via.1,Via (via area/gate area),Horizontal,,6,36,n/a 11 | .met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200 12 | .via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a 13 | .met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.850,400,400,2200 14 | .ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,, 15 | Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,, 16 | ,,,,,, 17 | "Max length of Poly (approx, assumes min width)",,135,,n/a,, 18 | Max number of Licons,,103,,n/a,, 19 | "Max length of LI (approx, assumes min width)",,370,,2620,, 20 | Max number of Mcon,,103,,726,, 21 | "Max length of Met1 (approx, assumes min width)",,570,,4280,, 22 | Max number of Via,,266,,1866,, 23 | "Max length of Met2 (approx, assumes min width)",,570,,4280,, 24 | Max number of Via2,,76,,535,, 25 | "Max length of Met3 (approx, assumes min width)",,230,,1760,, 26 | -------------------------------------------------------------------------------- /docs/rules/antenna/table-Ic-antenna-rules-s8tm.csv: -------------------------------------------------------------------------------- 1 | Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*),,,,,, 2 | ,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,, 3 | (ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus 4 | ,,,,,, 5 | .poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a 6 | .licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a 7 | .li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a 8 | .mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a 9 | .met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200 10 | .via.1,Via (via area/gate area),Horizontal,,6,36,n/a 11 | .met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200 12 | .via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a 13 | .met3.1,Met3 (met3 perimeter area/gate area),Vertical,2.000,400,400,2200 14 | .ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,, 15 | Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,, 16 | ,,,,,, 17 | "Max length of Poly (approx, assumes min width)",,135,,n/a,, 18 | Max number of Licons,,103,,n/a,, 19 | "Max length of LI (approx, assumes min width)",,370,,2620,, 20 | Max number of Mcon,,103,,726,, 21 | "Max length of Met1 (approx, assumes min width)",,570,,4280,, 22 | Max number of Via,,266,,1866,, 23 | "Max length of Met2 (approx, assumes min width)",,570,,4280,, 24 | Max number of Via2,,9,,65,, 25 | "Max length of Met3 (approx, assumes min width)",,95,,740,, 26 | -------------------------------------------------------------------------------- /.github/kokoro/steps/hostsetup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright 2020 Regents of the University of California 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # 18 | # SPDX-License-Identifier: Apache-2.0 19 | 20 | set -e 21 | 22 | echo 23 | echo "========================================" 24 | echo "Host updating packages" 25 | echo "----------------------------------------" 26 | sudo apt-get update 27 | echo "----------------------------------------" 28 | 29 | echo 30 | echo "========================================" 31 | echo "Host install packages" 32 | echo "----------------------------------------" 33 | sudo apt-get install -y \ 34 | bash \ 35 | build-essential \ 36 | ca-certificates \ 37 | colordiff \ 38 | coreutils \ 39 | git \ 40 | m4 \ 41 | make \ 42 | psmisc \ 43 | wget 44 | 45 | echo "----------------------------------------" 46 | -------------------------------------------------------------------------------- /docs/index.rst: -------------------------------------------------------------------------------- 1 | .. include:: common.inc 2 | 3 | .. toctree:: 4 | :hidden: 5 | 6 | versioning 7 | Current Status 8 | known_issues 9 | 10 | Design Rules 11 | 12 | contents 13 | 14 | analog 15 | digital 16 | sim 17 | verification 18 | 19 | Python API 20 | 21 | previous 22 | glossary 23 | 24 | contributing 25 | partners 26 | 27 | references 28 | 29 | 30 | Welcome to SkyWater SKY130 PDK's documentation! 31 | =============================================== 32 | 33 | .. warning:: 34 | This documentation is currently a **work in progress**. 35 | 36 | .. image:: _static/skywater-pdk-logo.png 37 | :align: center 38 | :alt: SkyWater PDK Logo Image. 39 | 40 | 41 | .. _CurrentStatus: 42 | 43 | Current Status - |current-status| 44 | ================================= 45 | 46 | .. include:: status.rst 47 | :start-after: current_status_text 48 | 49 | Resources 50 | ========= 51 | 52 | The latest SkyWater SKY130 PDK design resources can be downloaded from the following repositories: 53 | 54 | * `On Github @ google/skywater-pdk `_ 55 | * `Google CodeSearch interface @ https://cs.opensource.google/skywater-pdk `_ 56 | * `foss-eda-tools.googlesource.com/skywater-pdk `_ 57 | 58 | Indices and tables 59 | ================== 60 | 61 | * :ref:`glossary` 62 | * :ref:`genindex` 63 | * :ref:`modindex` 64 | * :ref:`search` 65 | -------------------------------------------------------------------------------- /docs/rules/device-details/cap_var/index.rst: -------------------------------------------------------------------------------- 1 | 1.8V accumulation-mode MOS varactors 2 | ------------------------------------ 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`capbn_b` 8 | - Model Name: :model:`sky130_fd_pr__cap_var_lvt`, :model:`sky130_fd_pr__cap_var_hvt` 9 | - Model Type: subcircuit 10 | 11 | Operating Voltages where SPICE models are valid 12 | 13 | - :math:`|V_0 – V_1| = 0` to 2.0V 14 | 15 | Details 16 | ~~~~~~~ 17 | 18 | The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model: 19 | 20 | - :model:`sky130_fd_pr__cap_var_lvt` - low VT PMOS device option 21 | - :model:`sky130_fd_pr__cap_var_hvt` - high VT PMOS device option 22 | 23 | The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request. 24 | 25 | 26 | .. include:: cap_var-table0.rst 27 | 28 | 29 | 30 | There is no equivalent varactor for 5V operation. The NHV or PHV devices should be connected as capacitors for use at 5V. 31 | 32 | The symbols for the varactors are shown below: 33 | 34 | |symbol-cap_var-a| |symbol-cap_var-b| 35 | 36 | The cross-section of the varactor is shown below: 37 | 38 | |cross-section-cap_var| 39 | 40 | .. |symbol-cap_var-a| image:: symbol-cap_var-a.svg 41 | .. |symbol-cap_var-b| image:: symbol-cap_var-b.svg 42 | .. |cross-section-cap_var| image:: cross-section-cap_var.svg 43 | 44 | -------------------------------------------------------------------------------- /docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (vhvi.vhv.1),Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,NC,, 3 | (vhvi.vhv.2),A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,NC,, 4 | (vhvi.vhv.3),Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,NC,, 5 | (vhvi.vhv.4),Any feature connected to VHVPoly becomes a very-high-voltage feature,NC,, 6 | (vhvi.vhv.5),"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,, 7 | (vhvi.vhv.6),"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",NC,, 8 | (vhvi.1.-),Min width of vhvi:dg,,0.020,µm 9 | (vhvi.2.-),Vhvi:dg cannot overlap areaid:ce,,, 10 | (vhvi.3.-),VHVGate must overlap hvi:dg,,, 11 | (vhvi.4.-),Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,, 12 | (vhvi.5.-),Vhvi:dg cannot straddle VHVSourceDrain,,, 13 | (vhvi.6.-),Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,, 14 | (vhvi.7.-),Vhvi:dg cannot straddle VHVPoly,,, 15 | (vhvi.8.-),"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240,µm 16 | -------------------------------------------------------------------------------- /docs/rules/device-details/pnp_05v0/pnp_05v0-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 1 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - NOM 8 | - LSL 9 | - USL 10 | - Units 11 | - Description 12 | 13 | * - BF0P68\_0P5 14 | - 14.29 15 | - 7.51 16 | - 21.02 17 | - 18 | - PNP forward current gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=0.5 µA` 19 | 20 | * - BF0P68\_5 21 | - 12.58 22 | - 6.59 23 | - 18.59 24 | - 25 | - PNP forward current gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=5.0 µA` 26 | 27 | * - VBE0P68\_0P5 28 | - 0.7180 29 | - 0.7120 30 | - 0.7240 31 | - V 32 | - PNP emitter-base voltage at :math:`I_E=0.5 µA` 33 | 34 | * - VBE0P68\_5 35 | - 0.7847 36 | - 0.7790 37 | - 0.7904 38 | - V 39 | - PNP emitter-base voltage at :math:`I_E=5.0 µA` 40 | 41 | * - BF3P4\_0P1 42 | - 13.20 43 | - 5.93 44 | - 20.20 45 | - 46 | - PNP forward current gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=0.1 µA` 47 | 48 | * - BF3P4\_10 49 | - 14.65 50 | - 6.10 51 | - 23.10 52 | - 53 | - PNP forward current gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=1.0 µA` 54 | 55 | * - VBE3P4\_0P1 56 | - 0.6129 57 | - 0.6087 58 | - 0.6172 59 | - V 60 | - PNP emitter-base voltage at :math:`I_E=0.1 µA` 61 | 62 | * - VBE3P4\_10 63 | - 0.7351 64 | - 0.7308 65 | - 0.7393 66 | - V 67 | - PNP emitter-base voltage at :math:`I_E=1.0 µA` 68 | 69 | -------------------------------------------------------------------------------- /docs/rules/periphery/p026-difftap_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (difftap.1),Width of diff or tap,P,0.150,µm 3 | (difftap.2),"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a",P,0.420,µm 4 | (difftap.2a),"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA,µm 5 | (difftap.2b),Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360,µm 6 | (difftap.3),"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270,µm 7 | (difftap.4),Min tap bound by one diffusion,,0.290, 8 | (difftap.5),Min tap bound by two diffusions,P,0.400, 9 | (difftap.6),Diff and tap are not allowed to extend beyond their abutting edge,,, 10 | (difftap.7),Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130,µm 11 | (difftap.8),Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,DE NE P,0.180,µm 12 | (difftap.9),Spacing of (n+) diffusion to N-well outside UHVI,DE NE P,0.340,µm 13 | (difftap.10),Enclosure of (n+) tap by N-well. Rule exempted inside UHVI.,NE P,0.180,µm 14 | (difftap.11),Spacing of (p+) tap to N-well. Rule exempted inside UHVI.,,0.130,µm 15 | (difftap.12),ESD_nwell_tap is considered shorted to the abutting diff,NC,, 16 | (difftap.13),Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,, 17 | -------------------------------------------------------------------------------- /docs/rules/periphery/p029-rpm_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (rpm.1a),Min width of rpm,,1.270,µm 3 | (rpm.1b),Min/Max prec_resistor width xhrpoly_0p35,,0.350,µm 4 | (rpm.1c),Min/Max prec_resistor width xhrpoly_0p69,,0.690,µm 5 | (rpm.1d),Min/Max prec_resistor width xhrpoly_1p41,,1.410,µm 6 | (rpm.1e),Min/Max prec_resistor width xhrpoly_2p85,,2.850,µm 7 | (rpm.1f),Min/Max prec_resistor width xhrpoly_5p73,,5.730,µm 8 | (rpm.1g),Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,, 9 | (rpm.1h),Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,, 10 | (rpm.1i),Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,, 11 | (rpm.1j),Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,, 12 | (rpm.1k),Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,, 13 | (rpm.2),Min spacing of rpm to rpm,,0.840,µm 14 | (rpm.3),rpm must enclose prec_resistor by atleast,,0.200, 15 | (rpm.4),prec_resistor must be enclosed by psdm by atleast,,0.110,µm 16 | (rpm.5),prec_resistor must be enclosed by npc by atleast,,0.095,µm 17 | (rpm.6),"Min spacing, no overlap, of rpm and nsdm",,0.200,µm 18 | (rpm.7),Min spacing between rpm and poly,,0.200,µm 19 | (rpm.8),poly must not straddle rpm,,, 20 | (rpm.9),"Min space, no overlap, between prec_resistor and hvntm",,0.185,µm 21 | (rpm.10),Min spacing of rpm to pwbm,,N/A,N/A 22 | (rpm.11),"| rpm should not overlap or straddle pwbm except cells 23 | | s8usbpdv2_csa_top 24 | | s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit 25 | | s8usbpdv2_20vconn_sw_300ma_ovp 26 | | s8usbpdv2_20sbu_sw_300ma_ovp",,N/A,N/A 27 | -------------------------------------------------------------------------------- /scripts/make/git.mk: -------------------------------------------------------------------------------- 1 | # Copyright 2020 SkyWater PDK Authors 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # https://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | FULL_VERSION := $(shell git describe --long) 16 | TAG_VERSION := $(firstword $(subst -, ,$(FULL_VERSION))) 17 | 18 | SUBMODULE_VERSION ?= latest 19 | 20 | ifeq (,$(FULL_VERSION)) 21 | $(error "Version value could not be determined. Make sure you fetch the tags.") 22 | endif 23 | 24 | LIBRARIES = $(sort $(notdir $(wildcard libraries/sky130_*))) 25 | 26 | LIBS_DOT_GIT = $(addsuffix /$(SUBMODULE_VERSION)/.git,$(addprefix libraries/,$(LIBRARIES))) 27 | 28 | libraries-info: 29 | @echo "The following libraries exist:" 30 | @for L in $(LIBRARIES); do \ 31 | LD=libraries/$$L/$(SUBMODULE_VERSION); \ 32 | echo " * $$L"; \ 33 | echo " $$(git submodule status $$LD)"; \ 34 | done 35 | @echo $(LIBS_DOT_GIT) 36 | 37 | submodules: $(LIBS_DOT_GIT) 38 | 39 | define LIB_template 40 | libraries/$(1)/%/.git: .gitmodules 41 | git submodule update --init $$(@D) 42 | endef 43 | 44 | $(foreach lib,$(LIBRARIES), $(eval $(call LIB_template,$(lib)))) 45 | -------------------------------------------------------------------------------- /docs/rules/periphery/p028-poly_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (poly.X.1),All FETs would be checked for W/Ls as documented in spec 001-02735 (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,, 3 | (poly.X.1a),Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,, 4 | (poly.1a),Width of poly,,0.150,µm 5 | (poly.1b),Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350,µm 6 | (poly.2),Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210,µm 7 | (poly.3),Min poly resistor width,,0.330,µm 8 | (poly.4),Spacing of poly on field to diff (parallel edges only),P,0.075,µm 9 | (poly.5),Spacing of poly on field to tap,P,0.055,µm 10 | (poly.6),Spacing of poly on diff to abutting tap (min source),P,0.300,µm 11 | (poly.7),Extension of diff beyond poly (min drain),P,0.250, 12 | (poly.8),Extension of poly beyond diffusion (endcap),P,0.130, 13 | (poly.9),Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480,µm 14 | (poly.10),Poly can't overlap inner corners of diff,,, 15 | (poly.11),No 90 deg turns of poly on diff,,, 16 | (poly.12),"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,, 17 | (poly.15),Poly must not overlap diff:rs,,, 18 | (poly.16),"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,, 19 | -------------------------------------------------------------------------------- /docs/rules/device-details.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import re 4 | import os 5 | 6 | RE_IMAGE = re.compile('.. (.*) image:: (.*)') 7 | RE_INCLUDE = re.compile('.. include:: (.*)') 8 | 9 | device_list = [ 10 | # 1.8V MOS 11 | "nfet_01v8", 12 | "nfet_01v8_lvt", 13 | "pfet_01v8", 14 | "pfet_01v8_lvt", 15 | "pfet_01v8_hvt", 16 | "cap_var", 17 | 18 | # 3.3V MOS 19 | "nfet_03v3_nvt", 20 | 21 | # 5V MOS 22 | "nfet_05v0_nvt", 23 | "nfet_g5v0d10v5", 24 | "pfet_g5v0d10v5", 25 | "pfet_g5v0d16v0", 26 | 27 | # 11V MOS 28 | "nfet_g11v0d16v0", 29 | 30 | # 20V MOS 31 | "nfet_20v0", 32 | "nfet_20v0_nvt", 33 | "nfet_20v0_zvt", 34 | "nfet_20v0_iso", 35 | "pfet_20v0", 36 | 37 | # ESD MOS 38 | "esd_nfet", 39 | 40 | # Diodes/Bipolar 41 | "diodes", 42 | "npn_05v0", 43 | "pnp_05v0", 44 | 45 | # Special active devices 46 | "special_sram", 47 | "special_sonosfet", 48 | 49 | # Well/Diffusion/Poly/Metal Resistors 50 | "res_generic", 51 | "res_high", 52 | "res_xhigh", 53 | 54 | # Metal Capacitors 55 | "cap_mim", 56 | "cap_vpp", 57 | ] 58 | 59 | print('Device Details') 60 | print('==============') 61 | print() 62 | 63 | for device_name in device_list: 64 | fname = os.path.join("device-details", device_name, "index.rst") 65 | 66 | with open(fname) as f: 67 | data = f.read() 68 | 69 | dirname = os.path.split(fname)[0] 70 | 71 | data = RE_IMAGE.sub(r'.. \1 image:: {}/\2'.format(dirname), data) 72 | data = RE_INCLUDE.sub(r'.. include:: {}/\1'.format(dirname), data) 73 | print(data) 74 | -------------------------------------------------------------------------------- /.github/kokoro/steps/git.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright 2020 Regents of the University of California 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # 18 | # SPDX-License-Identifier: Apache-2.0 19 | 20 | set -e 21 | 22 | echo 23 | echo "========================================" 24 | echo "Git log" 25 | echo "----------------------------------------" 26 | git log -n5 --stat 27 | echo "----------------------------------------" 28 | 29 | echo 30 | echo "========================================" 31 | echo "Git fetching tags" 32 | echo "----------------------------------------" 33 | # Don't fail if there are no tags 34 | git fetch --tags || true 35 | echo "----------------------------------------" 36 | 37 | echo 38 | echo "========================================" 39 | echo "Git version info" 40 | echo "----------------------------------------" 41 | git log -n1 42 | echo "----------------------------------------" 43 | git describe --tags || true 44 | echo "----------------------------------------" 45 | git describe --tags --always || true 46 | echo "----------------------------------------" 47 | -------------------------------------------------------------------------------- /.github/travis/common.sh: -------------------------------------------------------------------------------- 1 | #!/usr/env false 2 | # 3 | # Copyright 2020 SkyWater PDK Authors 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # SPDX-License-Identifier: Apache-2.0 18 | 19 | # Some colors, use it like following; 20 | # echo -e "Hello ${YELLOW}yellow${NC}" 21 | GRAY=' \033[0;30m' 22 | RED=' \033[0;31m' 23 | GREEN=' \033[0;32m' 24 | YELLOW=' \033[0;33m' 25 | PURPLE=' \033[0;35m' 26 | NC='\033[0m' # No Color 27 | 28 | SPACER="echo -e ${GRAY} - ${NC}" 29 | 30 | export -f travis_nanoseconds 31 | export -f travis_fold 32 | export -f travis_time_start 33 | export -f travis_time_finish 34 | export -f travis_wait 35 | export -f travis_jigger 36 | 37 | function start_section() { 38 | travis_fold start "$1" 39 | travis_time_start 40 | echo -e "${PURPLE}${1}${NC}: $2${NC}" 41 | echo -e "${GRAY}-------------------------------------------------------------------${NC}" 42 | } 43 | 44 | function end_section() { 45 | echo -e "${GRAY}-------------------------------------------------------------------${NC}" 46 | travis_time_finish 47 | travis_fold end "$1" 48 | } 49 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sonosfet/index.rst: -------------------------------------------------------------------------------- 1 | SONOS cells 2 | ----------- 3 | 4 | The SKY130 process currently supports two SONOS flash memory cells: 5 | 6 | - The original cell is supported in the S8PFHD, S8PHRC and S8PFN-20 technology options, with operating temperatures from -55°C to +155°C 7 | - The “star” cell is supported in the S8PHIRS technology option. Its cell size is approximately 25% smaller than the original cell, but its temperature range is restricted to -40°C to +125°C. 8 | 9 | Spice models for the memory cells exist for multiple conditions: 10 | 11 | 12 | .. include:: special_sonosfet-table0.rst 13 | 14 | 15 | 16 | Program and Erase characteristics are described in more detail in the ***S8 Nonvolatile Technology Spec*** (001-08712), and summarized below: 17 | 18 | 19 | .. include:: special_sonosfet-table1.rst 20 | 21 | 22 | 23 | Endurance behavior is illustrated below (100K cycles guaranteed): 24 | 25 | |sonos-erase-program| 26 | 27 | Data retention behavior is shown below at 85C\ |sonos-data-retention| 28 | 29 | E-test parameters are summarized below for both original and star cells: 30 | 31 | 32 | .. include:: special_sonosfet-table2.rst 33 | 34 | 35 | 36 | The schematic for the 2-T SONOS memory cell is shown below: 37 | 38 | |schematic-sonos-cell| 39 | 40 | The cross-section of the 2-T SONOS cell is shown below. 41 | 42 | |cross-section-sonos-cell| 43 | 44 | .. |sonos-erase-program| image:: sonos-erase-program.svg 45 | .. |sonos-data-retention| image:: sonos-data-retention.svg 46 | .. |schematic-sonos-cell| image:: schematic-sonos-cell.svg 47 | .. |cross-section-sonos-cell| image:: cross-section-sonos-cell.svg 48 | 49 | -------------------------------------------------------------------------------- /docs/rules/device-details/pnp_05v0/index.rst: -------------------------------------------------------------------------------- 1 | Bipolar PNP transistor 2 | ---------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__pnp_05v5` 8 | - Model Names: :model:`sky130_fd_pr__pnp_05v5`, :model:`sky130_fd_pr__pnp_05v5` 9 | 10 | Operating regime where SPICE models are valid 11 | 12 | - :math:`|V_{CE}| = 0` to 5.0V 13 | - :math:`|V_{BE}| = 0` to 5.0V 14 | - :math:`I_{CE} = 0.01` to 10 µA/µm\ :sup:`2` 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The SKY130 process offer a “free” PNP device, which utilizes the substrate as the collector. This device is not independently optimized, and can be used in forward-active mode. The following sizes of PNP are available: 20 | 21 | - ungated device with emitter 0.68 x 0.68 (A=0.4624 µm\ :sup:`2`) 22 | - ungated device with emitter 3.4 x 3.4 (A=11.56 µm\ :sup:`2`) 23 | 24 | Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. 25 | 26 | E-test specs for these devices are shown in the table below: 27 | 28 | 29 | .. include:: pnp_05v0-table0.rst 30 | 31 | 32 | 33 | Symbols for the :model:`sky130_fd_pr__pnp_05v5` is shown below 34 | 35 | |symbol-pnp_05v0-a| |symbol-pnp_05v0-b| 36 | 37 | The cross-section of the :model:`sky130_fd_pr__pnp_05v5` is shown below. 38 | 39 | No deep n-well exists in this device; the collector is the substrate. 40 | 41 | |cross-section-pnp_05v0| 42 | 43 | .. |symbol-pnp_05v0-a| image:: symbol-pnp_05v0-a.svg 44 | .. |symbol-pnp_05v0-b| image:: symbol-pnp_05v0-b.svg 45 | .. |cross-section-pnp_05v0| image:: cross-section-pnp_05v0.svg 46 | 47 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_01v8/nfet_01v8-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNL 31 | - 7/8 32 | - V 33 | - 0.538 34 | - 0.520 35 | - 0.557 36 | - 0.513 37 | - 0.564 38 | - 0.541 39 | - 0.515 40 | - 0.567 41 | 42 | * - VTXNN42 43 | - 0.42/1 44 | - V 45 | - 0.550 46 | - 0.522 47 | - 0.578 48 | - 0.510 49 | - 0.590 50 | - 0.550 51 | - 0.510 52 | - 0.590 53 | 54 | * - VTXNS15 55 | - 7/0.15 56 | - V 57 | - 0.645 58 | - 0.615 59 | - 0.677 60 | - 0.603 61 | - 0.689 62 | - 0.700 63 | - 0.661 64 | - 0.739 65 | 66 | * - VTSNSN15 67 | - 0.42/0.15 68 | - V 69 | - 0.738 70 | - 0.659 71 | - 0.818 72 | - 0.625 73 | - 0.852 74 | - 0.738 75 | - 0.625 76 | - 0.852 77 | 78 | * - IDSNS15 79 | - 7/0.15 80 | - mA 81 | - 3.512 82 | - 3.945 83 | - 3.078 84 | - 3.041 85 | - 3.983 86 | - 3.510 87 | - 3.039 88 | - 3.981 89 | 90 | * - ILKN15 91 | - 7/0.15 92 | - LOG A 93 | - Max = -10.25 94 | - -11.31 95 | - -18 96 | - -10.69 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_g5v0d10v5/nfet_g5v0d10v5-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Param 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNLH 31 | - 7/8 32 | - V 33 | - 0.811 34 | - 0.780 35 | - 0.843 36 | - 0.856 37 | - 0.767 38 | - 0.811 39 | - 0.767 40 | - 0.856 41 | 42 | * - VTXNN42H 43 | - 0.42/20 44 | - V 45 | - 0.813 46 | - 0.764 47 | - 0.862 48 | - 0.883 49 | - 0.743 50 | - 0.813 51 | - 0.743 52 | - 0.883 53 | 54 | * - VTXNS50H 55 | - 7/0.50 56 | - V 57 | - 0.822 58 | - 0.744 59 | - 0.899 60 | - 0.933 61 | - 0.711 62 | - 0.822 63 | - 0.711 64 | - 0.933 65 | 66 | * - VTXNSN50H 67 | - 0.42/0.50 68 | - V 69 | - 0.781 70 | - 0.672 71 | - 0.891 72 | - 0.937 73 | - 0.625 74 | - 0.781 75 | - 0.625 76 | - 0.937 77 | 78 | * - IDSNS50H 79 | - 7/0.50 80 | - mA 81 | - 12.1 82 | - 13.0 83 | - 11.2 84 | - 11.1 85 | - 13.1 86 | - 12.1 87 | - 11.1 88 | - 13.1 89 | 90 | * - ILKN50H 91 | - 7/0.50 92 | - LOG A 93 | - Max = -10.6 94 | - -12.3 95 | - -18 96 | - -10.9 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /.github/kokoro/steps/hostinfo.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright 2020 Regents of the University of California 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # 18 | # SPDX-License-Identifier: Apache-2.0 19 | 20 | set -e 21 | 22 | echo 23 | echo "========================================" 24 | echo "Host Environment" 25 | echo "----------------------------------------" 26 | export 27 | echo "----------------------------------------" 28 | 29 | echo 30 | echo "========================================" 31 | echo "Host CPU" 32 | echo "----------------------------------------" 33 | export CORES=$(nproc --all) 34 | echo "Cores: $CORES" 35 | echo 36 | echo "Memory" 37 | echo "----------------------------------------" 38 | cat /proc/meminfo 39 | echo "----------------------------------------" 40 | export MEM_GB=$(($(awk '/MemTotal/ {print $2}' /proc/meminfo)/(1024*1024))) 41 | echo "Memory (GB): $CORES" 42 | export MEM_CORES=$(($MEM_GB/4)) 43 | 44 | echo 45 | echo "========================================" 46 | echo "Package version" 47 | echo "----------------------------------------" 48 | set -x 49 | gcc --version 50 | set +x 51 | echo "----------------------------------------" 52 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_01v8_lvt/nfet_01v8_lvt-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNLL 31 | - 7/8 32 | - V 33 | - 0.434 34 | - 0.417 35 | - 0.452 36 | - 0.459 37 | - 0.410 38 | - 0.440 39 | - 0.415 40 | - 0.465 41 | 42 | * - VTXNN42L 43 | - 0.42/1 44 | - V 45 | - 0.485 46 | - 0.453 47 | - 0.516 48 | - 0.530 49 | - 0.440 50 | - 0.485 51 | - 0.440 52 | - 0.530 53 | 54 | * - VTXNS15L 55 | - 7/0.15 56 | - V 57 | - 0.611 58 | - 0.573 59 | - 0.65 60 | - 0.666 61 | - 0.556 62 | - 0.611 63 | - 0.556 64 | - 0.666 65 | 66 | * - VTXNSN15L 67 | - 0.42/0.15 68 | - V 69 | - 0.640 70 | - 0.562 71 | - 0.717 72 | - 0.750 73 | - 0.529 74 | - 0.640 75 | - 0.529 76 | - 0.750 77 | 78 | * - IDSNS15L 79 | - 7/0.15 80 | - mA 81 | - 4.010 82 | - 4.453 83 | - 3.567 84 | - 3.529 85 | - 4.491 86 | - 4.008 87 | - 3.527 88 | - 4.489 89 | 90 | * - ILKN15L 91 | - 7/0.15 92 | - LOG A 93 | - Max = -9.53 94 | - -10.73 95 | - -18 96 | - -9.54 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_g5v0d10v5/pfet_g5v0d10v5-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Param 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXPLH 31 | - 7/8 32 | - V 33 | - -1.027 34 | - -0.971 35 | - -1.083 36 | - -0.947 37 | - -1.107 38 | - -1.027 39 | - -1.107 40 | - -0.947 41 | 42 | * - VTXPN42H 43 | - 0.42/20 44 | - V 45 | - -0.933 46 | - -0.886 47 | - -0.979 48 | - -0.867 49 | - -0.998 50 | - -0.93 51 | - -1.00 52 | - -0.87 53 | 54 | * - VTXPS50H 55 | - 7/0.50 56 | - V 57 | - -0.956 58 | - -0.889 59 | - -1.022 60 | - -0.861 61 | - -1.05 62 | - -0.954 63 | - -1.049 64 | - -0.859 65 | 66 | * - VTXPSN50H 67 | - 0.42/0.50 68 | - V 69 | - -0.832 70 | - -0.737 71 | - -0.927 72 | - -0.697 73 | - -0.968 74 | - -0.831 75 | - -0.967 76 | - -0.695 77 | 78 | * - IDSPS50H 79 | - 7/0.50 80 | - mA 81 | - 7.02 82 | - 7.75 83 | - 6.30 84 | - 6.24 85 | - 7.809 86 | - 6.83 87 | - 6.07 88 | - 7.59 89 | 90 | * - ILKPS50H 91 | - 7/0.50 92 | - LOG A 93 | - Max = -10.0 94 | - -10.6 95 | - -18 96 | - -10 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8/pfet_01v8-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXPLS 31 | - 7/8 32 | - V 33 | - -1.050 34 | - -1.025 35 | - -1.075 36 | - -1.014 37 | - -1.086 38 | - -1.050 39 | - -1.086 40 | - -1.014 41 | 42 | * - VTXPN42S 43 | - 0.42/8 44 | - V 45 | - -0.941 46 | - -0.910 47 | - -0.960 48 | - -0.895 49 | - -0.983 50 | - -0.941 51 | - -0.985 52 | - -0.895 53 | 54 | * - VTXPS15S 55 | - 7/0.15 56 | - V 57 | - -0.781 58 | - -0.728 59 | - -0.835 60 | - -0.705 61 | - -0.858 62 | - -0.781 63 | - -0.858 64 | - -0.705 65 | 66 | * - VTXPSN15S 67 | - 0.42/0.15 68 | - V 69 | - -0.705 70 | - -0.599 71 | - -0.811 72 | - -0.554 73 | - -0.856 74 | - -0.705 75 | - -0.856 76 | - -0.554 77 | 78 | * - IDSPS15S 79 | - 7/0.15 80 | - mA 81 | - 1.347 82 | - 1.742 83 | - 0.952 84 | - 0.917 85 | - 1.777 86 | - 1.347 87 | - 0.917 88 | - 1.777 89 | 90 | * - ILKP15S 91 | - 7/0.15 92 | - LOG A 93 | - Max = -7.58 94 | - -10.09 95 | - -18 96 | - -7.58 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8_hvt/pfet_01v8_hvt-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXPL 31 | - 7/8 32 | - V 33 | - -1.107 34 | - -1.079 35 | - -1.124 36 | - -1.067 37 | - -1.141 38 | - -1.107 39 | - -1.141 40 | - -1.067 41 | 42 | * - VTXPN42 43 | - 0.42/8 44 | - V 45 | - -1.013 46 | - -0.974 47 | - -1.049 48 | - -0.959 49 | - -1.056 50 | - -1.023 51 | - -1.056 52 | - -0.959 53 | 54 | * - VTXPS15 55 | - 7/0.15 56 | - V 57 | - -0.888 58 | - -0.836 59 | - -0.940 60 | - -0.814 61 | - -0.962 62 | - -0.888 63 | - -0.963 64 | - -0.814 65 | 66 | * - VTXPSN15 67 | - 0.42/0.15 68 | - V 69 | - -0.819 70 | - -0.720 71 | - -0.918 72 | - -0.678 73 | - -0.951 74 | - -0.819 75 | - -0.951 76 | - -0.678 77 | 78 | * - IDSPS15 79 | - 7/0.15 80 | - mA 81 | - 1.003 82 | - 1.285 83 | - 0.721 84 | - 1.309 85 | - 0.697 86 | - 1.003 87 | - 0.697 88 | - 1.309 89 | 90 | * - ILKP15 91 | - 7/0.15 92 | - LOG A 93 | - Max = -10.7 94 | - -12 95 | - -18 96 | - -10.787 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_01v8_lvt/pfet_01v8_lvt-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTCPLL 31 | - 7/8 32 | - V 33 | - -0.651 34 | - -0.558 35 | - -0.744 36 | - -0.518 37 | - -0.784 38 | - -0.651 39 | - -0.785 40 | - -0.518 41 | 42 | * - VTCPN42L 43 | - 0.42/8 44 | - V 45 | - -0.630 46 | - -0.527 47 | - -0.733 48 | - -0.483 49 | - -0.777 50 | - -0.630 51 | - -1.042 52 | - -0.845 53 | 54 | * - VTCPS35L 55 | - 7/0.35 56 | - V 57 | - -0.533 58 | - -0.428 59 | - -0.638 60 | - -0.384 61 | - -0.683 62 | - -0.533 63 | - -0.683 64 | - -0.384 65 | 66 | * - VTCPSN35L 67 | - 0.42/0.35 68 | - V 69 | - -0.504 70 | - -0.373 71 | - -0.636 72 | - -0.316 73 | - -0.693 74 | - -8.505 75 | - -0.693 76 | - -0.316 77 | 78 | * - IDSPS35L 79 | - 7/0.35 80 | - mA 81 | - 1.22 82 | - 1.42 83 | - 1.02 84 | - 1.44 85 | - 1.00 86 | - 1.22 87 | - 1.00 88 | - 1.44 89 | 90 | * - ILKP35L 91 | - 7/0.35 92 | - LOG A 93 | - Max = -5.14 94 | - -6.671 95 | - -18 96 | - -5.144 97 | - 98 | - 99 | - 100 | - 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/esd_nfet/esd_nfet-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Param 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - IDSNESDHVS55 31 | - 21.5/0.55 32 | - mA 33 | - 12.172 34 | - 13.073 35 | - 11.277 36 | - 13.144 37 | - 11.207 38 | - 11.46 39 | - 10.57 40 | - 12.35 41 | 42 | * - ILKNESDHVS55 43 | - 21.5/0.55 44 | - LOG A 45 | - Max = -10.8 46 | - -12.49 47 | - -15 48 | - -11.21 49 | - 50 | - 51 | - 52 | - 53 | 54 | * - VTXNESDHVS55 55 | - 21.5/0.55 56 | - V 57 | - 0.817 58 | - 0.776 59 | - 0.858 60 | - 0.876 61 | - 0.758 62 | - 0.812 63 | - 0.752 64 | - 0.871 65 | 66 | * - IDSNESDLVS 67 | - 20.35/0.165 68 | - mA 69 | - 9.954 70 | - 11.027 71 | - 8.877 72 | - 11.055 73 | - 8.84 74 | - 8.145 75 | - 7.216 76 | - 9.075 77 | 78 | * - ILKNESDLVS 79 | - 20.35/0.165 80 | - LOG A 81 | - Max = -10.13 82 | - -10.85 83 | - -12.15 84 | - -10.15 85 | - 86 | - 87 | - 88 | - 89 | 90 | * - VTXNESDLVS 91 | - 20.35/0.165 92 | - V 93 | - 0.669 94 | - 0.621 95 | - 0.715 96 | - 0.737 97 | - 0.599 98 | - 0.6416 99 | - 0.5706 100 | - 0.7125 101 | 102 | -------------------------------------------------------------------------------- /docs/rules/device-details/esd_nfet/index.rst: -------------------------------------------------------------------------------- 1 | ESD NMOS FET 2 | ------------ 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 8 | - Model Name: :model:`sky130_fd_pr__esd_nfet_01v8`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` 9 | 10 | Operating Voltages where SPICE models are valid 11 | 12 | - :math:`V_{DS} = 0` to 11.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`) 13 | - :math:`V_{GS} = 0` to 5.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`) 14 | - :math:`V_{BS} = 0` to -5.5V, (:model:`sky130_fd_pr__nfet_g5v0d10v5`), +0.3 to -5.5V (:model:`sky130_fd_pr__nfet_05v0_nvt`), 0 to -1.95V (:model:`sky130_fd_pr__nfet_01v8*`) 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The ESD FET’s differ from the regular NMOS devices in several aspects, most notably: 20 | 21 | - Increased isolation spacing from contacts to surrounding STI 22 | - Increased drain contact-to-gate spacing 23 | - Placement of n-well under the drain contacts 24 | 25 | Major model output parameters are shown below and compared against the EDR (e-test) specs 26 | 27 | 28 | .. include:: esd_nfet-table0.rst 29 | 30 | 31 | 32 | The symbols of the :model:`sky130_fd_pr__esd_nfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` (ESD NMOS FET) are shown below: 33 | 34 | |symbol-esd_nfet_g5v0d10v5| |symbol-esd_nfet_g5v0d10v5_nvt| 35 | 36 | The cross-section of the ESD NMOS FET is shown below. 37 | 38 | |cross-section-esd_nfet| 39 | 40 | .. |symbol-esd_nfet_g5v0d10v5| image:: symbol-esd_nfet_g5v0d10v5.svg 41 | .. |symbol-esd_nfet_g5v0d10v5_nvt| image:: symbol-esd_nfet_g5v0d10v5_nvt.svg 42 | .. |cross-section-esd_nfet| image:: cross-section-esd_nfet.svg 43 | 44 | -------------------------------------------------------------------------------- /.github/kokoro/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # -*- coding: utf-8 -*- 3 | # 4 | # Copyright 2020 Regents of the University of California 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # 18 | # SPDX-License-Identifier: Apache-2.0 19 | 20 | set -e 21 | 22 | CALLED=$_ 23 | [[ "${BASH_SOURCE[0]}" != "${0}" ]] && SOURCED=1 || SOURCED=0 24 | 25 | SCRIPT_SRC="$(realpath ${BASH_SOURCE[0]})" 26 | SCRIPT_DIR="$(dirname "${SCRIPT_SRC}")" 27 | 28 | export PATH="/usr/sbin:/usr/bin:/sbin:/bin" 29 | 30 | cd github/$KOKORO_DIR 31 | 32 | . $SCRIPT_DIR/steps/auth.sh 33 | . $SCRIPT_DIR/steps/git.sh 34 | . $SCRIPT_DIR/steps/hostsetup.sh 35 | . $SCRIPT_DIR/steps/hostinfo.sh 36 | 37 | set -e 38 | 39 | echo 40 | echo "========================================" 41 | echo "Setting up build environment" 42 | echo "----------------------------------------" 43 | make env 44 | echo "----------------------------------------" 45 | 46 | echo 47 | echo "========================================" 48 | echo "Checkout all the submodules" 49 | echo "----------------------------------------" 50 | DOWNLOAD_JOBS=$(($CORES*2)) 51 | git submodule update --init --jobs $DOWNLOAD_JOBS 52 | 53 | echo 54 | echo "========================================" 55 | echo "Build the timing libraries" 56 | echo "----------------------------------------" 57 | make -j timing 58 | -------------------------------------------------------------------------------- /docs/versioning.rst: -------------------------------------------------------------------------------- 1 | .. include:: common.inc 2 | 3 | Versioning Information 4 | ====================== 5 | 6 | Current Status 7 | -------------- 8 | 9 | .. include:: status.rst 10 | :start-after: current_status_text 11 | 12 | Version Number Format 13 | --------------------- 14 | 15 | Version numbers for both the PDK and the supplied libraries are fully specified by a 3-digit version number followed by a git commit count and a git commit short hash. 16 | 17 | The 3-digit-number will be tagged in the associated git repository as ``vX.Y.Z`` and the fully specified value can be found by running |git-describe|_ tool inside the correct git repository. 18 | 19 | .. |git-describe| replace:: ``git describe`` 20 | .. _git-describe: https://git-scm.com/docs/git-describe 21 | 22 | The version number is broken down as ``vX.Y.Z-AAA-gHHHHH``; 23 | 24 | * The letter ``v``. 25 | 26 | * ``X`` = The "Milestone Release" Number 27 | 28 | * **0** indicates **"alpha"** level. The IP has **not** undergone full qualification. Parts of the IP **may be immature and untested**. 29 | 30 | * **1** indicates **"beta"** level. The IP has undergone qualification testing but has **not** been hardware verified. 31 | 32 | * **2** indicates **production** level. The IP has passed qualification testing and has been hardware verified. 33 | 34 | * ``Y`` = The "Major Release" Number 35 | 36 | * ``Z`` = The "Minor Release" Number 37 | 38 | * A single hyphen character ``-`` 39 | 40 | * ``AAA`` = The `git commit count `_ since the version number was tagged. 41 | 42 | * A single hyphen character followed by the letter g ``-g`` 43 | 44 | * ``HHHH`` = A `git commit short hash `_ which uniquely identifies a specific git commit inside the associated git repository. 45 | -------------------------------------------------------------------------------- /docs/rules/periphery/p046-mf_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (mf.1),Min. and max width of fuse,,0.800,µm 3 | (mf.2),Length of fuse,,7.200,µm 4 | (mf.3),Spacing between centers of adjacent fuses,,2.760,µm 5 | (mf.4),Spacing between center of fuse and fuse_metal (fuse shields are exempted),,3.300,µm 6 | (mf.5),Max. extension of fuse_metal beyond fuse boundary,,0.830, 7 | (mf.6),Spacing (no overlapping) between fuse center and Metal1,,3.300,µm 8 | (mf.7),Spacing (no overlapping) between fuse center and LI,,3.300,µm 9 | (mf.8),Spacing (no overlapping) between fuse center and poly,,2.660,µm 10 | (mf.9),Spacing (no overlapping) between fuse center and tap,,2.640,µm 11 | (mf.10),Spacing (no overlapping) between fuse center and diff,,3.250,µm 12 | (mf.11),Spacing (no overlapping) between fuse center and nwell,,3.320,µm 13 | (mf.12),Size of fuse_shield,,0.5x2.4,µm 14 | (mf.13),Min. spacing of center of fuse to fuse_shield,,2.200,µm 15 | (mf.14),Max. spacing of center of fuse to fuse_shield,,3.300,µm 16 | (mf.15),"Fuse_shields are only placed between periphery metal (i.e., without fuse:dg) and non-isolated edges of fuse as defined by mf.16",,, 17 | (mf.16),The edge of a fuse is considered non-isolated if wider than or equal to mf.2 and spaced to fuse_metal by less than …,,4.000, 18 | (mf.17),Offset between fuse_shields center and fuse center,NC,0.000, 19 | (mf.18),Min and max space between fuse_shield and fuse_metal (opposite edges). Rule checked within 1 gridpoint.,,0.600,µm 20 | (mf.19),Spacing (no overlapping) between fuse center and Metal2,,3.300,µm 21 | (mf.20),Only one fuse per metal line allowed,,, 22 | (mf.21),"Min spacing , no overlap, between metal3 and fuse center",,3.300,µm 23 | (mf.22),Min spacing between fuse_contact to fuse_contact,,1.960,µm 24 | (mf.23),Spacing (no overlapping) between fuse center and Metal4,,N/A,N/A 25 | (mf.24),Spacing (no overlapping) between fuse center and Metal5,,3.300,µm 26 | -------------------------------------------------------------------------------- /docs/rules/antenna/table-Ie-antenna-rules-s8p.csv: -------------------------------------------------------------------------------- 1 | Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*),,,,,, 2 | ,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,, 3 | (ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus 4 | ,,,,,, 5 | .poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a 6 | .licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a 7 | .li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a 8 | .mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a 9 | .met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200 10 | .via.1,Via (via area/gate area),Horizontal,,6,36,n/a 11 | .met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200 12 | .via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a 13 | .met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.800,400,400,2200 14 | via3.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a 15 | met4.1,Met4 (met4 perimeter area/gate area),Vertical,0.800,400,400,2200 16 | via4.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a 17 | waffle_chip,Met4 (met4 perimeter area/gate area),Vertical,2.000,400,400,2200 18 | .ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,, 19 | Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,, 20 | ,,,,,, 21 | "Max length of Poly (approx, assumes min width)",,135,,n/a,, 22 | Max number of Licons,,103,,n/a,, 23 | "Max length of LI (approx, assumes min width)",,370,,2620,, 24 | Max number of Mcon,,103,,726,, 25 | "Max length of Met1 (approx, assumes min width)",,570,,4280,, 26 | Max number of Via,,266,,1866,, 27 | "Max length of Met2 (approx, assumes min width)",,570,,4280,, 28 | Max number of Via2,,150,,1050,, 29 | "Max length of Met3 (approx, assumes min width)",,245,,1870,, 30 | Max number of Via3,,150,,1050,, 31 | "Max length of Met4 (approx, assumes min width)",,245,,1870,, 32 | Max number of Via4,,9,,65,, 33 | "Max length of Met5 (approx, assumes min width)",,95,,740,, 34 | -------------------------------------------------------------------------------- /docs/rules/layers.rst: -------------------------------------------------------------------------------- 1 | Layers Reference 2 | ================ 3 | 4 | Layers Definitions 5 | ------------------ 6 | 7 | .. csv-table:: Table C3: Device, LVS and other CAD definitions 8 | :file: layers/table-c3-device-lvs-other.csv 9 | :header-rows: 1 10 | :stub-columns: 1 11 | 12 | Auxiliary Layers 13 | ---------------- 14 | 15 | .. csv-table:: Table C4a: Purpose layer description in LSW window and Auxiliary Layers 16 | :file: layers/table-c4a-layer-description.csv 17 | :header-rows: 1 18 | :stub-columns: 1 19 | 20 | .. csv-table:: Table C4b: Purpose layer description in LSW window and Auxiliary Layers 21 | :file: layers/table-c4b-layer-description.csv 22 | :header-rows: 1 23 | :stub-columns: 1 24 | 25 | Devices and Layout vs Schematic (LVS) Information 26 | ------------------------------------------------- 27 | 28 | .. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS) 29 | :file: layers/table-c4b-layer-description.csv 30 | :header-rows: 1 31 | :stub-columns: 1 32 | 33 | .. include:: layers/table-f2a-lvs-key.rst 34 | 35 | 36 | .. csv-table:: Table F2b: Mask Generation table 37 | :file: layers/table-f2b-mask.tsv 38 | :delim: U+0009 39 | :header-rows: 1 40 | :stub-columns: 1 41 | 42 | .. include:: layers/table-f2b-mask-key.rst 43 | 44 | 45 | GDS Layers Information 46 | ---------------------- 47 | 48 | The :download:`gds_layers.csv file <./gds_layers.csv>` provides a raw list of the 49 | layers used in the process with name, description and the GDS layer and data type. 50 | 51 | .. csv-table:: Table - GDS Layers 52 | :file: gds_layers.csv 53 | :header-rows: 1 54 | :stub-columns: 1 55 | :widths: 10, 15, 10, 75 56 | 57 | Device and Layout vs. Schematic 58 | =============================== 59 | 60 | .. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS) 61 | :file: layers/table-f2a-lvs.tsv 62 | :delim: U+0009 63 | :header-rows: 1 64 | :stub-columns: 1 65 | 66 | -------------------------------------------------------------------------------- /docs/rules/antenna/table-Ig-antenna-rules-s8p12.csv: -------------------------------------------------------------------------------- 1 | Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*),,,,,, 2 | ,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,, 3 | (ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus 4 | ,,,,,, 5 | .poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a 6 | .licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a 7 | .li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a 8 | .mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a 9 | .met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200 10 | .via.1,Via (via area/gate area),Horizontal,,6,36,n/a 11 | .met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200 12 | .via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a 13 | .met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.800,400,400,2200 14 | via3.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a 15 | met4.1,Met4 (met4 perimeter area/gate area),Vertical,0.800,400,400,2200 16 | via4.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a 17 | met5.1,Met4 (met4 perimeter area/gate area),Vertical,1.200,400,400,2200 18 | .ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,, 19 | Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,, 20 | ,,,,,, 21 | "Max length of Poly (approx, assumes min width)",,135,,n/a,, 22 | Max number of Licons,,103,,n/a,, 23 | "Max length of LI (approx, assumes min width)",,370,,2620,, 24 | Max number of Mcon,,103,,726,, 25 | "Max length of Met1 (approx, assumes min width)",,570,,4280,, 26 | Max number of Via,,266,,1866,, 27 | "Max length of Met2 (approx, assumes min width)",,570,,4280,, 28 | Max number of Via2,,150,,1050,, 29 | "Max length of Met3 (approx, assumes min width)",,245,,1870,, 30 | Max number of Via3,,150,,1050,, 31 | "Max length of Met4 (approx, assumes min width)",,245,,1870,, 32 | Max number of Via4,,9,,65,, 33 | "Max length of Met5 (approx, assumes min width)",,165,,1240,, 34 | -------------------------------------------------------------------------------- /docs/rules/periphery/p039-via_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (via.1a),Min and max L and W of via outside :drc_tag:`areaid.mt`,AL,0.150,µm 3 | (via.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.150um, 0.230um and 0.280um",AL,, 4 | (via.2),Spacing of via to via,AL,0.170,µm 5 | (via.3),Only min. square vias are allowed except die seal ring where vias are (Via CD)*L,,0.2*L, 6 | (via.4a),0.150 µm Via must be enclosed by Met1 by at least …,,0.055,µm 7 | (via.4b),"Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 by atleast",AL,0.030,µm 8 | (via.4c),"Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 by atleast",AL,0.000,µm 9 | (via.5a),0.150 µm Via must be enclosed by Met1 on one of two adjacent sides by at least …,,0.085,µm 10 | (via.5b),"Inside :drc_tag:`areaid.mt`, 0.230 µm Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.060,µm 11 | (via.5c),"Inside :drc_tag:`areaid.mt`, 0.280 µm Via must be enclosed by met1 on one of two adjacent sides by at least …",AL,0.000,µm 12 | (via.11),Min and max L and W of via outside :drc_tag:`areaid.mt`,CU,0.180,µm 13 | (via.12),Min spacing between vias,CU,0.130,µm 14 | (via.13),Max of 5 vias within …,CU,0.350,µm 15 | (via.14),0.180 µm Via must be enclosed by parallel edges of Met1 by at least …,CU,0.040,µm 16 | (via.irdrop.1),"For 1 <= n <= 2 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm 17 | (via.irdrop.2),"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6,µm 18 | (via.irdrop.3),"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8,µm 19 | (via.irdrop.4),"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9,µm 20 | (via.14a),0.180 µm Via must be enclosed by 45 deg edges of Met1 by at least …,CU,0.037,deg µm 21 | -------------------------------------------------------------------------------- /docs/_static/favicon/safari-pinned-tab.svg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/fixup-headers.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # Copyright 2020 SkyWater PDK Authors 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # https://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | # SPDX-License-Identifier: Apache-2.0 17 | 18 | 19 | import os.path 20 | import sys 21 | import tempfile 22 | from collections import defaultdict 23 | 24 | 25 | def count_chars(l): 26 | o = defaultdict(lambda: 0) 27 | for i in l: 28 | o[i] += 1 29 | if '\n' in o: 30 | del o['\n'] 31 | return dict(o) 32 | 33 | 34 | def main(argv): 35 | assert len(argv) == 1, argv 36 | 37 | fname = argv[0] 38 | assert fname.endswith('.rst'), fname 39 | assert os.path.exists(fname), fname 40 | 41 | output = ['',] 42 | with open(fname) as f: 43 | for l in f: 44 | output.append(l) 45 | c = count_chars(l) 46 | if len(c) != 1: 47 | continue 48 | 49 | header = list(c.keys())[0] 50 | if header not in ['-', '=', '+', '~']: 51 | print("Possible header?", repr(l)) 52 | continue 53 | 54 | lastline = output[-2] 55 | 56 | if len(lastline) <= 4: 57 | continue 58 | 59 | oheader = (header * (len(lastline)-1))+'\n' 60 | output[-1] = oheader 61 | 62 | with open(fname, 'w') as f: 63 | f.write("".join(output[1:])) 64 | 65 | return 0 66 | 67 | 68 | if __name__ == "__main__": 69 | sys.exit(main(sys.argv[1:])) 70 | -------------------------------------------------------------------------------- /docs/rules/periphery/p041-via2_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (via2.X.1),Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flow and met2/capm to met3 in the SKY130DI* flow.,,, 3 | (via2.1a),Min and max L and W of via2 (except for rule via2.1b/1c/1d/1e/1f),AL,0.200,µm 4 | (via2.1b),"Three sizes of square Vias allowed inside areaid:mt: 0.280um, 1.2 um and 1.5 um",AL,N/A,N/A 5 | (via2.1c),Two sizes of square Vias allowed inside areaid:mt: 1.2 um and 1.5 um,AL,N/A,N/A 6 | (via2.1d),"Four sizes of square Vias allowed inside areaid:mt: 0.2um, 0.280um, 1.2 um and 1.5 um",AL,, 7 | (via2.1e),"Three sizes of square Vias allowed inside areaid:mt: 0.8um, 1.2 um and 1.5 um",AL,N/A,N/A 8 | (via2.1f),Two sizes of square Vias allowed outside areaid:mt: 0.8um and 1.2 um,AL,N/A,N/A 9 | (via2.2),Spacing of via2 to via2,AL,0.200,µm 10 | (via2.3),Only min. square via2s are allowed except die seal ring where via2s are (Via2 CD)*L,AL,0.2*L, 11 | (via2.4),Via2 must be enclosed by Met2 by at least …,AL,0.040,µm 12 | (via2.4a),"Inside :drc_tag:`areaid.mt`, 1.5 µm Via2 must be enclosed by met2 by atleast",,0.140,µm 13 | (via2.5),Via2 must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085,µm 14 | (via2.11),Min and max L and W of via2,CU,0.210,µm 15 | (via2.12),Min spacing between via2's,CU,0.180,µm 16 | (via2.13),Min spacing between via2 rows,CU,0.200,µm 17 | (via2.14),Via2 must be enclosed by met2 by atleast,CU,0.035,µm 18 | (via2.irdrop.1),"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0,µm 19 | (via2.irdrop.2),"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6,µm 20 | (via2.irdrop.3),"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.79,µm 21 | (via2.irdrop.4),"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9,µm 22 | -------------------------------------------------------------------------------- /docs/rules/layers/table-f2a-lvs-key.rst: -------------------------------------------------------------------------------- 1 | Explanation of symbols: 2 | 3 | * ``-`` = Layer illegal for the device 4 | * ``+`` = Layer allowed to overlap 5 | * ``D`` = DRAWN indicates that a layer is drawn by Design. 6 | * ``C`` = CREATED indicates that the layer is only created by CAD. 7 | 8 | .. rubric:: Footnotes 9 | 10 | .. [#f1] Low vt needs to be set on the schematic element 11 | .. [#f2] Ncm is drawn inside core. Otherwise it is created in periphery. See rules ncm.X.* for details 12 | .. [#f3] Drawn over half of device 13 | .. [#f4] ASSUMPTION: FET models will be same regardless of backend flow 14 | .. [#f5] The 2 core FETs and flash npass must have a poly.ml label with their model name. 15 | .. [#f6] over the drain 16 | .. [#f7] over the source 17 | .. [#f8] Information for RCX 18 | .. [#f9] Uses a black box for LVS. This is a fixed layout; Use symbol provided by modeling group 19 | .. [#f10] LVS will check that phighvt inside areaid.ce overlaps ncm 20 | .. [#f11] The default model is sonos_e, sonos_de and nvssonos_e. If sonos_p, sonos_dp and nvssonos_p model are required, poly.ml must be used 21 | .. [#f12] The capacitor.dg is drawn 0.17um from the edge of the cell to be LVS clean 22 | .. [#f13] Devices are LVS'ed by cell name, m=1 per cell, fixed area and perimeter (see QHC-18) 23 | .. [#f14] (dnwell not (pwres or pnp or npn or areaid.en or areaid.de or areaid.po)) not nwell must have condiode text; Refer to VUN-104, 192 for condiode usage 24 | .. [#f15] Tech element is created by the user, no CAD supplied tech element 25 | .. [#f16] There are multiple configurations of the Cu inductor. The layers present in one configuration may not be drawn in the other configuration. Also rdl will not be routed over met5 cu inductor, not checkable by CAD flow. 26 | .. [#f17] Used for substrate noise isolation regions only 27 | .. [#f18] Either UHVI or areaid.low_vt should be drawn over the sturctures 28 | .. [#f19] Psub-Deep Nwell Diode must have condiode text "condiodeHvPsub"; CVA-596 29 | .. [#f20] mrp1 can't overlay capacitor.dg: exempted s8rf2_xcmvpp11p5x11p7_lim5shield from the rule 30 | -------------------------------------------------------------------------------- /docs/rules/wlcsp/amkor.csv: -------------------------------------------------------------------------------- 1 | Allowed pitch,,Supported flows,,Allowed pitch, 2 | 400 um,500 um, s8p-5r\ns8p-10r*\ns8pf-10r*\ns8pfn-20r*\ns8p12-10r*\ns8spf-10r*,,400 um,500 um 3 | (pi1.-.-),(pi1_500.-.-),1st polyimide layer for WLCSP,,, 4 | ,,Function: Opens over the pad openings; Allows RDL layer to connect to top metal,,, 5 | 1,1,Min width of pi1 (for parallel opposite edges),,35.00,35.00 6 | 2,2,Min spacing between pi1,,20.00,20.00 7 | 3,3,pi1 must be enclosed by pad by atleast,,7.50,7.50 8 | (rdl.-),(rdl_500.-),Re-distribution layer,,, 9 | ,,Function: Re-distribution layer connects the top metal from the customer to the bumps,,, 10 | 1,1,Min width of rdl (for parallel opposite edges),,10.00,10.00 11 | 2,2,min spacing between two rdl,,10.00,10.00 12 | 3,3,pi1 must be enclosed by rdl by atleast,,10.00,10.00 13 | (pi2.-.-),(pi2_500.-.-),2nd polyimide layer for WLCSP,,, 14 | ,,Function: 2nd polyimide layer acts as a via between RDL and UBM,,, 15 | 1,1,Min width of pi2 (for parallel opposite edges),,170.00,220.00 16 | 3,3,"Min spacing, no overlap, between pi1 and pi2",,25.00,25.00 17 | (ubm.-.-),(ubm_500.-.-),Under bump metal,,, 18 | ,,Function: Layer added underneath the bump balls,,, 19 | 1,1,Min width of ubm (for parallel opposite edges),,215.00,250.00 20 | 3,3,pi2 must be enclosed by ubm by atleast,,15.00,15.00 21 | 4,4,ubm must be enclosed by rdl by atleast,,10.00,10.00 22 | 5,5,"Min spacing, no overlap, between pi1 and ubm",,10.00,10.00 23 | 6,6,Min spacing between center of ubm and outer edge of the seal ring,,155.00,195.00 24 | (bump.-.-),(bump_500.-.-),Bump balls for WLCSP,,, 25 | ,,Function: WLCSP bump balls,,, 26 | 1,1,Min width of bump (for parallel opposite edges),,261.00,310.00 27 | 2,2,Min/Max pitch spacing between bump (center to center),,400.00,500.00 28 | 2a,2a,Min/Max pitch spacing between bump (center to center) across the scribe,NC,400.00,500.00 29 | 3,3,Min spacing between bump and outer edge of the seal ring,,25.00,25.00 30 | 4,4,Min size of Chip_extent overlapping bump.dg,,750 X 1000,1000 X 1000 31 | 5,5,Max size of Chip_extent overlapping bump.dg,,6800 X 6800,6800 X 6800 32 | -------------------------------------------------------------------------------- /docs/rules/device-details/special_sram/index.rst: -------------------------------------------------------------------------------- 1 | SRAM cells 2 | ---------- 3 | 4 | The SKY130 process currently supports only single-port SRAM’s, which are contained in hard-IP libraries. These cells are constructed with smaller design rules (Table 9), along with OPC (optical proximity correction) techniques, to achieve small memory cells. Use of the memory cells or their devices outside the specific IP is prohibited. The schematic for the SRAM is shown below in Figure 10. This cell is available in the S8 IP offerings and is monitored at e-test through the use of “pinned out” devices within the specific arrays. 5 | 6 | |figure-10-schematics-of-the-single-port-sram| 7 | 8 | **Figure 10. Schematics of the Single Port SRAM.** 9 | 10 | A Dual-Port SRAM is currently being designed using a similar approach. Compilers for the SP and DP SRAM’s will be available end-2019. 11 | 12 | Operating Voltages where SPICE models are valid 13 | 14 | - :math:`V_{DS} = 0` to 1.8V 15 | - :math:`V_{GS} = 0` to 1.8V 16 | - :math:`V_{BS} = 0` to -1.8V 17 | 18 | Details 19 | ~~~~~~~ 20 | 21 | N-pass FET (SRAM) 22 | ^^^^^^^^^^^^^^^^^ 23 | 24 | Spice Model Information 25 | ~~~~~~~~~~~~~~~~~~~~~~~ 26 | 27 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 28 | - Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_pass` 29 | 30 | 31 | .. include:: special_sram-table0.rst 32 | 33 | 34 | 35 | N-latch FET (SRAM) 36 | ^^^^^^^^^^^^^^^^^^ 37 | 38 | Spice Model Information 39 | ~~~~~~~~~~~~~~~~~~~~~~~ 40 | 41 | - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` 42 | - Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_latch` 43 | 44 | 45 | .. include:: special_sram-table1.rst 46 | 47 | 48 | 49 | P-latch FET (SRAM) 50 | ^^^^^^^^^^^^^^^^^^ 51 | 52 | Spice Model Information 53 | ~~~~~~~~~~~~~~~~~~~~~~~ 54 | 55 | - Cell Name: :cell:`sky130_fd_pr__pfet_01v8` 56 | - Model Name (SRAM): :model:`sky130_fd_pr__special_pfet_pass` 57 | 58 | 59 | .. include:: special_sram-table2.rst 60 | 61 | 62 | 63 | .. |figure-10-schematics-of-the-single-port-sram| image:: figure-10-schematics-of-the-single-port-sram.svg 64 | 65 | -------------------------------------------------------------------------------- /docs/rules/periphery/p044-m4_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (m4.-),"| Algorithm should flag errors, for met4, if ANY of the following is true: 3 | | An entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window. 4 | | 80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window. 5 | | 60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window. 6 | | 50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window. 7 | | 40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window. 8 | | 30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window. 9 | | Exclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,, 10 | (m4.1),Min width of met4,,0.300,µm 11 | (m4.2),Min spacing between two met4,,0.300,µm 12 | (m4.3),via3 must be enclosed by met4 by atleast,AL,0.065,µm 13 | (m4.4),Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A,N/A 14 | (m4.4a),Min area of met4,,0.240,µm² 15 | (m4.5a),Min. spacing of features attached to or extending from huge_met4 for a distance of up to 0.400 µm to metal4 (rule not checked over non-huge met4 features),,0.400,µm 16 | (m4.5b),Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400,µm 17 | (m4.7),Min area of meta4 holes,CU,0.200,µm² 18 | (m4.pd.1),Min MM4_oxide_Pattern_density,RR,0.7,\- 19 | (m4.pd.2a),Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm 20 | (m4.pd.2b),Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70, 21 | (m4.11),Max width of metal4,CU,10.000,µm 22 | (m4.12),Add slots and remove vias and contacts if wider than…..,CU,10.000, 23 | (m4.13),Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,CU,0.77,\- 24 | (m4.14),Met4 PD window size,CU,50.000,µm 25 | (m4.14a),Met4 PD window step,CU,25.000,µm 26 | (m4.15),Via3 must be enclosed by met4 by at least…,CU,0.060,µm 27 | (m4.16),Min enclosure of pad by met4,CU,0.850,µm 28 | -------------------------------------------------------------------------------- /docs/_static/logo/osu_logo.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 5 | 9 | 10 | 12 | 15 | 16 | 18 | 20 | 22 | 23 | 24 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /docs/rules/periphery/p040-m2_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (m2.-),"| Algorithm should flag errors, for met2, if ANY of the following is true: 3 | | An entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window. 4 | | 80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window. 5 | | 60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window. 6 | | 50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window. 7 | | 40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window. 8 | | 30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window. 9 | | Exclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,, 10 | (m2.1),Width of metal 2,,0.140,µm 11 | (m2.2),Spacing of metal 2 to metal 2,,0.140,µm 12 | (m2.3a),Min. spacing of features attached to or extending from huge_met2 for a distance of up to 0.280 µm to metal2 (rule not checked over non-huge met2 features),,0.280,µm 13 | (m2.3b),Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280,µm 14 | (m2.3c),"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145,µm 15 | (m2.4),Via must be enclosed by Met2 by at least …,P AL,0.055,µm 16 | (m2.5),Via must be enclosed by Met2 on one of two adjacent sides by at least …,AL,0.085,µm 17 | (m2.6),Min metal2 area,,0.0676,µm² 18 | (m2.7),Min area of metal2 holes,,0.140,µm² 19 | (m2.pd.1),Min MM2_oxide_Pattern_density,RR,0.7,\- 20 | (m2.pd.2a),Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm 21 | (m2.pd.2b),Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70, 22 | (m2.11),Max width of metal2,CU,4.000,µm 23 | (m2.12),Add slots and remove vias and contacts if met2 wider than…..,CU,3.200, 24 | (m2.13),Max pattern density (PD) of metal2,CU,0.77,\- 25 | (m2.14),Met2 PD window size,CU,50.000,µm 26 | (m2.14a),Met2 PD window step,CU,25.000,µm 27 | (m2.15),Via must be enclosed by met2 by at least…,CU,0.040,µm 28 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_g11v0d16v0/nfet_g11v0d16v0-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNVHV20P00P7D 31 | - 20/0.7 32 | - V 33 | - 0.743 34 | - 0.616 35 | - 0.87 36 | - 0.924 37 | - 0.562 38 | - 0.7423 39 | - 0.5612 40 | - 0.9234 41 | 42 | * - VTXNVHV20P02P2D 43 | - 20/2.2 44 | - V 45 | - 0.767 46 | - 0.661 47 | - 0.874 48 | - 0.919 49 | - 0.615 50 | - 0.7668 51 | - 0.6150 52 | - 0.9191 53 | 54 | * - IDSNVHV20P00P7D 55 | - 20/0.7 56 | - mA 57 | - 9.012 58 | - 11.337 59 | - 6.68 60 | - 11.542 61 | - 6.477 62 | - 8.969 63 | - 6.430 64 | - 11.51 65 | 66 | * - IDSNVHV20P02P2D 67 | - 20/2.2 68 | - mA 69 | - 4.444 70 | - 5.56 71 | - 3.329 72 | - 5.657 73 | - 3.232 74 | - 4.440 75 | - 3.232 76 | - 5.656 77 | 78 | * - RDSNVHV20P00P7D 79 | - 20/0.7 80 | - Ω 81 | - 457.3 82 | - 266.1 83 | - 819.4 84 | - 826.4 85 | - 269.6 86 | - 458.5 87 | - 270.3 88 | - 828.2 89 | 90 | * - RDSNVHV20P02P2D 91 | - 20/2.2 92 | - Ω 93 | - 702.8 94 | - 499.7 95 | - 1087.8 96 | - 1097.7 97 | - 498.7 98 | - 703.8 99 | - 499.3 100 | - 1099.0 101 | 102 | * - ILKNVHV20P00P7D 103 | - 20/0.7 104 | - LOG A 105 | - Max = -9.01 106 | - -11.35 107 | - -18 108 | - -9.05 109 | - 110 | - 111 | - 112 | - 113 | 114 | * - ILKNVHV20P00P7D 115 | - 20/2.2 116 | - LOG A 117 | - Max = -9.44 118 | - -11.50 119 | - -18 120 | - -9.50 121 | - 122 | - 123 | - 124 | - 125 | 126 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_g5v0d16v0/pfet_g5v0d16v0-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Param 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXPVHV20P00P66 31 | - 20/0.66 32 | - V 33 | - -1.105 34 | - -1.015 35 | - -1.196 36 | - -0.975 37 | - -1.235 38 | - -1.10 39 | - -1.24 40 | - -0.98 41 | 42 | * - VTXPVHV20P02P20 43 | - 20/2.2 44 | - V 45 | - -1.098 46 | - -1.006 47 | - -1.189 48 | - -0.967 49 | - -1.229 50 | - -1.10 51 | - -1.23 52 | - -0.97 53 | 54 | * - IDSPVHV20P00P66 55 | - 20/0.66 56 | - mA 57 | - 4.912 58 | - 6.258 59 | - 3.593 60 | - 6.393 61 | - 3.505 62 | - 4.911 63 | - 3.505 64 | - 6.393 65 | 66 | * - IDSPVHV20P02P20 67 | - 20/2.2 68 | - mA 69 | - 1.902 70 | - 2.403 71 | - 1.392 72 | - 2.448 73 | - 1.343 74 | - 1.902 75 | - 1.343 76 | - 2.448 77 | 78 | * - RDSPVHV20P00P66 79 | - 20/0.66 80 | - Ω 81 | - 754.8 82 | - 483.1 83 | - 1269.0 84 | - 1274.7 85 | - 481.6 86 | - 757.1 87 | - 482.9 88 | - 1279 89 | 90 | * - RDSPVHV20P02P20 91 | - 20/2.2 92 | - Ω 93 | - 1407 94 | - 1021 95 | - 2128 96 | - 2163 97 | - 1015 98 | - 1409 99 | - 1016 100 | - 2167 101 | 102 | * - ILKPVHV20P00P66 103 | - 20/0.66 104 | - LOG A 105 | - Max = -9.66 106 | - -13.20 107 | - -14.55 108 | - -9.77 109 | - 110 | - 111 | - 112 | - 113 | 114 | * - ILKPVHV20P02P20 115 | - 20/2.2 116 | - LOG A 117 | - Max = -10.07 118 | - -13.20 119 | - -14.41 120 | - -10.42 121 | - 122 | - 123 | - 124 | - 125 | 126 | -------------------------------------------------------------------------------- /docs/rules/device-details/npn_05v0/index.rst: -------------------------------------------------------------------------------- 1 | Bipolar NPN transistor 2 | ---------------------- 3 | 4 | Spice Model Information 5 | ~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | - Cell Name: :cell:`sky130_fd_pr__npn_05v5` 8 | - Model Names: :model:`sky130_fd_pr__npn_05v5`, :model:`sky130_fd_pr__npn_11v0` 9 | 10 | Operating regime where SPICE models are valid 11 | 12 | - :math:`|V_{CE}| = 0` to 5.0V 13 | - :math:`|V_{BE}| = 0` to 5.0V 14 | - :math:`I_{CE} = 0.01` to 10 µA/µm\ :sup:`2` 15 | 16 | Details 17 | ~~~~~~~ 18 | 19 | The SKY130 process offers “free” NPN devices. The NPN uses the deep n-well as the collector. The device is not optimized, and must be used in the forward-active mode. The following sizes of NPN’s are available: 20 | 21 | - ungated device with emitter 1.0 x 1.0 22 | - ungated device with emitter 1.0 x 2.0 23 | - poly-gated version with octagonal emitter of A = 1.97 µm\ :sup:`2` 24 | 25 | The :model:`sky130_fd_pr__npn_11v0` device has a poly gate placed between the emitter and base diffusions, to prevent carrier recombination at the STI edge and increase β. The poly gate is connected to the emitter terminal. 26 | 27 | Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. E-test specs for the NPN devices are shown in the table below: 28 | 29 | 30 | .. include:: npn_05v0-table0.rst 31 | 32 | 33 | 34 | Symbols for the :model:`sky130_fd_pr__npn_05v5` are shown below 35 | 36 | |symbol-npn_05v0-1| |symbol-npn_05v0-2| |symbol-npn_05v0-3| 37 | 38 | The cross-section of the :model:`sky130_fd_pr__npn_05v5` is shown below. 39 | 40 | |cross-section-npn_05v0| 41 | 42 | The cross-section of the :model:`sky130_fd_pr__npn_11v0` is shown below. The poly gate is tied to the emitter to prevent the parasitic MOSFET from turning on. 43 | 44 | |cross-section-npn_11v0| 45 | 46 | .. |symbol-npn_05v0-1| image:: symbol-npn_05v0-1.svg 47 | .. |symbol-npn_05v0-2| image:: symbol-npn_05v0-2.svg 48 | .. |symbol-npn_05v0-3| image:: symbol-npn_05v0-3.svg 49 | .. |cross-section-npn_05v0| image:: cross-section-npn_05v0.svg 50 | .. |cross-section-npn_11v0| image:: cross-section-npn_11v0.svg 51 | 52 | -------------------------------------------------------------------------------- /docs/rules/device-details/npn_05v0/npn_05v0-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 1 3 | :stub-columns: 1 4 | 5 | 6 | * - Parameter 7 | - NOM 8 | - LSL 9 | - USL 10 | - Units 11 | - Description 12 | 13 | * - BFNPN1X1\_10P0 14 | - 37.5 15 | - 18.14 16 | - 56.93 17 | - 18 | - NPN forward Current Gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=10 µA` 19 | 20 | * - BFNPN1X1\_1P0 21 | - 36.72 22 | - 17.97 23 | - 55.38 24 | - 25 | - NPN forward Current Gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=1.0 µA` 26 | 27 | * - BFNPN1X2\_17P5 28 | - 35.14 29 | - 16.98 30 | - 53.37 31 | - 32 | - NPN forward Current Gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=17.5 µA` 33 | 34 | * - BFNPN1X2\_1P75 35 | - 34.57 36 | - 16.89 37 | - 52.2 38 | - 39 | - NPN forward Current Gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=1.75 µA` 40 | 41 | * - BFNPNPOLY\_3P16 42 | - 125.28 43 | - 62.37 44 | - 500 45 | - 46 | - NPN forward Current Gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=3.16 µA` 47 | 48 | * - BFNPNPOLY\_P316 49 | - 106.98 50 | - 55.94 51 | - 500 52 | - 53 | - NPN forward Current Gain (\ :math:`\frac{I_C}{I_B})` at :math:`I_E=0.316 µA` 54 | 55 | * - VBENPN1X1\_10P0 56 | - 0.7745 57 | - 0.7645 58 | - 0.7845 59 | - V 60 | - NPN emitter-base voltage at :math:`I_E=10 µA` 61 | 62 | * - VBENPN1X1\_1P0 63 | - 0.712 64 | - 0.702 65 | - 0.722 66 | - V 67 | - NPN emitter-base voltage at :math:`I_E=1.0 µA` 68 | 69 | * - VBENPN1X2\_17P5 70 | - 0.7745 71 | - 0.7645 72 | - 0.7845 73 | - V 74 | - NPN emitter-base voltage at :math:`I_E=17.5 µA` 75 | 76 | * - VBENPN1X2\_1P75 77 | - 0.712 78 | - 0.702 79 | - 0.722 80 | - V 81 | - NPN emitter-base voltage at :math:`I_E=1.75 µA` 82 | 83 | * - VBENPNPOLY\_3P16 84 | - 0.7073 85 | - 0.6933 86 | - 0.7213 87 | - V 88 | - NPN emitter-base voltage at :math:`I_E=3.16 µA` 89 | 90 | * - VBENPNPOLY\_P316 91 | - 0.6452 92 | - 0.6312 93 | - 0.6591 94 | - V 95 | - NPN emitter-base voltage at :math:`I_E=0.316 µA` 96 | 97 | -------------------------------------------------------------------------------- /docs/rules/periphery/p038-m1_dotdash.csv: -------------------------------------------------------------------------------- 1 | Name,Description,Flags,Value,Unit 2 | (m1.-),"| Algorithm should flag errors, for met1, if ANY of the following is true: 3 | | An entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window. 4 | | 80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window. 5 | | 60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window. 6 | | 50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window. 7 | | 40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window. 8 | | 30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window. 9 | | Exclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,, 10 | (m1.1),Width of metal1,,0.140,µm 11 | (m1.2),Spacing of metal1 to metal1,,0.140,µm 12 | (m1.3a),Min. spacing of features attached to or extending from huge_met1 for a distance of up to 0.280 µm to metal1 (rule not checked over non-huge met1 features),,0.280,µm 13 | (m1.3b),Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280,µm 14 | (m1.4),Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030,µm 15 | (m1.4a),"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005,µm 16 | (m1.5),Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,P AL,0.060,µm 17 | (m1.6),Min metal 1 area,,0.083,µm² 18 | (m1.7),Min area of metal1 holes,,0.140,µm² 19 | (m1.pd.1),Min MM1_oxide_Pattern_density,RR AL,0.7,\- 20 | (m1.pd.2a),Rule m1.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A AL,700,µm 21 | (m1.pd.2b),Rule m1.pd.1 has to be checked by dividing the chip into steps of …,A AL,70, 22 | (m1.11),Max width of metal1after slotting,CU NC,4.000,µm 23 | (m1.12),Add slots and remove vias and contacts if met1 wider than…..,CU,3.200, 24 | (m1.13),Max pattern density (PD) of met1,CU,0.77,\- 25 | (m1.14),Met1 PD window size,CU,50.000,µm 26 | (m1.14a),Met1 PD window step,CU,25.000,µm 27 | (m1.15),Mcon must be enclosed by met1 on one of two adjacent sides by at least …,CU,0.030,µm 28 | -------------------------------------------------------------------------------- /docs/rules/device-details/pfet_20v0/pfet_20v0-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Param 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXP20VHV1 31 | - 2\* 30/1.0 32 | - V 33 | - -1.043 34 | - -0.843 35 | - -1.243 36 | - -1.243 37 | - -0.843 38 | - -1.043 39 | - -1.243 40 | - -0.843 41 | 42 | * - VTBP20VHV1 43 | - 2\* 30/1.0 44 | - V 45 | - -1.588 46 | - -1.331 47 | - -1.845 48 | - -1.331 49 | - -1.845 50 | - -1.588 51 | - -1.845 52 | - -1.331 53 | 54 | * - BVP20VHV1 55 | - 2\* 30/1.0 56 | - V 57 | - 58 | - 59 | - 60 | - 61 | - 62 | - 36.31 63 | - 28.00 64 | - 60.00 65 | 66 | * - ID5P20VHV1 67 | - 2\* 30/1.0 68 | - mA 69 | - 1.292 70 | - 1.818 71 | - 0.772 72 | - 0.772 73 | - 1.818 74 | - 1.286 75 | - 0.7691 76 | - 1.805 77 | 78 | * - IDLP20VHV1 79 | - 2\* 30/1.0 80 | - mA 81 | - 0.261 82 | - 0.367 83 | - 0.157 84 | - 0.157 85 | - 0.367 86 | - 0.26 87 | - 0.156 88 | - 0.364 89 | 90 | * - IDSP20VHV1 91 | - 2\* 30/1.0 92 | - mA 93 | - 11.67 94 | - 16.31 95 | - 6.97 96 | - 6.97 97 | - 16.31 98 | - 11.6 99 | - 6.94 100 | - 16.2 101 | 102 | * - RDSP20VHV1 103 | - 2\* 30/1.0 104 | - Ω 105 | - 388.9 106 | - 277.0 107 | - 650.1 108 | - 650.1 109 | - 277.0 110 | - 388.9 111 | - 277.0 112 | - 650.1 113 | 114 | * - RSPOP20VHV1 115 | - 2\* 30/1.0 116 | - mΩ-mm\ :sup:`2` 117 | - 82.1 118 | - 58.5 119 | - 137.3 120 | - 137.3 121 | - 58.5 122 | - 82.12 123 | - 58.47 124 | - 137.3 125 | 126 | * - ILKP20VHV1 127 | - 2\* 30/1.0 128 | - LOG A 129 | - Max = -8.9 130 | - -11.63 131 | - -18 132 | - -9 133 | - 134 | - 135 | - 136 | - 137 | 138 | -------------------------------------------------------------------------------- /docs/rules/device-details/nfet_03v3_nvt-and-nfet_05v0_nvt/nfet_03v3_nvt-and-nfet_05v0_nvt-table0.rst: -------------------------------------------------------------------------------- 1 | .. list-table:: 2 | :header-rows: 2 3 | :stub-columns: 1 4 | 5 | 6 | * - Param 7 | - W/L 8 | - Units 9 | - MODEL 10 | - 11 | - 12 | - 13 | - 14 | - EDR 15 | - 16 | - 17 | 18 | * - 19 | - 20 | - 21 | - TT 22 | - FF 23 | - SS 24 | - FS 25 | - SF 26 | - NOM 27 | - MIN 28 | - MAX 29 | 30 | * - VTXNLNVH 31 | - 10/4.0 32 | - V 33 | - 0.121 34 | - 0.091 35 | - 0.151 36 | - 0.164 37 | - 0.079 38 | - 0.121 39 | - 0.079 40 | - 0.164 41 | 42 | * - VTXNS90NVH 43 | - 10/0.9 44 | - V 45 | - 5.855 46 | - 6.098 47 | - 5.605 48 | - 6.107 49 | - 5.592 50 | - 0.097 51 | - 0.044 52 | - 0.150 53 | 54 | * - VTXNSN90NVH 55 | - 0.42/0.9 56 | - V 57 | - 0.075 58 | - 0.017 59 | - 0.129 60 | - 0.152 61 | - -0.014 62 | - 0.075 63 | - -0.002 64 | - 0.152 65 | 66 | * - IDSNS90NTH 67 | - 10/0.9 68 | - mA 69 | - 0.097 70 | - 0.06 71 | - 0.134 72 | - 0.15 73 | - 0.044 74 | - 5.819 75 | - 5.558 76 | - 6.069 77 | 78 | * - ILKN90NVH 79 | - 10/0.9 80 | - LOG A 81 | - Max = -5.6 82 | - -6.5 83 | - -18 84 | - -5.6 85 | - 86 | - 87 | - 88 | - 89 | 90 | * - VTXNS50NTH 91 | - 10/0.5 92 | - V 93 | - -0.029 94 | - 0.029 95 | - 0.013 96 | - 0.031 97 | - 0.011 98 | - -0.029 99 | - -0.089 100 | - 0.031 101 | 102 | * - VTXNSN50NTH 103 | - 0.42/0.5 104 | - V 105 | - -0.033 106 | - 0.013 107 | - 0.02 108 | - 0.043 109 | - -0.009 110 | - -0.046 111 | - -0.142 112 | - 0.050 113 | 114 | * - IDSNS50NTH 115 | - 10/0.5 116 | - mA 117 | - 4.858 118 | - 5.294 119 | - 4.423 120 | - 5.331 121 | - 4.386 122 | - 4.823 123 | - 4.357 124 | - 5.291 125 | 126 | * - ILKN50NVH 127 | - 10/0.5 128 | - LOG A 129 | - Max = -3.6 130 | - -4.03 131 | - -18 132 | - -3.67 133 | - 134 | - 135 | - 136 | - 137 | 138 | --------------------------------------------------------------------------------