├── README.md ├── SystemC ├── Biblioteca e Tutorial │ ├── Icon │ ├── contador │ │ ├── Icon │ │ ├── contado.cpp │ │ └── testbench.cpp │ ├── contador_thread │ │ ├── Icon │ │ ├── contador.cpp │ │ └── testbench.cpp │ ├── hello.cpp │ ├── instalar_systemc.txt │ └── systemc-2.3.1.tgz ├── Icon ├── Minicurso5_Parte1___IntroduçãoModelagemSystemC.pdf ├── SystemC.pdf ├── UserGuideIEEE.pdf ├── aula_systemc.pdf └── compilacao ├── diagram └── .stub ├── enunciado.txt ├── processor ├── .processor.cpp.swp ├── .stub ├── Cicle_test │ ├── Add.output │ ├── Empty.output │ ├── Fib.output │ ├── J.output │ ├── Jn.output │ ├── Jz.output │ ├── Sub.output │ └── mult3.output ├── compile.sh ├── components │ ├── control │ │ ├── control.cpp │ │ ├── main.aux │ │ ├── main.log │ │ ├── main.out │ │ └── main.toc │ ├── decoder │ │ └── decoder.cpp │ ├── instruction_register │ │ └── instruction_register.cpp │ ├── multiplex │ │ ├── multiplex2.cpp │ │ └── multiplex3.cpp │ ├── pipeline_reg │ │ └── pipeline_reg.h │ ├── program_counter │ │ ├── pc.vcd │ │ ├── program_counter.cpp │ │ ├── test_program_counter │ │ └── test_program_counter.cpp │ ├── ram │ │ ├── ram.h │ │ ├── tests_ram │ │ └── tests_ram.cpp │ ├── register_base │ │ └── register_base.h │ └── ula │ │ └── ula.h ├── output.out ├── processor.cpp ├── processor_run ├── processor_run.cpp ├── run.sh └── tests │ ├── add.test │ ├── and.test │ ├── basic.test │ ├── basic2.test │ ├── cmp.test │ ├── empty.test │ ├── fib_5.test │ ├── j.test │ ├── jn.test │ ├── jz.test │ ├── ld.test │ ├── lri.test │ ├── multiplica3x6.test │ ├── not.test │ ├── or.test │ ├── st.test │ ├── sub.test │ ├── sum24.test │ └── xor.test ├── report ├── .stub ├── img │ ├── procdiag.png │ └── statediag.png ├── main.aux ├── main.log ├── main.out ├── main.pdf ├── main.tex ├── main.toc └── texput.log └── slide ├── Slide2 ├── .lpr.tex.swp ├── abntex2-modelo-references.bib ├── conclusao.tex ├── ficticio.tex ├── img │ ├── F.jpg │ ├── F2.jpg │ ├── Q.jpg │ ├── carplate.png │ ├── carplaterec.png │ ├── normplot31.jpg │ ├── normplot81.jpg │ ├── normplotsdescs │ │ ├── NormPlotD1.jpg │ │ ├── NormPlotD10.jpg │ │ ├── NormPlotD100.jpg │ │ ├── NormPlotD101.jpg │ │ ├── NormPlotD102.jpg │ │ ├── NormPlotD103.jpg │ │ ├── NormPlotD104.jpg │ │ ├── NormPlotD105.jpg │ │ ├── NormPlotD106.jpg │ │ ├── NormPlotD107.jpg │ │ ├── NormPlotD108.jpg │ │ ├── NormPlotD109.jpg │ │ ├── NormPlotD11.jpg │ │ ├── NormPlotD110.jpg │ │ ├── NormPlotD111.jpg │ │ ├── NormPlotD112.jpg │ │ ├── NormPlotD113.jpg │ │ ├── NormPlotD114.jpg │ │ ├── NormPlotD115.jpg │ │ ├── NormPlotD116.jpg │ │ ├── NormPlotD117.jpg │ │ ├── NormPlotD118.jpg │ │ ├── NormPlotD119.jpg │ │ ├── NormPlotD12.jpg │ │ ├── NormPlotD120.jpg │ │ ├── NormPlotD121.jpg │ │ ├── NormPlotD122.jpg │ │ ├── NormPlotD123.jpg │ │ ├── NormPlotD124.jpg │ │ ├── NormPlotD125.jpg │ │ ├── NormPlotD126.jpg │ │ ├── NormPlotD127.jpg │ │ ├── NormPlotD128.jpg │ │ ├── NormPlotD129.jpg │ │ ├── NormPlotD13.jpg │ │ ├── NormPlotD130.jpg │ │ ├── NormPlotD131.jpg │ │ ├── NormPlotD132.jpg │ │ ├── NormPlotD133.jpg │ │ ├── NormPlotD134.jpg │ │ ├── NormPlotD135.jpg │ │ ├── NormPlotD136.jpg │ │ ├── NormPlotD137.jpg │ │ ├── NormPlotD138.jpg │ │ ├── NormPlotD139.jpg │ │ ├── NormPlotD14.jpg │ │ ├── NormPlotD140.jpg │ │ ├── NormPlotD141.jpg │ │ ├── NormPlotD142.jpg │ │ ├── NormPlotD143.jpg │ │ ├── NormPlotD144.jpg │ │ ├── NormPlotD145.jpg │ │ ├── NormPlotD146.jpg │ │ ├── NormPlotD147.jpg │ │ ├── NormPlotD148.jpg │ │ ├── NormPlotD149.jpg │ │ ├── NormPlotD15.jpg │ │ ├── NormPlotD150.jpg │ │ ├── NormPlotD151.jpg │ │ ├── NormPlotD152.jpg │ │ ├── NormPlotD153.jpg │ │ ├── NormPlotD154.jpg │ │ ├── NormPlotD155.jpg │ │ ├── NormPlotD156.jpg │ │ ├── NormPlotD157.jpg │ │ ├── NormPlotD158.jpg │ │ ├── NormPlotD159.jpg │ │ ├── NormPlotD16.jpg │ │ ├── NormPlotD160.jpg │ │ ├── NormPlotD161.jpg │ │ ├── NormPlotD162.jpg │ │ ├── NormPlotD163.jpg │ │ ├── NormPlotD164.jpg │ │ ├── NormPlotD165.jpg │ │ ├── NormPlotD166.jpg │ │ ├── NormPlotD167.jpg │ │ ├── NormPlotD168.jpg │ │ ├── NormPlotD169.jpg │ │ ├── NormPlotD17.jpg │ │ ├── NormPlotD170.jpg │ │ ├── NormPlotD171.jpg │ │ ├── NormPlotD172.jpg │ │ ├── NormPlotD173.jpg │ │ ├── NormPlotD174.jpg │ │ ├── NormPlotD175.jpg │ │ ├── NormPlotD176.jpg │ │ ├── NormPlotD177.jpg │ │ ├── NormPlotD178.jpg │ │ ├── NormPlotD179.jpg │ │ ├── NormPlotD18.jpg │ │ ├── NormPlotD180.jpg │ │ ├── NormPlotD181.jpg │ │ ├── NormPlotD182.jpg │ │ ├── NormPlotD183.jpg │ │ ├── NormPlotD184.jpg │ │ ├── NormPlotD185.jpg │ │ ├── NormPlotD186.jpg │ │ ├── NormPlotD187.jpg │ │ ├── NormPlotD188.jpg │ │ ├── NormPlotD189.jpg │ │ ├── NormPlotD19.jpg │ │ ├── NormPlotD190.jpg │ │ ├── NormPlotD191.jpg │ │ ├── NormPlotD192.jpg │ │ ├── NormPlotD193.jpg │ │ ├── NormPlotD194.jpg │ │ ├── NormPlotD195.jpg │ │ ├── NormPlotD196.jpg │ │ ├── NormPlotD197.jpg │ │ ├── NormPlotD198.jpg │ │ ├── NormPlotD199.jpg │ │ ├── NormPlotD2.jpg │ │ ├── NormPlotD20.jpg │ │ ├── NormPlotD200.jpg │ │ ├── NormPlotD201.jpg │ │ ├── NormPlotD202.jpg │ │ ├── NormPlotD203.jpg │ │ ├── NormPlotD204.jpg │ │ ├── NormPlotD205.jpg │ │ ├── NormPlotD206.jpg │ │ ├── NormPlotD207.jpg │ │ ├── NormPlotD208.jpg │ │ ├── NormPlotD209.jpg │ │ ├── NormPlotD21.jpg │ │ ├── NormPlotD210.jpg │ │ ├── NormPlotD211.jpg │ │ ├── NormPlotD212.jpg │ │ ├── NormPlotD213.jpg │ │ ├── NormPlotD214.jpg │ │ ├── NormPlotD215.jpg │ │ ├── NormPlotD216.jpg │ │ ├── NormPlotD217.jpg │ │ ├── NormPlotD218.jpg │ │ ├── NormPlotD219.jpg │ │ ├── NormPlotD22.jpg │ │ ├── NormPlotD220.jpg │ │ ├── NormPlotD221.jpg │ │ ├── NormPlotD222.jpg │ │ ├── NormPlotD223.jpg │ │ ├── NormPlotD224.jpg │ │ ├── NormPlotD23.jpg │ │ ├── NormPlotD24.jpg │ │ ├── NormPlotD25.jpg │ │ ├── NormPlotD26.jpg │ │ ├── NormPlotD27.jpg │ │ ├── NormPlotD28.jpg │ │ ├── NormPlotD29.jpg │ │ ├── NormPlotD3.jpg │ │ ├── NormPlotD30.jpg │ │ ├── NormPlotD31.jpg │ │ ├── NormPlotD32.jpg │ │ ├── NormPlotD33.jpg │ │ ├── NormPlotD34.jpg │ │ ├── NormPlotD35.jpg │ │ ├── NormPlotD36.jpg │ │ ├── NormPlotD37.jpg │ │ ├── NormPlotD38.jpg │ │ ├── NormPlotD39.jpg │ │ ├── NormPlotD4.jpg │ │ ├── NormPlotD40.jpg │ │ ├── NormPlotD41.jpg │ │ ├── NormPlotD42.jpg │ │ ├── NormPlotD43.jpg │ │ ├── NormPlotD44.jpg │ │ ├── NormPlotD45.jpg │ │ ├── NormPlotD46.jpg │ │ ├── NormPlotD47.jpg │ │ ├── NormPlotD48.jpg │ │ ├── NormPlotD49.jpg │ │ ├── NormPlotD5.jpg │ │ ├── NormPlotD50.jpg │ │ ├── NormPlotD51.jpg │ │ ├── NormPlotD52.jpg │ │ ├── NormPlotD53.jpg │ │ ├── NormPlotD54.jpg │ │ ├── NormPlotD55.jpg │ │ ├── NormPlotD56.jpg │ │ ├── NormPlotD57.jpg │ │ ├── NormPlotD58.jpg │ │ ├── NormPlotD59.jpg │ │ ├── NormPlotD6.jpg │ │ ├── NormPlotD60.jpg │ │ ├── NormPlotD61.jpg │ │ ├── NormPlotD62.jpg │ │ ├── NormPlotD63.jpg │ │ ├── NormPlotD64.jpg │ │ ├── NormPlotD65.jpg │ │ ├── NormPlotD66.jpg │ │ ├── NormPlotD67.jpg │ │ ├── NormPlotD68.jpg │ │ ├── NormPlotD69.jpg │ │ ├── NormPlotD7.jpg │ │ ├── NormPlotD70.jpg │ │ ├── NormPlotD71.jpg │ │ ├── NormPlotD72.jpg │ │ ├── NormPlotD73.jpg │ │ ├── NormPlotD74.jpg │ │ ├── NormPlotD75.jpg │ │ ├── NormPlotD76.jpg │ │ ├── NormPlotD77.jpg │ │ ├── NormPlotD78.jpg │ │ ├── NormPlotD79.jpg │ │ ├── NormPlotD8.jpg │ │ ├── NormPlotD80.jpg │ │ ├── NormPlotD81.jpg │ │ ├── NormPlotD82.jpg │ │ ├── NormPlotD83.jpg │ │ ├── NormPlotD84.jpg │ │ ├── NormPlotD85.jpg │ │ ├── NormPlotD86.jpg │ │ ├── NormPlotD87.jpg │ │ ├── NormPlotD88.jpg │ │ ├── NormPlotD89.jpg │ │ ├── NormPlotD9.jpg │ │ ├── NormPlotD90.jpg │ │ ├── NormPlotD91.jpg │ │ ├── NormPlotD92.jpg │ │ ├── NormPlotD93.jpg │ │ ├── NormPlotD94.jpg │ │ ├── NormPlotD95.jpg │ │ ├── NormPlotD96.jpg │ │ ├── NormPlotD97.jpg │ │ ├── NormPlotD98.jpg │ │ └── NormPlotD99.jpg │ ├── procdiag.png │ └── statediag.png ├── lpr.tex ├── slides1.aux ├── slides1.bbl ├── slides1.blg ├── slides1.log ├── slides1.nav ├── slides1.out ├── slides1.pdf ├── slides1.snm ├── slides1.toc ├── slides2.aux ├── slides2.log ├── slides2.nav ├── slides2.out ├── slides2.pdf ├── slides2.snm ├── slides2.tex ├── slides2.toc ├── slides2.vrb └── texput.log ├── diagram └── .stub └── img ├── procdiag.png └── statediag.png /README.md: -------------------------------------------------------------------------------- 1 | # RISC Processor - SystemC 2 | This is a simple processor implemented in SystemC. It implements a small set of instructions and performs 3 | a trivial pipeline, with only two stages and no true predictions. 4 | 5 | The instruction word has the form: 6 | 7 | | OPCODE | D | F1 | F2 | 8 | |--------|---|----|----| 9 | | 4 bits | 9 bits | 9 bits | 9 bits| 10 | 11 | And the instruction set is listed below: 12 | 13 | | Instruction | Action | Example | 14 | | ----------- |:------------:|:--------------------------------------:| 15 | | AND | D<-F1 & F2 | AND 1 2 3 | 16 | | OR | D<-F1 | F2 | OR 1 2 3 | 17 | | XOR | D<-F1 ^ F2 | XOR 1 2 3 | 18 | | NOT | D<- ~F1 | NOT 1 2 3 | 19 | | CMP | Z<-1 if F1 == F2, N <-1 if F1 < F2 | CMP 1 2 3 | 20 | | ADD | D <- F1 + F2 | ADD 1 2 3 | 21 | | SUB | D <- F1 - F2 | SUB 1 2 3 | 22 | | LD | R[D] <- MEM[F1] | LD 1 2 | 23 | | ST | MEM[F1] <- R[D] | ST 1 2 | 24 | | J | CP <- D | J 1 | 25 | | JN | CP <- D, if N==1 | JN 1 | 26 | | JZ | CP <- D, if Z==1 | JZ 1 | 27 | | LRI | R[D] <- F1 | LRI 1 10 | 28 | 29 | Internally, the processor has the following structure (please notice that control signals were omitted for 30 | organization purposes): 31 | 32 | ![Block diagram](https://github.com/greati/processor_risc/blob/master/report/img/procdiag.png "Processor's diagram") 33 | 34 | ## Running 35 | 36 | First of all, I strongly recommend installing SystemC 2.3.1 following this tutorial: http://chaitulabs.blogspot.com.br/2014/05/systemc-231-installation-in-ubuntu.html. 37 | 38 | After that, enter the folder "processor" and execute the file ./compile.h. If it doesn't work, you can try to compile the file processor_run.cpp by yourself, indicating properly where the SystemC's libraries are. 39 | 40 | Finally, execute the ./processor_run program, passing a file with a list of instructions as argument. If you need examples 41 | of algorithms for this processor, take a look at the folder "processor/tests". 42 | 43 | Any suggestions or doubts, please refer to my e-mail, greati@ufrn.edu.br. 44 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/Icon : -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/Biblioteca e Tutorial/Icon -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/contador/Icon : -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/Biblioteca e Tutorial/contador/Icon -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/contador/contado.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | SC_MODULE (contador) { 4 | sc_in_clk clock ; 5 | sc_in reset ; 6 | sc_in enable; 7 | sc_out > counter_out; 8 | 9 | sc_uint<4> count; 10 | 11 | void incr_count () { 12 | if (reset.read() == 1) { 13 | count = 0; 14 | counter_out.write(count); 15 | } 16 | else if (enable.read() == 1) { 17 | count++; 18 | counter_out.write(count); 19 | } 20 | } 21 | 22 | SC_CTOR(contador) { 23 | SC_METHOD(incr_count); 24 | sensitive << reset; 25 | sensitive << clock.pos(); 26 | } 27 | }; 28 | 29 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/contador/testbench.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | #include "contador.cpp" 3 | 4 | int sc_main (int argc, char* argv[]) { 5 | sc_signal clock; 6 | sc_signal reset; 7 | sc_signal enable; 8 | sc_signal > counter_out; 9 | bool i = true; 10 | int c; 11 | 12 | contador counter("COUNTER"); 13 | counter.clock(clock); 14 | counter.reset(reset); 15 | counter.enable(enable); 16 | counter.counter_out(counter_out); 17 | 18 | sc_start(1, SC_NS); 19 | c = 0; 20 | enable = 1; 21 | reset=0; 22 | 23 | while(i){ 24 | cout << "#=== contador: " << counter_out << " | clock: " << c << " | tempo: " << sc_time_stamp() << endl; 25 | c++; 26 | 27 | if(c==2000){ 28 | i=false; 29 | } 30 | 31 | clock = 0; 32 | sc_start(1, SC_NS); 33 | clock = 1; 34 | sc_start(1, SC_NS); 35 | } 36 | 37 | return 0; 38 | 39 | } 40 | 41 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/contador_thread/Icon : -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/Biblioteca e Tutorial/contador_thread/Icon -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/contador_thread/contador.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | SC_MODULE (contador) { 4 | sc_in clock ; 5 | sc_in reset ; 6 | sc_in enable; 7 | sc_out > counter_out; 8 | int i = 0; 9 | 10 | sc_uint<4> count; 11 | 12 | void incr_count () { 13 | while(true){ 14 | if (reset.read() == 1) { 15 | count = 0; 16 | counter_out.write(count); 17 | 18 | } 19 | else if (enable.read() == 1) { 20 | count++; 21 | counter_out.write(count); 22 | 23 | } 24 | wait(); 25 | cout << "#=== contador: " << counter_out << " | clock: " << i << " | tempo: " << sc_time_stamp() << endl; 26 | i++; 27 | } 28 | } 29 | 30 | SC_CTOR(contador) { 31 | SC_THREAD(incr_count); 32 | sensitive << reset; 33 | sensitive << clock.pos(); 34 | } 35 | 36 | }; 37 | 38 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/contador_thread/testbench.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | #include "contador.cpp" 3 | 4 | int sc_main (int argc, char* argv[]) { 5 | //sc_signal clock; 6 | sc_clock clock("clk", 10, SC_NS, 0.5, 0.0, SC_NS, true); 7 | sc_signal reset; 8 | sc_signal enable; 9 | sc_signal > counter_out; 10 | bool i = true; 11 | int c; 12 | 13 | contador counter("COUNTER"); 14 | counter.clock(clock); 15 | counter.reset(reset); 16 | counter.enable(enable); 17 | counter.counter_out(counter_out); 18 | c = 0; 19 | enable = 1; 20 | reset=0; 21 | sc_start(); 22 | 23 | 24 | return 0; 25 | 26 | } 27 | 28 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/hello.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | SC_MODULE (hello_world) { 3 | SC_CTOR (hello_world) { 4 | 5 | } 6 | void say_hello() { 7 | cout << "Hello World.\n"; 8 | } 9 | }; 10 | 11 | int sc_main(int argc, char* argv[]) { 12 | hello_world hello("HELLO"); 13 | hello.say_hello(); 14 | return(0); 15 | } 16 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/instalar_systemc.txt: -------------------------------------------------------------------------------- 1 | Download da biblioteca SystemC: http://accellera.org/downloads/standards/systemc 2 | 3 | 1 - Descompactar em /usr/local 4 | 5 | 2 - $ cd /usr/local 6 | 7 | 3 - $ mkdir objdir 8 | 9 | 4 - $ cd objdir 10 | 11 | 5 - $ export CXX=compilador 12 | 13 | ex: > export CXX=g++ 14 | 15 | 6 - $ ../configure 16 | 17 | 7 - $ make 18 | 19 | 8 - $ make install 20 | 21 | 9 - deletar diretório objdir 22 | 23 | $ cd .. 24 | $ rm -rf objdir 25 | 26 | mais detalhes no arquivo INSTALL 27 | 28 | ====================================================== 29 | 30 | Para compilar: 31 | 32 | $ export SYSTEMC_HOME=/usr/local/systemc-2.3.1/ 33 | 34 | $ g++ -I. -I$SYSTEMC_HOME/include -L. -L$SYSTEMC_HOME/lib-linux64 -Wl,-rpath=$SYSTEMC_HOME/lib-linux64 -o hello hello.cpp -lsystemc -lm 35 | 36 | Para executar: 37 | 38 | $ ./hello 39 | 40 | ====================================================== 41 | 42 | No caso do erro: 43 | "error while loading shared libraries: libsystemc-2.3.1.so: cannot open shared object file: No such file or directory" 44 | 45 | $ sudo ln -s /usr/local/systemc-2.3.1/lib-linux64/libsystemc-2.3.1.so /usr/lib/libsystemc-2.3.0.so 46 | -------------------------------------------------------------------------------- /SystemC/Biblioteca e Tutorial/systemc-2.3.1.tgz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/Biblioteca e Tutorial/systemc-2.3.1.tgz -------------------------------------------------------------------------------- /SystemC/Icon : -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/Icon -------------------------------------------------------------------------------- /SystemC/Minicurso5_Parte1___IntroduçãoModelagemSystemC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/Minicurso5_Parte1___IntroduçãoModelagemSystemC.pdf -------------------------------------------------------------------------------- /SystemC/SystemC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/SystemC.pdf -------------------------------------------------------------------------------- /SystemC/UserGuideIEEE.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/UserGuideIEEE.pdf -------------------------------------------------------------------------------- /SystemC/aula_systemc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/SystemC/aula_systemc.pdf -------------------------------------------------------------------------------- /SystemC/compilacao: -------------------------------------------------------------------------------- 1 | g++ hello.cpp -o hello -lsystemc -lm 2 | -------------------------------------------------------------------------------- /diagram/.stub: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/diagram/.stub -------------------------------------------------------------------------------- /enunciado.txt: -------------------------------------------------------------------------------- 1 | Trabalho da disciplina DIM0431 - Arquitetura e Organização de Computadores - 2016.2. Desenvolvido por grupos de até 3 alunos. 2 | 3 | 4 | 5 | 1- Entrega (via tarefas-SIGAA): 30/11/16. 6 | 7 | 8 | 9 | 2- Apresentação (em sala): 05 e 07/12/16. 10 | 11 | 12 | 13 | 3- Descrição do Trabalho: 14 | 15 | 16 | 17 | 3.1- Implementar a arquitetura para um conjunto de instruções (ISA, Instruction-Set Architecture) composta por Parte de Controle e Parte Operativa, compatíveis com a filosofia RISC (Reduced Instruction-Set Computer) e que executam em “Pipeline” o seguinte conjunto de instruções: 18 | 19 | 20 | 21 | AND —> operação booleana AND 22 | 23 | OR —> operação booleana OR 24 | 25 | XOR —> operação booleana XOR 26 | 27 | NOT —> operação booleana NOT 28 | 29 | CMP —> comparação 30 | 31 | ADD —> soma 32 | 33 | SUB —> subtração 34 | 35 | LD —> leitura em memória 36 | 37 | ST —> armazenamento em memória 38 | 39 | J —> salto incondicional 40 | 41 | JN —> salto condicional; salta se (N)egativo 42 | 43 | JZ —> salto condicional; salta se (Z)ero 44 | 45 | 46 | 47 | 3.2- Serão decisões de projeto: 48 | 49 | A- o tamanho da palavra do processador; 50 | 51 | B- o formato da palavra de instrução; 52 | 53 | C- os modos de endereçamento de operandos; 54 | 55 | D- o tamanho do banco de registradores; 56 | 57 | E- o tamanho das memórias de instruções e de dados; 58 | 59 | F- o número de estágios do pipeline; 60 | 61 | G- o número e tipos de barramentos da parte operativa. 62 | 63 | 64 | 65 | 3.3- O trabalho consiste de: 66 | 67 | 68 | 69 | A- Implementação da arquitetura em VHDL ou SystemC; 70 | 71 | B- Resultados de simulações de instruções na arquitetura. Os resultados podem ser apresentados em diagramas de forma de onda e/ou textual; 72 | 73 | C- Relatório explicando e exemplificando a implementação da arquitetura e justificando as decisões de projeto acima elencadas (seção 3.2). O relatório deve conter pelo menos os diagramas de bloco das partes de controle e operativa e deve mostrar análises de desempenho (ciclos de relógio necessários à execução das instruções) em função dos comportamentos do pipeline. Entende-se por comportamentos do pipeline, os tratamentos implementados para as dependências de dados e de controle; e 74 | 75 | D- Apresentação (10 minutos). Os integrantes do grupo serão avaliados individualmente, e devem saber responder as perguntas relativas a todo o trabalho. 76 | 77 | 78 | -------------------------------------------------------------------------------- /processor/.processor.cpp.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/processor/.processor.cpp.swp -------------------------------------------------------------------------------- /processor/.stub: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/processor/.stub -------------------------------------------------------------------------------- /processor/Cicle_test/Add.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 6001001002 19 | ~~~~---------------------------~~~~ 20 | 21 | Processing instruction 0 22 | Processing instruction 6001001002 23 | Processing instruction 0 24 | 25 | Info: /OSCI/SystemC: Simulation stopped by user. 26 | 27 | Finished after 5 cicles. Final state: 28 | 29 | /******* REGISTERS ********/ 30 | [0]-0 31 | [1]-0 32 | [2]-0 33 | [3]-0 34 | [4]-0 35 | [5]-0 36 | [6]-0 37 | [7]-0 38 | [8]-0 39 | [9]-0 40 | 41 | /******* MEMORY ********/ 42 | [0] - 0 43 | [1] - 0 44 | [2] - 0 45 | [3] - 0 46 | [4] - 0 47 | [5] - 0 48 | [6] - 0 49 | [7] - 0 50 | [8] - 0 51 | [9] - 0 52 | 53 | -------------------------------------------------------------------------------- /processor/Cicle_test/Empty.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | ~~~~---------------------------~~~~ 19 | 20 | Processing instruction 0 21 | 22 | Info: /OSCI/SystemC: Simulation stopped by user. 23 | 24 | Finished after 0 cicles. Final state: 25 | 26 | /******* REGISTERS ********/ 27 | [0]-0 28 | [1]-0 29 | [2]-0 30 | [3]-0 31 | [4]-0 32 | [5]-0 33 | [6]-0 34 | [7]-0 35 | [8]-0 36 | [9]-0 37 | 38 | /******* MEMORY ********/ 39 | [0] - 0 40 | [1] - 0 41 | [2] - 0 42 | [3] - 0 43 | [4] - 0 44 | [5] - 0 45 | [6] - 0 46 | [7] - 0 47 | [8] - 0 48 | [9] - 0 49 | 50 | -------------------------------------------------------------------------------- /processor/Cicle_test/Fib.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 13003001000 19 | 13006000000 20 | 13007001000 21 | 13001000000 22 | 13002001000 23 | 13004001000 24 | 13005010000 25 | 7005005007 26 | 5009005004 27 | 11015000000 28 | 6003001002 29 | 6001006002 30 | 6002006003 31 | 6004007004 32 | 10008000000 33 | 9001003000 34 | ~~~~---------------------------~~~~ 35 | 36 | Processing instruction 0 37 | Processing instruction 13003001000 38 | Processing instruction 13006000000 39 | Processing instruction 13007001000 40 | Processing instruction 13001000000 41 | Processing instruction 13002001000 42 | Processing instruction 13004001000 43 | Processing instruction 13005010000 44 | Processing instruction 7005005007 45 | Processing instruction 5009005004 46 | Processing instruction 11015000000 47 | Processing instruction 6003001002 48 | Processing instruction 6001006002 49 | Processing instruction 6002006003 50 | Processing instruction 6004007004 51 | Processing instruction 10008000000 52 | Processing instruction 9001003000 53 | Processing instruction 5009005004 54 | Processing instruction 11015000000 55 | Processing instruction 6003001002 56 | Processing instruction 6001006002 57 | Processing instruction 6002006003 58 | Processing instruction 6004007004 59 | Processing instruction 10008000000 60 | Processing instruction 9001003000 61 | Processing instruction 5009005004 62 | Processing instruction 11015000000 63 | Processing instruction 6003001002 64 | Processing instruction 6001006002 65 | Processing instruction 6002006003 66 | Processing instruction 6004007004 67 | Processing instruction 10008000000 68 | Processing instruction 9001003000 69 | Processing instruction 5009005004 70 | Processing instruction 11015000000 71 | Processing instruction 6003001002 72 | Processing instruction 6001006002 73 | Processing instruction 6002006003 74 | Processing instruction 6004007004 75 | Processing instruction 10008000000 76 | Processing instruction 9001003000 77 | Processing instruction 5009005004 78 | Processing instruction 11015000000 79 | Processing instruction 6003001002 80 | Processing instruction 6001006002 81 | Processing instruction 6002006003 82 | Processing instruction 6004007004 83 | Processing instruction 10008000000 84 | Processing instruction 9001003000 85 | Processing instruction 5009005004 86 | Processing instruction 11015000000 87 | Processing instruction 6003001002 88 | Processing instruction 6001006002 89 | Processing instruction 6002006003 90 | Processing instruction 6004007004 91 | Processing instruction 10008000000 92 | Processing instruction 9001003000 93 | Processing instruction 5009005004 94 | Processing instruction 11015000000 95 | Processing instruction 6003001002 96 | Processing instruction 6001006002 97 | Processing instruction 6002006003 98 | Processing instruction 6004007004 99 | Processing instruction 10008000000 100 | Processing instruction 9001003000 101 | Processing instruction 5009005004 102 | Processing instruction 11015000000 103 | Processing instruction 6003001002 104 | Processing instruction 6001006002 105 | Processing instruction 6002006003 106 | Processing instruction 6004007004 107 | Processing instruction 10008000000 108 | Processing instruction 9001003000 109 | Processing instruction 5009005004 110 | Processing instruction 11015000000 111 | Processing instruction 6003001002 112 | Processing instruction 6001006002 113 | Processing instruction 6002006003 114 | Processing instruction 6004007004 115 | Processing instruction 10008000000 116 | Processing instruction 9001003000 117 | Processing instruction 5009005004 118 | Processing instruction 11015000000 119 | Processing instruction 6003001002 120 | Processing instruction 9001003000 121 | Processing instruction 0 122 | 123 | Info: /OSCI/SystemC: Simulation stopped by user. 124 | 125 | Finished after 374 cicles. Final state: 126 | 127 | /******* REGISTERS ********/ 128 | [0]-0 129 | [1]-34 130 | [2]-55 131 | [3]-55 132 | [4]-10 133 | [5]-9 134 | [6]-0 135 | [7]-1 136 | [8]-0 137 | [9]-0 138 | 139 | /******* MEMORY ********/ 140 | [0] - 0 141 | [1] - 55 142 | [2] - 0 143 | [3] - 0 144 | [4] - 0 145 | [5] - 0 146 | [6] - 0 147 | [7] - 0 148 | [8] - 0 149 | [9] - 0 150 | 151 | -------------------------------------------------------------------------------- /processor/Cicle_test/J.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 10005000000 19 | ~~~~---------------------------~~~~ 20 | 21 | Processing instruction 0 22 | Processing instruction 10005000000 23 | Processing instruction 0 24 | 25 | Info: /OSCI/SystemC: Simulation stopped by user. 26 | 27 | Finished after 7 cicles. Final state: 28 | 29 | /******* REGISTERS ********/ 30 | [0]-0 31 | [1]-0 32 | [2]-0 33 | [3]-0 34 | [4]-0 35 | [5]-0 36 | [6]-0 37 | [7]-0 38 | [8]-0 39 | [9]-0 40 | 41 | /******* MEMORY ********/ 42 | [0] - 0 43 | [1] - 0 44 | [2] - 0 45 | [3] - 0 46 | [4] - 0 47 | [5] - 0 48 | [6] - 0 49 | [7] - 0 50 | [8] - 0 51 | [9] - 0 52 | 53 | -------------------------------------------------------------------------------- /processor/Cicle_test/Jn.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 11005000000 19 | ~~~~---------------------------~~~~ 20 | 21 | Processing instruction 0 22 | Processing instruction 11005000000 23 | Processing instruction 0 24 | 25 | Info: /OSCI/SystemC: Simulation stopped by user. 26 | 27 | Finished after 4 cicles. Final state: 28 | 29 | /******* REGISTERS ********/ 30 | [0]-0 31 | [1]-0 32 | [2]-0 33 | [3]-0 34 | [4]-0 35 | [5]-0 36 | [6]-0 37 | [7]-0 38 | [8]-0 39 | [9]-0 40 | 41 | /******* MEMORY ********/ 42 | [0] - 0 43 | [1] - 0 44 | [2] - 0 45 | [3] - 0 46 | [4] - 0 47 | [5] - 0 48 | [6] - 0 49 | [7] - 0 50 | [8] - 0 51 | [9] - 0 52 | 53 | -------------------------------------------------------------------------------- /processor/Cicle_test/Jz.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 12005000000 19 | ~~~~---------------------------~~~~ 20 | 21 | Processing instruction 0 22 | Processing instruction 12005000000 23 | Processing instruction 0 24 | 25 | Info: /OSCI/SystemC: Simulation stopped by user. 26 | 27 | Finished after 4 cicles. Final state: 28 | 29 | /******* REGISTERS ********/ 30 | [0]-0 31 | [1]-0 32 | [2]-0 33 | [3]-0 34 | [4]-0 35 | [5]-0 36 | [6]-0 37 | [7]-0 38 | [8]-0 39 | [9]-0 40 | 41 | /******* MEMORY ********/ 42 | [0] - 0 43 | [1] - 0 44 | [2] - 0 45 | [3] - 0 46 | [4] - 0 47 | [5] - 0 48 | [6] - 0 49 | [7] - 0 50 | [8] - 0 51 | [9] - 0 52 | 53 | -------------------------------------------------------------------------------- /processor/Cicle_test/Sub.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 7001001002 19 | ~~~~---------------------------~~~~ 20 | 21 | Processing instruction 0 22 | Processing instruction 7001001002 23 | Processing instruction 0 24 | 25 | Info: /OSCI/SystemC: Simulation stopped by user. 26 | 27 | Finished after 5 cicles. Final state: 28 | 29 | /******* REGISTERS ********/ 30 | [0]-0 31 | [1]-0 32 | [2]-0 33 | [3]-0 34 | [4]-0 35 | [5]-0 36 | [6]-0 37 | [7]-0 38 | [8]-0 39 | [9]-0 40 | 41 | /******* MEMORY ********/ 42 | [0] - 0 43 | [1] - 0 44 | [2] - 0 45 | [3] - 0 46 | [4] - 0 47 | [5] - 0 48 | [6] - 0 49 | [7] - 0 50 | [8] - 0 51 | [9] - 0 52 | 53 | -------------------------------------------------------------------------------- /processor/Cicle_test/mult3.output: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | Found! Reading instructions... 16 | Loading into instruction memory... 17 | Done! Instructions to be processed: 18 | 13001003000 19 | 13002006000 20 | 13003001000 21 | 13004000000 22 | 13005000000 23 | 5009004001 24 | 12010000000 25 | 6005005002 26 | 7001001003 27 | 10005000000 28 | 9001005000 29 | ~~~~---------------------------~~~~ 30 | 31 | Processing instruction 0 32 | Processing instruction 13001003000 33 | Processing instruction 13002006000 34 | Processing instruction 13003001000 35 | Processing instruction 13004000000 36 | Processing instruction 13005000000 37 | Processing instruction 5009004001 38 | Processing instruction 12010000000 39 | Processing instruction 6005005002 40 | Processing instruction 7001001003 41 | Processing instruction 10005000000 42 | Processing instruction 9001005000 43 | Processing instruction 5009004001 44 | Processing instruction 12010000000 45 | Processing instruction 6005005002 46 | Processing instruction 7001001003 47 | Processing instruction 10005000000 48 | Processing instruction 9001005000 49 | Processing instruction 5009004001 50 | Processing instruction 12010000000 51 | Processing instruction 6005005002 52 | Processing instruction 7001001003 53 | Processing instruction 10005000000 54 | Processing instruction 9001005000 55 | Processing instruction 5009004001 56 | Processing instruction 12010000000 57 | Processing instruction 6005005002 58 | Processing instruction 9001005000 59 | Processing instruction 0 60 | 61 | Info: /OSCI/SystemC: Simulation stopped by user. 62 | 63 | Finished after 115 cicles. Final state: 64 | 65 | /******* REGISTERS ********/ 66 | [0]-0 67 | [1]-0 68 | [2]-6 69 | [3]-1 70 | [4]-0 71 | [5]-18 72 | [6]-0 73 | [7]-0 74 | [8]-0 75 | [9]-1 76 | 77 | /******* MEMORY ********/ 78 | [0] - 0 79 | [1] - 18 80 | [2] - 0 81 | [3] - 0 82 | [4] - 0 83 | [5] - 0 84 | [6] - 0 85 | [7] - 0 86 | [8] - 0 87 | [9] - 0 88 | 89 | -------------------------------------------------------------------------------- /processor/compile.sh: -------------------------------------------------------------------------------- 1 | g++ -I. -I$SYSTEMC_HOME/include -L. -L$SYSTEMC_HOME/lib-linux64 processor_run.cpp -o processor_run -lsystemc -lm -std=c++11 2 | -------------------------------------------------------------------------------- /processor/components/control/control.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | /* Component: Control module 4 | * 5 | * Control module of the processor. Responsible 6 | * for activating/deactivating functions of 7 | * the other components at each cycle. 8 | * 9 | * Implements internally a Mealy's finite state machine. 10 | * **/ 11 | SC_MODULE(control) { 12 | 13 | public: 14 | //-- Signals --// 15 | //-- In --// 16 | sc_in_clk clock; 17 | sc_in > opcode; // OPCODE 18 | sc_in > of1; // Operando fonte 1 19 | sc_in > of2; // Operando fonte 2 20 | sc_in > opd; // Operando destino 21 | sc_in N; 22 | sc_in Z; 23 | 24 | //-- Out --// 25 | // Program counter control 26 | sc_out enableCP; 27 | sc_out loadCP; 28 | sc_out resetCP; 29 | sc_out> jumpValueCP; 30 | 31 | // Instruction memory control 32 | sc_out enableIM; 33 | sc_out writeIM; 34 | 35 | // Data memory control; 36 | sc_out enableDM; 37 | sc_out writeDM; 38 | 39 | // Instruction register control 40 | sc_out enableRI; 41 | sc_out writeRI; 42 | sc_out> immediateValue; 43 | sc_out> immediateRegister; 44 | 45 | // Register base control 46 | sc_out enableRB; 47 | sc_out writeRB; 48 | 49 | // Register pipeline 50 | sc_out enableRPL; 51 | sc_out writeRPL; 52 | sc_out resetRPL; 53 | 54 | // ULA control 55 | sc_out resetZN; 56 | 57 | // Multiplex for write data on register base 58 | sc_out> seletorMultiRBW; 59 | 60 | // Multiplex for addressing DM 61 | sc_out> seletorMultiDM; 62 | 63 | //-- Constructor --// 64 | SC_CTOR(control) { 65 | SC_METHOD(state_machine); 66 | sensitive << clock.pos(); 67 | } 68 | 69 | private: 70 | //-- Local variables --// 71 | int curState = 0; 72 | bool restartPipe = false; 73 | 74 | //-- Methods for making pipeline easy --// 75 | 76 | /* 77 | * Prepare components so that, in the next cycle, 78 | * the instruction is available on the bus. 79 | * * */ 80 | void prepareInstToBus(); 81 | 82 | /* Prepare components so that the instruction 83 | * is stored in the instruction register in 84 | * the next cycle. 85 | * * */ 86 | void prepareInstBusToRI(); 87 | 88 | /* Prepare components so that the decodified instruction 89 | * is written in the pipeline register. 90 | * **/ 91 | void prepareRItoRPL(); 92 | 93 | /* Make the instruction waits when reaches the cycle 94 | * before the pipeline register (for pipeline purposes 95 | * only). 96 | * **/ 97 | void afterRIWrite(); 98 | 99 | /* The Mealy's state machine: uses the current 100 | * state and informations from outside in order 101 | * to keep the processor working properly in 102 | * terms of microinstructions. 103 | * **/ 104 | void state_machine(); 105 | 106 | 107 | }; 108 | 109 | void control::prepareInstToBus() { 110 | enableIM.write(1); // Enable IM 111 | writeIM.write(0); // Read from IM 112 | enableCP.write(1); // Increment counter 113 | } 114 | 115 | void control::prepareInstBusToRI() { 116 | enableIM.write(0); // Disable IM 117 | enableRI.write(1); // Enable RI 118 | writeRI.write(1); // Write IR 119 | enableCP.write(0); // Stop incrementing PC 120 | } 121 | 122 | void control::prepareRItoRPL() { 123 | enableRI.write(0); // Disable Ri 124 | enableRPL.write(1); // Enable pipeline register 125 | writeRPL.write(1); // Write pipeline register 126 | } 127 | 128 | void control::afterRIWrite() { 129 | enableRI.write(0); 130 | } 131 | 132 | void control::state_machine() { 133 | switch(curState) { 134 | // Write instruction in the bus 135 | case 0: 136 | prepareInstToBus(); 137 | curState = 1; 138 | break; 139 | // Once the instruction is in the bus, we write it into the RI 140 | case 1: 141 | prepareInstBusToRI(); 142 | curState = 2; 143 | break; 144 | // Once in the IR and in the bus for decoding, write at pipeline decoded 145 | case 2: 146 | if (!restartPipe) { 147 | prepareRItoRPL(); 148 | curState = 3; 149 | } else { 150 | curState = 0; 151 | restartPipe = false; 152 | } 153 | break; 154 | // Written in pipeline 155 | case 3: 156 | enableRPL.write(0); 157 | curState = 5; 158 | prepareInstToBus(); // Take new instruction (pipeline) 159 | break; 160 | // Prepare execution 161 | case 5: 162 | prepareInstBusToRI(); // Put new instruction on RI (pipeline) 163 | 164 | // Load operations: can be LRI (immediate) or LD 165 | if (opcode.read() == 8 || opcode.read() == 13) { 166 | enableRB.write(1); 167 | writeRB.write(1); 168 | // LRI operation 169 | if (opcode.read() == 13) { 170 | immediateRegister.write(opd.read()); 171 | immediateValue.write(of1.read()); 172 | seletorMultiRBW.write(2); 173 | curState = 9; 174 | // LD operation 175 | } else if (opcode.read() == 8) { 176 | enableDM.write(1); 177 | writeDM.write(0); 178 | seletorMultiRBW.write(1); 179 | seletorMultiDM.write(1); 180 | curState = 10; 181 | } 182 | // ST operation 183 | } else if (opcode.read() == 9) { 184 | enableRB.write(1); 185 | writeRB.write(0); 186 | curState = 7; 187 | seletorMultiDM.write(0); 188 | // J operation 189 | } else if (opcode.read() == 10) { 190 | enableCP.write(0); 191 | loadCP.write(1); 192 | jumpValueCP.write(opd); 193 | curState = 8; 194 | restartPipe = true; 195 | // JN operation 196 | } else if (opcode.read() == 11) { 197 | if (N.read() == 1) { 198 | jumpValueCP.write(opd); 199 | enableCP.write(0); 200 | loadCP.write(1); 201 | resetZN.write(1); 202 | restartPipe = true; 203 | } 204 | curState = 8; 205 | // JZ operation 206 | } else if (opcode.read() == 12) { 207 | if (Z.read() == 1) { 208 | jumpValueCP.write(opd); 209 | enableCP.write(0); 210 | loadCP.write(1); 211 | resetZN.write(1); 212 | restartPipe = true; 213 | } 214 | curState = 8; 215 | // ULA operations 216 | } else if (opcode.read() != 0) { 217 | seletorMultiRBW.write(0); 218 | enableRB.write(1); 219 | writeRB.write(0); 220 | curState = 6; 221 | } else if (opcode.read() == 0) { 222 | sc_stop(); 223 | } 224 | break; 225 | // Execute ULA operations 226 | case 6: 227 | enableRB.write(1); 228 | writeRB.write(1); 229 | curState = 9; 230 | afterRIWrite(); // Stop pipe propagation 231 | break; 232 | // Execute ST operation 233 | case 7: 234 | enableDM.write(1); 235 | writeDM.write(1); 236 | curState = 9; 237 | afterRIWrite(); // Stop pipe propagation 238 | break; 239 | // Execute jumps 240 | case 8: 241 | loadCP.write(0); 242 | curState = 2; 243 | break; 244 | // Store results from ULA operations 245 | case 9: 246 | enableRB.write(0); 247 | enableDM.write(0); 248 | curState = 2; 249 | afterRIWrite(); // Stop pipe propagation 250 | break; 251 | // Execute LD operation 252 | case 10: 253 | enableRB.write(1); 254 | writeRB.write(1); 255 | curState = 9; 256 | break; 257 | } 258 | } 259 | -------------------------------------------------------------------------------- /processor/components/control/main.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \catcode `"\active 4 | \providecommand\HyperFirstAtBeginDocument{\AtBeginDocument} 5 | \HyperFirstAtBeginDocument{\ifx\hyper@anchor\@undefined 6 | \global\let\oldcontentsline\contentsline 7 | \gdef\contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}} 8 | \global\let\oldnewlabel\newlabel 9 | \gdef\newlabel#1#2{\newlabelxx{#1}#2} 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[1][-]{section.3}{Diagrama}{}% 16 17 | \BOOKMARK [1][-]{section.4}{Testes}{}% 17 18 | \BOOKMARK [1][-]{section.5}{Resultados}{}% 18 19 | \BOOKMARK [1][-]{section.6}{Conclus\365es}{}% 19 20 | -------------------------------------------------------------------------------- /processor/components/control/main.toc: -------------------------------------------------------------------------------- 1 | \select@language {brazilian} 2 | \contentsline {section}{\numberline {1}Decis\IeC {\~o}es de projeto}{2}{section.1} 3 | \contentsline {subsection}{\numberline {1.1}Conjunto de instru\IeC {\c c}\IeC {\~o}es}{2}{subsection.1.1} 4 | \contentsline {subsection}{\numberline {1.2}Palavra de instru\IeC {\c c}\IeC {\~a}o}{2}{subsection.1.2} 5 | \contentsline {subsection}{\numberline {1.3}Modos de endere\IeC {\c c}amento}{2}{subsection.1.3} 6 | \contentsline {subsection}{\numberline {1.4}Mem\IeC {\'o}rias}{2}{subsection.1.4} 7 | \contentsline {subsection}{\numberline {1.5}Pipeline}{2}{subsection.1.5} 8 | \contentsline {subsection}{\numberline {1.6}Barramentos da Parte Operativa}{3}{subsection.1.6} 9 | \contentsline {section}{\numberline {2}Componentes}{3}{section.2} 10 | \contentsline {subsection}{\numberline {2.1}Contador de programa}{3}{subsection.2.1} 11 | \contentsline {subsection}{\numberline {2.2}Mem\IeC {\'o}ria de instru\IeC {\c c}\IeC {\~o}es}{3}{subsection.2.2} 12 | \contentsline {subsection}{\numberline {2.3}Mem\IeC {\'o}ria de dados}{3}{subsection.2.3} 13 | \contentsline {subsection}{\numberline {2.4}Banco de registradores}{3}{subsection.2.4} 14 | \contentsline {subsection}{\numberline {2.5}Decodificador de instru\IeC {\c c}\IeC {\~o}es}{3}{subsection.2.5} 15 | \contentsline {subsection}{\numberline {2.6}Unidade L\IeC {\'o}gica e Aritm\IeC {\'e}tica}{3}{subsection.2.6} 16 | \contentsline {subsection}{\numberline {2.7}Parte de controle}{3}{subsection.2.7} 17 | \contentsline {section}{\numberline {3}Diagrama}{3}{section.3} 18 | \contentsline {section}{\numberline {4}Testes}{3}{section.4} 19 | \contentsline {section}{\numberline {5}Resultados}{3}{section.5} 20 | \contentsline {section}{\numberline {6}Conclus\IeC {\~o}es}{3}{section.6} 21 | -------------------------------------------------------------------------------- /processor/components/decoder/decoder.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | /* Component: Instruction decoder 4 | * 5 | * Takes an integer instruction in the format 6 | * 7 | * [ooodddfffsss] 8 | * 9 | * And simply returns it's parts: 10 | * 11 | * [ooo] [ddd] [fff] [sss] 12 | * 13 | * where 14 | * 15 | * ooo: opcode 16 | * ddd: destination 17 | * fff: first operand 18 | * sss: second operand 19 | * 20 | * **/ 21 | SC_MODULE(decoder) { 22 | 23 | //-- Signals --// 24 | sc_in> inst; // Instruction 25 | 26 | sc_out> opcode; // OPCODE 27 | sc_out> of1; // Operando fonte 1 28 | sc_out> of2; // Operando fonte 2 29 | sc_out> od; // Operando destino 30 | 31 | /* Method that decodifies the instruction. 32 | * It performs simple arithmetic operations. 33 | * **/ 34 | void decode(); 35 | 36 | /* Constructor. 37 | * */ 38 | SC_CTOR(decoder) { 39 | cout << "New component - Decoder" << endl; 40 | SC_METHOD(decode); 41 | sensitive << inst; 42 | } 43 | }; 44 | 45 | void decoder::decode() { 46 | unsigned long long instruction = inst.read(); 47 | 48 | cout << "Processing instruction " << instruction << endl; 49 | 50 | of2.write(instruction % ((unsigned long long) 1e3)); 51 | instruction /= 1000; 52 | of1.write(instruction % 1000); 53 | instruction /= 1000; 54 | od.write(instruction % 1000); 55 | instruction /= 1000; 56 | opcode.write(instruction); 57 | } 58 | 59 | -------------------------------------------------------------------------------- /processor/components/instruction_register/instruction_register.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | /* Component: Instruction register 4 | * 5 | * Stores the next instruction to be 6 | * executed (or not, considering 7 | * a jump in the pipeline). 8 | * **/ 9 | SC_MODULE(instruction_register){ 10 | 11 | //-- Signals --// 12 | sc_in> instructionIn; 13 | sc_in enable; 14 | sc_in write; 15 | sc_in clock; 16 | sc_out> instructionOut; 17 | 18 | /* Write/read in/from the register. 19 | * * */ 20 | void mem(); 21 | 22 | sc_uint<64> instruction; 23 | 24 | SC_HAS_PROCESS(instruction_register); 25 | 26 | /* Constructor. 27 | * **/ 28 | instruction_register(sc_module_name _name) : sc_module{_name} { 29 | cout << "New component - Instruction Register" << endl; 30 | SC_METHOD(mem); 31 | sensitive << clock.pos(); 32 | } 33 | 34 | }; 35 | 36 | void instruction_register::mem() { 37 | if (enable.read() == 1) { 38 | if (write.read() == 1) { 39 | instruction = instructionIn.read(); 40 | instructionOut.write(instruction); 41 | } else if (write.read() == 0) { 42 | instructionOut.write(instruction); 43 | } 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /processor/components/multiplex/multiplex2.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | /* Multiplexer 2x1. 4 | * 5 | * Used for selecting the value used to 6 | * address the DM when in LD/ST. 7 | **/ 8 | SC_MODULE(multiplex2){ 9 | //-- Signal declarations --// 10 | sc_in> seletor; // Select an input 11 | sc_in> opd; // ULA input 12 | sc_in> of1; // DM input 13 | sc_out> saida; // Out 14 | 15 | /* Method that selects the right input 16 | * according to the selector. 17 | * **/ 18 | void select(); 19 | 20 | /** 21 | * Constructor 22 | */ 23 | SC_CTOR(multiplex2) { 24 | cout << "New component - Multiplexer3" << endl; 25 | SC_METHOD(select); 26 | sensitive << seletor << opd << of1; 27 | } 28 | 29 | }; 30 | 31 | void multiplex2::select() { 32 | if (seletor.read() == 0) { 33 | saida.write(opd.read()); 34 | } else if (seletor.read() == 1) { 35 | int t = of1.read(); 36 | sc_uint<9> a = t; 37 | saida.write(a); 38 | } 39 | } 40 | 41 | -------------------------------------------------------------------------------- /processor/components/multiplex/multiplex3.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | /* Multiplexer 3x1. 4 | * 5 | * Used for selecting the value 6 | * to write in the register base. 7 | **/ 8 | SC_MODULE(multiplex3){ 9 | //-- Signal declarations --// 10 | sc_in> seletor; // Select an input 11 | sc_in> saidaULA; // ULA input 12 | sc_in> dataDM; // DM input 13 | sc_in> immediateData; // Immediate input 14 | sc_out> saida; // Out 15 | 16 | /* Method that selects the right input 17 | * according to the selector. 18 | * **/ 19 | void select(); 20 | 21 | /** 22 | * Constructor 23 | */ 24 | SC_CTOR(multiplex3) { 25 | cout << "New component - Multiplexer3" << endl; 26 | SC_METHOD(select); 27 | sensitive << seletor << immediateData << saidaULA << dataDM; 28 | } 29 | 30 | }; 31 | 32 | void multiplex3::select() { 33 | if (seletor.read() == 0) { 34 | saida.write(saidaULA.read()); 35 | } else if (seletor.read() == 1) { 36 | saida.write(dataDM.read()); 37 | } else if (seletor.read() == 2) { 38 | int t = immediateData.read(); 39 | saida.write(t); 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /processor/components/pipeline_reg/pipeline_reg.h: -------------------------------------------------------------------------------- 1 | #ifndef _PIPELINE_ 2 | #define _PIPELINE_ 3 | 4 | #include "systemc.h" 5 | 6 | SC_MODULE(pipeline_reg) { 7 | 8 | //-- Signals --// 9 | sc_in clock; // Clock 10 | sc_in enable; // Available to read/write 11 | sc_in write; // write if 1; read if 0 12 | sc_in> opcodeIn; // OPCODE 13 | sc_in> of1In; // Operando fonte 1 14 | sc_in> of2In; // Operando fonte 2 15 | sc_in> odIn; // Operando destino 16 | sc_out> opcodeOut; // OPCODE 17 | sc_out> of1Out; // Operando fonte 1 18 | sc_out> of2Out; // Operando fonte 2 19 | sc_out> odOut; // Operando destino 20 | 21 | //-- Method --// 22 | void pipeline_reg_routine(); // Performs RAM's behaviour 23 | 24 | SC_HAS_PROCESS(pipeline_reg); 25 | 26 | //-- Constructor --// 27 | pipeline_reg (sc_module_name _name) : sc_module {_name} { 28 | cout << "New component - Pipeline register" << endl; 29 | SC_THREAD(pipeline_reg_routine); 30 | sensitive << clock.pos(); 31 | }; 32 | 33 | private: 34 | //-- Local --// 35 | int _opcode, _of1, _of2, _od; 36 | 37 | }; 38 | 39 | void pipeline_reg::pipeline_reg_routine() { 40 | while (true) { 41 | wait(); 42 | if (enable.read() == 1) { 43 | if (write.read() == 0) { 44 | opcodeOut.write(_opcode); 45 | of1Out.write(_of1); 46 | of2Out.write(_of2); 47 | odOut.write(_od); 48 | } else { 49 | _opcode = opcodeIn.read(); 50 | _od = odIn.read(); 51 | _of1 = of1In.read(); 52 | _of2 = of2In.read(); 53 | // Write immediately 54 | opcodeOut.write(_opcode); 55 | of1Out.write(_of1); 56 | of2Out.write(_of2); 57 | odOut.write(_od); 58 | } 59 | } 60 | } 61 | } 62 | 63 | #endif 64 | -------------------------------------------------------------------------------- /processor/components/program_counter/program_counter.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | /* Program counter 4 | * 5 | * Keeps a counter, allowing to increase by 1 and load 6 | * a value. Address the instruction memory. 7 | * */ 8 | SC_MODULE(program_counter){ 9 | //-- Signal declarations --// 10 | sc_in_clk clock; 11 | sc_in reset; 12 | sc_in enable; 13 | sc_in load; 14 | sc_out> counter_out; 15 | sc_in> counter_in; 16 | 17 | //-- Local variables --// 18 | sc_uint<8> count = 0; 19 | 20 | //-- The logic --// 21 | void increment() { 22 | if(reset.read() == 1) { 23 | count = 0; 24 | counter_out.write(count); 25 | } else if (enable.read() == 1) { 26 | count = count + 1; 27 | counter_out.write(count); 28 | } else if (load.read() == 1) { 29 | count = counter_in.read(); 30 | counter_out.write(count); 31 | } 32 | } 33 | 34 | //-- Constructor --// 35 | SC_CTOR(program_counter) { 36 | cout << "New component - Program Counter" << endl; 37 | SC_METHOD(increment); 38 | sensitive << reset << clock.pos(); 39 | } 40 | }; 41 | -------------------------------------------------------------------------------- /processor/components/program_counter/test_program_counter: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/processor/components/program_counter/test_program_counter -------------------------------------------------------------------------------- /processor/components/program_counter/test_program_counter.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | #include "program_counter.cpp" 3 | 4 | int sc_main(int argc, char * argv[]) { 5 | 6 | sc_signal clock; 7 | sc_signal enable; 8 | sc_signal reset; 9 | sc_signal > counter_out; 10 | 11 | // Instance 12 | program_counter pc("PC"); 13 | pc.clock(clock); 14 | pc.enable(enable); 15 | pc.reset(reset); 16 | pc.counter_out(counter_out); 17 | 18 | // Open VCD file 19 | sc_trace_file *wf = sc_create_vcd_trace_file("pc"); 20 | sc_trace(wf, clock, "clock"); 21 | sc_trace(wf, reset, "reset"); 22 | sc_trace(wf, enable, "enable"); 23 | sc_trace(wf, counter_out, "counter_out"); 24 | 25 | reset = 0; // Not reset now 26 | enable = 0; // Not counting now 27 | 28 | // Mostrar que mantém 0 29 | for (int i = 0; i < 5; ++i) { 30 | clock = 0; 31 | sc_start(); 32 | clock = 1; 33 | sc_start(); 34 | } 35 | 36 | // Reset! 37 | reset = 1; 38 | cout << sc_time_stamp() << "Asserting reset\n" << endl; 39 | for (int i = 0; i < 10; ++i) { 40 | clock = 0; 41 | sc_start(); 42 | clock = 1; 43 | sc_start(); 44 | } 45 | 46 | // Undoing Reset! 47 | reset = 0; 48 | cout << sc_time_stamp() << "De-asserting reset\n" << endl; 49 | for (int i = 0; i < 5; ++i) { 50 | clock = 0; 51 | sc_start(); 52 | clock = 1; 53 | sc_start(); 54 | } 55 | 56 | // Enable! 57 | enable = 1; 58 | cout << sc_time_stamp() << "Assert enable!\n" << endl; 59 | for (int i = 0; i < 256; ++i) { 60 | clock = 0; 61 | sc_start(); 62 | clock = 1; 63 | sc_start(); 64 | } 65 | 66 | cout << sc_time_stamp() << "De-assert enable!\n" << endl; 67 | enable = 0; 68 | 69 | cout << sc_time_stamp() << "End simulation!\n" << endl; 70 | sc_close_vcd_trace_file(wf); 71 | return 0; 72 | } 73 | -------------------------------------------------------------------------------- /processor/components/ram/ram.h: -------------------------------------------------------------------------------- 1 | #ifndef _RAM_ 2 | #define _RAM_ 3 | 4 | #include "systemc.h" 5 | #include 6 | #include 7 | 8 | template 9 | SC_MODULE(ram) { 10 | 11 | //-- Signals --// 12 | sc_in clock; // Clock 13 | sc_in enable; // Available to read/write 14 | sc_in write; // write if true; read if false 15 | sc_in> address; // Addressing the memory for write/read 16 | sc_in dataIn; // Data to be written/read 17 | sc_out dataOut; 18 | 19 | //-- Method --// 20 | void ram_routine(); // Performs RAM's behaviour 21 | void print(int); 22 | 23 | //-- Local --// 24 | std::string moduleName; // Only for debugging 25 | 26 | SC_HAS_PROCESS(ram); 27 | 28 | //-- Constructor --// 29 | ram (sc_module_name _name) : sc_module {_name} { 30 | cout << "New component - RAM - " << _name << endl; 31 | moduleName = _name; 32 | SC_THREAD(ram_routine); 33 | sensitive << clock.pos(); 34 | // Create memory in memory 35 | ramdata = new sc_signal[TSize]; 36 | } 37 | 38 | //-- Method that loads data into the memory --// 39 | void updateMemory(const std::vector & _data) { 40 | for (int i = 0; i < _data.size(); ++i) { 41 | ramdata[i] = _data[i]; 42 | } 43 | } 44 | 45 | private: 46 | sc_signal * ramdata; // Keeps the data written 47 | 48 | }; 49 | 50 | template 51 | void ram::print(int n) { 52 | for (int i = 0; i < n; ++i) { 53 | cout << "[" << i << "] - " << ramdata[i] << endl; 54 | } 55 | cout << endl; 56 | } 57 | 58 | template 59 | void ram::ram_routine() { 60 | while (true) { 61 | wait(); 62 | if (enable.read() == 1) { 63 | if (write.read() == 1) { 64 | ramdata[address.read()] = dataIn.read(); 65 | } else { 66 | dataOut.write(ramdata[address.read()]); 67 | } 68 | } 69 | } 70 | } 71 | 72 | #endif 73 | -------------------------------------------------------------------------------- /processor/components/ram/tests_ram: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/processor/components/ram/tests_ram -------------------------------------------------------------------------------- /processor/components/ram/tests_ram.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | #include "ram.h" 3 | 4 | int sc_main(int argn, char * argv[]) { 5 | 6 | //const char * inputFile = "in.text"; 7 | 8 | std::vector> initRam; 9 | 10 | ram,256> memRam("MEMRAM", initRam); 11 | 12 | sc_signal clock, enable, write; 13 | sc_signal address; 14 | sc_signal> data; 15 | 16 | memRam.clock(clock); 17 | memRam.enable(enable); 18 | memRam.write(write); 19 | memRam.address(address); 20 | memRam.data(data); 21 | 22 | enable = 0; 23 | write = 0; 24 | address = 9; 25 | data = 0; 26 | 27 | cout << data.read() << endl; 28 | sc_start(0, SC_PS); 29 | clock = 1; 30 | enable = 1; 31 | write = 1; 32 | data.write(0xF); 33 | address.write(0x10); 34 | sc_start(1, SC_PS); 35 | clock = 0; 36 | enable = 0; 37 | sc_start(1, SC_PS); 38 | enable = 1; 39 | write = 0; 40 | address.write(0x10); 41 | sc_start(1, SC_PS); 42 | cout << data.read() << endl; 43 | 44 | 45 | 46 | return 0; 47 | } 48 | -------------------------------------------------------------------------------- /processor/components/register_base/register_base.h: -------------------------------------------------------------------------------- 1 | #ifndef _REGS_ 2 | #define _REGS_ 3 | 4 | #include "systemc.h" 5 | 6 | template 7 | SC_MODULE(register_base) { 8 | 9 | //-- Signals --// 10 | sc_in clock; // Clock 11 | sc_in enable; // Available to read/write 12 | sc_in write; // write if true; read if false 13 | sc_in> addressSource1; // Addressing first operand 14 | sc_in> addressSource2; // Addressing second operand 15 | sc_in> addressDest; // Addressing destination operand 16 | sc_in dataToWrite; // Data to be written 17 | sc_out dataSource1; // Data for the first operand 18 | sc_out dataSource2; // Data for the second operand 19 | 20 | //-- Method --// 21 | void register_base_routine(); // Performs RAM's behaviour 22 | void print(int); 23 | 24 | SC_HAS_PROCESS(register_base); 25 | 26 | //-- Constructor --// 27 | register_base (sc_module_name _name) : sc_module {_name} { 28 | cout << "New component - Register base" << endl; 29 | SC_METHOD(register_base_routine); 30 | sensitive << clock.pos(); 31 | // Create memory in memory 32 | regdata = new sc_signal[TSize]; 33 | }; 34 | 35 | private: 36 | sc_signal * regdata; // Keeps the data written 37 | 38 | }; 39 | 40 | template 41 | void register_base::print(int n) { 42 | for (int i = 0; i < n; ++i) { 43 | cout << "[" << i << "]" << "-" << regdata[i] << endl; 44 | } 45 | cout << endl; 46 | } 47 | 48 | template 49 | void register_base::register_base_routine() { 50 | if (enable.read() == 1) { 51 | if (write.read() == 1) { 52 | regdata[addressDest.read()] = dataToWrite.read(); 53 | } else { 54 | dataSource1.write(regdata[addressSource1.read()]); 55 | dataSource2.write(regdata[addressSource2.read()]); 56 | } 57 | } 58 | } 59 | 60 | #endif 61 | -------------------------------------------------------------------------------- /processor/components/ula/ula.h: -------------------------------------------------------------------------------- 1 | #ifndef _ULA_ 2 | #define _ULA_ 3 | 4 | #include "systemc.h" 5 | 6 | SC_MODULE(ula) { 7 | 8 | //-- Sinais --// 9 | sc_out> saida; 10 | sc_out N; 11 | sc_out Z; 12 | sc_in> a; 13 | sc_in> b; 14 | sc_in> operacao; 15 | sc_in reset; // reset Z e N 16 | 17 | //-- Methods --// 18 | void compute(); 19 | 20 | SC_HAS_PROCESS(ula); 21 | 22 | //-- Constructor --// 23 | ula (sc_module_name _name) : sc_module {_name} { 24 | SC_METHOD(compute); 25 | sensitive << a << b << operacao << reset; 26 | }; 27 | 28 | }; 29 | 30 | 31 | void ula::compute(){ 32 | int ar = a.read(); 33 | int br = b.read(); 34 | int op = operacao.read(); 35 | 36 | if (reset.read() == 1) { 37 | N.write(0); 38 | Z.write(0); 39 | } 40 | 41 | switch(op){ 42 | case 6: 43 | saida.write(ar + br); 44 | break; 45 | case 7: 46 | saida.write(ar - br); 47 | break; 48 | case 5: 49 | if(ar == br) { 50 | saida.write(1); 51 | Z.write(1); 52 | N.write(0); 53 | } 54 | else if(ar < br) { 55 | saida.write(0); 56 | Z.write(0); 57 | N.write(1); 58 | } else { 59 | saida.write(2); 60 | Z.write(0); 61 | N.write(0); 62 | } 63 | break; 64 | case 1: 65 | saida.write(ar & br); 66 | break; 67 | case 2: 68 | saida.write(ar | br); 69 | break; 70 | case 3: 71 | saida.write(ar ^ br); 72 | break; 73 | case 4: 74 | saida.write(~ar); 75 | break; 76 | default: 77 | saida.write(0); 78 | break; 79 | } 80 | } 81 | 82 | #endif 83 | -------------------------------------------------------------------------------- /processor/output.out: -------------------------------------------------------------------------------- 1 | Loading processor... 2 | New component - RAM - IM 3 | New component - RAM - DM 4 | New component - Decoder 5 | New component - Program Counter 6 | New component - Register base 7 | New component - Multiplexer3 8 | New component - Multiplexer3 9 | New component - Pipeline register 10 | New component - Instruction Register 11 | 12 | The processor is ready to work. 13 | ~~~~---------------------------~~~~ 14 | Attempting to find instructions... 15 | -------------------------------------------------------------------------------- /processor/processor.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #include "components/multiplex/multiplex3.cpp" 12 | #include "components/multiplex/multiplex2.cpp" 13 | #include "components/ula/ula.h" 14 | #include "components/program_counter/program_counter.cpp" 15 | #include "components/ram/ram.h" 16 | #include "components/register_base/register_base.h" 17 | #include "components/decoder/decoder.cpp" 18 | #include "components/control/control.cpp" 19 | #include "components/pipeline_reg/pipeline_reg.h" 20 | #include "components/instruction_register/instruction_register.cpp" 21 | 22 | sc_uint<64> instStringToInt(const std::string & inst); 23 | 24 | /* Transform an instruction string in the format 25 | * 26 | * [OPCODE] [OD] [OF1] [OF2] 27 | * 28 | * into a unsigned long long in the format 29 | * 30 | * map[OPCODE][OD][OF1][OF2] 31 | * 32 | * Used for convert a instruction from a file 33 | * to a decodable format. 34 | * */ 35 | sc_uint<64> instStringToInt(const std::string & inst) { 36 | std::map m = { 37 | {"AND",1}, 38 | {"OR", 2}, 39 | {"XOR",3}, 40 | {"NOT",4}, 41 | {"CMP",5}, 42 | {"ADD",6}, 43 | {"SUB",7}, 44 | {"LD", 8}, 45 | {"ST", 9}, 46 | {"J", 10}, 47 | {"JN", 11}, 48 | {"JZ", 12}, 49 | {"LRI",13}}; 50 | sc_uint<64> instInt = 0; 51 | std::stringstream ss (inst); 52 | std::string opcode; 53 | int of1, of2, od; 54 | // Get OPCODE and OD 55 | ss >> opcode >> od; 56 | instInt += od * 1e6; 57 | instInt += m[opcode] * ((long long int) 1e9); 58 | if (opcode == "J" || opcode == "JN" || opcode == "JZ") 59 | return instInt; 60 | // Get OF1 61 | ss >> of1; 62 | instInt += of1 * 1e3; 63 | if (opcode == "ST" || opcode == "LD" || opcode == "LRI") 64 | return instInt; 65 | // Get OF2 66 | ss >> of2; 67 | instInt += of2; 68 | return instInt; 69 | }; 70 | 71 | SC_MODULE(processor) { 72 | 73 | //-- Local --// 74 | std::vector> instructions; 75 | 76 | //-- Components --// 77 | ram,256> IM{"IM"}; // Instruction memory 78 | ram,512> DM{"DM"}; // Data memory 79 | decoder DEC{"DEC"}; // Decoder 80 | program_counter PC{"PC"}; // Program counter 81 | ula ULA{"ULA"}; // ULA 82 | control CONTROL{"CONTROL"}; // Control 83 | register_base,32> REGISTERS{"REGISTERS"}; // Registers 84 | multiplex3 MULTIRB{"MULTIRB"}; 85 | multiplex2 MULTIDM{"MULTIDM"}; 86 | pipeline_reg PIPELINESE{"PIPELINESE"}; // Pipeline register search-exec 87 | instruction_register RI{"INSTREG"}; 88 | 89 | //-- Signals --// 90 | sc_in clock; 91 | 92 | //-> Control signals 93 | sc_signal sigEnableIM; 94 | sc_signal sigWriteIM; 95 | sc_signal> sigInIM; // nothing! 96 | 97 | sc_signal sigEnableCP; 98 | sc_signal sigLoadCP; 99 | sc_signal sigResetCP; 100 | 101 | sc_signal sigEnableDM; 102 | sc_signal sigWriteDM; 103 | 104 | sc_signal sigEnableRI; 105 | sc_signal sigWriteRI; 106 | 107 | sc_signal> sigImmediateValue; 108 | sc_signal> sigImmediateRegister; 109 | 110 | sc_signal sigEnableRB; 111 | sc_signal sigWriteRB; 112 | 113 | sc_signal sigEnableRPL; 114 | sc_signal sigWriteRPL; 115 | sc_signal sigResetRPL; 116 | 117 | sc_signal sigResetZN; 118 | 119 | sc_signal> sigSeletorMultiRBW; 120 | sc_signal> sigSeletorMultiDM; 121 | 122 | //-> Other 123 | sc_signal> sigOpcode; // OPCODE 124 | sc_signal> sigOf1; // Operando fonte 1 125 | sc_signal> sigOf2; // Operando fonte 2 126 | sc_signal> sigOpd; // Operando destino 127 | sc_signal> sigOpcodePipe; // OPCODE 128 | sc_signal> sigOf1Pipe; // Operando fonte 1 129 | sc_signal> sigOf2Pipe; // Operando fonte 2 130 | sc_signal> sigOpdPipe; // Operando destino 131 | sc_signal sigZ; 132 | sc_signal sigN; 133 | 134 | sc_signal> sigInstWordRI; 135 | 136 | sc_signal> sigInstAddress; 137 | sc_signal> sigInstWord; 138 | 139 | sc_signal> sigDataAddressDM; 140 | sc_signal> sigDataDM; 141 | 142 | sc_signal> sigCounterIn; 143 | 144 | sc_signal> sigSaidaULA; 145 | sc_signal> sigAULA; 146 | sc_signal> sigBULA; 147 | 148 | sc_signal> sigSaidaMultiRBW; 149 | 150 | sc_signal> sigSaidaMultiDM; 151 | 152 | 153 | /* Constructor that gets the path for an instruction's 154 | * file and converts them to integer instructions, 155 | * ready for decodification. 156 | * 157 | * Always called when constructing the processor. 158 | * */ 159 | processor(sc_module_name _name, const char * instructionsPath) : sc_module{_name} { 160 | sleep(1); 161 | cout << "\nThe processor is ready to work." << endl; 162 | sleep(1); 163 | 164 | //-- Connections --// 165 | 166 | //-> Control 167 | // In 168 | CONTROL.clock(clock); 169 | CONTROL.opcode(sigOpcodePipe); 170 | CONTROL.of1(sigOf1Pipe); 171 | CONTROL.of2(sigOf2Pipe); 172 | CONTROL.opd(sigOpdPipe); 173 | CONTROL.Z(sigZ); 174 | CONTROL.N(sigN); 175 | // Out 176 | CONTROL.enableIM(sigEnableIM); 177 | CONTROL.writeIM(sigWriteIM); 178 | CONTROL.enableCP(sigEnableCP); 179 | CONTROL.loadCP(sigLoadCP); 180 | CONTROL.resetCP(sigResetCP); 181 | CONTROL.enableDM(sigEnableDM); 182 | CONTROL.writeDM(sigWriteDM); 183 | CONTROL.enableRI(sigEnableRI); 184 | CONTROL.writeRI(sigWriteRI); 185 | CONTROL.immediateValue(sigImmediateValue); 186 | CONTROL.immediateRegister(sigImmediateRegister); 187 | CONTROL.enableRB(sigEnableRB); 188 | CONTROL.writeRB(sigWriteRB); 189 | CONTROL.enableRPL(sigEnableRPL); 190 | CONTROL.writeRPL(sigWriteRPL); 191 | CONTROL.resetRPL(sigResetRPL); 192 | CONTROL.resetZN(sigResetZN); 193 | CONTROL.seletorMultiRBW(sigSeletorMultiRBW); 194 | CONTROL.seletorMultiDM(sigSeletorMultiDM); 195 | CONTROL.jumpValueCP(sigCounterIn); 196 | 197 | //-> Instruction Memory 198 | // In 199 | IM.clock(clock); 200 | IM.enable(sigEnableIM); 201 | IM.write(sigWriteIM); 202 | IM.address(sigInstAddress); 203 | IM.dataIn(sigInIM); 204 | // Out 205 | IM.dataOut(sigInstWordRI); 206 | 207 | //-> Instruction register 208 | // In 209 | RI.clock(clock); 210 | RI.enable(sigEnableRI); 211 | RI.write(sigWriteRI); 212 | RI.instructionIn(sigInstWordRI); 213 | // Out 214 | RI.instructionOut(sigInstWord); 215 | 216 | //-> Data memory 217 | // In 218 | DM.clock(clock); 219 | DM.enable(sigEnableDM); 220 | DM.write(sigWriteDM); 221 | DM.address(sigSaidaMultiDM); 222 | DM.dataIn(sigAULA); 223 | // Out 224 | DM.dataOut(sigDataDM); 225 | 226 | //-> Decoder 227 | // In 228 | DEC.inst(sigInstWord); 229 | // Out 230 | DEC.opcode(sigOpcode); 231 | DEC.of1(sigOf1); 232 | DEC.of2(sigOf2); 233 | DEC.od(sigOpd); 234 | 235 | //-> Program counter 236 | // In 237 | PC.clock(clock); 238 | PC.reset(sigResetCP); 239 | PC.enable(sigEnableCP); 240 | PC.load(sigLoadCP); 241 | PC.counter_in(sigCounterIn); 242 | // Out 243 | PC.counter_out(sigInstAddress); 244 | 245 | //-> Pipeline register 246 | // In 247 | PIPELINESE.clock(clock); 248 | PIPELINESE.enable(sigEnableRPL); 249 | PIPELINESE.write(sigWriteRPL); 250 | PIPELINESE.opcodeIn(sigOpcode); 251 | PIPELINESE.of1In(sigOf1); 252 | PIPELINESE.of2In(sigOf2); 253 | PIPELINESE.odIn(sigOpd); 254 | // Out 255 | PIPELINESE.opcodeOut(sigOpcodePipe); 256 | PIPELINESE.of1Out(sigOf1Pipe); 257 | PIPELINESE.of2Out(sigOf2Pipe); 258 | PIPELINESE.odOut(sigOpdPipe); 259 | 260 | //-> ULA 261 | // In 262 | ULA.reset(sigResetZN); 263 | ULA.a(sigAULA); 264 | ULA.b(sigBULA); 265 | ULA.operacao(sigOpcodePipe); 266 | // Out 267 | ULA.saida(sigSaidaULA); 268 | ULA.N(sigN); 269 | ULA.Z(sigZ); 270 | 271 | //-> Register base 272 | // In 273 | REGISTERS.clock(clock); 274 | REGISTERS.enable(sigEnableRB); 275 | REGISTERS.write(sigWriteRB); 276 | REGISTERS.addressSource1(sigOf1Pipe); 277 | REGISTERS.addressSource2(sigOf2Pipe); 278 | REGISTERS.addressDest(sigOpdPipe); 279 | REGISTERS.dataToWrite(sigSaidaMultiRBW); 280 | // Out 281 | REGISTERS.dataSource1(sigAULA); 282 | REGISTERS.dataSource2(sigBULA); 283 | 284 | //-> Multiplex for write data on register base 285 | // In 286 | MULTIRB.seletor(sigSeletorMultiRBW); 287 | MULTIRB.saidaULA(sigSaidaULA); 288 | MULTIRB.dataDM(sigDataDM); 289 | MULTIRB.immediateData(sigImmediateValue); 290 | // Out 291 | MULTIRB.saida(sigSaidaMultiRBW); 292 | 293 | //-> Multiplex for addressing DM 294 | // In 295 | MULTIDM.seletor(sigSeletorMultiDM); 296 | MULTIDM.opd(sigOpdPipe); 297 | MULTIDM.of1(sigOf1Pipe); 298 | // Out 299 | MULTIDM.saida(sigSaidaMultiDM); 300 | 301 | 302 | //-- Sentivity list --// 303 | sensitive << clock.pos(); 304 | 305 | //-- Instruction's file read system --// 306 | std::ifstream ifs; 307 | std::string inst; 308 | int size = 0; 309 | ifs.open(instructionsPath,std::ifstream::in); 310 | 311 | cout << " ~~~~---------------------------~~~~" << endl; 312 | cout << "Attempting to find instructions..." << endl; 313 | sleep(1); 314 | if (ifs.is_open()) { 315 | cout << "Found! Reading instructions..." << endl; 316 | sleep(1); 317 | while (getline(ifs,inst)) { 318 | std::size_t found = inst.find("#"); 319 | if(found != std::string::npos && found != 0){ 320 | instructions.push_back(instStringToInt(inst.substr(0, found))); 321 | size++; 322 | }else if(found == std::string::npos){ 323 | instructions.push_back(instStringToInt(inst)); 324 | size++; 325 | } 326 | } 327 | cout << "Loading into instruction memory..." << endl; 328 | sleep(1); 329 | IM.updateMemory(instructions); // Update memory 330 | cout << "Done! Instructions to be processed:" << endl; 331 | for (int i = 0; i < instructions.size(); ++i) { 332 | cout << instructions[i] << endl; 333 | } 334 | } else { 335 | cout << "Error! Cannot find file with instructions." << endl; 336 | } 337 | cout << " ~~~~---------------------------~~~~" << endl << endl; 338 | sleep(1); 339 | } 340 | }; 341 | 342 | -------------------------------------------------------------------------------- /processor/processor_run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/processor/processor_run -------------------------------------------------------------------------------- /processor/processor_run.cpp: -------------------------------------------------------------------------------- 1 | #include "systemc.h" 2 | 3 | #include "processor.cpp" 4 | 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | int sc_main(int argn, char * argc[]){ 12 | 13 | cout << "Loading processor..." << endl; 14 | sleep(1); 15 | 16 | processor p("PROC", argc[1]); 17 | 18 | sc_signal clock; 19 | 20 | p.clock(clock); 21 | 22 | int numberCycles = 0; 23 | 24 | while (not sc_end_of_simulation_invoked()) { 25 | clock = 0; 26 | sc_start(1, SC_NS); 27 | clock = 1; 28 | sc_start(1, SC_NS); 29 | numberCycles++; 30 | } 31 | 32 | cout << "\nFinished after " << numberCycles - 4 << " cicles. Final state:\n" << endl; 33 | 34 | cout << "/******* REGISTERS ********/" << endl; 35 | p.REGISTERS.print(10); 36 | cout << "/******* MEMORY ********/" << endl; 37 | p.DM.print(10); 38 | return 0; 39 | } 40 | -------------------------------------------------------------------------------- /processor/run.sh: -------------------------------------------------------------------------------- 1 | ./processor_run $1 2 | -------------------------------------------------------------------------------- /processor/tests/add.test: -------------------------------------------------------------------------------- 1 | ADD 1 1 2 2 | -------------------------------------------------------------------------------- /processor/tests/and.test: -------------------------------------------------------------------------------- 1 | AND 1 1 2 2 | -------------------------------------------------------------------------------- /processor/tests/basic.test: -------------------------------------------------------------------------------- 1 | LRI 0 2 2 | LRI 1 3 3 | ST 0 0 4 | ST 1 1 5 | LD 2 0 6 | LD 3 1 7 | ADD 4 3 2 8 | SUB 5 4 3 9 | AND 6 1 2 10 | OR 7 1 2 11 | XOR 8 1 2 12 | NOT 9 1 13 | -------------------------------------------------------------------------------- /processor/tests/basic2.test: -------------------------------------------------------------------------------- 1 | LRI 0 2 2 | NOT 0 0 3 | -------------------------------------------------------------------------------- /processor/tests/cmp.test: -------------------------------------------------------------------------------- 1 | CMP 1 1 2 2 | -------------------------------------------------------------------------------- /processor/tests/empty.test: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/processor/tests/empty.test -------------------------------------------------------------------------------- /processor/tests/fib_5.test: -------------------------------------------------------------------------------- 1 | # FIBONACCI - Encontrar o n-ésimo elemento de fibonacci 2 | LRI 3 1 # Registrador 3 iniciado com o primeiro valor da sequencia 3 | LRI 6 0 # Registrador 6 com valor 0 para auxílio 4 | LRI 7 1 # Registrador 7 com valor 1 para auxílio 5 | LRI 1 0 # Registrador 1 representa o valor anterior 6 | LRI 2 1 # Registrador 2 representa o valor atual 7 | LRI 4 1 # Registrador 4 Contador de loop 8 | LRI 5 10 # Registrador 5(ONDE SE DEFINE O N-ÉSIMO TERMO DESEJADO) 9 | SUB 5 5 7 # Subtração em R5, de R5 - R7 10 | CMP 9 5 4 # Comparação em R9, de R5 e R4 11 | JN 15 # Caso R5 < R4, o código pula para linha 15 12 | ADD 3 1 2 # Adição em R3, de R1 + R2 13 | ADD 1 6 2 # Adição em R1, de R6 + R2 14 | ADD 2 6 3 # Adição em R2, de R6 + R3 15 | ADD 4 7 4 # Adição em R4, de R7 + R4 16 | J 8 # Pula o código para linha 8 17 | ST 1 3 # Armazena na posição 1 da memória o valor de R3 18 | -------------------------------------------------------------------------------- /processor/tests/j.test: -------------------------------------------------------------------------------- 1 | J 5 2 | -------------------------------------------------------------------------------- /processor/tests/jn.test: -------------------------------------------------------------------------------- 1 | JN 5 2 | -------------------------------------------------------------------------------- /processor/tests/jz.test: -------------------------------------------------------------------------------- 1 | JZ 5 2 | -------------------------------------------------------------------------------- /processor/tests/ld.test: -------------------------------------------------------------------------------- 1 | LD 3 1 2 | -------------------------------------------------------------------------------- /processor/tests/lri.test: -------------------------------------------------------------------------------- 1 | LRI 1 2 2 | LRI 2 2 3 | -------------------------------------------------------------------------------- /processor/tests/multiplica3x6.test: -------------------------------------------------------------------------------- 1 | LRI 1 3 2 | LRI 2 6 3 | LRI 3 1 4 | LRI 4 0 5 | LRI 5 0 6 | CMP 9 4 1 7 | JZ 10 8 | ADD 5 5 2 9 | SUB 1 1 3 10 | J 5 11 | ST 1 5 12 | -------------------------------------------------------------------------------- /processor/tests/not.test: -------------------------------------------------------------------------------- 1 | NOT 1 1 2 | -------------------------------------------------------------------------------- /processor/tests/or.test: -------------------------------------------------------------------------------- 1 | OR 1 1 2 2 | -------------------------------------------------------------------------------- /processor/tests/st.test: -------------------------------------------------------------------------------- 1 | ST 5 1 2 | -------------------------------------------------------------------------------- /processor/tests/sub.test: -------------------------------------------------------------------------------- 1 | SUB 1 1 2 2 | -------------------------------------------------------------------------------- /processor/tests/sum24.test: -------------------------------------------------------------------------------- 1 | LRI 1 2 2 | LRI 2 4 3 | ADD 3 1 2 4 | ST 1 3 5 | -------------------------------------------------------------------------------- /processor/tests/xor.test: -------------------------------------------------------------------------------- 1 | XOR 1 1 2 2 | -------------------------------------------------------------------------------- /report/.stub: -------------------------------------------------------------------------------- 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Emergency stop. 8 | <*> slides2.tex 9 | 10 | End of file on the terminal! 11 | 12 | 13 | Here is how much of TeX's memory you used: 14 | 3 strings out of 495004 15 | 108 string characters out of 6180662 16 | 46034 words of memory out of 5000000 17 | 3325 multiletter control sequences out of 15000+600000 18 | 3640 words of font info for 14 fonts, out of 8000000 for 9000 19 | 16 hyphenation exceptions out of 8191 20 | 0i,0n,0p,1b,6s stack positions out of 5000i,500n,10000p,200000b,80000s 21 | ! ==> Fatal error occurred, no output PDF file produced! 22 | -------------------------------------------------------------------------------- /slide/Slide2/.lpr.tex.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/slide/Slide2/.lpr.tex.swp -------------------------------------------------------------------------------- /slide/Slide2/abntex2-modelo-references.bib: -------------------------------------------------------------------------------- 1 | %% This BibTeX bibliography file was created using BibDesk. 2 | %% http://bibdesk.sourceforge.net/ 3 | 4 | %% Saved with string encoding Unicode (UTF-8) 5 | @article{Anagnostopoulos2014, 6 | abstract = {With the rapid development of public transportation system, automatic identification of vehicles become more and more practical in many applications during the past two decades. Nowadays, Intelligent Transportation Systems (ITS) are having a wide impact in people?s life as their scope is to improve transportation safety and mobility and to enhance productivity through the use of advanced technologies. ITS are divided into intelligent infrastructure systems and intelligent vehicle systems. A computer vision and character recognition algorithm for license plate recognition can be used as a core for intelligent infrastructure like electronic payment systems (toll payment, parking fee payment), freeway and arterial management systems for traffic surveillance. Moreover, as increased security awareness has made the need for vehicle based authentication technologies extremely significant the proposed system may be employed as access control system for monitoring of unauthorized vehicles entering private areas.}, 7 | affiliation = {Cultural Technology and Communication Department, University of the Aegean, Greece}, 8 | author = {Anagnostopoulos, Christos-Nikolaos E.}, 9 | doi = {10.1109/MITS.2013.2292652}, 10 | journal = {IEEE Intelligent Transportation Systems Magazine}, 11 | keywords = {Tutorials; Public transportation; Cameras; Charge coupled devices; Identification; Image color analysis; Character recognition}, 12 | language = {Undetermined}, 13 | number = {1}, 14 | pages = {59 - 67}, 15 | title = {License Plate Recognition: A Brief Tutorial}, 16 | volume = {6}, 17 | year = {2014} 18 | } 19 | 20 | @book{Allan, 21 | AUTHOR = {A{\"u}llan Almeida Dieguez}, 22 | TITLE = {{Reconhecimento de Caracteres de Placa Veicular Usando Redes Neurais}}, 23 | YEAR = {2010}, 24 | PUBLISHER = {Escola Politécnica – Departamento de Eletrônica e de Computação} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /slide/Slide2/conclusao.tex: -------------------------------------------------------------------------------- 1 | \begin{frame} 2 | \frametitle{Conclusão} 3 | \end{frame} 4 | -------------------------------------------------------------------------------- /slide/Slide2/ficticio.tex: -------------------------------------------------------------------------------- 1 | \subsection[Subsection]{Descrição do problema} 2 | \begin{frame} 3 | \frametitle{Descrição do problema} 4 | 5 | O problema consiste em um conjunto de dados de dimensão 6 com 150 instâncias, 6 | ou seja, é uma matriz $150 \times 6$. As seis variáveis estão relacionadas a três targets, A, B e 7 | C, e se encontram distribuídas desta forma: 8 | 9 | \begin{itemize} 10 | \item \textbf{Linhas 1 a 50:} Target A; 11 | \item \textbf{Linhas 51 a 100:} Target B; 12 | \item \textbf{Linhas 101 a 150:} Target C. 13 | \end{itemize} 14 | \end{frame} 15 | 16 | \subsection[Subsection]{Medidas de tendência central e distribuição} 17 | \begin{frame}[shrink=30] 18 | \frametitle{Medidas de tendência central} 19 | 20 | \vspace{3em} 21 | 22 | \begin{table} 23 | \begin{tabular}{ l | c | c | c | c | c | c } 24 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 & V6 \\ \hline \hline 25 | \textbf{Médias} & -1.4572e-15 & -1.6383e-15 & -1.2923e-15 & -5.5437e-16 & 1.6017e-15 & 3.0790e-16 \\ 26 | \end{tabular} 27 | \caption{Média aritmética} 28 | \end{table} 29 | 30 | \begin{table} 31 | \begin{tabular}{ l | c | c | c | c | c | c } 32 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 & V6 \\ \hline \hline 33 | \textbf{Medianas} & -0.052331 & -0.131539 & 0.335354 & 0.132067 & -0.259902 & -0.444690 \\ 34 | \end{tabular} 35 | \caption{Mediana} 36 | \end{table} 37 | 38 | \begin{table} 39 | \begin{tabular}{ l | c | c | c | c | c | c } 40 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 & V6 \\ \hline \hline 41 | \textbf{Modas} & -1.01844 & -0.13154 & -1.33575 & -1.31105 & -0.53542 & -0.44469 \\ 42 | \end{tabular} 43 | \caption{Moda} 44 | \end{table} 45 | 46 | \end{frame} 47 | 48 | \begin{frame}[shrink=30] 49 | \frametitle{Medidas de distribuição} 50 | \vspace{3em} 51 | \begin{table} 52 | \begin{tabular}{ l | c | c | c | c | c | c } 53 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 & V6 \\ \hline \hline 54 | \textbf{Desvios absolutos médios} & 0.83031 & 0.77267 & 0.88526 & 0.86342 & 0.85385 & 0.87463 \\ 55 | \end{tabular} 56 | \caption{Desvio absoluto médio} 57 | \end{table} 58 | 59 | \begin{table} 60 | \begin{tabular}{ l | c | c | c | c | c | c } 61 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 & V6 \\ \hline \hline 62 | \textbf{Variâncias} & 1 & 1 & 1 & 1 & 1 & 1 \\ 63 | \end{tabular} 64 | \caption{Variância} 65 | \end{table} 66 | 67 | \begin{table} 68 | \begin{tabular}{ l | c | c | c | c | c | c } 69 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 & V6 \\ \hline \hline 70 | \textbf{Desvios padrões} & 1 & 1 & 1 & 1 & 1 & 1 \\ 71 | \end{tabular} 72 | \caption{Desvio padrão} 73 | \end{table} 74 | 75 | \end{frame} 76 | 77 | \subsection[Subsection]{Grau de normalidade, assimetria, curtose e correlação} 78 | \begin{frame}[shrink=30] 79 | \frametitle{Grau de normalidade} 80 | \vspace{3em} 81 | \begin{figure}[!tbp] 82 | \centering 83 | \begin{minipage}[b]{0.25\textwidth} 84 | \includegraphics[width=\textwidth]{NormPlot_V1.jpg} 85 | \caption{Q-Q Plot V1} 86 | \end{minipage} 87 | \begin{minipage}[b]{0.25\textwidth} 88 | \includegraphics[width=\textwidth]{NormPlot_V2.jpg} 89 | \caption{Q-Q Plot V2} 90 | \end{minipage} 91 | \begin{minipage}[b]{0.25\textwidth} 92 | \includegraphics[width=\textwidth]{NormPlot_V3.jpg} 93 | \caption{Q-Q Plot V3} 94 | \end{minipage} 95 | \begin{minipage}[b]{0.25\textwidth} 96 | \includegraphics[width=\textwidth]{NormPlot_V4.jpg} 97 | \caption{Q-Q Plot V4} 98 | \end{minipage} 99 | \begin{minipage}[b]{0.25\textwidth} 100 | \includegraphics[width=\textwidth]{NormPlot_V5.jpg} 101 | \caption{Q-Q Plot V5} 102 | \end{minipage} 103 | \begin{minipage}[b]{0.25\textwidth} 104 | \includegraphics[width=\textwidth]{NormPlot_V6.jpg} 105 | \caption{Q-Q Plot V6} 106 | \end{minipage} 107 | \end{figure} 108 | 109 | \end{frame} 110 | 111 | \begin{frame}[shrink=30] 112 | \frametitle{Grau de assimetria e curtose} 113 | 114 | \vspace{3em} 115 | 116 | \begin{table} 117 | \begin{tabular}{ l | c | c | c | c | c } 118 | \textbf{Variável} & $\bar{x}$ & $x_{mo}$ & s & AS & Assimetria \\ \hline \hline 119 | \textbf{V1} & -1.4572e-15 & -1.0184e+00 & 1.0000e+00 & 1.01844e+00 & positiva \\ 120 | \textbf{V2} & -1.6383e-15 & -1.3154e-01 & 1.0000e+00 & 1.3154e-01 & negativa \\ 121 | \textbf{V3} & -1.2923e-15 & -1.3358e+00 & 1.0000e+00 & 1.3358e+00 & positiva \\ 122 | \textbf{V4} & -5.5437e-16 & -1.3111e+00 & 1.0000e+00 & 1.3111e+00 & positiva \\ 123 | \textbf{V5} & 1.6017e-15 & -5.3542e-01 & 1.0000e+00 & 5.3542e-01 & negativa 124 | \end{tabular} 125 | \caption{Grau de assimetria} 126 | \end{table} 127 | 128 | \begin{table} 129 | \begin{tabular}{ l | c | c | c | c | c } 130 | \textbf{Variáveis} & V1 & V2 & V3 & V4 & V5 \\ \hline \hline 131 | \textbf{Grau} & 2.4264 & 3.1810 & 1.6045 & 1.6639 & 2.1943 \\ 132 | \end{tabular} 133 | \caption{Grau de curtose das variáveis} 134 | \end{table} 135 | 136 | \end{frame} 137 | 138 | \begin{frame}[shrink=30] 139 | \frametitle{Grau de correlação} 140 | \vspace{3em} 141 | \begin{equation*} 142 | \begin{bmatrix} 143 | 1.000000 & -0.117570 & 0.871754 & 0.817941 & -0.448685 & 0.136343 & 0.782561 \\ 144 | -0.117570 & 1.000000 & -0.428440 & -0.366126 & 0.648175 & 0.079311 & -0.426658 \\ 145 | 0.871754 & -0.428440 & 1.000000 & 0.962865 & -0.828920 & 0.075906 & 0.949035 \\ 146 | 0.817941 & -0.366126 & 0.962865 & 1.000000 & -0.822567 & 0.088966 & 0.956547 \\ 147 | -0.448685 & 0.648175 & -0.828920 & -0.822567 & 1.000000 & 0.016014 & -0.837950 \\ 148 | 0.136343 & 0.079311 & 0.075906 & 0.088966 & 0.016014 & 1.000000 & 0.104404 \\ 149 | 0.782561 & -0.426658 & 0.949035 & 0.956547 & -0.837950 & 0.104404 & 1.000000 150 | \end{bmatrix} 151 | \end{equation*} 152 | 153 | \begin{block}{Descrição} 154 | A matriz acima representa a matriz de correlações das variáveis V1 à V6 (\textbf{normalizadas}) com \emph{targets}. Substituíram-se os \emph{targets} (\textit{A,B,C}) pelos números (\textit{1,2,3}), os quais foram incluídos em uma sétima coluna na matriz das variáveis normalizadas. 155 | \end{block} 156 | 157 | \end{frame} 158 | 159 | \subsection[Subsection]{Resolução do problema} 160 | \begin{frame} 161 | 162 | \frametitle{Resolução do problema - 1 variável} 163 | 164 | \begin{figure}[!tbp] 165 | \begin{minipage}[b]{0.45\textwidth} 166 | \includegraphics[width=\textwidth]{UniTargetPlot_V3.jpg} 167 | \caption{Plot V3} 168 | \end{minipage} 169 | \begin{minipage}[b]{0.45\textwidth} 170 | \includegraphics[width=\textwidth]{UniTargetPlot_V4.jpg} 171 | \caption{Plot V4} 172 | \end{minipage} 173 | \end{figure} 174 | 175 | \begin{block}{Análise} 176 | Ao analisar os gráficos, é possível perceber que as variáveis \textit{V3 e V4} podem solucionar o problema, pois conseguem delimitar as regiões de cada \textit{target} com poucas sobreposições. 177 | \end{block} 178 | 179 | \end{frame} 180 | 181 | \begin{frame}[shrink=30] 182 | \frametitle{Resolução do problema - 2 variáveis} 183 | 184 | \begin{block}{Análise} 185 | Neste caso, os pares de variáveis que podem resolver o problema são: 186 | (\textit{V1,V3}), (\textit{V1,V4}), (\textit{V1,V5}), (\textit{V2,V3}), (\textit{V2,V4}), (\textit{V3,V4}), (\textit{V3,V5}) e (\textit{V4,V5}). 187 | \end{block} 188 | \begin{figure}[!tbp] 189 | \centering 190 | \begin{minipage}[b]{0.3\textwidth} 191 | \includegraphics[width=\textwidth]{BiTargetPlot_V1V3.jpg} 192 | \caption{Plot V1-V3} 193 | \end{minipage} 194 | \begin{minipage}[b]{0.3\textwidth} 195 | \includegraphics[width=\textwidth]{BiTargetPlot_V1V4.jpg} 196 | \caption{Plot V1-V4} 197 | \end{minipage} 198 | \begin{minipage}[b]{0.3\textwidth} 199 | \includegraphics[width=\textwidth]{BiTargetPlot_V1V5.jpg} 200 | \caption{Plot V1-V5} 201 | \end{minipage} 202 | \begin{minipage}[b]{0.3\textwidth} 203 | \includegraphics[width=\textwidth]{BiTargetPlot_V2V3.jpg} 204 | \caption{Plot V2-V3} 205 | \end{minipage} 206 | \end{figure} 207 | 208 | \end{frame} 209 | 210 | \begin{frame}[shrink=30] 211 | \frametitle{Resolução do problema - 2 variáveis} 212 | 213 | \begin{figure}[!tbp] 214 | \centering 215 | 216 | \begin{minipage}[b]{0.3\textwidth} 217 | \includegraphics[width=\textwidth]{BiTargetPlot_V2V4.jpg} 218 | \caption{Plot V2-V4} 219 | \end{minipage} 220 | \begin{minipage}[b]{0.3\textwidth} 221 | \includegraphics[width=\textwidth]{BiTargetPlot_V3V4.jpg} 222 | \caption{Plot V3-V4} 223 | \end{minipage} 224 | \begin{minipage}[b]{0.3\textwidth} 225 | \includegraphics[width=\textwidth]{BiTargetPlot_V3V5.jpg} 226 | \caption{Plot V3-V5} 227 | \end{minipage} 228 | \begin{minipage}[b]{0.3\textwidth} 229 | \includegraphics[width=\textwidth]{BiTargetPlot_V4V5.jpg} 230 | \caption{Plot V4-V5} 231 | \end{minipage} 232 | 233 | \end{figure} 234 | 235 | \end{frame} 236 | 237 | 238 | 239 | -------------------------------------------------------------------------------- /slide/Slide2/img/F.jpg: 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Anagnostopoulos. 5 | \newblock License plate recognition: A brief tutorial. 6 | \newblock {\em IEEE Intelligent Transportation Systems Magazine}, 6(1):59 -- 7 | 67, 2014. 8 | 9 | \bibitem{Allan} 10 | A.~A. Dieguez. 11 | \newblock {\em {Reconhecimento de Caracteres de Placa Veicular Usando Redes 12 | Neurais}}. 13 | \newblock Escola Politécnica – Departamento de Eletrônica e de 14 | Computação, 2010. 15 | 16 | \end{thebibliography} 17 | -------------------------------------------------------------------------------- /slide/Slide2/slides1.blg: -------------------------------------------------------------------------------- 1 | This is BibTeX, Version 0.99d (TeX Live 2013/Debian) 2 | Capacity: max_strings=35307, hash_size=35307, hash_prime=30011 3 | The top-level auxiliary file: slides1.aux 4 | The style file: abbrv.bst 5 | Database file #1: abntex2-modelo-references.bib 6 | You've used 2 entries, 7 | 2118 wiz_defined-function locations, 8 | 511 strings with 4084 characters, 9 | and the built_in function-call counts, 522 in all, are: 10 | = -- 48 11 | > -- 14 12 | < -- 0 13 | + -- 6 14 | - -- 4 15 | * -- 31 16 | := -- 95 17 | add.period$ -- 6 18 | call.type$ -- 2 19 | change.case$ -- 7 20 | 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4 5 | \BOOKMARK [2][]{Outline0.5}{Conclus\365es}{}% 5 6 | -------------------------------------------------------------------------------- /slide/Slide2/slides2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/greati/processor_risc/47ec11060a218640816d4e34d6975b6d3e00fff5/slide/Slide2/slides2.pdf -------------------------------------------------------------------------------- /slide/Slide2/slides2.snm: -------------------------------------------------------------------------------- 1 | \beamer@slide {tab:inst}{4} 2 | \beamer@slide {tab:insttest}{22} 3 | \beamer@slide {tab:resultados}{26} 4 | -------------------------------------------------------------------------------- /slide/Slide2/slides2.tex: -------------------------------------------------------------------------------- 1 | \documentclass{beamer} 2 | 3 | \usepackage[utf8]{inputenc} 4 | \usepackage[portuguese]{babel} 5 | \usepackage{lipsum} 6 | \usepackage{amsmath} 7 | \usepackage{tikz} 8 | \usepackage{multicol} 9 | \usepackage{multirow} 10 | \usepackage[skins]{tcolorbox} 11 | \usepackage{longtable} 12 | \usepackage{booktabs} 13 | \usepackage{ltablex} 14 | \usepackage{listings} 15 | 16 | 17 | \DeclareUnicodeCharacter{00A0}{~} 18 | 19 | \usetheme{Darmstadt} % http://tex.stackexchange.com/questions/177042/beamer-latex-customized-formats 20 | \useoutertheme[subsection=false,footline=authortitle]{miniframes} 21 | % RGB scaled on 0-255 scale (section 17.1.1), colors pulled from title block 22 | \usecolortheme[RGB={8, 80, 135}]{structure} 23 | 24 | \title{Processador RISC} 25 | \subtitle{Projeto e implementação em SystemC} 26 | \author[Greati,Vinicius,Artur]{Vitor Greati \inst{1} \and Vinicius Campos\inst{1} \and Artur Curinga\inst{1}} 27 | \institute{ 28 | \inst{1} 29 | Instituto Metrópole Digital\\ 30 | UFRN 31 | } 32 | \date{Dezembro, 2016} 33 | \subject{Organização e Arquitetura de Computadores} 34 | 35 | \AtBeginSection[] 36 | { 37 | \begin{frame} 38 | \frametitle{Conteúdo} 39 | \tableofcontents[currentsection,currentsubsection] 40 | \end{frame} 41 | } 42 | 43 | \graphicspath{{img/}} 44 | 45 | \begin{document} 46 | 47 | \frame{\titlepage} 48 | 49 | \section{Projeto} 50 | \begin{frame}{Palavra de instrução} 51 | 52 | A programação consiste na listagem de instruções no formato: 53 | 54 | \begin{center} 55 | \begin{tabular}{|c|c|c|c|} 56 | \hline 57 | OPCODE & OD & F1 & F2\\ 58 | 4 bits & 9 bits & 9 bits & 9 bits\\ 59 | \hline 60 | \end{tabular} 61 | \end{center} 62 | 63 | Onde: 64 | 65 | \begin{description} 66 | \item [OPCODE] Código da operação 67 | \item [OD] Operando Destino (D) 68 | \item [F1] Operando Fonte 1 (F1) 69 | \item [F2] Operando Fonte 2 (F2) 70 | \end{description} 71 | \end{frame} 72 | 73 | \begin{frame}{Conjunto de instruções} 74 | 75 | \begin{table}[H] 76 | \footnotesize 77 | \centering 78 | \begin{tabular}{l | p{6cm} | l} 79 | Instrução & Ação & Exemplo\\ 80 | \hline 81 | LRI & $R[D] \leftarrow F1$ & LRI 1 27\\ 82 | AND & $D \leftarrow F1 \& F2$ & AND 1 2 3\\ 83 | OR & $D \leftarrow F1 | F2$ & OR 1 2 3\\ 84 | XOR & $D \leftarrow F1 \wedge F2$ & XOR 1 2 3\\ 85 | NOT & $D \leftarrow \bar{F1}$ & NOT 1 2\\ 86 | CMP & Z = 1, se $F1==F2$; N = 1, se $F1 < F2$; R[OD] = 0, se $F1 < F2$; R[OD] = 1, se $F1 == F2$, R[OD] = 2, se $F1 > F2$ & CMP 1 2 3\\ 87 | ADD & $R[D] \leftarrow F1 + F2$ & ADD 1 2 3\\ 88 | SUB & $R[D] \leftarrow F1 - F2$ & SUB 1 2 3\\ 89 | LD & $R[D] \leftarrow MEM[F1]$ & LD 1 2\\ 90 | ST & $MEM[D] \leftarrow R[F1]$ & ST 1 2\\ 91 | J & $CP \leftarrow F1$ & J 23\\ 92 | JN & $CP \leftarrow F1 \text{ if } N == 1$ & JN 23\\ 93 | JZ & $CP \leftarrow F1 \text{ if } Z == 1$ & JZ 23\\ 94 | \end{tabular} 95 | \label{tab:inst} 96 | \caption{Conjunto de instruções.} 97 | \end{table} 98 | \end{frame} 99 | 100 | \begin{frame}{Modos de endereçamento} 101 | 102 | Permitem-se três modos de endereçamento: 103 | 104 | \begin{block}{Direto} 105 | É fornecido o endereço da memória de dados 106 | que se deseja manipular. Apenas instruções \textbf{LD} e \textbf{ST} podem referenciar diretamente a memória. 107 | \end{block} 108 | 109 | \begin{block}{Registrador direto} 110 | É fornecido o endereço do 111 | registrador com que se deseja trabalhar. 112 | \end{block} 113 | 114 | \begin{block}{Registrador imediato} 115 | É fornecido o endereço 116 | do registrador e um valor imediato a ser inserido 117 | nele. 118 | \end{block} 119 | 120 | \end{frame} 121 | 122 | \begin{frame}{Memórias} 123 | 124 | \begin{block}{Registradores} 125 | Há 32 registradores disponíveis para palavras de 32 bits. 126 | \end{block} 127 | 128 | \begin{block}{Memória de instruções} 129 | 256 palavras de 32 bits. 130 | \end{block} 131 | 132 | \begin{block}{Memória de dados} 133 | 512 palavras de 32 bits. 134 | \end{block} 135 | 136 | \end{frame} 137 | 138 | \begin{frame}{Barramentos} 139 | \begin{block}{Controle} 140 | Transmite os sinais de controle para 141 | a parte operativa. 142 | \end{block} 143 | 144 | \begin{block}{Dados} 145 | Transmite as palavras de dados de 32 bits. 146 | \end{block} 147 | 148 | \begin{block}{Endereços} 149 | Transmite os endereços utilizados nas 150 | leituras e escritas em memória, com largura de 8 bits. 151 | \end{block} 152 | \end{frame} 153 | 154 | \begin{frame}{Pipeline} 155 | \begin{itemize} 156 | \item<1-> Apenas dois estágios: entre a busca e a execução; 157 | \item<2-> Um registrador guarda a palavra de instrução decodificada; 158 | \item<3-> É pessimista: sempre que ocorre uma intrução de \emph{jump}, 159 | desconsidera a instrução pré-carregada; 160 | \item<4-> Ainda que simples, demonstrou redução visível nos ciclos, como 161 | mostrado nos testes mais adiante. 162 | \end{itemize} 163 | \end{frame} 164 | 165 | 166 | \section{Diagramas} 167 | 168 | \begin{frame}{Parte operativa} 169 | \begin{figure}[H] 170 | \centering 171 | \includegraphics[scale=0.4]{img/procdiag} 172 | \end{figure} 173 | \end{frame} 174 | 175 | \begin{frame}{Parte de controle} 176 | 177 | {\footnotesize 178 | A parte de controle consiste em um bloco que recebe a palavra de instrução decodificada 179 | e utiliza uma máquina de estados para gerar os sinais de controle adequados 180 | a cada microinstrução. 181 | } 182 | \begin{figure}[H] 183 | \centering 184 | \includegraphics[scale=0.5]{img/statediag} 185 | \end{figure} 186 | 187 | \end{frame} 188 | 189 | \begin{frame}{Estados} 190 | A tabela abaixo descreve o que ocorre em cada estado: 191 | 192 | \begin{table}[H] 193 | \footnotesize 194 | \centering 195 | \begin{tabular}{l | p{7cm}} 196 | Estado & Ações\\ 197 | \hline 198 | 0 & Prepara para escrever a instrução no barramento.\\ 199 | 1 & Prepara para escrever a instrução no RI.\\ 200 | 2 & Caso o pipeline não seja reiniciado, prepara para escrever no 201 | registrador de pipeline. Caso seja, envia para o estado 0.\\ 202 | 3 & Desabilita escrita no pipeline, prepara nova instrução para o 203 | barramento do RI (pipelining).\\ 204 | 4 & Prepara a execução da instrução de fato e a escrita no RI da 205 | próxima instrução (pipelining).\\ 206 | 6 & Desabilita sinais após a execucação da ULA.\\ 207 | 7 & Desabilita sinais após a escrita na memória.\\ 208 | 8 & Desabilita escrita no CP e envia para o estado 2, para 209 | reiniciar o processo.\\ 210 | 9 & Desabilita sinais após guardar os resultados no banco de registradores.\\ 211 | 10 & Prepara execução da operação de LD.\\ 212 | \hline 213 | \end{tabular} 214 | \end{table} 215 | \end{frame} 216 | 217 | \section{Implementação} 218 | 219 | \begin{frame}{Implementação} 220 | \begin{itemize} 221 | \item<1-> Biblioteca SystemC 2.3.1; 222 | \item<2-> Cada módulo implementado separadamente, mantendo boa organização; 223 | \item<3-> O programa recebe um arquivo com um algoritmo escrito segundo as 224 | instruções da arquitetura; 225 | \item<4-> Para executar: 226 | {\ttfamily ./processador\_run instrucoes.txt} 227 | \end{itemize} 228 | \end{frame} 229 | 230 | \section{Testes} 231 | \begin{frame}{Execuções individuais} 232 | Primeiro, testamos cada instrução separadamente, obtendo o número de ciclos 233 | que cada uma toma, \textbf{considerando a identificação de parada}: 234 | 235 | \begin{table}[H] 236 | \footnotesize 237 | \centering 238 | \begin{tabular}{l | r} 239 | Instrução & Ciclos\\ 240 | \hline 241 | AND & 9\\ 242 | OR & 9\\ 243 | XOR & 9\\ 244 | NOT & 9\\ 245 | CMP & 9\\ 246 | ADD & 9\\ 247 | SUB & 9\\ 248 | LD & 9\\ 249 | ST & 9\\ 250 | J & 11\\ 251 | JN & 11\\ 252 | JZ & 11\\ 253 | LRI & 9\\ 254 | \end{tabular} 255 | \label{tab:insttest} 256 | \caption{Ciclos para cada instrução.} 257 | \end{table} 258 | \end{frame} 259 | 260 | \begin{frame}{Algoritmos para testes} 261 | Para testar o funcionamento do processador e do pipeline, os seguintes algoritmos foram utilizados:\\ 262 | \begin{block}{3x6} 263 | {\footnotesize 264 | LRI 1 3\\ 265 | LRI 2 6\\ 266 | LRI 3 1\\ 267 | LRI 4 0\\ 268 | LRI 5 0\\ 269 | CMP 9 4 1\\ 270 | JZ 10\\ 271 | ADD 5 5 2\\ 272 | SUB 1 1 3\\ 273 | J 5\\ 274 | ST 1 5\\ 275 | } 276 | \end{block} 277 | \end{frame} 278 | 279 | \begin{frame}{Algoritmos para testes} 280 | 281 | Computa o décimo elemento da sequência de Fibonacci e o armazena na memória:\\ 282 | \begin{block}{Fib(10)} 283 | {\scriptsize 284 | LRI 3 1\\ 285 | LRI 6 0\\ 286 | LRI 7 1\\ 287 | LRI 1 0\\ 288 | LRI 2 1\\ 289 | LRI 4 1\\ 290 | LRI 5 10\\ 291 | SUB 5 5 7\\ 292 | CMP 9 5 4\\ 293 | JN 15\\ 294 | ADD 3 1 2\\ 295 | ADD 1 6 2\\ 296 | ADD 2 6 3\\ 297 | ADD 4 7 4\\ 298 | J 8\\ 299 | ST 1 3\\ 300 | } 301 | \end{block} 302 | \end{frame} 303 | 304 | \begin{frame}{Algoritmos para testes} 305 | Realiza todas as operações lógicas possíveis com o processador 306 | em operandos advindos da memória de dados:\\ 307 | \begin{block}{Logic} 308 | {\footnotesize 309 | LRI 0 2\\ 310 | LRI 1 3\\ 311 | ST 0 0\\ 312 | ST 1 1\\ 313 | LD 2 0\\ 314 | LD 3 1\\ 315 | ADD 4 3 2\\ 316 | SUB 5 4 3\\ 317 | AND 6 1 2\\ 318 | OR 7 1 2\\ 319 | XOR 8 1 2\\ 320 | NOT 9 1\\ 321 | } 322 | \end{block} 323 | 324 | \end{frame} 325 | 326 | \begin{frame}{Resultados dos algoritmos} 327 | \begin{table}[H] 328 | \centering 329 | \begin{tabular}{c | c | c} 330 | 331 | Algoritmo & Ciclos sem pipeline & Ciclos com pipeline\\ 332 | \hline 333 | 3x6 & 149 & 115 \\ 334 | Fib(10) & 492 & 374 \\ 335 | Logic & 82 & 58 \\ 336 | \hline 337 | \end{tabular} 338 | \caption{Resultados de execução dos algoritmos de teste.} 339 | \label{tab:resultados} 340 | \end{table} 341 | \end{frame} 342 | 343 | \section{Conclusões} 344 | \begin{frame}{Conclusões} 345 | \begin{itemize} 346 | \item<1-> Implementou-se um processador simples, mas 347 | funcional, unindo conceitos da disciplina de OAC e de Circuitos 348 | Lógicos; 349 | \item<2-> Ainda com um \emph{pipeline} simplificado, foi visível a 350 | redução no ciclo de instruções, validando o poder dessa técnica; 351 | \item<3-> O projeto consolidou os conceitos 352 | aprendidos nas aulas teóricas, além de mostrar 353 | como se pode descrever \emph{hardware} de forma 354 | ainda mais abstrata. 355 | \end{itemize} 356 | \end{frame} 357 | 358 | \end{document} 359 | -------------------------------------------------------------------------------- /slide/Slide2/slides2.toc: -------------------------------------------------------------------------------- 1 | \beamer@endinputifotherversion {3.36pt} 2 | \select@language {portuguese} 3 | \beamer@sectionintoc {1}{Projeto}{2}{0}{1} 4 | \beamer@sectionintoc {2}{Diagramas}{12}{0}{2} 5 | \beamer@sectionintoc {3}{Implementa\IeC {\c c}\IeC {\~a}o}{16}{0}{3} 6 | \beamer@sectionintoc {4}{Testes}{21}{0}{4} 7 | \beamer@sectionintoc {5}{Conclus\IeC {\~o}es}{27}{0}{5} 8 | -------------------------------------------------------------------------------- /slide/Slide2/slides2.vrb: -------------------------------------------------------------------------------- 1 | \frametitle{Testes} 2 | Para testar o funcionamento do processador e do pipeline, os seguintes algoritmos foram utilizados: 3 | 4 | \begin{lstlisting} 5 | LRI 1 3 6 | LRI 2 6 7 | LRI 3 1 8 | LRI 4 0 9 | LRI 5 0 10 | CMP 9 4 1 11 | JZ 10 12 | ADD 5 5 2 13 | SUB 1 1 3 14 | J 5 15 | ST 1 5 16 | \end{lstlisting} 17 | \end{frame} 18 | 19 | \begin{frame}[fragile]{Testes} 20 | 21 | Computa o décimo elemento da sequência de Fibonacci e o armazena na memória: 22 | 23 | \begin{lstlisting} 24 | LRI 3 1 25 | LRI 6 0 26 | LRI 7 1 27 | LRI 1 0 28 | LRI 2 1 29 | LRI 4 1 30 | LRI 5 10 31 | SUB 5 5 7 32 | CMP 9 5 4 33 | JN 15 34 | ADD 3 1 2 35 | ADD 1 6 2 36 | ADD 2 6 3 37 | ADD 4 7 4 38 | J 8 39 | ST 1 3 40 | \end{lstlisting} 41 | \end{frame} 42 | 43 | \begin{frame}[fragile]{Testes} 44 | Realiza todas as operações lógicas possíveis com o processador 45 | em operandos advindos da memória de dados: 46 | 47 | \begin{lstlisting} 48 | LRI 0 2 49 | LRI 1 3 50 | ST 0 0 51 | ST 1 1 52 | LD 2 0 53 | LD 3 1 54 | ADD 4 3 2 55 | SUB 5 4 3 56 | AND 6 1 2 57 | OR 7 1 2 58 | XOR 8 1 2 59 | NOT 9 1 60 | \end{lstlisting} 61 | \end{frame} 62 | 63 | 64 | 65 | \end{document} 66 | -------------------------------------------------------------------------------- /slide/Slide2/texput.log: -------------------------------------------------------------------------------- 1 | This is pdfTeX, Version 3.14159265-2.6-1.40.16 (TeX Live 2015/Arch Linux) (preloaded format=pdflatex 2015.12.24) 6 DEC 2016 21:56 2 | entering extended mode 3 | restricted \write18 enabled. 4 | %&-line parsing enabled. 5 | **slides2.te 6 | 7 | ! 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