├── Chapters ├── 01_Mux21.aux ├── 01_Mux21.tex ├── 02_Bool.aux ├── 02_Bool.tex ├── 03_Encoder.aux ├── 03_Encoder.tex ├── 04_ALU.aux ├── 04_ALU.tex ├── 05_Vend.aux ├── 05_Vend.tex ├── 06_Counter.aux ├── 06_Counter.tex ├── 07_Timer.aux ├── 07_Timer.tex ├── 08_React.aux ├── 08_React.tex ├── 09_ROM.aux ├── 09_ROM.tex ├── 10_RAM.aux ├── 10_RAM.tex ├── 11_Processor.aux ├── 11_Processor.tex ├── 12_CPU.aux ├── 12_CPU.tex ├── 12_Elevator.aux ├── 13_Elevator.aux ├── 13_Elevator.tex ├── 50_Appendix.aux ├── 50_Appendix.log ├── 50_Appendix.tex ├── 90_Detect.tex ├── Lab Manual Pt 1-Exploring Digital Logic with Logisim-Evolution.docx ├── Quiz_Questions.tex └── my_scraps.tex ├── FrontBackmatter ├── Abstract.tex ├── Acknowledgments.tex ├── Bibliography.tex ├── Colophon.aux ├── Colophon.tex ├── Contents.aux ├── Contents.tex ├── Declaration.tex ├── Dedication.tex ├── DirtyTitlepage.tex ├── Preface.aux ├── Preface.tex ├── Publications.tex ├── StyleGuide.aux ├── StyleGuide.tex ├── Titleback.aux ├── Titleback.tex ├── Titlepage.aux └── Titlepage.tex ├── LICENSE ├── README.md ├── Student_Files ├── Homework │ ├── Lab01_Mux21.circ │ ├── Lab02_Bool.circ │ ├── Lab03_Encoder.circ │ ├── Lab04_ALU.circ │ ├── Lab05_Vend.circ │ ├── Lab06_Counter.circ │ ├── Lab07_Timer.circ │ ├── Lab08_React.circ │ ├── Lab09_ROM.circ │ ├── Lab10_RAM.circ │ ├── Lab11_Processor.circ │ └── Lab12_Elevator.circ └── Supplemental │ ├── Lab02_Eq1_test.txt │ ├── Lab02_Eq2_test.txt │ ├── Lab03_Encoder_test.txt │ ├── Lab04_ALU_Ar_test.txt │ ├── Lab04_ALU_Lo_test.txt │ ├── Lab04_ALU_test.txt │ └── Lab09_ROM.txt ├── classicthesis.sty ├── dl_lab-config.tex ├── dl_lab.aux ├── dl_lab.lof ├── dl_lab.log ├── dl_lab.lol ├── dl_lab.lot ├── dl_lab.out ├── dl_lab.pdf ├── dl_lab.synctex.gz ├── dl_lab.tex ├── dl_lab.toc └── gfx ├── 00_00.png ├── 01-01.PNG ├── 01-02.PNG ├── 01-03.PNG ├── 01-04.PNG ├── 01-05.PNG ├── 01-06.PNG ├── 01-07.PNG ├── 01-08.PNG ├── 02-01.PNG ├── 02-02.PNG ├── 02-03.PNG ├── 02-04.PNG ├── 02-05.PNG ├── 02-06.PNG ├── 02-07.PNG ├── 02-08.PNG ├── 03-01.PNG ├── 03-02.PNG ├── 03-03.PNG ├── 03-04.PNG ├── 03-05.PNG ├── 03-06.PNG ├── 04-01.PNG ├── 04-02.PNG ├── 04-03.PNG ├── 04-04.PNG ├── 05-01.PNG ├── 05-02.PNG ├── 05-03.PNG ├── 05-04.PNG ├── 05-05.PNG ├── 05-06.PNG ├── 06-01.PNG ├── 06-02.PNG ├── 06-03.PNG ├── 06-04.PNG ├── 06-05.PNG ├── 06-06.PNG ├── 06-07.PNG ├── 06-08.PNG ├── 06-09.PNG ├── 06-10.PNG ├── 06-11.PNG ├── 06-12.PNG ├── 07-01.PNG ├── 07-02.PNG ├── 08-01.PNG ├── 09-01.PNG ├── 09-02.PNG ├── 09-03.PNG ├── 09-04.PNG ├── 09-05.PNG ├── 09-06.PNG ├── 09-07.PNG ├── 09-08.PNG ├── 09-09.PNG ├── 09-10.PNG ├── 09-98.PNG ├── 09-99.PNG ├── 10-01.PNG ├── 10-02.PNG ├── 10-03.PNG ├── 10-04.PNG ├── 10-05.PNG ├── 11-01.PNG ├── 11-02.PNG ├── 11-03.PNG ├── 11-04.PNG ├── 11-05.PNG ├── 11-06.PNG ├── 12-01.PNG ├── 13-01.png ├── 50-7400-pinout.PNG ├── 50-7400.PNG ├── 50-7402-pinout.PNG ├── 50-7402.PNG ├── 50-7404-pinout.PNG ├── 50-7404.PNG ├── 50-7408-pinout.PNG ├── 50-7408.PNG ├── 50-7410-pinout.PNG ├── 50-7410.PNG ├── 50-7411.PNG ├── 50-74125.PNG ├── 50-7413.PNG ├── 50-7421.PNG ├── 50-74266.PNG ├── 50-7427.PNG ├── 50-7430.PNG ├── 50-7432.PNG ├── 50-7442.PNG ├── 50-7447.PNG ├── 50-7451.PNG ├── 50-7454.PNG ├── 50-7458.PNG ├── 50-7464.PNG ├── 50-7486.PNG ├── 50-74HC595.jpg ├── 60-06-03.png ├── 60-06-04.PNG ├── 60-06-05.PNG ├── 60-06-06.PNG └── Originals ├── 00_00_Image_Missing.psd └── 01_mux21.circ /Chapters/01_Mux21.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \@writefile{toc}{\contentsline {chapter}{\numberline {1}\spacedlowsmallcaps {Introduction To Logisim-evolution}}{3}{chapter.1}\protected@file@percent } 4 | \@writefile{lof}{\addvspace {10\p@ }} 5 | \@writefile{lot}{\addvspace {10\p@ }} 6 | \@writefile{lol}{\addvspace {10\p@ }} 7 | \def\mph@nr{1} 8 | \@writefile{toc}{\contentsline {section}{\numberline {1.1}Purpose}{3}{section.1.1}\protected@file@percent } 9 | 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/Chapters/03_Encoder.tex: -------------------------------------------------------------------------------- 1 | %******************************************* 2 | % Lab 03: Priority Encoder 3 | %******************************************* 4 | \chapter{Priority Encoder} 5 | 6 | \section{Purpose} 7 | 8 | Often a circuit will receive data from several sources at one time and there must be a way to prioritize those inputs. This circuit creates a simple priority encoder for nine different inputs. This is a fairly simple circuit but is best explained by building and ``playing around'' with it rather than attempting to understand a printed text; thus, the explanation for this lab is somewhat limited. 9 | 10 | \section{Procedure} 11 | 12 | Start \LE and create a subcircuit named \lstinline[columns=fixed]|Encoder|. Open that subcircuit and place 12 \texttt{AND} gates as illustrated in Figure \ref{fig:03-01}. 13 | 14 | \begin{figure}[H] 15 | \centering 16 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/03-01} 17 | \caption{AND Gates} 18 | \label{fig:03-01} 19 | \end{figure} 20 | 21 | The gates have one data bit and these properties: 22 | 23 | \begin{itemize} 24 | \item \textbf{U1}: Five inputs, numbers two, three, and four negated. 25 | \item \textbf{U2}: Four inputs, numbers two and three negated. 26 | \item \textbf{U3}: Three inputs, number two negated. 27 | \item \textbf{U4}: Two inputs, none negated. 28 | \item \textbf{U5}: Four inputs, numbers two and three negated. 29 | \item \textbf{U6}: Four inputs, numbers one and two negated. 30 | \item \textbf{U7-U12}: Two inputs, none negated. 31 | \end{itemize} 32 | 33 | Many of the output signals need to be combined with \texttt{OR} gates and those should be added next, as in Figure \ref{fig:03-02}. Note: U16 is a \texttt{NOR} (\textit{Gates} library) gate. 34 | 35 | \begin{figure}[H] 36 | \centering 37 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/03-02} 38 | \caption{OR Gates Added} 39 | \label{fig:03-02} 40 | \end{figure} 41 | 42 | This encoder is designed to prioritize nine input lines so nine inputs must be added, as illustrated in Figure \ref{fig:03-03}. 43 | 44 | \begin{figure}[H] 45 | \centering 46 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/03-03} 47 | \caption{Inputs Added} 48 | \label{fig:03-03} 49 | \end{figure} 50 | 51 | Wiring this circuit is the most challenging part of the build. As illustrated in Figure \ref{fig:03-04}, the inputs are wired to several different \texttt{AND} gates. 52 | 53 | \begin{figure}[H] 54 | \centering 55 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/03-04} 56 | \caption{Wiring the Encoder} 57 | \label{fig:03-04} 58 | \end{figure} 59 | 60 | Finally, four output ports are added, as illustrated in Figure \ref{fig:03-05}. 61 | 62 | \begin{figure}[H] 63 | \centering 64 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/03-05} 65 | \caption{Nine-line Priority Encoder} 66 | \label{fig:03-05} 67 | \end{figure} 68 | 69 | This circuit is designed to output a \acf{BCD} number, so no further conversion is needed to be able to read the highest priority input line. At this point, the circuit is complete and the \textit{poke} tool can be used to change the inputs and observe how that high input bit drives the outputs. 70 | 71 | To finish the project, open the \lstinline[columns=fixed]|main| circuit and drop the \lstinline[columns=fixed]|Encoder| on the drawing canvas. Add nine inputs and label them \textit{In1} through \textit{In9}. Place a four-bit output labeled \textit{PriOut} and wire the four outputs through a splitter to that output port. To make it easier to read the \ac{BCD} number, connect a Hex Digit Display (\textit{Input/Output} library) to the four-bit bus between the splitter and output port. The completed \lstinline[columns=fixed]|main| circuit is illustrated in Figure \ref{fig:03-06}. 72 | 73 | \begin{figure}[H] 74 | \centering 75 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/03-06} 76 | \caption{Main Circuit} 77 | \label{fig:03-06} 78 | \end{figure} 79 | 80 | In Figure \ref{fig:03-06}, notice that two inputs are selected, \textit{In4} and \textit{In6}. Since \textit{In6} is a higher priority (it is a larger number), the output is set for six and \textit{In4} is ignored. 81 | 82 | \subsection{Testing the Circuit} 83 | 84 | The circuit is now complete. It should be tested by entering various combinations of inputs and observing that the output always displays the highest numbered input. 85 | 86 | \section{Deliverable} 87 | 88 | To receive a grade for this lab, create the Nine-line Priority Encoder circuit as defined in this lab. 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\setcounter{tikztimingtrans}{0} 81 | \setcounter{tikztimingtranspos}{0} 82 | \setcounter{r@tfl@t}{0} 83 | \setcounter{tcbbreakpart}{0} 84 | \setcounter{tcblayer}{0} 85 | \setcounter{FancyVerbLine}{19} 86 | \setcounter{float@type}{16} 87 | \setcounter{listings}{0} 88 | \setcounter{loldepth}{1} 89 | \setcounter{lstlisting}{0} 90 | \setcounter{section@level}{0} 91 | } 92 | -------------------------------------------------------------------------------- /Chapters/04_ALU.tex: -------------------------------------------------------------------------------- 1 | %******************************************* 2 | % Lab 04: ALU 3 | %******************************************* 4 | \chapter{Arithmetic Logic Unit (ALU)}\label{lab04} 5 | 6 | \section{Purpose} 7 | 8 | In this lab you will build an \acf{ALU}. An \ac{ALU} is an important digital logic device used to perform all sorts of arithmetic and logic functions in a circuit. The commercial 74181 \ac{ALU} has two four-bit data inputs along with a one-bit mode (M) and a four-bit select input. Depending on those settings, the device will complete one of the functions listed in Table \ref{tab0301}. 9 | 10 | \begin{table}[H] 11 | \sffamily 12 | \newcommand{\head}[1]{\textcolor{white}{\textbf{#1}}} 13 | \begin{center} 14 | \rowcolors{2}{gray!10}{white} % Color every other line a light gray 15 | \begin{tabular}{ccc} 16 | \rowcolor{black!75} 17 | \head{Select} & \head{Logic (M=1)} &\head{Arithmetic (M=0)} \\ 18 | 0000 & A' & A \\ 19 | 0001 & (A + B)' & A + B \\ 20 | 0010 & A'B & A + B' \\ 21 | 0011 & Logical 0 & minus 1 (2's Comp) \\ 22 | 0100 & (AB)' & A + AB' \\ 23 | 0101 & B' & (A + B) plus AB' \\ 24 | 0110 & A XOR B & A minus B minus 1 \\ 25 | 0111 & AB' & AB' minus 1 \\ 26 | 1000 & A' + B & A plus AB \\ 27 | 1001 & (A XOR B)' & A plus B \\ 28 | 1010 & B & (A + B') plus AB \\ 29 | 1011 & AB & AB minus 1 \\ 30 | 1100 & Logical 1 & A plus A \\ 31 | 1101 & A + B' & (A + B) plus A \\ 32 | 1110 & A + B & (A + B') plus A \\ 33 | 1111 & A & A minus 1 34 | \end{tabular} 35 | \end{center} 36 | \caption{Function Table for 74181 ALU} 37 | \label{tab0301} 38 | \end{table} 39 | 40 | Notes: in the ``Arithmetic'' column, the + sign indicates logic \textit{OR} while the words \textit{plus} and \textit{minus} indicate arithmetic add and subtract operations. The value of \textit{A plus A} is the same as shifting the bits left to the next most significant position. 41 | 42 | The \ac{ALU} built in this lab is not as complex as a 74181 \ac{IC}, however it demonstrates the basic functions of an \ac{ALU}. 43 | 44 | \section{Procedure} 45 | 46 | \marginpar{This is a rather complex circuit so several completed subcircuits are provided.}Load the \ac{ALU} starter circuit in \textit{Logisim-evolution}. That starter circuit already has the \lstinline[columns=fixed]|main|, \lstinline[columns=fixed]|ALU|, and \lstinline[columns=fixed]|Arithmetic| subcircuits completed. 47 | 48 | \subsection{main} 49 | 50 | The \lstinline[columns=fixed]|main| circuit does nothing more than provide a human-friendly interface for the rest of the \ac{ALU}. That interface include two four-bit inputs (labeled \textit{InA} and \textit{InB}), a three-bit select, a one-bit mode, a carry-in and carry-out bit (so the \ac{ALU} could be chained to another to create an eight-bit device), a \textit{compare} output (TRUE if the two inputs are equal), and a four-bit output (labeled \textit{ALUOut}). In operation, numbers are entered on \textit{InA} and \textit{InB}, the mode and select are set, and then the result is read on \textit{ALUOut}. 51 | 52 | \begin{figure}[H] 53 | \centering 54 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/04-01} 55 | \caption{ALU main} 56 | \label{fig:04-01} 57 | \end{figure} 58 | 59 | \subsection{ALU} 60 | 61 | The \lstinline[columns=fixed]|ALU| subcircuit contains the logic that routes \textit{InA}, \textit{InB}, and \textit{Sel} to two other subcircuits, \lstinline[columns=fixed]|Arithmetic| or \lstinline[columns=fixed]|Logic|. It then uses a multiplexer to route the output of one of those subcircuits to an output port depending on the setting of the \textit{Mode} bit. Note that the inputs are sent to both subcircuits but only the output specified by the \textit{Mode} is returned to the user. This type of logic is also used in the \lstinline[columns=fixed]|Arithmetic| circuit. 62 | 63 | \begin{figure}[H] 64 | \centering 65 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/04-02} 66 | \caption{ALU Subcircuit} 67 | \label{fig:04-02} 68 | \end{figure} 69 | 70 | \subsection{Arithmetic} 71 | 72 | This subcircuit contains numerous devices from the \textit{Arithmetic} library and they are all wired appropriately for whatever operation is selected. The concept for this subcircuit is rather simple but routing the wiring to all of the devices is challenging. 73 | 74 | Notice that two multiplexers are necessary since the circuit provides two different outputs. The top multiplexer routes the four-bit solution and the bottom multiplexer routes the carry-out bit. The \textit{compare} output is always active since it is comparing the input signals and does not rely on the function that is selected. 75 | 76 | \begin{figure}[H] 77 | \centering 78 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/04-03} 79 | \caption{Arithmetic Subcircuit} 80 | \label{fig:04-03} 81 | \end{figure} 82 | 83 | \subsection{Challenge} 84 | 85 | In the starter circuit, the \lstinline[columns=fixed]|Logic| subcircuit is only a shell with three inputs and one output. 86 | 87 | \begin{figure}[H] 88 | \centering 89 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/04-04} 90 | \caption{Logic Subcircuit} 91 | \label{fig:04-04} 92 | \end{figure} 93 | 94 | Complete that subcircuit by adding the necessary logic gates and wiring, similar to the \lstinline[columns=fixed]|Arithmetic| subcircuit. This subcircuit is much simpler than the \lstinline[columns=fixed]|Arithmetic| subcircuit since there are no carry-in, carry-out, or compare bits. When completed, the subcircuit only needs eight logic gates and a multiplexer added to the starter. 95 | 96 | \subsection{Testing the Circuit} 97 | 98 | The \lstinline[columns=fixed]|ALU| should be tested by entering several values on \textit{InA} and \textit{InB} and then select all possible arithmetic and logic operations. The outputs for each check should be accurate. 99 | 100 | \section{Deliverable} 101 | 102 | To receive a grade for this lab, complete the Challenge. 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\setcounter{listings}{0} 63 | \setcounter{loldepth}{1} 64 | \setcounter{lstlisting}{0} 65 | \setcounter{section@level}{0} 66 | } 67 | -------------------------------------------------------------------------------- /Chapters/07_Timer.tex: -------------------------------------------------------------------------------- 1 | %**************************************** 2 | % Lab 07: Timer 3 | %**************************************** 4 | \chapter{Timer} 5 | 6 | \section{Purpose} 7 | 8 | A timer is used to time events. This lab creates a timer where the minimum and maximum counts can be set and counts both up and down. The timer assumes an input clock pulse at 1 Hz (or 60 pulses per minute) but for testing, the clock can be set to any value. 9 | 10 | \section{Procedure} 11 | 12 | The lab starter circuit includes several versions of the timer as an illustration of the thought process used to develop the final product. 13 | 14 | \begin{itemize} 15 | \item \textbf{Timer\_V1}. This is little more than a test of the Counter (\textit{Memory} library) component. The various inputs were wired so both the \textit{Load} and \textit{Up} input pins could be tested. Instead of a clock pulse, a Button (\textit{Input/Output} library) was used for better control over the device. A Bin2BCD (\textit{BFH mega functions} library) device was used for easier interpretation of the output. 16 | \item \textbf{Timer\_V2}. The first circuit was expanded such that both the minimum and maximum counts could be specified. Note that the multiplexer (\textit{Plexers} library) selects whether the minimum or maximum number is loaded depending on whether the count is Up or Down. 17 | \item \textbf{Timer\_V3}. This is the version of the timer that will be completed for this lab. 18 | \end{itemize} 19 | 20 | \subsection{Timer\_V3} 21 | 22 | Complete the circuit to match Figure \ref{fig:07-01}. 23 | 24 | \begin{figure}[H] 25 | \centering 26 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/07-01} 27 | \caption{Completed Timer} 28 | \label{fig:07-01} 29 | \end{figure} 30 | 31 | In the timer circuit, the key is the comparator in the lower left corner. That device compares the binary output of the counter to either the minimum or maximum requested value and if they are equal the comparator sends a reset signal to start the count over. 32 | 33 | There are two multiplexers with a subtle, but important, difference. The Maximum input value is wired to the top input of the top multiplexer but the bottom input of the bottom multiplexer. The result is the when the count is ``Up'' the Minimum input is loaded into the counter but the Maximum input is used in the compare, so the counter starts at the minimum and counts up to the maximum. The opposite is true for a ``Down'' count. 34 | 35 | Finally, the BCD output is combined by a splitter (\textit{Wiring} library) into a 12-bit bus for transmission. 36 | 37 | \subsection{Testing the Circuit} 38 | 39 | The \lstinline[columns=fixed]|Timer_V3| subcircuit should be added to the \lstinline[columns=fixed]|main| circuit and wired as in Figure \ref{fig:07-02}. 40 | 41 | \begin{figure}[H] 42 | \centering 43 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/07-02} 44 | \caption{Timer Main Circuit} 45 | \label{fig:07-02} 46 | \end{figure} 47 | 48 | To test the circuit: 49 | 50 | \begin{enumerate} 51 | \item Enter binary four for a minimum value and eight for a maximum value. (Actually, any values can be entered but four and eight are enough to test the circuit.) 52 | \item Poke \textit{Up\_Down} to change its value to one so the circuit counts up. 53 | \item Poke the Reset button and observe that the BCD out changes to 004. 54 | \item Activate the clock \textsc{Simulate -> Ticks Enabled} and observe that it counts up from four to eight and then resets to four. If the speed of the timer is not reasonable then the \textsc{Simulate -> Tick Frequency} can be adjusted. 55 | \item Poke \textit{Up\_Down} to change the count to down and observe that the timer now counts from eight to four and resets. 56 | \end{enumerate} 57 | 58 | \section{Challenge} 59 | 60 | As designed, the output of this circuit is an integer count. If it were set for counting seconds then the count of seconds would increase from 59 to 60 then 61 rather than going 0:59, 1:00, 1:01 as expected. Rewrite the \lstinline[columns=fixed]|Timer_V3| subcircuit so the output is two BCD numbers: minutes and seconds. As a hint, the Divider (\textit{Arithmetic} library) device products an integer (``modulus'') division along with a remainder. It should help to divide the count by 60, use the whole number as ``minutes'' and the remainder as the ``seconds.'' 61 | 62 | \section{Deliverable} 63 | 64 | To receive a grade for this lab, complete the Challenge. Be sure the standard identifying information is at the top left of the \lstinline{main} circuit, similar to: 65 | 66 | \bigskip 67 | % The minipage environment keeps the three lines together - no page break. 68 | \begin{minipage}{\linewidth} 69 | \begin{verbatim} 70 | George Self 71 | Lab 07: Timer 72 | March 1, 2018 73 | \end{verbatim} 74 | \end{minipage} 75 | \bigskip 76 | 77 | Save the file with this name: \emph{\texttt{Lab07\_Timer}} and submit that file for grading. 78 | 79 | -------------------------------------------------------------------------------- /Chapters/08_React.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \mph@setcol{ii:64}{\mph@nr} 4 | \@writefile{toc}{\contentsline {chapter}{\numberline {8}\spacedlowsmallcaps {Reaction Timer}}{65}{chapter.8}\protected@file@percent } 5 | \@writefile{lof}{\addvspace {10\p@ }} 6 | \@writefile{lot}{\addvspace {10\p@ }} 7 | \@writefile{lol}{\addvspace {10\p@ }} 8 | \def\mph@nr{18} 9 | \@writefile{toc}{\contentsline {section}{\numberline {8.1}Purpose}{65}{section.8.1}\protected@file@percent } 10 | \@writefile{lof}{\contentsline {figure}{\numberline {8.1}{\ignorespaces Reaction Timer\relax }}{65}{figure.8.1}\protected@file@percent } 11 | \newlabel{fig:08-01}{{8.1}{65}{Reaction Timer\relax }{figure.8.1}{}} 12 | \@writefile{toc}{\contentsline {section}{\numberline {8.2}Procedure}{65}{section.8.2}\protected@file@percent } 13 | \mph@setcol{ii:65}{\mph@nr} 14 | \@writefile{toc}{\contentsline {section}{\numberline {8.3}Deliverable}{66}{section.8.3}\protected@file@percent } 15 | \mph@setcol{ii:66}{\mph@nr} 16 | \@setckpt{Chapters/08_React}{ 17 | \setcounter{page}{67} 18 | \setcounter{equation}{0} 19 | \setcounter{enumi}{5} 20 | \setcounter{enumii}{0} 21 | \setcounter{enumiii}{0} 22 | \setcounter{enumiv}{0} 23 | \setcounter{footnote}{0} 24 | \setcounter{mpfootnote}{0} 25 | \setcounter{part}{4} 26 | \setcounter{chapter}{8} 27 | \setcounter{section}{3} 28 | \setcounter{subsection}{0} 29 | \setcounter{subsubsection}{0} 30 | \setcounter{paragraph}{0} 31 | \setcounter{subparagraph}{0} 32 | \setcounter{figure}{1} 33 | \setcounter{table}{0} 34 | \setcounter{dummy}{6} 35 | \setcounter{parentequation}{0} 36 | \setcounter{caption@flags}{0} 37 | \setcounter{ContinuedFloat}{0} 38 | \setcounter{KVtest}{0} 39 | \setcounter{subfigure}{0} 40 | \setcounter{subfigure@save}{0} 41 | \setcounter{lofdepth}{1} 42 | \setcounter{subtable}{0} 43 | \setcounter{subtable@save}{0} 44 | \setcounter{lotdepth}{1} 45 | \setcounter{lstnumber}{1} 46 | \setcounter{Item}{46} 47 | \setcounter{bookmark@seq@number}{0} 48 | \setcounter{tikztiming@nrows}{0} 49 | \setcounter{tikztimingrows}{0} 50 | \setcounter{tikztimingtrans}{0} 51 | \setcounter{tikztimingtranspos}{0} 52 | \setcounter{r@tfl@t}{0} 53 | \setcounter{tcbbreakpart}{0} 54 | \setcounter{tcblayer}{0} 55 | \setcounter{FancyVerbLine}{19} 56 | \setcounter{float@type}{16} 57 | \setcounter{listings}{0} 58 | \setcounter{loldepth}{1} 59 | \setcounter{lstlisting}{0} 60 | \setcounter{section@level}{0} 61 | } 62 | -------------------------------------------------------------------------------- /Chapters/08_React.tex: -------------------------------------------------------------------------------- 1 | %***************************************** 2 | % Lab 08: Reaction Timer 3 | %***************************************** 4 | \chapter{Reaction Timer} 5 | 6 | \section{Purpose} 7 | 8 | This lab continues the exploration of timing circuits and is intended to provide additional practice with sequential circuit design. The project is to build a circuit that times a user's reaction speed. When complete, the \lstinline[columns=fixed]|main| circuit should look something like Figure \ref{fig:08-01}. 9 | 10 | \begin{figure}[H] 11 | \centering 12 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/08-01} 13 | \caption{Reaction Timer} 14 | \label{fig:08-01} 15 | \end{figure} 16 | 17 | In operation: 18 | 19 | \begin{enumerate} 20 | \item The user clicks \textit{start}. 21 | \item An unseen timer begins and counts down a random length of time while the ``Waiting'' LED is lit. The countdown should be less than 10 seconds so use a 4-bit counter for this part of the circuit. 22 | \item When the unseen timer reaches zero the ``Waiting'' LED turns off and the numbers on the two hex displays begin to increase. 23 | \item The user clicks the \textit{Stop} button to stop the timer. 24 | \item The reaction time is displayed on the two hex displays. 25 | \end{enumerate} 26 | 27 | \section{Procedure} 28 | 29 | The design of this circuit is left to the student, but the timer built in Lab 7 would be a good starter for this lab. As a tip, \LE includes a Random Generator (\textit{Memory} library) that can be used to create a random countdown for the ``Waiting'' subcircuit. Finally, the \textsc{Simulate -> Tick Frequency} can be set to a low number (maybe 4 Hz) to build and troubleshoot the circuit for convenience but it should then be set somewhat faster to actually measure a user's reaction time. 30 | 31 | \section{Deliverable} 32 | 33 | To receive a grade for this lab, complete the circuit. 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%************************************************************** 4 | \chapter{RAM} 5 | 6 | \section{Purpose} 7 | 8 | This lab is used to demonstrate how a \acf{RAM} device operates. 9 | 10 | \section{Procedure} 11 | 12 | A RAM (\textit{Memory} library) device is similar to a ROM device as used in Lab \ref{Lab09}, \nameref{Lab09}. A RAM device has an address input port, a data port, and several control ports. An address is loaded in the Address Port then on the next clock signal the device either reads the data at that address and outputs it on the data port or inputs whatever is on the data port and writes it to that address. Figure \ref{fig:10-01} illustrates a counter connected to a RAM address port so as the counter outputs an increasing value the RAM will ``step through'' memory locations. 13 | 14 | \begin{figure}[H] 15 | \centering 16 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/10-01} 17 | \caption{RAM Basics} 18 | \label{fig:10-01} 19 | \end{figure} 20 | 21 | In operation, a high signal on RAM port M1 enables the write function and the RAM device will store whatever is present on the data ports into the address pointed to on the address port. A high signal on port M2 enables the output function (a ``read'' function) and the RAM device will send whatever is present in the address pointed to on the address port to the data ports. 22 | 23 | Notice that the data ports have both an in and out pointing arrow to indicate that those ports are designed for both input and output, depending on the setting of M1 and M2. 24 | 25 | Figure \ref{fig:10-02} shows a RAM device with the various control signals. (Note: to show more detail, the right edge of the RAM device was cut from the figure.) 26 | 27 | \begin{figure}[H] 28 | \centering 29 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/10-02} 30 | \caption{RAM With Control Signals} 31 | \label{fig:10-02} 32 | \end{figure} 33 | 34 | \marginpar{To simplify the circuit wiring, tunnels are used to transport various signals around the circuit.}At the top left of the subcircuit a button is used to generate a clock pulse. By using a button students can pulse the circuit slowly and observe how the RAM device operates. In an actual circuit that button would be replaced by a Clock (\textit{Wiring} library). 35 | 36 | At the top of the circuit is a T Flip-Flop (\textit{Memory} library) that is used to control whether the RAM device is reading or writing data. Because it is important that M1 and M2, the two control ports on the RAM device, are never both high at one time a flip-flop is the perfect controller. The T input on the flip-flop is tied to a constant high so whenever the rd\_wrt button is pressed the RAM device toggles between read and write functions. 37 | 38 | The Counter has a Reset button attached that will reset its count to zero so the RAM device will always either read or write from its lowest memory location. In actual practice the counter would need a much more complex circuit to set a specific start point for the RAM device to read or write but for this simple demonstration circuit it is enough to always start read/write operations from the lowest memory location. 39 | 40 | The next step is to set up the data bus on the east side of the RAM device. It is important that the bus does not attempt to carry data out of the RAM device at the same time that data are being sent to the RAM device. Thus, control buffers are used to determine the direction of data flow between the RAM device and the data bus. Figure \ref{fig:10-03} shows the data bus with the control buffers. (Note: to show more detail, the counter was cut from the left edge of the figure.) 41 | 42 | \begin{figure}[H] 43 | \centering 44 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/10-03} 45 | \caption{Data Bus} 46 | \label{fig:10-03} 47 | \end{figure} 48 | 49 | Notice that the outputs of the read/write flip-flop are being used to control the direction of the data flow for the RAM device. 50 | 51 | To complete the demonstration circuit, a Keyboard (\textit{Input/Output} library) device is added to write ASCII characters into RAM memory and a TTY (\textit{Input/Output} library) device is used to display ASCII characters read from RAM memory. Figure \ref{fig:10-04} shows the input/output devices. (Note: to show more detail, part of the RAM and TTY devices were cut from the edges of the figure.) 52 | 53 | \begin{figure}[H] 54 | \centering 55 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/10-04} 56 | \caption{RAM With Input/Output Devices} 57 | \label{fig:10-04} 58 | \end{figure} 59 | 60 | For reference, the entire circuit is in Figure \ref{fig:10-05}. 61 | 62 | \begin{figure}[H] 63 | \centering 64 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/10-05} 65 | \caption{RAM With Input/Output Devices} 66 | \label{fig:10-05} 67 | \end{figure} 68 | 69 | To operate the keyboard device, click it and enter some text from the computer's keyboard. Then as that device is clocked one ASCII character at a time will be sent to the output port at its south-east corner. As in ASCII devices used in earlier labs, a splitter is used for both the keyboard and TTY display to strip the most significant bit from the data bus since the bus is eight bits wide but ASCII is only a seven-bit code. 70 | 71 | Finally, two indicator LEDS have been added to make it clear whether data are being written to RAM or read from RAM. 72 | 73 | \subsection{Testing the Circuit} 74 | 75 | To test the complete circuit: 76 | 77 | \begin{enumerate} 78 | \item Click Reset to set the counter to zero. 79 | \item Click the ``rd\_wrt'' button until the ``Write\_to\_RAM'' LED is on. 80 | \item Click the keyboard device and enter some text. 81 | \item Click the ``clk'' button to stream the text from the keyboard into RAM. Notice how the RAM device display changes to indicate the ASCII codes that have been stored. 82 | \item Click Reset to set the counter to zero. 83 | \item Click the ``clr'' button on the TTY device to clear that display. 84 | \item Click the ``rd\_wrt'' button until the ``Read\_from\_RAM'' LED is on. 85 | \item Click the ``clk'' button to stream text from RAM to the TTY device. Notice that this does not remove the text from RAM so it is still available for another reading if desired. 86 | \end{enumerate} 87 | 88 | \section{Challenge} 89 | 90 | Build the circuit as described in this Lab and ensure that it operates as expected. 91 | 92 | \section{Deliverable} 93 | 94 | To receive a grade for this lab, complete the Challenge. Be sure the standard identifying information is at the top left of the \lstinline{main} circuit, similar to: 95 | 96 | \bigskip 97 | % The minipage environment keeps the three lines together - no page break. 98 | \begin{minipage}{\linewidth} 99 | \begin{verbatim} 100 | George Self 101 | Lab 10: RAM 102 | February 16, 2018 103 | \end{verbatim} 104 | \end{minipage} 105 | \bigskip 106 | 107 | Save the file with this name: \textit{Lab10\_RAM} and submit that file for grading. 108 | -------------------------------------------------------------------------------- /Chapters/11_Processor.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \@writefile{toc}{\contentsline {chapter}{\numberline {11}\spacedlowsmallcaps {Processor}}{83}{chapter.11}\protected@file@percent } 4 | \@writefile{lof}{\addvspace {10\p@ }} 5 | \@writefile{lot}{\addvspace {10\p@ }} 6 | \@writefile{lol}{\addvspace {10\p@ }} 7 | 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%************************************************************** 2 | % Lab 12: CPU 3 | %************************************************************** 4 | \chapter{Central Processing Unit}\label{lab12} 5 | 6 | \section{Introduction} 7 | 8 | \subsection{First Steps} 9 | 10 | When building a \ac{CPU}, the first few steps do not involve slinging gates into a circuit. As in most things, planning will save time when executing. 11 | 12 | \subsubsection{Purpose} 13 | 14 | The first question to answer when building a \ac{CPU} is its purpose. It makes a great deal of difference whether the \ac{CPU} is intended for a single purpose of some sort or a more generalized application. The better the purpose can be defined the simpler (and easier) the designing job becomes. For example, there is no need to design a \ac{CPU} with a lot of ``bells and whistles'' that is intended to be embedded in a microwave oven. A simple 4-bit \ac{CPU} can do that job. 15 | 16 | \subsubsection{Instruction Set} 17 | 18 | After the \acp{CPU} purpose has been defined, the instruction set must be designed. In general, the fewer instructions that are needed for the \ac{CPU} to do its job, the simpler the design will be. Of course, the designer must include enough instructions to ensure the \ac{CPU} can be effective.\footnote{As an aside, there has been some theoretical work concerning the smallest possible instruction set that can still be used to create a working \ac{CPU}. The current record is one: one instruction is all that is necessary to create a functional \ac{CPU}. While some would argue which instruction is best; in general, computer scientists agree that ``Subtract and Branch if Less Than or Equal to Zero'' is most efficient. To find out more about this type of \ac{CPU}, search for ``SUBLEQ.''} 19 | 20 | \subsubsection{States} 21 | 22 | The next step is to define the various states the \ac{CPU} can enter and what should happen in each state. While that discussion is beyond the scope of this lesson, in general the \acp{CPU} various functions are mapped out so the designer can create circuits to match each function. 23 | 24 | A \acp{CPU} states can be divided into three broad categories: Fetch, Decode, Execute. During the Fetch state, an instruction is fetched from memory and brought into the \ac{CPU}. The instruction is next decoded so the \ac{CPU} knows what type of instruction was fetched. Finally, the microcode steps required by the instruction are executed. The entire cycle repeats until the program is completed. Here is a generic diagram of the instruction cycle: 25 | 26 | \bigskip 27 | 28 | \smartdiagram[circular diagram:clockwise]{% 29 | Fetch,Decode,Execute 30 | } 31 | 32 | \section{Purpose} 33 | 34 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 35 | % After I create the CPU I need to start here and update this part of the lab. 36 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 37 | 38 | A \ac{CPU} contains several components that are tied together with bus lines. Figure \ref{fig:11-01} is a block diagram that shows the main components of the \ac{CPU} being studied in this book: 39 | 40 | \begin{figure}[H] 41 | \centering 42 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/11-01} 43 | \caption{Simple Processor} 44 | \label{fig:11-01} 45 | \end{figure} 46 | 47 | Here is the purpose for each of these components (from the top of the diagram): 48 | 49 | \begin{itemize} 50 | \item The Ctrl circuit controls all functions within the \ac{CPU}. The output of the Ctrl circuit is placed on the Control Bus where it can then be used to turn on/off various multiplexors and control buffers in order to control the data flow between the components on the data bus. In operation, the \ac{CPU} “fetches” the next program instruction from memory, and then the control circuit interprets that instruction and opens or closes data paths as appropriate. 51 | \item The Arithmetic Logic Unit (ALU) is responsible for all data manipulation, such as adding two numbers. The ALU sends the results of its work to a register called the Accumulator (which is internal to the ALU on this \ac{CPU}). 52 | \item The Gen Regs (General Registers) are a number of registers that are used to temporarily store information while it is being processed. These registers may be considered the “scratch pad” of the \ac{CPU}. 53 | \item The Pgm Cnter (Program Counter) keeps track of the address of the memory location that contains the next program instruction to be executed. That instruction is then “fetched” and processed by the Ctrl circuit. 54 | \item The Addr Reg (Address Register) contains a RAM address that is important for the current operation; perhaps, for example, a single byte of an ASCII encoded message that needs to be displayed on the screen. The output of the Address Register is sent directly to RAM through the Address Bus. 55 | \item RAM contains the program that is currently being executed. Most of the information traveling on the Data Bus either comes from or is going to RAM. 56 | \item Peripherals are devices that the \ac{CPU} must control; such as a hard drive or monitor. 57 | \end{itemize} 58 | 59 | \footnote{Much of the material in this unit was adapted from a similar lab written by Dr. Lawlor for TKGate, another logic simulator. Here is the URL for that lab: \url{http://www.cs.uaf.edu/2008/fall/cs441/lecture/09_09_\ac{CPU}_construction.html}} 60 | 61 | \section{Procedure} 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | \subsection{Testing the Circuit} 73 | 74 | The circuit should be tested by ... 75 | 76 | \section{Challenge} 77 | 78 | Whatever 79 | 80 | \section{Deliverable} 81 | 82 | To receive a grade for this lab, build the \ac{CPU} circuit and then complete the Challenge. Be sure the standard identifying information is at the top left of the \ac{CPU} \lstinline{main} circuit, similar to: 83 | 84 | \bigskip 85 | % The minipage environment keeps the three lines together - no page break. 86 | \begin{minipage}{\linewidth} 87 | \begin{verbatim} 88 | George Self 89 | Lab 12: CPU 90 | April 30, 2018 91 | \end{verbatim} 92 | \end{minipage} 93 | \bigskip 94 | 95 | Save the \ac{CPU} circuit in a file with this name: \textit{Lab12\_CPU}. Complete the code required in the Challenge and store that in a Word or Text file with the name \textit{Lab12\_Code}. Submit both files for grading. 96 | 97 | -------------------------------------------------------------------------------- /Chapters/12_Elevator.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \@writefile{toc}{\contentsline {chapter}{\numberline {5}\spacedlowsmallcaps {Timer}}{25}{chapter.5}} 4 | \@writefile{lof}{\addvspace {10\p@ }} 5 | \@writefile{lot}{\addvspace {10\p@ }} 6 | \@writefile{lol}{\addvspace {10\p@ }} 7 | \def\mph@nr{5} 8 | \@writefile{toc}{\contentsline {section}{\numberline {5.1}Purpose}{25}{section.5.1}} 9 | \@writefile{toc}{\contentsline {section}{\numberline {5.2}Procedure}{25}{section.5.2}} 10 | \@writefile{toc}{\contentsline {subsection}{\numberline {5.2.1}Subcircuit 1: Whatever}{25}{subsection.5.2.1}} 11 | \@writefile{lof}{\contentsline {figure}{\numberline {5.1}{\ignorespaces Caption\relax }}{25}{figure.5.1}} 12 | \newlabel{fig:00-00}{{5.1}{25}{Caption\relax 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\setcounter{lstnumber}{1} 45 | \setcounter{Item}{63} 46 | \setcounter{bookmark@seq@number}{0} 47 | \setcounter{tikztiming@nrows}{0} 48 | \setcounter{tikztimingrows}{0} 49 | \setcounter{tikztimingtrans}{0} 50 | \setcounter{tikztimingtranspos}{0} 51 | \setcounter{r@tfl@t}{0} 52 | \setcounter{tcbbreakpart}{0} 53 | \setcounter{tcblayer}{0} 54 | \setcounter{FancyVerbLine}{5} 55 | \setcounter{float@type}{16} 56 | \setcounter{listings}{0} 57 | \setcounter{loldepth}{1} 58 | \setcounter{lstlisting}{0} 59 | \setcounter{section@level}{0} 60 | } 61 | -------------------------------------------------------------------------------- /Chapters/13_Elevator.tex: -------------------------------------------------------------------------------- 1 | %************************************************************** 2 | % Lab 13: Elevator 3 | %************************************************************** 4 | \chapter{Elevator} 5 | 6 | \section{Purpose} 7 | 8 | This final lab is used as a capstone digital logic project. 9 | 10 | \section{Challenge} 11 | 12 | For this lab, build a circuit that simulates an elevator. This lab does not include step-by-step directions; instead, this document only specifies the requirement and students are on their own to design and build the circuit. 13 | 14 | Here are the specifications: 15 | 16 | \begin{enumerate} 17 | \item The elevator should be in a 3-story building and stop on each floor. 18 | \item There should be a call button on each floor so a guest can request the elevator. When a guest presses the call button, if the elevator is not busy, then it should proceed to the requested floor. If the elevator is busy, it should return to the called floor as soon as it finishes the current trip. 19 | \item The elevator car must have a button for each floor (for this lab, ignore buttons like ``Open Door''). When one of the buttons is pressed, the elevator will move to the requested floor. If the elevator is already on the requested floor (for example, some guest on the second floor presses the ``Floor 2'' button), then the elevator will do nothing. 20 | \item The simulator must have some way to indicate where the elevator is located (its current floor). That could be done with a numeric display (a 7-segment display) or with some sort of light system (an LED on each floor that will light up when the elevator is present). There may be other ways to indicate the elevator's location, so creativity is encouraged. 21 | \item The simulator must have some way to indicate the ``door open'' and ``door close'' process. For example, a row of LEDs could light in sequence to show the door opening and a few seconds later closing again. 22 | \end{enumerate} 23 | 24 | Figure \ref{fig:13-01} is one student's concept from an earlier class. 25 | 26 | \begin{figure}[H] 27 | \centering 28 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/13-01} 29 | \caption{Example Elevator Simulator} 30 | \label{fig:13-01} 31 | \end{figure} 32 | 33 | \section{Deliverable} 34 | 35 | To receive a grade for this lab, complete the elevator simulator. Be sure the standard identifying information is at the top left of the \lstinline{main} circuit: 36 | 37 | \bigskip 38 | % The minipage environment keeps the three lines together - no page break. 39 | \begin{minipage}{\linewidth} 40 | \begin{verbatim} 41 | George Self 42 | Lab 12: Elevator 43 | April 30, 2018 44 | \end{verbatim} 45 | \end{minipage} 46 | \bigskip 47 | 48 | Save the file with this name: \textit{Lab12\_elevator} and submit that file for grading. -------------------------------------------------------------------------------- /Chapters/90_Detect.tex: -------------------------------------------------------------------------------- 1 | %************************************************************** 2 | % Lab 07: Bit Pattern Detector 3 | %************************************************************** 4 | \chapter{Bit Pattern Detector} 5 | 6 | \section{Purpose} 7 | 8 | This lab builds a circuit that detects a specific pattern of bits on an input stream. This is a very simple circuit that introduces shift registers. three starter versions of this lab are provided as an iterative process. 9 | 10 | \section{Procedure} 11 | 12 | \subsection{Subcircuit V1} 13 | 14 | Start a new \textit{Logisim-evolution} project and create a subcircuit labeled \lstinline|V1|. 15 | 16 | Place a Shift Register (\textit{Memory} library) on the drawing canvas. Set the properties of the shift register to one data bit and four stages. Wire Buttons (\textit{Input/Output} library) to the \textit{R} and \textit{clk} inputs and label those buttons \textit{\texttt{Reset}} and \textit{\texttt{clk}}. Wire a one-bit input pin to the \textit{1,3D} input on the shift register and label it \textit{\texttt{InData}}. 17 | 18 | Using a splitter, gather all four outputs into a single bus and wire that bus to one input on a comparator (\textit{Arithmetic} library). Wire a Constant (\textit{Wiring} library) \textit{a} on the other comparator input. Finally, wire a Probe (\textit{Wiring} library) with a Radix set to Hexadecimal to the output bus. 19 | 20 | When completed, the circuit should look like Figure \ref{fig:07-01}. 21 | 22 | \begin{figure}[H] 23 | \centering 24 | \includegraphics[width=\maxwidth{.95\linewidth}]{gfx/07-01} 25 | \caption{Pattern Detector, V1} 26 | \label{fig:07-01} 27 | \end{figure} 28 | 29 | \subsection{Testing the Circuit} 30 | 31 | \begin{enumerate} 32 | \item Poke \textit{Reset} to reset the shift register. 33 | \item Poke \textit{InData} to make it go high and then poke \textit{clk}. 34 | \item Poke \textit{InData} to make it go low and then poke \textit{clk}. 35 | \item Poke \textit{InData} to make it go high and then poke \textit{clk}. 36 | \item Poke \textit{InData} to make it go low and then poke \textit{clk}. 37 | \item \textit{Detected} should go high. 38 | \end{enumerate} 39 | 40 | 41 | \section{Challenge} 42 | 43 | Whatever 44 | 45 | \section{Deliverable} 46 | 47 | To receive a grade for this lab, complete the Challenge. Be sure the standard identifying information is at the top left of the \lstinline{main} circuit: 48 | 49 | \bigskip 50 | % The minipage environment keeps the three lines together - no page break. 51 | \begin{minipage}{\linewidth} 52 | \begin{verbatim} 53 | George Self 54 | Lab 07: Bit Pattern Detector 55 | March 11, 2018 56 | \end{verbatim} 57 | \end{minipage} 58 | \bigskip 59 | 60 | Save the file with this name: \textit{Lab07\_Detect} and submit that file for grading. 61 | 62 | -------------------------------------------------------------------------------- /Chapters/Lab Manual Pt 1-Exploring Digital Logic with Logisim-Evolution.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/grself/CIS221_Lab_Manual/4421ab0de3e70976b8095e37eddb12ff9b597aa0/Chapters/Lab Manual Pt 1-Exploring Digital Logic with Logisim-Evolution.docx -------------------------------------------------------------------------------- /FrontBackmatter/Abstract.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Abstract 3 | %******************************************************* 4 | %\renewcommand{\abstractname}{Abstract} 5 | \pdfbookmark[1]{Abstract}{Abstract} 6 | \begingroup 7 | \let\clearpage\relax 8 | \let\cleardoublepage\relax 9 | \let\cleardoublepage\relax 10 | 11 | \chapter*{Abstract} 12 | Short summary of the contents in English\dots a great guide by 13 | Kent Beck how to write good abstracts can be found here: 14 | \begin{center} 15 | \url{https://plg.uwaterloo.ca/~migod/research/beckOOPSLA.html} 16 | \end{center} 17 | 18 | \vfill 19 | 20 | \pdfbookmark[1]{Zusammenfassung}{Zusammenfassung} 21 | \chapter*{Zusammenfassung} 22 | Kurze Zusammenfassung des Inhaltes in deutscher Sprache\dots 23 | 24 | \endgroup 25 | 26 | \vfill -------------------------------------------------------------------------------- /FrontBackmatter/Acknowledgments.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Acknowledgments 3 | %******************************************************* 4 | \pdfbookmark[1]{Acknowledgments}{acknowledgments} 5 | 6 | \begin{flushright}{\slshape 7 | We have seen that computer programming is an art, \\ 8 | because it applies accumulated knowledge to the world, \\ 9 | because it requires skill and ingenuity, and especially \\ 10 | because it produces objects of beauty.} \\ \medskip 11 | --- \defcitealias{knuth:1974}{Donald E. Knuth}\citetalias{knuth:1974} \citep{knuth:1974} 12 | \end{flushright} 13 | 14 | 15 | 16 | \bigskip 17 | 18 | \begingroup 19 | \let\clearpage\relax 20 | \let\cleardoublepage\relax 21 | \let\cleardoublepage\relax 22 | \chapter*{Acknowledgments} 23 | Put your acknowledgments here. 24 | 25 | Many thanks to everybody who already sent me a postcard! 26 | 27 | Regarding the typography and other help, many thanks go to Marco 28 | Kuhlmann, Philipp Lehman, Lothar Schlesier, Jim Young, Lorenzo 29 | Pantieri and Enrico Gregorio\footnote{Members of GuIT (Gruppo 30 | Italiano Utilizzatori di \TeX\ e \LaTeX )}, J\"org Sommer, 31 | Joachim K\"ostler, Daniel Gottschlag, Denis Aydin, Paride 32 | Legovini, Steffen Prochnow, Nicolas Repp, Hinrich Harms, 33 | Roland Winkler, Jörg Weber, Henri Menke, Claus Lahiri, 34 | Clemens Niederberger, Stefano Bragaglia, Jörn Hees, 35 | and the whole \LaTeX-community for support, ideas and 36 | some great software. 37 | 38 | \bigskip 39 | 40 | \noindent\emph{Regarding \mLyX}: The \mLyX\ port was intially done by 41 | \emph{Nicholas Mariette} in March 2009 and continued by 42 | \emph{Ivo Pletikosi\'c} in 2011. Thank you very much for your 43 | work and for the contributions to the original style. 44 | 45 | 46 | \endgroup 47 | 48 | 49 | 50 | -------------------------------------------------------------------------------- /FrontBackmatter/Bibliography.tex: -------------------------------------------------------------------------------- 1 | %******************************************************************** 2 | % Bibliography 3 | %******************************************************* 4 | % work-around to have small caps also here in the headline 5 | \manualmark 6 | \markboth{\spacedlowsmallcaps{\bibname}}{\spacedlowsmallcaps{\bibname}} % work-around to have small caps also 7 | %\phantomsection 8 | \refstepcounter{dummy} 9 | \addtocontents{toc}{\protect\vspace{\beforebibskip}} % to have the bib a bit from the rest in the toc 10 | \addcontentsline{toc}{chapter}{\tocEntry{\bibname}} 11 | \label{app:bibliography} 12 | \printbibliography 13 | -------------------------------------------------------------------------------- /FrontBackmatter/Colophon.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \mph@setcol{ii:137}{\mph@nr} 4 | \@setckpt{FrontBackmatter/Colophon}{ 5 | \setcounter{page}{138} 6 | \setcounter{equation}{0} 7 | \setcounter{enumi}{5} 8 | \setcounter{enumii}{0} 9 | \setcounter{enumiii}{0} 10 | \setcounter{enumiv}{0} 11 | \setcounter{footnote}{0} 12 | \setcounter{mpfootnote}{0} 13 | \setcounter{part}{6} 14 | \setcounter{chapter}{1} 15 | \setcounter{section}{35} 16 | \setcounter{subsection}{0} 17 | \setcounter{subsubsection}{0} 18 | \setcounter{paragraph}{0} 19 | \setcounter{subparagraph}{0} 20 | \setcounter{figure}{27} 21 | \setcounter{table}{39} 22 | \setcounter{dummy}{6} 23 | \setcounter{parentequation}{0} 24 | \setcounter{caption@flags}{0} 25 | \setcounter{ContinuedFloat}{0} 26 | \setcounter{KVtest}{0} 27 | \setcounter{subfigure}{0} 28 | \setcounter{subfigure@save}{0} 29 | \setcounter{lofdepth}{1} 30 | \setcounter{subtable}{0} 31 | \setcounter{subtable@save}{0} 32 | \setcounter{lotdepth}{1} 33 | \setcounter{lstnumber}{1} 34 | \setcounter{Item}{63} 35 | \setcounter{bookmark@seq@number}{0} 36 | \setcounter{tikztiming@nrows}{0} 37 | \setcounter{tikztimingrows}{0} 38 | \setcounter{tikztimingtrans}{0} 39 | \setcounter{tikztimingtranspos}{0} 40 | \setcounter{r@tfl@t}{0} 41 | \setcounter{tcbbreakpart}{0} 42 | \setcounter{tcblayer}{0} 43 | \setcounter{FancyVerbLine}{5} 44 | \setcounter{float@type}{16} 45 | \setcounter{listings}{0} 46 | \setcounter{loldepth}{1} 47 | \setcounter{lstlisting}{0} 48 | \setcounter{section@level}{0} 49 | } 50 | -------------------------------------------------------------------------------- /FrontBackmatter/Colophon.tex: -------------------------------------------------------------------------------- 1 | \pagestyle{empty} 2 | 3 | \hfill 4 | 5 | \vfill 6 | 7 | 8 | \pdfbookmark[0]{Colophon}{colophon} 9 | \section*{Colophon} 10 | This book was typeset using the typographical look-and-feel \texttt{classicthesis} developed by Andr\'e Miede. 11 | The style was inspired by Robert Bringhurst's seminal book on typography ``\emph{The Elements of Typographic Style}''. 12 | \texttt{classicthesis} is available for both \LaTeX\ and \mLyX: 13 | \begin{center} 14 | \url{https://bitbucket.org/amiede/classicthesis/} 15 | \end{center} 16 | Happy users of \texttt{classicthesis} usually send a real postcard to the author, a collection of postcards received so far is featured here: 17 | \begin{center} 18 | \url{http://postcards.miede.de/} 19 | \end{center} 20 | 21 | \bigskip 22 | 23 | \noindent\finalVersionString 24 | 25 | Hermann Zapf's \emph{Palatino} and \emph{Euler} type faces (Type~1 PostScript fonts \emph{URW 26 | Palladio L} and \emph{FPL}) are used. The ``typewriter'' text is typeset in \emph{Bera Mono}, 27 | originally developed by Bitstream, Inc. as ``Bitstream Vera''. (Type~1 PostScript fonts were made 28 | available by Malte Rosenau and 29 | Ulrich Dirr.) 30 | 31 | %\paragraph{note:} The custom size of the textblock was calculated 32 | %using the directions given by Mr. Bringhurst (pages 26--29 and 33 | %175/176). 10~pt Palatino needs 133.21~pt for the string 34 | %``abcdefghijklmnopqrstuvwxyz''. This yields a good line length between 35 | %24--26~pc (288--312~pt). Using a ``\emph{double square textblock}'' 36 | %with a 1:2 ratio this results in a textblock of 312:624~pt (which 37 | %includes the headline in this design). A good alternative would be the 38 | %``\emph{golden section textblock}'' with a ratio of 1:1.62, here 39 | %312:505.44~pt. For comparison, \texttt{DIV9} of the \texttt{typearea} 40 | %package results in a line length of 389~pt (32.4~pc), which is by far 41 | %too long. However, this information will only be of interest for 42 | %hardcore pseudo-typographers like me.% 43 | % 44 | %To make your own calculations, use the following commands and look up 45 | %the corresponding lengths in the book: 46 | %\begin{verbatim} 47 | % \settowidth{\abcd}{abcdefghijklmnopqrstuvwxyz} 48 | % \the\abcd\ % prints the value of the length 49 | %\end{verbatim} 50 | %Please see the file \texttt{classicthesis.sty} for some precalculated 51 | %values for Palatino and Minion. 52 | % 53 | % \settowidth{\abcd}{abcdefghijklmnopqrstuvwxyz} 54 | % \the\abcd\ % prints the value of the length 55 | 56 | 57 | 58 | 59 | -------------------------------------------------------------------------------- /FrontBackmatter/Contents.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \mph@setcol{ii:v}{\mph@nr} 4 | \mph@setcol{ii:vi}{\mph@nr} 5 | \mph@setcol{ii:vii}{\mph@nr} 6 | \mph@setcol{ii:viii}{\mph@nr} 7 | \mph@setcol{ii:ix}{\mph@nr} 8 | \mph@setcol{ii:x}{\mph@nr} 9 | \@writefile{toc}{\contentsline {chapter}{List of Figures}{xi}{dummy.3}\protected@file@percent } 10 | \mph@setcol{ii:xi}{\mph@nr} 11 | \mph@setcol{ii:xii}{\mph@nr} 12 | \@writefile{toc}{\contentsline {chapter}{List of Tables}{xiii}{dummy.4}\protected@file@percent } 13 | \mph@setcol{ii:xiii}{\mph@nr} 14 | \@writefile{toc}{\contentsline {chapter}{Listings}{xiv}{dummy.5}\protected@file@percent } 15 | \newacro{ALU}[\AC@hyperlink{ALU}{ALU}]{Arithmetic Logic Unit} 16 | \newacro{ASCII}[\AC@hyperlink{ASCII}{ASCII}]{American Standard Code for Information Interchange} 17 | \newacro{ASIC}[\AC@hyperlink{ASIC}{ASIC}]{Application-Specific Integrated Circuit} 18 | \newacro{BCD}[\AC@hyperlink{BCD}{BCD}]{Binary Coded Decimal} 19 | \newacro{BDD}[\AC@hyperlink{BDD}{BDD}]{Binary Decision Diagram} 20 | \newacro{BIOS}[\AC@hyperlink{BIOS}{BIOS}]{Basic Input/Output System} 21 | \newacro{BLIF}[\AC@hyperlink{BLIF}{BLIF}]{Berkeley Logic Interchange Format} 22 | \newacro{CAT}[\AC@hyperlink{CAT}{CAT}]{Computer-Aided Tools} 23 | \newacro{CISC}[\AC@hyperlink{CISC}{CISC}]{Complex Instruction Set Computer} 24 | \newacro{CPU}[\AC@hyperlink{CPU}{CPU}]{Central Processing Unit} 25 | \newacro{DRAM}[\AC@hyperlink{DRAM}{DRAM}]{Dynamic Random Access Memory} 26 | \newacro{DUT}[\AC@hyperlink{DUT}{DUT}]{Device Under Test} 27 | \newacro{EBCDIC}[\AC@hyperlink{EBCDIC}{EBCDIC}]{Extended Binary Coded Decimal Interchange Code} 28 | \newacro{EDA}[\AC@hyperlink{EDA}{EDA}]{Electronic Design Automation} 29 | \newacro{FSM}[\AC@hyperlink{FSM}{FSM}]{Finite State Machine} 30 | \newacro{HDL}[\AC@hyperlink{HDL}{HDL}]{Hardware Description Language} 31 | \newacro{IC}[\AC@hyperlink{IC}{IC}]{Integrated Circuit} 32 | \newacro{IEEE}[\AC@hyperlink{IEEE}{IEEE}]{Institute of Electrical and Electronics Engineers} 33 | \newacro{KARMA}[\AC@hyperlink{KARMA}{KARMA}]{KARnaugh MAp simplifier} 34 | \newacro{LED}[\AC@hyperlink{LED}{LED}]{Light Emitting Diode} 35 | \newacro{LSB}[\AC@hyperlink{LSB}{LSB}]{Least Significant Bit} 36 | \newacro{LSN}[\AC@hyperlink{LSN}{LSN}]{Least Significant Nibble} 37 | \newacro{MSB}[\AC@hyperlink{MSB}{MSB}]{Most Significant Bit} 38 | \newacro{MSN}[\AC@hyperlink{MSN}{MSN}]{Most Significant Nibble} 39 | \newacro{NaN}[\AC@hyperlink{NaN}{NaN}]{Not a Number} 40 | \newacro{OER}[\AC@hyperlink{OER}{OER}]{Open Educational Resource} 41 | \newacro{PCB}[\AC@hyperlink{PCB}{PCB}]{Printed Circuit Board} 42 | \newacro{POS}[\AC@hyperlink{POS}{POS}]{Product of Sums} 43 | \newacro{PROM}[\AC@hyperlink{PROM}{PROM}]{Programmable Read-Only Memory} 44 | \newacro{RAM}[\AC@hyperlink{RAM}{RAM}]{Random Access Memory} 45 | \newacro{RISC}[\AC@hyperlink{RISC}{RISC}]{Reduced Instruction Set Computer} 46 | \newacro{ROM}[\AC@hyperlink{ROM}{ROM}]{Read Only Memory} 47 | \newacro{RPM}[\AC@hyperlink{RPM}{RPM}]{Rotations Per Minute} 48 | \newacro{RTL}[\AC@hyperlink{RTL}{RTL}]{Register Transfer Language} 49 | \newacro{SECDED}[\AC@hyperlink{SECDED}{SECDED}]{Single Error Correction, Double Error Detection} 50 | \newacro{SOP}[\AC@hyperlink{SOP}{SOP}]{Sum of Products} 51 | \newacro{SDRAM}[\AC@hyperlink{SDRAM}{SDRAM}]{Synchronized Dynamic Random Access Memory} 52 | \newacro{SRAM}[\AC@hyperlink{SRAM}{SRAM}]{Static Random Access Memory} 53 | \mph@setcol{ii:xiv}{\mph@nr} 54 | \newacro{TTL}[\AC@hyperlink{TTL}{TTL}]{Transistor-Transistor Logic} 55 | \newacro{USB}[\AC@hyperlink{USB}{USB}]{Universal Synchronous Bus} 56 | \newacro{VHDL}[\AC@hyperlink{VHDL}{VHDL}]{VHSIC Hardware Descriptive Language} 57 | \newacro{VHSIC}[\AC@hyperlink{VHSIC}{VHSIC}]{Very High Speed Integrated Circuit} 58 | \newacro{VLIW}[\AC@hyperlink{VLIW}{VLIW}]{Very Long Instruction Word} 59 | \mph@setcol{ii:xv}{\mph@nr} 60 | \@setckpt{FrontBackmatter/Contents}{ 61 | \setcounter{page}{16} 62 | \setcounter{equation}{0} 63 | \setcounter{enumi}{0} 64 | \setcounter{enumii}{0} 65 | \setcounter{enumiii}{0} 66 | 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Contents}{0} % Only Chapter Headings 12 | 13 | %******************************************************* 14 | % Table of Contents 15 | %******************************************************* 16 | %\phantomsection 17 | \refstepcounter{dummy} 18 | \pdfbookmark[1]{\contentsname}{tableofcontents} 19 | \setcounter{tocdepth}{2} % <-- 2 includes up to subsections in the ToC 20 | \setcounter{secnumdepth}{3} % <-- 3 numbers up to subsubsections 21 | \manualmark 22 | \markboth{\spacedlowsmallcaps{\contentsname}}{\spacedlowsmallcaps{\contentsname}} 23 | \tableofcontents 24 | \automark[section]{chapter} 25 | \renewcommand{\chaptermark}[1]{\markboth{\spacedlowsmallcaps{#1}}{\spacedlowsmallcaps{#1}}} 26 | \renewcommand{\sectionmark}[1]{\markright{\thesection\enspace\spacedlowsmallcaps{#1}}} 27 | %******************************************************* 28 | % List of Figures and of the Tables 29 | %******************************************************* 30 | \clearpage 31 | 32 | \begingroup 33 | \let\clearpage\relax 34 | \let\cleardoublepage\relax 35 | \let\cleardoublepage\relax 36 | %******************************************************* 37 | % List of Figures 38 | %******************************************************* 39 | %\phantomsection 40 | \refstepcounter{dummy} 41 | \addcontentsline{toc}{chapter}{\listfigurename} 42 | \pdfbookmark[1]{\listfigurename}{lof} 43 | \listoffigures 44 | 45 | \vspace{8ex} 46 | 47 | %******************************************************* 48 | % List of Tables 49 | %******************************************************* 50 | %\phantomsection 51 | \refstepcounter{dummy} 52 | \addcontentsline{toc}{chapter}{\listtablename} 53 | \pdfbookmark[1]{\listtablename}{lot} 54 | \listoftables 55 | 56 | \vspace{8ex} 57 | % \newpage 58 | 59 | %******************************************************* 60 | % List of Listings 61 | %******************************************************* 62 | %\phantomsection 63 | \refstepcounter{dummy} 64 | \addcontentsline{toc}{chapter}{\lstlistlistingname} 65 | \pdfbookmark[1]{\lstlistlistingname}{lol} 66 | \lstlistoflistings 67 | 68 | \vspace{8ex} 69 | 70 | %******************************************************* 71 | % Acronyms 72 | %******************************************************* 73 | %\phantomsection 74 | \refstepcounter{dummy} 75 | \pdfbookmark[1]{Acronyms}{acronyms} 76 | \markboth{\spacedlowsmallcaps{Acronyms}}{\spacedlowsmallcaps{Acronyms}} 77 | \chapter*{Acronyms} 78 | % Notes: alphabitize this list as you create it. 79 | % Accronyms in this list are not printed unless they show up in the text somewhere 80 | \begin{acronym}[UMLX] 81 | \acro{ALU}{Arithmetic Logic Unit} 82 | \acro{ASCII}{American Standard Code for Information Interchange} 83 | \acro{ASIC}{Application-Specific Integrated Circuit} 84 | \acro{BCD}{Binary Coded Decimal} 85 | \acro{BDD}{Binary Decision Diagram} 86 | \acro{BIOS}{Basic Input/Output System} 87 | \acro{BLIF}{Berkeley Logic Interchange Format} 88 | \acro{CAT}{Computer-Aided Tools} 89 | \acro{CISC}{Complex Instruction Set Computer} 90 | \acro{CPU}{Central Processing Unit} 91 | \acro{DRAM}{Dynamic Random Access Memory} 92 | \acro{DUT}{Device Under Test} 93 | \acro{EBCDIC}{Extended Binary Coded Decimal Interchange Code} 94 | \acro{EDA}{Electronic Design Automation} 95 | \acro{FSM}{Finite State Machine} 96 | \acro{HDL}{Hardware Description Language} 97 | \acro{IC}{Integrated Circuit} 98 | \acro{IEEE}{Institute of Electrical and Electronics Engineers} 99 | \acro{KARMA}{KARnaugh MAp simplifier} 100 | \acro{LED}{Light Emitting Diode} 101 | \acro{LSB}{Least Significant Bit} 102 | \acro{LSN}{Least Significant Nibble} 103 | \acro{MSB}{Most Significant Bit} 104 | \acro{MSN}{Most Significant Nibble} 105 | \acro{NaN}{Not a Number} 106 | \acro{OER}{Open Educational Resource} 107 | \acro{PCB}{Printed Circuit Board} 108 | \acro{POS}{Product of Sums} 109 | \acro{PROM}{Programmable Read-Only Memory} 110 | \acro{RAM}{Random Access Memory} 111 | \acro{RISC}{Reduced Instruction Set Computer} 112 | \acro{ROM}{Read Only Memory} 113 | \acro{RPM}{Rotations Per Minute} 114 | \acro{RTL}{Register Transfer Language} 115 | \acro{SECDED}{Single Error Correction, Double Error Detection} 116 | \acro{SOP}{Sum of Products} 117 | \acro{SDRAM}{Synchronized Dynamic Random Access Memory} 118 | \acro{SRAM}{Static Random Access Memory} 119 | \acro{TTL}{Transistor-Transistor Logic} 120 | \acro{USB}{Universal Synchronous Bus} 121 | \acro{VHDL}{VHSIC Hardware Descriptive Language} 122 | \acro{VHSIC}{Very High Speed Integrated Circuit} 123 | \acro{VLIW}{Very Long Instruction Word} 124 | \end{acronym} 125 | \endgroup 126 | -------------------------------------------------------------------------------- /FrontBackmatter/Declaration.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Declaration 3 | %******************************************************* 4 | \refstepcounter{dummy} 5 | \pdfbookmark[0]{Declaration}{declaration} 6 | \chapter*{Declaration} 7 | \thispagestyle{empty} 8 | Put your declaration here. 9 | \bigskip 10 | 11 | \noindent\textit{\myLocation, \myTime} 12 | 13 | \smallskip 14 | 15 | \begin{flushright} 16 | \begin{tabular}{m{5cm}} 17 | \\ \hline 18 | \centering\myName \\ 19 | \end{tabular} 20 | \end{flushright} 21 | -------------------------------------------------------------------------------- /FrontBackmatter/Dedication.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Dedication 3 | %******************************************************* 4 | \thispagestyle{empty} 5 | %\phantomsection 6 | \refstepcounter{dummy} 7 | \pdfbookmark[1]{Dedication}{Dedication} 8 | 9 | \vspace*{3cm} 10 | 11 | \begin{center} 12 | \emph{Ohana} means family. \\ 13 | Family means nobody gets left behind, or forgotten. \\ \medskip 14 | --- Lilo \& Stitch 15 | \end{center} 16 | 17 | \medskip 18 | 19 | \begin{center} 20 | Dedicated to the loving memory of Rudolf Miede. \\ \smallskip 21 | 1939\,--\,2005 22 | \end{center} -------------------------------------------------------------------------------- /FrontBackmatter/DirtyTitlepage.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Little Dirty Titlepage 3 | %******************************************************* 4 | \thispagestyle{empty} 5 | %\pdfbookmark[1]{Titel}{title} 6 | %******************************************************* 7 | \begin{center} 8 | \spacedlowsmallcaps{\myName} \\ \medskip 9 | 10 | \begingroup 11 | \color{Maroon}\spacedallcaps{\myTitle} 12 | \endgroup 13 | \end{center} 14 | -------------------------------------------------------------------------------- /FrontBackmatter/Preface.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \newlabel{preface}{{}{iii}{Preface}{chapter*.1}{}} 4 | \AC@undonewlabel{acro:OER} 5 | \newlabel{acro:OER}{{}{iii}{Preface}{section*.2}{}} 6 | \acronymused{OER} 7 | \mph@setcol{ii:iii}{\mph@nr} 8 | \@setckpt{FrontBackmatter/Preface}{ 9 | \setcounter{page}{4} 10 | \setcounter{equation}{0} 11 | \setcounter{enumi}{0} 12 | \setcounter{enumii}{0} 13 | \setcounter{enumiii}{0} 14 | \setcounter{enumiv}{0} 15 | \setcounter{footnote}{0} 16 | \setcounter{mpfootnote}{0} 17 | \setcounter{part}{0} 18 | \setcounter{chapter}{0} 19 | \setcounter{section}{0} 20 | \setcounter{subsection}{0} 21 | \setcounter{subsubsection}{0} 22 | \setcounter{paragraph}{0} 23 | \setcounter{subparagraph}{0} 24 | \setcounter{figure}{0} 25 | \setcounter{table}{0} 26 | \setcounter{dummy}{0} 27 | \setcounter{parentequation}{0} 28 | \setcounter{caption@flags}{0} 29 | \setcounter{ContinuedFloat}{0} 30 | \setcounter{KVtest}{0} 31 | \setcounter{subfigure}{0} 32 | \setcounter{subfigure@save}{0} 33 | \setcounter{lofdepth}{1} 34 | \setcounter{subtable}{0} 35 | \setcounter{subtable@save}{0} 36 | \setcounter{lotdepth}{1} 37 | \setcounter{lstnumber}{1} 38 | \setcounter{Item}{0} 39 | \setcounter{bookmark@seq@number}{0} 40 | \setcounter{tikztiming@nrows}{0} 41 | \setcounter{tikztimingrows}{0} 42 | \setcounter{tikztimingtrans}{0} 43 | \setcounter{tikztimingtranspos}{0} 44 | \setcounter{r@tfl@t}{0} 45 | \setcounter{tcbbreakpart}{0} 46 | \setcounter{tcblayer}{0} 47 | \setcounter{FancyVerbLine}{0} 48 | \setcounter{float@type}{16} 49 | \setcounter{listings}{0} 50 | \setcounter{loldepth}{1} 51 | \setcounter{lstlisting}{0} 52 | \setcounter{section@level}{0} 53 | } 54 | -------------------------------------------------------------------------------- /FrontBackmatter/Preface.tex: -------------------------------------------------------------------------------- 1 | %***************************************** 2 | \chapter*{Preface}\label{preface} 3 | %***************************************** 4 | 5 | I have taught CIS 221, \textit{Digital Logic}, for Cochise College since about 2003 and enjoy working with students on this topic. From the start, I wanted students to work with labs as part of our studies and actually design circuits to complement our theoretical instruction. As I evaluated circuit design software I had three criteria: 6 | 7 | \begin{itemize} 8 | \item \textbf{\ac{OER}}. It is important to me that students use software that is available free of charge and is supported by the entire web community. 9 | \item \textbf{Platform}. While most of my students use a Windows-based system, some use Macintosh and it was important to me to use software that is available for both of those platforms. As a bonus, most OER software is also available for the Linux system, though I'm not aware of any of my students who are using Linux. 10 | \item \textbf{Simplicity}. I wanted to use software that was easy to master so students could spend their time understanding digital logic rather than learning the arcane structures of a simulation language. 11 | \end{itemize} 12 | 13 | I originally wrote a number of lab exercises using \textit{Logisim}, but the creator of that software, Carl Burch, announced that he would quit developing it in 2014. Because it was published as an open source project, a group of Swiss institutes started with the \textit{Logisim} software and developed a new version that integrated several new tools, like a chronogram, and released it under the name \LE. 14 | 15 | It is my hope that students will find these labs instructive and the labs enhance their learning of digital logic. This lab manual is written with \LaTeX\ and published under a \href{https://creativecommons.org/publicdomain/zero/1.0/}{Creative Commons Zero} license with a goal that other instructors can modify it to meet their own needs. The source code can be found at \href{https://github.com/grself/CIS221_Lab_Manual}{my personal GITHUB page} and I always welcome comments that will help me improve this manual. 16 | 17 | \bigskip 18 | \begin{flushright} 19 | \textemdash George Self 20 | \end{flushright} 21 | 22 | 23 | -------------------------------------------------------------------------------- /FrontBackmatter/Publications.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Publications 3 | %******************************************************* 4 | \pdfbookmark[1]{Publications}{publications} 5 | \chapter*{Publications}\graffito{This is just an early --~and currently ugly~-- test!} 6 | This might come in handy for PhD theses: some ideas and figures have appeared previously in the following publications: 7 | 8 | %\noindent Put your publications from the thesis here. The packages \texttt{multibib} or \texttt{bibtopic} etc. can be used to handle multiple different bibliographies in your document. 9 | 10 | \begin{refsection}[ownpubs] 11 | \small 12 | \nocite{*} % is local to to the enclosing refsection 13 | \printbibliography[heading=none] 14 | \end{refsection} 15 | 16 | \emph{Attention}: This requires a separate run of \texttt{bibtex} for your \texttt{refsection}, \eg, \texttt{ClassicThesis1-blx} for this file. You might also use \texttt{biber} as the backend for \texttt{biblatex}. See also \url{http://tex.stackexchange.com/questions/128196/problem-with-refsection}. -------------------------------------------------------------------------------- /FrontBackmatter/StyleGuide.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \mph@setcol{ii:99}{\mph@nr} 4 | \mph@setcol{ii:100}{\mph@nr} 5 | \@setckpt{FrontBackmatter/StyleGuide}{ 6 | \setcounter{page}{101} 7 | \setcounter{equation}{0} 8 | \setcounter{enumi}{5} 9 | \setcounter{enumii}{0} 10 | \setcounter{enumiii}{0} 11 | \setcounter{enumiv}{0} 12 | \setcounter{footnote}{0} 13 | \setcounter{mpfootnote}{0} 14 | \setcounter{part}{6} 15 | \setcounter{chapter}{1} 16 | \setcounter{section}{0} 17 | \setcounter{subsection}{0} 18 | \setcounter{subsubsection}{0} 19 | \setcounter{paragraph}{0} 20 | \setcounter{subparagraph}{0} 21 | \setcounter{figure}{0} 22 | \setcounter{table}{0} 23 | \setcounter{dummy}{7} 24 | \setcounter{parentequation}{0} 25 | \setcounter{ContinuedFloat}{0} 26 | \setcounter{KVtest}{0} 27 | \setcounter{subfigure}{0} 28 | \setcounter{subfigure@save}{0} 29 | \setcounter{lofdepth}{1} 30 | \setcounter{subtable}{0} 31 | \setcounter{subtable@save}{0} 32 | \setcounter{lotdepth}{1} 33 | \setcounter{lstnumber}{1} 34 | \setcounter{Item}{63} 35 | \setcounter{bookmark@seq@number}{105} 36 | \setcounter{tikztiming@nrows}{0} 37 | \setcounter{tikztimingrows}{0} 38 | \setcounter{tikztimingtrans}{0} 39 | \setcounter{tikztimingtranspos}{0} 40 | \setcounter{r@tfl@t}{0} 41 | \setcounter{tcbbreakpart}{0} 42 | \setcounter{tcblayer}{0} 43 | \setcounter{FancyVerbLine}{5} 44 | \setcounter{float@type}{16} 45 | \setcounter{lips@count}{0} 46 | \setcounter{listings}{0} 47 | \setcounter{loldepth}{1} 48 | \setcounter{lstlisting}{0} 49 | \setcounter{section@level}{0} 50 | } 51 | -------------------------------------------------------------------------------- /FrontBackmatter/StyleGuide.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Declaration 3 | %******************************************************* 4 | \refstepcounter{dummy} 5 | \pdfbookmark[0]{Style Guide}{styleguide} 6 | \chapter*{Style Guide} 7 | \thispagestyle{empty} 8 | 9 | \begin{itemize} 10 | 11 | \item \textsc{Boolean Expressions}. Use math equations for in-line Boolean expressions and equations. 12 | 13 | \item \textsc{Circuit/Subcircuit Name}. Use \lstinline[columns=fixed]|Circuit_4|. 14 | 15 | \item \textsc{Figures and Tables}. 16 | 17 | \begin{itemize} 18 | \item Figures and Tables use an [H] specification 19 | \item Captions go at the end of the table block so it is printed under the table to match figures and listings. (Figures and Listings place the caption under by default) 20 | \end{itemize} 21 | 22 | \item \textsc{File Names}. File names should be in Typewriter and Emphasis styles: \emph{\texttt{Lab01\_Mux21}}. 23 | 24 | \item \textsc{Library Devices}. Devices (like counters) in regular font but with the italicized library name following, like: Counter (\textit{Memory} library). 25 | 26 | \item \textsc{Gates}. Should be in all caps and typewriter font: \texttt{AND} 27 | 28 | \item \textsc{Menu Items}. Use small caps: \textsc{Simulate -> Reset Simulation}. 29 | 30 | \item \textsc{Numbers}. 31 | 32 | \begin{itemize} 33 | \item Numbers use normal font, not math or some other special font. 34 | \item Spell out numbers up to ten; thus, not ``1s,'' but ones. 35 | \item Larger numbers with a suffix, like ``s,'' do not use an apostrophe: not ten's, but tens. 36 | \end{itemize} 37 | 38 | \item \textsc{Pin Names}. Pin names (like \textit{Q1}) are italicized. This is also true for variable names and types of flip-flops. 39 | 40 | \item \textsc{Properties}. Properties (like \textit{Facing}) are italicized. 41 | 42 | \item \textsc{Signals}. Should be italicized in typewriter font: \textit{\texttt{Activate}} 43 | 44 | \item \textsc{Tools}. Tools (like \textit{Poke}) are capitalized and italicized. 45 | 46 | \item \textsc{True/False}. The words \emph{True} and \emph{False} are capitalized and in an \lstinline[columns=fixed]|\emph{}| block. 47 | 48 | \item \textsc{Vocabulary} 49 | 50 | \begin{itemize} 51 | \item ``Flip-flop'' is hyphenated 52 | \item ``Logisim-evoluation'' is placed in italics with only ``Logisim'' capitalized: \textit{Logisim-evolution} 53 | \item ``Subcircuit'' is not hyphenated 54 | \end{itemize} 55 | 56 | \end{itemize} 57 | 58 | -------------------------------------------------------------------------------- /FrontBackmatter/Titleback.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \mph@setcol{ii:ii}{\mph@nr} 4 | \@setckpt{FrontBackmatter/Titleback}{ 5 | \setcounter{page}{3} 6 | \setcounter{equation}{0} 7 | \setcounter{enumi}{0} 8 | \setcounter{enumii}{0} 9 | \setcounter{enumiii}{0} 10 | \setcounter{enumiv}{0} 11 | \setcounter{footnote}{0} 12 | \setcounter{mpfootnote}{0} 13 | \setcounter{part}{0} 14 | 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\setcounter{float@type}{16} 45 | \setcounter{listings}{0} 46 | \setcounter{loldepth}{1} 47 | \setcounter{lstlisting}{0} 48 | \setcounter{section@level}{0} 49 | } 50 | -------------------------------------------------------------------------------- /FrontBackmatter/Titleback.tex: -------------------------------------------------------------------------------- 1 | \thispagestyle{empty} 2 | 3 | \hfill 4 | 5 | \vfill 6 | 7 | \noindent\myName: \emph{\myTitle} %\mySubtitle %\myDegree, 8 | %\textcopyright\ \myTime 9 | 10 | \doclicenseThis 11 | 12 | %\bigskip 13 | % 14 | %\noindent\spacedlowsmallcaps{Supervisors}: \\ 15 | %\myProf \\ 16 | %\myOtherProf \\ 17 | %\mySupervisor 18 | % 19 | %\medskip 20 | % 21 | %\noindent\spacedlowsmallcaps{Location}: \\ 22 | %\myLocation 23 | % 24 | %\medskip 25 | % 26 | %\noindent\spacedlowsmallcaps{Time Frame}: \\ 27 | %\myTime 28 | -------------------------------------------------------------------------------- /FrontBackmatter/Titlepage.aux: -------------------------------------------------------------------------------- 1 | \relax 2 | \providecommand\hyper@newdestlabel[2]{} 3 | \mph@setcol{ii:i}{\mph@nr} 4 | \@setckpt{FrontBackmatter/Titlepage}{ 5 | \setcounter{page}{2} 6 | \setcounter{equation}{0} 7 | \setcounter{enumi}{0} 8 | \setcounter{enumii}{0} 9 | \setcounter{enumiii}{0} 10 | \setcounter{enumiv}{0} 11 | \setcounter{footnote}{0} 12 | \setcounter{mpfootnote}{0} 13 | \setcounter{part}{0} 14 | \setcounter{chapter}{0} 15 | \setcounter{section}{0} 16 | \setcounter{subsection}{0} 17 | \setcounter{subsubsection}{0} 18 | \setcounter{paragraph}{0} 19 | \setcounter{subparagraph}{0} 20 | \setcounter{figure}{0} 21 | \setcounter{table}{0} 22 | \setcounter{dummy}{0} 23 | \setcounter{parentequation}{0} 24 | \setcounter{caption@flags}{0} 25 | \setcounter{ContinuedFloat}{0} 26 | \setcounter{KVtest}{0} 27 | \setcounter{subfigure}{0} 28 | \setcounter{subfigure@save}{0} 29 | \setcounter{lofdepth}{1} 30 | \setcounter{subtable}{0} 31 | \setcounter{subtable@save}{0} 32 | \setcounter{lotdepth}{1} 33 | \setcounter{lstnumber}{1} 34 | \setcounter{Item}{0} 35 | \setcounter{bookmark@seq@number}{0} 36 | \setcounter{tikztiming@nrows}{0} 37 | \setcounter{tikztimingrows}{0} 38 | \setcounter{tikztimingtrans}{0} 39 | \setcounter{tikztimingtranspos}{0} 40 | \setcounter{r@tfl@t}{0} 41 | \setcounter{tcbbreakpart}{0} 42 | \setcounter{tcblayer}{0} 43 | \setcounter{FancyVerbLine}{0} 44 | \setcounter{float@type}{16} 45 | \setcounter{listings}{0} 46 | \setcounter{loldepth}{1} 47 | \setcounter{lstlisting}{0} 48 | \setcounter{section@level}{0} 49 | } 50 | -------------------------------------------------------------------------------- /FrontBackmatter/Titlepage.tex: -------------------------------------------------------------------------------- 1 | %******************************************************* 2 | % Titlepage 3 | %******************************************************* 4 | \begin{titlepage} 5 | % Original Title Page code follows... 6 | % if you want the titlepage to be centered, uncomment and fine-tune the line below (KOMA classes environment) 7 | \begin{addmargin}[-1cm]{-3cm} 8 | \begin{center} 9 | \large 10 | 11 | \hfill 12 | 13 | \vfill 14 | 15 | \begingroup 16 | \color{Maroon}\spacedallcaps{\myTitle} \\ \bigskip 17 | \endgroup 18 | 19 | \spacedlowsmallcaps{\myName} 20 | 21 | \vfill 22 | 23 | % \includegraphics[width=6cm]{gfx/TFZsuperellipse_bw} \\ \medskip 24 | 25 | % \mySubtitle \\ \medskip 26 | %\myDegree \\ 27 | %\myDepartment \\ 28 | %\myFaculty \\ 29 | %\myUni \\ \bigskip 30 | 31 | \myTime\ -- \myVersion 32 | 33 | \vfill 34 | 35 | \end{center} 36 | \end{addmargin} 37 | \end{titlepage} -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | ## creative commons 2 | 3 | # CC0 1.0 Universal 4 | 5 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE LEGAL 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Affirmer understands and acknowledges that Creative Commons is not a party to this document and has no duty or obligation with respect to this CC0 or use of the Work. 44 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Cochise College CIS 221: Lab Manual 2 | 3 | This is the lab manual for the Cochise College CIS 221, Digital Logic, class. The labs use the *Logisim-evolution* simulator and these labs are designed to teach all aspects of both combinational and sequential logic circuits. 4 | 5 | * Lab 1: Introduction to *Logisim-evolution*: Students create a simple 2-Way, 1-Bit Multiplexer. 6 | * Lab 2: Subcircuits: This lab challenges students to create two subcircuits that create a device to test a three-bit and four-bit input against a Boolean equation and output a high only when the proper inputs are set. This lab also introduces the test vector capability of *Logisim-Evolution*. 7 | * Lab 3: Priority Encoder: This circuit continues to develop students' skill in manipulating *Logisim-evolution* and creating a slightly more complex circuit than the first two. 8 | * Lab 4: Arithmatic-Logic Unit: This is the first of a complex combinational logic circuit and challenges students to create an ALU using some of the built-in devices available in *Logisim-evolution*. 9 | * Lab 5: Vending Machine: this is the most complex combinational circuit in the lab manual. Students start with a Vending Machine simulation but are required to apply several modifications to the design. 10 | * Lab 6: D Flip-flop Counter: This is the first sequential circuit and introduces students to several different four-stage flip-flop counters. The lab also introduces the *Logisim-Evolution* chronogram feature. 11 | * Lab 7: Timer: This is a fairly complex timer circuit with an up/down setting and where the start/stop count can be specified. 12 | * Lab 8: Reaction Timer: This is a fun circuit that builds a timer that tests the user's reaction time. 13 | * Lab 9: ROM: This lab demonstrates how ROM works. The circuit builds a "Magic 8-ball" simulator and uses saying pre-loaded in ROM to respond to the user's yes/no questions. 14 | * Lab 10: RAM: This lab demonstrates how RAM works and shows students how to work with bi-directional input/output pins on a device. 15 | * Lab 11: Simple Processor: Students build a very simple processor for this lab. While it is not a Central Processing Unit it does show students how a code can control the flow of data around a simple loop and would be the most rudimentary introduction to CPU design. 16 | * Lab 12: Elevator: This is a capstone project where students are given specifications for a simple elevator simulator and challenged to build that circuit. 17 | 18 | This book was written with Latex and can be cloned and re-purposed as desired. The accompanying digital logic text book can be found at http://bit.ly/2w6qU2C. Also, the author created a series of YouTube videos to help students complete each of these labs. Those videos can be found at http://bit.ly/2KLMcoc. -------------------------------------------------------------------------------- /Student_Files/Homework/Lab01_Mux21.circ: -------------------------------------------------------------------------------- 1 | 2 | 3 | This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution). 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | addr/data: 8 8 34 | 0 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- 42 | -- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains 43 | -- Project : 44 | -- File : 45 | -- Autor : 46 | -- Date : 47 | -- 48 | -------------------------------------------------------------------------------- 49 | -- Description : 50 | -- 51 | -------------------------------------------------------------------------------- 52 | 53 | library ieee; 54 | use ieee.std_logic_1164.all; 55 | --use ieee.numeric_std.all; 56 | 57 | entity VHDL_Component is 58 | port( 59 | ------------------------------------------------------------------------------ 60 | --Insert input ports below 61 | horloge_i : in std_logic; -- input bit example 62 | val_i : in std_logic_vector(3 downto 0); -- input vector example 63 | ------------------------------------------------------------------------------ 64 | --Insert output ports below 65 | max_o : out std_logic; -- output bit example 66 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 67 | ); 68 | end VHDL_Component; 69 | 70 | -------------------------------------------------------------------------------- 71 | --Complete your VHDL description below 72 | architecture type_architecture of VHDL_Component is 73 | 74 | 75 | begin 76 | 77 | 78 | end type_architecture; 79 | 80 | 81 | 82 | 83 | 84 | library ieee; 85 | use ieee.std_logic_1164.all; 86 | 87 | entity TCL_Generic is 88 | port( 89 | --Insert input ports below 90 | horloge_i : in std_logic; -- input bit example 91 | val_i : in std_logic_vector(3 downto 0); -- input vector example 92 | 93 | --Insert output ports below 94 | max_o : out std_logic; -- output bit example 95 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 96 | ); 97 | end TCL_Generic; 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 |
111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | -------------------------------------------------------------------------------- /Student_Files/Homework/Lab02_Bool.circ: -------------------------------------------------------------------------------- 1 | 2 | 3 | This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution). 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | addr/data: 8 8 33 | 0 34 | 35 | 36 | 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- 41 | -- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains 42 | -- Project : 43 | -- File : 44 | -- Autor : 45 | -- Date : 46 | -- 47 | -------------------------------------------------------------------------------- 48 | -- Description : 49 | -- 50 | -------------------------------------------------------------------------------- 51 | 52 | library ieee; 53 | use ieee.std_logic_1164.all; 54 | --use ieee.numeric_std.all; 55 | 56 | entity VHDL_Component is 57 | port( 58 | ------------------------------------------------------------------------------ 59 | --Insert input ports below 60 | horloge_i : in std_logic; -- input bit example 61 | val_i : in std_logic_vector(3 downto 0); -- input vector example 62 | ------------------------------------------------------------------------------ 63 | --Insert output ports below 64 | max_o : out std_logic; -- output bit example 65 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 66 | ); 67 | end VHDL_Component; 68 | 69 | -------------------------------------------------------------------------------- 70 | --Complete your VHDL description below 71 | architecture type_architecture of VHDL_Component is 72 | 73 | 74 | begin 75 | 76 | 77 | end type_architecture; 78 | 79 | 80 | 81 | 82 | 83 | library ieee; 84 | use ieee.std_logic_1164.all; 85 | 86 | entity TCL_Generic is 87 | port( 88 | --Insert input ports below 89 | horloge_i : in std_logic; -- input bit example 90 | val_i : in std_logic_vector(3 downto 0); -- input vector example 91 | 92 | --Insert output ports below 93 | max_o : out std_logic; -- output bit example 94 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 95 | ); 96 | end TCL_Generic; 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 |
110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | -------------------------------------------------------------------------------- /Student_Files/Homework/Lab03_Encoder.circ: -------------------------------------------------------------------------------- 1 | 2 | 3 | This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution). 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | addr/data: 8 8 37 | 0 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 |
52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | -------------------------------------------------------------------------------- /Student_Files/Homework/Lab10_RAM.circ: -------------------------------------------------------------------------------- 1 | 2 | 3 | This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution). 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | addr/data: 8 8 33 | 0 34 | 35 | 36 | 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- 41 | -- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains 42 | -- Project : 43 | -- File : 44 | -- Autor : 45 | -- Date : 46 | -- 47 | -------------------------------------------------------------------------------- 48 | -- Description : 49 | -- 50 | -------------------------------------------------------------------------------- 51 | 52 | library ieee; 53 | use ieee.std_logic_1164.all; 54 | --use ieee.numeric_std.all; 55 | 56 | entity VHDL_Component is 57 | port( 58 | ------------------------------------------------------------------------------ 59 | --Insert input ports below 60 | horloge_i : in std_logic; -- input bit example 61 | val_i : in std_logic_vector(3 downto 0); -- input vector example 62 | ------------------------------------------------------------------------------ 63 | --Insert output ports below 64 | max_o : out std_logic; -- output bit example 65 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 66 | ); 67 | end VHDL_Component; 68 | 69 | -------------------------------------------------------------------------------- 70 | --Complete your VHDL description below 71 | architecture type_architecture of VHDL_Component is 72 | 73 | 74 | begin 75 | 76 | 77 | end type_architecture; 78 | 79 | 80 | 81 | 82 | 83 | library ieee; 84 | use ieee.std_logic_1164.all; 85 | 86 | entity TCL_Generic is 87 | port( 88 | --Insert input ports below 89 | horloge_i : in std_logic; -- input bit example 90 | val_i : in std_logic_vector(3 downto 0); -- input vector example 91 | 92 | --Insert output ports below 93 | max_o : out std_logic; -- output bit example 94 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 95 | ); 96 | end TCL_Generic; 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 |
110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | -------------------------------------------------------------------------------- /Student_Files/Homework/Lab12_Elevator.circ: -------------------------------------------------------------------------------- 1 | 2 | 3 | This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution). 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | addr/data: 8 8 37 | 0 38 | 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- 45 | -- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains 46 | -- Project : 47 | -- File : 48 | -- Autor : 49 | -- Date : 50 | -- 51 | -------------------------------------------------------------------------------- 52 | -- Description : 53 | -- 54 | -------------------------------------------------------------------------------- 55 | 56 | library ieee; 57 | use ieee.std_logic_1164.all; 58 | --use ieee.numeric_std.all; 59 | 60 | entity VHDL_Component is 61 | port( 62 | ------------------------------------------------------------------------------ 63 | --Insert input ports below 64 | horloge_i : in std_logic; -- input bit example 65 | val_i : in std_logic_vector(3 downto 0); -- input vector example 66 | ------------------------------------------------------------------------------ 67 | --Insert output ports below 68 | max_o : out std_logic; -- output bit example 69 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 70 | ); 71 | end VHDL_Component; 72 | 73 | -------------------------------------------------------------------------------- 74 | --Complete your VHDL description below 75 | architecture type_architecture of VHDL_Component is 76 | 77 | 78 | begin 79 | 80 | 81 | end type_architecture; 82 | 83 | 84 | 85 | 86 | 87 | library ieee; 88 | use ieee.std_logic_1164.all; 89 | 90 | entity TCL_Generic is 91 | port( 92 | --Insert input ports below 93 | horloge_i : in std_logic; -- input bit example 94 | val_i : in std_logic_vector(3 downto 0); -- input vector example 95 | 96 | --Insert output ports below 97 | max_o : out std_logic; -- output bit example 98 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 99 | ); 100 | end TCL_Generic; 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 |
114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab02_Eq1_test.txt: -------------------------------------------------------------------------------- 1 | # Test vector for Boolean Equation 1 2 | In1A In1B In1C Out1 3 | 0 0 0 0 4 | 0 0 1 0 5 | 0 1 0 1 6 | 0 1 1 0 7 | 1 0 0 1 8 | 1 0 1 0 9 | 1 1 0 0 10 | 1 1 1 1 -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab02_Eq2_test.txt: -------------------------------------------------------------------------------- 1 | # Test vector for Boolean Equation 2 2 | In2A In2B In2C In2D Out2 3 | 0 0 0 0 0 4 | 0 0 0 1 0 5 | 0 0 1 0 1 6 | 0 0 1 1 0 7 | 0 1 0 0 0 8 | 0 1 0 1 0 9 | 0 1 1 0 0 10 | 0 1 1 1 1 11 | 1 0 0 0 0 12 | 1 0 0 1 0 13 | 1 0 1 0 1 14 | 1 0 1 1 0 15 | 1 1 0 0 0 16 | 1 1 0 1 0 17 | 1 1 1 0 1 18 | 1 1 1 1 0 -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab03_Encoder_test.txt: -------------------------------------------------------------------------------- 1 | # Test vector for Priority Encoder 2 | # This just spot checks a few input combinations 3 | In1 In3 In5 In9 PriOut[4] 4 | 0 0 0 0 0000 5 | 1 0 0 0 0001 6 | 1 1 0 0 0011 7 | 0 1 1 0 0101 8 | 0 0 1 1 1001 9 | 0 1 1 1 1001 10 | 1 1 1 1 1001 -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab04_ALU_Ar_test.txt: -------------------------------------------------------------------------------- 1 | # Test vector for the Arithmetic part of the ALU 2 | # This just spot checks a few input combinations 3 | InA[4] InB[4] Sel[3] ArOut[4] COut Cmp 4 | 0000 0000 000 1110 0 1 # -1 5 | 0111 0000 001 0110 0 0 # A - 1 (7 - 1) 6 | 0111 0111 010 1110 0 1 # A + B (7 + 7) 7 | 1000 1000 010 0000 1 1 # A + B (8 + 8) 8 | 1000 0111 011 0001 0 0 # A - B (8 - 7) 9 | 1000 1001 011 1111 1 0 # A - B (8 - 9) 10 | 0010 0010 100 0011 0 1 # AB-1 (4 - 1) 11 | 1000 0010 100 1111 1 0 # AB-1 (0 - 1) *Note: 8*2 = 16, which is 0 12 | 0010 0010 101 1001 0 1 # AB'-1 (10 - 1) 13 | 1000 0010 101 0111 0 0 # AB'-1 (8 - 1) 14 | 0010 0000 110 0100 0 0 # A + A (2 + 2) 15 | 1000 0000 110 0000 1 0 # A + A (8 + 8) *Note: 16 = 0 16 | 0010 0000 111 0011 0 0 # A + 1 (2 + 1) 17 | 1000 0000 111 1001 0 0 # A + 1 (8 + 1) -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab04_ALU_Lo_test.txt: -------------------------------------------------------------------------------- 1 | # Test vector for the Logic part of the ALU 2 | # This just spot checks a few input combinations 3 | InA[4] InB[4] Sel[3] LoOut[4] 4 | 0000 0000 000 0000 # AB 5 | 1111 0001 000 0001 # AB 6 | 0000 0000 001 1111 #(AB)' 7 | 0101 0101 001 1010 #(AB)' 8 | 1111 0101 010 1111 # A+B 9 | 0101 0000 010 0101 # A+B 10 | 1111 0101 011 0000 #(A+B)' 11 | 0101 0000 011 1010 #(A+B)' 12 | 1111 0101 100 1010 # A xor B 13 | 0101 0000 100 0101 # A xor B 14 | 1111 0101 101 1010 # AB' 15 | 0101 0000 101 0101 # AB' 16 | 0111 0101 110 1111 # A+B' 17 | 0101 0010 110 1101 # A+B' 18 | 1111 xxxx 111 0000 # A' 19 | 0101 xxxx 111 1010 # A' -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab04_ALU_test.txt: -------------------------------------------------------------------------------- 1 | # Test vector for the ALU 2 | # This just spot checks a few input combinations 3 | CIn InA[4] InB[4] Sel[3] Mode COut Cmp ALUOut[4] 4 | # Arithmetic Tests 5 | 0 0000 0000 010 0 0 1 0000 # A+B 6 | 0 1000 0111 011 0 0 0 0001 # A-B 7 | 1 0100 xxxx 110 0 0 0 1001 # A+A+1 8 | 0 1111 xxxx 111 0 1 0 0000 # A + 1 9 | # Logic Tests 10 | 0 1100 0100 000 1 x x 0100 # AB 11 | 0 0101 0001 010 1 x x 0101 # A+B 12 | 0 0101 0001 011 1 x x 1010 # (A+B)' 13 | 0 0101 xxxx 111 1 x x 1010 # A' -------------------------------------------------------------------------------- /Student_Files/Supplemental/Lab09_ROM.txt: -------------------------------------------------------------------------------- 1 | v2.0 raw 2 | 0 49 74 20 69 73 20 63 3 | 65 72 74 61 69 6e 0 49 4 | 74 20 69 73 20 64 65 63 5 | 69 64 65 64 6c 79 20 73 6 | 6f 0 57 69 74 68 6f 75 7 | 74 20 61 20 64 6f 75 62 8 | 74 0 59 65 73 20 64 65 9 | 66 69 6e 69 74 65 6c 79 10 | 0 59 6f 75 20 6d 61 79 11 | 20 72 65 6c 79 20 6f 6e 12 | 20 69 74 0 41 73 20 49 13 | 20 73 65 65 20 69 74 20 14 | 79 65 73 0 4d 6f 73 74 15 | 20 6c 69 6b 65 6c 79 0 16 | 4f 75 74 6c 6f 6f 6b 20 17 | 67 6f 6f 64 0 59 65 73 18 | 0 53 69 67 6e 73 20 70 19 | 6f 69 6e 74 20 74 6f 20 20 | 79 65 73 0 52 65 70 6c 21 | 79 20 68 61 7a 79 20 74 22 | 72 79 20 61 67 61 69 6e 23 | 0 41 73 6b 20 61 67 61 24 | 69 6e 20 6c 61 74 65 72 25 | 0 42 65 74 74 65 72 20 26 | 6e 6f 74 20 74 65 6c 6c 27 | 20 79 6f 75 20 6e 6f 77 28 | 0 43 61 6e 6e 6f 74 20 29 | 70 72 65 64 69 63 74 20 30 | 6e 6f 77 0 43 6f 6e 63 31 | 65 6e 74 72 61 74 65 20 32 | 61 6e 64 20 61 73 6b 20 33 | 61 67 61 69 6e 0 44 6f 34 | 20 6e 6f 74 20 63 6f 75 35 | 6e 74 20 6f 6e 20 69 74 36 | 0 4d 79 20 72 65 70 6c 37 | 79 20 69 73 20 6e 6f 0 38 | 4d 79 20 73 6f 75 72 63 39 | 65 73 20 73 61 79 20 6e 40 | 6f 0 4f 75 74 6c 6f 6f 41 | 6b 20 6e 6f 74 20 73 6f 42 | 20 67 6f 6f 64 0 56 65 43 | 72 79 20 64 6f 75 62 74 44 | 66 75 6c 45 | -------------------------------------------------------------------------------- /dl_lab.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/grself/CIS221_Lab_Manual/4421ab0de3e70976b8095e37eddb12ff9b597aa0/dl_lab.log -------------------------------------------------------------------------------- /dl_lab.lol: -------------------------------------------------------------------------------- 1 | \babel@toc {american}{} 2 | \deactivateaddvspace 3 | \babel@toc {american}{} 4 | \addvspace {10\p@ } 5 | \addvspace {10\p@ } 6 | \addvspace {10\p@ } 7 | \addvspace {10\p@ } 8 | \addvspace {10\p@ } 9 | \addvspace {10\p@ } 10 | \addvspace {10\p@ } 11 | \addvspace {10\p@ } 12 | \addvspace {10\p@ } 13 | \addvspace {10\p@ } 14 | \addvspace {10\p@ } 15 | \addvspace {10\p@ } 16 | \addvspace {10\p@ } 17 | -------------------------------------------------------------------------------- /dl_lab.lot: -------------------------------------------------------------------------------- 1 | \babel@toc {american}{} 2 | \deactivateaddvspace 3 | \babel@toc {american}{} 4 | \addvspace {10\p@ } 5 | \addvspace {10\p@ } 6 | \addvspace {10\p@ } 7 | \addvspace {10\p@ } 8 | \contentsline {table}{\numberline {4.1}{\ignorespaces Function Table for 74181 ALU\relax }}{31}{table.caption.11}% 9 | \addvspace {10\p@ } 10 | \addvspace {10\p@ } 11 | \contentsline {table}{\numberline {6.1}{\ignorespaces Up Counter Output\relax }}{49}{table.caption.13}% 12 | \contentsline {table}{\numberline {6.2}{\ignorespaces Down Counter Output\relax }}{50}{table.caption.14}% 13 | \contentsline {table}{\numberline {6.3}{\ignorespaces Decade Counter Output\relax }}{52}{table.caption.15}% 14 | \contentsline {table}{\numberline {6.4}{\ignorespaces Ring Counter Output\relax }}{53}{table.caption.16}% 15 | \contentsline {table}{\numberline {6.5}{\ignorespaces Johnson Counter Output\relax }}{55}{table.caption.17}% 16 | \addvspace {10\p@ } 17 | \addvspace {10\p@ } 18 | \addvspace {10\p@ } 19 | \addvspace {10\p@ } 20 | \addvspace {10\p@ } 21 | \contentsline {table}{\numberline {11.1}{\ignorespaces R0 <- LdImm\relax }}{88}{table.caption.21}% 22 | \contentsline {table}{\numberline {11.2}{\ignorespaces R1 <- LdImm\relax }}{89}{table.caption.22}% 23 | \contentsline {table}{\numberline {11.3}{\ignorespaces ALU <- LdImm\relax }}{89}{table.caption.23}% 24 | \contentsline {table}{\numberline {11.4}{\ignorespaces R0 <- Inc(R0)\relax }}{89}{table.caption.24}% 25 | \contentsline {table}{\numberline {11.5}{\ignorespaces R0 <- R0 + R1\relax }}{90}{table.caption.25}% 26 | \contentsline {table}{\numberline {11.6}{\ignorespaces R0 <- R0 - R1\relax }}{90}{table.caption.26}% 27 | \contentsline {table}{\numberline {11.7}{\ignorespaces R1 <- R0\relax }}{90}{table.caption.27}% 28 | \contentsline {table}{\numberline {11.8}{\ignorespaces R0 <-> R1\relax }}{91}{table.caption.28}% 29 | \addvspace {10\p@ } 30 | \addvspace {10\p@ } 31 | \contentsline {table}{\numberline {A.1}{\ignorespaces Pinout For 7400\relax }}{100}{table.caption.30}% 32 | \contentsline {table}{\numberline {A.2}{\ignorespaces Pinout For 7402\relax }}{101}{table.caption.31}% 33 | \contentsline {table}{\numberline {A.3}{\ignorespaces Pinout For 7404\relax }}{102}{table.caption.32}% 34 | \contentsline {table}{\numberline {A.4}{\ignorespaces Pinout For 7408\relax }}{103}{table.caption.33}% 35 | \contentsline {table}{\numberline {A.5}{\ignorespaces Pinout For 7410\relax }}{104}{table.caption.34}% 36 | \contentsline {table}{\numberline {A.6}{\ignorespaces Pinout For 7411\relax }}{105}{table.caption.35}% 37 | \contentsline {table}{\numberline {A.7}{\ignorespaces Pinout For 7413\relax }}{106}{table.caption.36}% 38 | \contentsline {table}{\numberline {A.8}{\ignorespaces Pinout For 7414\relax }}{107}{table.caption.37}% 39 | \contentsline {table}{\numberline {A.9}{\ignorespaces Pinout For 7418\relax }}{108}{table.caption.38}% 40 | \contentsline {table}{\numberline {A.10}{\ignorespaces Pinout For 7419\relax }}{109}{table.caption.39}% 41 | \contentsline {table}{\numberline {A.11}{\ignorespaces Pinout For 7420\relax }}{110}{table.caption.40}% 42 | \contentsline {table}{\numberline {A.12}{\ignorespaces Pinout For 7421\relax }}{111}{table.caption.41}% 43 | \contentsline {table}{\numberline {A.13}{\ignorespaces Pinout For 7424\relax }}{112}{table.caption.42}% 44 | \contentsline {table}{\numberline {A.14}{\ignorespaces Pinout For 7427\relax }}{113}{table.caption.43}% 45 | \contentsline {table}{\numberline {A.15}{\ignorespaces Pinout For 7430\relax }}{114}{table.caption.44}% 46 | \contentsline {table}{\numberline {A.16}{\ignorespaces Pinout For 7432\relax }}{115}{table.caption.45}% 47 | \contentsline {table}{\numberline {A.17}{\ignorespaces Pinout For 7436\relax }}{116}{table.caption.46}% 48 | \contentsline {table}{\numberline {A.18}{\ignorespaces Truth Table For The 7442 Circuit\relax }}{117}{table.caption.47}% 49 | \contentsline {table}{\numberline {A.19}{\ignorespaces Pinout For 7442\relax }}{117}{table.caption.48}% 50 | \contentsline {table}{\numberline {A.20}{\ignorespaces Truth Table For The 7443 Circuit\relax }}{118}{table.caption.49}% 51 | \contentsline {table}{\numberline {A.21}{\ignorespaces Pinout For 7443\relax }}{119}{table.caption.50}% 52 | \contentsline {table}{\numberline {A.22}{\ignorespaces Truth Table For The 7444 Circuit\relax }}{120}{table.caption.51}% 53 | \contentsline {table}{\numberline {A.23}{\ignorespaces Pinout For 7444\relax }}{120}{table.caption.52}% 54 | \contentsline {table}{\numberline {A.24}{\ignorespaces Truth Table For The 7447 Circuit\relax }}{122}{table.caption.53}% 55 | \contentsline {table}{\numberline {A.25}{\ignorespaces Pinout For 7447\relax }}{123}{table.caption.54}% 56 | \contentsline {table}{\numberline {A.26}{\ignorespaces Pinout For 7451\relax }}{124}{table.caption.55}% 57 | \contentsline {table}{\numberline {A.27}{\ignorespaces Pinout For 7454\relax }}{125}{table.caption.56}% 58 | \contentsline {table}{\numberline {A.28}{\ignorespaces Pinout For 7458\relax }}{126}{table.caption.57}% 59 | \contentsline {table}{\numberline {A.29}{\ignorespaces Pinout For 7464\relax }}{127}{table.caption.58}% 60 | \contentsline {table}{\numberline {A.30}{\ignorespaces Pinout For 7474\relax }}{127}{table.caption.59}% 61 | \contentsline {table}{\numberline {A.31}{\ignorespaces Pinout For 7485\relax }}{128}{table.caption.60}% 62 | \contentsline {table}{\numberline {A.32}{\ignorespaces Pinout For 7486\relax }}{129}{table.caption.61}% 63 | \contentsline {table}{\numberline {A.33}{\ignorespaces Pinout For 74125\relax }}{130}{table.caption.62}% 64 | \contentsline {table}{\numberline {A.34}{\ignorespaces Pinout For 74165\relax }}{130}{table.caption.63}% 65 | \contentsline {table}{\numberline {A.35}{\ignorespaces Pinout For 74175\relax }}{131}{table.caption.64}% 66 | \contentsline {table}{\numberline {A.36}{\ignorespaces Pinout For 74266\relax }}{132}{table.caption.65}% 67 | \contentsline {table}{\numberline {A.37}{\ignorespaces Pinout For 74273\relax }}{133}{table.caption.66}% 68 | \contentsline {table}{\numberline {A.38}{\ignorespaces Pinout For 74283\relax }}{134}{table.caption.67}% 69 | \contentsline {table}{\numberline {A.39}{\ignorespaces Pinout For 74377\relax }}{135}{table.caption.68}% 70 | -------------------------------------------------------------------------------- /dl_lab.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/grself/CIS221_Lab_Manual/4421ab0de3e70976b8095e37eddb12ff9b597aa0/dl_lab.out -------------------------------------------------------------------------------- /dl_lab.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/grself/CIS221_Lab_Manual/4421ab0de3e70976b8095e37eddb12ff9b597aa0/dl_lab.pdf -------------------------------------------------------------------------------- /dl_lab.synctex.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/grself/CIS221_Lab_Manual/4421ab0de3e70976b8095e37eddb12ff9b597aa0/dl_lab.synctex.gz -------------------------------------------------------------------------------- /dl_lab.tex: -------------------------------------------------------------------------------- 1 | % ********************************************************* 2 | % Digital Logic 3 | % ********************************************************* 4 | 5 | \RequirePackage{fix-cm} % fix some latex issues see: http://texdoc.net/texmf-dist/doc/latex/base/fixltx2e.pdf 6 | \documentclass[ twoside,openright,titlepage,numbers=noenddot,headinclude, 7 | footinclude=true,cleardoublepage=empty,abstractoff, 8 | BCOR=5mm,fontsize=11pt,american]{scrreprt} 9 | 10 | % ********************************************************* 11 | % Note: Make all your adjustments in here 12 | % ********************************************************* 13 | \input{dl_lab-config} 14 | 15 | % ********************************************************* 16 | % Hyphenation 17 | % ********************************************************* 18 | %\hyphenation{put special hyphenation here} 19 | 20 | % ********************************************************* 21 | % Begin Document 22 | % ********************************************************* 23 | \begin{document} 24 | \frenchspacing 25 | \raggedbottom 26 | \selectlanguage{american} 27 | \pagenumbering{roman} 28 | \pagestyle{plain} 29 | % ********************************************************* 30 | % Frontmatter 31 | % ********************************************************* 32 | \include{FrontBackmatter/Titlepage} % >>>>> Include <<<<< 33 | \include{FrontBackmatter/Titleback} % >>>>> Include <<<<< 34 | \include{FrontBackmatter/Preface} % >>>>> Include <<<<< 35 | \pagestyle{scrheadings} % >>>>> Include <<<<< 36 | \cleardoublepage\include{FrontBackmatter/Contents} % >>>>> Include <<<<< 37 | 38 | % ********************************************************* 39 | % Part 1: Introduction 40 | % ********************************************************* 41 | \cleardoublepage\pagenumbering{arabic} 42 | %\setcounter{page}{90} 43 | % use \cleardoublepage here to avoid problems with pdfbookmark 44 | \cleardoublepage % >>>>> Include <<<<< 45 | \ctparttext{\LE is used to create and test simulations of digital circuits. This part of the lab manual includes only one lab designed to introduce \LE and teach the fundamentals of using this application.} 46 | \part{Introduction To Logisim-Evolution} 47 | %\printinunitsof{cm}\prntlen{\textwidth} % Print the width of the text line 48 | \include{Chapters/01_Mux21} 49 | 50 | % ********************************************************* 51 | % Part 2: Foundations 52 | % ********************************************************* 53 | % use \cleardoublepage here to avoid problems with pdfbookmark 54 | \cleardoublepage 55 | \ctparttext{\textsc{Foundational Exercises} are designed to provide practice with simple logic circuits in order to both develop skill with \LE and illustrate the foundations of digital logic.} 56 | \part{Foundations} 57 | \include{Chapters/02_Bool} 58 | \include{Chapters/03_Encoder} 59 | 60 | % ********************************************************* 61 | % Part 3: Combinational Circuits 62 | % ********************************************************* 63 | % use \cleardoublepage here to avoid problems with pdfbookmark 64 | \cleardoublepage % >>>>> Include <<<<< 65 | \ctparttext{\textsc{Combinational Logic} is the bedrock for all digital logic circuits. A combinational circuit's output is determined only by the status of the various inputs and an external clock signal is not necessary as in sequential circuits. All of the circuits completed so far in this manual have been combinational and the two labs in this part of the manual are designed to further develop the concepts of combinational digital logic with two relatively complex examples.} 66 | \part{Combinational Circuits} 67 | \include{Chapters/04_ALU} 68 | \include{Chapters/05_Vend} 69 | 70 | % ********************************************************* 71 | % Part 4: Sequential Circuits 72 | % ********************************************************* 73 | % use \cleardoublepage here to avoid problems with pdfbookmark 74 | \cleardoublepage 75 | \ctparttext{\textsc{Sequential Logic} circuits develop the concepts of clock-driven logic while creating several practical counters and memory circuits. These labs also introduce the \LE \textit{Chronogram}, which builds timing diagrams for sequential logic circuits.} 76 | \part{Sequential Circuits} 77 | \include{Chapters/06_Counter} 78 | \include{Chapters/07_Timer} 79 | \include{Chapters/08_React} 80 | \include{Chapters/09_ROM} 81 | \include{Chapters/10_RAM} 82 | 83 | % ********************************************************* 84 | % Part 5: Simulation 85 | % ********************************************************* 86 | % use \cleardoublepage here to avoid problems with pdfbookmark 87 | \cleardoublepage 88 | \ctparttext{\textsc{Simulation} is the most complex topic covered in this lab manual. Included in this manual are a simple processor, designed to teach the foundations of a Central Processing Unit, and an elevator simulator, designed to be a capstone project.} % >>>>> Include <<<<< 89 | \part{Simulation} % >>>>> Include <<<<< 90 | \include{Chapters/11_Processor} 91 | %%%%% Do Not Use Ch 12 Yet - it ain't ready! \include{Chapters/12_CPU} 92 | \include{Chapters/13_Elevator} 93 | 94 | % ********************************************************* 95 | % Backmatter 96 | % ********************************************************* 97 | \appendix 98 | %\renewcommand{\thechapter}{\alph{chapter}} 99 | \cleardoublepage 100 | \part{Appendix} 101 | \include{Chapters/50_Appendix} 102 | % ********************************************************* 103 | % Other Stuff in the Back 104 | % ********************************************************* 105 | \cleardoublepage\include{FrontBackmatter/Colophon} 106 | %\cleardoublepage\include{FrontBackmatter/StyleGuide} 107 | 108 | \blankpage 109 | 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library ieee; 39 | use ieee.std_logic_1164.all; 40 | --use ieee.numeric_std.all; 41 | 42 | entity VHDL_Component is 43 | port( 44 | ------------------------------------------------------------------------------ 45 | --Insert input ports below 46 | horloge_i : in std_logic; -- input bit example 47 | val_i : in std_logic_vector(3 downto 0); -- input vector example 48 | ------------------------------------------------------------------------------ 49 | --Insert output ports below 50 | max_o : out std_logic; -- output bit example 51 | cpt_o : out std_logic_vector(3 downto 0) -- output vector example 52 | ); 53 | end VHDL_Component; 54 | 55 | -------------------------------------------------------------------------------- 56 | --Complete your VHDL description below 57 | architecture type_architecture of VHDL_Component is 58 | 59 | 60 | begin 61 | 62 | 63 | end type_architecture; 64 | 65 | 66 | 67 | 68 | 69 | library ieee; 70 | use ieee.std_logic_1164.all; 71 | 72 | entity TCL_Generic is 73 | port( 74 | --Insert input ports below 75 | horloge_i : in std_logic; -- input bit example 76 | val_i : in std_logic_vector(3 downto 0); -- input vector example 77 | 78 | --Insert output ports below 79 | max_o : out std_logic; -- output bit example 80 | cpt_o : out std_logic_Vector(3 downto 0) -- output vector example 81 | ); 82 | end TCL_Generic; 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 |
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