├── .gitignore ├── README.md ├── bitstreams ├── bincombine.py ├── combine.bin ├── firmware.bin ├── hardware.bin └── readme.md ├── boards └── rev_c │ ├── assembly indecator │ ├── back.pdf │ └── front.pdf │ ├── bom │ └── schematic_BOM.xlsx │ ├── centroid │ └── schematic.mnt │ ├── gerber │ ├── schematic.cmp │ ├── schematic.crc │ ├── schematic.crs │ ├── schematic.drd │ ├── schematic.dri │ ├── schematic.gpi │ ├── schematic.l15 │ ├── schematic.ly2 │ ├── schematic.plc │ ├── schematic.pls │ ├── schematic.sol │ ├── schematic.stc │ └── schematic.sts │ ├── hyper_ram.lbr │ ├── hyperflash.lbr │ ├── modifiedsmd.lbr │ └── source file rev c │ ├── schematic.brd │ └── schematic.sch ├── icestorm └── hyperram.sh ├── radiant ├── pinout.pdc ├── pll │ ├── constraints │ │ └── pll_timing.ldc │ ├── for_lse │ │ ├── .vdbs │ │ │ ├── dbStat.txt │ │ │ ├── pll_rtl.vdb │ │ │ └── pll_tech.vdb │ │ ├── pll.arearep │ │ ├── pll.lsedata │ │ ├── pll.lseproj │ │ ├── pll.udb │ │ ├── pll.vm │ │ ├── pll_lse.twr │ │ ├── pll_lse.twr.html │ │ ├── pll_prim.v │ │ ├── synthesis.log │ │ ├── xxx_lse_cp_file_list │ │ └── xxx_lse_sign_file │ ├── misc │ │ ├── pll_tmpl.v │ │ └── pll_tmpl.vhd │ ├── pll.cfg │ ├── pll.ipx │ ├── pll.svg │ └── rtl │ │ ├── core │ │ └── lscc_pll.v │ │ ├── pll.v │ │ └── pll_bb.v ├── riscv32_radiant.rdf └── src │ ├── flash_io.v │ ├── hbc_io.v │ └── top.v ├── riscv32 ├── hardware │ ├── apio.ini │ ├── flash_io.v │ ├── hbc.v │ ├── hbc_io.v │ ├── picosoc.v │ ├── pinout.pcf │ ├── pll.v │ ├── simpleuart.v │ ├── spimemio.v │ ├── top.v │ ├── wdt.v │ └── zpicorv32.v └── software │ ├── Makefile │ ├── firmware.c │ ├── sections.c │ ├── sections.lds │ └── start.s ├── sim ├── hbc_io.v └── hbc_tb.v └── standalone ├── hbc.v ├── hbc_io.v └── hbc_wrapper.v /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gtjennings1/HyperBUS/HEAD/.gitignore -------------------------------------------------------------------------------- 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