├── fulladder_1_bit.v
├── xor_8_bit.v
├── and_8_bit.v
├── reg_file.v
├── overflow_detection.v
├── _xmsgs
└── pn_parser.xmsgs
├── alu_with_register_file.v
├── multi_8_bit_test.v
├── and_8_bit_test.v
├── xor_8_bit_test.v
├── adder_with_overflow.v
├── adder_8_bit_test.v
├── adder_8_bit_with_overflow_test.v
├── reg_file_test.v
├── four_to_one_mux.v
├── alu.v
├── alu_test.v
├── alu_with_register_file_tb.v
├── fulladder_1_bit_test.v
├── adder_8_bit.v
├── multi_8_bit.v
├── four_to_one_mux_test.v
├── overflow_detection_test.v
├── iseconfig
├── alu_8_bit.projectmgr
└── fulladder_1_bit.xreport
└── alu_8_bit.xise
/fulladder_1_bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // fulladder_1_bit.v - 1 Bit Full Adder
6 |
7 | module fulladder_1_bit(
8 | input a, b, c_in,
9 | output s, c_out
10 | );
11 | assign s = a ^ b ^ c_in;
12 | assign c_out = ((a ^ b) & c_in) | (a & b);
13 | endmodule
14 |
--------------------------------------------------------------------------------
/xor_8_bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // xor_8_bit.v - XOR Module
6 |
7 | module xor_8_bit(
8 | input [7:0] a,
9 | input [7:0] b,
10 | output reg [7:0] op
11 | );
12 |
13 | integer i;
14 |
15 | always @(*) begin
16 | for(i=0; i<8; i=i+1) begin
17 | op[i] = a[i] ^ b[i];
18 | end
19 | end
20 |
21 | endmodule
--------------------------------------------------------------------------------
/and_8_bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // and_8_bit.v - AND Module
6 |
7 | module and_8_bit(
8 | input [7:0] a,
9 | input [7:0] b,
10 | output reg [7:0] op
11 | );
12 |
13 | integer i;
14 |
15 | always @(*) begin
16 | for(i=0; i<8; i=i+1) begin
17 | op[i] = a[i] & b[i];
18 | end
19 | end
20 |
21 | endmodule
22 |
--------------------------------------------------------------------------------
/reg_file.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // reg_file.v - Register File
6 |
7 | module reg_file(
8 | input clock,
9 | input [23:0] data,
10 | input [15:0] result,
11 | output reg [7:0] a,
12 | output reg [7:0] b,
13 | output reg [7:0] y
14 | );
15 | reg [7:0] reg_x, reg_y;
16 |
17 | always @(posedge clock) begin
18 |
19 | a = data[23:16];
20 | b = data[15:8];
21 |
22 | reg_x = result[15:8];
23 | y = result[7:0];
24 |
25 | end
26 |
27 | endmodule
28 |
--------------------------------------------------------------------------------
/overflow_detection.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // overflow_detection.v - Overflow Detection Module
6 |
7 | module overflow_detection(
8 | input a_last_bit,
9 | input b_last_bit,
10 | input sum_last_bit,
11 | output reg overflow
12 | );
13 | reg x, y;
14 |
15 | always @(*) begin
16 | x = a_last_bit ^ b_last_bit;
17 | y = b_last_bit ^ sum_last_bit;
18 |
19 | if(x) overflow <= 1'b0;
20 | else if(!y) overflow <= 1'b0;
21 | else overflow <= 1'b1;
22 | end
23 |
24 | endmodule
25 |
--------------------------------------------------------------------------------
/_xmsgs/pn_parser.xmsgs:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
--------------------------------------------------------------------------------
/alu_with_register_file.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // alu_with_register_file.v - The Overall ALU Block
6 |
7 | module alu_with_register_file(
8 | input [25:0] instruction,
9 | input clock,
10 | output [15:0] out,
11 | output overflow,
12 | output c_out
13 | );
14 | wire [7:0] a, b, y;
15 | reg_file x1( .clock(clock), .data( instruction[23:0] ), .result( out ), .a(a), .b(b), .y(y) );
16 | alu x2( .a(a), .b(b), .op_code( instruction[25:24] ), .out(out), .overflow(overflow), .c_out(c_out) );
17 |
18 | endmodule
19 |
--------------------------------------------------------------------------------
/multi_8_bit_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module multi_8_bit_test;
7 |
8 | // Inputs
9 | reg [7:0] a;
10 | reg [7:0] b;
11 |
12 | // Outputs
13 | wire [15:0] p;
14 |
15 | // Instantiate the Unit Under Test (UUT)
16 | multi_8_bit uut (
17 | .a(a),
18 | .b(b),
19 | .p(p)
20 | );
21 |
22 | initial begin
23 | // Initialize Inputs
24 | a = 0;
25 | b = 0;
26 | end
27 |
28 | initial
29 | $monitor( "a(%b) * b(%b) = product(%b)", a, b, p );
30 |
31 | always @(a or b) begin
32 | #100 {a,b} = 278;
33 | #200 {a,b} = 1802;
34 | end
35 |
36 | endmodule
37 |
38 |
--------------------------------------------------------------------------------
/and_8_bit_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module and_8_bit_test;
7 |
8 | // Inputs
9 | reg [7:0] a;
10 | reg [7:0] b;
11 |
12 | // Outputs
13 | wire [7:0] op;
14 |
15 | // Instantiate the Unit Under Test (UUT)
16 | and_8_bit uut (
17 | .a(a),
18 | .b(b),
19 | .op(op)
20 | );
21 |
22 | initial begin
23 | // Initialize Inputs
24 | a = 0;
25 | b = 0;
26 | end
27 |
28 | initial
29 | $monitor( "a(%b) & b(%b) = product(%b)", a, b, op );
30 |
31 | always @(a or b) begin
32 | #100 {a,b} = 278;
33 | #200 {a,b} = 1802;
34 | end
35 |
36 |
37 |
38 | endmodule
39 |
40 |
--------------------------------------------------------------------------------
/xor_8_bit_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // xor_8_bit_test.v - Test Bench for XOR module.
6 |
7 | module xor_8_bit_test;
8 |
9 | // Inputs
10 | reg [7:0] a;
11 | reg [7:0] b;
12 |
13 | // Outputs
14 | wire [7:0] op;
15 |
16 | // Instantiate the Unit Under Test (UUT)
17 | xor_8_bit uut (
18 | .a(a),
19 | .b(b),
20 | .op(op)
21 | );
22 |
23 | initial begin
24 | // Initialize Inputs
25 | a = 0;
26 | b = 0;
27 | end
28 |
29 | initial
30 | $monitor( "a(%b) & b(%b) = product(%b)", a, b, op );
31 |
32 | always @(a or b) begin
33 | #100 {a,b} = 278;
34 | #200 {a,b} = 1802;
35 | end
36 |
37 | endmodule
38 |
39 |
--------------------------------------------------------------------------------
/adder_with_overflow.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // adder_8_bit_with_overflow.v - Adder Module combined with Overflow Module
6 |
7 | module adder_8_bit_with_overflow(
8 | input [7:0] a,
9 | input [7:0] b,
10 | output [7:0] sum,
11 | output c_out,
12 | output overflow
13 | );
14 | wire [7:0] temp_sum;
15 | wire [7:0] overflow_extend;
16 |
17 | adder_8_bit x1( .a(a), .b(b), .sum(temp_sum), .c_out(c_out) );
18 | overflow_detection x2( .a_last_bit( a[7] ), .b_last_bit( b[7] ), .sum_last_bit( temp_sum[7] ), .overflow(overflow) );
19 |
20 | assign overflow_extend = { {7{overflow}}, overflow};
21 |
22 | assign sum = ((~overflow_extend) & temp_sum);
23 |
24 | endmodule
25 |
--------------------------------------------------------------------------------
/adder_8_bit_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module adder_8_bit_test;
7 |
8 | // Inputs
9 | reg [7:0] a;
10 | reg [7:0] b;
11 |
12 | // Outputs
13 | wire [7:0] sum;
14 | wire c_out;
15 |
16 | integer i;
17 |
18 | // Instantiate the Unit Under Test (UUT)
19 | adder_8_bit uut (
20 | .a(a),
21 | .b(b),
22 | .sum(sum),
23 | .c_out(c_out)
24 | );
25 |
26 | initial begin
27 | // Initialize Inputs
28 | a = 0;
29 | b = 0;
30 | end
31 |
32 | initial
33 | $monitor( "a(%b) + b(%b) = carry sum(%b %b)", a, b, c_out, sum );
34 |
35 | always @(a or b) begin
36 | for ( i = 0; i < 16*16*16*16; i=i+1 )
37 | #1 {a,b} = i;
38 | end
39 |
40 | endmodule
41 |
--------------------------------------------------------------------------------
/adder_8_bit_with_overflow_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module adder_8_bit_with_overflow_test;
4 |
5 | // Inputs
6 | reg [7:0] a;
7 | reg [7:0] b;
8 |
9 | // Outputs
10 | wire [7:0] sum;
11 | wire c_out;
12 | wire overflow;
13 |
14 | integer i;
15 | // Instantiate the Unit Under Test (UUT)
16 | adder_8_bit_with_overflow uut (
17 | .a(a),
18 | .b(b),
19 | .sum(sum),
20 | .c_out(c_out),
21 | .overflow(overflow)
22 | );
23 |
24 | initial begin
25 | // Initialize Inputs
26 | a = 0;
27 | b = 0;
28 | end
29 |
30 | initial
31 | $monitor( "a(%b) + b(%b) = carry sum overflow(%b %b %b)", a, b, c_out, sum, overflow );
32 |
33 |
34 | always @(a or b) begin
35 | for ( i = 0; i < 16*16*16*16; i=i+1 )
36 | #1 {a,b} = i;
37 | end
38 |
39 | endmodule
40 |
41 |
--------------------------------------------------------------------------------
/reg_file_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module reg_file_test;
7 |
8 | // Inputs
9 | reg clock;
10 | reg [23:0] data;
11 | reg [15:0] result;
12 |
13 | // Outputs
14 |
15 | wire [7:0] a;
16 | wire [7:0] b;
17 | wire [7:0] y;
18 |
19 | // Instantiate the Unit Under Test (UUT)
20 | reg_file uut (
21 | .clock(clock),
22 | .data(data),
23 | .result(result),
24 | .a(a),
25 | .b(b),
26 | .y(y)
27 | );
28 |
29 | initial begin
30 | // Initialize Inputs
31 | clock = 0;
32 | data = 8371901;
33 | result = 0;
34 |
35 | #200
36 | result = 16'b0000000000110101;
37 | #300 $stop;
38 | end
39 |
40 | always
41 | #30 clock = !clock;
42 |
43 | endmodule
44 |
45 |
--------------------------------------------------------------------------------
/four_to_one_mux.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // four_to_one_mux.v - Multiplexer to select output.
6 |
7 | module four_to_one_mux(
8 | input [1:0]opcode,
9 | input [7:0]add_answer,
10 | input [15:0]mul_answer,
11 | input [7:0]and_answer,
12 | input [7:0]xor_answer,
13 | output reg [15:0]final_answer
14 | );
15 | reg [1:0]x;
16 |
17 | always@(*) begin
18 | assign x = opcode;
19 | case(x[1:0])
20 | 2'b00: assign final_answer={ {8{add_answer[7]} } , add_answer };
21 | 2'b01: assign final_answer={ {8{and_answer[7]} } , and_answer };
22 | 2'b11: assign final_answer= mul_answer;
23 | 2'b10: assign final_answer={ {8{xor_answer[7]} } , xor_answer };
24 | endcase
25 | end
26 |
27 | endmodule
28 |
--------------------------------------------------------------------------------
/alu.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // alu.v - ALU Module
6 |
7 | module alu(
8 | input [7:0] a,
9 | input [7:0] b,
10 | input [1:0] op_code,
11 | output [15:0] out,
12 | output overflow,
13 | output c_out
14 | );
15 | wire [7:0] add_result;
16 | wire [7:0] and_result;
17 | wire [15:0] mult_result;
18 | wire [7:0] xor_result;
19 | adder_8_bit_with_overflow x1( .a(a), .b(b), .sum(add_result), .c_out(c_out), .overflow(overflow) );
20 | and_8_bit x2( .a(a), .b(b), .op(and_result) );
21 | multi_8_bit x3( .a(a), .b(b), .p(mult_result) );
22 | xor_8_bit x4( .a(a), .b(b), .op(xor_result) );
23 | four_to_one_mux x5( .opcode(op_code), .add_answer(add_result), .mul_answer(mult_result), .xor_answer(xor_result), .and_answer(and_result), .final_answer(out) );
24 |
25 | endmodule
26 |
--------------------------------------------------------------------------------
/alu_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module alu_test;
7 |
8 | // Inputs
9 | reg [7:0] a;
10 | reg [7:0] b;
11 | reg [1:0] op_code;
12 |
13 | // Outputs
14 | wire [15:0] out;
15 | wire overflow;
16 | wire c_out;
17 |
18 | // Instantiate the Unit Under Test (UUT)
19 | alu uut (
20 | .a(a),
21 | .b(b),
22 | .op_code(op_code),
23 | .out(out),
24 | .overflow(overflow),
25 | .c_out(c_out)
26 | );
27 |
28 | initial begin
29 | // Initialize Inputs
30 | a = 0;
31 | b = 0;
32 | op_code = 0;
33 |
34 | end
35 |
36 | always @(a or b) begin
37 | #100 a = 45; b = 61; op_code = 2'b00;
38 | #200 a = 45; b = 61; op_code = 2'b01;
39 | #300 a = 45; b = 61; op_code = 2'b11;
40 | #300 a = 45; b = 61; op_code = 2'b10;
41 | end
42 |
43 | endmodule
44 |
45 |
--------------------------------------------------------------------------------
/alu_with_register_file_tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | module alu_with_register_file_tb;
4 |
5 | // Inputs
6 | reg [25:0] instruction;
7 | reg clock;
8 |
9 | // Outputs
10 | wire [15:0] out;
11 | wire overflow;
12 | wire c_out;
13 |
14 | // Instantiate the Unit Under Test (UUT)
15 | alu_with_register_file uut (
16 | .instruction(instruction),
17 | .clock(clock),
18 | .out(out),
19 | .overflow(overflow),
20 | .c_out(c_out)
21 | );
22 |
23 | initial begin
24 | instruction = 26'b00010011100001001000000000;
25 | clock = 0;
26 |
27 | #100 instruction = 26'b01010011100001001000000000;
28 |
29 | #100 instruction = 26'b11010011100001001000000000;
30 |
31 | #100 instruction = 26'b10010011100001001000000000;
32 |
33 | #100 instruction = 26'b00011110000111110000000000;
34 |
35 | #100 $stop;
36 | end
37 |
38 |
39 |
40 | always
41 | #33 clock = !clock;
42 |
43 | endmodule
44 |
45 |
--------------------------------------------------------------------------------
/fulladder_1_bit_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module fulladder_1_bit_test;
7 |
8 | // Inputs
9 | reg a;
10 | reg b;
11 | reg c_in;
12 |
13 | //Outputs
14 | wire s;
15 | wire c_out;
16 |
17 | integer i;
18 |
19 | // Instantiate the Unit Under Test (UUT)
20 | fulladder_1_bit uut (
21 | .a(a),
22 | .b(b),
23 | .c_in(c_in),
24 | .s(s),
25 | .c_out(c_out)
26 | );
27 |
28 | initial begin
29 | // Initialize Inputs
30 | a = 0;
31 | b = 0;
32 | c_in = 0;
33 | end
34 |
35 | always @ (a, b, c_in) begin
36 |
37 | //generate truth table
38 | for (i = 0; i < 8; i = i + 1)
39 | // every 10 ns set a, b, and cin to the binary rep. of i
40 | begin
41 | #10 {a, b, c_in} = i;
42 | $monitor("%d ns: a + b + cin = %b + %b + %b = cout sum = %b %b",
43 | $time, a, b, c_in, c_out, s );
44 | end
45 | // Wait 100 ns for global reset to finish
46 | #10 $stop;
47 |
48 | end
49 |
50 | endmodule
51 |
52 |
--------------------------------------------------------------------------------
/adder_8_bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // adder_8_bit.v - 8 bit Full Adder Module
6 |
7 | module adder_8_bit(
8 | input [7:0] a,
9 | input [7:0] b,
10 | output [7:0] sum,
11 | output c_out
12 | );
13 | wire c_in;
14 | assign c_in = 1'b0;
15 | fulladder_1_bit f0( .a( a[0] ), .b( b[0] ), .c_in( c_in ), .s( sum[0]), .c_out( ripple0 ) );
16 | fulladder_1_bit f1( .a( a[1] ), .b( b[1] ), .c_in( ripple0 ), .s( sum[1]), .c_out(ripple1) );
17 | fulladder_1_bit f2( .a( a[2] ), .b( b[2] ), .c_in( ripple1 ), .s( sum[2]), .c_out(ripple2) );
18 | fulladder_1_bit f3( .a( a[3] ), .b( b[3] ), .c_in( ripple2 ), .s( sum[3]), .c_out(ripple3) );
19 | fulladder_1_bit f4( .a( a[4] ), .b( b[4] ), .c_in( ripple3 ), .s( sum[4]), .c_out(ripple4) );
20 | fulladder_1_bit f5( .a( a[5] ), .b( b[5] ), .c_in( ripple4 ), .s( sum[5]), .c_out(ripple5) );
21 | fulladder_1_bit f6( .a( a[6] ), .b( b[6] ), .c_in( ripple5 ), .s( sum[6]), .c_out(ripple6) );
22 | fulladder_1_bit f7( .a( a[7] ), .b( b[7] ), .c_in( ripple6 ), .s( sum[7]), .c_out(c_out) );
23 | endmodule
24 |
--------------------------------------------------------------------------------
/multi_8_bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 | // multi_8_bit.v - Booth Multiplier Module
6 |
7 | module multi_8_bit(
8 | //a : multiplicand
9 | //b : multiplier
10 | //p : product
11 | input [7:0] a,
12 | input [7:0] b,
13 | output reg [15:0] p
14 | );
15 | reg [16:0] tmp_a, tmp_a_2comp, tmp_p;
16 | reg [7:0] a_2comp;
17 | integer i;
18 |
19 | always @(*) begin
20 | //Calculating the two's complement of the multiplicand.
21 | a_2comp = ((~ a) + 1'b1);
22 | tmp_a = {a, 9'b000000000};
23 | tmp_a_2comp = {a_2comp, 9'b000000000};
24 |
25 | //Temporary product initial value
26 | tmp_p = {8'b00000000, b, 1'b0};
27 |
28 | for(i=0; i<8; i=i+1) begin
29 | case(tmp_p[1:0])
30 | 2'b00 : tmp_p = { tmp_p[16], tmp_p[16:1] };
31 | 2'b01 : begin
32 | tmp_p = tmp_p + tmp_a;
33 | tmp_p = { tmp_p[16], tmp_p[16:1] };
34 | end
35 | 2'b11 : tmp_p = { tmp_p[16], tmp_p[16:1] };
36 | 2'b10 : begin
37 | tmp_p = tmp_p + tmp_a_2comp;
38 | tmp_p = { tmp_p[16], tmp_p[16:1] };
39 | end
40 | default : tmp_p = 17'bx;
41 | endcase
42 | end
43 |
44 | assign p = tmp_p[16:1];
45 | end
46 | endmodule
47 |
--------------------------------------------------------------------------------
/four_to_one_mux_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module four_to_one_mux_test;
7 |
8 | // Inputs
9 | reg [1:0] opcode;
10 | reg [7:0] add_answer;
11 | reg [15:0] mul_answer;
12 | reg [7:0] and_answer;
13 | reg [7:0] xor_answer;
14 |
15 | // Outputs
16 | wire [15:0] final_answer;
17 |
18 | // Instantiate the Unit Under Test (UUT)
19 | four_to_one_mux uut (
20 | .opcode(opcode),
21 | .add_answer(add_answer),
22 | .mul_answer(mul_answer),
23 | .and_answer(and_answer),
24 | .xor_answer(xor_answer),
25 | .final_answer(final_answer)
26 | );
27 |
28 | initial begin
29 | // Initialize Inputs
30 | opcode = 00;
31 | add_answer = 10;
32 | mul_answer = 11;
33 | and_answer = 12;
34 | xor_answer = 13;
35 | #100;
36 | opcode = 01;
37 | add_answer = 10;
38 | mul_answer = 11;
39 | and_answer = 12;
40 | xor_answer = 13;
41 |
42 | #100;
43 | opcode = 10;
44 | add_answer = 10;
45 | mul_answer = 11;
46 | and_answer = 12;
47 | xor_answer = 13;
48 | #100;
49 | opcode = 11;
50 | add_answer = 10;
51 | mul_answer = 11;
52 | and_answer = 12;
53 | xor_answer = 13;
54 | #100;
55 |
56 | end
57 |
58 | endmodule
59 |
60 |
--------------------------------------------------------------------------------
/overflow_detection_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | // GroupID-73(15116003_15116066) - Abhimanyu Bambhaniya & Utkarsh Gupta
4 | // Date: October 27, 2016
5 |
6 | module overflow_detection_test;
7 |
8 | // Inputs
9 | reg a_last_bit;
10 | reg b_last_bit;
11 | reg sum_last_bit;
12 |
13 | // Outputs
14 | wire overflow;
15 |
16 | // Instantiate the Unit Under Test (UUT)
17 | overflow_detection uut (
18 | .a_last_bit(a_last_bit),
19 | .b_last_bit(b_last_bit),
20 | .sum_last_bit(sum_last_bit),
21 | .overflow(overflow)
22 | );
23 |
24 | initial begin
25 | // Initialize Inputs
26 | a_last_bit = 0;
27 | b_last_bit = 0;
28 | sum_last_bit = 1;
29 | #100;
30 | a_last_bit = 0;
31 | b_last_bit = 1;
32 | sum_last_bit = 1;
33 | #100;
34 | a_last_bit = 1;
35 | b_last_bit = 0;
36 | sum_last_bit = 1;
37 | #100;
38 | a_last_bit = 1;
39 | b_last_bit = 1;
40 | sum_last_bit = 1;
41 | #100;
42 | a_last_bit = 0;
43 | b_last_bit = 0;
44 | sum_last_bit = 0;
45 | #100;
46 | a_last_bit = 1;
47 | b_last_bit = 0;
48 | sum_last_bit = 0;
49 | #100;
50 | a_last_bit = 0;
51 | b_last_bit = 1;
52 | sum_last_bit = 0;
53 | #100;
54 | a_last_bit = 1;
55 | b_last_bit = 1;
56 | sum_last_bit = 0;
57 | #100;
58 |
59 |
60 |
61 | end
62 |
63 | endmodule
64 |
65 |
--------------------------------------------------------------------------------
/iseconfig/alu_8_bit.projectmgr:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 | 2
10 | /adder_8_bit E:|Verilog Assignment|alu-8bit|adder_8_bit.v
11 | /adder_8_bit_with_overflow E:|Verilog Assignment|alu-8bit|adder_with_overflow.v
12 | /adder__8_bit_with_overflow E:|Verilog Assignment|alu-8bit|adder_with_overflow.v
13 | /adder_with_overflow E:|Verilog Assignment|alu-8bit|adder_with_overflow.v
14 | /adder_with_overflow E:|Verilog Assignment|alu-8bit|adder_with_overflow.v/x1 - adder_8_bit
15 | /alu E:|Verilog Assignment|alu-8bit|alu.v
16 | /alu_with_register_file E:|Verilog Assignment|alu-8bit|alu_with_register_file.v/x2 - alu
17 |
18 |
19 | x2 - alu (E:/Verilog Assignment/alu-8bit/alu.v)
20 |
21 | 0
22 | 0
23 | 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000132000000020000000000000000000000000200000064ffffffff000000810000000300000002000001320000000100000003000000000000000100000003
24 | true
25 | x2 - alu (E:/Verilog Assignment/alu-8bit/alu.v)
26 |
27 |
28 |
29 | 1
30 | Design Utilities
31 |
32 |
33 |
34 |
35 | 0
36 | 0
37 | 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000
38 | false
39 |
40 |
41 |
42 |
43 | 1
44 |
45 |
46 | 0
47 | 0
48 | 000000ff0000000000000001000000000000000001000000000000000000000000000000000000027d000000040101000100000000000000000000000064ffffffff0000008100000000000000040000008a0000000100000000000000240000000100000000000000660000000100000000000001690000000100000000
49 | false
50 | fulladder_1_bit.v
51 |
52 |
53 |
54 | 1
55 | work
56 |
57 |
58 | 0
59 | 0
60 | 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000
61 | false
62 | work
63 |
64 |
65 |
66 | 1
67 | Configure Target Device
68 | Design Utilities
69 | Implement Design
70 | Synthesize - XST
71 | User Constraints
72 |
73 |
74 |
75 |
76 | 0
77 | 0
78 | 000000ff000000000000000100000001000000000000000000000000000000000000000000000001cc000000010000000100000000000000000000000064ffffffff000000810000000000000001000001cc0000000100000000
79 | false
80 |
81 |
82 |
83 |
84 | 2
85 | /adder_8_bit_test E:|Verilog Assignment|alu-8bit|adder_8_bit_test.v
86 | /adder_8_bit_test E:|Verilog Assignment|alu-8bit|adder_8_bit_test.v/uut - adder_8_bit
87 | /adder_8_bit_with_overflow E:|Verilog Assignment|alu-8bit|adder_with_overflow.v
88 | /adder_8_bit_with_overflow_test E:|Verilog Assignment|alu-8bit|adder_8_bit_with_overflow_test.v
89 | /adder_8_bit_with_overflow_test E:|Verilog Assignment|alu-8bit|adder_8_bit_with_overflow_test.v/uut - adder_8_bit_with_overflow
90 | /adder_with_overflow E:|Verilog Assignment|alu-8bit|adder_with_overflow.v
91 | /alu E:|Verilog Assignment|alu-8bit|alu.v
92 | /alu_test E:|Verilog Assignment|alu-8bit|alu_test.v
93 | /alu_test E:|Verilog Assignment|alu-8bit|alu_test.v/uut - alu
94 | /alu_with_register_file E:|Verilog Assignment|alu-8bit|alu_with_register_file.v
95 | /alu_with_register_file_tb E:|Verilog Assignment|alu-8bit|alu_with_register_file_tb.v
96 | /and_8_bit_test E:|Verilog Assignment|alu-8bit|and_8_bit_test.v
97 | /four_to_one_mux_test E:|Verilog Assignment|alu-8bit|four_to_one_mux_test.v
98 | /fulladder_1_bit_test E:|Verilog Assignment|alu-8bit|fulladder_1_bit_test.v
99 | /multi_8_bit_test E:|Verilog Assignment|alu-8bit|multi_8_bit_test.v
100 | /mux_test E:|Verilog Assignment|alu-8bit|four_to_one_mux_test.v
101 | /overflow_detection_test E:|Verilog Assignment|alu-8bit|overflow_detection_test.v
102 | /reg_file_test E:|Verilog Assignment|alu-8bit|reg_file_test.v
103 | /xor_8_bit_test E:|Verilog Assignment|alu-8bit|xor_8_bit_test.v
104 |
105 |
106 | alu_with_register_file_tb (E:/Verilog Assignment/alu-8bit/alu_with_register_file_tb.v)
107 |
108 | 3
109 | 0
110 | 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000019e000000020000000000000000000000000200000064ffffffff0000008100000003000000020000019e0000000100000003000000000000000100000003
111 | true
112 | alu_with_register_file_tb (E:/Verilog Assignment/alu-8bit/alu_with_register_file_tb.v)
113 |
114 |
115 |
116 | 1
117 | Design Utilities
118 |
119 |
120 |
121 |
122 | 0
123 | 0
124 | 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000
125 | false
126 |
127 |
128 |
129 |
130 | 1
131 |
132 |
133 | Simulate Behavioral Model
134 |
135 | 0
136 | 0
137 | 000000ff000000000000000100000001000000000000000000000000000000000000000000000001cc000000010000000100000000000000000000000064ffffffff000000810000000000000001000001cc0000000100000000
138 | false
139 | Simulate Behavioral Model
140 |
141 | 000000ff00000000000000020000011b0000011b01000000050100000002
142 | Behavioral Simulation
143 |
144 |
145 |
--------------------------------------------------------------------------------
/iseconfig/fulladder_1_bit.xreport:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | 2016-10-29T20:23:35
5 | fulladder_1_bit
6 | Unknown
7 | E:/Verilog Assignment/alu-8bit/iseconfig/fulladder_1_bit.xreport
8 | E:/Verilog Assignment/alu_8_bit\
9 | 2016-10-28T18:27:06
10 | false
11 |
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/alu_8_bit.xise:
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