├── .cproject ├── .mxproject ├── .project ├── .settings ├── com.st.stm32cube.ide.mcu.sfr.prefs ├── com.st.stm32cube.ide.mcu.sfrview.prefs ├── language.settings.xml ├── org.eclipse.cdt.codan.core.prefs ├── org.eclipse.cdt.core.prefs └── stm32cubeide.project.prefs ├── Core ├── Inc │ ├── main.h │ ├── stm32g0xx_hal_conf.h │ └── stm32g0xx_it.h ├── Src │ ├── main.c │ ├── stm32g0xx_hal_msp.c │ ├── stm32g0xx_it.c │ ├── syscalls.c │ ├── sysmem.c │ └── system_stm32g0xx.c └── Startup │ └── startup_stm32g070kbtx.s ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32G0xx │ │ │ ├── Include │ │ │ ├── stm32g070xx.h │ │ │ ├── stm32g0xx.h │ │ │ └── system_stm32g0xx.h │ │ │ └── LICENSE.txt │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_armclang_ltm.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv81mml.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm35p.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── LICENSE.txt └── STM32G0xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32g0xx_hal.h │ ├── stm32g0xx_hal_adc.h │ ├── stm32g0xx_hal_adc_ex.h │ ├── stm32g0xx_hal_cortex.h │ ├── stm32g0xx_hal_def.h │ ├── stm32g0xx_hal_dma.h │ ├── stm32g0xx_hal_dma_ex.h │ ├── stm32g0xx_hal_exti.h │ ├── stm32g0xx_hal_flash.h │ ├── stm32g0xx_hal_flash_ex.h │ ├── stm32g0xx_hal_gpio.h │ ├── stm32g0xx_hal_gpio_ex.h │ ├── stm32g0xx_hal_pwr.h │ ├── stm32g0xx_hal_pwr_ex.h │ ├── stm32g0xx_hal_rcc.h │ ├── stm32g0xx_hal_rcc_ex.h │ ├── stm32g0xx_hal_tim.h │ ├── stm32g0xx_hal_tim_ex.h │ ├── stm32g0xx_ll_adc.h │ ├── stm32g0xx_ll_bus.h │ ├── stm32g0xx_ll_cortex.h │ ├── stm32g0xx_ll_dma.h │ ├── stm32g0xx_ll_dmamux.h │ ├── stm32g0xx_ll_exti.h │ ├── stm32g0xx_ll_gpio.h │ ├── stm32g0xx_ll_pwr.h │ ├── stm32g0xx_ll_rcc.h │ ├── stm32g0xx_ll_system.h │ ├── stm32g0xx_ll_tim.h │ └── stm32g0xx_ll_utils.h │ ├── LICENSE.txt │ ├── License.md │ └── Src │ ├── stm32g0xx_hal.c │ ├── stm32g0xx_hal_adc.c │ ├── stm32g0xx_hal_adc_ex.c │ ├── stm32g0xx_hal_cortex.c │ ├── stm32g0xx_hal_dma.c │ ├── stm32g0xx_hal_dma_ex.c │ ├── stm32g0xx_hal_exti.c │ ├── stm32g0xx_hal_flash.c │ ├── stm32g0xx_hal_flash_ex.c │ ├── stm32g0xx_hal_gpio.c │ ├── stm32g0xx_hal_pwr.c │ ├── stm32g0xx_hal_pwr_ex.c │ ├── stm32g0xx_hal_rcc.c │ ├── stm32g0xx_hal_rcc_ex.c │ ├── stm32g0xx_hal_tim.c │ ├── stm32g0xx_hal_tim_ex.c │ ├── stm32g0xx_ll_adc.c │ ├── stm32g0xx_ll_dma.c │ └── stm32g0xx_ll_rcc.c ├── ESC_V2_DShot_pwm.ioc ├── KiCad ├── ESC_G0_DevBoard_V2.kicad_pcb ├── ESC_G0_DevBoard_V2.kicad_sch └── readm.md ├── LICENSE ├── PCB ├── ESC_G0_DevBoard_V2_r11.zip └── Readme.md ├── README.md ├── STM32G070KBTX_FLASH.ld ├── cpp └── src │ └── main.cpp ├── images ├── ESC Front.jpg ├── ESC back.jpg └── misc.txt └── test.txt /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousLibFiles] 2 | LibFiles=Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_bus.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_system.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_utils.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ramfunc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_gpio.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_pwr.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_cortex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h;Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_tim.h;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_bus.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_system.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_utils.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ramfunc.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_gpio.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_pwr.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_cortex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h;Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h;Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_tim.h;Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g070xx.h;Drivers\CMSIS\Device\ST\STM32G0xx\Include\stm32g0xx.h;Drivers\CMSIS\Device\ST\STM32G0xx\Include\system_stm32g0xx.h;Drivers\CMSIS\Device\ST\STM32G0xx\Source\Templates\system_stm32g0xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; 3 | 4 | [PreviousUsedCubeIDEFiles] 5 | SourceFiles=Core\Src\main.c;Core\Src\stm32g0xx_it.c;Core\Src\stm32g0xx_hal_msp.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G0xx\Source\Templates\system_stm32g0xx.c;Core\Src\system_stm32g0xx.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c;Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G0xx\Source\Templates\system_stm32g0xx.c;Core\Src\system_stm32g0xx.c;;; 6 | HeaderPath=Drivers\STM32G0xx_HAL_Driver\Inc;Drivers\STM32G0xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32G0xx\Include;Drivers\CMSIS\Include;Core\Inc; 7 | CDefines=USE_HAL_DRIVER;STM32G070xx;USE_HAL_DRIVER;USE_HAL_DRIVER; 8 | 9 | [PreviousGenFiles] 10 | AdvancedFolderStructure=true 11 | HeaderFileListSize=3 12 | HeaderFiles#0=..\Core\Inc\stm32g0xx_it.h 13 | HeaderFiles#1=..\Core\Inc\stm32g0xx_hal_conf.h 14 | HeaderFiles#2=..\Core\Inc\main.h 15 | HeaderFolderListSize=1 16 | HeaderPath#0=..\Core\Inc 17 | HeaderFiles=; 18 | SourceFileListSize=3 19 | SourceFiles#0=..\Core\Src\stm32g0xx_it.c 20 | SourceFiles#1=..\Core\Src\stm32g0xx_hal_msp.c 21 | SourceFiles#2=..\Core\Src\main.c 22 | SourceFolderListSize=1 23 | SourcePath#0=..\Core\Src 24 | SourceFiles=; 25 | 26 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | ESC_V2_DShot_pwm 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.st.stm32cube.ide.mcu.MCUProjectNature 23 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature 24 | org.eclipse.cdt.core.cnature 25 | org.eclipse.cdt.core.ccnature 26 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature 27 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature 28 | com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature 29 | com.st.stm32cube.ide.mcu.MCURootProjectNature 30 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 31 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 32 | 33 | 34 | -------------------------------------------------------------------------------- /.settings/com.st.stm32cube.ide.mcu.sfr.prefs: -------------------------------------------------------------------------------- 1 | eclipse.preferences.version=1 2 | svd_custom_file_path= 3 | svd_file_path=platform\:/plugin/com.st.stm32cube.ide.mcu.productdb.debug/resources/cmsis/STMicroelectronics_CMSIS_SVD/STM32G070.svd 4 | -------------------------------------------------------------------------------- /.settings/com.st.stm32cube.ide.mcu.sfrview.prefs: -------------------------------------------------------------------------------- 1 | eclipse.preferences.version=1 2 | sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} 3 | -------------------------------------------------------------------------------- /.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /.settings/org.eclipse.cdt.core.prefs: -------------------------------------------------------------------------------- 1 | doxygen/doxygen_new_line_after_brief=true 2 | doxygen/doxygen_use_brief_tag=false 3 | doxygen/doxygen_use_javadoc_tags=true 4 | doxygen/doxygen_use_pre_tag=false 5 | doxygen/doxygen_use_structural_commands=false 6 | eclipse.preferences.version=1 7 | -------------------------------------------------------------------------------- /.settings/stm32cubeide.project.prefs: -------------------------------------------------------------------------------- 1 | 66BE74F758C12D739921AEA421D593D3=1 2 | 8DF89ED150041C4CBC7CB9A9CAA90856=7BD7E5427610A12EBC60D247FFC51784 3 | DC22A860405A8BF2F2C095E5B6529F12=7BD7E5427610A12EBC60D247FFC51784 4 | eclipse.preferences.version=1 5 | -------------------------------------------------------------------------------- /Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2022 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __MAIN_H 23 | #define __MAIN_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32g0xx_hal.h" 31 | 32 | /* Private includes ----------------------------------------------------------*/ 33 | /* USER CODE BEGIN Includes */ 34 | 35 | /* USER CODE END Includes */ 36 | 37 | /* Exported types ------------------------------------------------------------*/ 38 | /* USER CODE BEGIN ET */ 39 | 40 | /* USER CODE END ET */ 41 | 42 | /* Exported constants --------------------------------------------------------*/ 43 | /* USER CODE BEGIN EC */ 44 | 45 | /* USER CODE END EC */ 46 | 47 | /* Exported macro ------------------------------------------------------------*/ 48 | /* USER CODE BEGIN EM */ 49 | 50 | /* USER CODE END EM */ 51 | 52 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); 53 | 54 | /* Exported functions prototypes ---------------------------------------------*/ 55 | void Error_Handler(void); 56 | 57 | /* USER CODE BEGIN EFP */ 58 | void maincpp(); 59 | /* USER CODE END EFP */ 60 | 61 | /* Private defines -----------------------------------------------------------*/ 62 | #define ZC_A_Pin GPIO_PIN_9 63 | #define ZC_A_GPIO_Port GPIOB 64 | #define ZC_A_EXTI_IRQn EXTI4_15_IRQn 65 | #define ZC_C_Pin GPIO_PIN_14 66 | #define ZC_C_GPIO_Port GPIOC 67 | #define ZC_C_EXTI_IRQn EXTI4_15_IRQn 68 | #define ZC_B_Pin GPIO_PIN_15 69 | #define ZC_B_GPIO_Port GPIOC 70 | #define ZC_B_EXTI_IRQn EXTI4_15_IRQn 71 | #define BAT_VOLTS_Pin GPIO_PIN_2 72 | #define BAT_VOLTS_GPIO_Port GPIOA 73 | #define OD_C_Pin GPIO_PIN_6 74 | #define OD_C_GPIO_Port GPIOA 75 | #define PWM_C_Pin GPIO_PIN_7 76 | #define PWM_C_GPIO_Port GPIOA 77 | #define OD_B_Pin GPIO_PIN_0 78 | #define OD_B_GPIO_Port GPIOB 79 | #define PWM_B_Pin GPIO_PIN_1 80 | #define PWM_B_GPIO_Port GPIOB 81 | #define OD_A_Pin GPIO_PIN_2 82 | #define OD_A_GPIO_Port GPIOB 83 | #define REV_Pin GPIO_PIN_9 84 | #define REV_GPIO_Port GPIOA 85 | #define PWM_A_Pin GPIO_PIN_6 86 | #define PWM_A_GPIO_Port GPIOC 87 | #define signal_Pin GPIO_PIN_3 88 | #define signal_GPIO_Port GPIOB 89 | #define LED_Pin GPIO_PIN_4 90 | #define LED_GPIO_Port GPIOB 91 | #define Proshot_Pin GPIO_PIN_6 92 | #define Proshot_GPIO_Port GPIOB 93 | 94 | /* USER CODE BEGIN Private defines */ 95 | 96 | /* USER CODE END Private defines */ 97 | 98 | #ifdef __cplusplus 99 | } 100 | #endif 101 | 102 | #endif /* __MAIN_H */ 103 | -------------------------------------------------------------------------------- /Core/Inc/stm32g0xx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32g0xx_hal_conf.h 5 | * @author MCD Application Team 6 | * @brief HAL configuration file. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2018 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef STM32G0xx_HAL_CONF_H 23 | #define STM32G0xx_HAL_CONF_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Exported types ------------------------------------------------------------*/ 30 | /* Exported constants --------------------------------------------------------*/ 31 | 32 | /* ########################## Module Selection ############################## */ 33 | /** 34 | * @brief This is the list of modules to be used in the HAL driver 35 | */ 36 | #define HAL_MODULE_ENABLED 37 | #define HAL_ADC_MODULE_ENABLED 38 | /* #define HAL_CEC_MODULE_ENABLED */ 39 | /* #define HAL_COMP_MODULE_ENABLED */ 40 | /* #define HAL_CRC_MODULE_ENABLED */ 41 | /* #define HAL_CRYP_MODULE_ENABLED */ 42 | /* #define HAL_DAC_MODULE_ENABLED */ 43 | /* #define HAL_EXTI_MODULE_ENABLED */ 44 | /* #define HAL_FDCAN_MODULE_ENABLED */ 45 | /* #define HAL_HCD_MODULE_ENABLED */ 46 | /* #define HAL_I2C_MODULE_ENABLED */ 47 | /* #define HAL_I2S_MODULE_ENABLED */ 48 | /* #define HAL_IWDG_MODULE_ENABLED */ 49 | /* #define HAL_IRDA_MODULE_ENABLED */ 50 | /* #define HAL_LPTIM_MODULE_ENABLED */ 51 | /* #define HAL_PCD_MODULE_ENABLED */ 52 | /* #define HAL_RNG_MODULE_ENABLED */ 53 | /* #define HAL_RTC_MODULE_ENABLED */ 54 | /* #define HAL_SMARTCARD_MODULE_ENABLED */ 55 | /* #define HAL_SMBUS_MODULE_ENABLED */ 56 | /* #define HAL_SPI_MODULE_ENABLED */ 57 | #define HAL_TIM_MODULE_ENABLED 58 | /* #define HAL_UART_MODULE_ENABLED */ 59 | /* #define HAL_USART_MODULE_ENABLED */ 60 | /* #define HAL_WWDG_MODULE_ENABLED */ 61 | #define HAL_GPIO_MODULE_ENABLED 62 | #define HAL_EXTI_MODULE_ENABLED 63 | #define HAL_DMA_MODULE_ENABLED 64 | #define HAL_RCC_MODULE_ENABLED 65 | #define HAL_FLASH_MODULE_ENABLED 66 | #define HAL_PWR_MODULE_ENABLED 67 | #define HAL_CORTEX_MODULE_ENABLED 68 | 69 | /* ########################## Register Callbacks selection ############################## */ 70 | /** 71 | * @brief This is the list of modules where register callback can be used 72 | */ 73 | #define USE_HAL_ADC_REGISTER_CALLBACKS 0u 74 | #define USE_HAL_CEC_REGISTER_CALLBACKS 0u 75 | #define USE_HAL_COMP_REGISTER_CALLBACKS 0u 76 | #define USE_HAL_CRYP_REGISTER_CALLBACKS 0u 77 | #define USE_HAL_DAC_REGISTER_CALLBACKS 0u 78 | #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u 79 | #define USE_HAL_HCD_REGISTER_CALLBACKS 0u 80 | #define USE_HAL_I2C_REGISTER_CALLBACKS 0u 81 | #define USE_HAL_I2S_REGISTER_CALLBACKS 0u 82 | #define USE_HAL_IRDA_REGISTER_CALLBACKS 0u 83 | #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u 84 | #define USE_HAL_PCD_REGISTER_CALLBACKS 0u 85 | #define USE_HAL_RNG_REGISTER_CALLBACKS 0u 86 | #define USE_HAL_RTC_REGISTER_CALLBACKS 0u 87 | #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u 88 | #define USE_HAL_SPI_REGISTER_CALLBACKS 0u 89 | #define USE_HAL_TIM_REGISTER_CALLBACKS 0u 90 | #define USE_HAL_UART_REGISTER_CALLBACKS 0u 91 | #define USE_HAL_USART_REGISTER_CALLBACKS 0u 92 | #define USE_HAL_WWDG_REGISTER_CALLBACKS 0u 93 | 94 | /* ########################## Oscillator Values adaptation ####################*/ 95 | /** 96 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 97 | * This value is used by the RCC HAL module to compute the system frequency 98 | * (when HSE is used as system clock source, directly or through the PLL). 99 | */ 100 | #if !defined (HSE_VALUE) 101 | #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ 102 | #endif /* HSE_VALUE */ 103 | 104 | #if !defined (HSE_STARTUP_TIMEOUT) 105 | #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ 106 | #endif /* HSE_STARTUP_TIMEOUT */ 107 | 108 | /** 109 | * @brief Internal High Speed oscillator (HSI) value. 110 | * This value is used by the RCC HAL module to compute the system frequency 111 | * (when HSI is used as system clock source, directly or through the PLL). 112 | */ 113 | #if !defined (HSI_VALUE) 114 | #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ 115 | #endif /* HSI_VALUE */ 116 | 117 | #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 118 | /** 119 | * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. 120 | * This internal oscillator is mainly dedicated to provide a high precision clock to 121 | * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. 122 | * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency 123 | * which is subject to manufacturing process variations. 124 | */ 125 | #if !defined (HSI48_VALUE) 126 | #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. 127 | The real value my vary depending on manufacturing process variations.*/ 128 | #endif /* HSI48_VALUE */ 129 | #endif 130 | 131 | /** 132 | * @brief Internal Low Speed oscillator (LSI) value. 133 | */ 134 | #if !defined (LSI_VALUE) 135 | #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ 136 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 137 | The real value may vary depending on the variations 138 | in voltage and temperature.*/ 139 | /** 140 | * @brief External Low Speed oscillator (LSE) value. 141 | * This value is used by the UART, RTC HAL module to compute the system frequency 142 | */ 143 | #if !defined (LSE_VALUE) 144 | #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ 145 | #endif /* LSE_VALUE */ 146 | 147 | #if !defined (LSE_STARTUP_TIMEOUT) 148 | #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ 149 | #endif /* LSE_STARTUP_TIMEOUT */ 150 | 151 | /** 152 | * @brief External clock source for I2S1 peripheral 153 | * This value is used by the RCC HAL module to compute the I2S1 clock source 154 | * frequency. 155 | */ 156 | #if !defined (EXTERNAL_I2S1_CLOCK_VALUE) 157 | #define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/ 158 | #endif /* EXTERNAL_I2S1_CLOCK_VALUE */ 159 | 160 | #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 161 | /** 162 | * @brief External clock source for I2S2 peripheral 163 | * This value is used by the RCC HAL module to compute the I2S2 clock source 164 | * frequency. 165 | */ 166 | #if !defined (EXTERNAL_I2S2_CLOCK_VALUE) 167 | #define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/ 168 | #endif /* EXTERNAL_I2S2_CLOCK_VALUE */ 169 | #endif 170 | 171 | /* Tip: To avoid modifying this file each time you need to use different HSE, 172 | === you can define the HSE value in your toolchain compiler preprocessor. */ 173 | 174 | /* ########################### System Configuration ######################### */ 175 | /** 176 | * @brief This is the HAL system configuration section 177 | */ 178 | #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ 179 | #define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */ 180 | #define USE_RTOS 0U 181 | #define PREFETCH_ENABLE 1U 182 | #define INSTRUCTION_CACHE_ENABLE 1U 183 | 184 | /* ################## SPI peripheral configuration ########################## */ 185 | 186 | /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver 187 | * Activated: CRC code is present inside driver 188 | * Deactivated: CRC code cleaned from driver 189 | */ 190 | 191 | #define USE_SPI_CRC 0U 192 | 193 | /* ################## CRYP peripheral configuration ########################## */ 194 | 195 | #define USE_HAL_CRYP_SUSPEND_RESUME 1U 196 | 197 | /* ########################## Assert Selection ############################## */ 198 | /** 199 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 200 | * HAL drivers code 201 | */ 202 | /* #define USE_FULL_ASSERT 1U */ 203 | 204 | /* Includes ------------------------------------------------------------------*/ 205 | /** 206 | * @brief Include modules header file 207 | */ 208 | 209 | #ifdef HAL_RCC_MODULE_ENABLED 210 | #include "stm32g0xx_hal_rcc.h" 211 | #endif /* HAL_RCC_MODULE_ENABLED */ 212 | 213 | #ifdef HAL_GPIO_MODULE_ENABLED 214 | #include "stm32g0xx_hal_gpio.h" 215 | #endif /* HAL_GPIO_MODULE_ENABLED */ 216 | 217 | #ifdef HAL_DMA_MODULE_ENABLED 218 | #include "stm32g0xx_hal_dma.h" 219 | #endif /* HAL_DMA_MODULE_ENABLED */ 220 | 221 | #ifdef HAL_CORTEX_MODULE_ENABLED 222 | #include "stm32g0xx_hal_cortex.h" 223 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 224 | 225 | #ifdef HAL_ADC_MODULE_ENABLED 226 | #include "stm32g0xx_hal_adc.h" 227 | #include "stm32g0xx_hal_adc_ex.h" 228 | #endif /* HAL_ADC_MODULE_ENABLED */ 229 | 230 | #ifdef HAL_CEC_MODULE_ENABLED 231 | #include "stm32g0xx_hal_cec.h" 232 | #endif /* HAL_CEC_MODULE_ENABLED */ 233 | 234 | #ifdef HAL_COMP_MODULE_ENABLED 235 | #include "stm32g0xx_hal_comp.h" 236 | #endif /* HAL_COMP_MODULE_ENABLED */ 237 | 238 | #ifdef HAL_CRC_MODULE_ENABLED 239 | #include "stm32g0xx_hal_crc.h" 240 | #endif /* HAL_CRC_MODULE_ENABLED */ 241 | 242 | #ifdef HAL_CRYP_MODULE_ENABLED 243 | #include "stm32g0xx_hal_cryp.h" 244 | #endif /* HAL_CRYP_MODULE_ENABLED */ 245 | 246 | #ifdef HAL_DAC_MODULE_ENABLED 247 | #include "stm32g0xx_hal_dac.h" 248 | #endif /* HAL_DAC_MODULE_ENABLED */ 249 | 250 | #ifdef HAL_EXTI_MODULE_ENABLED 251 | #include "stm32g0xx_hal_exti.h" 252 | #endif /* HAL_EXTI_MODULE_ENABLED */ 253 | 254 | #ifdef HAL_FLASH_MODULE_ENABLED 255 | #include "stm32g0xx_hal_flash.h" 256 | #endif /* HAL_FLASH_MODULE_ENABLED */ 257 | 258 | #ifdef HAL_FDCAN_MODULE_ENABLED 259 | #include "stm32g0xx_hal_fdcan.h" 260 | #endif /* HAL_FDCAN_MODULE_ENABLED */ 261 | 262 | #ifdef HAL_HCD_MODULE_ENABLED 263 | #include "stm32g0xx_hal_hcd.h" 264 | #endif /* HAL_HCD_MODULE_ENABLED */ 265 | 266 | #ifdef HAL_I2C_MODULE_ENABLED 267 | #include "stm32g0xx_hal_i2c.h" 268 | #endif /* HAL_I2C_MODULE_ENABLED */ 269 | 270 | #ifdef HAL_I2S_MODULE_ENABLED 271 | #include "stm32g0xx_hal_i2s.h" 272 | #endif /* HAL_I2S_MODULE_ENABLED */ 273 | 274 | #ifdef HAL_IRDA_MODULE_ENABLED 275 | #include "stm32g0xx_hal_irda.h" 276 | #endif /* HAL_IRDA_MODULE_ENABLED */ 277 | 278 | #ifdef HAL_IWDG_MODULE_ENABLED 279 | #include "stm32g0xx_hal_iwdg.h" 280 | #endif /* HAL_IWDG_MODULE_ENABLED */ 281 | 282 | #ifdef HAL_LPTIM_MODULE_ENABLED 283 | #include "stm32g0xx_hal_lptim.h" 284 | #endif /* HAL_LPTIM_MODULE_ENABLED */ 285 | 286 | #ifdef HAL_PCD_MODULE_ENABLED 287 | #include "stm32g0xx_hal_pcd.h" 288 | #endif /* HAL_PCD_MODULE_ENABLED */ 289 | 290 | #ifdef HAL_PWR_MODULE_ENABLED 291 | #include "stm32g0xx_hal_pwr.h" 292 | #endif /* HAL_PWR_MODULE_ENABLED */ 293 | 294 | #ifdef HAL_RNG_MODULE_ENABLED 295 | #include "stm32g0xx_hal_rng.h" 296 | #endif /* HAL_RNG_MODULE_ENABLED */ 297 | 298 | #ifdef HAL_RTC_MODULE_ENABLED 299 | #include "stm32g0xx_hal_rtc.h" 300 | #endif /* HAL_RTC_MODULE_ENABLED */ 301 | 302 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 303 | #include "stm32g0xx_hal_smartcard.h" 304 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 305 | 306 | #ifdef HAL_SMBUS_MODULE_ENABLED 307 | #include "stm32g0xx_hal_smbus.h" 308 | #endif /* HAL_SMBUS_MODULE_ENABLED */ 309 | 310 | #ifdef HAL_SPI_MODULE_ENABLED 311 | #include "stm32g0xx_hal_spi.h" 312 | #endif /* HAL_SPI_MODULE_ENABLED */ 313 | 314 | #ifdef HAL_TIM_MODULE_ENABLED 315 | #include "stm32g0xx_hal_tim.h" 316 | #endif /* HAL_TIM_MODULE_ENABLED */ 317 | 318 | #ifdef HAL_UART_MODULE_ENABLED 319 | #include "stm32g0xx_hal_uart.h" 320 | #endif /* HAL_UART_MODULE_ENABLED */ 321 | 322 | #ifdef HAL_USART_MODULE_ENABLED 323 | #include "stm32g0xx_hal_usart.h" 324 | #endif /* HAL_USART_MODULE_ENABLED */ 325 | 326 | #ifdef HAL_WWDG_MODULE_ENABLED 327 | #include "stm32g0xx_hal_wwdg.h" 328 | #endif /* HAL_WWDG_MODULE_ENABLED */ 329 | 330 | /* Exported macro ------------------------------------------------------------*/ 331 | #ifdef USE_FULL_ASSERT 332 | /** 333 | * @brief The assert_param macro is used for functions parameters check. 334 | * @param expr If expr is false, it calls assert_failed function 335 | * which reports the name of the source file and the source 336 | * line number of the call that failed. 337 | * If expr is true, it returns no value. 338 | * @retval None 339 | */ 340 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 341 | /* Exported functions ------------------------------------------------------- */ 342 | void assert_failed(uint8_t *file, uint32_t line); 343 | #else 344 | #define assert_param(expr) ((void)0U) 345 | #endif /* USE_FULL_ASSERT */ 346 | 347 | #ifdef __cplusplus 348 | } 349 | #endif 350 | 351 | #endif /* STM32G0xx_HAL_CONF_H */ 352 | -------------------------------------------------------------------------------- /Core/Inc/stm32g0xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32g0xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32G0xx_IT_H 22 | #define __STM32G0xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void NMI_Handler(void); 50 | void HardFault_Handler(void); 51 | void SVC_Handler(void); 52 | void PendSV_Handler(void); 53 | void SysTick_Handler(void); 54 | void EXTI4_15_IRQHandler(void); 55 | void DMA1_Channel1_IRQHandler(void); 56 | void ADC1_IRQHandler(void); 57 | void TIM1_CC_IRQHandler(void); 58 | void TIM15_IRQHandler(void); 59 | void TIM17_IRQHandler(void); 60 | /* USER CODE BEGIN EFP */ 61 | 62 | /* USER CODE END EFP */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32G0xx_IT_H */ 69 | -------------------------------------------------------------------------------- /Core/Src/stm32g0xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32g0xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "stm32g0xx_it.h" 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN PD */ 34 | 35 | /* USER CODE END PD */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN PM */ 39 | 40 | /* USER CODE END PM */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* Private user code ---------------------------------------------------------*/ 53 | /* USER CODE BEGIN 0 */ 54 | 55 | /* USER CODE END 0 */ 56 | 57 | /* External variables --------------------------------------------------------*/ 58 | extern ADC_HandleTypeDef hadc1; 59 | extern DMA_HandleTypeDef hdma_tim1_ch3; 60 | extern TIM_HandleTypeDef htim1; 61 | extern TIM_HandleTypeDef htim15; 62 | extern TIM_HandleTypeDef htim17; 63 | /* USER CODE BEGIN EV */ 64 | 65 | /* USER CODE END EV */ 66 | 67 | /******************************************************************************/ 68 | /* Cortex-M0+ Processor Interruption and Exception Handlers */ 69 | /******************************************************************************/ 70 | /** 71 | * @brief This function handles Non maskable interrupt. 72 | */ 73 | void NMI_Handler(void) 74 | { 75 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 76 | 77 | /* USER CODE END NonMaskableInt_IRQn 0 */ 78 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 79 | while (1) 80 | { 81 | } 82 | /* USER CODE END NonMaskableInt_IRQn 1 */ 83 | } 84 | 85 | /** 86 | * @brief This function handles Hard fault interrupt. 87 | */ 88 | void HardFault_Handler(void) 89 | { 90 | /* USER CODE BEGIN HardFault_IRQn 0 */ 91 | 92 | /* USER CODE END HardFault_IRQn 0 */ 93 | while (1) 94 | { 95 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 96 | /* USER CODE END W1_HardFault_IRQn 0 */ 97 | } 98 | } 99 | 100 | /** 101 | * @brief This function handles System service call via SWI instruction. 102 | */ 103 | void SVC_Handler(void) 104 | { 105 | /* USER CODE BEGIN SVC_IRQn 0 */ 106 | 107 | /* USER CODE END SVC_IRQn 0 */ 108 | /* USER CODE BEGIN SVC_IRQn 1 */ 109 | 110 | /* USER CODE END SVC_IRQn 1 */ 111 | } 112 | 113 | /** 114 | * @brief This function handles Pendable request for system service. 115 | */ 116 | void PendSV_Handler(void) 117 | { 118 | /* USER CODE BEGIN PendSV_IRQn 0 */ 119 | 120 | /* USER CODE END PendSV_IRQn 0 */ 121 | /* USER CODE BEGIN PendSV_IRQn 1 */ 122 | 123 | /* USER CODE END PendSV_IRQn 1 */ 124 | } 125 | 126 | /** 127 | * @brief This function handles System tick timer. 128 | */ 129 | void SysTick_Handler(void) 130 | { 131 | /* USER CODE BEGIN SysTick_IRQn 0 */ 132 | 133 | /* USER CODE END SysTick_IRQn 0 */ 134 | HAL_IncTick(); 135 | /* USER CODE BEGIN SysTick_IRQn 1 */ 136 | 137 | /* USER CODE END SysTick_IRQn 1 */ 138 | } 139 | 140 | /******************************************************************************/ 141 | /* STM32G0xx Peripheral Interrupt Handlers */ 142 | /* Add here the Interrupt Handlers for the used peripherals. */ 143 | /* For the available peripheral interrupt handler names, */ 144 | /* please refer to the startup file (startup_stm32g0xx.s). */ 145 | /******************************************************************************/ 146 | 147 | /** 148 | * @brief This function handles EXTI line 4 to 15 interrupts. 149 | */ 150 | void EXTI4_15_IRQHandler(void) 151 | { 152 | /* USER CODE BEGIN EXTI4_15_IRQn 0 */ 153 | 154 | /* USER CODE END EXTI4_15_IRQn 0 */ 155 | HAL_GPIO_EXTI_IRQHandler(ZC_A_Pin); 156 | HAL_GPIO_EXTI_IRQHandler(ZC_C_Pin); 157 | HAL_GPIO_EXTI_IRQHandler(ZC_B_Pin); 158 | /* USER CODE BEGIN EXTI4_15_IRQn 1 */ 159 | 160 | /* USER CODE END EXTI4_15_IRQn 1 */ 161 | } 162 | 163 | /** 164 | * @brief This function handles DMA1 channel 1 interrupt. 165 | */ 166 | void DMA1_Channel1_IRQHandler(void) 167 | { 168 | /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ 169 | 170 | /* USER CODE END DMA1_Channel1_IRQn 0 */ 171 | HAL_DMA_IRQHandler(&hdma_tim1_ch3); 172 | /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ 173 | 174 | /* USER CODE END DMA1_Channel1_IRQn 1 */ 175 | } 176 | 177 | /** 178 | * @brief This function handles ADC1 interrupt. 179 | */ 180 | void ADC1_IRQHandler(void) 181 | { 182 | /* USER CODE BEGIN ADC1_IRQn 0 */ 183 | 184 | /* USER CODE END ADC1_IRQn 0 */ 185 | HAL_ADC_IRQHandler(&hadc1); 186 | /* USER CODE BEGIN ADC1_IRQn 1 */ 187 | 188 | /* USER CODE END ADC1_IRQn 1 */ 189 | } 190 | 191 | /** 192 | * @brief This function handles TIM1 capture compare interrupt. 193 | */ 194 | void TIM1_CC_IRQHandler(void) 195 | { 196 | /* USER CODE BEGIN TIM1_CC_IRQn 0 */ 197 | 198 | /* USER CODE END TIM1_CC_IRQn 0 */ 199 | HAL_TIM_IRQHandler(&htim1); 200 | /* USER CODE BEGIN TIM1_CC_IRQn 1 */ 201 | 202 | /* USER CODE END TIM1_CC_IRQn 1 */ 203 | } 204 | 205 | /** 206 | * @brief This function handles TIM15 global interrupt. 207 | */ 208 | void TIM15_IRQHandler(void) 209 | { 210 | /* USER CODE BEGIN TIM15_IRQn 0 */ 211 | 212 | /* USER CODE END TIM15_IRQn 0 */ 213 | HAL_TIM_IRQHandler(&htim15); 214 | /* USER CODE BEGIN TIM15_IRQn 1 */ 215 | 216 | /* USER CODE END TIM15_IRQn 1 */ 217 | } 218 | 219 | /** 220 | * @brief This function handles TIM17 global interrupt. 221 | */ 222 | void TIM17_IRQHandler(void) 223 | { 224 | /* USER CODE BEGIN TIM17_IRQn 0 */ 225 | 226 | /* USER CODE END TIM17_IRQn 0 */ 227 | HAL_TIM_IRQHandler(&htim17); 228 | /* USER CODE BEGIN TIM17_IRQn 1 */ 229 | 230 | /* USER CODE END TIM17_IRQn 1 */ 231 | } 232 | 233 | /* USER CODE BEGIN 1 */ 234 | 235 | /* USER CODE END 1 */ 236 | -------------------------------------------------------------------------------- /Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | 34 | /* Variables */ 35 | extern int __io_putchar(int ch) __attribute__((weak)); 36 | extern int __io_getchar(void) __attribute__((weak)); 37 | 38 | 39 | char *__env[1] = { 0 }; 40 | char **environ = __env; 41 | 42 | 43 | /* Functions */ 44 | void initialise_monitor_handles() 45 | { 46 | } 47 | 48 | int _getpid(void) 49 | { 50 | return 1; 51 | } 52 | 53 | int _kill(int pid, int sig) 54 | { 55 | errno = EINVAL; 56 | return -1; 57 | } 58 | 59 | void _exit (int status) 60 | { 61 | _kill(status, -1); 62 | while (1) {} /* Make sure we hang here */ 63 | } 64 | 65 | __attribute__((weak)) int _read(int file, char *ptr, int len) 66 | { 67 | int DataIdx; 68 | 69 | for (DataIdx = 0; DataIdx < len; DataIdx++) 70 | { 71 | *ptr++ = __io_getchar(); 72 | } 73 | 74 | return len; 75 | } 76 | 77 | __attribute__((weak)) int _write(int file, char *ptr, int len) 78 | { 79 | int DataIdx; 80 | 81 | for (DataIdx = 0; DataIdx < len; DataIdx++) 82 | { 83 | __io_putchar(*ptr++); 84 | } 85 | return len; 86 | } 87 | 88 | int _close(int file) 89 | { 90 | return -1; 91 | } 92 | 93 | 94 | int _fstat(int file, struct stat *st) 95 | { 96 | st->st_mode = S_IFCHR; 97 | return 0; 98 | } 99 | 100 | int _isatty(int file) 101 | { 102 | return 1; 103 | } 104 | 105 | int _lseek(int file, int ptr, int dir) 106 | { 107 | return 0; 108 | } 109 | 110 | int _open(char *path, int flags, ...) 111 | { 112 | /* Pretend like we always fail */ 113 | return -1; 114 | } 115 | 116 | int _wait(int *status) 117 | { 118 | errno = ECHILD; 119 | return -1; 120 | } 121 | 122 | int _unlink(char *name) 123 | { 124 | errno = ENOENT; 125 | return -1; 126 | } 127 | 128 | int _times(struct tms *buf) 129 | { 130 | return -1; 131 | } 132 | 133 | int _stat(char *file, struct stat *st) 134 | { 135 | st->st_mode = S_IFCHR; 136 | return 0; 137 | } 138 | 139 | int _link(char *old, char *new) 140 | { 141 | errno = EMLINK; 142 | return -1; 143 | } 144 | 145 | int _fork(void) 146 | { 147 | errno = EAGAIN; 148 | return -1; 149 | } 150 | 151 | int _execve(char *name, char **argv, char **env) 152 | { 153 | errno = ENOMEM; 154 | return -1; 155 | } 156 | -------------------------------------------------------------------------------- /Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | 27 | /** 28 | * Pointer to the current high watermark of the heap usage 29 | */ 30 | static uint8_t *__sbrk_heap_end = NULL; 31 | 32 | /** 33 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 34 | * and others from the C library 35 | * 36 | * @verbatim 37 | * ############################################################################ 38 | * # .data # .bss # newlib heap # MSP stack # 39 | * # # # # Reserved by _Min_Stack_Size # 40 | * ############################################################################ 41 | * ^-- RAM start ^-- _end _estack, RAM end --^ 42 | * @endverbatim 43 | * 44 | * This implementation starts allocating at the '_end' linker symbol 45 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 46 | * The implementation considers '_estack' linker symbol to be RAM end 47 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 48 | * reserved size, please increase the '_Min_Stack_Size'. 49 | * 50 | * @param incr Memory size 51 | * @return Pointer to allocated memory 52 | */ 53 | void *_sbrk(ptrdiff_t incr) 54 | { 55 | extern uint8_t _end; /* Symbol defined in the linker script */ 56 | extern uint8_t _estack; /* Symbol defined in the linker script */ 57 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 58 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 59 | const uint8_t *max_heap = (uint8_t *)stack_limit; 60 | uint8_t *prev_heap_end; 61 | 62 | /* Initialize heap end at first call */ 63 | if (NULL == __sbrk_heap_end) 64 | { 65 | __sbrk_heap_end = &_end; 66 | } 67 | 68 | /* Protect heap from growing into the reserved MSP stack */ 69 | if (__sbrk_heap_end + incr > max_heap) 70 | { 71 | errno = ENOMEM; 72 | return (void *)-1; 73 | } 74 | 75 | prev_heap_end = __sbrk_heap_end; 76 | __sbrk_heap_end += incr; 77 | 78 | return (void *)prev_heap_end; 79 | } 80 | -------------------------------------------------------------------------------- /Core/Src/system_stm32g0xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32g0xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32g0xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. 22 | * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to 23 | * configure the system clock before to branch to main program. 24 | * 25 | * This file configures the system clock as follows: 26 | *============================================================================= 27 | *----------------------------------------------------------------------------- 28 | * System Clock source | HSI 29 | *----------------------------------------------------------------------------- 30 | * SYSCLK(Hz) | 16000000 31 | *----------------------------------------------------------------------------- 32 | * HCLK(Hz) | 16000000 33 | *----------------------------------------------------------------------------- 34 | * AHB Prescaler | 1 35 | *----------------------------------------------------------------------------- 36 | * APB Prescaler | 1 37 | *----------------------------------------------------------------------------- 38 | * HSI Division factor | 1 39 | *----------------------------------------------------------------------------- 40 | * PLL_M | 1 41 | *----------------------------------------------------------------------------- 42 | * PLL_N | 8 43 | *----------------------------------------------------------------------------- 44 | * PLL_P | 7 45 | *----------------------------------------------------------------------------- 46 | * PLL_Q | 2 47 | *----------------------------------------------------------------------------- 48 | * PLL_R | 2 49 | *----------------------------------------------------------------------------- 50 | * Require 48MHz for RNG | Disabled 51 | *----------------------------------------------------------------------------- 52 | *============================================================================= 53 | ****************************************************************************** 54 | * @attention 55 | * 56 | * Copyright (c) 2018-2021 STMicroelectronics. 57 | * All rights reserved. 58 | * 59 | * This software is licensed under terms that can be found in the LICENSE file 60 | * in the root directory of this software component. 61 | * If no LICENSE file comes with this software, it is provided AS-IS. 62 | * 63 | ****************************************************************************** 64 | */ 65 | /** @addtogroup CMSIS 66 | * @{ 67 | */ 68 | 69 | /** @addtogroup stm32g0xx_system 70 | * @{ 71 | */ 72 | 73 | /** @addtogroup STM32G0xx_System_Private_Includes 74 | * @{ 75 | */ 76 | 77 | #include "stm32g0xx.h" 78 | 79 | #if !defined (HSE_VALUE) 80 | #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ 81 | #endif /* HSE_VALUE */ 82 | 83 | #if !defined (HSI_VALUE) 84 | #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ 85 | #endif /* HSI_VALUE */ 86 | 87 | #if !defined (LSI_VALUE) 88 | #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ 89 | #endif /* LSI_VALUE */ 90 | 91 | #if !defined (LSE_VALUE) 92 | #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ 93 | #endif /* LSE_VALUE */ 94 | 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @addtogroup STM32G0xx_System_Private_TypesDefinitions 100 | * @{ 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** @addtogroup STM32G0xx_System_Private_Defines 108 | * @{ 109 | */ 110 | 111 | /************************* Miscellaneous Configuration ************************/ 112 | /* Note: Following vector table addresses must be defined in line with linker 113 | configuration. */ 114 | /*!< Uncomment the following line if you need to relocate the vector table 115 | anywhere in Flash or Sram, else the vector table is kept at the automatic 116 | remap of boot address selected */ 117 | /* #define USER_VECT_TAB_ADDRESS */ 118 | 119 | #if defined(USER_VECT_TAB_ADDRESS) 120 | /*!< Uncomment the following line if you need to relocate your vector Table 121 | in Sram else user remap will be done in Flash. */ 122 | /* #define VECT_TAB_SRAM */ 123 | #if defined(VECT_TAB_SRAM) 124 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 125 | This value must be a multiple of 0x200. */ 126 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 127 | This value must be a multiple of 0x200. */ 128 | #else 129 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 130 | This value must be a multiple of 0x200. */ 131 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 132 | This value must be a multiple of 0x200. */ 133 | #endif /* VECT_TAB_SRAM */ 134 | #endif /* USER_VECT_TAB_ADDRESS */ 135 | /******************************************************************************/ 136 | /** 137 | * @} 138 | */ 139 | 140 | /** @addtogroup STM32G0xx_System_Private_Macros 141 | * @{ 142 | */ 143 | 144 | /** 145 | * @} 146 | */ 147 | 148 | /** @addtogroup STM32G0xx_System_Private_Variables 149 | * @{ 150 | */ 151 | /* The SystemCoreClock variable is updated in three ways: 152 | 1) by calling CMSIS function SystemCoreClockUpdate() 153 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 154 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 155 | Note: If you use this function to configure the system clock; then there 156 | is no need to call the 2 first functions listed above, since SystemCoreClock 157 | variable is updated automatically. 158 | */ 159 | uint32_t SystemCoreClock = 16000000UL; 160 | 161 | const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; 162 | const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /** @addtogroup STM32G0xx_System_Private_FunctionPrototypes 169 | * @{ 170 | */ 171 | 172 | /** 173 | * @} 174 | */ 175 | 176 | /** @addtogroup STM32G0xx_System_Private_Functions 177 | * @{ 178 | */ 179 | 180 | /** 181 | * @brief Setup the microcontroller system. 182 | * @param None 183 | * @retval None 184 | */ 185 | void SystemInit(void) 186 | { 187 | /* Configure the Vector Table location -------------------------------------*/ 188 | #if defined(USER_VECT_TAB_ADDRESS) 189 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ 190 | #endif /* USER_VECT_TAB_ADDRESS */ 191 | } 192 | 193 | /** 194 | * @brief Update SystemCoreClock variable according to Clock Register Values. 195 | * The SystemCoreClock variable contains the core clock (HCLK), it can 196 | * be used by the user application to setup the SysTick timer or configure 197 | * other parameters. 198 | * 199 | * @note Each time the core clock (HCLK) changes, this function must be called 200 | * to update SystemCoreClock variable value. Otherwise, any configuration 201 | * based on this variable will be incorrect. 202 | * 203 | * @note - The system frequency computed by this function is not the real 204 | * frequency in the chip. It is calculated based on the predefined 205 | * constant and the selected clock source: 206 | * 207 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor 208 | * 209 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) 210 | * 211 | * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE 212 | * 213 | * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE 214 | * 215 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) 216 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 217 | * 218 | * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value 219 | * 16 MHz) but the real value may vary depending on the variations 220 | * in voltage and temperature. 221 | * 222 | * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value 223 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 224 | * frequency of the crystal used. Otherwise, this function may 225 | * have wrong result. 226 | * 227 | * - The result of this function could be not correct when using fractional 228 | * value for HSE crystal. 229 | * 230 | * @param None 231 | * @retval None 232 | */ 233 | void SystemCoreClockUpdate(void) 234 | { 235 | uint32_t tmp; 236 | uint32_t pllvco; 237 | uint32_t pllr; 238 | uint32_t pllsource; 239 | uint32_t pllm; 240 | uint32_t hsidiv; 241 | 242 | /* Get SYSCLK source -------------------------------------------------------*/ 243 | switch (RCC->CFGR & RCC_CFGR_SWS) 244 | { 245 | case RCC_CFGR_SWS_0: /* HSE used as system clock */ 246 | SystemCoreClock = HSE_VALUE; 247 | break; 248 | 249 | case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ 250 | SystemCoreClock = LSI_VALUE; 251 | break; 252 | 253 | case RCC_CFGR_SWS_2: /* LSE used as system clock */ 254 | SystemCoreClock = LSE_VALUE; 255 | break; 256 | 257 | case RCC_CFGR_SWS_1: /* PLL used as system clock */ 258 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 259 | SYSCLK = PLL_VCO / PLLR 260 | */ 261 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 262 | pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; 263 | 264 | if(pllsource == 0x03UL) /* HSE used as PLL clock source */ 265 | { 266 | pllvco = (HSE_VALUE / pllm); 267 | } 268 | else /* HSI used as PLL clock source */ 269 | { 270 | pllvco = (HSI_VALUE / pllm); 271 | } 272 | pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 273 | pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); 274 | 275 | SystemCoreClock = pllvco/pllr; 276 | break; 277 | 278 | case 0x00000000U: /* HSI used as system clock */ 279 | default: /* HSI used as system clock */ 280 | hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); 281 | SystemCoreClock = (HSI_VALUE/hsidiv); 282 | break; 283 | } 284 | /* Compute HCLK clock frequency --------------------------------------------*/ 285 | /* Get HCLK prescaler */ 286 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; 287 | /* HCLK clock frequency */ 288 | SystemCoreClock >>= tmp; 289 | } 290 | 291 | 292 | /** 293 | * @} 294 | */ 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /** 301 | * @} 302 | */ 303 | -------------------------------------------------------------------------------- /Core/Startup/startup_stm32g070kbtx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32g070xx.s 4 | * @author MCD Application Team 5 | * @brief STM32G070xx devices vector table GCC toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M0+ processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | * Copyright (c) 2018-2021 STMicroelectronics. 18 | * All rights reserved. 19 | * 20 | * This software is licensed under terms that can be found in the LICENSE file 21 | * in the root directory of this software component. 22 | * If no LICENSE file comes with this software, it is provided AS-IS. 23 | * 24 | ****************************************************************************** 25 | */ 26 | 27 | .syntax unified 28 | .cpu cortex-m0plus 29 | .fpu softvfp 30 | .thumb 31 | 32 | .global g_pfnVectors 33 | .global Default_Handler 34 | 35 | /* start address for the initialization values of the .data section. 36 | defined in linker script */ 37 | .word _sidata 38 | /* start address for the .data section. defined in linker script */ 39 | .word _sdata 40 | /* end address for the .data section. defined in linker script */ 41 | .word _edata 42 | /* start address for the .bss section. defined in linker script */ 43 | .word _sbss 44 | /* end address for the .bss section. defined in linker script */ 45 | .word _ebss 46 | 47 | /** 48 | * @brief This is the code that gets called when the processor first 49 | * starts execution following a reset event. Only the absolutely 50 | * necessary set is performed, after which the application 51 | * supplied main() routine is called. 52 | * @param None 53 | * @retval None 54 | */ 55 | 56 | .section .text.Reset_Handler 57 | .weak Reset_Handler 58 | .type Reset_Handler, %function 59 | 60 | 61 | 62 | Reset_Handler: ldr r0, =_estack 63 | mov sp, r0 /* set stack pointer */ 64 | 65 | /* Call the clock system initialization function.*/ 66 | bl SystemInit 67 | 68 | /* Copy the data segment initializers from flash to SRAM */ 69 | ldr r0, =_sdata 70 | ldr r1, =_edata 71 | ldr r2, =_sidata 72 | movs r3, #0 73 | b LoopCopyDataInit 74 | 75 | CopyDataInit: 76 | ldr r4, [r2, r3] 77 | str r4, [r0, r3] 78 | adds r3, r3, #4 79 | 80 | LoopCopyDataInit: 81 | adds r4, r0, r3 82 | cmp r4, r1 83 | bcc CopyDataInit 84 | 85 | /* Zero fill the bss segment. */ 86 | ldr r2, =_sbss 87 | ldr r4, =_ebss 88 | movs r3, #0 89 | b LoopFillZerobss 90 | 91 | FillZerobss: 92 | str r3, [r2] 93 | adds r2, r2, #4 94 | 95 | LoopFillZerobss: 96 | cmp r2, r4 97 | bcc FillZerobss 98 | 99 | /* Call static constructors */ 100 | bl __libc_init_array 101 | /* Call the application s entry point.*/ 102 | bl main 103 | 104 | LoopForever: 105 | b LoopForever 106 | 107 | .size Reset_Handler, .-Reset_Handler 108 | 109 | /** 110 | * @brief This is the code that gets called when the processor receives an 111 | * unexpected interrupt. This simply enters an infinite loop, preserving 112 | * the system state for examination by a debugger. 113 | * 114 | * @param None 115 | * @retval None 116 | */ 117 | .section .text.Default_Handler,"ax",%progbits 118 | Default_Handler: 119 | Infinite_Loop: 120 | b Infinite_Loop 121 | .size Default_Handler, .-Default_Handler 122 | 123 | /****************************************************************************** 124 | * 125 | * The minimal vector table for a Cortex M0. Note that the proper constructs 126 | * must be placed on this to ensure that it ends up at physical address 127 | * 0x0000.0000. 128 | * 129 | ******************************************************************************/ 130 | .section .isr_vector,"a",%progbits 131 | .type g_pfnVectors, %object 132 | .size g_pfnVectors, .-g_pfnVectors 133 | 134 | g_pfnVectors: 135 | .word _estack 136 | .word Reset_Handler 137 | .word NMI_Handler 138 | .word HardFault_Handler 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word 0 143 | .word 0 144 | .word 0 145 | .word 0 146 | .word SVC_Handler 147 | .word 0 148 | .word 0 149 | .word PendSV_Handler 150 | .word SysTick_Handler 151 | .word WWDG_IRQHandler /* Window WatchDog */ 152 | .word 0 /* reserved */ 153 | .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ 154 | .word FLASH_IRQHandler /* FLASH */ 155 | .word RCC_IRQHandler /* RCC */ 156 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ 157 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ 158 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ 159 | .word 0 /* reserved */ 160 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 161 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ 162 | .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ 163 | .word ADC1_IRQHandler /* ADC1 */ 164 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ 165 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 166 | .word 0 /* reserved */ 167 | .word TIM3_IRQHandler /* TIM3 */ 168 | .word TIM6_IRQHandler /* TIM6 */ 169 | .word TIM7_IRQHandler /* TIM7 */ 170 | .word TIM14_IRQHandler /* TIM14 */ 171 | .word TIM15_IRQHandler /* TIM15 */ 172 | .word TIM16_IRQHandler /* TIM16 */ 173 | .word TIM17_IRQHandler /* TIM17 */ 174 | .word I2C1_IRQHandler /* I2C1 */ 175 | .word I2C2_IRQHandler /* I2C2 */ 176 | .word SPI1_IRQHandler /* SPI1 */ 177 | .word SPI2_IRQHandler /* SPI2 */ 178 | .word USART1_IRQHandler /* USART1 */ 179 | .word USART2_IRQHandler /* USART2 */ 180 | .word USART3_4_IRQHandler /* USART3, USART4 */ 181 | 182 | /******************************************************************************* 183 | * 184 | * Provide weak aliases for each Exception handler to the Default_Handler. 185 | * As they are weak aliases, any function with the same name will override 186 | * this definition. 187 | * 188 | *******************************************************************************/ 189 | 190 | .weak NMI_Handler 191 | .thumb_set NMI_Handler,Default_Handler 192 | 193 | .weak HardFault_Handler 194 | .thumb_set HardFault_Handler,Default_Handler 195 | 196 | .weak SVC_Handler 197 | .thumb_set SVC_Handler,Default_Handler 198 | 199 | .weak PendSV_Handler 200 | .thumb_set PendSV_Handler,Default_Handler 201 | 202 | .weak SysTick_Handler 203 | .thumb_set SysTick_Handler,Default_Handler 204 | 205 | .weak WWDG_IRQHandler 206 | .thumb_set WWDG_IRQHandler,Default_Handler 207 | 208 | .weak RTC_TAMP_IRQHandler 209 | .thumb_set RTC_TAMP_IRQHandler,Default_Handler 210 | 211 | .weak FLASH_IRQHandler 212 | .thumb_set FLASH_IRQHandler,Default_Handler 213 | 214 | .weak RCC_IRQHandler 215 | .thumb_set RCC_IRQHandler,Default_Handler 216 | 217 | .weak EXTI0_1_IRQHandler 218 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 219 | 220 | .weak EXTI2_3_IRQHandler 221 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 222 | 223 | .weak EXTI4_15_IRQHandler 224 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 225 | 226 | .weak DMA1_Channel1_IRQHandler 227 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 228 | 229 | .weak DMA1_Channel2_3_IRQHandler 230 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 231 | 232 | .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler 233 | .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler 234 | 235 | .weak ADC1_IRQHandler 236 | .thumb_set ADC1_IRQHandler,Default_Handler 237 | 238 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 239 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 240 | 241 | .weak TIM1_CC_IRQHandler 242 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 243 | 244 | .weak TIM3_IRQHandler 245 | .thumb_set TIM3_IRQHandler,Default_Handler 246 | 247 | .weak TIM6_IRQHandler 248 | .thumb_set TIM6_IRQHandler,Default_Handler 249 | 250 | .weak TIM7_IRQHandler 251 | .thumb_set TIM7_IRQHandler,Default_Handler 252 | 253 | .weak TIM14_IRQHandler 254 | .thumb_set TIM14_IRQHandler,Default_Handler 255 | 256 | .weak TIM15_IRQHandler 257 | .thumb_set TIM15_IRQHandler,Default_Handler 258 | 259 | .weak TIM16_IRQHandler 260 | .thumb_set TIM16_IRQHandler,Default_Handler 261 | 262 | .weak TIM17_IRQHandler 263 | .thumb_set TIM17_IRQHandler,Default_Handler 264 | 265 | .weak I2C1_IRQHandler 266 | .thumb_set I2C1_IRQHandler,Default_Handler 267 | 268 | .weak I2C2_IRQHandler 269 | .thumb_set I2C2_IRQHandler,Default_Handler 270 | 271 | .weak SPI1_IRQHandler 272 | .thumb_set SPI1_IRQHandler,Default_Handler 273 | 274 | .weak SPI2_IRQHandler 275 | .thumb_set SPI2_IRQHandler,Default_Handler 276 | 277 | .weak USART1_IRQHandler 278 | .thumb_set USART1_IRQHandler,Default_Handler 279 | 280 | .weak USART2_IRQHandler 281 | .thumb_set USART2_IRQHandler,Default_Handler 282 | 283 | .weak USART3_4_IRQHandler 284 | .thumb_set USART3_4_IRQHandler,Default_Handler 285 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32G0xx device used in the target application 11 | * - To use or not the peripherals drivers in application code(i.e. 12 | * code will be based on direct access to peripherals registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | * Copyright (c) 2018-2021 STMicroelectronics. 20 | * All rights reserved. 21 | * 22 | * This software is licensed under terms that can be found in the LICENSE file 23 | * in the root directory of this software component. 24 | * If no LICENSE file comes with this software, it is provided AS-IS. 25 | * 26 | ****************************************************************************** 27 | */ 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32g0xx 33 | * @{ 34 | */ 35 | 36 | #ifndef STM32G0xx_H 37 | #define STM32G0xx_H 38 | 39 | #ifdef __cplusplus 40 | extern "C" { 41 | #endif /* __cplusplus */ 42 | 43 | /** @addtogroup Library_configuration_section 44 | * @{ 45 | */ 46 | 47 | /** 48 | * @brief STM32 Family 49 | */ 50 | #if !defined (STM32G0) 51 | #define STM32G0 52 | #endif /* STM32G0 */ 53 | 54 | /* Uncomment the line below according to the target STM32G0 device used in your 55 | application 56 | */ 57 | 58 | #if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \ 59 | && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \ 60 | && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \ 61 | && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx) 62 | /* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */ 63 | /* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */ 64 | /* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */ 65 | /* #define STM32G070xx */ /*!< STM32G070xx Devices */ 66 | /* #define STM32G071xx */ /*!< STM32G071xx Devices */ 67 | /* #define STM32G081xx */ /*!< STM32G081xx Devices */ 68 | /* #define STM32G050xx */ /*!< STM32G050xx Devices */ 69 | /* #define STM32G051xx */ /*!< STM32G051xx Devices */ 70 | /* #define STM32G061xx */ /*!< STM32G061xx Devices */ 71 | /* #define STM32G030xx */ /*!< STM32G030xx Devices */ 72 | /* #define STM32G031xx */ /*!< STM32G031xx Devices */ 73 | /* #define STM32G041xx */ /*!< STM32G041xx Devices */ 74 | #endif 75 | 76 | /* Tip: To avoid modifying this file each time you need to switch between these 77 | devices, you can define the device in your toolchain compiler preprocessor. 78 | */ 79 | #if !defined (USE_HAL_DRIVER) 80 | /** 81 | * @brief Comment the line below if you will not use the peripherals drivers. 82 | In this case, these drivers will not be included and the application code will 83 | be based on direct access to peripherals registers 84 | */ 85 | /*#define USE_HAL_DRIVER */ 86 | #endif /* USE_HAL_DRIVER */ 87 | 88 | /** 89 | * @brief CMSIS Device version number $VERSION$ 90 | */ 91 | #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 92 | #define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ 93 | #define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ 94 | #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 95 | #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ 96 | |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ 97 | |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ 98 | |(__STM32G0_CMSIS_VERSION_RC)) 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** @addtogroup Device_Included 105 | * @{ 106 | */ 107 | 108 | #if defined(STM32G0B1xx) 109 | #include "stm32g0b1xx.h" 110 | #elif defined(STM32G0C1xx) 111 | #include "stm32g0c1xx.h" 112 | #elif defined(STM32G0B0xx) 113 | #include "stm32g0b0xx.h" 114 | #elif defined(STM32G071xx) 115 | #include "stm32g071xx.h" 116 | #elif defined(STM32G081xx) 117 | #include "stm32g081xx.h" 118 | #elif defined(STM32G070xx) 119 | #include "stm32g070xx.h" 120 | #elif defined(STM32G031xx) 121 | #include "stm32g031xx.h" 122 | #elif defined(STM32G041xx) 123 | #include "stm32g041xx.h" 124 | #elif defined(STM32G030xx) 125 | #include "stm32g030xx.h" 126 | #elif defined(STM32G051xx) 127 | #include "stm32g051xx.h" 128 | #elif defined(STM32G061xx) 129 | #include "stm32g061xx.h" 130 | #elif defined(STM32G050xx) 131 | #include "stm32g050xx.h" 132 | #else 133 | #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" 134 | #endif 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /** @addtogroup Exported_types 141 | * @{ 142 | */ 143 | typedef enum 144 | { 145 | RESET = 0, 146 | SET = !RESET 147 | } FlagStatus, ITStatus; 148 | 149 | typedef enum 150 | { 151 | DISABLE = 0, 152 | ENABLE = !DISABLE 153 | } FunctionalState; 154 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 155 | 156 | typedef enum 157 | { 158 | SUCCESS = 0, 159 | ERROR = !SUCCESS 160 | } ErrorStatus; 161 | 162 | /** 163 | * @} 164 | */ 165 | 166 | 167 | /** @addtogroup Exported_macros 168 | * @{ 169 | */ 170 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 171 | 172 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 173 | 174 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 175 | 176 | #define CLEAR_REG(REG) ((REG) = (0x0)) 177 | 178 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 179 | 180 | #define READ_REG(REG) ((REG)) 181 | 182 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 183 | 184 | /* Use of interrupt control for register exclusive access */ 185 | /* Atomic 32-bit register access macro to set one or several bits */ 186 | #define ATOMIC_SET_BIT(REG, BIT) \ 187 | do { \ 188 | uint32_t primask; \ 189 | primask = __get_PRIMASK(); \ 190 | __set_PRIMASK(1); \ 191 | SET_BIT((REG), (BIT)); \ 192 | __set_PRIMASK(primask); \ 193 | } while(0) 194 | 195 | /* Atomic 32-bit register access macro to clear one or several bits */ 196 | #define ATOMIC_CLEAR_BIT(REG, BIT) \ 197 | do { \ 198 | uint32_t primask; \ 199 | primask = __get_PRIMASK(); \ 200 | __set_PRIMASK(1); \ 201 | CLEAR_BIT((REG), (BIT)); \ 202 | __set_PRIMASK(primask); \ 203 | } while(0) 204 | 205 | /* Atomic 32-bit register access macro to clear and set one or several bits */ 206 | #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 207 | do { \ 208 | uint32_t primask; \ 209 | primask = __get_PRIMASK(); \ 210 | __set_PRIMASK(1); \ 211 | MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ 212 | __set_PRIMASK(primask); \ 213 | } while(0) 214 | 215 | /* Atomic 16-bit register access macro to set one or several bits */ 216 | #define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ 217 | 218 | /* Atomic 16-bit register access macro to clear one or several bits */ 219 | #define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ 220 | 221 | /* Atomic 16-bit register access macro to clear and set one or several bits */ 222 | #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 223 | 224 | /*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ 225 | /** 226 | * @} 227 | */ 228 | 229 | #if defined (USE_HAL_DRIVER) 230 | #include "stm32g0xx_hal.h" 231 | #endif /* USE_HAL_DRIVER */ 232 | 233 | #ifdef __cplusplus 234 | } 235 | #endif /* __cplusplus */ 236 | 237 | #endif /* STM32G0xx_H */ 238 | /** 239 | * @} 240 | */ 241 | 242 | /** 243 | * @} 244 | */ 245 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32g0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2018-2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /** @addtogroup CMSIS 19 | * @{ 20 | */ 21 | 22 | /** @addtogroup stm32g0xx_system 23 | * @{ 24 | */ 25 | 26 | /** 27 | * @brief Define to prevent recursive inclusion 28 | */ 29 | #ifndef SYSTEM_STM32G0XX_H 30 | #define SYSTEM_STM32G0XX_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | /** @addtogroup STM32G0xx_System_Includes 37 | * @{ 38 | */ 39 | 40 | /** 41 | * @} 42 | */ 43 | 44 | 45 | /** @addtogroup STM32G0xx_System_Exported_types 46 | * @{ 47 | */ 48 | /* This variable is updated in three ways: 49 | 1) by calling CMSIS function SystemCoreClockUpdate() 50 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 51 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 52 | Note: If you use this function to configure the system clock; then there 53 | is no need to call the 2 first functions listed above, since SystemCoreClock 54 | variable is updated automatically. 55 | */ 56 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 57 | 58 | extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 59 | extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32G0xx_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32G0xx_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32G0xx_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /*SYSTEM_STM32G0XX_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the Apache-2.0 license shall apply. 5 | You may obtain a copy of the Apache-2.0 at: 6 | https://opensource.org/licenses/Apache-2.0 7 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ 109 | (((MPU_RASR_ENABLE_Msk)))) 110 | 111 | /** 112 | * MPU Region Attribute and Size Register Value 113 | * 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 117 | * \param IsShareable Region is shareable between multiple bus masters. 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 120 | * \param SubRegionDisable Sub-region disable field. 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. 122 | */ 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 125 | 126 | /** 127 | * MPU Memory Access Attribute for strongly ordered memory. 128 | * - TEX: 000b 129 | * - Shareable 130 | * - Non-cacheable 131 | * - Non-bufferable 132 | */ 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 134 | 135 | /** 136 | * MPU Memory Access Attribute for device memory. 137 | * - TEX: 000b (if shareable) or 010b (if non-shareable) 138 | * - Shareable or non-shareable 139 | * - Non-cacheable 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 141 | * 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. 143 | */ 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 145 | 146 | /** 147 | * MPU Memory Access Attribute for normal memory. 148 | * - TEX: 1BBb (reflecting outer cacheability rules) 149 | * - Shareable or non-shareable 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 152 | * 153 | * \param OuterCp Configures the outer cache policy. 154 | * \param InnerCp Configures the inner cache policy. 155 | * \param IsShareable Configures the memory as shareable or non-shareable. 156 | */ 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute non-cacheable policy. 161 | */ 162 | #define ARM_MPU_CACHEP_NOCACHE 0U 163 | 164 | /** 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. 166 | */ 167 | #define ARM_MPU_CACHEP_WB_WRA 1U 168 | 169 | /** 170 | * MPU Memory Access Attribute write-through, no write allocate policy. 171 | */ 172 | #define ARM_MPU_CACHEP_WT_NWA 2U 173 | 174 | /** 175 | * MPU Memory Access Attribute write-back, no write allocate policy. 176 | */ 177 | #define ARM_MPU_CACHEP_WB_NWA 3U 178 | 179 | 180 | /** 181 | * Struct for a single MPU Region 182 | */ 183 | typedef struct { 184 | uint32_t RBAR; //!< The region base address register value (RBAR) 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 186 | } ARM_MPU_Region_t; 187 | 188 | /** Enable the MPU. 189 | * \param MPU_Control Default access permissions for unconfigured regions. 190 | */ 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 192 | { 193 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 194 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 195 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 196 | #endif 197 | __DSB(); 198 | __ISB(); 199 | } 200 | 201 | /** Disable the MPU. 202 | */ 203 | __STATIC_INLINE void ARM_MPU_Disable(void) 204 | { 205 | __DMB(); 206 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 207 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 208 | #endif 209 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | MPU->RNR = rnr; 218 | MPU->RASR = 0U; 219 | } 220 | 221 | /** Configure an MPU region. 222 | * \param rbar Value for RBAR register. 223 | * \param rsar Value for RSAR register. 224 | */ 225 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 226 | { 227 | MPU->RBAR = rbar; 228 | MPU->RASR = rasr; 229 | } 230 | 231 | /** Configure the given MPU region. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rsar Value for RSAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 237 | { 238 | MPU->RNR = rnr; 239 | MPU->RBAR = rbar; 240 | MPU->RASR = rasr; 241 | } 242 | 243 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 244 | * \param dst Destination data is copied to. 245 | * \param src Source data is copied from. 246 | * \param len Amount of data words to be copied. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 249 | { 250 | uint32_t i; 251 | for (i = 0U; i < len; ++i) 252 | { 253 | dst[i] = src[i]; 254 | } 255 | } 256 | 257 | /** Load the given number of MPU regions from a table. 258 | * \param table Pointer to the MPU configuration table. 259 | * \param cnt Amount of regions to be configured. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 262 | { 263 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 264 | while (cnt > MPU_TYPE_RALIASES) { 265 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 266 | table += MPU_TYPE_RALIASES; 267 | cnt -= MPU_TYPE_RALIASES; 268 | } 269 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 270 | } 271 | 272 | #endif 273 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | #if defined(MPU_RLAR_PXN_Pos) 105 | 106 | /** \brief Region Limit Address Register with PXN value 107 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 108 | * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. 109 | * \param IDX The attribute index to be associated with this memory region. 110 | */ 111 | #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ 112 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 113 | ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ 114 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 115 | (MPU_RLAR_EN_Msk)) 116 | 117 | #endif 118 | 119 | /** 120 | * Struct for a single MPU Region 121 | */ 122 | typedef struct { 123 | uint32_t RBAR; /*!< Region Base Address Register value */ 124 | uint32_t RLAR; /*!< Region Limit Address Register value */ 125 | } ARM_MPU_Region_t; 126 | 127 | /** Enable the MPU. 128 | * \param MPU_Control Default access permissions for unconfigured regions. 129 | */ 130 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 131 | { 132 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 133 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 134 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 135 | #endif 136 | __DSB(); 137 | __ISB(); 138 | } 139 | 140 | /** Disable the MPU. 141 | */ 142 | __STATIC_INLINE void ARM_MPU_Disable(void) 143 | { 144 | __DMB(); 145 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 146 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 147 | #endif 148 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 149 | } 150 | 151 | #ifdef MPU_NS 152 | /** Enable the Non-secure MPU. 153 | * \param MPU_Control Default access permissions for unconfigured regions. 154 | */ 155 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 156 | { 157 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 158 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 160 | #endif 161 | __DSB(); 162 | __ISB(); 163 | } 164 | 165 | /** Disable the Non-secure MPU. 166 | */ 167 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 168 | { 169 | __DMB(); 170 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 171 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 172 | #endif 173 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 174 | } 175 | #endif 176 | 177 | /** Set the memory attribute encoding to the given MPU. 178 | * \param mpu Pointer to the MPU to be configured. 179 | * \param idx The attribute index to be set [0-7] 180 | * \param attr The attribute value to be set. 181 | */ 182 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 183 | { 184 | const uint8_t reg = idx / 4U; 185 | const uint32_t pos = ((idx % 4U) * 8U); 186 | const uint32_t mask = 0xFFU << pos; 187 | 188 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 189 | return; // invalid index 190 | } 191 | 192 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 193 | } 194 | 195 | /** Set the memory attribute encoding. 196 | * \param idx The attribute index to be set [0-7] 197 | * \param attr The attribute value to be set. 198 | */ 199 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 200 | { 201 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 202 | } 203 | 204 | #ifdef MPU_NS 205 | /** Set the memory attribute encoding to the Non-secure MPU. 206 | * \param idx The attribute index to be set [0-7] 207 | * \param attr The attribute value to be set. 208 | */ 209 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 210 | { 211 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 212 | } 213 | #endif 214 | 215 | /** Clear and disable the given MPU region of the given MPU. 216 | * \param mpu Pointer to MPU to be used. 217 | * \param rnr Region number to be cleared. 218 | */ 219 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 220 | { 221 | mpu->RNR = rnr; 222 | mpu->RLAR = 0U; 223 | } 224 | 225 | /** Clear and disable the given MPU region. 226 | * \param rnr Region number to be cleared. 227 | */ 228 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 229 | { 230 | ARM_MPU_ClrRegionEx(MPU, rnr); 231 | } 232 | 233 | #ifdef MPU_NS 234 | /** Clear and disable the given Non-secure MPU region. 235 | * \param rnr Region number to be cleared. 236 | */ 237 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 238 | { 239 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 240 | } 241 | #endif 242 | 243 | /** Configure the given MPU region of the given MPU. 244 | * \param mpu Pointer to MPU to be used. 245 | * \param rnr Region number to be configured. 246 | * \param rbar Value for RBAR register. 247 | * \param rlar Value for RLAR register. 248 | */ 249 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 250 | { 251 | mpu->RNR = rnr; 252 | mpu->RBAR = rbar; 253 | mpu->RLAR = rlar; 254 | } 255 | 256 | /** Configure the given MPU region. 257 | * \param rnr Region number to be configured. 258 | * \param rbar Value for RBAR register. 259 | * \param rlar Value for RLAR register. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 262 | { 263 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 264 | } 265 | 266 | #ifdef MPU_NS 267 | /** Configure the given Non-secure MPU region. 268 | * \param rnr Region number to be configured. 269 | * \param rbar Value for RBAR register. 270 | * \param rlar Value for RLAR register. 271 | */ 272 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 273 | { 274 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 275 | } 276 | #endif 277 | 278 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 279 | * \param dst Destination data is copied to. 280 | * \param src Source data is copied from. 281 | * \param len Amount of data words to be copied. 282 | */ 283 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 284 | { 285 | uint32_t i; 286 | for (i = 0U; i < len; ++i) 287 | { 288 | dst[i] = src[i]; 289 | } 290 | } 291 | 292 | /** Load the given number of MPU regions from a table to the given MPU. 293 | * \param mpu Pointer to the MPU registers to be used. 294 | * \param rnr First region number to be configured. 295 | * \param table Pointer to the MPU configuration table. 296 | * \param cnt Amount of regions to be configured. 297 | */ 298 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 299 | { 300 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 301 | if (cnt == 1U) { 302 | mpu->RNR = rnr; 303 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 304 | } else { 305 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 306 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 307 | 308 | mpu->RNR = rnrBase; 309 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 310 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 311 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 312 | table += c; 313 | cnt -= c; 314 | rnrOffset = 0U; 315 | rnrBase += MPU_TYPE_RALIASES; 316 | mpu->RNR = rnrBase; 317 | } 318 | 319 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 320 | } 321 | } 322 | 323 | /** Load the given number of MPU regions from a table. 324 | * \param rnr First region number to be configured. 325 | * \param table Pointer to the MPU configuration table. 326 | * \param cnt Amount of regions to be configured. 327 | */ 328 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 329 | { 330 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 331 | } 332 | 333 | #ifdef MPU_NS 334 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 335 | * \param rnr First region number to be configured. 336 | * \param table Pointer to the MPU configuration table. 337 | * \param cnt Amount of regions to be configured. 338 | */ 339 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 340 | { 341 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 342 | } 343 | #endif 344 | 345 | #endif 346 | 347 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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-------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_hal_adc_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of ADC HAL extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2018 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32G0xx_HAL_ADC_EX_H 21 | #define STM32G0xx_HAL_ADC_EX_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32g0xx_hal_def.h" 29 | 30 | /** @addtogroup STM32G0xx_HAL_Driver 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup ADCEx 35 | * @{ 36 | */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 | * @{ 41 | */ 42 | 43 | /** 44 | * @} 45 | */ 46 | 47 | /* Exported constants --------------------------------------------------------*/ 48 | 49 | /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 54 | * @{ 55 | */ 56 | #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on 57 | all STM32 devices) */ 58 | /** 59 | * @} 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /* Exported macros -----------------------------------------------------------*/ 67 | 68 | /* Private macros ------------------------------------------------------------*/ 69 | 70 | /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 71 | * @{ 72 | */ 73 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ 74 | /* code of final user. */ 75 | 76 | /** 77 | * @brief Check whether or not ADC is independent. 78 | * @param __HANDLE__ ADC handle. 79 | * @note When multimode feature is not available, the macro always returns SET. 80 | * @retval SET (ADC is independent) or RESET (ADC is not). 81 | */ 82 | #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 83 | 84 | 85 | /** 86 | * @brief Calibration factor size verification (7 bits maximum). 87 | * @param __CALIBRATION_FACTOR__ Calibration factor value. 88 | * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 89 | */ 90 | #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 91 | 92 | /** 93 | * @brief Verify the ADC oversampling ratio. 94 | * @param __RATIO__ programmed ADC oversampling ratio. 95 | * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 96 | */ 97 | #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 98 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 99 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 100 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 101 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 102 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 103 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 104 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 105 | 106 | /** 107 | * @brief Verify the ADC oversampling shift. 108 | * @param __SHIFT__ programmed ADC oversampling shift. 109 | * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 110 | */ 111 | #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 112 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 113 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 114 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 115 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 116 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 117 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 118 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 119 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 120 | 121 | /** 122 | * @brief Verify the ADC oversampling triggered mode. 123 | * @param __MODE__ programmed ADC oversampling triggered mode. 124 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 125 | */ 126 | #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 127 | ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 128 | 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | 135 | /* Exported functions --------------------------------------------------------*/ 136 | /** @addtogroup ADCEx_Exported_Functions 137 | * @{ 138 | */ 139 | 140 | /** @addtogroup ADCEx_Exported_Functions_Group1 141 | * @{ 142 | */ 143 | /* IO operation functions *****************************************************/ 144 | 145 | /* ADC calibration */ 146 | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); 147 | uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc); 148 | HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); 149 | 150 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 151 | void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 152 | void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 153 | void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 154 | void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc); 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /** @addtogroup ADCEx_Exported_Functions_Group2 161 | * @{ 162 | */ 163 | /* Peripheral Control functions ***********************************************/ 164 | HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 165 | 166 | /** 167 | * @} 168 | */ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /** 175 | * @} 176 | */ 177 | 178 | /** 179 | * @} 180 | */ 181 | 182 | #ifdef __cplusplus 183 | } 184 | #endif 185 | 186 | #endif /* STM32G0xx_HAL_ADC_EX_H */ 187 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2018 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32G0xx_HAL_DEF 22 | #define STM32G0xx_HAL_DEF 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32g0xx.h" 30 | #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ 31 | #include 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | 35 | /** 36 | * @brief HAL Status structures definition 37 | */ 38 | typedef enum 39 | { 40 | HAL_OK = 0x00U, 41 | HAL_ERROR = 0x01U, 42 | HAL_BUSY = 0x02U, 43 | HAL_TIMEOUT = 0x03U 44 | } HAL_StatusTypeDef; 45 | 46 | /** 47 | * @brief HAL Lock structures definition 48 | */ 49 | typedef enum 50 | { 51 | HAL_UNLOCKED = 0x00U, 52 | HAL_LOCKED = 0x01U 53 | } HAL_LockTypeDef; 54 | 55 | /* Exported macros -----------------------------------------------------------*/ 56 | 57 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 58 | 59 | #define HAL_MAX_DELAY 0xFFFFFFFFU 60 | 61 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) 62 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 63 | 64 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 65 | do{ \ 66 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 67 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 68 | } while(0U) 69 | 70 | /** @brief Reset the Handles State field. 71 | * @param __HANDLE__ specifies the Peripheral Handle. 72 | * @note This macro can be used for the following purpose: 73 | * - When the Handle is declared as local variable; before passing it as parameter 74 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 75 | * to set to 0 the Handles "State" field. 76 | * Otherwise, "State" field may have any random value and the first time the function 77 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 78 | * (i.e. HAL_PPP_MspInit() will not be executed). 79 | * - When there is a need to reconfigure the low level hardware: instead of calling 80 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 81 | * In this later function, when the Handles "State" field is set to 0, it will execute the function 82 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 83 | * @retval None 84 | */ 85 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 86 | 87 | #if (USE_RTOS == 1U) 88 | /* Reserved for future use */ 89 | #error " USE_RTOS should be 0 in the current HAL release " 90 | #else 91 | #define __HAL_LOCK(__HANDLE__) \ 92 | do{ \ 93 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 94 | { \ 95 | return HAL_BUSY; \ 96 | } \ 97 | else \ 98 | { \ 99 | (__HANDLE__)->Lock = HAL_LOCKED; \ 100 | } \ 101 | }while (0U) 102 | 103 | #define __HAL_UNLOCK(__HANDLE__) \ 104 | do{ \ 105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 106 | }while (0U) 107 | #endif /* USE_RTOS */ 108 | 109 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 110 | #ifndef __weak 111 | #define __weak __attribute__((weak)) 112 | #endif /* __weak */ 113 | #ifndef __packed 114 | #define __packed __attribute__((packed)) 115 | #endif /* __packed */ 116 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 117 | #ifndef __weak 118 | #define __weak __attribute__((weak)) 119 | #endif /* __weak */ 120 | #ifndef __packed 121 | #define __packed __attribute__((__packed__)) 122 | #endif /* __packed */ 123 | #endif /* __GNUC__ */ 124 | 125 | 126 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 127 | /* GNU Compiler */ 128 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 129 | #ifndef __ALIGN_BEGIN 130 | #define __ALIGN_BEGIN 131 | #endif /* __ALIGN_BEGIN */ 132 | #ifndef __ALIGN_END 133 | #define __ALIGN_END __attribute__ ((aligned (4))) 134 | #endif /* __ALIGN_END */ 135 | #elif defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */ 136 | #ifndef __ALIGN_END 137 | #define __ALIGN_END __attribute__ ((aligned (4U))) 138 | #endif /* __ALIGN_END */ 139 | #ifndef __ALIGN_BEGIN 140 | #define __ALIGN_BEGIN 141 | #endif /* __ALIGN_BEGIN */ 142 | #else 143 | #ifndef __ALIGN_END 144 | #define __ALIGN_END 145 | #endif /* __ALIGN_END */ 146 | #ifndef __ALIGN_BEGIN 147 | /* ARM Compiler */ 148 | #if defined (__CC_ARM) /* ARM Compiler V5 */ 149 | #define __ALIGN_BEGIN __align(4U) 150 | /* IAR Compiler */ 151 | #elif defined (__ICCARM__) 152 | #define __ALIGN_BEGIN 153 | #endif /* __CC_ARM */ 154 | #endif /* __ALIGN_BEGIN */ 155 | #endif /* __GNUC__ */ 156 | 157 | /** 158 | * @brief __RAM_FUNC definition 159 | */ 160 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 161 | /* ARM Compiler V4/V5 and V6 162 | -------------------------- 163 | RAM functions are defined using the toolchain options. 164 | Functions that are executed in RAM should reside in a separate source module. 165 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 166 | area of a module to a memory space in physical RAM. 167 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 168 | dialog. 169 | */ 170 | #define __RAM_FUNC 171 | 172 | #elif defined ( __ICCARM__ ) 173 | /* ICCARM Compiler 174 | --------------- 175 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 176 | */ 177 | #define __RAM_FUNC __ramfunc 178 | 179 | #elif defined ( __GNUC__ ) 180 | /* GNU Compiler 181 | ------------ 182 | RAM functions are defined using a specific toolchain attribute 183 | "__attribute__((section(".RamFunc")))". 184 | */ 185 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 186 | 187 | #endif /* __CC_ARM || __ARMCC_VERSION */ 188 | 189 | /** 190 | * @brief __NOINLINE definition 191 | */ 192 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 193 | /* ARM V4/V5 and V6 & GNU Compiler 194 | ------------------------------- 195 | */ 196 | #define __NOINLINE __attribute__ ( (noinline) ) 197 | 198 | #elif defined ( __ICCARM__ ) 199 | /* ICCARM Compiler 200 | --------------- 201 | */ 202 | #define __NOINLINE _Pragma("optimize = no_inline") 203 | 204 | #endif /* __CC_ARM || __ARMCC_VERSION */ 205 | 206 | 207 | #ifdef __cplusplus 208 | } 209 | #endif 210 | 211 | #endif /* STM32G0xx_HAL_DEF */ 212 | 213 | 214 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_hal_dma_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of DMA HAL extension module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2018 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32G0xx_HAL_DMA_EX_H 21 | #define STM32G0xx_HAL_DMA_EX_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32g0xx_hal_def.h" 29 | #include "stm32g0xx_ll_dmamux.h" 30 | 31 | /** @addtogroup STM32G0xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup DMAEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief HAL DMAMUX Synchronization configuration structure definition 46 | */ 47 | typedef struct 48 | { 49 | uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. 50 | This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ 51 | 52 | uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. 53 | This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ 54 | 55 | FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled 56 | This parameter can take the value ENABLE or DISABLE */ 57 | 58 | FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. 59 | This parameter can take the value ENABLE or DISABLE */ 60 | 61 | uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event 62 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 63 | 64 | 65 | } HAL_DMA_MuxSyncConfigTypeDef; 66 | 67 | 68 | /** 69 | * @brief HAL DMAMUX request generator parameters structure definition 70 | */ 71 | typedef struct 72 | { 73 | uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator 74 | This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ 75 | 76 | uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. 77 | This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ 78 | 79 | uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event 80 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 81 | 82 | } HAL_DMA_MuxRequestGeneratorConfigTypeDef; 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | /* Exported constants --------------------------------------------------------*/ 89 | /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 90 | * @{ 91 | */ 92 | 93 | /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection 94 | * @{ 95 | */ 96 | #define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization signal from EXTI Line0 */ 97 | #define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization signal from EXTI Line1 */ 98 | #define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization signal from EXTI Line2 */ 99 | #define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization signal from EXTI Line3 */ 100 | #define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization signal from EXTI Line4 */ 101 | #define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization signal from EXTI Line5 */ 102 | #define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization signal from EXTI Line6 */ 103 | #define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization signal from EXTI Line7 */ 104 | #define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization signal from EXTI Line8 */ 105 | #define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization signal from EXTI Line9 */ 106 | #define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization signal from EXTI Line10 */ 107 | #define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization signal from EXTI Line11 */ 108 | #define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization signal from EXTI Line12 */ 109 | #define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization signal from EXTI Line1 3 */ 110 | #define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization signal from EXTI Line1 4 */ 111 | #define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization signal from EXTI Line1 5 */ 112 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization signal from DMAMUX channel0 Event */ 113 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization signal from DMAMUX channel1 Event */ 114 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2 /*!< Synchronization signal from DMAMUX channel2 Event */ 115 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3 /*!< Synchronization signal from DMAMUX channel3 Event */ 116 | #if defined(LPTIM1) 117 | #define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */ 118 | #endif /* LPTIM1 */ 119 | #if defined(LPTIM2) 120 | #define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */ 121 | #endif /* LPTIM2 */ 122 | #define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC /*!< Synchronization signal from TIM14 OC */ 123 | 124 | #define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection 130 | * @{ 131 | */ 132 | #define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */ 133 | #define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */ 134 | #define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */ 135 | #define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */ 136 | 137 | /** 138 | * @} 139 | */ 140 | 141 | /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection 142 | * @{ 143 | */ 144 | #define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request signal generation from EXTI Line0 */ 145 | #define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request signal generation from EXTI Line1 */ 146 | #define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request signal generation from EXTI Line2 */ 147 | #define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request signal generation from EXTI Line3 */ 148 | #define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request signal generation from EXTI Line4 */ 149 | #define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request signal generation from EXTI Line5 */ 150 | #define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request signal generation from EXTI Line6 */ 151 | #define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request signal generation from EXTI Line7 */ 152 | #define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request signal generation from EXTI Line8 */ 153 | #define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request signal generation from EXTI Line9 */ 154 | #define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request signal generation from EXTI Line10 */ 155 | #define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request signal generation from EXTI Line11 */ 156 | #define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request signal generation from EXTI Line12 */ 157 | #define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request signal generation from EXTI Line13 */ 158 | #define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request signal generation from EXTI Line14 */ 159 | #define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request signal generation from EXTI Line15 */ 160 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request signal generation from DMAMUX channel0 Event */ 161 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request signal generation from DMAMUX channel1 Event */ 162 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2 /*!< Request signal generation from DMAMUX channel2 Event */ 163 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3 /*!< Request signal generation from DMAMUX channel3 Event */ 164 | #if defined(LPTIM1) 165 | #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */ 166 | #endif /* LPTIM1 */ 167 | #if defined(LPTIM2) 168 | #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */ 169 | #endif /* LPTIM2 */ 170 | #define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC /*!< Request signal generation from TIM14 OC */ 171 | 172 | #define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC 173 | /** 174 | * @} 175 | */ 176 | 177 | /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection 178 | * @{ 179 | */ 180 | #define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */ 181 | #define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */ 182 | #define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */ 183 | #define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */ 184 | 185 | /** 186 | * @} 187 | */ 188 | 189 | /** 190 | * @} 191 | */ 192 | 193 | /* Exported macro ------------------------------------------------------------*/ 194 | 195 | /* Exported functions --------------------------------------------------------*/ 196 | /** @addtogroup DMAEx_Exported_Functions 197 | * @{ 198 | */ 199 | 200 | /* IO operation functions *****************************************************/ 201 | /** @addtogroup DMAEx_Exported_Functions_Group1 202 | * @{ 203 | */ 204 | 205 | /* ------------------------- REQUEST -----------------------------------------*/ 206 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, 207 | HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); 208 | HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); 209 | HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); 210 | /* -------------------------------------------------------------------------- */ 211 | 212 | /* ------------------------- SYNCHRO -----------------------------------------*/ 213 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); 214 | /* -------------------------------------------------------------------------- */ 215 | 216 | void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); 217 | 218 | /** 219 | * @} 220 | */ 221 | 222 | /** 223 | * @} 224 | */ 225 | 226 | 227 | /* Private macros ------------------------------------------------------------*/ 228 | /** @defgroup DMAEx_Private_Macros DMAEx Private Macros 229 | * @brief DMAEx private macros 230 | * @{ 231 | */ 232 | 233 | #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \ 234 | (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \ 235 | ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC))) 236 | 237 | #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) 238 | 239 | #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ 240 | ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ 241 | ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ 242 | ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) 243 | 244 | #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) 245 | 246 | #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ 247 | ((EVENT) == ENABLE)) 248 | 249 | #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \ 250 | (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \ 251 | ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN))) 252 | 253 | #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) 254 | 255 | #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \ 256 | ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ 257 | ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ 258 | ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) 259 | 260 | /** 261 | * @} 262 | */ 263 | 264 | 265 | /** 266 | * @} 267 | */ 268 | 269 | /** 270 | * @} 271 | */ 272 | 273 | #ifdef __cplusplus 274 | } 275 | #endif 276 | 277 | #endif /* STM32G0xx_HAL_DMA_EX_H */ 278 | 279 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_hal_flash_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of FLASH HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2018 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file in 13 | * the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | ****************************************************************************** 16 | */ 17 | 18 | /* Define to prevent recursive inclusion -------------------------------------*/ 19 | #ifndef STM32G0xx_HAL_FLASH_EX_H 20 | #define STM32G0xx_HAL_FLASH_EX_H 21 | 22 | #ifdef __cplusplus 23 | extern "C" { 24 | #endif 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | #include "stm32g0xx_hal_def.h" 28 | 29 | /** @addtogroup STM32G0xx_HAL_Driver 30 | * @{ 31 | */ 32 | 33 | /** @addtogroup FLASHEx 34 | * @{ 35 | */ 36 | 37 | /* Exported types ------------------------------------------------------------*/ 38 | /* Exported constants --------------------------------------------------------*/ 39 | /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants 40 | * @{ 41 | */ 42 | /** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check 43 | * @{ 44 | */ 45 | #define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ 46 | #define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */ 47 | /** 48 | * @} 49 | */ 50 | /** 51 | * @} 52 | */ 53 | 54 | /* Exported macro ------------------------------------------------------------*/ 55 | /* Exported functions --------------------------------------------------------*/ 56 | /** @addtogroup FLASHEx_Exported_Functions 57 | * @{ 58 | */ 59 | 60 | /* Extended Program operation functions *************************************/ 61 | /** @addtogroup FLASHEx_Exported_Functions_Group1 62 | * @{ 63 | */ 64 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); 65 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 66 | void HAL_FLASHEx_EnableDebugger(void); 67 | void HAL_FLASHEx_DisableDebugger(void); 68 | uint32_t HAL_FLASHEx_FlashEmptyCheck(void); 69 | void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); 70 | #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) 71 | void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks); 72 | #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ 73 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 74 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 75 | /** 76 | * @} 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /* Private macros ------------------------------------------------------------*/ 84 | /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants 85 | * @{ 86 | */ 87 | #define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */ 88 | #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */ 89 | /** 90 | * @} 91 | */ 92 | 93 | 94 | /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 95 | * @{ 96 | */ 97 | #define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) 98 | void FLASH_PageErase(uint32_t Banks, uint32_t Page); 99 | /** 100 | * @} 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | #ifdef __cplusplus 112 | } 113 | #endif 114 | 115 | #endif /* STM32G0xx_HAL_FLASH_EX_H */ 116 | 117 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_utils.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_ll_utils.h 4 | * @author MCD Application Team 5 | * @brief Header file of UTILS LL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2018 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | @verbatim 18 | ============================================================================== 19 | ##### How to use this driver ##### 20 | ============================================================================== 21 | [..] 22 | The LL UTILS driver contains a set of generic APIs that can be 23 | used by user: 24 | (+) Device electronic signature 25 | (+) Timing functions 26 | (+) PLL configuration functions 27 | 28 | @endverbatim 29 | ****************************************************************************** 30 | */ 31 | 32 | /* Define to prevent recursive inclusion -------------------------------------*/ 33 | #ifndef STM32G0xx_LL_UTILS_H 34 | #define STM32G0xx_LL_UTILS_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /* Includes ------------------------------------------------------------------*/ 41 | #include "stm32g0xx.h" 42 | 43 | /** @addtogroup STM32G0xx_LL_Driver 44 | * @{ 45 | */ 46 | 47 | /** @defgroup UTILS_LL UTILS 48 | * @{ 49 | */ 50 | 51 | /* Private types -------------------------------------------------------------*/ 52 | /* Private variables ---------------------------------------------------------*/ 53 | 54 | /* Private constants ---------------------------------------------------------*/ 55 | /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants 56 | * @{ 57 | */ 58 | 59 | /* Max delay can be used in LL_mDelay */ 60 | #define LL_MAX_DELAY 0xFFFFFFFFU 61 | 62 | /** 63 | * @brief Unique device ID register base address 64 | */ 65 | #define UID_BASE_ADDRESS UID_BASE 66 | 67 | /** 68 | * @brief Flash size data register base address 69 | */ 70 | #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE 71 | 72 | /** 73 | * @brief Package data register base address 74 | */ 75 | #define PACKAGE_BASE_ADDRESS PACKAGE_BASE 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /* Private macros ------------------------------------------------------------*/ 82 | /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros 83 | * @{ 84 | */ 85 | /** 86 | * @} 87 | */ 88 | /* Exported types ------------------------------------------------------------*/ 89 | /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures 90 | * @{ 91 | */ 92 | /** 93 | * @brief UTILS PLL structure definition 94 | */ 95 | typedef struct 96 | { 97 | uint32_t PLLM; /*!< Division factor for PLL VCO input clock. 98 | This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV 99 | 100 | This feature can be modified afterwards using unitary function 101 | @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 102 | 103 | uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. 104 | This parameter must be a number between Min_Data = 8 and Max_Data = 86 105 | 106 | This feature can be modified afterwards using unitary function 107 | @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 108 | 109 | uint32_t PLLR; /*!< Division for the main system clock. 110 | This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV 111 | 112 | This feature can be modified afterwards using unitary function 113 | @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 114 | } LL_UTILS_PLLInitTypeDef; 115 | 116 | /** 117 | * @brief UTILS System, AHB and APB buses clock configuration structure definition 118 | */ 119 | typedef struct 120 | { 121 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 122 | This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV 123 | 124 | This feature can be modified afterwards using unitary function 125 | @ref LL_RCC_SetAHBPrescaler(). */ 126 | 127 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 128 | This parameter can be a value of @ref RCC_LL_EC_APB1_DIV 129 | 130 | This feature can be modified afterwards using unitary function 131 | @ref LL_RCC_SetAPB1Prescaler(). */ 132 | } LL_UTILS_ClkInitTypeDef; 133 | 134 | /** 135 | * @} 136 | */ 137 | 138 | /* Exported constants --------------------------------------------------------*/ 139 | /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants 140 | * @{ 141 | */ 142 | 143 | /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation 144 | * @{ 145 | */ 146 | #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ 147 | #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ 148 | /** 149 | * @} 150 | */ 151 | 152 | /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE 153 | * @{ 154 | */ 155 | #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 156 | #define LL_UTILS_PACKAGETYPE_QFP100 0x00000000U /*!< LQFP100 package type */ 157 | #define LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000001U /*!< LQFP32/UFQFPN32 General purpose (GP) */ 158 | #define LL_UTILS_PACKAGETYPE_QFN32_N 0x00000002U /*!< LQFP32/UFQFPN32 N-version */ 159 | #define LL_UTILS_PACKAGETYPE_QFN48_GP 0x00000004U /*!< LQFP48/UFQPN48 General purpose (GP) */ 160 | #define LL_UTILS_PACKAGETYPE_QFN48_N 0x00000005U /*!< LQFP48/UFQPN48 N-version */ 161 | #define LL_UTILS_PACKAGETYPE_WLCSP52 0x00000006U /*!< WLCSP52 */ 162 | #define LL_UTILS_PACKAGETYPE_QFN64_GP 0x00000007U /*!< LQFP64 General purpose (GP) */ 163 | #define LL_UTILS_PACKAGETYPE_QFN64_N 0x00000008U /*!< LQFP64 N-version */ 164 | #define LL_UTILS_PACKAGETYPE_BGA64_N 0x0000000AU /*!< UFBGA64 N-version */ 165 | #define LL_UTILS_PACKAGETYPE_QFP80 0x0000000BU /*!< LQFP80 package type */ 166 | #define LL_UTILS_PACKAGETYPE_BGA100 0x0000000CU /*!< UBGA100 package type */ 167 | #elif defined(STM32G061xx) || defined(STM32G051xx) || defined(STM32G050xx) || defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx) 168 | #define LL_UTILS_PACKAGETYPE_SO8 0x00000001U /*!< SO8 package type */ 169 | #define LL_UTILS_PACKAGETYPE_WLCSP18 0x00000002U /*!< WLCSP18 package type */ 170 | #define LL_UTILS_PACKAGETYPE_TSSOP20 0x00000003U /*!< TSSOP20 package type */ 171 | #define LL_UTILS_PACKAGETYPE_QFP28 0x00000004U /*!< UFQFPN28 package type */ 172 | #define LL_UTILS_PACKAGETYPE_QFN32 0x00000005U /*!< UFQFPN32 / LQFP32 package type */ 173 | #define LL_UTILS_PACKAGETYPE_QFN48 0x00000007U /*!< UFQFPN48 / LQFP48 package type */ 174 | #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) 175 | #define LL_UTILS_PACKAGETYPE_QFN28_GP 0x00000000U /*!< UFQFPN28 general purpose (GP) package type */ 176 | #define LL_UTILS_PACKAGETYPE_QFN28_PD 0x00000001U /*!< UFQFPN28 Power Delivery (PD) */ 177 | #define LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000004U /*!< UFQFPN32 / LQFP32 general purpose (GP) package type */ 178 | #define LL_UTILS_PACKAGETYPE_QFN32_PD 0x00000005U /*!< UFQFPN32 / LQFP32 Power Delivery (PD) package type */ 179 | #define LL_UTILS_PACKAGETYPE_QFN48 0x00000008U /*!< UFQFPN48 / LQFP488 package type */ 180 | #define LL_UTILS_PACKAGETYPE_QFP64 0x0000000CU /*!< LQPF64 package type */ 181 | #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /* Exported macro ------------------------------------------------------------*/ 191 | 192 | /* Exported functions --------------------------------------------------------*/ 193 | /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions 194 | * @{ 195 | */ 196 | 197 | /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE 198 | * @{ 199 | */ 200 | 201 | /** 202 | * @brief Get Word0 of the unique device identifier (UID based on 96 bits) 203 | * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format 204 | */ 205 | __STATIC_INLINE uint32_t LL_GetUID_Word0(void) 206 | { 207 | return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); 208 | } 209 | 210 | /** 211 | * @brief Get Word1 of the unique device identifier (UID based on 96 bits) 212 | * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) 213 | */ 214 | __STATIC_INLINE uint32_t LL_GetUID_Word1(void) 215 | { 216 | return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); 217 | } 218 | 219 | /** 220 | * @brief Get Word2 of the unique device identifier (UID based on 96 bits) 221 | * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] 222 | */ 223 | __STATIC_INLINE uint32_t LL_GetUID_Word2(void) 224 | { 225 | return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); 226 | } 227 | 228 | /** 229 | * @brief Get Flash memory size 230 | * @note This bitfield indicates the size of the device Flash memory expressed in 231 | * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. 232 | * @retval FLASH_SIZE[15:0]: Flash memory size 233 | */ 234 | __STATIC_INLINE uint32_t LL_GetFlashSize(void) 235 | { 236 | return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL); 237 | } 238 | 239 | /** 240 | * @brief Get Package type 241 | * @retval PKG[3:0]: Package type - This parameter can be a value of @ref UTILS_EC_PACKAGETYPE 242 | * @if defined(STM32G0C1xx) 243 | * @arg @ref LL_UTILS_PACKAGETYPE_QFP100 244 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP 245 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN32_N 246 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN48_GP 247 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN48_N 248 | * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP52 249 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN64_GP 250 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN64_N 251 | * @arg @ref LL_UTILS_PACKAGETYPE_BGA64_N 252 | * @arg @ref LL_UTILS_PACKAGETYPE_QFP80 253 | * @arg @ref LL_UTILS_PACKAGETYPE_BGA100 254 | * @elif defined(STM32G061xx) || defined(STM32G041xx) 255 | * @arg @ref LL_UTILS_PACKAGETYPE_SO8 256 | * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP18 257 | * @arg @ref LL_UTILS_PACKAGETYPE_TSSOP20 258 | * @arg @ref LL_UTILS_PACKAGETYPE_QFP28 259 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN32 260 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN48 261 | * @elif defined(STM32G081xx) 262 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN28_GP 263 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN28_PD 264 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP 265 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN32_PD 266 | * @arg @ref LL_UTILS_PACKAGETYPE_QFN48 267 | * @arg @ref LL_UTILS_PACKAGETYPE_QFP64 268 | * @endif 269 | * 270 | */ 271 | __STATIC_INLINE uint32_t LL_GetPackageType(void) 272 | { 273 | #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) 274 | return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); 275 | #else 276 | return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU); 277 | #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ 278 | } 279 | 280 | /** 281 | * @} 282 | */ 283 | 284 | /** @defgroup UTILS_LL_EF_DELAY DELAY 285 | * @{ 286 | */ 287 | 288 | /** 289 | * @brief This function configures the Cortex-M SysTick source of the time base. 290 | * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) 291 | * @note When a RTOS is used, it is recommended to avoid changing the SysTick 292 | * configuration by calling this function, for a delay use rather osDelay RTOS service. 293 | * @param Ticks Number of ticks 294 | * @retval None 295 | */ 296 | __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) 297 | { 298 | /* Configure the SysTick to have interrupt in 1ms time base */ 299 | SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 300 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 301 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 302 | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ 303 | } 304 | 305 | void LL_Init1msTick(uint32_t HCLKFrequency); 306 | void LL_mDelay(uint32_t Delay); 307 | 308 | /** 309 | * @} 310 | */ 311 | 312 | /** @defgroup UTILS_EF_SYSTEM SYSTEM 313 | * @{ 314 | */ 315 | 316 | void LL_SetSystemCoreClock(uint32_t HCLKFrequency); 317 | ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 318 | LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 319 | ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, 320 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 321 | ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); 322 | 323 | /** 324 | * @} 325 | */ 326 | 327 | /** 328 | * @} 329 | */ 330 | 331 | /** 332 | * @} 333 | */ 334 | 335 | /** 336 | * @} 337 | */ 338 | 339 | #ifdef __cplusplus 340 | } 341 | #endif 342 | 343 | #endif /* STM32G0xx_LL_UTILS_H */ 344 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the BSD-3-Clause license shall apply. 5 | You may obtain a copy of the BSD-3-Clause at: 6 | https://opensource.org/licenses/BSD-3-Clause 7 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/License.md: -------------------------------------------------------------------------------- 1 | Copyright 2018 STMicroelectronics. 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without modification, 5 | are permitted provided that the following conditions are met: 6 | 7 | 1. Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | 2. Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation and/or 12 | other materials provided with the distribution. 13 | 14 | 3. Neither the name of the copyright holder nor the names of its contributors 15 | may be used to endorse or promote products derived from this software without 16 | specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_hal_adc_ex.c 4 | * @author MCD Application Team 5 | * @brief This file provides firmware functions to manage the following 6 | * functionalities of the Analog to Digital Converter (ADC) 7 | * peripheral: 8 | * + Peripheral Control functions 9 | * Other functions (generic functions) are available in file 10 | * "stm32g0xx_hal_adc.c". 11 | * 12 | ****************************************************************************** 13 | * @attention 14 | * 15 | * Copyright (c) 2018 STMicroelectronics. 16 | * All rights reserved. 17 | * 18 | * This software is licensed under terms that can be found in the LICENSE file 19 | * in the root directory of this software component. 20 | * If no LICENSE file comes with this software, it is provided AS-IS. 21 | * 22 | ****************************************************************************** 23 | @verbatim 24 | [..] 25 | (@) Sections "ADC peripheral features" and "How to use this driver" are 26 | available in file of generic functions "stm32g0xx_hal_adc.c". 27 | [..] 28 | @endverbatim 29 | */ 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32g0xx_hal.h" 33 | 34 | /** @addtogroup STM32G0xx_HAL_Driver 35 | * @{ 36 | */ 37 | 38 | /** @defgroup ADCEx ADCEx 39 | * @brief ADC Extended HAL module driver 40 | * @{ 41 | */ 42 | 43 | #ifdef HAL_ADC_MODULE_ENABLED 44 | 45 | /* Private typedef -----------------------------------------------------------*/ 46 | /* Private define ------------------------------------------------------------*/ 47 | 48 | /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants 49 | * @{ 50 | */ 51 | 52 | /* Fixed timeout value for ADC calibration. */ 53 | /* Values defined to be higher than worst cases: maximum ratio between ADC */ 54 | /* and CPU clock frequencies. */ 55 | /* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ 56 | /* source PLL 8MHz, ADC clock prescaler 256), CPU frequency 52MHz. */ 57 | /* Calibration time max = 116 / fADC (refer to datasheet) */ 58 | /* = 193 024 CPU cycles */ 59 | #define ADC_CALIBRATION_TIMEOUT (193024UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ 60 | #define ADC_DISABLE_TIMEOUT (2UL) 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /* Private macro -------------------------------------------------------------*/ 67 | /* Private variables ---------------------------------------------------------*/ 68 | /* Private function prototypes -----------------------------------------------*/ 69 | /* Exported functions --------------------------------------------------------*/ 70 | 71 | /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions 72 | * @{ 73 | */ 74 | 75 | /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions 76 | * @brief Extended IO operation functions 77 | * 78 | @verbatim 79 | =============================================================================== 80 | ##### IO operation functions ##### 81 | =============================================================================== 82 | [..] This section provides functions allowing to: 83 | 84 | (+) Perform the ADC self-calibration. 85 | (+) Get calibration factors. 86 | (+) Set calibration factors. 87 | 88 | @endverbatim 89 | * @{ 90 | */ 91 | 92 | /** 93 | * @brief Perform an ADC automatic self-calibration 94 | * Calibration prerequisite: ADC must be disabled (execute this 95 | * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). 96 | * @note Calibration factor can be read after calibration, using function 97 | * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). 98 | * @param hadc ADC handle 99 | * @retval HAL status 100 | */ 101 | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) 102 | { 103 | HAL_StatusTypeDef tmp_hal_status; 104 | __IO uint32_t wait_loop_index = 0UL; 105 | uint32_t backup_setting_cfgr1; 106 | uint32_t calibration_index; 107 | uint32_t calibration_factor_accumulated = 0; 108 | uint32_t tickstart; 109 | 110 | /* Check the parameters */ 111 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 112 | 113 | __HAL_LOCK(hadc); 114 | 115 | /* Calibration prerequisite: ADC must be disabled. */ 116 | 117 | /* Disable the ADC (if not already disabled) */ 118 | tmp_hal_status = ADC_Disable(hadc); 119 | 120 | /* Check if ADC is effectively disabled */ 121 | if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 122 | { 123 | /* Set ADC state */ 124 | ADC_STATE_CLR_SET(hadc->State, 125 | HAL_ADC_STATE_REG_BUSY, 126 | HAL_ADC_STATE_BUSY_INTERNAL); 127 | 128 | /* Manage settings impacting calibration */ 129 | /* - Disable ADC mode auto power-off */ 130 | /* - Disable ADC DMA transfer request during calibration */ 131 | /* Note: Specificity of this STM32 series: Calibration factor is */ 132 | /* available in data register and also transferred by DMA. */ 133 | /* To not insert ADC calibration factor among ADC conversion data */ 134 | /* in array variable, DMA transfer must be disabled during */ 135 | /* calibration. */ 136 | backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); 137 | CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); 138 | 139 | /* ADC calibration procedure */ 140 | /* Note: Perform an averaging of 8 calibrations for optimized accuracy */ 141 | for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++) 142 | { 143 | /* Start ADC calibration */ 144 | LL_ADC_StartCalibration(hadc->Instance); 145 | 146 | /* Wait for calibration completion */ 147 | while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 148 | { 149 | wait_loop_index++; 150 | if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 151 | { 152 | /* Update ADC state machine to error */ 153 | ADC_STATE_CLR_SET(hadc->State, 154 | HAL_ADC_STATE_BUSY_INTERNAL, 155 | HAL_ADC_STATE_ERROR_INTERNAL); 156 | 157 | __HAL_UNLOCK(hadc); 158 | 159 | return HAL_ERROR; 160 | } 161 | } 162 | 163 | calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance); 164 | } 165 | /* Compute average */ 166 | calibration_factor_accumulated /= calibration_index; 167 | /* Apply calibration factor */ 168 | LL_ADC_Enable(hadc->Instance); 169 | LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated); 170 | LL_ADC_Disable(hadc->Instance); 171 | 172 | /* Wait for ADC effectively disabled before changing configuration */ 173 | /* Get tick count */ 174 | tickstart = HAL_GetTick(); 175 | 176 | while (LL_ADC_IsEnabled(hadc->Instance) != 0UL) 177 | { 178 | if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 179 | { 180 | /* New check to avoid false timeout detection in case of preemption */ 181 | if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) 182 | { 183 | /* Update ADC state machine to error */ 184 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 185 | 186 | /* Set ADC error code to ADC peripheral internal error */ 187 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 188 | 189 | return HAL_ERROR; 190 | } 191 | } 192 | } 193 | 194 | /* Restore configuration after calibration */ 195 | SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); 196 | 197 | /* Set ADC state */ 198 | ADC_STATE_CLR_SET(hadc->State, 199 | HAL_ADC_STATE_BUSY_INTERNAL, 200 | HAL_ADC_STATE_READY); 201 | } 202 | else 203 | { 204 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 205 | 206 | /* Note: No need to update variable "tmp_hal_status" here: already set */ 207 | /* to state "HAL_ERROR" by function disabling the ADC. */ 208 | } 209 | 210 | __HAL_UNLOCK(hadc); 211 | 212 | return tmp_hal_status; 213 | } 214 | 215 | /** 216 | * @brief Get the calibration factor. 217 | * @param hadc ADC handle. 218 | * @retval Calibration value. 219 | */ 220 | uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc) 221 | { 222 | /* Check the parameters */ 223 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 224 | 225 | /* Return the selected ADC calibration value */ 226 | return ((hadc->Instance->CALFACT) & 0x0000007FU); 227 | } 228 | 229 | /** 230 | * @brief Set the calibration factor to overwrite automatic conversion result. 231 | * ADC must be enabled and no conversion is ongoing. 232 | * @param hadc ADC handle 233 | * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) 234 | * @retval HAL state 235 | */ 236 | HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor) 237 | { 238 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; 239 | uint32_t tmp_adc_is_conversion_on_going_regular; 240 | 241 | /* Check the parameters */ 242 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 243 | assert_param(IS_ADC_CALFACT(CalibrationFactor)); 244 | 245 | __HAL_LOCK(hadc); 246 | 247 | /* Verification of hardware constraints before modifying the calibration */ 248 | /* factors register: ADC must be enabled, no conversion on going. */ 249 | tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 250 | 251 | if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 252 | && (tmp_adc_is_conversion_on_going_regular == 0UL) 253 | ) 254 | { 255 | hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; 256 | hadc->Instance->CALFACT |= CalibrationFactor; 257 | } 258 | else 259 | { 260 | /* Update ADC state machine */ 261 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 262 | /* Update ADC error code */ 263 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 264 | 265 | /* Update ADC state machine to error */ 266 | tmp_hal_status = HAL_ERROR; 267 | } 268 | 269 | __HAL_UNLOCK(hadc); 270 | 271 | return tmp_hal_status; 272 | } 273 | 274 | /** 275 | * @brief Analog watchdog 2 callback in non-blocking mode. 276 | * @param hadc ADC handle 277 | * @retval None 278 | */ 279 | __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) 280 | { 281 | /* Prevent unused argument(s) compilation warning */ 282 | UNUSED(hadc); 283 | 284 | /* NOTE : This function should not be modified. When the callback is needed, 285 | function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. 286 | */ 287 | } 288 | 289 | /** 290 | * @brief Analog watchdog 3 callback in non-blocking mode. 291 | * @param hadc ADC handle 292 | * @retval None 293 | */ 294 | __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) 295 | { 296 | /* Prevent unused argument(s) compilation warning */ 297 | UNUSED(hadc); 298 | 299 | /* NOTE : This function should not be modified. When the callback is needed, 300 | function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. 301 | */ 302 | } 303 | 304 | 305 | /** 306 | * @brief End Of Sampling callback in non-blocking mode. 307 | * @param hadc ADC handle 308 | * @retval None 309 | */ 310 | __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) 311 | { 312 | /* Prevent unused argument(s) compilation warning */ 313 | UNUSED(hadc); 314 | 315 | /* NOTE : This function should not be modified. When the callback is needed, 316 | function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. 317 | */ 318 | } 319 | 320 | /** 321 | * @brief ADC channel configuration ready callback in non-blocking mode. 322 | * @param hadc ADC handle 323 | * @retval None 324 | */ 325 | __weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc) 326 | { 327 | /* Prevent unused argument(s) compilation warning */ 328 | UNUSED(hadc); 329 | 330 | /* NOTE : This function should not be modified. When the callback is needed, 331 | function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file. 332 | */ 333 | } 334 | 335 | /** 336 | * @} 337 | */ 338 | 339 | /** 340 | * @brief Disable ADC voltage regulator. 341 | * @note Disabling voltage regulator allows to save power. This operation can 342 | * be carried out only when ADC is disabled. 343 | * @note To enable again the voltage regulator, the user is expected to 344 | * resort to HAL_ADC_Init() API. 345 | * @param hadc ADC handle 346 | * @retval HAL status 347 | */ 348 | HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) 349 | { 350 | HAL_StatusTypeDef tmp_hal_status; 351 | 352 | /* Check the parameters */ 353 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 354 | 355 | /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ 356 | if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 357 | { 358 | LL_ADC_DisableInternalRegulator(hadc->Instance); 359 | tmp_hal_status = HAL_OK; 360 | } 361 | else 362 | { 363 | tmp_hal_status = HAL_ERROR; 364 | } 365 | 366 | return tmp_hal_status; 367 | } 368 | 369 | /** 370 | * @} 371 | */ 372 | 373 | /** 374 | * @} 375 | */ 376 | 377 | #endif /* HAL_ADC_MODULE_ENABLED */ 378 | /** 379 | * @} 380 | */ 381 | 382 | /** 383 | * @} 384 | */ 385 | -------------------------------------------------------------------------------- /Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32g0xx_hal_dma_ex.c 4 | * @author MCD Application Team 5 | * @brief DMA Extension HAL module driver 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the DMA Extension peripheral: 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### How to use this driver ##### 13 | ============================================================================== 14 | [..] 15 | The DMA Extension HAL driver can be used as follows: 16 | (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. 17 | (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. 18 | Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used 19 | to respectively enable/disable the request generator. 20 | 21 | (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from 22 | the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. 23 | As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be 24 | called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project 25 | (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) 26 | 27 | @endverbatim 28 | ****************************************************************************** 29 | * @attention 30 | * 31 | * Copyright (c) 2018 STMicroelectronics. 32 | * All rights reserved. 33 | * 34 | * This software is licensed under terms that can be found in the LICENSE file 35 | * in the root directory of this software component. 36 | * If no LICENSE file comes with this software, it is provided AS-IS. 37 | * 38 | ****************************************************************************** 39 | */ 40 | 41 | /* Includes ------------------------------------------------------------------*/ 42 | #include "stm32g0xx_hal.h" 43 | 44 | /** @addtogroup STM32G0xx_HAL_Driver 45 | * @{ 46 | */ 47 | 48 | /** @defgroup DMAEx DMAEx 49 | * @brief DMA Extended HAL module driver 50 | * @{ 51 | */ 52 | 53 | #ifdef HAL_DMA_MODULE_ENABLED 54 | 55 | /* Private typedef -----------------------------------------------------------*/ 56 | /* Private define ------------------------------------------------------------*/ 57 | /* Private macro -------------------------------------------------------------*/ 58 | /* Private variables ---------------------------------------------------------*/ 59 | /* Private Constants ---------------------------------------------------------*/ 60 | /* Private function prototypes -----------------------------------------------*/ 61 | /* Exported functions --------------------------------------------------------*/ 62 | 63 | 64 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 65 | * @{ 66 | */ 67 | 68 | /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions 69 | * @brief Extended features functions 70 | * 71 | @verbatim 72 | =============================================================================== 73 | ##### Extended features functions ##### 74 | =============================================================================== 75 | [..] This section provides functions allowing to: 76 | 77 | (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. 78 | (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. 79 | Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used 80 | to respectively enable/disable the request generator. 81 | (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from 82 | the DMAMUX IRQ handler 83 | 84 | @endverbatim 85 | * @{ 86 | */ 87 | 88 | /** 89 | * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). 90 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains 91 | * the configuration information for the specified DMA channel. 92 | * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters 93 | * @retval HAL status 94 | */ 95 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) 96 | { 97 | /* Check the parameters */ 98 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 99 | 100 | assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); 101 | 102 | assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); 103 | assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); 104 | assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); 105 | assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); 106 | 107 | /*Check if the DMA state is ready */ 108 | if (hdma->State == HAL_DMA_STATE_READY) 109 | { 110 | /* Process Locked */ 111 | __HAL_LOCK(hdma); 112 | 113 | /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ 114 | MODIFY_REG(hdma->DMAmuxChannel->CCR, \ 115 | (~DMAMUX_CxCR_DMAREQ_ID), \ 116 | (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ 117 | pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ 118 | ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos))); 119 | 120 | /* Process UnLocked */ 121 | __HAL_UNLOCK(hdma); 122 | 123 | return HAL_OK; 124 | } 125 | else 126 | { 127 | /* Set the error code to busy */ 128 | hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 129 | 130 | /* Return error status */ 131 | return HAL_ERROR; 132 | } 133 | } 134 | 135 | /** 136 | * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). 137 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains 138 | * the configuration information for the specified DMA channel. 139 | * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef 140 | * contains the request generator parameters. 141 | * 142 | * @retval HAL status 143 | */ 144 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, 145 | HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) 146 | { 147 | HAL_StatusTypeDef status; 148 | HAL_DMA_StateTypeDef temp_state = hdma->State; 149 | 150 | /* Check the parameters */ 151 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 152 | 153 | assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); 154 | 155 | assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); 156 | assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); 157 | 158 | /* check if the DMA state is ready 159 | and DMA is using a DMAMUX request generator block 160 | */ 161 | if (hdma->DMAmuxRequestGen == 0U) 162 | { 163 | /* Set the error code to busy */ 164 | hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 165 | 166 | /* error status */ 167 | status = HAL_ERROR; 168 | } 169 | else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) 170 | { 171 | /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ 172 | 173 | /* Process Locked */ 174 | __HAL_LOCK(hdma); 175 | 176 | /* Set the request generator new parameters*/ 177 | hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ 178 | ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \ 179 | pRequestGeneratorConfig->Polarity; 180 | /* Process UnLocked */ 181 | __HAL_UNLOCK(hdma); 182 | 183 | return HAL_OK; 184 | } 185 | else 186 | { 187 | /* Set the error code to busy */ 188 | hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 189 | 190 | /* error status */ 191 | status = HAL_ERROR; 192 | } 193 | 194 | return status; 195 | } 196 | 197 | /** 198 | * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). 199 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains 200 | * the configuration information for the specified DMA channel. 201 | * @retval HAL status 202 | */ 203 | HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) 204 | { 205 | /* Check the parameters */ 206 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 207 | 208 | /* check if the DMA state is ready 209 | and DMA is using a DMAMUX request generator block 210 | */ 211 | if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) 212 | { 213 | 214 | /* Enable the request generator*/ 215 | hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; 216 | 217 | return HAL_OK; 218 | } 219 | else 220 | { 221 | return HAL_ERROR; 222 | } 223 | } 224 | 225 | /** 226 | * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). 227 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains 228 | * the configuration information for the specified DMA channel. 229 | * @retval HAL status 230 | */ 231 | HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) 232 | { 233 | /* Check the parameters */ 234 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 235 | 236 | /* check if the DMA state is ready 237 | and DMA is using a DMAMUX request generator block 238 | */ 239 | if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) 240 | { 241 | 242 | /* Disable the request generator*/ 243 | hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; 244 | 245 | return HAL_OK; 246 | } 247 | else 248 | { 249 | return HAL_ERROR; 250 | } 251 | } 252 | 253 | /** 254 | * @brief Handles DMAMUX interrupt request. 255 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains 256 | * the configuration information for the specified DMA channel. 257 | * @retval None 258 | */ 259 | void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) 260 | { 261 | /* Check for DMAMUX Synchronization overrun */ 262 | if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) 263 | { 264 | /* Disable the synchro overrun interrupt */ 265 | hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 266 | 267 | /* Clear the DMAMUX synchro overrun flag */ 268 | hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 269 | 270 | /* Update error code */ 271 | hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; 272 | 273 | if (hdma->XferErrorCallback != NULL) 274 | { 275 | /* Transfer error callback */ 276 | hdma->XferErrorCallback(hdma); 277 | } 278 | } 279 | 280 | if (hdma->DMAmuxRequestGen != 0) 281 | { 282 | /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ 283 | if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) 284 | { 285 | /* Disable the request gen overrun interrupt */ 286 | hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 287 | 288 | /* Clear the DMAMUX request generator overrun flag */ 289 | hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 290 | 291 | /* Update error code */ 292 | hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; 293 | 294 | if (hdma->XferErrorCallback != NULL) 295 | { 296 | /* Transfer error callback */ 297 | hdma->XferErrorCallback(hdma); 298 | } 299 | } 300 | } 301 | } 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | /** 308 | * @} 309 | */ 310 | 311 | #endif /* HAL_DMA_MODULE_ENABLED */ 312 | /** 313 | * @} 314 | */ 315 | 316 | /** 317 | * @} 318 | */ 319 | 320 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 321 | -------------------------------------------------------------------------------- /KiCad/readm.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /PCB/ESC_G0_DevBoard_V2_r11.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/guser210/ESC-V2/2714366c6d817941ac3a8858353c1091c0777fb4/PCB/ESC_G0_DevBoard_V2_r11.zip -------------------------------------------------------------------------------- /PCB/Readme.md: -------------------------------------------------------------------------------- 1 | ![image](https://github.com/guser210/ESC-V2/assets/6046585/f2d13bc7-ea0e-4698-a414-b6b61e365564) 2 | ![image](https://github.com/guser210/ESC-V2/assets/6046585/07bbde7b-0d15-4360-87f5-5e271a495740) 3 | 4 | 5 | 6 | ![image](https://github.com/guser210/ESC-V2/assets/6046585/3b2fff03-5497-4f16-937a-3407c8b7b893) 7 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ESC-V2 2 | Full STM32CubeEDI project of the ESC I currently use on my Drones. 3 | 4 | You can find more information on the link below, 5 | 6 | 7 | https://discord.gg/pByahDupYP 8 | 9 | ![image](https://cdn.discordapp.com/attachments/1066083280308404344/1140803933107929151/93A70E43-7BA1-49BC-A37B-BBA931728A13.jpg) 10 | ![image](https://cdn.discordapp.com/attachments/1066083280308404344/1140532718191525938/BA7B2CEE-2301-44EB-997F-8B13DB4D5C3C.jpg) 11 | ![image](https://github.com/guser210/ESC-V2/assets/6046585/781d6b8e-5619-4d25-af24-7355e7edcf27) 12 | 13 | ![ESC Front](https://github.com/guser210/ESC-V2/assets/6046585/0a57a7bc-3b0d-4569-b760-84f927f793ba) 14 | ![ESC back](https://github.com/guser210/ESC-V2/assets/6046585/e1468b1b-e189-43b7-9d42-315512028756) 15 | -------------------------------------------------------------------------------- /STM32G070KBTX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** @file : LinkerScript.ld 5 | ** 6 | ** @author : Auto-generated by STM32CubeIDE 7 | ** 8 | ** @brief : Linker script for STM32G070KBTx Device from STM32G0 series 9 | ** 128Kbytes FLASH 10 | ** 36Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed as is, without any warranty 20 | ** of any kind. 21 | ** 22 | ****************************************************************************** 23 | ** @attention 24 | ** 25 | ** Copyright (c) 2022 STMicroelectronics. 26 | ** All rights reserved. 27 | ** 28 | ** This software is licensed under terms that can be found in the LICENSE file 29 | ** in the root directory of this software component. 30 | ** If no LICENSE file comes with this software, it is provided AS-IS. 31 | ** 32 | ****************************************************************************** 33 | */ 34 | 35 | /* Entry Point */ 36 | ENTRY(Reset_Handler) 37 | 38 | /* Highest address of the user mode stack */ 39 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ 40 | 41 | _Min_Heap_Size = 0x200; /* required amount of heap */ 42 | _Min_Stack_Size = 0x400; /* required amount of stack */ 43 | 44 | /* Memories definition */ 45 | MEMORY 46 | { 47 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 36K 48 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K 49 | } 50 | 51 | /* Sections */ 52 | SECTIONS 53 | { 54 | /* The startup code into "FLASH" Rom type memory */ 55 | .isr_vector : 56 | { 57 | . = ALIGN(4); 58 | KEEP(*(.isr_vector)) /* Startup code */ 59 | . = ALIGN(4); 60 | } >FLASH 61 | 62 | /* The program code and other data into "FLASH" Rom type memory */ 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | *(.text) /* .text sections (code) */ 67 | *(.text*) /* .text* sections (code) */ 68 | *(.glue_7) /* glue arm to thumb code */ 69 | *(.glue_7t) /* glue thumb to arm code */ 70 | *(.eh_frame) 71 | 72 | KEEP (*(.init)) 73 | KEEP (*(.fini)) 74 | 75 | . = ALIGN(4); 76 | _etext = .; /* define a global symbols at end of code */ 77 | } >FLASH 78 | 79 | /* Constant data into "FLASH" Rom type memory */ 80 | .rodata : 81 | { 82 | . = ALIGN(4); 83 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 84 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 85 | . = ALIGN(4); 86 | } >FLASH 87 | 88 | .ARM.extab : { 89 | . = ALIGN(4); 90 | *(.ARM.extab* .gnu.linkonce.armextab.*) 91 | . = ALIGN(4); 92 | } >FLASH 93 | 94 | .ARM : { 95 | . = ALIGN(4); 96 | __exidx_start = .; 97 | *(.ARM.exidx*) 98 | __exidx_end = .; 99 | . = ALIGN(4); 100 | } >FLASH 101 | 102 | .preinit_array : 103 | { 104 | . = ALIGN(4); 105 | PROVIDE_HIDDEN (__preinit_array_start = .); 106 | KEEP (*(.preinit_array*)) 107 | PROVIDE_HIDDEN (__preinit_array_end = .); 108 | . = ALIGN(4); 109 | } >FLASH 110 | 111 | .init_array : 112 | { 113 | . = ALIGN(4); 114 | PROVIDE_HIDDEN (__init_array_start = .); 115 | KEEP (*(SORT(.init_array.*))) 116 | KEEP (*(.init_array*)) 117 | PROVIDE_HIDDEN (__init_array_end = .); 118 | . = ALIGN(4); 119 | } >FLASH 120 | 121 | .fini_array : 122 | { 123 | . = ALIGN(4); 124 | PROVIDE_HIDDEN (__fini_array_start = .); 125 | KEEP (*(SORT(.fini_array.*))) 126 | KEEP (*(.fini_array*)) 127 | PROVIDE_HIDDEN (__fini_array_end = .); 128 | . = ALIGN(4); 129 | } >FLASH 130 | 131 | /* Used by the startup to initialize data */ 132 | _sidata = LOADADDR(.data); 133 | 134 | /* Initialized data sections into "RAM" Ram type memory */ 135 | .data : 136 | { 137 | . = ALIGN(4); 138 | _sdata = .; /* create a global symbol at data start */ 139 | *(.data) /* .data sections */ 140 | *(.data*) /* .data* sections */ 141 | *(.RamFunc) /* .RamFunc sections */ 142 | *(.RamFunc*) /* .RamFunc* sections */ 143 | 144 | . = ALIGN(4); 145 | _edata = .; /* define a global symbol at data end */ 146 | 147 | } >RAM AT> FLASH 148 | 149 | /* Uninitialized data section into "RAM" Ram type memory */ 150 | . = ALIGN(4); 151 | .bss : 152 | { 153 | /* This is used by the startup in order to initialize the .bss section */ 154 | _sbss = .; /* define a global symbol at bss start */ 155 | __bss_start__ = _sbss; 156 | *(.bss) 157 | *(.bss*) 158 | *(COMMON) 159 | 160 | . = ALIGN(4); 161 | _ebss = .; /* define a global symbol at bss end */ 162 | __bss_end__ = _ebss; 163 | } >RAM 164 | 165 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ 166 | ._user_heap_stack : 167 | { 168 | . = ALIGN(8); 169 | PROVIDE ( end = . ); 170 | PROVIDE ( _end = . ); 171 | . = . + _Min_Heap_Size; 172 | . = . + _Min_Stack_Size; 173 | . = ALIGN(8); 174 | } >RAM 175 | 176 | /* Remove information from the compiler libraries */ 177 | /DISCARD/ : 178 | { 179 | libc.a ( * ) 180 | libm.a ( * ) 181 | libgcc.a ( * ) 182 | } 183 | 184 | .ARM.attributes 0 : { *(.ARM.attributes) } 185 | } 186 | -------------------------------------------------------------------------------- /images/ESC Front.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/guser210/ESC-V2/2714366c6d817941ac3a8858353c1091c0777fb4/images/ESC Front.jpg -------------------------------------------------------------------------------- /images/ESC back.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/guser210/ESC-V2/2714366c6d817941ac3a8858353c1091c0777fb4/images/ESC back.jpg -------------------------------------------------------------------------------- /images/misc.txt: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /test.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/guser210/ESC-V2/2714366c6d817941ac3a8858353c1091c0777fb4/test.txt --------------------------------------------------------------------------------