├── .env.template ├── .github └── workflows │ ├── clear-cache.yml │ ├── prune_ghcr.yml │ ├── release.yml │ └── run-checks-github-runners.yml ├── .gitignore ├── .gitmodules ├── Dockerfile ├── LICENSE ├── README.md ├── architecture_descriptions ├── intel.yml ├── intel_cyclone10lp.yml ├── lattice_ecp5.yml ├── sofa.yml ├── xilinx_7_series.yml └── xilinx_ultrascale_plus.yml ├── bin ├── README.md ├── btor_to_racket.rkt ├── convert_params_to_inputs.py ├── lakeroad-portfolio.py ├── main.rkt ├── simulate_with_verilator.py └── verilog_to_racket.py ├── dependencies.sh ├── fmt.sh ├── import_all_primitives.sh ├── integration_tests ├── README.md ├── lakeroad │ ├── addmulor_3_stage_unsigneds_9_bit.v │ ├── assume │ │ ├── assume_example.sv │ │ └── assume_failing_example.sv │ ├── bsg_mul_add_unsigned │ │ ├── bsg_defines.sv │ │ ├── bsg_dff.sv │ │ ├── bsg_dff_chain.sv │ │ └── bsg_mul_add_unsigned_13bit.sv │ ├── combinational_multiplier_lattice.v │ ├── combinational_multiplier_xilinx.v │ ├── example_test_using_include.v │ ├── example_test_using_include │ │ └── impl.v │ ├── intel_cyclone10lp_mul_0_stage_unsigned_18_bit.v │ ├── intel_cyclone10lp_mul_1_stage_unsigned_18_bit.v │ ├── intel_cyclone10lp_mul_2_stage_unsigned_18_bit.v │ ├── lattice_mult_2_stage_signed_8_bit.sv │ ├── lit.cfg │ ├── mul16_yosys_techmap.txt │ ├── one_stage_add_mul_add_signed_11_bit_xilinx.sv │ ├── one_stage_add_mul_add_signed_12_bit_xilinx.sv │ ├── one_stage_add_mul_add_signed_18_bit_xilinx.sv │ ├── one_stage_mul_or_lattice.v │ ├── one_stage_multiplier_lattice.v │ ├── pipeline_depth_0_with_clk_test.v │ ├── three_stage_mul_and_lattice.v │ ├── three_stage_multiplier_lattice.v │ ├── three_stage_multiplier_xilinx.v │ ├── two_stage_mul_and_lattice.v │ ├── two_stage_multiplier_xilinx.v │ ├── xilinx-7-series │ │ ├── 7_series_addmuladd_1_stage_signed_11_bit.sv │ │ ├── 7_series_addmuladd_1_stage_signed_9_bit.sv │ │ ├── 7_series_addmulsub_1_stage_unsigned_17_bit.sv │ │ ├── 7_series_muladd_1_stage_signed_11_bit.sv │ │ ├── 7_series_muladd_1_stage_unsigned_14_bit.sv │ │ ├── 7_series_muladd_1_stage_unsigned_9_bit.sv │ │ ├── 7_series_mulsub_0_stage_unsigned_9_bit.sv │ │ ├── 7_series_mulsub_1_stage_unsigned_14_bit.sv │ │ ├── 7_series_mulsub_1_stage_unsigned_9_bit.sv │ │ ├── 7_series_mult_0_stage_signed_12_bit.sv │ │ ├── 7_series_mult_0_stage_unsigned_8_bit.sv │ │ ├── 7_series_mult_0_stage_unsigned_9_bit.sv │ │ ├── 7_series_mult_1_stage_signed_9_bit.sv │ │ ├── 7_series_mult_2_stage_unsigned_11_bit.sv │ │ ├── 7_series_submulsub_1_stage_signed_18_bit.sv │ │ └── 7_series_submulsub_2_stage_unsigned_18_bit.sv │ ├── xilinx_add_mul_and_3_stage_unsigned_9_bit.sv │ ├── xilinx_addmuladd_2_stage_unsigned_18_bit.sv │ ├── xilinx_addmuland_1_stage_signed_18_bit.sv │ ├── xilinx_addmulsub_3_stage_unsigned_18_bit.sv │ ├── xilinx_muladd_0_stage_signed_8_bit.sv │ ├── xilinx_muladd_0_stage_signed_8_bit_yosys_plugin.sv │ ├── xilinx_muladd_0_stage_unsigned_13_bit.sv │ ├── xilinx_muladd_3_stage_signed_18_bit.sv │ ├── xilinx_mulsub_1_stage_unsigned_14_bit.sv │ ├── xilinx_mulsub_3_stage_signed_18_bit.sv │ ├── xilinx_mulsub_3_stage_signed_8_bit.sv │ ├── xilinx_mult_1_stage_signed_11_bit.sv │ ├── xilinx_mult_1_stage_signed_12_bit.sv │ ├── xilinx_mult_1_stage_signed_9_bit.sv │ ├── xilinx_mult_1_stage_unsigned_11_bit.sv │ ├── xilinx_mult_2_stage_unsigned_11_bit.sv │ ├── xilinx_preaddmul_1_stage_signed_18_bit.sv │ ├── xilinx_preaddmul_3_stage_signed_18_bit.sv │ ├── xilinx_submuland_3_stage_signed_18_bit.sv │ ├── xilinx_ultrascale_plus_add16_2_instr.txt │ ├── xilinx_ultrascale_plus_dsp_internal_shift.v │ ├── xilinx_ultrascale_plus_dsp_internal_shift_broken.v │ ├── xilinx_ultrascale_plus_dsp_internal_shift_explicit_arithmetic_shift.v │ ├── xilinx_ultrascale_plus_mac_with_internal_shift.v │ ├── xilinx_ultrascale_plus_mul_two_dsp_large.sv │ ├── xilinx_ultrascale_plus_mul_two_dsp_small.sv │ ├── xilinx_ultrascale_plus_wide_add.v │ └── xilinx_ultrascale_plus_wide_add_yosys.v ├── run.sh └── simulate_with_verilator │ ├── lit.cfg │ ├── simple_test.sv │ ├── simple_test_all_zeroes_fail.sv │ ├── simple_test_all_zeroes_ignore.sv │ ├── simple_test_combinational.sv │ ├── simple_test_error.sv │ └── simple_test_multiple_outputs.sv ├── misc ├── verilator.mk.template └── verilator_testbench.sv.template ├── modules_for_importing ├── README.md ├── SOFA │ ├── frac_lut4.v │ └── frac_lut4_mux.v ├── lattice_ecp5 │ ├── CCU2C.v │ ├── LUT2.v │ └── LUT4.v └── xilinx_ultrascale_plus │ ├── CARRY8.v │ ├── DSP48E2.v │ ├── LUT6.v │ └── LUT6_2.v ├── racket ├── architecture-description.rkt ├── btor.rkt ├── circt-comb-operators.rkt ├── comp-json.rkt ├── compile-to-json.rkt ├── generated │ ├── intel-altmult-accum.rkt │ ├── intel-cyclone10lp-mac-mult.rkt │ ├── intel-cyclone10lp-mac-out.rkt │ ├── lattice-ecp5-alu24b.rkt │ ├── lattice-ecp5-alu54a.rkt │ ├── lattice-ecp5-alu54b.rkt │ ├── lattice-ecp5-ccu2c.rkt │ ├── lattice-ecp5-lut2.rkt │ ├── lattice-ecp5-lut4.rkt │ ├── lattice-ecp5-mult18x18c.rkt │ ├── lattice-ecp5-mult18x18d.rkt │ ├── sofa-frac-lut4.rkt │ ├── xilinx-7-series-dsp48e1.rkt │ ├── xilinx-ultrascale-plus-carry8.rkt │ ├── xilinx-ultrascale-plus-dsp48e2.rkt │ ├── xilinx-ultrascale-plus-lut6-2.rkt │ └── xilinx-ultrascale-plus-lut6.rkt ├── interpreter.rkt ├── language.rkt ├── lattice-end-to-end.rkt ├── logical-to-physical.rkt ├── lut.rkt ├── programs-to-synthesize.rkt ├── signal.rkt ├── sketches.rkt ├── sofa-end-to-end.rkt ├── synthesize.rkt ├── test-intel-altmult-accum.rkt ├── test-lattice-ecp5-alu54a.rkt ├── test-lattice-ecp5-alu54b.rkt ├── testbench.cc.template ├── testbench_bw16.cc.template ├── testbench_bw32.cc.template ├── testbench_bw64.cc.template ├── testing.rkt ├── ultrascale-tests-end-to-end.rkt ├── utils.rkt └── xilinx-ultrascale-plus-lut2.rkt ├── release_files ├── README.md ├── examples │ ├── lattice_ecp5_2stage_muland_unsigned_16bit.sh │ ├── verilog │ │ ├── lattice_ecp5_2stage_muland_unsigned_16bit.sv │ │ ├── lattice_ecp5_2stage_muland_unsigned_16bit_yosys_annotations.sv │ │ ├── xilinx_ultrascale_1stage_addmuladd_signed_11bit.sv │ │ └── xilinx_ultrascale_1stage_addmuladd_signed_11bit_yosys_annotations.sv │ └── xilinx_ultrascale_1stage_addmuladd_signed_11bit.sh └── run-examples.sh ├── requirements.txt ├── run-tests.sh ├── spec-sheets ├── README.md ├── ug574-ultrascale-clb.pdf └── ug579-ultrascale-dsp.pdf ├── verilog └── simulation │ ├── lattice-ecp5 │ ├── CCU2C.v │ ├── LUT2.v │ ├── LUT4.v │ └── README.md │ ├── skywater │ ├── README.md │ ├── sky130_fd_sc_hd__buf.behavioral.v │ ├── sky130_fd_sc_hd__buf.functional.v │ ├── sky130_fd_sc_hd__buf.v │ ├── sky130_fd_sc_hd__buf_2.v │ ├── sky130_fd_sc_hd__inv.behavioral.v │ ├── sky130_fd_sc_hd__inv.functional.v │ ├── sky130_fd_sc_hd__inv.v │ ├── sky130_fd_sc_hd__inv_1.v │ ├── sky130_fd_sc_hd__mux2.behavioral.v │ ├── sky130_fd_sc_hd__mux2.functional.v │ ├── sky130_fd_sc_hd__mux2.v │ ├── sky130_fd_sc_hd__mux2_1.v │ ├── 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