├── sv_icon.png ├── images ├── vs_code_snippets.gif ├── sv_screenshot_monokai_pro.png └── sv_screenshot_vs_code_dark.png ├── .gitignore ├── sv-1800-2012.code-workspace ├── crash_course ├── sv-1800-2012-cc-15-interprocess-communication.svh ├── sv-1800-2012-cc-35-dpi.svh ├── sv-1800-2012-cc-33-configs.svh ├── sv-1800-2012-cc-26-packages.svh ├── sv-1800-2012-cc-10-assignments.svh ├── sv-1800-2012-cc-25-interfaces.svh ├── sv-1800-2012-cc-23-modules.svh ├── sv-1800-2012-cc-11-operators.svh ├── sv-1800-2012-cc-12-procedural-programming.svh ├── sv-1800-2012-cc-13-task-and-functions.svh ├── sv-1800-2012-cc-14-clocking-blocks.svh ├── sv-1800-2012-cc-18-constraints-and-randomization.svh ├── sv-1800-2012-cc-09-processes.svh ├── sv-1800-2012-cc-01.svh ├── sv-1800-2012-cc-19-functional-coverage.svh ├── sv-1800-2012-cc-06-types.svh ├── sv-1800-2012-cc-02.svh ├── sv-1800-2012-cc-16-assertions.svh └── sv-1800-2012-cc-08-classes.svh ├── LICENSE.md ├── package.json ├── language-configuration.json ├── README.md ├── snippets ├── sv_language_constructs.json ├── uvm_macros.json ├── sv_containers.json ├── uvm_phases.json └── uvm_containers.json └── CHANGELOG.md /sv_icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gvekony/sv-1800-2012/HEAD/sv_icon.png -------------------------------------------------------------------------------- /images/vs_code_snippets.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gvekony/sv-1800-2012/HEAD/images/vs_code_snippets.gif -------------------------------------------------------------------------------- /images/sv_screenshot_monokai_pro.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gvekony/sv-1800-2012/HEAD/images/sv_screenshot_monokai_pro.png -------------------------------------------------------------------------------- /images/sv_screenshot_vs_code_dark.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/gvekony/sv-1800-2012/HEAD/images/sv_screenshot_vs_code_dark.png -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # output is generated 2 | # output folder could hold persistent files but that requires 3 | # force add 4 | /output/* 5 | 6 | # vscode generated files 7 | /.vscode/* 8 | *.code-workspace 9 | 10 | # macos generated files 11 | .DS_Store 12 | -------------------------------------------------------------------------------- /sv-1800-2012.code-workspace: -------------------------------------------------------------------------------- 1 | { 2 | "folders": [ 3 | { 4 | "path": "." 5 | } 6 | ], 7 | "settings": { 8 | "editor.insertSpaces": true, 9 | "editor.quickSuggestions": { 10 | "other": true, 11 | "comments": false, 12 | "strings": true 13 | }, 14 | "editor.tabSize": 4, 15 | "files.trimTrailingWhitespace": true, 16 | "files.insertFinalNewline": true 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-15-interprocess-communication.svh: -------------------------------------------------------------------------------- 1 | typedef mailbox #(string) s_mbox; 2 | 3 | 4 | s_mbox sm = new; 5 | string s; 6 | sm.put( "hello" ); 7 | ... 8 | sm.get( s ); // s <- "hello" 9 | 10 | -> ->> wait 11 | 12 | event done, blast; // declare two new events 13 | event done_too = done; // declare done_too as alias to done 14 | task trigger( event ev ); 15 | -> ev; 16 | endtask 17 | 18 | fork 19 | @ done_too; // wait for done through done_too 20 | #1 trigger( done ); // trigger done through task trigger 21 | join 22 | 23 | fork 24 | -> blast; 25 | wait ( blast.triggered ); 26 | join 27 | 28 | wait_order 29 | 30 | fork 31 | T1: forever @ E2; 32 | T2: forever @ E1; 33 | T3: begin 34 | E2 = E1; 35 | forever -> E2; 36 | end 37 | join -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2018 Gergo Vekony 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 6 | 7 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 8 | 9 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 10 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-35-dpi.svh: -------------------------------------------------------------------------------- 1 | // Package: DPI_container_pkg 2 | // 3 | package DPI_container_pkg; 4 | import "DPI-C" function void myInit(); 5 | 6 | // from standard math library 7 | import "DPI-C" pure function real sin(real); 8 | 9 | // from standard C library: memory management 10 | import "DPI-C" function chandle malloc(int size); // standard C function 11 | import "DPI-C" function void free(chandle ptr); // standard C function 12 | 13 | // abstract data structure: queue 14 | import "DPI-C" function chandle newQueue(input string name_of_queue); 15 | 16 | // Note: the following import uses the same foreign function for 17 | // implementation as the prior import, but has different SystemVerilog name 18 | // and provides a default value for the argument. 19 | import "DPI-C" newQueue=function chandle newAnonQueue(input string s=null); 20 | import "DPI-C" function chandle newElem(bit [15:0]); 21 | import "DPI-C" function void enqueue(chandle queue, chandle elem); 22 | import "DPI-C" function chandle dequeue(chandle queue); 23 | 24 | // miscellanea 25 | import "DPI-C" function bit [15:0] getStimulus(); 26 | import "DPI-C" context function void processTransaction(chandle elem, 27 | output logic [64:1] arr [0:63]); 28 | 29 | import "DPI-C" task checkResults(input string s, bit [511:0] packet); 30 | 31 | export "DPI-C" f_plus = function \f+ ; // "f+" exported as "f_plus" 32 | export "DPI-C" function f; // "f" exported under its own name 33 | import "DPI-C" init_1 = function void \init[1] (); // "init_1" is a linkage name 34 | import "DPI-C" \begin = function void \init[2] (); // "begin" is a linkage name 35 | 36 | endpackage: DPI_container_pkg 37 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-33-configs.svh: -------------------------------------------------------------------------------- 1 | config cfgl; 2 | design rtlLib.top; 3 | instance top use #(.WIDTH(32)); 4 | instance top.a1 use #(.W(top.WIDTH)); 5 | endconfig 6 | 7 | config cfg2; 8 | localparam S = 24; 9 | design rtlLib.top4; 10 | instance top4.a1 use #(.W(top4.S)); 11 | instance top4.a2 use #(.W(S)); 12 | endconfig 13 | 14 | config cfg3; 15 | design rtlLib.top5; 16 | instance top5.a1 use #(.W()); // set only parameter W back to its default 17 | endconfig 18 | 19 | config cfg4;/*some silly comment*/ 20 | design rtlLib.top; 21 | instance top.a1 use #(); // set all parameters in instance a1 22 | // back to their defaults 23 | endconfig 24 | 25 | module top8 (...); 26 | parameter WIDTH = 32; 27 | adder a1 #(.ID("a1")) (...); 28 | adder a2 #(.ID("a2"),.W(WIDTH))(...); 29 | endmodule 30 | 31 | config cfg6; 32 | design rtlLib.test; 33 | instance test.t use #(.WIDTH(48)); 34 | endconfig 35 | endconfig 36 | 37 | config cfg1; 38 | design rtlLib.top ; 39 | default liblist aLib rtlLib; 40 | endconfig 41 | 42 | config cfg2; 43 | design rtlLib.top ; 44 | default liblist gateLib aLib rtlLib; 45 | endconfig 46 | 47 | config cfg3; 48 | design rtlLib.top ; 49 | default liblist aLib rtlLib; 50 | cell m use gateLib.m ; 51 | endconfig 52 | 53 | config cfg4 54 | design rtlLib.top ; 55 | default liblist gateLib rtlLib; 56 | instance top.a2 liblist aLib; 57 | endconfig 58 | 59 | config cfg5; 60 | design aLib.adder; 61 | default liblist gateLib aLib; 62 | instance adder.f1 liblist rtlLib; 63 | endconfig 64 | 65 | config cfg6; 66 | design rtlLib.top; 67 | default liblist aLib rtlLib; 68 | instance top.a2 use work.cfg5:config ; 69 | endconfig -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-26-packages.svh: -------------------------------------------------------------------------------- 1 | package ComplexPkg; 2 | typedef struct { 3 | shortreal i, r; 4 | } Complex; 5 | 6 | function Complex add(Complex a, b); 7 | add.r = a.r + b.r; 8 | add.i = a.i + b.i; 9 | endfunction 10 | 11 | function Complex mul(Complex a, b); 12 | mul.r = (a.r * b.r) - (a.i * b.i); 13 | mul.i = (a.r * b.i) + (a.i * b.r); 14 | endfunction 15 | endpackage : ComplexPkg 16 | 17 | package p; 18 | typedef enum { FALSE, TRUE } bool_t; 19 | endpackage 20 | 21 | package q; 22 | typedef enum { ORIGINAL, FALSE } teeth_t; 23 | endpackage 24 | 25 | module top1 ; 26 | import p::*; 27 | import q::teeth_t; 28 | export *::*; 29 | 30 | teeth_t myteeth; 31 | 32 | initial begin 33 | myteeth = q:: FALSE; // OK: 34 | myteeth = FALSE; // ERROR: Direct reference to FALSE refers to the 35 | end // FALSE enumeration literal imported from p 36 | endmodule 37 | 38 | package p; 39 | int x; 40 | endpackage 41 | 42 | package p2; 43 | int x; 44 | endpackage 45 | 46 | module top; 47 | import p::*; // line 1 48 | if (1) begin : b 49 | initial x = 1; // line 2 50 | import p2::*; // line 3 51 | end 52 | endmodule 53 | 54 | package A; 55 | typedef struct { 56 | bit [ 7:0] opcode; 57 | bit [23:0] addr; 58 | } instruction_t; 59 | endpackage: A 60 | 61 | package B; 62 | typedef enum bit {FALSE, TRUE} boolean_t; 63 | endpackage: B 64 | 65 | /* known bug */ 66 | module M import A::instruction_t, B::*; 67 | #(WIDTH = 32) 68 | ( 69 | input [WIDTH-1:0] data, 70 | input instruction_t a, 71 | output [WIDTH-1:0] result, 72 | output boolean_t OK 73 | ); 74 | ... 75 | endmodule: M 76 | 77 | package p1; 78 | int x, y; 79 | endpackage 80 | 81 | package p2; 82 | import p1::x; 83 | export p1::*; // exports p1::x as the name "x"; 84 | // p1::x and p2::x are the same declaration 85 | endpackage 86 | 87 | package p3; 88 | import p1::*; 89 | import p2::*; 90 | export p2::*; 91 | endpackage: p3 92 | -------------------------------------------------------------------------------- /package.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "systemverilog-1800-2012", 3 | "displayName": "SystemVerilog-1800-2012", 4 | "description": "Unified hardware design, specification, and verification language + One functional verification methodology for everyone.", 5 | "version": "1.0.27", 6 | "publisher": "gvekony", 7 | "engines": { 8 | "vscode": "^1.12.0" 9 | }, 10 | "license": "MIT", 11 | "author": { 12 | "name": "Gergo Vekony", 13 | "email": "gvekony@gmail.com" 14 | }, 15 | "repository": { 16 | "type": "git", 17 | "url": "https://github.com/gvekony/sv-1800-2012" 18 | }, 19 | "categories": [ 20 | "Formatters", 21 | "Programming Languages", 22 | "Snippets" 23 | ], 24 | "keywords": [ 25 | "Hardware Verification Language", 26 | "HDL", 27 | "Verilog", 28 | "SystemVerilog", 29 | "UVM" 30 | ], 31 | "contributes": { 32 | "languages": [ 33 | { 34 | "id": "systemverilog", 35 | "aliases": [ 36 | "SystemVerilog-1800-2012", 37 | "SV", 38 | "sv" 39 | ], 40 | "extensions": [ 41 | ".sv", 42 | ".sva", 43 | ".svi", 44 | ".svh", 45 | ".v", 46 | ".vh" 47 | ], 48 | "configuration": "./language-configuration.json" 49 | } 50 | ], 51 | "grammars": [ 52 | { 53 | "language": "systemverilog", 54 | "scopeName": "source.systemverilog", 55 | "path": "./syntaxes/systemverilog.tmLanguage.json" 56 | } 57 | ], 58 | "snippets": [ 59 | { 60 | "language": "systemverilog", 61 | "path": "./snippets/sv_containers.json" 62 | }, 63 | { 64 | "language": "systemverilog", 65 | "path": "./snippets/sv_language_constructs.json" 66 | }, 67 | { 68 | "language": "systemverilog", 69 | "path": "./snippets/uvm_containers.json" 70 | }, 71 | { 72 | "language": "systemverilog", 73 | "path": "./snippets/uvm_macros.json" 74 | }, 75 | { 76 | "language": "systemverilog", 77 | "path": "./snippets/uvm_phases.json" 78 | } 79 | ] 80 | }, 81 | "extensionKind": [ 82 | "workspace", 83 | "ui" 84 | ], 85 | "icon": "sv_icon.png", 86 | "__metadata": { 87 | "id": "7b02296d-50c0-4efa-abca-4aa654a94b01", 88 | "publisherDisplayName": "gvekony", 89 | "publisherId": "7b42f5f6-26f4-4cd5-93e2-d0904d85ae74" 90 | } 91 | } 92 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-10-assignments.svh: -------------------------------------------------------------------------------- 1 | wire mynet ; 2 | assign (strong1, pull0) mynet = enable; 3 | 4 | module adder (sum_out, carry_out, carry_in, ina, inb); 5 | output [3:0] sum_out; 6 | output carry_out; 7 | input [3:0] ina, inb; 8 | input carry_in; 9 | 10 | wire carry_out, carry_in; 11 | wire [3:0] sum_out, ina, inb; 12 | 13 | assign {carry_out, sum_out} = ina + inb + carry_in; 14 | endmodule 15 | 16 | module select_bus(busout, bus0, bus1, bus2, bus3, enable, s); 17 | parameter n = 16; 18 | parameter Zee = 16'bz; 19 | 20 | output [1:n] busout; 21 | input [1:n] bus0, bus1, bus2, bus3; 22 | input enable; 23 | input [1:2] s; 24 | 25 | tri [1:n] data; // net declaration 26 | // net declaration with continuous assignment 27 | tri [1:n] busout = enable ? data : Zee; 28 | // assignment statement with four continuous assignments 29 | assign 30 | data = (s == 0) ? bus0 : Zee, 31 | data = (s == 1) ? bus1 : Zee, 32 | data = (s == 2) ? bus2 : Zee, 33 | data = (s == 3) ? bus3 : Zee; 34 | endmodule 35 | 36 | wire #10ns wireA; 37 | 38 | rega = 0; 39 | rega[3] = 1; // a bit-select 40 | rega[3:5] = 7; // a part-select 41 | mema[address] = 8'hff; // assignment to a mem element 42 | {carry, acc} = rega + regb; // a concatenation 43 | 44 | always @(posedge c) begin 45 | a <= b; // evaluates, schedules, 46 | b <= a; // and executes in two steps 47 | end 48 | 49 | module dff (q, d, clear, preset, clock); 50 | output q; 51 | input d, clear, preset, clock; 52 | logic q; 53 | 54 | always @(clear or preset) 55 | if (!clear) 56 | assign q = 0; 57 | else if (!preset) 58 | assign q = 1; 59 | else 60 | deassign q; 61 | 62 | always @(posedge clock) 63 | q = d; 64 | endmodule 65 | 66 | module test; 67 | logic a, b, c, d; 68 | wire e; 69 | and and1 (e, a, b, c); 70 | initial begin 71 | $monitor("%d d=%b,e=%b", $stime, d, e); 72 | assign d = a & b & c; 73 | a = 1; 74 | b = 0; 75 | c = 1; 76 | #10; 77 | force d = (a | b | c); 78 | force e = (a | b | c); 79 | #10; 80 | release d; 81 | release e; 82 | #10 $finish; 83 | end 84 | endmodule 85 | 86 | var int A[N] = '{default:1}; 87 | var integer i = '{31:1, 23:1, 15:1, 8:1, default:0}; 88 | typedef struct {real r, th;} C; 89 | var C x = '{th:PI/2.0, r:1.0}; 90 | var real y [0:1] = '{0.0, 1.1}, z [0:9] = '{default: 3.1416}; 91 | 92 | module mod1; 93 | typedef struct { 94 | int x; 95 | int y; 96 | } st; 97 | 98 | st s1; 99 | int k = 1; 100 | initial begin 101 | #1 s1 = '{1, 2+k}; // by position 102 | #1 $display( s1.x, s1.y); 103 | #1 s1 = '{x:2, y:3+k}; // by name 104 | #1 $display( s1.x, s1.y); 105 | #1 $finish; 106 | end 107 | endmodule 108 | 109 | module byte_rip (inout wire [31:0] W, inout wire [7:0] LSB, MSB); 110 | alias W[7:0] = LSB; 111 | alias W[31:24] = MSB; 112 | endmodule 113 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-25-interfaces.svh: -------------------------------------------------------------------------------- 1 | interface simple_bus; // Define the interface 2 | logic req, gnt; 3 | logic [7:0] addr, data; 4 | logic [1:0] mode; 5 | logic start, rdy; 6 | endinterface: simple_bus 7 | 8 | interface static i2; 9 | wire a, b, c, d; 10 | modport master (input a, b, output c, d); 11 | modport slave (output a, b, input c, d); 12 | endinterface 13 | 14 | interface i2; 15 | wire a, b, c, d; 16 | modport master (input a, b, output c, d); 17 | modport slave (output a, b, input c, d); 18 | endinterface: i2 19 | 20 | interface simple_bus (input logic clk); // Define the interface 21 | logic req, gnt; 22 | logic [7:0] addr, data; 23 | logic [1:0] mode; 24 | logic start, rdy; 25 | 26 | bufif1 b1(); 27 | 28 | modport slave ( 29 | input req, addr, mode, start, clk, 30 | output gnt, rdy, 31 | ref data 32 | ); 33 | 34 | modport master ( 35 | input gnt, rdy, clk, 36 | output req, addr, mode, start, 37 | ref data 38 | ); 39 | 40 | endinterface: simple_bus 41 | 42 | interface A_Bus( input logic clk ); 43 | wire req, gnt; 44 | wire [7:0] addr, data; 45 | clocking sb @(posedge clk); 46 | input gnt; 47 | output req, addr; 48 | inout data; 49 | 50 | property p1; 51 | req ##[1:3] gnt; 52 | endproperty 53 | endclocking 54 | 55 | modport DUT ( 56 | input clk, req, addr, // Device under test modport 57 | output gnt, 58 | inout data 59 | ); 60 | 61 | modport STB ( 62 | clocking sb 63 | ); // synchronous testbench modport 64 | 65 | modport TB ( 66 | input gnt, // asynchronous testbench modport 67 | output req, addr, 68 | inout data 69 | ); 70 | 71 | endinterface 72 | 73 | interface static simple_bus (input logic clk); // Define the interface 74 | logic req, gnt; 75 | logic [7:0] addr, data; 76 | logic [1:0] mode; 77 | logic start, rdy; 78 | 79 | task masterRead(input logic [7:0] raddr); // masterRead method 80 | ... 81 | endtask: masterRead 82 | 83 | task slaveRead; // slaveRead method 84 | ... 85 | endtask: slaveRead 86 | 87 | endinterface: simple_bus 88 | 89 | interface simple_bus (input logic clk); // Define the interface 90 | modport slave (input req, addr, mode, start, clk, 91 | output gnt, rdy, 92 | ref data, 93 | import slaveRead, slaveWrite, 94 | export slaveWrite, slaveRead 95 | ); 96 | endinterface: simple_bus 97 | 98 | interface ebus_i; 99 | integer I; // reference to I not allowed through modport mp 100 | typedef enum {Y,N} choice; 101 | choice Q; 102 | 103 | localparam True = 1; 104 | 105 | modport mp(input Q); 106 | endinterface 107 | 108 | module Top; 109 | ebus_i ebus (); 110 | sub s1 (ebus.mp); 111 | endmodule 112 | 113 | module sub(interface.mp i); 114 | typedef i.choice yes_no; // import type from interface 115 | yes_no P; 116 | assign P = i.Q; // refer to Q with a port reference 117 | initial 118 | Top.ebus.Q = i.True; // refer to Q with a hierarchical reference 119 | initial 120 | Top.ebus.I = 0; // referring to i.I would not be legal because 121 | endmodule 122 | -------------------------------------------------------------------------------- /language-configuration.json: -------------------------------------------------------------------------------- 1 | { 2 | "comments": { 3 | "lineComment": "//", 4 | "blockComment": [ "/*", "*/" ] 5 | }, 6 | // symbols used as brackets 7 | "brackets": [["{", "}"], ["[", "]"], ["(", ")"]], 8 | // symbols that are auto closed when typing 9 | "autoClosingPairs": [ 10 | { "open": "{", "close": "}" }, 11 | { "open": "[", "close": "]" }, 12 | { "open": "(", "close": ")" }, 13 | { "open": "\"", "close": "\"", "notIn": ["string", "comment"]}, 14 | { "open": "/*", "close": "*/", "notIn": ["string"]}, 15 | ], 16 | // symbols that that can be used to surround a selection 17 | "surroundingPairs": [ 18 | ["{", "}"], 19 | ["[", "]"], 20 | ["(", ")"], 21 | ["\"", "\""], 22 | ["/* ", " */"] 23 | ], 24 | "wordPattern": "(-?\\d*\\.\\d\\w*)|([^\\`\\~\\!\\@\\#\\%\\^\\&\\*\\(\\)\\-\\=\\+\\[\\{\\]\\}\\\\\\|\\;\\:\\'\\\"\\,\\.\\<\\>\\/\\?\\s]+)", 25 | "indentationRules": { 26 | "increaseIndentPattern": "^\\s*(((priority|unique|unique0)\\s+)?(case|casex|casez)|checker|(virtual\\s+)?class|config|covergroup|generate|interface|module|package|primitive|program|property|randcase|randsequence|sequence|specify|((virtual\\s+)?((local|protected|static)\\s+)?|(local|protected|static)\\s+(virtual\\s+)?)(function|task))\\b|^((?!\\/\\/|\\/\\*).)*\\bbegin\\b(?!.*\\bend\\b)|^((?!\\/\\/|\\/\\*|\\bdisable\\b|\\bwait\\b).)*\\bfork\\b(?!.*\\b(join(_any|_none|))\\b)|^((?!\\/\\/|\\/\\*).)*\\{\\s*((\\/\\/|\\/\\*).*|$)|^\\s*((default|global)\\s+)?(clocking\\b).*\\@", 27 | "decreaseIndentPattern": "^\\s*(end(case|checker|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|task)\\b)|^\\s*end\\b|^\\s*join(_any|_none|)\\b|^\\s*\\}", 28 | // sadly there is no option to include multi lines... so this rule fails on the first unterminated block comment line. Life is cruel. ^^ 29 | // "indentNextLinePattern": "^(?!.*(begin|end|fork|join|\\`\\w+(\\(.*\\))?|\\;|\\{)\\s*(\\/\\/|\\/\\*)?).*[^\\s;{}]\\s*$", 30 | // unIndented contains: comments, macros, attributes 31 | "unIndentedLinePattern": "^\\s*(\\/\\/|\\/\\*|\\`\\w+|\\(\\*).*$" 32 | }, 33 | "folding": { 34 | "markers": { 35 | "start": "^\\s*(`celldefine|`ifdef|`ifndef|`pragma\\s+protect\\b.*\\b(begin|begin_protected)\\b|`unconnected_drive)\\b|^\\s*(((priority|unique|unique0)\\s+)?(case|casex|casez)|checker|(virtual\\s+)?class|config|covergroup|generate|interface|module|package|primitive|program|property|randcase|randsequence|sequence|specify|(virtual\\s+)?((local|protected|static)\\s+)?(function|task))\\b|^((?!\\/\\/|\\/\\*).)*\\bbegin\\b(?!.*\\bend\\b)|^((?!\\/\\/|\\/\\*|\\bdisable\\b|\\bwait\\b).)*\\bfork\\b(?!.*\\b(join(_any|_none|))\\b)|^((?!\\/\\/|\\/\\*).)*\\{\\s*((\\/\\/|\\/\\*).*|$)|^\\s*((default|global)\\s+)?(clocking\\b).*\\@", 36 | "end": "^\\s*(`endcelldefine|`endif|`nounconnected_drive|`pragma\\s+protect\\b.*\\b(end|end_protected)|`resetall)\\b|^\\s*(end(case|checker|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|task)\\b)|^\\s*end\\b|^\\s*join(_any|_none|)\\b|^\\s*\\}" 37 | } 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-23-modules.svh: -------------------------------------------------------------------------------- 1 | module mh1 (input var int in1, 2 | input var shortreal in2, 3 | output tagged_st out); 4 | ... 5 | assign 6 | always_ff @(posedge clk) begin 7 | end 8 | endmodule:a::mh1 9 | 10 | module mh2 (input var int in1, 11 | input var shortreal in2, 12 | output tagged_st out); 13 | ... 14 | endmodule: mh2::a 15 | endmodule 16 | /* */ 17 | module a; 18 | endmodule// 19 | module b; 20 | endmodule: b// 21 | module c; 22 | endmodule 23 | 24 | 25 | module test(a,b,c,d,e,f,g,h); 26 | input [7:0] a; // no explicit net declaration - net is unsigned 27 | input [7:0] b; // 28 | input signed [7:0] c; 29 | input signed [7:0] d; // no explicit net declaration - net is signed 30 | output [7:0] e; // no explicit net declaration - net is unsigned 31 | output [7:0] f; 32 | output signed [7:0] g; 33 | output signed [7:0] h; // no explicit net declaration - net is signed 34 | wire signed [7:0] b; // port b inherits signed attribute from net decl. 35 | wire [7:0] c; // net c inherits signed attribute from port 36 | logic signed [7:0] f;// port f inherits signed attribute from logic decl. 37 | logic [7:0] g; // logic g inherits signed attribute from port 38 | endmodule 39 | 40 | module cpuMod(interface d, interface j); 41 | ... 42 | endmodule//comment2 43 | interface a; 44 | endinterface// 45 | module bus_conn ( 46 | output logic [7:0] dataout, 47 | input [7:0] datain = My_DataIn 48 | ); 49 | module as::cpuMod(interface d, interface j); 50 | ... 51 | module cpuMod(interface b, interface i); 52 | ... 53 | endmodule: as::labelled_output 54 | 55 | interface nested_if(); 56 | ... 57 | module aa::nested_mod(); 58 | endmodule: aa::nested_mod 59 | 60 | endinterface: a::nested_if 61 | 62 | endmodule: as::asdaf 63 | assign dataout = datain; 64 | endmodule: asd::asd 65 | endmodule 66 | 67 | function a(); 68 | endfunction: b::a 69 | 70 | module generic_decoder #(num_code_bits = 3, localparam num_out_bits = 1 << num_code_bits) 71 | (input [num_code_bits-1:0] A, output reg [num_out_bits-1:0] Y); 72 | endmodule 73 | 74 | $root(); 75 | 76 | module dff_flat(input d, ck, pr, clr, output q, nq); 77 | wire q1, nq1, q2, nq2; 78 | nand g1b (nq1, d, clr, q1); 79 | nand g1a (q1, ck, nq2, nq1); 80 | nand g2b (nq2, ck, clr, q2); 81 | nand g2a (q2, nq1, pr, nq2); 82 | nand g3a (q, nq2, clr, nq); 83 | nand g3b (nq, q1, pr, q); 84 | endmodule 85 | 86 | extern module m (.*); 87 | extern module static a #(parameter size= 8, parameter type TP = logic [7:0])(input [size:0] a, output TP b); 88 | 89 | module top (); 90 | wire [8:0] a; 91 | logic [7:0] b; 92 | wire c, d; 93 | m mm (.*); 94 | a aa (.*); 95 | .* 96 | endmodule 97 | 98 | module m1 (a,b); 99 | real r1,r2; 100 | parameter [2:0] A = 3'h2; 101 | parameter B = 3'h2; 102 | initial begin 103 | r1 = A; 104 | r2 = B; 105 | $display("r1 is %f r2 is %f",r1,r2); 106 | end 107 | endmodule: m1 108 | 109 | module m2; 110 | wire a,b; 111 | defparam f1.A = 3.1415; 112 | defparam f1.B = 3.1415; 113 | m1 f1(a,b); 114 | endmodule: m2 115 | 116 | // Example of binding a program instance to a module: 117 | bind cpu fpu_props fpu_rules_1( 118 | .clk(b), 119 | .rst(c) 120 | ); 121 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-11-operators.svh: -------------------------------------------------------------------------------- 1 | #2ns 2 | ##2 3 | #1step 4 | // assignment_operator ::= // from A.6.2 5 | = | += | -= | *= | /= | %= | &= | |= | ^= | <<= | >>= | <<<= | >>>= 6 | // unary_operator ::= // from A.8.6 7 | + | - | ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~ 8 | // binary_operator ::= 9 | + | - | * | / | % | == | != | === | !== | ==? | !=? | && | || | ** 10 | | < | <= | > | >= | & | | | ^ | ^~ | ~^ | >> | << | >>> | <<< 11 | | -> | <-> 12 | // inc_or_dec_operator ::= 13 | ++ | -- 14 | 15 | a = int'(a) 16 | 17 | int IntA; 18 | IntA = -12 / 3; // The result is -4 19 | IntA = -'d 12 / 3; // The result is 1431655761 20 | IntA = -'sd 12 / 3; // The result is -4 21 | IntA = -4'sd 12 / 3; // -4'sd12 is the negative of the 4-bit 22 | // quantity 1100, which is -4. -(-4) = 4 23 | // The result is 1 24 | (a < size-1) && (b != c) && (index != lastone) 25 | 26 | bit ba = a inside { [16:23], [32:47] }; 27 | string I; 28 | if (I inside {["a rock":"hard place"]}) ... 29 | 30 | logic [2:0] val; 31 | while ( val inside {3'b1?1} ) ... // matches 3'b101, 3'b111, 3'b1x1, 3'b1z1 32 | wire r; 33 | assign r=3'bz11 inside {3'b1?1, 3'b011}; // r = 1'bx 34 | 35 | send: 36 | begin // Create random packet and transmit 37 | byte q[$]; 38 | Packet p = new; 39 | void'(p.randomize()); 40 | q = {<< byte{p.header, p.len, p.payload, p.crc}}; // pack 41 | stream = {stream, q}; // append to stream 42 | end 43 | ... 44 | receive: begin // Receive packet, unpack, and remove 45 | byte q[$]; 46 | Packet p = new; 47 | {<< byte{ p.header, p.len, p.payload with [0 +: p.len], p.crc }} = stream; 48 | stream = stream[ $bits(p) / 8 : $ ]; // remove packet 49 | end 50 | 51 | int j = { "A", "B", "C", "D" }; 52 | { << byte {j}} // generates stream "D" "C" "B" "A" (little endian) 53 | { << 16 {j}} // generates stream "C" "D" "A" "B" 54 | { << { 8'b0011_0101 }} // generates stream 'b1010_1100 (bit reverse) 55 | { << 4 { 6'b11_0101 }} // generates stream 'b0101_11 56 | { >> 4 { 6'b11_0101 }} // generates stream 'b1101_01 (same) 57 | { << 2 { { << { 4'b1101 }} }} // generates stream 'b1110 58 | 59 | typedef union tagged { 60 | struct { 61 | bit [4:0] reg1, reg2, regd; 62 | } Add; 63 | 64 | union tagged { 65 | bit [9:0] JmpU; 66 | 67 | struct { 68 | bit [1:0] cc; 69 | bit [9:0] addr; 70 | } JmpC; 71 | 72 | } Jmp; 73 | } Instr; 74 | 75 | // operator overload 76 | bind + function float faddif(int, float); 77 | bind + function float faddfi(float, int); 78 | float A, B, C, D; 79 | assign A = B + C; //equivalent to A = faddff(B, C); 80 | assign D = A + 1.0; //equivalent to A = faddfr(A, 1.0); 81 | 82 | bind = function float fcopyi(int); // cast int to float 83 | bind = function float fcopyr(real); // cast real to float 84 | bind = function float fcopyr(shortreal); // cast shortreal to float 85 | float A, B; 86 | bind + function float faddff(float, float); 87 | always @(posedge clock) A += B; // equivalent to A = A + B 88 | 89 | let valid_arb(request, valid, override) = |(request & valid) || override; 90 | let mult(x, y) = ($bits(x) + $bits(y))'(x * y); 91 | // let with formal arguments and default value on y 92 | let eq(x, y = b) = x == y; 93 | // without parameters, binds to a, b above 94 | let tmp = a && b; 95 | 96 | function static user_type get_fiszfasz(); 97 | endfunction: get_fiszfasz 98 | 99 | function static int get_name(); 100 | endfunction: get_name 101 | 102 | package pex_gen9_common_expressions; 103 | let valid_arb(request, valid, override) = |(request & valid) || override; 104 | endpackage 105 | module my_checker; 106 | import pex_gen9_common_expressions::*; 107 | if (valid_arb(.request(req), .valid(vld), .override(ovr))) ; 108 | endmodule -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-12-procedural-programming.svh: -------------------------------------------------------------------------------- 1 | if (expression) statement; 2 | else if (expression) statement; 3 | else if (expression) statement; 4 | else statement; 5 | 6 | // declare variables and parameters 7 | logic [31:0] instruction, 8 | segment_area[255:0]; 9 | logic [7:0] index; 10 | logic [5:0] modify_seg1, 11 | modify_seg2, 12 | modify_seg3; 13 | parameter 14 | segment1 = 0, inc_seg1 = 1, 15 | segment2 = 20, inc_seg2 = 2, 16 | segment3 = 64, inc_seg3 = 4, 17 | data = 128; 18 | 19 | // test the index variable 20 | if (index < segment2) begin 21 | instruction = segment_area [index + modify_seg1]; 22 | index = index + inc_seg1; 23 | end 24 | else if (index < segment3) begin 25 | instruction = segment_area [index + modify_seg2]; 26 | index = index + inc_seg2; 27 | end 28 | else if (index < data) begin 29 | instruction = segment_area [index + modify_seg3]; 30 | index = index + inc_seg3; 31 | end 32 | else 33 | instruction = segment_area [index]; 34 | 35 | if (e matches (tagged Jmp (tagged JmpC '{cc:.c,addr:.a}))) 36 | ... // c and a can be used here 37 | else ; 38 | ... 39 | 40 | if (e matches (tagged Jmp .j) &&& j matches (tagged JmpC '{cc:.c,addr:.a})) 41 | ... // c and a can be used here 42 | else ; 43 | 44 | logic [15:0] data; 45 | logic [9:0] result; 46 | case (data) 47 | 16'd0: result = 10'b0111111111; 48 | 16'd1: result = 10'b1011111111; 49 | 16'd2: result = 10'b1101111111; 50 | 16'd3: result = 10'b1110111111; 51 | 16'd4: result = 10'b1111011111; 52 | 16'd5: result = 10'b1111101111; 53 | 16'd6: result = 10'b1111110111; 54 | 16'd7: result = 10'b1111111011; 55 | 16'd8: result = 10'b1111111101; 56 | 16'd9: result = 10'b1111111110; 57 | default: result = 'x; 58 | endcase 59 | 60 | case (1) 61 | encode[2] : $display("Select Line 2") ; 62 | encode[1] : $display("Select Line 1") ; 63 | encode[0] : $display("Select Line 0") ; 64 | default : $display("Error: One of the bits expected ON"); 65 | endcase 66 | 67 | bit [2:0] a; 68 | unique case(a) // values 3,5,6,7 cause a violation report 69 | 0,1: $display("0 or 1"); 70 | 2: $display("2"); 71 | 4: $display("4"); 72 | endcase 73 | 74 | priority casez(a) // values 4,5,6,7 cause a violation report 75 | 3'b00?: $display("0 or 1"); 76 | 3'b0??: $display("2 or 3"); 77 | endcase 78 | 79 | unique0 case(a) // values 3,5,6,7 do not cause a violation report 80 | 0,1: $display("0 or 1"); 81 | 2: $display("2"); 82 | 4: $display("4"); 83 | endcase 84 | 85 | always_comb begin : a1 86 | unique case (1'b1) 87 | a : z = b; 88 | not_a : z = c; 89 | endcase 90 | end 91 | 92 | case (v) matches 93 | tagged Invalid : $display ("v is Invalid"); 94 | tagged Valid .n : $display ("v is Valid with value %d", n); 95 | endcase 96 | 97 | case (instr) matches 98 | tagged Add s: case (s) matches 99 | '{.*, .*, 0} : ; // no op 100 | '{.r1, .r2, .rd} : rf[rd] = rf[r1] + rf[r2]; 101 | endcase 102 | tagged Jmp .j: case (j) matches 103 | tagged JmpU .a : pc = pc + a; 104 | tagged JmpC '{.c, .a} : if (rf[c]) pc = a; 105 | default ; 106 | default: ; 107 | endcase 108 | endcase 109 | 110 | case (instr) matches 111 | tagged Add '{reg2:.r2,regd:.rd,reg1:.r1} &&& (rd != 0): rf[rd] = rf[r1] + rf[r2]; 112 | tagged Jmp (tagged JmpU .a) : pc = pc + a; 113 | tagged Jmp (tagged JmpC '{addr:.a,cc:.c}) : if (rf[c]) pc = a; 114 | endcase 115 | 116 | foreach( words [ j ] ) 117 | $display( j , words[j] ); // print each index and value 118 | foreach( prod[ k, m ] ) 119 | prod[k][m] = k * m; // initialize 120 | 121 | return break continue 122 | 123 | initial begin 124 | clock1 <= 0; 125 | clock2 <= 0; 126 | fork 127 | forever #10 clock1 = ~clock1; 128 | #5 forever #10 clock2 = ~clock2; 129 | join 130 | end 131 | 132 | logic [2:0] status; 133 | always @(posedge clock) 134 | priority case (status) inside 135 | 1, 3 : task1; // matches 'b001 and 'b011 136 | 3'b0?0, [4:7] : task2; // matches 'b000 'b010 'b0x0 'b0z0 'b100 'b101 'b110 'b111 137 | endcase // priority case fails all other values including 'b00x 'b01x 'bxxx -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-13-task-and-functions.svh: -------------------------------------------------------------------------------- 1 | task static mytask1 (output int x, input logic y); 2 | ... 3 | endtask 4 | 5 | task automatic mytask2; 6 | output x; 7 | input y; 8 | int x; 9 | logic y; 10 | ... 11 | endtask: mytask2 12 | 13 | class a; 14 | extern task lights_out(inout int x); 15 | pure virtual task lights(input int unsigned x); 16 | endclass: a 17 | 18 | module traffic_lights; 19 | logic clock, red, amber, green; 20 | parameter on = 1, off = 0, red_tics = 350, 21 | amber_tics = 30, green_tics = 200; 22 | // initialize colors 23 | initial red = off; 24 | initial amber = off; 25 | initial green = off; 26 | 27 | always begin: sequence_to_control_the_lights 28 | red = on; // turn red light on 29 | light(red, red_tics); // and wait. 30 | green = on; // turn green light on 31 | light(green, green_tics); // and wait. 32 | amber = on; // turn amber light on 33 | light(amber, amber_tics); // and wait. 34 | end: sequence_to_control_the_lights 35 | // task to wait for 'tics' positive edge clocks 36 | // before turning 'color' light off 37 | task light (output color, input [31:0] tics); 38 | repeat (tics) @ (posedge clock); 39 | color = off; // turn light off. 40 | endtask: light 41 | 42 | always begin: waveform_for_the_clock 43 | #100 clock = 0; 44 | #100 clock = 1; 45 | end: waveform_for_the_clock 46 | endmodule: traffic_lights 47 | 48 | // define the function 49 | function automatic integer factorial (input [31:0] operand); 50 | if (operand >= 2) 51 | factorial = factorial (operand - 1) * operand; 52 | else 53 | factorial = 1; 54 | endfunction: factorial 55 | 56 | function integer clogb2 (input [31:0] value); 57 | value = value - 1; 58 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 59 | value = value >> 1; 60 | endfunction 61 | 62 | function user_integer clogb2 (input [31:0] value); 63 | value = value - 1; 64 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 65 | value = value >> 1; 66 | endfunction 67 | 68 | function integer a::clogb2 (input [31:0] value); 69 | value = value - 1; 70 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 71 | value = value >> 1; 72 | endfunction 73 | 74 | function user_integer a::clogb2 (input [31:0] value); 75 | value = value - 1; 76 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 77 | value = value >> 1; 78 | endfunction 79 | 80 | 81 | function user_integer_t clogb2 (input [31:0] value); 82 | value = value - 1; 83 | for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 84 | value = value >> 1; 85 | endfunction 86 | 87 | function automatic bit watch_for_zero( IntClass p ); 88 | fork 89 | forever @p.a begin: Forever_block 90 | if ( p.a == 0 ) $display ("Unexpected zero"); 91 | end: Forever_block 92 | join_none 93 | return ( p.a == 0 ); 94 | endfunction 95 | endfunction 96 | 97 | function automatic int crc( ref byte packet [1000:1] ); 98 | for( int j= 1; j <= 1000; j++ ) begin 99 | crc ^= packet[j]; 100 | end 101 | endfunction 102 | 103 | function automatic user_int crc( ref byte packet [1000:1] ); 104 | for( int j= 1; j <= 1000; j++ ) begin 105 | crc ^= packet[j]; 106 | end 107 | endfunction 108 | 109 | task automatic show ( const ref byte data [] ); 110 | for ( int j = 0; j < data.size ; j++ ) 111 | $display( data[j] ); // data can be read but not written 112 | endtask 113 | 114 | class external_wrapper; 115 | extern protected virtual function user_integer_t send(int value); 116 | 117 | extern protected virtual function user_integer send(int value); 118 | 119 | extern protected virtual function int send(int value); 120 | endclass: external_wrapper 121 | 122 | virtual class C#(parameter DECODE_W, parameter ENCODE_W = $clog2(DECODE_W)); 123 | 124 | static function logic [ENCODE_W-1:0] ENCODER_f (input logic [DECODE_W-1:0] DecodeIn); 125 | ENCODER_f = '0; 126 | for (int i=0; i (posedge clk1) 85 | ... 86 | end 87 | endmodule 88 | endmodule 89 | 90 | module subsystem1; 91 | logic subclk1; 92 | global clocking sub_sys1 @(subclk1); 93 | int i; 94 | endclocking 95 | // ... 96 | common_sub common(); 97 | endmodule 98 | 99 | module top; 100 | subsystem1 sub1(); 101 | subsystem2 sub2(); 102 | endmodule 103 | 104 | module subsystem1; 105 | logic subclk1; 106 | global clocking sub_sys1 @(subclk1); 107 | // ... 108 | endclocking 109 | common_sub common(); 110 | endmodule 111 | 112 | module subsystem2; 113 | logic subclk2; 114 | global clocking sub_sys2 @(subclk2); 115 | // ... 116 | common_sub common(); 117 | endclocking 118 | endmodule 119 | 120 | module common_sub; 121 | always @($global_clock) begin 122 | // ... 123 | end 124 | endmodule 125 | 126 | module top; 127 | logic a, b, c, clk; 128 | global clocking top_clocking @(clk); 129 | endclocking 130 | // ... 131 | property p1(req, ack); 132 | @($global_clock) req |=> ack; 133 | endproperty 134 | 135 | property p2(req, ack, interrupt); 136 | @($global_clock) accept_on(interrupt) p1(req, ack); 137 | endproperty: p2 138 | 139 | my_checker check( 140 | p2(a, b, c), 141 | @$global_clock a[*1:$] ##1 b 142 | ); 143 | endmodule 144 | 145 | checker my_checker(property p, sequence s); 146 | logic checker_clk; 147 | global clocking checker_clocking @(checker_clk); 148 | 149 | // ... 150 | endclocking 151 | assert property (p); 152 | cover property (s); 153 | endchecker 154 | 155 | bus.data[3:0] <= 4'h5; // drive data in Re-NBA region of the current cycle 156 | ##1 bus.data <= 8'hz; // wait 1 default clocking cycle, then drive data 157 | ##2; bus.data <= 2; // wait 2 default clocking cycles, then drive data 158 | bus.data <= ##2 r; // remember the value of r and then drive 159 | // data 2 (bus) cycles later 160 | bus.data <= #4 r; // error: regular intra-assignment delay not allowed 161 | // in synchronous drives 162 | 163 | module m; 164 | bit a = 1'b1; 165 | default clocking cb @(posedge clk); 166 | output a; 167 | endclocking 168 | 169 | initial begin 170 | ## 1; 171 | cb.a <= 1'b0; 172 | @(x); // x is triggered by reactive stimulus running in same time step 173 | cb.a <= 1'b1; 174 | end 175 | endmodule 176 | 177 | reg j; 178 | 179 | clocking pe @(posedge clk); 180 | output j; 181 | endclocking 182 | 183 | clocking ne @(negedge clk); 184 | output j; 185 | endclocking 186 | 187 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SystemVerilog-1800-2012 README 2 | 3 | This extension incorporates syntax highlighting and snippet support for `IEEE Std 1800-2012 - SystemVerilog` hardware description language and `Universal Verification Methodology` (UVM) in [Visual Studio Code](https://code.visualstudio.com/). 4 | 5 | # Note 6 | Please note, that I've created this extension to create a comfortable environment for my workflow. It **does not** and **does not even aim** to fullfill the needs of everyone, especially since I am much more involved in the UVM based verification side than in design. It will not give you any kind of built in support for any FOSS or industry tools (eg.: Verilator, VCS, ModelSim, etc.) by default, so please don't expect that. 7 | 8 | At this stage the extension does not have instantation pattern or language server support neither. However you can expect proper syntax recognization, scoping and snippets for both SystemVerilog and UVM. 9 | 10 | If you still like the extension, please feel free to throw me a 'Hi!' if we meet at a conference or exhibition or even on LinkedIn. I'd like to hear about your experiences! :) 11 | 12 | # Features 13 | * Syntax highlighting and basic syntax checking capabilites for SystemVerilog. 14 | * Scope based start end checking for *module-endmodule*, *fork-join*, *begin-end*, etc. constructs to help debugging via the highlighting 15 | * Formatting and indentation support (via the built in command: **Reindent Lines**) to VS Code's natural limitations on *well written code* 16 | * UVM class and type integration (mostly done, in progress) 17 | * Snippet support for the verification side of SV and UVM 18 | 19 | ![Screenshot](https://github.com/gvekony/sv-1800-2012/raw/master/images/sv_screenshot_monokai_pro.png) 20 | 21 | ## Fully or partially supported SystemVerilog-2012-1800 features 22 | * checkers 23 | * classes (abstract, concrete) 24 | * comments, attributes, various conventional highlights (accessors, numbers, etc.) 25 | * constraint blocks 26 | * coverage, covergroups 27 | * interfaces, modports, clocking blocks 28 | * modules 29 | * packages 30 | * programs 31 | * tasks and functions (extern, virtual, etc.) 32 | * gate level and user-defined primitives 33 | 34 | ### SV Snippets 35 | SystemVerilog snippets are available with a `sv_` prefix. 36 | 37 | * Containers: sv_module, sv_interface, sv_class 38 | * Language constructs: sv_block_parallel, sv_block_sequential, sv_if, sv_if_blocks, sv_if_blocks_labels 39 | 40 | As VS Code uses clever search in words and snippets pressing `sq` will most likely result in `sv_block_sequential` so you don't need to type the whole snippet expression. :) 41 | 42 | ## UVM 43 | * UVM classes and functions are partially supported, implementation is work in progress. 44 | * UVM config_db calls, macros and types are partially supported via highlighting and snippets. 45 | 46 | ### UVM Snippets 47 | The most common UVM boilerplates are available with an `uvm_` prefix. 48 | 49 | * UVM containers, eg.: uvm_class_object, uvm_class_object_params, uvm_class_component, uvm_class_component_params, etc. 50 | * ConfigDB accesses, eg.: uvm_config_db_get, uvm_config_db_set, uvm_config_db_get_guarded, etc. 51 | * Factory instantiations, eg.: uvm_factory_instantiation_object, uvm_factory_instantiation_component 52 | * Macros (field macros are purposely omitted): uvm_macro_info, uvm_macro_warning, uvm_macro_error, uvm_macro_object_utils, etc. 53 | * Phases in both short extern versions and fully fledged ones, eg.: `uvm_extern_phase_build`, `uvm_phase_pre_configure`, etc. 54 | 55 | ![Snippets](https://github.com/gvekony/sv-1800-2012/raw/master/images/vs_code_snippets.gif) 56 | 57 | ## Indentation rules 58 | * Indentation rules are added for the common constructs of SystemVerilog (eg.: module-endmodule, begin-end, etc.) for VS Code's `reindent` function 59 | * As VS Code uses tmLanguage (TextMate) styled rules for this, there is no multiline support, eg. block comments can break your indentation if a line starts with begin for example. 60 | 61 | ## Extra folding rules 62 | * Extra folding (but not indentation) rules are set for SystemVerilog compiler directives (eg.: ifdef-endif, pragma protect begin-end, etc.) 63 | * Similarly to indentation rules, line breaked `` `pragma protect begin`` break this feature. 64 | 65 | # Release Notes 66 | ## [1.0.27] 67 | ### Changes 68 | * Added `uvm_sequence` functions snippet. 69 | * Updated the main UVM phase snippet definition with proper objection related `uvm_info` macros. 70 | * Added whitespace guide snippet aligned for `$sformatf()`. 71 | * Added `c_` and `if_` to variable naming conventions to represent combinatorical wires and interfaces. (Design Naming Convention) 72 | ### Bugfixes 73 | * Added missing `extensionKind` to package.json thus enabled remote install for SSH development. 74 | * Added indent pattern for `(local|protected|static) virtual` functions and tasks. 75 | 76 | # License and source information 77 | 78 | [MIT](https://github.com/gvekony/sv-1800-2012/blob/master/LICENSE.md) © **Gergo Vekony** 79 | 80 | The source can be found @ [GitHub](https://github.com/gvekony/sv-1800-2012) 81 | 82 | -------------------------------------------------------------------------------- /snippets/sv_language_constructs.json: -------------------------------------------------------------------------------- 1 | { 2 | "systemverilog_fork_join": { 3 | "prefix": "sv_block_parallel", 4 | "body": [ 5 | "fork${1:: label}", 6 | "\t$0", 7 | "join${2:}$1", 8 | "${3:// disable fork;}\n" 9 | ], 10 | "description": "The fork-join parallel block construct enables the creation of concurrent processes from each of its parallel statements." 11 | }, 12 | "systemverilog_begin_end": { 13 | "prefix": "sv_block_sequential", 14 | "body": [ 15 | "begin${1:: label}", 16 | "\t$0", 17 | "end$1\n" 18 | ], 19 | "description": "The procedural statements in a sequential block shall be executed sequentially in the given order." 20 | }, 21 | "systemverilog_if_else": { 22 | "prefix": "sv_if", 23 | "body": [ 24 | "if (${1:condition}) ${2:true_block_statement}", 25 | "else ${3:false_block_statement}\n$0" 26 | ], 27 | "description": "The conditional statement (or if–else statement) is used to make a decision about whether a statement is executed." 28 | }, 29 | "systemverilog_if_else_with_blocks": { 30 | "prefix": "sv_if_blocks", 31 | "body": [ 32 | "if (${1:condition}) begin", 33 | "\t$0", 34 | "end", 35 | "else begin", 36 | "\t", 37 | "end\n" 38 | ], 39 | "description": "The conditional statement (or if–else statement) is used to make a decision about whether a statement is executed." 40 | }, 41 | "systemverilog_if_else_with_blocks_labels": { 42 | "prefix": "sv_if_blocks_labels", 43 | "body": [ 44 | "if (${1:condition}) begin${2:: true_block_label}", 45 | "\t$0", 46 | "end$2", 47 | "else begin${3:: false_block_label}", 48 | "\t", 49 | "end$3\n" 50 | ], 51 | "description": "The conditional statement (or if–else statement) is used to make a decision about whether a statement is executed." 52 | }, 53 | "systemverilog_function": { 54 | "prefix": "sv_function", 55 | "body": [ 56 | "$5function ${1:return} ${2:$TM_FILENAME_BASE}${3:::}${4:name}(${6:parameters});", 57 | "\t$0", 58 | "endfunction: $4\n" 59 | ], 60 | "description": "function ... endfunction construct" 61 | }, 62 | "systemverilog_task": { 63 | "prefix": "sv_task", 64 | "body": [ 65 | "$4task ${1:$TM_FILENAME_BASE}${2:::}${3:name}(${5:parameters});", 66 | "\t$0", 67 | "endtask: $3\n" 68 | ], 69 | "description": "task ... endtask construct" 70 | }, 71 | 72 | "sv_always_comb": { 73 | "prefix": "sv_always_comb", 74 | "body": [ 75 | "always_comb begin${1:: }", 76 | "\t$0", 77 | "end$1" 78 | ], 79 | "description": "Always block for combinatorial logics." 80 | }, 81 | "sv_always_ff": { 82 | "prefix": "sv_always_ff", 83 | "body": [ 84 | "always_ff @(posedge ${1:clk}) begin${2:: }", 85 | "\t$0", 86 | "end$2\n" 87 | ], 88 | "description": "Always block for synchronous logics." 89 | }, 90 | "sv_always_ff_with_rst": { 91 | "prefix": "sv_always_ff_with_rst", 92 | "body": [ 93 | "always_ff @(posedge ${1:clk}) begin${2:: }", 94 | "\tif (${3:rst}) begin${4:: }", 95 | "\t\t$0", 96 | "\tend$4", 97 | "\telse begin${5:: }", 98 | "\t\t", 99 | "\tend$5", 100 | "end$2\n" 101 | ], 102 | "description": "Always block for synchronous logics with reset support." 103 | }, 104 | 105 | // Common System Calls 106 | "bits" : { 107 | "prefix": "$bits", 108 | "body": [ 109 | "\\$bits($1)$0" 110 | ], 111 | "description": "The $bits system function returns the number of bits required to hold an expression as a bit stream." 112 | }, 113 | "cast": { 114 | "prefix": "$cast", 115 | "body": [ 116 | "\\$cast(${1:singular_dest_var}, ${2:singular_source_expr})$0" 117 | ], 118 | "description": "The $cast system function performs a dynamic cast of an expression type." 119 | }, 120 | "sformatf": { 121 | "prefix": "$sformatf", 122 | "body": [ 123 | "\\$sformatf(\"$1\", $2)$0" 124 | ], 125 | "description": "Returns a formatted string." 126 | }, 127 | "timeformat": { 128 | "prefix": "$timeformat", 129 | "body": [ 130 | "\\$timeformat(${1:units_number}, ${2:precision_number}, ${3:suffix_string}, ${4:minimum_field_width});\n$0" 131 | ], 132 | "description": "The $timeformat system task specifies how the %t format specification reports time information." 133 | }, 134 | "urandom_range": { 135 | "prefix": "$urandom_range", 136 | "body": [ 137 | "\\$urandom_range(${1:maxval}, ${2:minval = 0})$0" 138 | ], 139 | "description": "The $urandom_range() function returns an unsigned integer within a specified range." 140 | } 141 | } 142 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-18-constraints-and-randomization.svh: -------------------------------------------------------------------------------- 1 | class Bus #( asd () ); 2 | rand bit[15:0] addr; 3 | rand bit[31:0] data; 4 | 5 | extern constraint abc; 6 | 7 | pure static constraint Bus::asdasf; 8 | 9 | static constraint abc; 10 | 11 | constraint word_align { 12 | addr[1:0] == 2'b0; 13 | } 14 | 15 | endclass 16 | 17 | static constraint abc; 18 | 19 | static constraint Bus::abc { 20 | 21 | } 22 | 23 | typedef enum {low, mid, high} AddrType; 24 | 25 | class MyBus extends Bus; 26 | 27 | rand AddrType atype; 28 | 29 | constraint a {} 30 | 31 | constraint addr_range 32 | { 33 | (atype == low ) -> addr inside { [0 : 15] }; 34 | (atype == mid ) -> addr inside { [16 : 127]}; 35 | (atype == high) -> addr inside {[128 : 255]}; 36 | } 37 | endclass 38 | 39 | task exercise_bus (MyBus bus); 40 | int res; 41 | // EXAMPLE 1: restrict to low addresses 42 | res = bus.randomize() with {atype == low;}; 43 | // EXAMPLE 2: restrict to address between 10 and 20 44 | res = bus.randomize() with {10 <= addr && addr <= 20;}; 45 | // EXAMPLE 3: restrict data values to powers-of-two 46 | res = bus.randomize() with {(data & (data - 1)) == 0;}; 47 | endtask 48 | 49 | class MyXYPair extends XYPair; 50 | function void pre_randomize(); 51 | super.pre_randomize(); 52 | $display("Before randomize x=%0d, y=%0d", x, y); 53 | endfunction 54 | 55 | function void post_randomize(); 56 | super.post_randomize(); 57 | $display("After randomize x=%0d, y=%0d", x, y); 58 | endfunction 59 | endclass 60 | 61 | int success = p.randomize(); 62 | 63 | function bit gen_stim(); 64 | bit success, rd_wr; 65 | success = randomize( addr, data, rd_wr ); // call std::randomize 66 | return rd_wr ; 67 | endfunction 68 | 69 | 70 | class packet; 71 | typedef struct { 72 | randc int addr = 1 + constant; 73 | int crc; 74 | rand byte data [] = {1,2,3,4}; 75 | } header; 76 | 77 | rand header h1; 78 | endclass 79 | 80 | class C; 81 | rand int x; 82 | 83 | static constraint proto; 84 | 85 | constraint proto1; // implicit form 86 | extern constraint proto2; // explicit form 87 | 88 | 89 | rand byte a[5]; 90 | rand byte b; 91 | rand byte excluded; 92 | constraint u { unique {b, a[2:3], excluded}; } 93 | constraint exclusion { excluded == 5; } 94 | 95 | mode == little -> len < 10; 96 | mode == big -> len > 100; 97 | 98 | constraint C1 { foreach ( A [ i ] ) A[i] inside {2,4,8,16}; } 99 | constraint c1 { A.size inside {[1:10]}; } 100 | constraint c2 { foreach ( A[ k ] ) (k < A.size - 1) -> A[k + 1] > A[k]; } 101 | 102 | rand bit [31:0] d; 103 | constraint c { s -> {d == 0;} } 104 | constraint order { solve s before d; } 105 | 106 | endclass 107 | 108 | constraint C::proto1 { x inside {-4, 5, 7}}; } 109 | constraint C::proto2 { x >= 0; } 110 | 111 | virtual class D; 112 | pure constraint test; 113 | 114 | endclass 115 | 116 | 117 | rand integer x, y, z; 118 | constraint c1 {x inside {3, 5, [9:15], [24:32], [y:2*y], z};} 119 | rand integer a, b, c; 120 | constraint c2 {a inside {b, c};} 121 | integer fives[4] = '{ 5, 10, 15, 20 }; 122 | rand integer v; 123 | constraint c3 { v inside {fives}; } 124 | 125 | x != 200; 126 | x dist {100 := 1, 200 := 2, 300 := 5} 127 | 128 | class Packet; 129 | rand int length; 130 | constraint deflt { soft length inside {32,1024}; } 131 | endclass 132 | 133 | class B; 134 | rand int x; 135 | constraint B1 { soft x == 5; } 136 | constraint B2 { 137 | disable soft x; 138 | soft x dist {5, 8}; 139 | } 140 | endclass 141 | 142 | get_randstate(); 143 | set_randstate(); 144 | srandom(); 145 | 146 | randcase 147 | 3 : x = 1; 148 | 1 : x = 2; 149 | 4 : x = 3; 150 | endcase 151 | 152 | randcase 153 | a + b : x = 1; 154 | a - b : x = 2; 155 | a ^ ~b : x = 3; 156 | 12'b800 : x = 4; 157 | endcase 158 | 159 | randsequence( main ) 160 | main : first second done ; 161 | first : add | dec ; 162 | second : pop | push ; 163 | done : { $display("done"); } ; 164 | add : { $display("add"); } ; 165 | dec : { $display("dec"); } ; 166 | pop : { $display("pop"); } ; 167 | push : { $display("push"); } ; 168 | rand join asd; 169 | endsequence 170 | 171 | randsequence() 172 | WRITE : SETUP DATA ; 173 | SETUP : { if( fifo_length >= max_length ) break; } COMMAND ; 174 | DATA : ... 175 | endsequence 176 | 177 | randsequence() 178 | TOP : P1 P2 ; 179 | P1 : A B C ; 180 | P2 : A { if( flag == 1 ) return; } B C ; 181 | A : { $display( "A" ); } ; 182 | B : { if( flag == 2 ) return; $display( "B" ); } ; 183 | C : { $display( "C" ); } ; 184 | endsequence 185 | 186 | int cnt; 187 | ... 188 | randsequence( A ) 189 | void A : A1 A2; 190 | void A1 : { cnt = 1; } B repeat(5) C B 191 | { $display("c=%d, b1=%d, b2=%d", C, B[1], B[2]); } 192 | ; 193 | void A2 : if (cond) D(5) else D(20) 194 | { $display("d1=%d, d2=%d", D[1], D[2]); } 195 | ; 196 | int B : C { return C;} 197 | | C C { return C[2]; } 198 | | C C C { return C[3]; } 199 | ; 200 | int C : { cnt = cnt + 1; return cnt; }; 201 | int D (int prm) : { return prm; }; 202 | endsequence 203 | 204 | function int[$] GenQueue(int low, int high); 205 | int[$] q; 206 | randsequence() 207 | TOP : BOUND(low) LIST BOUND(high) ; 208 | LIST : LIST ITEM := 8 { q = { q, ITEM }; } 209 | | ITEM := 2 { q = { q, ITEM }; } 210 | ; 211 | int ITEM : { return $urandom_range( low, high ); } ; 212 | BOUND(int b) : { q = { q, b }; } ; 213 | endsequence 214 | GenQueue = q; 215 | endfunction 216 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-09-processes.svh: -------------------------------------------------------------------------------- 1 | initial begin: label_test 2 | a = 0; // initialize a 3 | for (int index = 0; index < size; index++) 4 | memory[index] = 0; // initialize memory word 5 | end: label_test 6 | 7 | begin:label_test1 8 | begin: label_test2 9 | end :label_test2 10 | end : label_test1 11 | 12 | end // unmatched pair 13 | 14 | always areg = ~areg; 15 | 16 | always_comb 17 | a = b & c; 18 | 19 | always_comb 20 | d <= #1ns b & c; 21 | 22 | always_comb 23 | begin 24 | a = b & c; 25 | A1:assert (a != e) else if (!disable_error) $error("failed"); 26 | end 27 | 28 | always_latch 29 | if(ck) q <= d; 30 | 31 | always_ff @(posedge clock iff reset == 0 or posedge reset) 32 | begin 33 | r1 <= reset ? 0 : r2 + 1; 34 | end 35 | 36 | final 37 | begin 38 | $display("Number of cycles executed %d",$time/period); 39 | $display("Final PC = %h",PC); 40 | end 41 | 42 | begin 43 | areg = breg; 44 | @(posedge clock) creg = areg; // assignment delayed until 45 | end 46 | 47 | parameter d = 50; // d declared as a parameter and 48 | logic [7:0] r; // r declared as an 8-bit variable 49 | begin // a waveform controlled by sequential delays 50 | #d r = 'h35; 51 | #d r = 'hE2; 52 | #d r = 'h00; 53 | #d r = 'hF7; 54 | end 55 | 56 | fork 57 | begin 58 | $display( "First Block\n" ); 59 | #20ns; 60 | end 61 | begin 62 | $display( "Second Block\n" ); 63 | @eventA; 64 | end 65 | join 66 | 67 | task wait_20; 68 | fork 69 | # 20; 70 | return ; // Illegal: cannot return; task lives in another process 71 | join_none 72 | endtask 73 | 74 | begin 75 | fork : fork_label 76 | @Aevent; 77 | @Bevent; 78 | join_any : fork_label 79 | areg = breg; 80 | end 81 | 82 | labelB: fork // label before the begin or fork 83 | ... 84 | join_none : labelB 85 | 86 | @r rega = regb; // controlled by any value change in the reg r 87 | @(posedge clock) rega = regb; // controlled by posedge on clock 88 | forever @(negedge clock) rega = regb; // controlled by negedge on clock 89 | forever @(edge clock) rega = regb; // controlled by edge on clock 90 | 91 | real AOR[]; // dynamic array of reals 92 | byte stream[$]; // queue of bytes 93 | initial wait(AOR.size() > 0) ....; // waits for array to be allocated 94 | initial wait($bits(stream) > 60)...; // waits for total number of bits 95 | // in stream greater than 60 96 | Packet p = new; // Packet 1 -- Packet is defined in 8.2 97 | Packet q = new; // Packet 2 98 | initial fork 99 | @(p.status); // Wait for status in Packet 1 to change 100 | @p; // Wait for a change to handle p 101 | # 10 p = q; // triggers @p. 102 | // @(p.status) now waits for status in Packet 2 to change, 103 | // if not already different from Packet 1 104 | join 105 | 106 | @(trig or enable) rega = regb; // controlled by trig or enable 107 | @(posedge clk_a or posedge clk_b or trig) rega = regb; 108 | 109 | always @(a, b, c, d, e) 110 | always @(posedge clk, negedge rstn) 111 | always @(a or b, c, d or e) 112 | 113 | always @(*) // equivalent to @(a or b or c or d or f) 114 | y = (a & b) | (c & d) | myfunction(f); 115 | 116 | always @* begin // equivalent to @(a or b or c or d or tmp1 or tmp2) 117 | tmp1 = a & b; 118 | tmp2 = c & d; 119 | y = tmp1 | tmp2; 120 | end 121 | 122 | always @* begin // equivalent to @(b) 123 | @(i) kid = b; // i is not added to @* 124 | end 125 | 126 | always @* begin // equivalent to @(a or b or c or d) 127 | x = a ^ b; 128 | @* // equivalent to @(c or d) 129 | x = c ^ d; 130 | end 131 | 132 | always @* begin // same as @(state or go or ws) 133 | next = 4'b0; 134 | case (1'b1) 135 | state[IDLE]: 136 | if (go) next[READ] = 1'b1; 137 | else next[IDLE] = 1'b1; 138 | state[READ]: next[DLY ] = 1'b1; 139 | state[DLY ]: 140 | if (!ws) next[DONE] = 1'b1; 141 | else next[READ] = 1'b1; 142 | state[DONE]: next[IDLE] = 1'b1; 143 | endcase 144 | end 145 | 146 | module latch (output logic [31:0] y, input [31:0] a, input enable); 147 | always @(a iff enable == 1) 148 | y <= a; //latch is in transparent mode 149 | endmodule 150 | 151 | sequence abc; 152 | @(posedge clk) a ##1 b ##1 c; 153 | endsequence 154 | 155 | program test; 156 | initial begin 157 | @ abc $display( "Saw a-b-c" ); 158 | L1 : ... 159 | end 160 | endprogram 161 | 162 | program check; 163 | initial begin 164 | wait( abc.triggered || de.triggered ); 165 | if( abc.triggered ) 166 | $display( "abc succeeded" ); 167 | if( de.triggered ) 168 | $display( "de succeeded" ); 169 | L2 : ... 170 | end 171 | endprogram 172 | 173 | a = repeat(3) @(posedge clk) b; 174 | a = repeat(num) @(clk) data; 175 | a <= repeat(a+b) @(posedge phi1 or negedge phi2) data; 176 | 177 | task do_test; 178 | fork 179 | exec1(); 180 | exec2(); 181 | join_any 182 | fork 183 | exec3(); 184 | exec4(); 185 | join_none 186 | wait fork; // block until exec1 ... exec4 complete 187 | endtask 188 | 189 | begin : block_name 190 | rega = regb; 191 | disable block_name; 192 | regc = rega; // this assignment will never execute 193 | end 194 | 195 | task get_first( output int adr ); 196 | fork 197 | wait_device( 1, adr ); 198 | wait_device( 7, adr ); 199 | wait_device( 13, adr ); 200 | join_any 201 | disable fork; 202 | endtask 203 | 204 | class process; 205 | typedef enum { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED } state; 206 | extern static function process self(); 207 | extern function state .status(); 208 | extern function void .kill(); 209 | extern task .await(); 210 | extern function void .suspend(); 211 | extern function void .resume(); 212 | extern function void srandom( int seed ); 213 | extern function string get_randstate(); 214 | extern function void set_randstate( string state ); 215 | endclass -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-01.svh: -------------------------------------------------------------------------------- 1 | // systemverilog crash course #1 2 | pure virtual function static void asdafasdaf(); 3 | extern virtual function void aqwerasd(); 4 | pure virtual function automatic void asdaf(); 5 | 6 | Example 1: Unsized literal constant numbers 7 | 659 // is a decimal number 8 | 'h 837FF // is a hexadecimal number 9 | 'o7460 // is an octal number 10 | 4af // is illegal (hexadecimal format requires 'h) 11 | Example 2: Sized literal constant numbers 12 | 4'b1001 // is a 4-bit binary number 13 | 5 'D 3 // is a 5-bit decimal number 14 | 3'b01x // is a 3-bit number with the least 15 | // significant bit unknown 16 | 12'hx // is a 12-bit unknown number 17 | 16'hz // is a 16-bit high-impedance number 18 | Example 3: Using sign with literal constant numbers 19 | 8 'd -6 // this is illegal syntax 20 | -8 'd 6 // this defines the two's complement of 6, 21 | // held in 8 bits—equivalent to -(8'd 6) 22 | 4 'shf // this denotes the 4-bit number '1111', to 23 | // be interpreted as a 2's complement number, 24 | // or '-1'. This is equivalent to -4'h 1 25 | -4 'sd15 // this is equivalent to -(-4'd 1), or '0001' 26 | 16'sd? // the same as 16'sbz 27 | Example 4: Automatic left padding of literal constant numbers 28 | logic [11:0] a, b, c, d; 29 | logic [84:0] e, f, g; 30 | initial begin 31 | a = 'h x; // yields xxx 32 | Copyright © 2013 IEEE. All rights reserved. 33 | b = 'h 3x; // yields 03x 34 | c = 'h z3; // yields zz3 35 | d = 'h 0z3; // yields 0z3 36 | e = 'h5; // yields {82{1'b0},3'b101} 37 | f = 'hx; // yields {85{1'hx}} 38 | g = 'hz; // yields {85{1'hz}} 39 | end 40 | 41 | 42 | virtual function void a(); 43 | endfunction: a 44 | function void lorem_ipsum(); 45 | endfunction: lorem_ipsum 46 | virtual task static tasky_task(); 47 | endtask 48 | virtual function bit[31:0] a(); 49 | endfunction: a 50 | 51 | function void a(); 52 | endfunction: a 53 | function void a(); 54 | for(int i=1; i<120; i++); 55 | endfunction: a 56 | 57 | for(int i=1; i<120; i++) 58 | 59 | interface a(input bit[31:0] data); 60 | endinterface:a 61 | 62 | interface class fw_agent_if extends fw_base_if; 63 | endclass: fw_base_if 64 | 65 | class fw_agent_parent extends uvm_component implements fw_agent_if; 66 | endclass: fw_agent_parent 67 | 68 | virtual class d; 69 | // pure constraint test; 70 | endclass 71 | 72 | class D2 extends B2; 73 | rand int x; 74 | constraint d { soft y inside {[5:9]} ; } 75 | constraint e ; /* d1 */ 76 | rand D1 p1; 77 | rand B1 p2; 78 | rand D1 p3; 79 | constraint f { soft p1.x < p2.x ; } 80 | constraint A2 { disable soft x; } // discard soft constraints 81 | endclass 82 | 83 | module my_module( 84 | input clk, // Clock 85 | input logic clk_en, // Clock Enable 86 | input rst_n, // Asynchronous reset active low; 87 | my_interface.master my_if ,// interface 88 | input my_pkg::my_type_in din, 89 | input [7:0] ctrl, // Control 90 | output reg [15:0] testbus , 91 | output my_pkg::my_type_out dout // output data 92 | ); 93 | 94 | logic [3:0] cnt; // counter 95 | logic [15:0] test; // tests comment 96 | 97 | reg [4:0] reg0; 98 | logic [15:0] t1,t2,t3; 99 | my_pkg::my_type data0; 100 | 101 | /* constraints */ 102 | constraint proto1; 103 | extern static constraint proto2; 104 | pure static constraint my_module::proto3; 105 | 106 | constraint my_module::proto2{ 107 | x inside {1, 0, 3}; 108 | } 109 | constraint c { s -> d == 0; } 110 | constraint order { solve s before d; } 111 | 112 | //------------------------------------------------------------------------------ 113 | // Process alignment 114 | //------------------------------------------------------------------------------ 115 | 116 | always_ff @(posedge clk or negedge rst_n) 117 | if(~rst_n) 118 | dout <= 0; 119 | else if(clk_en) begin 120 | dout <= ~dout; 121 | testbus <= ctrl[3:0]; 122 | end 123 | 124 | // case align 125 | always_comb begin : proc_comb 126 | case(my_if.sel) 127 | 16: test = din[16]; // blabla 128 | 7: test = din[7]; 129 | 3: begin 130 | case(cnt[1:0]) 131 | 0 : test = 4'h0; 132 | 1 : test = 5 + test; // test 133 | 2 : test = 6 - test;// blabl 134 | default : test = test[0] ? test : 4'b0000; 135 | endcase 136 | end 137 | 4 : 138 | if(test) begin 139 | test = test - 1; 140 | end else begin 141 | test = cnt; 142 | end 143 | default : test = ctrl; // default case 144 | endcase 145 | end 146 | 147 | // test more indentation level 148 | always_ff @(posedge rst_n ) begin : proc_ 149 | if(clk) begin 150 | test <= 0; 151 | testbus <= 0; 152 | cnt <= 4'h0; 153 | end else begin 154 | if(clk_en) 155 | if(test[0]) 156 | if(test[1]) begin 157 | cnt <= 0; 158 | if(test[2]) 159 | cnt <= 4'h2; // splitception o0 160 | end 161 | else begin 162 | testbus <= cnt; 163 | if(cnt[16]) 164 | cnt <= cnt + 1; 165 | end 166 | end 167 | end 168 | 169 | // Test module instantiation with and without param 170 | my_submodule i_sub ( 171 | .i0(din), 172 | .in1(my_pkg::test'(ctrl)), 173 | .clk_en(clk_en), 174 | .output_data(test) 175 | ); 176 | 177 | my_submodule i_sub_ast(.*); 178 | 179 | // test split statement: align on ( or = 180 | always @(ctrl, test, din, my_if.field0, 181 | cnt, my_if.field1, dout) 182 | // line Comment 183 | testbus = ((ctrl[0] == 1'b1) && my_if.field0) ? my_pkg::testbus_value0 : 184 | ((ctrl[1] == 1'b1) && my_if.field1) ? my_pkg::testbus_value1 : 185 | ((ctrl[2] == 1'b1) && dout[4]) ? cnt : 186 | my_pkg::testbus_default ; 187 | 188 | assign test = ctrl[7:0]; // assign_comment 189 | assign cnt = test + 4; 190 | 191 | assign testbus = {cnt,test}; 192 | 193 | my_param_submodule #( 194 | .PARAM0(1), 195 | .P4(my_pkg::P4) 196 | ) i_param_sub ( 197 | .input_0(din[1:0]), 198 | .in1(ctrl[7:0]), 199 | .clk_en(clk_en), 200 | .output_data(cnt[15:10]) 201 | ); 202 | 203 | // Function: abs 204 | // Returns absolute value of integer 205 | function integer abs(input integer value); 206 | if (value >=0 ) begin 207 | return value; 208 | end 209 | else 210 | return -value; 211 | endfunction : abs 212 | 213 | function a_test(); 214 | endfunction: a_test 215 | 216 | endmodule 217 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-19-functional-coverage.svh: -------------------------------------------------------------------------------- 1 | class a; 2 | covergroup g1 @(posedge clk); 3 | c: coverpoint color; 4 | endgroup 5 | 6 | covergroup g2 @(posedge clk); 7 | Hue: coverpoint pixel_hue; 8 | Offset: coverpoint pixel_offset; 9 | AxC: cross color, pixel_adr; // cross 2 variables 10 | all: cross color, Hue, Offset; // cross 1 variable and 2 coverpoints 11 | endgroup 12 | 13 | covergroup cov1 @m_z; // embedded covergroup 14 | coverpoint m_x; 15 | coverpoint m_y; 16 | bins 17 | binsof 18 | get_coverage(); 19 | endgroup 20 | 21 | class MC; 22 | logic [3:0] m_x; 23 | local logic m_z; 24 | bit m_e; 25 | 26 | covergroup cv1 @(posedge clk); 27 | coverpoint m_x; 28 | endgroup 29 | 30 | endclass 31 | 32 | covergroup cg ( ref int x , ref int y, input int c); 33 | coverpoint x; // creates coverpoint "x" covering the formal "x" 34 | x: coverpoint y; // INVALID: coverpoint label "x" already exists 35 | b: coverpoint y; // creates coverpoint "b" covering the formal "y" 36 | cx: coverpoint x; // creates coverpoint "cx" covering the formal "x" 37 | option.weight = c; // set weight of "cg" to value of formal "c" 38 | bit [7:0] d: coverpoint y[31:24]; // creates coverpoint "d" covering the 39 | // high order 8 bits of the formal "y" 40 | 41 | e: coverpoint x { 42 | option.weight = 2; // set the weight of coverpoint "e" 43 | } 44 | 45 | e.option.weight = 2; // INVALID use of "e", also syntax error 46 | cross x, y { // Creates implicit coverpoint "y" covering 47 | // the formal "y". Then creates a cross of 48 | // coverpoints "x", "y" 49 | option.weight = c; // set weight of cross to value of formal "c" 50 | } 51 | b: cross y, x; // INVALID: coverpoint label "b" already exists 52 | endgroup 53 | 54 | covergroup cg (ref int ra, input int low, int high ) @(posedge clk); 55 | coverpoint ra // sample variable passed by reference 56 | { 57 | bins good = { [low : high] }; 58 | bins bad[] = default; 59 | } 60 | endgroup 61 | 62 | covergroup cg @(posedge clk); 63 | coverpoint v_a 64 | { 65 | bins sa = (4 => 5 => 6), ([7:9],10=>11,12); 66 | bins sb[] = (4=> 5 => 6), ([7:9],10=>11,12); 67 | bins sc = (12 => 3 [-> 1]); 68 | bins allother = default sequence ; 69 | wildcard bins g12_15 = { 4'b11?? }; 70 | ignore_bins ignore_vals = {7,8}; 71 | ignore_bins ignore_trans = (1=>3=>5); 72 | illegal_bins bad_vals = {1,2,3}; 73 | illegal_bins bad_trans = (4=>5=>6); 74 | } 75 | endgroup 76 | 77 | bit [2:0] p1; // type expresses values in the range 0 to 7 78 | bit signed [2:0] p2; // type expresses values in the range –4 to 3 79 | 80 | covergroup g1 @(posedge clk); 81 | coverpoint p1 { 82 | bins b1 = { 1, [2:5], [6:10] }; 83 | bins b2 = { -1, [1:10], 15 }; 84 | } 85 | 86 | coverpoint p2 { 87 | bins b3 = {1, [2:5], [6:10] }; 88 | bins b4 = { -1, [1:10], 15 }; 89 | } 90 | endgroup 91 | 92 | covergroup cov3 @(posedge clk); 93 | A: coverpoint a_var { bins yy[] = { [0:9] }; } 94 | CC: cross b_var, A; 95 | endgroup 96 | 97 | int i,j; 98 | covergroup ct; 99 | coverpoint i { bins i[] = { [0:1] }; } 100 | coverpoint j { bins j[] = { [0:1] }; } 101 | x1: cross i,j; 102 | x2: cross i,j { 103 | bins i_zero = binsof(i) intersect { 0 }; 104 | } 105 | endgroup 106 | 107 | covergroup cg; 108 | coverpoint a 109 | { 110 | bins low[] = {[0:127]}; 111 | bins high = {[128:255]}; 112 | } 113 | coverpoint b 114 | { 115 | bins two[] = b with (item % 2 == 0) 116 | bins three[] = b with (item % 3 == 0) 117 | } 118 | X: cross a,b 119 | { 120 | bins apple = X with (a+b < 257) matches 127; 121 | bins cherry = (( binsof(b) intersect {[0:50]} && binsof(a.low) intersect {[0:50]}) with (a==b)) ; 122 | bins plum = (binsof(b.two) with (b > 12) || binsof(a.low) with (a & b & mask)); 123 | } 124 | endgroup 125 | endclass 126 | 127 | module mod_m; 128 | logic [31:0] a, b; 129 | covergroup cg(int cg_lim); 130 | coverpoint a; 131 | coverpoint b; 132 | aXb : cross a, b 133 | { 134 | function CrossQueueType myFunc1(int f_lim); 135 | for (int i = 0; i < f_lim; ++i) 136 | myFunc1.push_back('{i,i}); 137 | endfunction 138 | 139 | bins one = myFunc1(cg_lim); 140 | bins two = myFunc2(cg_lim); 141 | 142 | function CrossQueueType myFunc2(logic [31:0] f_lim); 143 | for (logic [31:0] i = 0; i < f_lim; ++i) 144 | myFunc2.push_back('{2*i,2*i}); 145 | endfunction 146 | } 147 | endgroup 148 | cg cg_inst = new(3); 149 | endmodule 150 | 151 | class b; 152 | covergroup yy; 153 | cross a, b 154 | { 155 | ignore_bins ignore = binsof(a) intersect { 5, [1:3] }; 156 | illegal_bins illegal = binsof(y) intersect {bad}; 157 | } 158 | endgroup 159 | endclass b; 160 | 161 | module a; 162 | g1.option.comment = "Here is a comment set for the instance g1"; 163 | g1.a.option.weight = 3; // Set weight for coverpoint "a" of instance g1 164 | 165 | option.at_least 166 | option.auto_bin_max 167 | option.comment 168 | option.cross_num_print_missing 169 | option.detect_overlap 170 | option.goal 171 | option.name 172 | option.per_instance 173 | option.strobe 174 | option.weight 175 | 176 | type_option.at_least 177 | type_option.auto_bin_max 178 | type_option.comment 179 | type_option.cross_num_print_missing 180 | type_option.detect_overlap 181 | type_option.goal 182 | type_option.name 183 | type_option.per_instance 184 | type_option.strobe 185 | type_option.weight 186 | 187 | option.comment 188 | option.distribute_first 189 | option.goal 190 | option.merge_instances 191 | option.strobe 192 | option.weight 193 | with 194 | type_option.comment 195 | type_option.distribute_first 196 | type_option.goal 197 | type_option.merge_instances 198 | type_option.strobe 199 | type_option.weight 200 | 201 | covergroup p_cg with function sample(bit a, int x); 202 | coverpoint x; 203 | cross x, a; 204 | endgroup : p_cg 205 | 206 | p_cg cg1 = new; 207 | 208 | property p1; 209 | int x; 210 | @(posedge clk)(a, x = b) ##1 (c, cg1.sample(a, x)); 211 | endproperty : p1 212 | 213 | c1: cover property (p1); 214 | 215 | function automatic void F(int j); 216 | bit d; 217 | ... 218 | cg1.sample( d, j ); 219 | endfunction 220 | 221 | covergroup C1 (int v) with function sample (int v, bit b); // error (v) 222 | coverpoint v; 223 | option.per_instance = b;// error: b may only designate a coverpoint 224 | option.weight = v; // error: v is ambiguous 225 | endgroup 226 | 227 | $set_coverage_db_name(); 228 | endmodule 229 | -------------------------------------------------------------------------------- /snippets/uvm_macros.json: -------------------------------------------------------------------------------- 1 | { 2 | // REPORT MACROS 3 | "uvm_macro_info": { 4 | "prefix": "uvm_info", 5 | "body": ["`uvm_info(${1|get_name(),get_full_name(),\"\"|}, \"${2:message}\", ${3|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})\n$0"], 6 | "description": "Calls uvm_report_info if VERBOSITY is lower than the configured verbosity of the associated reporter. ID is given as the message tag and message is given as the message text. The file and line are also sent to the uvm_report_info call." 7 | }, 8 | "uvm_macro_warning": { 9 | "prefix": "uvm_warning", 10 | "body": ["`uvm_warning(${1|get_name(),get_full_name(),\"\"|}, \"${2:message}\")\n$0"], 11 | "description": "Calls uvm_report_warning with a verbosity of UVM_NONE. ID is given as the message tag and message is given as the message text. The file and line are also sent to the uvm_report_warning call." 12 | }, 13 | "uvm_macro_error": { 14 | "prefix": "uvm_error", 15 | "body": ["`uvm_error(${1|get_name(),get_full_name(),\"\"|}, \"${2:message}\")\n$0"], 16 | "description": "Calls uvm_report_error with a verbosity of UVM_NONE. ID is given as the message tag and message is given as the message text. The file and line are also sent to the uvm_report_error call." 17 | }, 18 | "uvm_macro_fatal": { 19 | "prefix": "uvm_fatal", 20 | "body": ["`uvm_fatal(${1|get_name(),get_full_name(),\"\"|}, \"${2:message}\")\n$0"], 21 | "description": "Calls uvm_report_fatal with a verbosity of UVM_NONE. ID is given as the message tag and message is given as the message text. The file and line are also sent to the uvm_report_fatal call." 22 | }, 23 | 24 | // FACTORY RELATED MACROS 25 | "uvm_macro_object_utils": { 26 | "prefix": "uvm_object_utils", 27 | "context": "meta.class.systemverilog", 28 | "body": ["`uvm_object_utils(${1:type})\n$0"], 29 | "description": "The utils macros define the infrastructure needed to enable the object/component for correct factory operation." 30 | }, 31 | "uvm_macro_object_param_utils": { 32 | "prefix": "uvm_object_param_utils", 33 | "context": "meta.class.systemverilog", 34 | "body": ["`uvm_object_param_utils(${1:type})\n$0"], 35 | "description": "The utils macros define the infrastructure needed to enable the object/component for correct factory operation." 36 | }, 37 | "uvm_macro_component_utils": { 38 | "prefix": "uvm_component_utils", 39 | "context": "meta.class.systemverilog", 40 | "body": ["`uvm_component_utils(${1:type})\n$0"], 41 | "description": "The utils macros define the infrastructure needed to enable the object/component for correct factory operation." 42 | }, 43 | "uvm_macro_component_param_utils": { 44 | "prefix": "uvm_component_param_utils", 45 | "context": "meta.class.systemverilog", 46 | "body": ["`uvm_component_param_utils(${1:type})\n$0"], 47 | "description": "The utils macros define the infrastructure needed to enable the object/component for correct factory operation." 48 | }, 49 | "uvm_macro_object_registry": { 50 | "prefix": "uvm_object_registry", 51 | "body": ["`uvm_object_registry(${1:type}, \"${2:lookup_string}\")\n$0"], 52 | "description": "Registers a uvm_object-based class type and lookup string lookup_string with the factory. lookup_string typically is the name of the class in quotes." 53 | }, 54 | "uvm_macro_component_registry": { 55 | "prefix": "uvm_component_registry", 56 | "body": ["`uvm_component_registry(${1:type}, \"${2:lookup_string}\")\n$0"], 57 | "description": "Registers a uvm_component-based class type and lookup string lookup_string with the factory. lookup_string typically is the name of the class in quotes." 58 | }, 59 | 60 | // CONFIG_DB ACCESSORS 61 | "uvm_config_db_set": { 62 | "prefix": "uvm_config_db_set", 63 | "body": ["uvm_config_db#(${1:type})::set(${2:contxt}, ${3:inst_name}, ${4:field_name}, ${5:value});\n$0"], 64 | "description": "Create a new or update an existing configuration setting for field_name in inst_name from cntxt." 65 | }, 66 | "uvm_config_db_get": { 67 | "prefix": "uvm_config_db_get", 68 | "body": ["uvm_config_db#(${1:type})::get(${2:contxt}, ${3:inst_name}, ${4:field_name}, ${5:value});\n$0"], 69 | "description": "Get the value for field_name in inst_name, using component cntxt as the starting search point." 70 | }, 71 | "uvm_config_db_get_guarded": { 72 | "prefix": "uvm_config_db_get_guarded", 73 | "body": [ 74 | "assert (uvm_config_db#(${1:type})::get(${2:contxt}, ${3:inst_name}, ${4:field_name}, ${5:value})) begin", 75 | "\t`uvm_info(${7:get_name()}, \"${8:${4/([\"])//gi}} has been found in ConfigDB.\", ${9:UVM_LOW})", 76 | "end else `uvm_fatal($7, \"$8 cannot be found in ConfigDB!\")\n$0" 77 | ], 78 | "description": "Get the value for field_name in inst_name, using component cntxt as the starting search point." 79 | }, 80 | "uvm_config_db_exists": { 81 | "prefix": "uvm_config_db_exists", 82 | "body": ["uvm_config_db#(${1:type})::exists(${2:contxt}, ${3:inst_name}, ${4:field_name}, ${5:});\n$0"], 83 | "description": "Check if a value for field_name is available in inst_name, using component cntxt as the starting search point." 84 | }, 85 | "uvm_config_db_wait_modified": { 86 | "prefix": "uvm_config_db_wait_modified", 87 | "body": ["uvm_config_db#(${1:type})::wait_modified(${2:contxt}, ${3:inst_name}, ${4:field_name});\n$0"], 88 | "description": "Wait for a configuration setting to be set for field_name in cntxt and inst_name. The task blocks until a new configuration setting is applied that effects the specified field." 89 | }, 90 | 91 | // TLM MACROS 92 | "uvm_macro_analysis_imp_decl": { 93 | "prefix": "uvm_macro_analysis_imp_decl", 94 | "context": "meta.class.systemverilog", 95 | "body": ["`uvm_analysis_imp_decl(${1:suffix})\n$0"], 96 | "description": "The `uvm_analysis_imp_decl allows for a component to support input from many places." 97 | }, 98 | 99 | // MISC MACROS 100 | "uvm_macro_record_field": { 101 | "prefix": "uvm_macro_record_field", 102 | "context": "meta.function.systemverilog", 103 | "body": ["`uvm_record_field(\"${1:property_id}\", ${2:property_name});\n$0"], 104 | "description": "Macro for recording name-value pairs into a transaction recording database." 105 | }, 106 | 107 | // UVM FACTORY INSTANTIATION MACROS 108 | "uvm_object_factory_instantiation": { 109 | "context": "meta.class-body.systemverilog", 110 | "prefix": "uvm_factory_instantiation_object", 111 | "body": [ 112 | "${1:} = ${2:}::type_id::create(.name(\"$1\"), .contxt(get_full_name()));\n" 113 | ] 114 | }, 115 | "uvm_component_factory_instantiation": { 116 | "context": "meta.class-body.systemverilog", 117 | "prefix": "uvm_factory_instantation_component", 118 | "body": [ 119 | "${1:} = ${2:}::type_id::create(.name(\"$1\"), .parent(this));\n" 120 | ] 121 | }, 122 | "uvm_factory_inst_override": { 123 | "context": "meta.class-body.systemverilog", 124 | "prefix": "uvm_factory_inst_override", 125 | "body": [ 126 | "${1:}::type_id::set_inst_override(${2:}::get_type(), {get_full_name(), \"${3:*}\"});\n" 127 | ] 128 | }, 129 | "uvm_factory_type_override": { 130 | "context": "meta.class-body.systemverilog", 131 | "prefix": "uvm_factory_type_override", 132 | "body": [ 133 | "${1:}::type_id::set_type_override(${2:}::get_type());\n" 134 | ] 135 | } 136 | } 137 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-06-types.svh: -------------------------------------------------------------------------------- 1 | module wrapper(); 2 | 3 | // user-defined data type T 4 | typedef struct { 5 | real field1; 6 | bit field2; 7 | } T; 8 | 9 | // user-defined resolution function Tsum 10 | function automatic T Tsum (input T driver[]); 11 | Tsum.field1 = 0.0; 12 | foreach (driver[i]) 13 | Tsum.field1 += driver[i].field1; 14 | endfunction 15 | 16 | nettype T wT; // an unresolved nettype wT whose data type is T 17 | // a nettype wTsum whose data type is T and 18 | // resolution function is Tsum 19 | nettype T wTsum with Tsum; 20 | // user-defined data type TR 21 | typedef real TR[5]; 22 | // an unresolved nettype wTR whose data type 23 | // is an array of real 24 | nettype TR wTR; 25 | // declare another name nettypeid2 for nettype wTsum 26 | nettype wTsum nettypeid2; 27 | 28 | // typedefs 29 | 30 | interface intf_i; 31 | typedef int data_t; 32 | endinterface 33 | 34 | module sub(intf_i p); 35 | typedef p.data_t my_data_t; 36 | my_data_t data; 37 | // type of 'data' will be int when connected to interface above 38 | endmodule 39 | 40 | // Correct: IDLE=0, XX='x, S1=1, S2=2 41 | enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next; 42 | // Syntax error: IDLE=0, XX='x, S1=??, S2=?? 43 | enum integer {IDLE, XX='x, S1, S2} state, next; 44 | // Correct declaration - bronze and gold are unsized 45 | enum bit [3:0] {bronze='h3, silver, gold='h5} medal2; 46 | // Correct declaration - bronze and gold sizes are redundant 47 | enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3; 48 | // Error in the bronze and gold member declarations 49 | enum bit [3:0] {bronze=5'h13, silver, gold=3'h5} medal4; 50 | 51 | // matching and equivalent 52 | typedef bit node; // 'bit' and 'node' are matching types 53 | typedef type1 type2; // 'type1' and 'type2' are matching types 54 | 55 | struct packed {int A; int B;} AB1, AB2; // AB1, AB2 have matching types 56 | struct packed {int A; int B;} AB3; // the type of AB3 does 57 | 58 | typedef bit signed [7:0] BYTE; // matches the byte type 59 | typedef bit signed [0:7] ETYB; // does not match the byte type 60 | 61 | typedef byte MEM_BYTES [256]; 62 | typedef bit signed [7:0] MY_MEM_BYTES [256]; // MY_MEM_BYTES matches 63 | // MEM_BYTES 64 | typedef logic [1:0] [3:0] NIBBLES; 65 | typedef logic [7:0] MY_BYTE; // MY_BYTE and NIBBLES are not matching types 66 | typedef logic MD_ARY [][2:0]; 67 | typedef logic MD_ARY_TOO [][0:2]; // Does not match MD_ARY 68 | 69 | typedef byte signed MY_CHAR; // MY_CHAR matches the byte type 70 | 71 | typedef bit signed [7:0] BYTE; // equivalent to the byte type 72 | typedef struct packed signed {bit[3:0] a, b;} uint8; 73 | // equivalent to the byte type 74 | bit [9:0] A [0:5]; 75 | bit [size-1:0] A [value-2:5]; 76 | bit [1:10] B [6]; 77 | typedef bit [10:1] uint10; 78 | uint10 C [6:1]; // A, B and C have equivalent types 79 | typedef int anint [0:0]; // anint is not type equivalent to int 80 | 81 | // Illegal conversion from 24-bit struct to 32 bit int - compile time error 82 | struct {bit[7:0] a; shortint b;} a; 83 | int b = int'(a); 84 | // Illegal conversion from 20-bit struct to int (32 bits) - run time error 85 | struct {bit a[$]; shortint b;} a = {{1,2,3,4},67}; 86 | int b = int'(a); 87 | // Illegal conversion from int (32 bits) to struct dest_t (25 or 33 bits), 88 | // compile time error 89 | typedef struct {byte a[$]; bit b;} dest_t; 90 | int a; 91 | dest_t b = dest_t'(a); 92 | 93 | 94 | this.member.function(); 95 | module testmodule(); 96 | this.member.function(); 97 | endmodule 98 | 99 | // structures 100 | struct { bit [7:0] opcode; bit [23:0] addr; }IR; // anonymous structure 101 | // defines variable IR 102 | IR.opcode = 1; // set field in IR. 103 | typedef struct { 104 | bit [7:0] opcode; 105 | bit [23:0] addr; 106 | } instruction_t; // named structure type 107 | instruction_t IR; // define variable 108 | 109 | struct packed signed { 110 | int a; 111 | shortint b; 112 | byte c; 113 | bit [7:0] d; 114 | } pack1; // signed, 2-state 115 | 116 | struct packed unsigned { 117 | time a; 118 | integer b; 119 | logic [31:0] c; 120 | } pack2; // unsigned, 4-state 121 | 122 | typedef union { int i; shortreal f; } num; // named union type 123 | num n; 124 | n.f = 0.0; // set n in floating point format 125 | typedef struct { 126 | bit isfloat; 127 | union { int i; shortreal f; } n; // anonymous union type 128 | } tagged_t; // named structure 129 | 130 | typedef union packed { // default unsigned 131 | s_atmcell acell; 132 | bit [423:0] bit_slice; 133 | bit [52:0][7:0] byte_slice; 134 | } u_atmcell; 135 | 136 | const'(x) 137 | $cast(ax, int) 138 | endmodule: wrapper 139 | 140 | virtual class C#(parameter type T = logic, parameter SIZE = 1); 141 | typedef logic [SIZE-1:0] t_vector; 142 | typedef T t_array [SIZE-1:0]; 143 | typedef struct { 144 | t_vector m0 [2*SIZE-1:0]; 145 | t_array m1; 146 | } t_struct; 147 | endclass 148 | 149 | //--- 150 | package p1; 151 | typedef struct {int A;} t_1; 152 | endpackage 153 | 154 | typedef struct {int A;} t_2; 155 | 156 | module sub(); 157 | import p1::t_1; 158 | parameter type t_3 = int; 159 | parameter type t_4 = int; 160 | 161 | typedef struct {int A;} t_5; 162 | 163 | t_1 v1; t_2 v2; t_3 v3; t_4 v4; t_5 v5; 164 | endmodule 165 | 166 | module top(); 167 | typedef struct {int A;} t_6; 168 | 169 | sub #(.t_3(t_6)) s1 (); 170 | sub #(.t_3(t_6)) s2 (); 171 | 172 | initial begin 173 | s1.v1 = s2.v1; // legal - both types from package p1 (rule 8) 174 | s1.v2 = s2.v2; // legal - both types from $unit (rule 4) 175 | s1.v3 = s2.v3; // legal - both types from top (rule 2) 176 | s1.v4 = s2.v4; // legal - both types are int (rule 1) 177 | s1.v5 = s2.v5; // illegal - types from s1 and s2 (rule 4) 178 | end 179 | endmodule 180 | //--- 181 | 182 | module wrapper(); 183 | string SA[10], qs[$]; 184 | int IA[int], qi[$]; 185 | // Find all items greater than 5 186 | qi = IA.find( x ) with (x.find>5); 187 | qi = IA.find(x); // shall be an error 188 | // Find indices of all items equal to 3 189 | qi = IA.find_index with ( item == 3 ); 190 | // Find first item equal to Bob 191 | qs = SA.find_first with ( item == "Bob" ); 192 | // Find last item equal to Henry 193 | qs = SA.find_last( y ) with ( y == "Henry" ); 194 | // Find index of last item greater than Z 195 | qi = SA.find_last_index( s ) with ( s > "Z" ); 196 | // Find smallest item 197 | qi = IA.min; 198 | // Find string with largest numerical value 199 | qs = SA.max with ( item.atoi ); 200 | // Find all unique string elements 201 | qs = SA.unique; 202 | // Find all unique strings in lowercase 203 | qs = SA.unique( s ) with ( s.tolower ); 204 | 205 | string s[] = { "hello", "sad", "world" }; 206 | s.reverse; // s becomes { "world", "sad", "hello" }; 207 | int q[$] = { 4, 5, 3, 1 }; 208 | q.sort; // q becomes { 1, 3, 4, 5 } 209 | 210 | struct { byte red, green, blue; } c [512]; 211 | c.sort with ( item.red ); // sort c using the red field only 212 | c.sort( x ) with ( {x.blue, x.green} ); // sort by blue then green 213 | 214 | byte b[] = { 1, 2, 3, 4 }; 215 | int y; 216 | y = b.sum ; // y becomes 10 => 1 + 2 + 3 + 4 217 | y = b.product ; // y becomes 24 => 1 * 2 * 3 * 4 218 | y = b.xor with ( item + 4 ); // y becomes 12 => 5 ^ 6 ^ 7 ^ 8 219 | logic [7:0] m [2][2] = '{ '{5, 10}, '{15, 20} }; 220 | int y; 221 | y = m.sum with (item.sum with (item)); // y becomes 50 => 5+10+15+20 222 | logic bit_arr_t [1024]; 223 | int y; 224 | y = bit_arr_t.sum with ( int'(item) ); // forces result to be 32-bit 225 | 226 | int arr[]; 227 | int q[$]; 228 | ... 229 | // find all items equal to their position (index) 230 | q = arr.find with ( item == item.index ); 231 | endmodule -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-02.svh: -------------------------------------------------------------------------------- 1 | // SYNTAX TEST "SystemVerilog.sublime-syntax" 2 | 3 | `define my_macro ; 4 | // <- constant.other.preprocessor 5 | // ^ entity.name.type.define 6 | `my_macro 7 | // <- constant.other.define 8 | 9 | extern protected virtual function int send(); 10 | endfunction 11 | 12 | 13 | /*------------------------------------------------------------------------------ 14 | -- Test interface definition with modport 15 | ------------------------------------------------------------------------------*/ 16 | 17 | interface my_interface1; 18 | // <- keyword.control 19 | // ^ entity.name.type.class 20 | logic one; 21 | // ^ storage.type 22 | logic two; 23 | 24 | modport sys ( 25 | // ^ keyword.control 26 | // ^ support.function.generic 27 | input one, 28 | // ^ support.type 29 | output two 30 | // ^ support.type 31 | ); 32 | endinterface /* my_interface1 */ 33 | // <- keyword.control 34 | // ^ comment.block 35 | 36 | // Interface with indentation 37 | interface my_interface2; 38 | // ^ keyword.control 39 | // ^ entity.name.type.class 40 | logic one; 41 | logic two; 42 | 43 | modport sys ( 44 | inout one, 45 | // ^ support.type 46 | output two 47 | ); 48 | 49 | endinterface 50 | 51 | /*------------------------------------------------------------------------------ 52 | -- Typedef 53 | ------------------------------------------------------------------------------*/ 54 | typedef logic [31:0] t_queue_of_levels [$]; 55 | typedef logic [31:0] queue_of_levels [$]; 56 | typedef logic [31:0] queue_of_levels_t [$]; 57 | // <- keyword.control 58 | // ^ storage.type 59 | // ^ constant.numeric.decimal 60 | // ^ keyword.operator 61 | // ^ entity.name.type 62 | // ^ keyword.operator 63 | 64 | typedef my_module#(16) t_my_module_16; 65 | // ^ keyword.control 66 | // ^ storage.type 67 | // ^ keyword.operator 68 | // ^ constant.numeric.decimal 69 | // ^ entity.name.type 70 | 71 | typedef logic[7:0] at_byte; 72 | // ^ keyword.control 73 | // ^ storage.type 74 | // ^ constant.numeric.decimal 75 | // ^ keyword.operator 76 | // ^ entity.name.type 77 | 78 | 79 | /*------------------------------------------------------------------------------ 80 | -- Module declaration 81 | ------------------------------------------------------------------------------*/ 82 | 83 | module my_module 84 | // <- keyword.control 85 | // ^ entity.name.type 86 | import my_pkg::*; 87 | // ^ keyword.control 88 | // ^ support.type.scope 89 | // ^ keyword.operator.scope 90 | // ^ keyword.operator 91 | #(parameter int P1=0, 92 | //^ keyword.operator 93 | // ^ keyword.other 94 | // ^ storage.type 95 | // ^ constant.other.net 96 | logic [15:0] P2 = 16'b0000_1111, 97 | // ^ constant.other.net 98 | // ^ constant.numeric 99 | // ^ constant.numeric 100 | real P3 = my_pkg::pp, 101 | // ^ storage.type 102 | // ^ support.type 103 | ) 104 | ( 105 | my_interface1.sys if1, 106 | // ^ storage.type.interface 107 | // ^ support.modport 108 | my_interface2 if2, // Coment if2 109 | // ^ storage.type.interface 110 | // ^ comment.line 111 | input logic clk, /* comment clk */ 112 | // ^ comment.block 113 | output wire my_out 114 | ); 115 | 116 | timeunit 1ns; 117 | // ^ keyword.control 118 | // ^ constant.numeric.time 119 | timeprecision 1fs; 120 | // <- keyword.control 121 | // ^ constant.numeric.time 122 | 123 | /*------------------------------------------------------------------------------ 124 | -- User Defined type 125 | ------------------------------------------------------------------------------*/ 126 | t_byte b0, // Comments 127 | // ^ storage.type.userdefined 128 | b1; 129 | local t_byte b2 = 8'hFF; 130 | // <- keyword.other 131 | // ^ storage.type.userdefined 132 | // ^ keyword.operator 133 | // ^ constant.numeric 134 | 135 | mytype [3:0][4][`MACRO*4] myvar3[PARAM-1:`TEST/4]; // userdefined type with packed/unpacked 136 | mytype [3:0][4][`MACRO*4] myvar3[PARAM-1:`TEST/4]; // userdefined type with packed/unpacked 137 | // <- storage.type.userdefined 138 | 139 | logic [3:0] sig_logic = 4'shC; 140 | 141 | /*------------------------------------------------------------------------------ 142 | -- PSL 143 | ------------------------------------------------------------------------------*/ 144 | // psl a_mypsl_assert: assert never {sig_logic!=4'hX}; 145 | // <- meta.psl 146 | 147 | /*------------------------------------------------------------------------------ 148 | -- Instantiation of interface, module 149 | ------------------------------------------------------------------------------*/ 150 | my_interface1#(1) if1(clk,rst_n); 151 | virtual my_interface1#(3,4) if2; 152 | 153 | my_module i_my_module 154 | ( 155 | .if1(if1), 156 | .if2(if2), 157 | .clk(`MYMACRO(5).clk), 158 | // ^ support.function.port 159 | // ^ constant.other.define 160 | // ^ -support.function.port 161 | .my_out(my_out), 162 | ); 163 | 164 | parameter 165 | my_module.test_param = 23'h44; 166 | 167 | localparam mytype myvar = mytype'(MY_INIT/4+8); 168 | localparam myvar1 = MY_INIT1; 169 | localparam logic [1:0] myvar2 = MY_INIT2; 170 | 171 | /*------------------------------------------------------------------------------ 172 | -- Structure / Typedef 173 | ------------------------------------------------------------------------------*/ 174 | typedef struct {logic a; int b; bit [3:0] c;} mystruct; 175 | protected const mystruct c_var = '{a:0,b:1,c:4'hD}; 176 | // ^ support.function.field 177 | 178 | /*------------------------------------------------------------------------------ 179 | -- Task & functions 180 | ------------------------------------------------------------------------------*/ 181 | 182 | task connect(virtual nfc_ip_top_if dut_if); 183 | // <- keyword.control 184 | // ^ entity.name.function 185 | // ^ keyword.other 186 | // ^ storage.type 187 | endtask 188 | 189 | 190 | function void my_func(ref logic d, input int din, 191 | input bit[3:0] d, 192 | output bit[$clog(kk)-1:0] d2, 193 | // ^ support.function.systemverilog 194 | output dout); 195 | $display("d=%0d",d); 196 | endfunction : my_func 197 | 198 | function automatic integer CLOGB2; 199 | endfunction 200 | 201 | /*------------------------------------------------------------------------------ 202 | -- Invalid syntax 203 | ------------------------------------------------------------------------------*/ 204 | [[(([()]))]] 205 | ())] 206 | []]) 207 | (])) 208 | [)]] 209 | // <- -invalid.illegal 210 | // <- invalid.illegal 211 | // <- -invalid.illegal 212 | // <- invalid.illegal 213 | // <- -invalid.illegal 214 | // <- invalid.illegal 215 | // <- -invalid.illegal 216 | // <- invalid.illegal 217 | 218 | /*------------------------------------------------------------------------------ 219 | -- MISC 220 | ------------------------------------------------------------------------------*/ 221 | 222 | nettype t_mytype mytype with myresolve; 223 | // ^ keyword.control 224 | // ^ storage.type 225 | // ^ entity.name.type 226 | // ^ keyword.control 227 | // ^ support.function.resolve 228 | 229 | 230 | fork 231 | join_any 232 | 233 | fork : f_label 234 | begin : b_label 235 | 236 | end : b_label 237 | join : f_label 238 | 239 | covergroup cg @(e); 240 | option.per_instance = 1; 241 | cp : coverpoint cp_name { 242 | bins b01 = {[0:1]}; 243 | bins b23 = {[2:3]}; 244 | bins others = default; 245 | option.comment = "comment"; 246 | option.at_least = 1_000; // 247 | } 248 | endgroup 249 | 250 | always_ff @(posedge clk or negedge rst_n) begin : proc_ 251 | if (~rst_n) 252 | a <= '0; 253 | else if (en) 254 | a <= a + b; 255 | end 256 | 257 | 258 | generate 259 | for (int i = 0; i < count; i++) begin 260 | some #(1,2,3) i ( 261 | .a(a), 262 | b, 263 | c 264 | ); 265 | end 266 | endgenerate 267 | 268 | 269 | -------------------------------------------------------------------------------- /snippets/sv_containers.json: -------------------------------------------------------------------------------- 1 | { 2 | "sv_module": { 3 | "prefix": "sv_module", 4 | "body": [ 5 | "// Module: $1", 6 | "//", 7 | "module ${1:$TM_FILENAME_BASE}", 8 | "\t/* package imports */", 9 | "\t#(", 10 | "\t\t${2:}", 11 | "\t)(", 12 | "\t\t${3:}", 13 | "\t);\n", 14 | "\t$0", 15 | "endmodule: $1\n" 16 | ], 17 | "description": "Basic SystemVerilog module construct." 18 | }, 19 | "sv_interface": { 20 | "prefix": "sv_interface", 21 | "body": [ 22 | "// Interface: $1", 23 | "//", 24 | "interface ${1:$TM_FILENAME_BASE}", 25 | "\t/* package imports */", 26 | "\t#(", 27 | "\t\t${2:}", 28 | "\t)(", 29 | "\t\t${3:}", 30 | "\t);\n", 31 | "\t$0", 32 | "endinterface: $1\n" 33 | ], 34 | "description": "Basic SystemVerilog interface construct." 35 | }, 36 | "sv_package": { 37 | "prefix": "sv_package", 38 | "body": [ 39 | "// Package: $1", 40 | "//", 41 | "package ${1:$TM_FILENAME_BASE};", 42 | "\t// Group: Typedefs", 43 | "\t$2\n", 44 | "\t// Group: Parameters", 45 | "\t$3\n", 46 | "\t$0", 47 | "endpackage: $1\n" 48 | ], 49 | "description": "Basic SystemVerilog package construct." 50 | }, 51 | "sv_class": { 52 | "prefix": "sv_class", 53 | "body": [ 54 | "// Class: $1", 55 | "//", 56 | "class ${1:$TM_FILENAME_BASE};", 57 | "\t// Group: Variables\n\n", 58 | "\t// Group: Constraints\n\n", 59 | "\t// Group: Functions\n", 60 | "\t// Constructor: new", 61 | "\tfunction new(string name = \"$1\");", 62 | "\tendfunction: new", 63 | "\t$0\n", 64 | "endclass: $1\n" 65 | ], 66 | "description": "SV class template" 67 | }, 68 | "sv_typedef": { 69 | "prefix": "sv_typedef", 70 | "body": [ 71 | "// Typedef: $3", 72 | "// --- Prototype ---", 73 | "// typedef $1 $2$3", 74 | "// ---", 75 | "typedef ${1:enum} ${2:#() }${3:};", 76 | "$0" 77 | ], 78 | "description": "SV Typedef construct for NaturalDocs" 79 | }, 80 | 81 | "sv_guard_ifndef": { 82 | "prefix": "sv_guard_ifndef", 83 | "body": [ 84 | "`ifndef __${1:${TM_FILENAME/((\\w*)([\\.\\s])?)/${2:/upcase}${3:+_}/g}}", 85 | "`define __$1", 86 | "\n$0\n", 87 | "`endif\n" 88 | ], 89 | "description": "Basic SystemVerilog guard ifndef-define-endif construct." 90 | }, 91 | 92 | // Constraints 93 | "sv_extern_constraint": { 94 | "context": ["meta.class.systemverilog"], 95 | "prefix": "extern_constraint", 96 | "body": [ 97 | "// Constraint: $1", 98 | "extern constraint $1;\n$0" 99 | ], 100 | "description": "Constraint declaration stub." 101 | }, 102 | "sv_constraint_block": { 103 | "context": [ 104 | "meta.class.systemverilog", 105 | "source.systemverilog" 106 | ], 107 | "prefix": "constraint_block", 108 | "body": [ 109 | "constraint ${1:$TM_FILENAME_BASE}${2:::}$3 {", 110 | "\t/* solve order constraints */\n", 111 | "\t/* rand variable constraints */", 112 | "\t$0", 113 | "}\n" 114 | ], 115 | "description": "Constraint block template." 116 | }, 117 | 118 | // Coverage 119 | "sv_covergroup": { 120 | "prefix": "sv_covergroup", 121 | "body": [ 122 | "// Covergroup: cg_$1", 123 | "//", 124 | "covergroup cg_${1:identifier} (${2:port_list}) ${3:@(coverage_event)};", 125 | "\t$0", 126 | "endgroup: cg_$1" 127 | ], 128 | "description": "Basic SystemVerilog covergroup template." 129 | }, 130 | "sv_covergroup_options": { 131 | "prefix": "sv_covergroup_options", 132 | "body": [ 133 | "// option.name = \"\";", 134 | "// option.at_least = ;", 135 | "// option.auto_bin_max = ;", 136 | "// option.comment = \"\";", 137 | "// option.cross_num_print_missing = ;", 138 | "// option.detect_overlap = ;", 139 | "// option.get_inst_coverage = ;", 140 | "// option.goal = ;", 141 | "// option.per_instance = ;", 142 | "// option.weight = ;", 143 | "$0" 144 | ], 145 | "description": "Covergroup option block template." 146 | }, 147 | "sv_covergroup_type_options": { 148 | "prefix": "sv_covergroup_type_options", 149 | "body": [ 150 | "// type_option.comment = \"\";", 151 | "// type_option.distribute_first = ;", 152 | "// type_option.goal = ;", 153 | "// type_option.merge_instances = ;", 154 | "// type_option.strobe = ;", 155 | "// type_option.weight = ;", 156 | "$0" 157 | ], 158 | "description": "Covergroup type_options block template." 159 | }, 160 | "sv_coverpoint": { 161 | "prefix": "sv_coverpoint", 162 | "body": [ 163 | "// Coverpoint: cp_$1", 164 | "cp_${1:cover_point_identifier}: coverpoint ${2:covered_expression} iff (${3:1}) {", 165 | "\t$0", 166 | "}\n" 167 | ], 168 | "description": "Coverage point template." 169 | }, 170 | "sv_coverpoint_options": { 171 | "prefix": "sv_coverpoint_options", 172 | "body": [ 173 | "// option.at_least = ;", 174 | "// option.auto_bin_max = ;", 175 | "// option.comment = \"\";", 176 | "// option.detect_overlap = ;", 177 | "// option.goal = ;", 178 | "// option.weight = ;", 179 | "$0" 180 | ], 181 | "description": "Coverage point option block template." 182 | }, 183 | "sv_coverpoint_type_options": { 184 | "prefix": [ 185 | "sv_coverpoint_type_options", 186 | "sv_cross_type_options" 187 | ], 188 | "body": [ 189 | "// type_option.comment = \"\";", 190 | "// type_option.goal = ;", 191 | "// type_option.weight = ;", 192 | "$0" 193 | ], 194 | "description": "Coverage point and cross coverage type_options block template." 195 | }, 196 | "sv_covercross": { 197 | "prefix": "sv_covercross", 198 | "body": [ 199 | "// Cross: cx_$1", 200 | "cx_${1:cross_identifier}: cross ${2:list_of_cross_items} iff (${3:1}) {", 201 | "\t$0", 202 | "}\n" 203 | ], 204 | "description": "Cross coverage template." 205 | }, 206 | "sv_covercross_options": { 207 | "prefix": "sv_covercross_options", 208 | "body": [ 209 | "// option.at_least = ;", 210 | "// option.comment = \"\";", 211 | "// option.cross_num_print_missing = ;", 212 | "// option.goal = ;", 213 | "// option.weight = ;", 214 | "$0" 215 | ], 216 | "description": "Cross coverage option block template." 217 | } 218 | 219 | // Separators 220 | "sv_separator_block": { 221 | "prefix": "sv_separator_block", 222 | "body": [ 223 | "/*", 224 | "** $0", 225 | "**", 226 | "*/\n" 227 | ], 228 | "description": "C++ style block comment." 229 | }, 230 | "sv_separator_large": { 231 | "prefix": "sv_separator_full", 232 | "body": [ 233 | "/*----------------------------------------------------------------------------*/", 234 | "/* $0 */", 235 | "/*----------------------------------------------------------------------------*/\n" 236 | ], 237 | "description": "Large 80 ch wide separator." 238 | }, 239 | "sv_separator_small_label": { 240 | "prefix": "sv_separator_half", 241 | "body": [ 242 | "/*--- $0 ---*/", 243 | "/*------------------------------------*/\n", 244 | ], 245 | "description": "Small 40 ch wide separator." 246 | }, 247 | "sv_whitespace_guide": { 248 | "prefix": "sv_whitespace_guide", 249 | "body": [ 250 | "// guide 0---4---8--12--16--20--24--28--32--36--40--44--48--52--56--60--" 251 | ], 252 | "description": "A simple whitespace guide." 253 | } 254 | } 255 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Change Log (Functional Changes) 2 | ## [1.0.27] 3 | ### Changes 4 | * Added `uvm_sequence` functions snippet. 5 | * Updated the main UVM phase snippet definition with proper objection related `uvm_info` macros. 6 | * Added whitespace guide snippet aligned for `$sformatf()`. 7 | * Added `c_` and `if_` to variable naming conventions to represent combinatorical wires and interfaces. (Design Naming Convention) 8 | ### Bugfixes 9 | * Added missing `extensionKind` to package.json thus enabled remote install for SSH development. 10 | * Added indent pattern for `(local|protected|static) virtual` functions and tasks. 11 | 12 | ## [1.0.26] Snippet reorganization: Coronavirus edition 13 | ### Changes 14 | * Reworked UVM related snippets to be more convenient. 15 | * Parametrized UVM class snippets (eg.: `uvm_component_with_parameters`) will construct a proper parameter list for the typedef and the factory registration macro. The regexp transformation is not failsafe, but works well with `type` and `parameter` definitions. (eg.: `class x #(type T, parameter w = 3);`) 16 | * UVM sequence item related `do_` function snippets received an overhaul. (eg.: `uvm_sequence_item_do_compare`, `uvm_sequence_item_convert2string`, `uvm_sequence_item_do_print`, etc.) Instead of user constructed placeholders, they contain examples for placeholders via comments. Their structures are also unified. 17 | * The `uvm_info` macro snippet received a conditional placeholder for the verbosity setting. 18 | * The `uvm_error`, `uvm_fatal`, `uvm_info` and `uvm_warning` macro snippet received various conditional placeholder options for the ID field. 19 | * Added snippet for uvm_sequence derived classes with defined callback stubs and quick reference. (eg.: `uvm_sequence`) 20 | * UVM Phase snippets received a proper context parameter, but alas VSCode ignores it alltogether. 21 | * Fixed `sv_class` and UVM class snippets to contain the same NaturalDocs group headers. (Variables, Constraints, Functions) 22 | * Added snippets for some system tasks and functions; mostly because of the common use or the bogus parameter list. (eg: `$cast`, `$sformatf`, `$timeformat`, etc.) 23 | * Added snippet support for the external and normal constraint blocks of SystemVerilog. (eg.: `sv_extern_constraint`, `sv_constraint_block`) 24 | * Added snippet support for the covergroup, coverpoint and cross coverage blocks; also added snippets for their appropriate option and type_option structures. (eg.: `sv_covergroup`, `sv_covergroup_options`, `sv_covercross`, etc.) 25 | 26 | ### Bugfixes 27 | * A few minor syntax fixes. 28 | 29 | ## [1.0.25] 30 | ### Changes 31 | * Added snippet support for always block and design type variable names, also added parameter_parens construct. 32 | * UVM phase function/task snippets follow the rule of `(uvm_)(extern_)?(phase)()` now. (eg.: `uvm_extern_phase_build` or `uvm_phase_build`) Somehow it worked differently on Windows, Linux and MacOS with the previous definition. (Makes more sense to me to get the desired snippet via pressing `UPBU` or `UXPBU`.) 33 | 34 | ### Bugfixes 35 | * Fixed `[(b[1].size()]` type scoping error where `.size()` was treated as an instantiation parameter. 36 | * `define` folding mark removed. Might be a strange legacy from the past? 37 | * Removed case independency from the do and while keywords. A full refactor of case independent flag might be required. 38 | * Added proper scope support for multiple uvm_analysis_imp-s (macro defined extended names). 39 | 40 | 41 | ## [1.0.24] 42 | ### Changes 43 | Language definition overhaul: 44 | * Fixed and added proper support (autocomplete, stray checking, etc.) for all three kinds of paranthesis (Curly, Square, Round). 45 | * UVM types and enum values received a major overhaul. 46 | * Refactored the typedef scoping rules to have more flexibility regarding unpacked vectorized typedefs. 47 | * Proper support of unbound expressions via `$`. 48 | * Added snippets for factory overrides (`uvm_factory_inst_override`, `uvm_factory_type_override`). 49 | 50 | ### Bugfixes 51 | * Folding markers end bug fixed; it consumed the rest of the file after the last fold. 52 | * Component factory instantiation snippet was missing a `)`. 53 | 54 | ## [1.0.22] 55 | ### Changes 56 | Minor snippet additions: 57 | * Cleared up `uvm_config_db_get_guarded` snippet to be more user friendly. 58 | * Added UVM Factory instantiation snippets. (`uvm_object_factory_instantiation`, `uvm_component_factory_instantiation`) 59 | * Added UVM objection snippet (`uvm_objection_block`) to be available in task contexts. 60 | 61 | ## [1.0.20] 62 | ### Changes 63 | * Changed sv_guard snippet to automatically use uppercase defines with `.` replaced to `_`. 64 | * Changed the SV module and interface container snippets to default the name to the file name. 65 | * Changed the SV module and interface snippets to point out proper `package_import_declaration` placement. By importing packages here, the package contents are available even in the parameter and port list and the import does not happen in the compilation unit/global namespace, thus avoiding confusions and overrides in various simulators. (See SV-LRM-2017: Syntax23-1 for more details.) 66 | * Changed the SV function and task snippets to default the class scope to the file name. 67 | * Changed the UVM phase snippets to default the class scope to the file name. 68 | 69 | ### Bugfixes 70 | * Fixed reindent feature to ignore the `disable fork` and `wait fork` statements in the indentation increase. 71 | 72 | ## [1.0.19] 73 | ### Changes 74 | * Changed the `sv_function` and `sv_task` snippet to have the class resolution operator `::` in a separate scope. 75 | 76 | ## [1.0.18] 77 | ### Bugfixes 78 | * Import-Export keyword and related construct refactorization. (To support multiple imported items and entity name scopes in modules and interfaces.) 79 | * Various UVM snippet related fixes and improvements. 80 | 81 | ## [1.0.15] 82 | ### Bugfixes 83 | * Changed: endtask [: [class_scope] task_identifier] -> endtask [: task_identifier] Changed: endfunction [: [class_scope] task_identifier] -> endfunction [: function_identifier] in snippets. Reason: class scope at the end of tasks and functions compile in ModelSim/QuestaSim but fails with more strict compiler implementations. 84 | * Fixed various snippet issues. 85 | 86 | ## [1.0.14] 87 | ### Bugfixes 88 | * Fixed reindent issue for virtual and pure virtual functions and tasks. 89 | 90 | ### Features 91 | * Added NaturalDocs compatible comment lines for SystemVerilog and UVM snippet constructs. 92 | 93 | ## [1.0.13] 94 | ### Bugfixes 95 | * [#2] Fixed unscoped property declaration in generate block. Due to tmLanguage limitations property-endproperty constructs will now be scoped in _all_ begin-end blocks as they cannot be differentiated from generate block begin-end blocks. Also changed the scoping of *genvar* keyword; it is moved to the net_types group. 96 | 97 | ## [1.0.12] 98 | ### Bugfixes 99 | * Fixed reindent bug. One ')' was lost somewhere in the process. 100 | 101 | ## [1.0.10] & [1.0.11] 102 | ### Features 103 | * Marketplace related changes and fixes. 104 | 105 | ## [1.0.9] 106 | ### Features 107 | * Added several snippet to support quick UVM class deployment. Sequence item received a specialized snippet and also the do_ sequence item method boilerplates are added. (eg.: uvm_sequence_item, uvm_sequence_item_do_copy etc.) 108 | * Snippets are uniformized and end-of-line added to most of them. 109 | * Added snippets for separators/headers (eg.: sv_separator_full, sv_separator_block etc.) 110 | * Added protected|static|local method qualifiers to indentation rules. 111 | 112 | ## [1.0.8] 113 | ### Features 114 | * Better support of UVM source code, eg.: /* local */ extern functions, oneliner tasks and functions, etc. 115 | * Minor bugfixes in UVM phase snippets. 116 | 117 | ## [1.0.7] 118 | ### Features 119 | * Added external stubs for UVM phases; and also added UVM_runtime_phases to the snippet library. 120 | 121 | ## [1.0.6] 122 | ### Features 123 | * Added net and variable types to the compilation unit namespace 124 | * Compiler directives and system tasks are now correctly included in the appropriate scopes 125 | * External function declaration now correctly scopes the function name and the return type 126 | 127 | ## [1.0.5] 128 | ### Features 129 | * Added folding rules for all langauage constructs eg.: module-endmodule, class-endclass etc., to be foldable even when the indentation of the code is not perfect. Exceptions: begin-end, fork-join, as the editor has certain limitations; eg.: a line of 'end else begin' breaks the processing. Reindent still works on these lines and folding by indentation is possible 130 | * Also indentation regex rules are now more verbose; for some reason the folding markers work this way 131 | * Added support for user defined macro calls 132 | ### Bugfixes 133 | * Compiler directives now scope correctly; standardized end-of-line termination on several scopes 134 | * Global clocking without a clocking_identifier now scopes correctly 135 | * Standardized end label scoping of classes, properties and sequences 136 | * Typedef with queue types will scope correctly 137 | * Module instantiation, function call parameters now scope correctly 138 | 139 | ## [1.0.4] 140 | * Added snippet demonstration gif 141 | * Added correct scoping to externally defined functions, tasks, modules, etc. 142 | * End label handling of module, interface, etc. constructs moved to the punctuation region. 143 | * End labels are handled well even when the previous end(construct) keyword is stray and illegal. 144 | 145 | ## [1.0.2] 146 | * Corrected indent pattern on open curly braces 147 | * Added special formal types to parenthesis (sequence, untyped) 148 | * Fixed attribute bug in always(*) constructs 149 | * Added operators to covergroup body (iff operator) 150 | * Added nettype user defined type 151 | * Added property and sequence to clocking block 152 | 153 | ## [1.0.1] 154 | ### License information and screenshots are added 155 | 156 | ## [1.0.0] 157 | ### Initial release 158 | #### The addon supports the following features 159 | * classes 160 | * comments, attributes, various conventional highlights (accessors, numbers, etc.) 161 | * constraint blocks 162 | * coverage 163 | * interfaces 164 | * modules 165 | * packages 166 | * tasks and functions 167 | 168 | #### Limited support on the following features 169 | * checkers 170 | * programs 171 | * user-defined primitives 172 | * UVM related classes, types, macros and functions 173 | 174 | #### Unsupported features and problems 175 | * specify blocks 176 | * Logical '<=' and the assignment '<=' are not differentiated yet. Solution: logical operators shall only be applied inside of a parenthesis.(?) 177 | * A.1.2: SystemVerilog source text: { package_import_declaration } in module_nonansi_header, module_ansi_header is not supported. 178 | -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-16-assertions.svh: -------------------------------------------------------------------------------- 1 | module abc(); 2 | assert_f: 3 | assert(f) $info("passed"); 4 | else $error("failed"); 5 | 6 | assume_inputs: 7 | assume (in_a || in_b) $info("assumption holds"); 8 | else $error("assumption does not hold"); 9 | 10 | time t; 11 | 12 | always @(posedge clk) 13 | if (state == REQ) 14 | assert (req1 || req2) 15 | else begin 16 | t = $time; 17 | #5 $error("assert failed at time %0t", t); 18 | end 19 | 20 | assert #0 (expression) action_block; 21 | assert final (expression) action_block; 22 | 23 | function f(bit v); 24 | p: assert #0 (v); 25 | ... 26 | endfunction 27 | 28 | always_comb begin: myblk 29 | a = b || f(c); 30 | end 31 | 32 | always @(a or b) begin : b1 33 | a3: assert #0 (a == b) rptobj.success(0); else rptobj.error(0, a, b); 34 | #1; 35 | a4: assert #0 (a == b) rptobj.success(1); else rptobj.error(1, a, b); 36 | end : b1 37 | endmodule 38 | 39 | module dut(input logic clk, input logic a, input logic b); 40 | logic c; 41 | 42 | always_ff @(posedge clk) 43 | c <= b; 44 | 45 | a1: assert #0 (!(a & c)) $display("Pass"); else $display("Fail"); 46 | a2: assert final (!(a & c)) $display("Pass"); else $display("Fail"); 47 | endmodule 48 | 49 | module dut_two(); 50 | global clocking @clk; 51 | endclocking 52 | ... 53 | assert property(@$global_clock a); 54 | assume property(@$global_clock a); 55 | cover property(@$global_clock a); 56 | restrict property(@$global_clock a); 57 | 58 | bit a; 59 | integer b; 60 | byte q[$]; 61 | 62 | property p1; 63 | $rose(a) |-> q[0]; 64 | endproperty: p1 65 | 66 | property p2; 67 | integer l_b; 68 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; 69 | endproperty 70 | 71 | bit count[2:0]; 72 | realtime t; 73 | initial count = 0; 74 | always @(posedge clk) begin 75 | if (count == 0) t = $realtime; //capture t in a procedural context 76 | count++; 77 | end 78 | 79 | property p1; 80 | @(posedge clk) 81 | count == 7 |-> $realtime – t < 50.5; 82 | endproperty 83 | 84 | property p2; 85 | realtime l_t; 86 | 87 | @(posedge clk) 88 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> 89 | $realtime – l_t < 50.5; 90 | endproperty 91 | 92 | and intersect or first_match throughout within 93 | 94 | sequence s1; 95 | @(posedge clk) a ##1 b ##1 c; 96 | endsequence 97 | 98 | sequence s2; 99 | @(posedge clk) d ##1 e ##1 f; 100 | endsequence 101 | 102 | sequence s3; 103 | @(negedge clk) g ##1 h ##1 i; 104 | endsequence 105 | 106 | sequence s4; 107 | @(edge clk) j ##1 k ##1 l; 108 | endsequence 109 | 110 | sequence delay_example(x, y, min, max, delay1); 111 | x ##delay1 y[*min:max]; 112 | endsequence: delay_example 113 | 114 | // Legal 115 | a1: assert property (@(posedge clk) delay_example(x, y, 3, $, 2)); 116 | int z, d; 117 | // Illegal: z and d are not elaboration-time constants 118 | a2_illegal: assert property (@(posedge clk) delay_example(x, y, z, $, d)); 119 | 120 | sequence delay_arg_example (max, shortint delay1, delay2, min); 121 | x ##delay1 y[*min:max] ##delay2 z; 122 | endsequence: delay_arg_example 123 | 124 | parameter my_delay=2; 125 | cover property (delay_arg_example($, my_delay, my_delay-1, 3)); 126 | 127 | logic b_d, d_d; 128 | sequence legal_loc_var_formal ( 129 | local inout logic a, 130 | local logic b = b_d, // input inferred, default actual argument b_d 131 | c, // local input logic inferred, no default actual argument 132 | d = d_d, // local input logic inferred, default actual argument d_d 133 | logic e, f // e and f are not local variable formal arguments 134 | ); 135 | 136 | logic g = c, h = g || d; 137 | ... 138 | endsequence 139 | ##[*] ##2 ##[+] 140 | 141 | req ##[4:32] gnt 142 | req ##1 gnt 143 | 144 | d ##1 e ##1 f // second sequence seq2 145 | (a ##1 b ##1 c) ##0 (d ##1 e ##1 f) // overlapped concatenation 146 | a ##1 b ##1 c&&d ##1 e ##1 f 147 | 148 | req ##[4:$] gnt 149 | a ##1 b ##1 c ##3 `true 150 | 151 | sequence delay_example(x, y, min, max, delay1); 152 | x ##delay1 y[*min:max]; 153 | endsequence 154 | // Legal 155 | a1: assert property (@(posedge clk) delay_example(x, y, 3, $, 2)); 156 | 157 | int z, d; 158 | 159 | // Illegal: z and d are not elaboration-time constants 160 | a2_illegal: assert property (@(posedge clk) delay_example(x, y, z, $, d)); 161 | 162 | sequence s20_1(data,en); 163 | (!frame && (data==data_bus)) ##1 (c_be[0:3] == en); 164 | endsequence 165 | 166 | sequence s1(w, x, y); 167 | w ##1 x ##[2:10] y; 168 | endsequence 169 | 170 | sequence delay_arg_example (max, shortint delay1, delay2, min); 171 | x ##delay1 y[*min:max] ##delay2 z; 172 | endsequence 173 | 174 | parameter my_delay=2; 175 | cover property (delay_arg_example($, my_delay, my_delay-1, 3)); 176 | 177 | a ##1 b ##1 b ##1 b ##1 c 178 | a ##1 b [*3] ##1 c 179 | a [*3] means a ##1 a ##1 a 180 | a [*0] 181 | 182 | sequence t2; 183 | (a ##[2:3] b) or (c ##[1:2] d); 184 | endsequence 185 | sequence ts2; 186 | first_match(t2); 187 | endsequence 188 | 189 | property abc(a, b, c); 190 | disable iff (a==2) @(posedge clk) not (b ##1 c); 191 | endproperty 192 | 193 | env_prop: ASSERT property (abc(rst, in1, in2)) $display("env_prop passed."); 194 | else $display("env_prop failed."); 195 | and 196 | 197 | 198 | Assertion_label: 199 | assert (a == 1) ; 200 | else ; 201 | 202 | property check_phase1; 203 | s1 |-> (phase1_prop and (1'b1 |=> check_phase2)); 204 | endproperty 205 | property check_phase2; 206 | s2 |-> (phase2_prop and (1'b1 |=> check_phase1)); 207 | endproperty 208 | 209 | property p_delay(logic [1:0] delay); 210 | case (delay) 211 | 2'd0 : a && b; 212 | 2'd1 : a ##2 b; 213 | 2'd2 : a ##4 b; 214 | 2'd3 : a ##8 b; 215 | default: 0; // cause a failure if delay has x or z values 216 | endcase 217 | endproperty 218 | 219 | property fibonacci2 (int a, b, n, fib_sig); 220 | (n > 0) 221 | |-> 222 | ( 223 | (fib_sig == a) 224 | and 225 | (1'b1 |=> fibonacci2(b, a + b, n - 1, fib_sig)) 226 | ); 227 | endproperty 228 | 229 | property rule5; 230 | @(posedge clk) 231 | a ##1 (b || c)[->1] |-> 232 | if (b) 233 | (##1 d |-> e) 234 | else // c 235 | f ; 236 | endproperty 237 | 238 | @(posedge clk0) if (b) @(posedge clk1) s1 else @(posedge clk2) s2 239 | 240 | @(c) x |=> @(c) y ##1 @(d) z 241 | @(c) x |=> y ##1 @(d) z 242 | 243 | property mult_p8; 244 | @(posedge clk) a ##1 b |-> 245 | if (c) 246 | (1 |=> @(posedge clk1) d) 247 | else 248 | e ##1 @(posedge clk2) f ; 249 | endproperty 250 | 251 | sequence_instance.matched() 252 | formal_argument_sequence.matched 253 | 254 | sequence e1(a,b,c); 255 | @(posedge clk) $rose(a) ##1 b ##1 c ; 256 | endsequence 257 | sequence e2; 258 | @(posedge sysclk) reset ##1 inst ##1 e1(ready,proc1,proc2).matched [->1] 259 | ##1 branch_back; 260 | endsequence 261 | 262 | property abc(a, b, c); 263 | disable iff (a==2) @(posedge clk) not (b ##1 c); 264 | endproperty 265 | 266 | env_prop: assert property (abc(rst, in1, in2)) 267 | $display("env_prop passed."); 268 | else 269 | $display("env_prop failed."); 270 | 271 | a1:assume property ( @(posedge clk) req dist {0:=40, 1:=60} ) ; 272 | property proto ; 273 | @(posedge clk) req |-> req[*1:$] ##0 ack; 274 | endproperty 275 | 276 | a1:assume property (@(posedge clk) req dist {0:=40, 1:=60} ); 277 | assume_req1:assume property (pr1); 278 | assume_req2:assume property (pr2); 279 | assume_req3:assume property (pr3); 280 | assert_ack1:assert property (pa1) 281 | else $display("\n ack asserted while req is still deasserted"); 282 | assert_ack2:assert property (pa2) 283 | else $display("\n ack is extended over more than one cycle"); 284 | 285 | restrict property (@(posedge clk) ctr == '0); 286 | 287 | assert property ( property_spec ) action_block; 288 | always assert property ( property_spec ) action_block; 289 | cover property ( property_spec ) statement_or_null; 290 | always cover property ( property_spec ) statement_or_null; 291 | 292 | module top(input logic clk); 293 | logic a,b,c; 294 | 295 | sequence seq3; 296 | @(posedge clk) b ##1 c; 297 | endsequence 298 | 299 | c1: cover property (seq3); 300 | ... 301 | endmodule: top 302 | 303 | property r1; 304 | q != d; 305 | endproperty 306 | always @(posedge mclk) begin 307 | q <= d1; 308 | r1_p1: assert property (r1); 309 | r1_p2: assert property (@(posedge scanclk)r1); 310 | end 311 | 312 | default clocking @(posedge clk); 313 | endclocking 314 | always @(a or b or c) begin : b2 315 | if (c == 8'hff) begin 316 | a2: assert property (a && b); 317 | end else begin 318 | a3: assert property (a || b); 319 | end 320 | end 321 | 322 | always @(clear_b2) begin : b3 323 | disable b2; 324 | end 325 | 326 | $inferred_clock 327 | $inferred_disable 328 | 329 | module m(logic a, b, c, d, rst1, clk1, clk2); 330 | logic rst; 331 | default clocking @(negedge clk1); 332 | endclocking 333 | default disable iff rst1; 334 | 335 | property p_triggers(start_event, end_event, form, clk = $inferred_clock, 336 | rst = $inferred_disable); 337 | @clk disable iff (rst) 338 | (start_event ##0 end_event[->1]) |=> form; 339 | endproperty 340 | 341 | property p_multiclock(clkw, clkx = $inferred_clock, clky, w, x, y, z); 342 | @clkw w ##1 @clkx x |=> @clky y ##1 z; 343 | endproperty 344 | 345 | a1: assert property (p_triggers(a, b, c)); 346 | a2: assert property (p_triggers(a, b, c, posedge clk1, 1'b0) ); 347 | always @(posedge clk2 or posedge rst) begin 348 | if (rst) ... ; 349 | else begin 350 | a3: assert property (p_triggers(a, b, c)); 351 | ... 352 | end 353 | end 354 | 355 | a4: assert property(p_multiclock(negedge clk2, , posedge clk1, a, b, c, d) ); 356 | endmodule 357 | 358 | sequence s2; @(posedge clk) a ##2 b; 359 | endsequence 360 | property p2; not s2; 361 | endproperty 362 | assert property (p2); 363 | 364 | // — Property, for example: 365 | property p3; @(posedge clk) not (a ##2 b); 366 | endproperty 367 | assert property (p3); 368 | // — Contextually inferred clock from a procedural block, for example: 369 | always @(posedge clk) assert property (not (a ##2 b)); 370 | // — A clocking block, for example: 371 | clocking master_clk @(posedge clk); 372 | property p3; not (a ##2 b); 373 | endproperty 374 | endclocking 375 | 376 | assert property (master_clk.p3); 377 | 378 | // — Default clock, for example: 379 | default clocking master_clk ; // master clock as defined above 380 | property p4; (a ##2 b); 381 | endproperty 382 | assert property (p4); 383 | 384 | expect wait 385 | endsequence 386 | endmodule -------------------------------------------------------------------------------- /crash_course/sv-1800-2012-cc-08-classes.svh: -------------------------------------------------------------------------------- 1 | // Class crash course -- source: SV-LRM-1800-2012 2 | 3 | typedef class a; 4 | 5 | endclass 6 | endclass 7 | 8 | typedef interface class IntfD; 9 | 10 | endclass 11 | endclass 12 | 13 | class static Packet ; 14 | //data or class properties 15 | bit [3:0] command; 16 | bit [40:0] address; 17 | bit [4:0] master_id; 18 | integer time_requested; 19 | integer time_issued; 20 | integer status; 21 | typedef enum { ERR_OVERFLOW= 10, ERR_UNDERFLOW = 1123} PCKT_TYPE; 22 | const integer buffer_size = 100; 23 | const integer header_size; 24 | 25 | // initialization 26 | function new(); 27 | command = 4'd0; 28 | address = 41'b0; 29 | master_id = 5'bx; 30 | header_size = 10; 31 | endfunction 32 | 33 | // methods 34 | // public access entry points 35 | task clean(); 36 | command = 0; address = 0; master_id = 5'bx; 37 | endtask 38 | 39 | task issue_request( int delay ); 40 | // send request to bus 41 | uvm_bottomup_phase(.aasd()) 42 | 43 | endtask 44 | task my_task; 45 | input a, b; 46 | inout c; 47 | output d, e; 48 | ... // statements that perform the work of the task 49 | ... 50 | c = a; // the assignments that initialize result outputs 51 | d = b; 52 | e = c; 53 | endtask 54 | 55 | function integer current_status(); 56 | current_status = status; 57 | endfunction 58 | endclass 59 | 60 | class C; 61 | int c1 = 1; 62 | int c2 = 1; 63 | int c3 = 1; 64 | function new(int a); 65 | c2 = 2; 66 | c3 = a; 67 | endfunction 68 | endclass: C 69 | 70 | class D extends C; 71 | int d1 = 4; 72 | int d2 = c2; 73 | int d3 = 6; 74 | function new; 75 | super.new(d3); 76 | endfunction 77 | endclass 78 | 79 | class E #(type T = int) extends C; 80 | T x; 81 | function new(T x_init); 82 | super.new(); 83 | begin: asd 84 | // this is sad 85 | x = x_init; 86 | end: asd 87 | endfunction 88 | endclass: E 89 | 90 | class id; 91 | static int current = 0; 92 | 93 | static function int next_id(); 94 | next_id = ++current; // OK to access static class property 95 | endfunction 96 | endclass 97 | 98 | class B ; 99 | integer i = 1; 100 | baseA a = new; 101 | endclass 102 | 103 | class xtndA extends baseA; 104 | rand int x; 105 | constraint cst1 { x < 10; } 106 | endclass: xtndA 107 | 108 | class Packet; // base class 109 | integer value; 110 | function integer delay(); 111 | delay = value * value; 112 | endfunction 113 | endclass 114 | 115 | class LinkedPacket extends Packet; // derived class 116 | integer value; 117 | 118 | function integer delay(); 119 | delay = super.delay()+ value * super.value; 120 | endfunction 121 | endclass 122 | 123 | class BasePacket; 124 | int A = 1; 125 | int B = 2; 126 | 127 | function void printA; 128 | $display("BasePacket::A is %d", A); 129 | endfunction : printA 130 | 131 | virtual function void printB; 132 | $display("BasePacket::B is %d", B); 133 | endfunction : printB 134 | endclass : BasePacket 135 | 136 | class My_Packet extends BasePacket; 137 | int A = 3; 138 | int B = 4; 139 | 140 | function void printA; 141 | $display("My_Packet::A is %d", A); 142 | endfunction: printA 143 | 144 | virtual function void printB; 145 | $display("My_Packet::B is %d", B); 146 | endfunction : printB 147 | endclass : My_Packet 148 | 149 | // abstract classes 150 | virtual class BasePacket; 151 | pure virtual function integer send(bit[31:0] data); // No implementation 152 | endclass: BasePacket 153 | 154 | class EtherPacket extends BasePacket; 155 | virtual function integer send(bit[31:0] data); 156 | // body of the function 157 | ... 158 | endfunction 159 | endclass: EtherPacket 160 | 161 | // nesting 162 | class Outer; 163 | int outerProp; 164 | local int outerLocalProp; 165 | static int outerStaticProp; 166 | static local int outerLocalStaticProp; 167 | 168 | class Inner; 169 | function void innerMethod(Outer h); 170 | outerStaticProp = 0; 171 | // Legal, same as Outer::outerStaticProp 172 | outerLocalStaticProp = 0; 173 | // Legal, nested classes may access local's in outer class 174 | outerProp = 0; 175 | // Illegal, unqualified access to non-static outer 176 | h.outerProp = 0; 177 | // Legal, qualified access. 178 | h.outerLocalProp = 0; 179 | // Legal, qualified access and locals to outer class allowed. 180 | endfunction 181 | endclass 182 | 183 | endclass 184 | 185 | // external declarations 186 | class Packet; 187 | Packet next; 188 | function Packet get_next(); 189 | get_next = next; 190 | endfunction 191 | // out-of-body (extern) declaration 192 | 193 | extern protected virtual function int send(int value); 194 | 195 | endclass 196 | 197 | function int Packet::send(int value); 198 | // dropped protected virtual, added Packet:: 199 | // body of method 200 | ... 201 | endfunction 202 | 203 | // parameters 204 | class vector #(int size = 1); 205 | bit [size-1:0] a; 206 | endclass 207 | 208 | vector #(10) vten; // object with vector of size 10 209 | vector #(.size(2)) vtwo; // object with vector of size 2 210 | typedef vector#(4) Vfour; // Class with vector of size 4 211 | 212 | class stack #(type T = int); 213 | local T items[]; 214 | task push( T a ); 215 | ... 216 | endtask 217 | task pop( ref T a ); 218 | ... 219 | endtask 220 | endclass 221 | 222 | class vector #(int size = 1); 223 | bit [size-1:0] a; 224 | static int count = 0; 225 | 226 | function void disp_count(); 227 | $display( "count: %d of size %d", count, size ); 228 | endfunction 229 | endclass 230 | 231 | class C #(type T = bit); 232 | ... 233 | endclass // base class 234 | 235 | class d1 #(type P = real) extends C; // T is bit (the default) 236 | endclass 237 | endclass 238 | class D2 #(type P = real) extends C #(integer); // T is integer 239 | endclass 240 | class D3 #(type P = real) extends C #(P); // T is P 241 | endclass 242 | class D1 #(type P = real) extends uvm_driver ; // T is bit (the default) 243 | endclass 244 | class D2#(type P = real) extends uvm_agent#(integer); // T is integer 245 | endclass 246 | class D3#(type P = real) extends CP; // T is P 247 | endclass 248 | class D4 #(type P = C#(real)) extends P; // for default T is real 249 | endclass 250 | 251 | // interface classes 252 | interface class A; 253 | 254 | endclass: Abcd// asda 255 | 256 | 257 | class B implements A; 258 | endclass 259 | 260 | class C extends B; 261 | endclass 262 | 263 | interface class PutImp#(type PUT_T = logic); 264 | pure virtual function void put(PUT_T a); 265 | endclass 266 | 267 | interface class GetImp#(type GET_T = logic); 268 | pure virtual function GET_T get(); 269 | endclass 270 | 271 | class MyQueue #(type T = logic, int DEPTH = 1); 272 | T PipeQueue[$:DEPTH-1]; 273 | virtual function void deleteQ(); 274 | PipeQueue.delete(); 275 | endfunction 276 | endclass 277 | 278 | class Fifo::Fofi_2 #(type T = logic, parameter int DEPTH = 1) extends uvm_object#(T, DEPTH) implements uvm_agent#(T), Pop_if#(T); // 279 | virtual function void put(T a); 280 | PipeQueue.push_back(a); 281 | endfunction 282 | 283 | virtual function T get(); 284 | get = PipeQueue.pop_front(); 285 | endfunction 286 | endclass 287 | 288 | virtual class XFifo#(type T_in = logic, type T_out = logic, int DEPTH = 1) extends MyQueue#(T_out) implements PutImp#(T_in), GetImp#(T_out); 289 | 290 | pure virtual function T_out translate(T_in a); 291 | 292 | virtual function void put(T_in a); 293 | PipeQueue.push_back(translate(a)); 294 | endfunction 295 | virtual function T_out get(); 296 | get = PipeQueue.pop_front(); 297 | endfunction 298 | endclass 299 | 300 | interface class IntfClass; 301 | pure virtual function void f(); 302 | endclass 303 | 304 | class BaseClass; 305 | function void f(); 306 | begin: asdaf 307 | $display("Called BaseClass::f()"); 308 | end: asdaf 309 | endfunction 310 | endclass 311 | 312 | class ExtClass extends BaseClass implements IntfClass; 313 | virtual function void f(); 314 | $display("Called ExtClass::f()"); 315 | endfunction 316 | endclass 317 | 318 | interface class IntfA #(type T1 = logic); 319 | typedef T1[1:0] T2; 320 | pure virtual function T2 funcA(); 321 | endclass : IntfA 322 | 323 | interface class IntfB #(type T = bit) extends IntfA #(T); 324 | pure virtual function T2 funcB(); // legal, type T2 is inherited 325 | endclass : IntfB 326 | 327 | // partial implementation 328 | interface class IntfClass; 329 | pure virtual function bit funcA(); 330 | pure virtual function bit funcB(); 331 | endclass 332 | 333 | // Partial implementation of IntfClass 334 | virtual class ClassA implements IntfClass; 335 | virtual function bit funcA(); 336 | return (1); 337 | endfunction 338 | pure virtual function bit funcB(); 339 | endclass 340 | 341 | // Complete implementation of IntfClass 342 | class ClassB extends ClassA; 343 | virtual function bit funcB(); 344 | return (1); 345 | endfunction 346 | endclass 347 | 348 | int'(2.0 * 3.0) 349 | shortint' ({8'hFA, 8'hCE}) 350 | A = cast_t1'(expr_1) + cast_t2'(expr_2); 351 | 352 | x = 1.2e-4; 353 | 354 | class Jumbo_Packet; 355 | const int max_size = 9 * 1024; // global constant 356 | byte payload []; 357 | 358 | function new( int size ); 359 | payload = new[ size > max_size ? max_size : size ]; 360 | endfunction 361 | endclass 362 | 363 | 364 | class Base; 365 | 366 | typedef enum {bin,oct,dec,hex} radix; 367 | static task print( radix r, integer n ); ... 368 | await kill 369 | endtask 370 | 371 | pure virtual function void a(); 372 | 373 | endclass 374 | 375 | Base b = new; 376 | int bin = 123; 377 | b.print( Base::bin, bin ); // Base::bin and bin are different 378 | Base::print( Base::hex, 66 ); 379 | 380 | class BasePacket; 381 | int A = 1; 382 | int B = 2; 383 | function void printA; 384 | $display("BasePacket::A is %d", A); 385 | endfunction : printA 386 | virtual function void printB; 387 | $display("BasePacket::B is %d", B); 388 | endfunction : printB 389 | endclass : BasePacket 390 | 391 | class My_Packet extends BasePacket; 392 | int A = 3; 393 | int B = 4; 394 | function void printA; 395 | $display("My_Packet::A is %d", A); 396 | endfunction: printA 397 | virtual function void printB; 398 | $display("My_Packet::B is %d", B); 399 | endfunction : printB 400 | endclass : My_Packet 401 | 402 | typedef int T; // T and int are matching data types. 403 | class C; 404 | virtual function C some_method(int a); 405 | endfunction 406 | endclass 407 | 408 | class D extends C; 409 | virtual function D some_method(T a); 410 | endfunction 411 | endclass 412 | 413 | class E #(type Y = logic) extends C; 414 | virtual function D some_method(Y a); 415 | endfunction 416 | endclass 417 | 418 | E #() v1; // Illegal: type parameter Y resolves to logic, which is not 419 | // a matching type for argument a 420 | E #(int) v2; // Legal: type parameter Y resolves to int 421 | typedef real T; 422 | 423 | class C; 424 | typedef int T_t; 425 | extern function T_t f(); 426 | extern function real f2(); 427 | endclass: Cabalero 428 | 429 | function C::T_t C::f(); // the return must use the scope resolution 430 | // since the type is defined within the class 431 | return 1; 432 | endfunction 433 | 434 | function real C::f2(); 435 | return 1.0; 436 | endfunction 437 | 438 | class vector #(int size = 1); 439 | bit [size-1:0] a; 440 | endclass 441 | 442 | vector #(10) vten; // object with vector of size 10 443 | vector #(.size(2)) vtwo; // object with vector of size 2 444 | typedef vector#(4) Vfour; // Class with vector of size 4 445 | 446 | class stack #(type T = int); 447 | local T items[]; 448 | task push( T a ); ... 449 | endtask 450 | task pop( ref T a ); ... 451 | endtask 452 | endclass 453 | 454 | class stack #(type T = int); 455 | local T items[]; 456 | task push( T a ); ... 457 | endtask 458 | task pop( ref T a ); ... 459 | endtask 460 | endclass 461 | 462 | class incorporator #(); 463 | // The preceding class defines a generic stack class, which can be instantiated with any arbitrary type: 464 | stack is; // default: a stack of ints 465 | stack#(bit[1:10]) bs; // a stack of 10-bit vector 466 | stack#(real) rs; // a stack of real numbers 467 | // Any type can be supplied as a parameter, including a user-defined type such as a 468 | endclass: incorporator 469 | 470 | class C #(type T = bit); ... 471 | endclass // base class 472 | 473 | class D1 #(type P = real) extends uvm_driver; // T is bit (the default) 474 | 475 | class D2 #(type P = real) extends C #(integer); // T is integer 476 | 477 | class D3 #(type P = real) extends C #(P); // T is P 478 | 479 | class D4 #(type P = C#(real)) extends P; // for default T is real 480 | 481 | endclass 482 | endclass 483 | endclass 484 | endclass 485 | 486 | interface class PutImp#(type PUT_T = logic); 487 | pure virtual function void put(PUT_T a); 488 | endclass 489 | 490 | interface class GetImp#(type GET_T = logic); 491 | pure virtual function GET_T get(); 492 | endclass 493 | 494 | class Fifo#(type T = logic, int DEPTH=1) implements PutImp#(T), GetImp#(T); 495 | T myFifo [$:DEPTH-1]; 496 | virtual function void put(T a); 497 | myFifo.push_back(a); 498 | endfunction 499 | virtual function T get(); 500 | get = myFifo.pop_front(); 501 | endfunction 502 | endclass 503 | 504 | class Stack#(type T = logic, int DEPTH=1) implements PutImp#(T), GetImp#(T); 505 | T myFifo [$:DEPTH-1]; 506 | virtual function void put(T a); 507 | myFifo.push_front(a); 508 | endfunction 509 | virtual function T get(); 510 | get = myFifo.pop_front(); 511 | endfunction 512 | endclass 513 | 514 | interface class IntfClass; 515 | pure virtual function void f(); 516 | endclass 517 | 518 | class BaseClass; 519 | function void f(); 520 | $display("Called BaseClass::f()"); 521 | endfunction 522 | endclass 523 | 524 | class ExtClass #(int) extends BaseClass implements IntfClass; 525 | virtual function void f(); 526 | $display("Called ExtClass::f()"); 527 | endfunction 528 | endclass//asd 529 | 530 | 531 | class ClassB implements IntfD #(bit); // illegal 532 | virtual function bit[1:0] funcD(); 533 | endfunction 534 | endclass : ClassB 535 | 536 | // This interface class declaration must be declared before ClassB 537 | interface class IntfD #(type T1 = logic); 538 | pure virtual function T2 funcD(); 539 | typedef T1[1:0] T2; 540 | endclass:IntfD//asds 541 | 542 | endclass 543 | endclass 544 | 545 | interface class IntfBase; 546 | parameter SIZE = 64; 547 | endclass: IntfBase 548 | 549 | interface class IntfExt1 extends IntfBase; 550 | pure virtual function bit funcExt1(); 551 | endclass 552 | 553 | interface class IntfExt2 extends IntfBase; 554 | pure virtual function bit funcExt2(); 555 | endclass 556 | 557 | interface class IntfExt3 extends uvm_object, IntfExt2, IntfExt4 ; 558 | endclass -------------------------------------------------------------------------------- /snippets/uvm_phases.json: -------------------------------------------------------------------------------- 1 | { 2 | "uvm_extern_build_phase": { 3 | "context": "meta.class.systemverilog", 4 | "prefix": "uvm_extern_phase_build", 5 | "body": [ 6 | "// Function: build_phase", 7 | "extern function void build_phase(uvm_phase phase);\n$0" 8 | ], 9 | "description": "UVM build_phase stub" 10 | }, 11 | "uvm_extern_connect_phase": { 12 | "context": "meta.class.systemverilog", 13 | "prefix": "uvm_extern_phase_connect", 14 | "body": [ 15 | "// Function: connect_phase", 16 | "extern function void connect_phase(uvm_phase phase);\n$0" 17 | ], 18 | "description": "UVM connect_phase stub" 19 | }, 20 | "uvm_extern_end_of_elaboration_phase": { 21 | "context": "meta.class.systemverilog", 22 | "prefix": "uvm_extern_phase_end_of_elaboration", 23 | "body": [ 24 | "// Function: end_of_elaboration_phase", 25 | "extern function void end_of_elaboration_phase(uvm_phase phase);\n$0" 26 | ], 27 | "description": "UVM end_of_elaboration stub" 28 | }, 29 | "uvm_extern_start_of_simulation_phase": { 30 | "context": "meta.class.systemverilog", 31 | "prefix": "uvm_extern_phase_start_of_simulation", 32 | "body": [ 33 | "// Function: start_of_simulation_phase", 34 | "extern function void start_of_simulation_phase(uvm_phase phase);\n$0" 35 | ], 36 | "description": "UVM start_of_simulation_phase stub" 37 | }, 38 | "uvm_extern_run_phase": { 39 | "context": "meta.class.systemverilog", 40 | "prefix": "uvm_extern_phase_run", 41 | "body": [ 42 | "// Function: run_phase", 43 | "extern task run_phase(uvm_phase phase);\n$0" 44 | ], 45 | "description": "UVM run_phase stub" 46 | }, 47 | "uvm_extern_pre_reset_phase": { 48 | "context": "meta.class.systemverilog", 49 | "prefix": "uvm_extern_phase_pre_reset", 50 | "body": [ 51 | "// Function: pre_reset_phase", 52 | "extern task pre_reset_phase(uvm_phase phase);\n$0" 53 | ], 54 | "description": "UVM pre_reset_phase stub" 55 | }, 56 | "uvm_extern_reset_phase": { 57 | "context": "meta.class.systemverilog", 58 | "prefix": "uvm_extern_phase_reset", 59 | "body": [ 60 | "// Function: reset_phase", 61 | "extern task reset_phase(uvm_phase phase);\n$0" 62 | ], 63 | "description": "UVM reset_phase stub" 64 | }, 65 | "uvm_extern_post_reset_phase": { 66 | "context": "meta.class.systemverilog", 67 | "prefix": "uvm_extern_phase_post_reset", 68 | "body": [ 69 | "// Function: post_reset_phase", 70 | "extern task post_reset_phase(uvm_phase phase);\n$0" 71 | ], 72 | "description": "UVM post_reset_phase stub" 73 | }, 74 | "uvm_extern_pre_configure_phase": { 75 | "context": "meta.class.systemverilog", 76 | "prefix": "uvm_extern_phase_pre_configure", 77 | "body": [ 78 | "// Function: pre_configure_phase", 79 | "extern task pre_configure_phase(uvm_phase phase);\n$0" 80 | ], 81 | "description": "UVM pre_configure_phase stub" 82 | }, 83 | "uvm_extern_configure_phase": { 84 | "context": "meta.class.systemverilog", 85 | "prefix": "uvm_extern_phase_configure", 86 | "body": [ 87 | "// Function: configure_phase", 88 | "extern task configure_phase(uvm_phase phase);\n$0" 89 | ], 90 | "description": "UVM configure_phase stub" 91 | }, 92 | "uvm_extern_post_configure_phase": { 93 | "context": "meta.class.systemverilog", 94 | "prefix": "uvm_extern_phase_post_configure", 95 | "body": [ 96 | "// Function: post_configure_phase", 97 | "extern task post_configure_phase(uvm_phase phase);\n$0" 98 | ], 99 | "description": "UVM post_configure_phase stub" 100 | }, 101 | "uvm_extern_pre_main_phase": { 102 | "context": "meta.class.systemverilog", 103 | "prefix": "uvm_extern_phase_pre_main", 104 | "body": [ 105 | "// Function: pre_main_phase", 106 | "extern task pre_main_phase(uvm_phase phase);\n$0" 107 | ], 108 | "description": "UVM pre_main_phase stub" 109 | }, 110 | "uvm_extern_main_phase": { 111 | "context": "meta.class.systemverilog", 112 | "prefix": "uvm_extern_phase_main", 113 | "body": [ 114 | "// Function: main_phase", 115 | "extern task main_phase(uvm_phase phase);\n$0" 116 | ], 117 | "description": "UVM main_phase stub" 118 | }, 119 | "uvm_extern_post_main_phase": { 120 | "context": "meta.class.systemverilog", 121 | "prefix": "uvm_extern_phase_post_main", 122 | "body": [ 123 | "// Function: post_main_phase", 124 | "extern task post_main_phase(uvm_phase phase);\n$0" 125 | ], 126 | "description": "UVM post_main_phase stub" 127 | }, 128 | "uvm_extern_pre_shutdown_phase": { 129 | "context": "meta.class.systemverilog", 130 | "prefix": "uvm_extern_phase_pre_shutdown", 131 | "body": [ 132 | "// Function: pre_shutdown_phase", 133 | "extern task pre_shutdown_phase(uvm_phase phase);\n$0" 134 | ], 135 | "description": "UVM pre_shutdown_phase stub" 136 | }, 137 | "uvm_extern_shutdown_phase": { 138 | "context": "meta.class.systemverilog", 139 | "prefix": "uvm_extern_phase_shutdown", 140 | "body": [ 141 | "// Function: shutdown_phase", 142 | "extern task shutdown_phase(uvm_phase phase);\n$0" 143 | ], 144 | "description": "UVM shutdown_phase stub" 145 | }, 146 | "uvm_extern_post_shutdown_phase": { 147 | "context": "meta.class.systemverilog", 148 | "prefix": "uvm_extern_phase_post_shutdown", 149 | "body": [ 150 | "// Function: post_shutdown_phase", 151 | "extern task post_shutdown_phase(uvm_phase phase);\n$0" 152 | ], 153 | "description": "UVM post_shutdown_phase stub" 154 | }, 155 | "uvm_extern_extract_phase": { 156 | "context": "meta.class.systemverilog", 157 | "prefix": "uvm_extern_phase_extract", 158 | "body": [ 159 | "// Function: extract_phase", 160 | "extern function void extract_phase(uvm_phase phase);\n$0" 161 | ], 162 | "description": "UVM extract_phase stub" 163 | }, 164 | "uvm_extern_check_phase": { 165 | "context": "meta.class.systemverilog", 166 | "prefix": "uvm_extern_phase_check", 167 | "body": [ 168 | "// Function: check_phase", 169 | "extern function void check_phase(uvm_phase phase);\n$0" 170 | ], 171 | "description": "UVM extract_phase stub" 172 | }, 173 | "uvm_extern_report_phase": { 174 | "context": "meta.class.systemverilog", 175 | "prefix": "uvm_extern_phase_report", 176 | "body": [ 177 | "// Function: report_phase", 178 | "extern function void report_phase(uvm_phase phase);\n$0" 179 | ], 180 | "description": "UVM report_phase stub" 181 | }, 182 | "uvm_extern_final_phase": { 183 | "context": "meta.class.systemverilog", 184 | "prefix": "uvm_extern_phase_final", 185 | "body": [ 186 | "// Function: final_phase", 187 | "extern function void final_phase(uvm_phase phase);\n$0" 188 | ], 189 | "description": "UVM report_phase stub" 190 | }, 191 | 192 | // UVM PHASE DEFINITIONS 193 | "uvm_build_phase": { 194 | "context": [ 195 | "meta.class.systemverilog", 196 | "source.systemverilog" 197 | ], 198 | "prefix": "uvm_phase_build", 199 | "body": [ 200 | "function void ${1:$TM_FILENAME_BASE}${2:::}build_phase(uvm_phase phase);", 201 | "\t/* note: Do not call super.build_phase() from any class that is extended from an UVM base class! */", 202 | "\t/* For more information see UVM Cookbook v1800.2 p.503 */", 203 | "\t$3//super.build_phase(phase);\n", 204 | "\t$0", 205 | "endfunction: build_phase\n" 206 | ], 207 | "description": "UVM build_phase template" 208 | }, 209 | "uvm_connect_phase": { 210 | "context": [ 211 | "meta.class.systemverilog", 212 | "source.systemverilog" 213 | ], 214 | "prefix": "uvm_phase_connect", 215 | "body": [ 216 | "function void ${1:$TM_FILENAME_BASE}${2:::}connect_phase(uvm_phase phase);", 217 | "\tsuper.connect_phase(phase);\n", 218 | "\t$0", 219 | "endfunction: connect_phase\n" 220 | ], 221 | "description": "UVM connect_phase template" 222 | }, 223 | "uvm_end_of_elaboration_phase": { 224 | "context": [ 225 | "meta.class.systemverilog", 226 | "source.systemverilog" 227 | ], 228 | "prefix": "uvm_phase_end_of_elaboration", 229 | "body": [ 230 | "function void ${1:$TM_FILENAME_BASE}${2:::}end_of_elaboration_phase(uvm_phase phase);", 231 | "\tsuper.end_of_elaboration_phase(phase);\n", 232 | "\t$0", 233 | "endfunction: end_of_elaboration_phase\n" 234 | ], 235 | "description": "UVM end_of_elaboration_phase template" 236 | }, 237 | 238 | "uvm_start_of_simulation_phase": { 239 | "context": [ 240 | "meta.class.systemverilog", 241 | "source.systemverilog" 242 | ], 243 | "prefix": "uvm_phase_start_of_simulation", 244 | "body": [ 245 | "function void ${1:$TM_FILENAME_BASE}${2:::}start_of_simulation_phase(uvm_phase phase);", 246 | "\tsuper.start_of_simulation_phase(phase);", 247 | "\t$0", 248 | "endfunction: start_of_simulation_phase\n" 249 | ], 250 | "description": "UVM start_of_simulation_phase template" 251 | }, 252 | "uvm_run_phase": { 253 | "context": [ 254 | "meta.class.systemverilog", 255 | "source.systemverilog" 256 | ], 257 | "prefix": "uvm_phase_run", 258 | "body": [ 259 | "task ${1:$TM_FILENAME_BASE}${2:::}run_phase(uvm_phase phase);", 260 | "\tphase.raise_objection(this);", 261 | "\t`uvm_info(${3|get_name(),get_full_name(),\"\"|}, \"${4:} started, objection raised.\", ${5|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})", 262 | "\n\t$0\n", 263 | "\tphase.drop_objection(this);", 264 | "\t`uvm_info($3, \"$4 finished, objection dropped.\", $5)", 265 | "endtask: run_phase\n" 266 | ], 267 | "description": "UVM run_phase template" 268 | }, 269 | "uvm_pre_reset_phase": { 270 | "context": [ 271 | "meta.class.systemverilog", 272 | "source.systemverilog" 273 | ], 274 | "prefix": "uvm_phase_pre_reset", 275 | "body": [ 276 | "task ${1:$TM_FILENAME_BASE}${2:::}pre_reset_phase(uvm_phase phase);", 277 | "\t$0", 278 | "endtask: pre_reset_phase\n" 279 | ], 280 | "description": "UVM pre_reset_phase template" 281 | }, 282 | "uvm_reset_phase": { 283 | "context": [ 284 | "meta.class.systemverilog", 285 | "source.systemverilog" 286 | ], 287 | "prefix": "uvm_phase_reset", 288 | "body": [ 289 | "task ${1:$TM_FILENAME_BASE}${2:::}reset_phase(uvm_phase phase);", 290 | "\tphase.raise_objection(this);", 291 | "\t`uvm_info(${3|get_name(),get_full_name(),\"\"|}, \"${4:} started, objection raised.\", ${5|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})", 292 | "\n\t$0\n", 293 | "\tphase.drop_objection(this);", 294 | "\t`uvm_info($3, \"$4 finished, objection dropped.\", $5)", 295 | "endtask: reset_phase\n" 296 | ], 297 | "description": "UVM reset_phase template" 298 | }, 299 | "uvm_post_reset_phase": { 300 | "context": [ 301 | "meta.class.systemverilog", 302 | "source.systemverilog" 303 | ], 304 | "prefix": "uvm_phase_post_reset", 305 | "body": [ 306 | "task ${1:$TM_FILENAME_BASE}${2:::}post_reset_phase(uvm_phase phase);", 307 | "\t$0", 308 | "endtask: post_reset_phase\n" 309 | ], 310 | "description": "UVM post_reset_phase template" 311 | }, 312 | "uvm_pre_configure_phase": { 313 | "context": [ 314 | "meta.class.systemverilog", 315 | "source.systemverilog" 316 | ], 317 | "prefix": "uvm_phase_pre_configure", 318 | "body": [ 319 | "task ${1:$TM_FILENAME_BASE}${2:::}pre_configure_phase(uvm_phase phase);", 320 | "\t$0", 321 | "endtask: pre_configure_phase\n" 322 | ], 323 | "description": "UVM pre_configure_phase template" 324 | }, 325 | "uvm_configure_phase": { 326 | "context": [ 327 | "meta.class.systemverilog", 328 | "source.systemverilog" 329 | ], 330 | "prefix": "uvm_phase_configure", 331 | "body": [ 332 | "task ${1:$TM_FILENAME_BASE}${2:::}configure_phase(uvm_phase phase);", 333 | "\tphase.raise_objection(this);", 334 | "\t`uvm_info(${3|get_name(),get_full_name(),\"\"|}, \"${4:} started, objection raised.\", ${5|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})", 335 | "\n\t$0\n", 336 | "\tphase.drop_objection(this);", 337 | "\t`uvm_info($3, \"$4 finished, objection dropped.\", $5)", 338 | "endtask: configure_phase\n" 339 | ], 340 | "description": "UVM post_configure_phase template" 341 | }, 342 | "uvm_post_configure_phase": { 343 | "context": [ 344 | "meta.class.systemverilog", 345 | "source.systemverilog" 346 | ], 347 | "prefix": "uvm_phase_post_configure", 348 | "body": [ 349 | "task ${1:$TM_FILENAME_BASE}${2:::}post_configure_phase(uvm_phase phase);", 350 | "\t$0", 351 | "endtask: post_configure_phase\n" 352 | ], 353 | "description": "UVM post_configure_phase template" 354 | }, 355 | "uvm_pre_main_phase": { 356 | "context": [ 357 | "meta.class.systemverilog", 358 | "source.systemverilog" 359 | ], 360 | "prefix": "uvm_phase_pre_main", 361 | "body": [ 362 | "task ${1:$TM_FILENAME_BASE}${2:::}pre_main_phase(uvm_phase phase);", 363 | "\t$0", 364 | "endtask: pre_main_phase\n" 365 | ], 366 | "description": "UVM pre_main_phase template" 367 | }, 368 | "uvm_main_phase": { 369 | "context": [ 370 | "meta.class.systemverilog", 371 | "source.systemverilog" 372 | ], 373 | "prefix": "uvm_phase_main", 374 | "body": [ 375 | "task ${1:$TM_FILENAME_BASE}${2:::}main_phase(uvm_phase phase);", 376 | "\tphase.raise_objection(this);", 377 | "\t`uvm_info(${3|get_name(),get_full_name(),\"\"|}, \"${4:} started, objection raised.\", ${5|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})", 378 | "\n\t$0\n", 379 | "\tphase.drop_objection(this);", 380 | "\t`uvm_info($3, \"$4 finished, objection dropped.\", $5)", 381 | "endtask: main_phase\n" 382 | ], 383 | "description": "UVM main_phase template" 384 | }, 385 | "uvm_post_main_phase": { 386 | "context": [ 387 | "meta.class.systemverilog", 388 | "source.systemverilog" 389 | ], 390 | "prefix": "uvm_phase_post_main", 391 | "body": [ 392 | "task ${1:$TM_FILENAME_BASE}${2:::}post_main_phase(uvm_phase phase);", 393 | "\t$0", 394 | "endtask: post_main_phase\n" 395 | ], 396 | "description": "UVM post_main_phase template" 397 | }, 398 | "uvm_pre_shutdown_phase": { 399 | "context": [ 400 | "meta.class.systemverilog", 401 | "source.systemverilog" 402 | ], 403 | "prefix": "uvm_phase_pre_shutdown", 404 | "body": [ 405 | "task ${1:$TM_FILENAME_BASE}${2:::}pre_shutdown_phase(uvm_phase phase);", 406 | "\t$0", 407 | "endtask: pre_shutdown_phase\n" 408 | ], 409 | "description": "UVM pre_shutdown_phase template" 410 | }, 411 | "uvm_shutdown_phase": { 412 | "context": [ 413 | "meta.class.systemverilog", 414 | "source.systemverilog" 415 | ], 416 | "prefix": "uvm_phase_shutdown", 417 | "body": [ 418 | "task ${1:$TM_FILENAME_BASE}${2:::}shutdown_phase(uvm_phase phase);", 419 | "\tphase.raise_objection(this);", 420 | "\t`uvm_info(${3|get_name(),get_full_name(),\"\"|}, \"${4:} started, objection raised.\", ${5|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})", 421 | "\n\t$0\n", 422 | "\tphase.drop_objection(this);", 423 | "\t`uvm_info($3, \"$4 finished, objection dropped.\", $5)", 424 | "endtask: shutdown_phase\n" 425 | ], 426 | "description": "UVM shutdown_phase template" 427 | }, 428 | "uvm_post_shutdown_phase": { 429 | "context": [ 430 | "meta.class.systemverilog", 431 | "source.systemverilog" 432 | ], 433 | "prefix": "uvm_phase_post_shutdown", 434 | "body": [ 435 | "task ${1:$TM_FILENAME_BASE}${2:::}post_shutdown_phase(uvm_phase phase);", 436 | "\t$0", 437 | "endtask: post_shutdown_phase\n" 438 | ], 439 | "description": "UVM post_shutdown_phase template" 440 | }, 441 | 442 | "uvm_extract_phase": { 443 | "context": [ 444 | "meta.class.systemverilog", 445 | "source.systemverilog" 446 | ], 447 | "prefix": "uvm_phase_extract", 448 | "body": [ 449 | "function void ${1:$TM_FILENAME_BASE}${2:::}extract_phase(uvm_phase phase);", 450 | "\tsuper.extract_phase(phase);", 451 | "\t$0", 452 | "endfunction: extract_phase\n" 453 | ], 454 | "description": "UVM extract_phase template" 455 | }, 456 | "uvm_check_phase": { 457 | "context": [ 458 | "meta.class.systemverilog", 459 | "source.systemverilog" 460 | ], 461 | "prefix": "uvm_phase_check", 462 | "body": [ 463 | "function void ${1:$TM_FILENAME_BASE}${2:::}check_phase(uvm_phase phase);", 464 | "\tsuper.check_phase(phase);", 465 | "\t$0", 466 | "endfunction: check_phase\n" 467 | ], 468 | "description": "UVM check_phase template" 469 | }, 470 | "uvm_report_phase": { 471 | "context": [ 472 | "meta.class.systemverilog", 473 | "source.systemverilog" 474 | ], 475 | "prefix": "uvm_phase_report", 476 | "body": [ 477 | "function void ${1:$TM_FILENAME_BASE}${2:::}report_phase(uvm_phase phase);", 478 | "\tsuper.report_phase(phase);", 479 | "\t$0", 480 | "endfunction: report_phase\n" 481 | ], 482 | "description": "UVM report_phase template" 483 | }, 484 | "uvm_final_phase": { 485 | "context": [ 486 | "meta.class.systemverilog", 487 | "source.systemverilog" 488 | ], 489 | "prefix": "uvm_phase_final", 490 | "body": [ 491 | "function void ${1:$TM_FILENAME_BASE}${2:::}final_phase(uvm_phase phase);", 492 | "\tsuper.final_phase(phase);", 493 | "\t$0", 494 | "endfunction: final_phase\n" 495 | ], 496 | "description": "UVM final_phase template" 497 | }, 498 | 499 | "uvm_objection_block": { 500 | "context": [ 501 | "meta.class.systemverilog", 502 | "source.systemverilog" 503 | ], 504 | "prefix": "uvm_objection_block", 505 | "body": [ 506 | "phase.raise_objection(this);", 507 | "`uvm_info(${1|get_name(),get_full_name(),\"\"|}, \"${2:} started, objection raised.\", ${3|UVM_NONE,UVM_LOW,UVM_MEDIUM,UVM_HIGH,UVM_FULL,UVM_DEBUG|})", 508 | "\n$0\n", 509 | "phase.drop_objection(this);", 510 | "`uvm_info($1, \"$2 finished, objection dropped.\", $3)", 511 | ], 512 | "description": "UVM raise_objection & drop_objection template" 513 | } 514 | 515 | 516 | } 517 | -------------------------------------------------------------------------------- /snippets/uvm_containers.json: -------------------------------------------------------------------------------- 1 | { 2 | "uvm_object": { 3 | "prefix": "uvm_object", 4 | "context": [ 5 | "meta.package.systemverilog", 6 | "source.systemverilog" 7 | ], 8 | "body": [ 9 | "// Class: $1", 10 | "//", 11 | "class ${1:$TM_FILENAME_BASE} extends ${2:uvm_object};", 12 | "\t`uvm_object_utils($1);\n", 13 | "\t// Group: Variables\n\n", 14 | "\t// Group: Constraints\n\n", 15 | "\t// Group: Functions\n", 16 | "\t// Constructor: new", 17 | "\tfunction new(string name = \"$1\");", 18 | "\t\tsuper.new(name);", 19 | "\tendfunction: new", 20 | "\t$0", 21 | "endclass: $1\n" 22 | ], 23 | "description": "UVM object class template" 24 | }, 25 | "uvm_object_with_parameters": { 26 | "prefix": "uvm_object_with_parameters", 27 | "context": [ 28 | "meta.package.systemverilog", 29 | "source.systemverilog" 30 | ], 31 | "body": [ 32 | "// Class: $1", 33 | "//", 34 | "class ${1:$TM_FILENAME_BASE} #(${2:parameters}) extends ${3:uvm_object};", 35 | "\ttypedef $1 #(${2/(\\b(parameter|type)\\s+([A-Za-z_][A-Za-z0-9_$]*)(\\s*=\\s*([A-Za-z0-9_$]+))?)*\\b/$3/g}) this_type_t;", 36 | "\t`uvm_object_param_utils(this_type_t);\n", 37 | "\t// Group: Variables\n\n", 38 | "\t// Group: Constraints\n\n", 39 | "\t// Group: Functions\n", 40 | "\t// Constructor: new", 41 | "\tfunction new(string name = \"$1\");", 42 | "\t\tsuper.new(name);", 43 | "\tendfunction: new", 44 | "\t$0", 45 | "endclass: $1\n" 46 | ], 47 | "description": "UVM parametrized object class template" 48 | }, 49 | 50 | "uvm_component": { 51 | "prefix": "uvm_component", 52 | "context": [ 53 | "meta.package.systemverilog", 54 | "source.systemverilog" 55 | ], 56 | "body": [ 57 | "// Class: $1", 58 | "//", 59 | "class ${1:$TM_FILENAME_BASE} extends ${2:uvm_component};", 60 | "\t`uvm_component_utils($1);\n", 61 | "\t// Group: Configuration Object(s)\n", 62 | "\t// Var: config_obj", 63 | "\t${3:config_obj_t} config_obj;\n\n", 64 | "\t// Group: Components\n\n", 65 | "\t// Group: Variables\n\n", 66 | "\t// Group: Functions\n", 67 | "\t// Constructor: new", 68 | "\tfunction new(string name = \"$1\", uvm_component parent);", 69 | "\t\tsuper.new(name, parent);", 70 | "\tendfunction: new\n", 71 | "\t$0", 72 | "endclass: $1\n" 73 | ], 74 | "description": "UVM component class template" 75 | }, 76 | "uvm_component_with_parameters": { 77 | "prefix": "uvm_component_with_parameters", 78 | "context": [ 79 | "meta.package.systemverilog", 80 | "source.systemverilog" 81 | ], 82 | "body": [ 83 | "// Class: $1", 84 | "//", 85 | "class ${1:$TM_FILENAME_BASE} #(${2:parameters}) extends ${3:uvm_component};", 86 | "\ttypedef $1 #(${2/(\\b(parameter|type)\\s+([A-Za-z_][A-Za-z0-9_$]*)(\\s*=\\s*([A-Za-z0-9_$]+))?)*\\b/$3/g}) this_type_t;", 87 | "\t`uvm_component_param_utils(this_type_t);\n", 88 | "\t// Group: Configuration Object(s)\n", 89 | "\t// Var: config_obj", 90 | "\t${4:config_obj_t} config_obj;\n\n", 91 | "\t// Group: Components\n\n", 92 | "\t// Group: Variables\n\n", 93 | "\t// Constructor: new", 94 | "\tfunction new(string name = \"$1\", uvm_component parent);", 95 | "\t\tsuper.new(name, parent);", 96 | "\tendfunction: new\n", 97 | "\t$0", 98 | "endclass: $1\n" 99 | ], 100 | "description": "UVM parametrized component class template" 101 | }, 102 | "uvm_component_extended": { 103 | "prefix": "uvm_component_extended", 104 | "context": [ 105 | "meta.package.systemverilog", 106 | "source.systemverilog" 107 | ], 108 | "body": [ 109 | "// Class: $1", 110 | "//", 111 | "class ${1:$TM_FILENAME_BASE} extends ${2:base_class};", 112 | "\t`uvm_component_utils($1);\n", 113 | "\t// Group: Configuration Object(s)\n\n", 114 | "\t// Group: Components\n\n", 115 | "\t// Group: Variables\n\n", 116 | "\t// Group: Functions\n", 117 | "\t// Constructor: new", 118 | "\tfunction new(string name = \"$1\", uvm_component parent);", 119 | "\t\tsuper.new(name, parent);", 120 | "\tendfunction: new\n", 121 | "\t/*--- UVM Build Phases ---*/", 122 | "\t/*------------------------------------*/", 123 | "\t// Function: build_phase", 124 | "\textern function void build_phase(uvm_phase phase);", 125 | "\t// Function: connect_phase", 126 | "\textern function void connect_phase(uvm_phase phase);", 127 | "\t// Function: end_of_elaboration_phase", 128 | "\textern function void end_of_elaboration_phase(uvm_phase phase);\n", 129 | "\t/*--- UVM Run Phases ---*/", 130 | "\t/*------------------------------------*/", 131 | "\t// Function: start_of_simulation_phase", 132 | "\textern function void start_of_simulation_phase(uvm_phase phase);", 133 | "\t// Function: reset_phase", 134 | "\textern task reset_phase(uvm_phase phase);", 135 | "\t// Function: configure_phase", 136 | "\textern task configure_phase(uvm_phase phase);", 137 | "\t// Function: main_phase", 138 | "\textern task main_phase(uvm_phase phase);", 139 | "\t// Function: shutdown_phase", 140 | "\textern task shutdown_phase(uvm_phase phase);\n", 141 | "\t/*--- UVM Cleanup Phases ---*/", 142 | "\t/*------------------------------------*/", 143 | "\t// Function: extract_phase", 144 | "\textern function void extract_phase(uvm_phase phase);", 145 | "\t// Function: report_phase", 146 | "\textern function void report_phase(uvm_phase phase);", 147 | "\t$0", 148 | "endclass: $1\n\n", 149 | "/*----------------------------------------------------------------------------*/", 150 | "/* UVM Build Phases */", 151 | "/*----------------------------------------------------------------------------*/", 152 | "function void $1::build_phase(uvm_phase phase);", 153 | "\t/* note: Do not call super.build_phase() from any class that is extended from an UVM base class! */", 154 | "\t/* For more information see UVM Cookbook v1800.2 p.503 */", 155 | "\t// super.build_phase(phase);", 156 | "endfunction: build_phase\n\n", 157 | "function void $1::connect_phase(uvm_phase phase);", 158 | "\tsuper.connect_phase(phase);", 159 | "endfunction: connect_phase\n\n", 160 | "function void $1::end_of_elaboration_phase(uvm_phase phase);", 161 | "\tsuper.end_of_elaboration_phase(phase);", 162 | "endfunction: end_of_elaboration_phase\n\n", 163 | "/*----------------------------------------------------------------------------*/", 164 | "/* UVM Run Phases */", 165 | "/*----------------------------------------------------------------------------*/", 166 | "function void $1::start_of_simulation_phase(uvm_phase phase);", 167 | "\tsuper.start_of_simulation_phase(phase);", 168 | "endfunction: start_of_simulation_phase\n\n", 169 | "task $1::reset_phase(uvm_phase phase);", 170 | "endtask: reset_phase\n\n", 171 | "task $1::configure_phase(uvm_phase phase);", 172 | "endtask: configure_phase\n\n", 173 | "task $1::main_phase(uvm_phase phase);", 174 | "endtask: main_phase\n\n", 175 | "task $1::shutdown_phase(uvm_phase phase);", 176 | "endtask: shutdown_phase\n\n", 177 | "/*----------------------------------------------------------------------------*/", 178 | "/* UVM Cleanup Phases */", 179 | "/*----------------------------------------------------------------------------*/", 180 | "function void $1::report_phase(uvm_phase phase);", 181 | "\tsuper.report_phase(phase);", 182 | "endfunction: report_phase\n\n", 183 | "function void $1::extract_phase(uvm_phase phase);", 184 | "\tsuper.extract_phase(phase);", 185 | "endfunction: extract_phase\n\n" 186 | ], 187 | "description": "UVM component class extended template" 188 | }, 189 | 190 | "uvm_sequence": { 191 | "prefix": "uvm_sequence", 192 | "context": [ 193 | "meta.package.systemverilog", 194 | "source.systemverilog" 195 | ], 196 | "body": [ 197 | "// Class: $1", 198 | "//", 199 | "class ${1:$TM_FILENAME_BASE} extends ${2:uvm_sequence};", 200 | "\t`uvm_object_utils($1);\n", 201 | "\t// Group: Variables\n\n", 202 | "\t// Group: Constraints\n\n", 203 | "\t// Group: Functions\n", 204 | "\t// Constructor: new", 205 | "\tfunction new(string name = \"$1\");", 206 | "\t\tsuper.new(name);", 207 | "\tendfunction: new\n", 208 | "\t// Task: pre_start", 209 | "\t// This task is a user-definable callback that is called before the optional ", 210 | "\t// execution of .", 211 | "\t// extern virtual task pre_start();\n", 212 | "\t// Task: pre_body", 213 | "\t// This task is a user-definable callback that is called before the execution ", 214 | "\t// of ~only~ when the sequence is started with .", 215 | "\t// If is called with ~call_pre_post~ set to 0, ~pre_body~ is not called.", 216 | "\t// extern virtual task pre_body();\n", 217 | "\t// Task: pre_do", 218 | "\t// This task is a user-definable callback task that is called ~on the parent ", 219 | "\t// sequence~, if any. The sequence has issued a wait_for_grant() call and after", 220 | "\t// the sequencer has selected this sequence, and before the item is randomized.", 221 | "\t//", 222 | "\t// Although pre_do is a task, consuming simulation cycles may result in unexpected", 223 | "\t// behavior on the driver.", 224 | "\t// extern virtual task pre_do(bit is_item);\n", 225 | "\t// Function: mid_do", 226 | "\t// This function is a user-definable callback function that is called after the ", 227 | "\t// sequence item has been randomized, and just before the item is sent to the ", 228 | "\t// driver.", 229 | "\t// extern virtual function void mid_do(uvm_sequence_item this_item);\n", 230 | "\t// Task: body", 231 | "\t// This is the user-defined task where the main sequence code resides.", 232 | "\textern virtual task body();\n", 233 | "\t// Function: post_do", 234 | "\t// This function is a user-definable callback function that is called after the ", 235 | "\t// driver has indicated that it has completed the item, using either this ", 236 | "\t// item_done or put methods. ", 237 | "\t// extern virtual function void post_do(uvm_sequence_item this_item);\n", 238 | "\t// Task: post_body", 239 | "\t// This task is a user-definable callback task that is called after the execution ", 240 | "\t// of ~only~ when the sequence is started with .", 241 | "\t// If is called with ~call_pre_post~ set to 0, ~post_body~ is not called.", 242 | "\t// extern virtual task post_body();\n", 243 | "\t// Task: post_start", 244 | "\t// This task is a user-definable callback that is called after the optional ", 245 | "\t// execution of .", 246 | "\t// extern virtual task post_start();", 247 | "\t$0", 248 | "endclass: $1" 249 | ], 250 | "description": "UVM sequence class template" 251 | }, 252 | "uvm_sequence_with_parameters": { 253 | "prefix": "uvm_sequence_with_parameters", 254 | "context": [ 255 | "meta.package.systemverilog", 256 | "source.systemverilog" 257 | ], 258 | "body": [ 259 | "// Class: $1", 260 | "//", 261 | "class ${1:$TM_FILENAME_BASE} #(${2:parameters}) extends ${3:uvm_sequence};", 262 | "\ttypedef $1 #(${2/(\\b(parameter|type)\\s+([A-Za-z_][A-Za-z0-9_$]*)(\\s*=\\s*([A-Za-z0-9_$]+))?)*\\b/$3/g}) this_type_t;", 263 | "\t`uvm_object_param_utils(this_type_t);\n", 264 | "\t// Group: Variables\n\n", 265 | "\t// Group: Constraints\n\n", 266 | "\t// Group: Functions\n", 267 | "\t// Constructor: new", 268 | "\tfunction new(string name = \"$1\");", 269 | "\t\tsuper.new(name);", 270 | "\tendfunction: new\n", 271 | "\t// Task: pre_start", 272 | "\t// This task is a user-definable callback that is called before the optional ", 273 | "\t// execution of .", 274 | "\t// extern virtual task pre_start();\n", 275 | "\t// Task: pre_body", 276 | "\t// This task is a user-definable callback that is called before the execution ", 277 | "\t// of ~only~ when the sequence is started with .", 278 | "\t// If is called with ~call_pre_post~ set to 0, ~pre_body~ is not called.", 279 | "\t// extern virtual task pre_body();\n", 280 | "\t// Task: pre_do", 281 | "\t// This task is a user-definable callback task that is called ~on the parent ", 282 | "\t// sequence~, if any. The sequence has issued a wait_for_grant() call and after", 283 | "\t// the sequencer has selected this sequence, and before the item is randomized.", 284 | "\t//", 285 | "\t// Although pre_do is a task, consuming simulation cycles may result in unexpected", 286 | "\t// behavior on the driver.", 287 | "\t// extern virtual task pre_do(bit is_item);\n", 288 | "\t// Function: mid_do", 289 | "\t// This function is a user-definable callback function that is called after the ", 290 | "\t// sequence item has been randomized, and just before the item is sent to the ", 291 | "\t// driver.", 292 | "\t// extern virtual function void mid_do(uvm_sequence_item this_item);\n", 293 | "\t// Task: body", 294 | "\t// This is the user-defined task where the main sequence code resides.", 295 | "\textern virtual task body();\n", 296 | "\t// Function: post_do", 297 | "\t// This function is a user-definable callback function that is called after the ", 298 | "\t// driver has indicated that it has completed the item, using either this ", 299 | "\t// item_done or put methods. ", 300 | "\t// extern virtual function void post_do(uvm_sequence_item this_item);\n", 301 | "\t// Task: post_body", 302 | "\t// This task is a user-definable callback task that is called after the execution ", 303 | "\t// of ~only~ when the sequence is started with .", 304 | "\t// If is called with ~call_pre_post~ set to 0, ~post_body~ is not called.", 305 | "\t// extern virtual task post_body();\n", 306 | "\t// Task: post_start", 307 | "\t// This task is a user-definable callback that is called after the optional ", 308 | "\t// execution of .", 309 | "\t// extern virtual task post_start();", 310 | "\t$0", 311 | "endclass: $1" 312 | ], 313 | "description": "UVM sequence class template with parameters" 314 | }, 315 | "uvm_sequence_functions": { 316 | "prefix": "uvm_sequence_functions", 317 | "context": [ 318 | "meta.package.systemverilog", 319 | "source.systemverilog" 320 | ], 321 | "body": [ 322 | "// task ${1:$TM_FILENAME_BASE::}pre_start();", 323 | "// endtask: pre_start\n\n", 324 | "// task $1pre_body();", 325 | "// endtask: pre_body\n\n", 326 | "// task $1pre_do(bit is_item);", 327 | "// endtask: pre_do\n\n", 328 | "// function void $1mid_do(uvm_sequence_item this_item);", 329 | "// endfunction: mid_do\n\n", 330 | "task $1body();", 331 | "\t$0", 332 | "endtask: body\n\n", 333 | "// function void $1post_do(uvm_sequence_item this_item);", 334 | "// endfunction: post_do\n\n", 335 | "// task $1post_body();", 336 | "// endtask: post_body\n\n", 337 | "// task $1post_start();", 338 | "// endtask: post_start\n" 339 | ], 340 | "description": "UVM Sequence class functions" 341 | }, 342 | 343 | "uvm_sequence_item": { 344 | "prefix": "uvm_sequence_item", 345 | "context": [ 346 | "meta.package.systemverilog", 347 | "source.systemverilog" 348 | ], 349 | "body": [ 350 | "// Class: $1", 351 | "//", 352 | "class ${1:$TM_FILENAME_BASE} extends ${2:uvm_sequence_item};", 353 | "\ttypedef $1 this_type_t;", 354 | "\t`uvm_object_utils($1);\n", 355 | "\t// Group: Variables\n\n", 356 | "\t// Group: Constraints\n\n", 357 | "\t// Group: Functions\n", 358 | "\t// Constructor: new", 359 | "\tfunction new(string name = \"$1\");", 360 | "\t\tsuper.new(name);", 361 | "\tendfunction: new\n", 362 | "\t// Function: do_copy", 363 | "\t// extern function void do_copy(uvm_object rhs);", 364 | "\t// Function: do_compare", 365 | "\t// extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);", 366 | "\t// Function: convert2string", 367 | "\t// extern function string convert2string();", 368 | "\t// Function: do_print", 369 | "\t// extern function void do_print(uvm_printer printer);", 370 | "\t// Function: do_record", 371 | "\t// extern function void do_record(uvm_recorder recorder);", 372 | "\t// Function: do_pack", 373 | "\t// extern function void do_pack();", 374 | "\t// Function: do_unpack", 375 | "\t// extern function void do_unpack();", 376 | "\t$0", 377 | "endclass: $1\n\n", 378 | "/*----------------------------------------------------------------------------*/", 379 | "/* Constraints */", 380 | "/*----------------------------------------------------------------------------*/", 381 | "\n\n\n", 382 | "/*----------------------------------------------------------------------------*/", 383 | "/* Functions */", 384 | "/*----------------------------------------------------------------------------*/", 385 | "\n" 386 | ], 387 | "description": "UVM sequence item class template" 388 | }, 389 | "uvm_sequence_item_with_parameters": { 390 | "prefix": "uvm_sequence_item_with_parameters", 391 | "context": [ 392 | "meta.package.systemverilog", 393 | "source.systemverilog" 394 | ], 395 | "body": [ 396 | "// Class: $1", 397 | "//", 398 | "class ${1:$TM_FILENAME_BASE} #(${2:parameters}) extends ${3:uvm_sequence_item};", 399 | "\ttypedef $1 #(${2/(\\b(parameter|type)\\s+([A-Za-z_][A-Za-z0-9_$]*)(\\s*=\\s*([A-Za-z0-9_$]+))?)*\\b/$3/g}) this_type_t;", 400 | "\t`uvm_object_param_utils(this_type_t);\n", 401 | "\t// Group: Variables\n\n", 402 | "\t// Group: Constraints\n\n", 403 | "\t// Group: Functions\n", 404 | "\t// Constructor: new", 405 | "\tfunction new(string name = \"$1\");", 406 | "\t\tsuper.new(name);", 407 | "\tendfunction: new\n", 408 | "\t// Function: do_copy", 409 | "\t// extern function void do_copy(uvm_object rhs);", 410 | "\t// Function: do_compare", 411 | "\t// extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);", 412 | "\t// Function: convert2string", 413 | "\t// extern function string convert2string();", 414 | "\t// Function: do_print", 415 | "\t// extern function void do_print(uvm_printer printer);", 416 | "\t// Function: do_record", 417 | "\t// extern function void do_record(uvm_recorder recorder);", 418 | "\t// Function: do_pack", 419 | "\t// extern function void do_pack();", 420 | "\t// Function: do_unpack", 421 | "\t// extern function void do_unpack();", 422 | "\t$0", 423 | "endclass: $1\n\n", 424 | "/*----------------------------------------------------------------------------*/", 425 | "/* Constraints */", 426 | "/*----------------------------------------------------------------------------*/", 427 | "\n\n\n", 428 | "/*----------------------------------------------------------------------------*/", 429 | "/* Functions */", 430 | "/*----------------------------------------------------------------------------*/", 431 | "\n" 432 | ], 433 | "description": "UVM parametrized sequence item class template" 434 | }, 435 | 436 | "uvm_sequence_item_do_copy": { 437 | "prefix": "uvm_sequence_item_do_copy", 438 | "context": [ 439 | "meta.class.systemverilog", 440 | "source.systemverilog" 441 | ], 442 | "body": [ 443 | "function void ${1:$TM_FILENAME_BASE}${2:::}do_copy(uvm_object rhs);", 444 | "\tthis_type_t rhs_;\n", 445 | "\tif (!\\$cast(rhs_, rhs)) begin", 446 | "\t\t`uvm_error({this.get_name(), \".do_copy()\"}, \"Cast failed!\");", 447 | "\t\treturn;", 448 | "\tend", 449 | "\t// `uvm_info({this.get_name(), \".do_copy()\"}, \"Cast succeded.\", UVM_HIGH);\n", 450 | "\t/* chain the copy with parent classes */", 451 | "\tsuper.do_copy(rhs);\n", 452 | "\t/* list of local properties to be copied */", 453 | "\t// ;", 454 | "endfunction: do_copy\n\n$0" 455 | ], 456 | "description": "UVM sequence item do_copy() stub" 457 | }, 458 | "uvm_sequence_item_do_compare": { 459 | "prefix": "uvm_sequence_item_do_compare", 460 | "context": [ 461 | "meta.class.systemverilog", 462 | "source.systemverilog" 463 | ], 464 | "body": [ 465 | "function bit ${1:$TM_FILENAME_BASE}${2:::}do_compare(uvm_object rhs, uvm_comparer comparer);", 466 | "\tthis_type_t rhs_;\n", 467 | "\tif (!\\$cast(rhs_, rhs)) begin", 468 | "\t\t`uvm_error({this.get_name(), \".do_compare()\"}, \"Cast failed!\");", 469 | "\t\treturn;", 470 | "\tend", 471 | "\t// `uvm_info({this.get_name(), \".do_compare()\"}, \"Cast succeded.\", UVM_HIGH);\n", 472 | "\t/* chain the compare with parent classes */", 473 | "\tdo_compare = super.do_compare(rhs, comparer);\n", 474 | "\t/* list of local properties to be compared: */", 475 | "\tdo_compare &= (", 476 | "\t\t// &&", 477 | "\t\t// ", 478 | "\t);", 479 | "endfunction: do_compare\n\n$0" 480 | ], 481 | "description": "UVM sequence item do_compare() stub" 482 | }, 483 | "uvm_sequence_item_convert2string": { 484 | "prefix": "uvm_sequence_item_convert2string", 485 | "context": [ 486 | "meta.class.systemverilog", 487 | "source.systemverilog" 488 | ], 489 | "body": [ 490 | "function string ${1:$TM_FILENAME_BASE}${2:::}convert2string();", 491 | "\tstring s;\n", 492 | "\t/* chain the convert2string with parent classes */", 493 | "\ts = super.convert2string();\n", 494 | "\t/* list of local properties to be printed: */", 495 | "\t// guide 0---4---8--12--16--20--24--28--32--36--40--44--48--", 496 | "\t// s = {s, \\$sformatf(\"property_label : 0x%0h\\n\", property_name)};", 497 | "\t// s = {s, \\$sformatf(\"property_label : %0d\\n\", property_name)};\n", 498 | "\treturn s;", 499 | "endfunction: convert2string\n\n$0" 500 | ], 501 | "description": "UVM sequence item convert2string() stub" 502 | }, 503 | "uvm_sequence_item_do_print": { 504 | "prefix": "uvm_sequence_item_do_print", 505 | "context": [ 506 | "meta.class.systemverilog", 507 | "source.systemverilog" 508 | ], 509 | "body": [ 510 | "function void ${1:$TM_FILENAME_BASE}${2:::}do_print(uvm_printer printer)", 511 | "\t/* chain the print with parent classes */", 512 | "\tsuper.do_print(printer);\n", 513 | "\t/* list of local properties to be printed: */", 514 | "\t// printer.print_string(\"property_label\", property_name);", 515 | "\t// printer.print_field_int(\"property_label\", property_name, \\$bits(property_name), UVM_HEX);", 516 | "endfunction: do_print\n\n$0" 517 | ], 518 | "description": "UVM sequence item do_print() stub" 519 | }, 520 | "uvm_sequence_item_do_record": { 521 | "prefix": "uvm_sequence_item_do_record", 522 | "context": [ 523 | "meta.class.systemverilog", 524 | "source.systemverilog" 525 | ], 526 | "body": [ 527 | "function void ${1:$TM_FILENAME_BASE}${2:::}do_record(uvm_recorder recorder);", 528 | "\t/* chain the record with parent classes */", 529 | "\tsuper.do_record(recorder);\n", 530 | "\t/* list of local properties to be recorded: */", 531 | "\t/* note: use uvm_record_int, uvm_record_string, uvm_record_time, uvm_record_real for known basic types. */", 532 | "\t// `uvm_record_string(\"property_label\", property_name);", 533 | "\t// `uvm_record_int(\"property_label\", property_name, \\$bits(property_name), UVM_HEX);", 534 | "endfunction: do_record\n\n$0" 535 | ], 536 | "description": "UVM sequence item do_record() stub" 537 | }, 538 | "uvm_sequence_item_do_pack": { 539 | "prefix": "uvm_sequence_item_do_pack", 540 | "context": [ 541 | "meta.class.systemverilog", 542 | "source.systemverilog" 543 | ], 544 | "body": [ 545 | "function void ${1:$TM_FILENAME_BASE}${2:::}do_pack(uvm_packer packer);", 546 | "\t/* chain the pack with parent classes */", 547 | "\tsuper.do_pack(packer);\n", 548 | "\t/* list of local properties to be packed: */", 549 | "\t// note: look up the appropriate macro(s) for your properties!", 550 | "\t// `uvm_pack_int(property_name);", 551 | "\t// `uvm_pack_queue(property_name);", 552 | "\t// `uvm_pack_string(property_name);", 553 | "endfunction: do_pack\n\n$0" 554 | ], 555 | "description": "Compresses object contents into a bit format." 556 | }, 557 | "uvm_sequence_item_do_unpack": { 558 | "prefix": "uvm_sequence_item_do_unpack", 559 | "context": [ 560 | "meta.class.systemverilog", 561 | "source.systemverilog" 562 | ], 563 | "body": [ 564 | "function void ${1:$TM_FILENAME_BASE}${2:::}do_unpack(uvm_packer packer);", 565 | "\t/* chain the unpack with parent classes */", 566 | "\tsuper.do_unpack(packer);\n", 567 | "\t/* list of local properties to be unpacked: */", 568 | "\t// note: look up the appropriate macro(s) for your properties!", 569 | "\t// `uvm_unpack_int(property_name);", 570 | "\t// `uvm_unpack_queue(property_name);", 571 | "\t// `uvm_unpack_string(property_name);", 572 | "endfunction: do_unpack\n\n$0" 573 | ], 574 | "description": "Converts a bit format into the data object format." 575 | } 576 | 577 | } 578 | --------------------------------------------------------------------------------