├── README.md ├── p00_Getting_Started └── c00 │ ├── s01_one.v │ └── s02_zero.v ├── p02_Cirucuits ├── c06_Basic_Gates │ ├── s02_m2014_q4i.v │ ├── s01_m2014_q4h.v │ ├── s10_mt2015_q4a.v │ ├── s11_mt2015_q4b.v │ ├── s03_m2014_q4e.v │ ├── s04_m2014_q4f.v │ ├── s09_mt2015_eq2.v │ ├── s05_m2014_q4g.v │ ├── s13_ringer.v │ ├── s07_7420.v │ ├── s14_thermostat.v │ ├── s16_gatesv.v │ ├── s06_gates.v │ ├── s17_gatesv100.v │ ├── s15_popcount3.v │ ├── s08_truthtable1.v │ └── s12_mt2015_q4.v ├── c08_Arithmetic_Circuits │ ├── s01_hadd.v │ ├── s02_fadd.v │ ├── s06_adder100.v │ ├── s05_ece241_2014_q1c.v │ ├── s07_bcdadd4.v │ ├── s03_adder3.v │ └── s04_m2014_q4j.v ├── c09_Karnaugh_Map_to_Circuit │ ├── s01_kmap1.v │ ├── s06_m2014_q3.v │ ├── s07_2012_q1g.v │ ├── s08_ece241_2014_q3.v │ ├── s02_kmap2.v │ ├── s03_kmap3.v │ ├── s05_ece241_2013_q2.v │ └── s04_kmap4.v ├── c07_Multiplexers │ ├── s01_mux2to1.v │ ├── s04_mux256to1.v │ ├── s02_mux2to1v.v │ ├── s05_mux256to1v.v │ └── s03_mux9to1v.v ├── c10_Latches_and_Flip_Flops │ ├── s01_dff.v │ ├── s02_dff8.v │ ├── s13_ece241_2014_q4.v │ ├── s07_m2014_q4a.v │ ├── s11_mt2015_muxdff.v │ ├── s10_m2014_q4d.v │ ├── s09_m2014_q4c.v │ ├── s08_m2014_q4b.v │ ├── s03_dff8r.v │ ├── s04_dff8p.v │ ├── s05_dff8ar.v │ ├── s14_ece241_2013_q7.v │ ├── s12_2014_q4a.v │ ├── s15_edgedetect.v │ ├── s16_edgedetect2.v │ ├── s18_dualedge.v │ ├── s06_dff16e.v │ └── s17_edgecapture.v ├── c11_Counters │ ├── s01_count15.v │ ├── s02_count10.v │ ├── s03_count1to10.v │ ├── s04_countslow.v │ ├── s06_ece241_2014_q7b.v │ ├── s05_ece241_2014_q7a.v │ ├── s07_countbcd.v │ └── s08_count_clock.v ├── c12_Shift_Registers │ ├── s07_m2014_q4k.v │ ├── s04_lfsr5.v │ ├── s01_shift4.v │ ├── s02_rotate100.v │ ├── s06_lfsr32.v │ ├── s03_shift18.v │ ├── s09_ece241_2013_q12.v │ ├── s05_mt2015_lfsr.v │ └── s08_2014_q4b.v ├── c14_Finite_State_Machines │ ├── s28_m2014_q6c.v │ ├── s06_fsm3onehot.v │ ├── s04_fsm2s.v │ ├── s01_fsm1.v │ ├── s03_fsm2.v │ ├── s05_fsm3comb.v │ ├── s23_ece241_2014_q5b.v │ ├── s10_lemmings1.v │ ├── s22_ece241_2014_q5a.v │ ├── s08_fsm3s.v │ ├── s02_fsm1s.v │ ├── s07_fsm3.v │ ├── s27_m2014_q6b.v │ ├── s21_ece241_2013_q8.v │ ├── s26_2014_q3c.v │ ├── s25_2014_q3bfsm.v │ ├── s29_m2014_q6.v │ ├── s30_2012_q2fsm.v │ ├── s31_2012_q2b.v │ ├── s15_fsm_ps2.v │ ├── s32_2013_q2afsm.v │ ├── s24_2014_q3fsm.v │ ├── s14_fsm_onehot.v │ ├── s16_fsm_ps2data.v │ ├── s11_lemmings2.v │ ├── s17_fsm_serial.v │ ├── s33_2013_q2bfsm.v │ ├── s20_fsm_hdlc.v │ ├── s09_ece241_2013_q4.v │ ├── s18_fsm_serialdata.v │ ├── s12_lemmings3.v │ ├── s19_fsm_serialdp.v │ └── s13_lemmings4.v ├── c15_Building_Larger_Circuits │ ├── s01_count1k.v │ ├── s02_shiftcount.v │ ├── s04_fsmshift.v │ ├── s03_fsmseq.v │ ├── s07_fsmonehot.v │ ├── s05_fsm.v │ └── s06_fancytimer.v └── c13_More_Circuits │ ├── s01_rule90.v │ ├── s02_rule110.v │ └── s03_conwaylife.v ├── p01_Verilog_Language ├── c01_Basics │ ├── s01_wire.v │ ├── s03_notgate.v │ ├── s04_andgate.v │ ├── s05_norgate.v │ ├── s06_xnorgate.v │ ├── s02_wire4.v │ ├── s07_wire_decl.v │ └── s08_7458.v ├── c02_Vectors │ ├── s08_vector4.v │ ├── s03_vector2.v │ ├── s02_vector1.v │ ├── s05_gates4.v │ ├── s07_vectorr.v │ ├── s09_vector5.v │ ├── s01_vector0.v │ ├── s04_vectorgates.v │ └── s06_vector3.v ├── c05_More_Verilog_Features │ ├── s02_reduction.v │ ├── s03_gate100.v │ ├── s04_vector100r.v │ ├── s05_popcount255.v │ ├── s01_conditional.v │ ├── s06_adder100i.v │ └── s07_bcdadd100.v ├── c03_Modules │ ├── s01_module.v │ ├── s02_module_pos.v │ ├── s03_module_name.v │ ├── s04_module_shift.v │ ├── s06_module_add.v │ ├── s09_module_addsub.v │ ├── s05_module_shift8.v │ ├── s07_module_fadd.v │ └── s08_module_cseladd.v └── c04_Procedures │ ├── s01_alwaysblock1.v │ ├── s03_always_if.v │ ├── s02_alwaysblock2.v │ ├── s07_always_casez.v │ ├── s04_always_if2.v │ ├── s08_always_nolatches.v │ ├── s05_always_case.v │ └── s06_always_case2.v ├── p03_Verification_Reading_Simulations ├── c16_Finding_bugs_in_code │ ├── s01_mux2.v │ ├── s04_addsubz.v │ ├── s02_nand3.v │ ├── s05_case.v │ └── s03_mux4.v └── c17_Build_a_circurt_from_a_simulation_waveform │ ├── s07_circuit7.v │ ├── s01_circuit1.v │ ├── s08_circuit8.v │ ├── s09_circuit9.v │ ├── s04_circuit4.v │ ├── s05_circuit5.v │ ├── s06_circuit6.v │ ├── s03_circuit3.v │ ├── s10_circuit10.v │ └── s02_circuit2.v ├── p04_Verification_Writing_Testbenches ├── s01_clock.v ├── s03_and.v ├── s02_tb1.v ├── s05_tff.v └── s04_tb2.v └── LICENSE /README.md: -------------------------------------------------------------------------------- 1 | # hdlbits -------------------------------------------------------------------------------- /p00_Getting_Started/c00/s01_one.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Step_one 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | output one 11 | ); 12 | 13 | assign one = 1'b1; 14 | 15 | endmodule -------------------------------------------------------------------------------- /p00_Getting_Started/c00/s02_zero.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Zero 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | output zero 11 | ); 12 | 13 | assign zero = 1'b0; 14 | 15 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s02_m2014_q4i.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4i 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | output out 11 | ); 12 | 13 | assign out = 1'b0; 14 | 15 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s01_wire.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Wire 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input in, 11 | output out 12 | ); 13 | 14 | assign out = in; 15 | 16 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s03_notgate.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Notgate 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input in, 11 | output out 12 | ); 13 | 14 | assign out = ~in; 15 | 16 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s01_m2014_q4h.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4h 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input in, 11 | output out 12 | ); 13 | 14 | assign out = in; 15 | 16 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s04_andgate.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Andgate 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | 15 | assign out = a & b; 16 | 17 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s05_norgate.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Norgate 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | 15 | assign out = ~(a | b); 16 | 17 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s06_xnorgate.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Xnorgate 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | 15 | assign out = ~(a ^ b); 16 | 17 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s10_mt2015_q4a.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mt2015_q4a 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input x, 11 | input y, 12 | output z 13 | ); 14 | 15 | assign z = (x ^ y) & x; 16 | 17 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s11_mt2015_q4b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mt2015_q4b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input x, 11 | input y, 12 | output z 13 | ); 14 | 15 | assign z = (x == y); 16 | 17 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s08_vector4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vector4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [7:0] in, 11 | output [31:0] out 12 | ); 13 | 14 | assign out = {{24{in[7]}}, in}; 15 | 16 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s02_reduction.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Reduction 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [7:0] in, 11 | output parity 12 | ); 13 | 14 | assign parity = ^in; 15 | 16 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s03_m2014_q4e.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4e 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input in1, 11 | input in2, 12 | output out 13 | ); 14 | 15 | assign out = ~(in1 | in2); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s04_m2014_q4f.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4f 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input in1, 11 | input in2, 12 | output out 13 | ); 14 | 15 | assign out = in1 & ~in2; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s09_mt2015_eq2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mt2015_eq2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [1:0] A, 11 | input [1:0] B, 12 | output z 13 | ); 14 | 15 | assign z = (A == B); 16 | 17 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s01_hadd.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Hadd 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | output cout, 13 | output sum 14 | ); 15 | 16 | assign {cout, sum} = a + b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s01_kmap1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Kmap1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | output out 14 | ); 15 | 16 | assign out = a | b | c; 17 | 18 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s03_vector2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vector2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [31:0] in, 11 | output [31:0] out 12 | ); 13 | 14 | assign out = {in[7:0], in[15:8], in[23:16], in[31:24]}; 15 | 16 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c07_Multiplexers/s01_mux2to1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mux2to1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input sel, 13 | output out 14 | ); 15 | 16 | assign out = sel ? b : a; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /p02_Cirucuits/c07_Multiplexers/s04_mux256to1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mux256to1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [255:0] in, 11 | input [7:0] sel, 12 | output out 13 | ); 14 | 15 | assign out = in[sel]; 16 | 17 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s06_m2014_q3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [4:1] x, 11 | output f 12 | ); 13 | 14 | assign f = (~x[1] & x[3]) | (x[2] & x[4]); 15 | 16 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s05_m2014_q4g.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4g 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input in1, 11 | input in2, 12 | input in3, 13 | output out 14 | ); 15 | 16 | assign out = ~(in1 ^ in2) ^ in3; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s01_dff.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dff 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input d, 12 | output reg q 13 | ); 14 | 15 | always @(posedge clk) begin 16 | q <= d; 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s02_fadd.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fadd 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input cin, 13 | output cout, 14 | output sum 15 | ); 16 | 17 | assign {cout, sum} = a + b + cin; 18 | 19 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s07_2012_q1g.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2012_q1g 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [4:1] x, 11 | output f 12 | ); 13 | 14 | assign f = (~x[1] & x[3]) | (~x[2] & ~x[4]) | (x[2] & x[3] & x[4]); 15 | 16 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c07_Multiplexers/s02_mux2to1v.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mux2to1v 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [99:0] a, 11 | input [99:0] b, 12 | input sel, 13 | output [99:0] out 14 | ); 15 | 16 | assign out = sel ? b : a; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s02_vector1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vector1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input wire [15:0] in, 11 | output wire [7:0] out_hi, 12 | output wire [7:0] out_lo 13 | ); 14 | 15 | assign out_hi = in[15:8]; 16 | assign out_lo = in[7:0]; 17 | 18 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c16_Finding_bugs_in_code/s01_mux2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bugs_mux2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input sel, 11 | input [7:0] a, 12 | input [7:0] b, 13 | output [7:0] out 14 | ); 15 | 16 | assign out = sel ? a : b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s13_ringer.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Ringer 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input ring, 11 | input vibrate_mode, 12 | output ringer, 13 | output motor 14 | ); 15 | 16 | assign motor = ring & vibrate_mode; 17 | assign ringer = ring & ~vibrate_mode; 18 | 19 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s01_module.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | output out 13 | ); 14 | 15 | mod_a mod_a_u1 ( 16 | .in1 ( a ), 17 | .in2 ( b ), 18 | .out ( out ) 19 | ); 20 | 21 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c07_Multiplexers/s05_mux256to1v.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mux256to1v 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input [1023:0] in, 11 | input [7:0] sel, 12 | output [3:0] out 13 | ); 14 | 15 | assign out = {in[{sel, 2'b11}], in[{sel, 2'b10}], in[{sel, 2'b01}], in[{sel, 2'b00}]}; 16 | 17 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s06_adder100.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Adder100 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [99:0] a, 11 | input [99:0] b, 12 | input cin, 13 | output cout, 14 | output [99:0] sum 15 | ); 16 | 17 | assign {cout, sum} = a + b + {99'b0, cin}; 18 | 19 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s05_gates4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Gates4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [3:0] in, 11 | output out_and, 12 | output out_or, 13 | output out_xor 14 | ); 15 | 16 | assign out_and = ∈ 17 | assign out_or = |in; 18 | assign out_xor = ^in; 19 | 20 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s02_dff8.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dff8 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [7:0] d, 12 | output [7:0] q 13 | ); 14 | 15 | reg [7:0] q_r; 16 | always @(posedge clk ) begin 17 | q_r <= d; 18 | end 19 | 20 | assign q = q_r; 21 | 22 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s02_wire4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Wire4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | output w, 14 | output x, 15 | output y, 16 | output z 17 | ); 18 | 19 | assign w = a; 20 | assign x = b; 21 | assign y = b; 22 | assign z = c; 23 | 24 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s07_vectorr.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vectorr 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [7:0] in, 11 | output [7:0] out 12 | ); 13 | 14 | genvar i; 15 | generate 16 | for (i = 0; i < 8; i = i + 1) begin : loop 17 | assign out[i] = in[7-i]; 18 | end 19 | endgenerate 20 | 21 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s03_gate100.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Gates100 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [99:0] in, 11 | output out_and, 12 | output out_or, 13 | output out_xor 14 | ); 15 | 16 | assign out_and = ∈ 17 | assign out_or = |in; 18 | assign out_xor = ^in; 19 | 20 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s05_ece241_2014_q1c.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q1c 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [7:0] a, 11 | input [7:0] b, 12 | output [7:0] s, 13 | output overflow 14 | ); 15 | 16 | assign s = a + b; 17 | assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]); 18 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s04_vector100r.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/vector100r 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [99:0] in, 11 | output [99:0] out 12 | ); 13 | 14 | generate 15 | genvar i; 16 | for (i = 0; i < 100; i = i + 1) begin : loop 17 | assign out[i] = in[99-i]; 18 | end 19 | endgenerate 20 | 21 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s07_circuit7.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit7 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input a, 12 | output q 13 | ); 14 | 15 | reg r; 16 | 17 | always @(posedge clk) begin 18 | r <= ~a; 19 | end 20 | 21 | assign q = r; 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s09_vector5.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vector5 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | input e, 15 | output [24:0] out 16 | ); 17 | 18 | assign out = ~{{5{a, b, c, d, e}}} ^ {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}}; 19 | 20 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s13_ece241_2014_q4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input x, 12 | output z 13 | ); 14 | 15 | reg [2:0] q_r; 16 | always @(posedge clk) begin 17 | q_r <= {~q_r[2] | x, ~q_r[1] & x, q_r[0] ^ x}; 18 | end 19 | 20 | assign z = ~|q_r; 21 | 22 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s07_m2014_q4a.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4a 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input d, 11 | input ena, 12 | output reg q 13 | ); 14 | 15 | always @(*) begin 16 | // 17 | // This latch is intended 18 | // 19 | if (ena) 20 | q = d; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s02_module_pos.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_pos 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out1, 15 | output out2 16 | ); 17 | 18 | mod_a mod_a_i0 ( 19 | out1, 20 | out2, 21 | a, 22 | b, 23 | c, 24 | d 25 | ); 26 | 27 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s08_ece241_2014_q3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input c, 11 | input d, 12 | output [3:0] mux_in 13 | ); 14 | 15 | assign mux_in[0] = c ? 1'b1 : d; 16 | assign mux_in[1] = 1'b0; 17 | assign mux_in[2] = ~d; 18 | assign mux_in[3] = c ? d : 1'b0; 19 | 20 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s11_mt2015_muxdff.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mt2015_muxdff 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input L, 12 | input r_in, 13 | input q_in, 14 | output reg Q 15 | ); 16 | 17 | always @(posedge clk) begin 18 | if (L) 19 | Q <= r_in; 20 | else 21 | Q <= q_in; 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s02_kmap2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Kmap2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out 15 | ); 16 | 17 | assign out = (~a & ~d) | 18 | ( ~b & ~c ) | 19 | (~a & b & c ) | 20 | ( a & & c & d); 21 | 22 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s01_vector0.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vector0 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input wire [2:0] vec, 11 | output wire [2:0] outv, 12 | output wire o2, 13 | output wire o1, 14 | output wire o0 15 | ); 16 | 17 | assign outv = vec; 18 | 19 | assign o0 = vec[0]; 20 | assign o1 = vec[1]; 21 | assign o2 = vec[2]; 22 | 23 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s07_wire_decl.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Wire_decl 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out, 15 | output out_n 16 | ); 17 | 18 | wire m; 19 | assign m = a & b; 20 | 21 | wire n; 22 | assign n = c & d; 23 | 24 | assign out = m | n; 25 | 26 | assign out_n = ~out; 27 | 28 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s04_vectorgates.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vectorgates 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [2:0] a, 11 | input [2:0] b, 12 | output [2:0] out_or_bitwise, 13 | output out_or_logical, 14 | output [5:0] out_not 15 | ); 16 | 17 | assign out_or_bitwise = a | b; 18 | assign out_or_logical = | (a | b); 19 | assign out_not = {~b, ~a}; 20 | 21 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s10_m2014_q4d.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4d 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input in, 12 | output out 13 | ); 14 | 15 | reg out_r; 16 | wire out_next; 17 | always @(posedge clk ) begin 18 | out_r <= out_next; 19 | end 20 | 21 | assign out_next = in ^ out_r; 22 | 23 | assign out = out_r; 24 | 25 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s09_m2014_q4c.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4c 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | 10 | module top_module ( 11 | input clk, 12 | input d, 13 | input r, 14 | output q 15 | ); 16 | 17 | reg q_r; 18 | always @(posedge clk) begin 19 | if (r) 20 | q_r <= '0; 21 | else 22 | q_r <= d; 23 | end 24 | 25 | assign q = q_r; 26 | 27 | endmodule -------------------------------------------------------------------------------- /p04_Verification_Writing_Testbenches/s01_clock.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Tb/clock 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | `timescale 1ps/1ps 10 | 11 | module top_module ( ); 12 | 13 | localparam CLK_PERIOD = 10; 14 | 15 | reg clk; 16 | initial begin 17 | clk = 1'b0; 18 | 19 | forever 20 | #(CLK_PERIOD / 2) clk = ~clk; 21 | end 22 | 23 | 24 | dut dut_u0 ( 25 | .clk ( clk ) 26 | ); 27 | 28 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s07_7420.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/7420 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input p1a, 11 | input p1b, 12 | input p1c, 13 | input p1d, 14 | output p1y, 15 | input p2a, 16 | input p2b, 17 | input p2c, 18 | input p2d, 19 | output p2y 20 | ); 21 | 22 | assign p1y = ~(p1a & p1b & p1c & p1d); 23 | assign p2y = ~(p2a & p2b & p2c & p2d); 24 | 25 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s08_m2014_q4b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input d, 12 | input ar, 13 | output q 14 | ); 15 | 16 | reg q_r; 17 | always @(posedge clk, posedge ar) begin 18 | if (ar) 19 | q_r <= '0; 20 | else 21 | q_r <= d; 22 | end 23 | 24 | assign q = q_r; 25 | 26 | endmodule -------------------------------------------------------------------------------- /p04_Verification_Writing_Testbenches/s03_and.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Tb/and 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | `timescale 1ps/1ps 10 | 11 | module top_module ( ); 12 | 13 | reg [1:0] in; 14 | wire out; 15 | 16 | andgate andgate_u0 ( 17 | .in ( in ), 18 | .out ( out ) 19 | ); 20 | 21 | initial begin 22 | in = 2'b00; 23 | 24 | repeat (3) #10 in = in + 1'b1; 25 | end 26 | 27 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c02_Vectors/s06_vector3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Vector3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [4:0] a, 11 | input [4:0] b, 12 | input [4:0] c, 13 | input [4:0] d, 14 | input [4:0] e, 15 | input [4:0] f, 16 | output [7:0] w, 17 | output [7:0] x, 18 | output [7:0] y, 19 | output [7:0] z 20 | ); 21 | 22 | assign {w, x, y, z } = {a, b, c, d, e, f, 2'b11}; 23 | 24 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s14_thermostat.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Thermostat 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input too_cold, 11 | input too_hot, 12 | input mode, 13 | input fan_on, 14 | output heater, 15 | output aircon, 16 | output fan 17 | ); 18 | 19 | assign heater = mode & too_cold; 20 | assign aircon = ~mode & too_hot; 21 | assign fan = fan_on | (heater | aircon); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s01_count15.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Count15 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | output [3:0] q 13 | ); 14 | 15 | reg [3:0] counter; 16 | always @(posedge clk) begin 17 | if (reset) 18 | counter <= '0; 19 | else 20 | counter <= counter + 1'b1; 21 | end 22 | 23 | assign q = counter; 24 | 25 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s01_alwaysblock1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Alwaysblock1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input a, 12 | input b, 13 | output wire out_assign, 14 | output reg out_alwaysblock 15 | ); 16 | 17 | assign out_assign = a & b; 18 | 19 | always @(*) begin 20 | out_alwaysblock = a & b; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s03_dff8r.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dff8r 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input [7:0] d, 13 | output [7:0] q 14 | ); 15 | 16 | reg [7:0] q_r; 17 | always @(posedge clk) begin 18 | if (reset) 19 | q_r <= '0; 20 | else 21 | q_r <= d; 22 | end 23 | 24 | assign q = q_r; 25 | 26 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s04_dff8p.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dff8p 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input [7:0] d, 13 | output [7:0] q 14 | ); 15 | 16 | reg [7:0] q_r; 17 | always @(negedge clk) begin 18 | if (reset) 19 | q_r <= 8'h34; 20 | else 21 | q_r <= d; 22 | end 23 | 24 | assign q = q_r; 25 | 26 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s03_kmap3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Kmap3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out 15 | ); 16 | 17 | assign out = ( a ) | 18 | ( ~b & c ); 19 | 20 | /* verilator lint_off UNUSED */ 21 | wire [0:0] unused; 22 | assign unused = {d}; 23 | /* verilator lint_on UNUSED */ 24 | 25 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s05_dff8ar.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dff8ar 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input [7:0] d, 13 | output [7:0] q 14 | ); 15 | 16 | reg [7:0] q_r; 17 | always @(posedge clk, posedge areset) begin 18 | if (areset) 19 | q_r <= '0; 20 | else 21 | q_r <= d; 22 | end 23 | 24 | assign q = q_r; 25 | 26 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c16_Finding_bugs_in_code/s04_addsubz.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bugs_addsubz 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input do_sub, 11 | input [7:0] a, 12 | input [7:0] b, 13 | output reg [7:0] out, 14 | output reg result_is_zero 15 | ); 16 | 17 | always @(*) begin 18 | out = a + (do_sub ? -b : b); 19 | 20 | result_is_zero = !(|out); 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /p04_Verification_Writing_Testbenches/s02_tb1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Tb/clock 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | `timescale 1ps/1ps 10 | 11 | module top_module ( 12 | output reg A, 13 | output reg B 14 | ); 15 | 16 | initial begin 17 | A = 1'b0; 18 | B = 1'b0; 19 | 20 | # 10 21 | A = 1'b1; 22 | 23 | # 5 24 | B = 1'b1; 25 | 26 | # 5 27 | A = 1'b0; 28 | 29 | # 20 30 | B = 1'b0; 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s05_popcount255.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/popcount255 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [254:0] in, 11 | output [7:0] out 12 | ); 13 | 14 | integer i; 15 | reg [7:0] result; 16 | 17 | always @(*) begin 18 | result = '0; 19 | 20 | for (i = 0; i < 255; i = i + 1) 21 | result = result + {7'b0, in[i]}; 22 | end 23 | 24 | assign out = result; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s03_module_name.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_name 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out1, 15 | output out2 16 | ); 17 | 18 | mod_a mod_a_i0 ( 19 | .out1 ( out1 ), 20 | .out2 ( out2 ), 21 | .in1 ( a ), 22 | .in2 ( b ), 23 | .in3 ( c ), 24 | .in4 ( d ) 25 | ); 26 | 27 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s01_circuit1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | output q 13 | ); 14 | 15 | // 16 | // a 17 | // 18 | // b q 0 1 19 | // 20 | // 0 0 0 21 | // 22 | // 1 0 1 23 | // 24 | // 25 | // q = a & b 26 | // 27 | // 28 | assign q = a & b; 29 | 30 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s07_m2014_q4k.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4k 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input resetn, // synchronous reset 12 | input in, 13 | output out 14 | ); 15 | 16 | reg [3:0] q_reg; 17 | always @(posedge clk) begin 18 | if (!resetn) 19 | q_reg <= '0; 20 | else 21 | q_reg <= {q_reg[2:0], in}; 22 | end 23 | 24 | assign out = q_reg[3]; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s28_m2014_q6c.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q6b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [5:0] y, 11 | input w, 12 | output Y1, 13 | output Y3 14 | ); 15 | 16 | assign Y1 = y[0] & w; 17 | assign Y3 = (y[1] & ~w) | (y[2] & ~w) | (y[4] & ~w) | (y[5] & ~w); 18 | 19 | /* verilator lint_off UNUSED */ 20 | wire [0:0] unused; 21 | assign unused = {y[3]}; 22 | /* verilator lint_on UNUSED */ 23 | 24 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s08_circuit8.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit8 4 | // 5 | // Be carefull when testing this module on FPGA 6 | // 7 | // 8 | 9 | `default_nettype none 10 | 11 | module top_module ( 12 | input clock, 13 | input a, 14 | output p, 15 | output q 16 | ); 17 | 18 | reg r; 19 | always @(negedge clock) begin 20 | r <= a; 21 | end 22 | 23 | assign q = r; 24 | 25 | assign p = clock ? a : p; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c01_Basics/s08_7458.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/7458 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input p1a, 11 | input p1b, 12 | input p1c, 13 | input p1d, 14 | input p1e, 15 | input p1f, 16 | input p2a, 17 | input p2b, 18 | input p2c, 19 | input p2d, 20 | output p1y, 21 | output p2y 22 | ); 23 | 24 | assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f); 25 | 26 | assign p2y = (p2a & p2b) | (p2c & p2d); 27 | 28 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s01_conditional.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Always_nolatches 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [7:0] a, 11 | input [7:0] b, 12 | input [7:0] c, 13 | input [7:0] d, 14 | output [7:0] min 15 | ); 16 | 17 | wire [7:0] minab; 18 | wire [7:0] mincd; 19 | 20 | assign minab = (a < b) ? a : b; 21 | assign mincd = (c < d) ? c : d; 22 | 23 | assign min = (minab < mincd) ? minab : mincd; 24 | 25 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s16_gatesv.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Gatesv 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [3:0] in, 11 | output [2:0] out_both, 12 | output [3:1] out_any, 13 | output [3:0] out_different 14 | ); 15 | 16 | assign out_both = {in[3] & in[2], in[2] & in[1], in[1] & in[0]}; 17 | assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]}; 18 | assign out_different = {(in[3] != in[0]), (in[2] != in[3]), (in[1] != in[2]), (in[0] != in[1])}; 19 | 20 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s14_ece241_2013_q7.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q7 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input j, 12 | input k, 13 | output Q 14 | ); 15 | 16 | reg q_r; 17 | always @(posedge clk) begin 18 | case ({j, k}) 19 | 2'b00 : q_r <= q_r; 20 | 2'b01 : q_r <= 1'b0; 21 | 2'b10 : q_r <= 1'b1; 22 | 2'b11 : q_r <= ~q_r; 23 | endcase 24 | end 25 | 26 | assign Q = q_r; 27 | 28 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s05_ece241_2013_q2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out_sop, 15 | output out_pos 16 | ); 17 | 18 | assign out_sop = ( c & d) | 19 | (~a & ~b & c ); 20 | 21 | assign out_pos = ( c ) & 22 | (~a | d) & 23 | ( ~b | d); 24 | 25 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s12_2014_q4a.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2014_q4a 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input w, 12 | input R, 13 | input E, 14 | input L, 15 | output Q 16 | ); 17 | 18 | reg q_r; 19 | always @(posedge clk) begin 20 | if (L) 21 | q_r <= R; 22 | else 23 | if (E) 24 | q_r <= w; 25 | else 26 | q_r <= q_r; 27 | end 28 | 29 | assign Q = q_r; 30 | 31 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s09_circuit9.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit9 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input a, 12 | output [3:0] q 13 | ); 14 | 15 | reg [3:0] r; 16 | always @(posedge clk) begin 17 | if(a) 18 | r <= 4'd4; 19 | else if (q == 4'd6) 20 | r <= 4'd0; 21 | else 22 | r <= r + 1'b1; 23 | end 24 | 25 | assign q = r; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s02_count10.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Count10 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | output [3:0] q 13 | ); 14 | 15 | reg [3:0] counter; 16 | always @(posedge clk) begin 17 | if (reset) 18 | counter <= '0; 19 | else 20 | if (counter == 4'd10 - 1'b1) 21 | counter <= '0; 22 | else 23 | counter <= counter + 1'b1; 24 | end 25 | 26 | assign q = counter; 27 | 28 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s15_edgedetect.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Edgedetect 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [7:0] in, 12 | output [7:0] pedge 13 | ); 14 | reg [7:0] edge_r; 15 | always @(posedge clk ) begin 16 | edge_r <= in; 17 | end 18 | 19 | wire [7:0] rising; 20 | assign rising = ~edge_r & in; 21 | 22 | reg [7:0] q_r; 23 | always @(posedge clk ) begin 24 | q_r <= rising; 25 | end 26 | 27 | assign pedge = q_r; 28 | 29 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s03_count1to10.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Count1to10 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | output [3:0] q 13 | ); 14 | 15 | reg [3:0] counter; 16 | always @(posedge clk) begin 17 | if (reset) 18 | counter <= 4'd1; 19 | else 20 | if (counter == 4'd11 - 1'b1) 21 | counter <= 4'd1; 22 | else 23 | counter <= counter + 1'b1; 24 | end 25 | 26 | assign q = counter; 27 | 28 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s04_lfsr5.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Lfsr5 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | output [4:0] q 13 | ); 14 | 15 | reg [4:0] q_reg; 16 | wire [4:0] q_next; 17 | always @(posedge clk) begin 18 | if (reset) 19 | q_reg <= 5'h1; 20 | else 21 | q_reg <= q_next; 22 | end 23 | 24 | assign q_next = {1'b0 ^ q_reg[0], q_reg[4], q_reg[3] ^ q_reg[0], q_reg[2], q_reg[1]}; 25 | 26 | assign q = q_reg; 27 | 28 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s03_always_if.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Always_if 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input a, 12 | input b, 13 | input sel_b1, 14 | input sel_b2, 15 | output wire out_assign, 16 | output reg out_always 17 | ); 18 | 19 | assign out_assign = ( sel_b1 & sel_b2) ? b : a; 20 | 21 | always @(*) begin 22 | if (sel_b1 & sel_b2) 23 | out_always = b; 24 | else 25 | out_always = a; 26 | end 27 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s16_edgedetect2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Edgedetect2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [7:0] in, 12 | output [7:0] anyedge 13 | ); 14 | 15 | reg [7:0] edge_r; 16 | always @(posedge clk ) begin 17 | edge_r <= in; 18 | end 19 | 20 | wire [7:0] toggle; 21 | assign toggle = edge_r ^ in; 22 | 23 | reg [7:0] q_r; 24 | always @(posedge clk) begin 25 | q_r <= toggle; 26 | end 27 | 28 | assign anyedge = q_r; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c16_Finding_bugs_in_code/s02_nand3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bugs_nand3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | output out 14 | ); 15 | 16 | wire and_out; 17 | 18 | andgate inst1 ( 19 | .a ( a ), 20 | .b ( b ), 21 | .c ( c ), 22 | .d ( 1'b1 ), 23 | .e ( 1'b1 ), 24 | .out ( and_out ) 25 | ); 26 | 27 | assign out = !and_out; 28 | 29 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s02_alwaysblock2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Alwaysblock2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input clk, 12 | input a, 13 | input b, 14 | output wire out_assign, 15 | output reg out_always_comb, 16 | output reg out_always_ff 17 | ); 18 | 19 | assign out_assign = a ^ b; 20 | 21 | always @(*) begin 22 | out_always_comb = a ^ b; 23 | end 24 | 25 | always @(posedge clk) begin 26 | out_always_ff <= a ^ b; 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c09_Karnaugh_Map_to_Circuit/s04_kmap4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Kmap4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output out 15 | ); 16 | 17 | assign out = (~a & b & ~c & ~d) | 18 | ( a & ~b & ~c & ~d) | 19 | (~a & ~b & ~c & d) | 20 | ( a & b & ~c & d) | 21 | (~a & b & c & d) | 22 | ( a & ~b & c & d) | 23 | (~a & ~b & c & ~d) | 24 | ( a & b & c & ~d); 25 | 26 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s06_gates.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Gates 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input a, 11 | input b, 12 | output out_and, 13 | output out_or, 14 | output out_xor, 15 | output out_nand, 16 | output out_nor, 17 | output out_xnor, 18 | output out_anotb 19 | ); 20 | 21 | assign out_and = a & b; 22 | assign out_or = a | b; 23 | assign out_xor = a ^ b; 24 | assign out_nand = ~(a & b); 25 | assign out_nor = ~(a | b); 26 | assign out_xnor = ~(a ^ b); 27 | assign out_anotb = a & ~b; 28 | 29 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s01_count1k.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/review2015_count1k 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module #( 10 | parameter MAX = 1000, 11 | parameter N = $clog2(MAX) 12 | ) 13 | ( 14 | input clk, 15 | input reset, 16 | output [N - 1:0] q 17 | ); 18 | 19 | reg [N - 1:0] counter; 20 | 21 | always @(posedge clk) begin 22 | if(reset) 23 | counter <= '0; 24 | else if (counter == MAX - 1'b1) 25 | counter <= '0; 26 | else 27 | counter <= counter + 1'b1; 28 | end 29 | 30 | assign q = counter; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s02_shiftcount.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/review2015_shiftcount 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input shift_ena, 12 | input count_ena, 13 | input data, 14 | output [3:0] q 15 | ); 16 | 17 | reg [3:0] counter; 18 | 19 | always @(posedge clk) begin 20 | if (shift_ena) 21 | counter <= {counter[2:0], data}; 22 | else if (count_ena) 23 | counter <= counter - 1'b1; 24 | end 25 | 26 | assign q = counter; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s17_gatesv100.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Gatesv100 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [99:0] in, 11 | output [98:0] out_both, 12 | output [99:1] out_any, 13 | output [99:0] out_different 14 | ); 15 | 16 | localparam BASE = 0, 17 | LIMIT = 99; 18 | 19 | assign out_both = in[LIMIT - 1 + 1:BASE + 1] & in[LIMIT - 1:BASE]; 20 | 21 | assign out_any = in[LIMIT - 1 + 1:BASE + 1] | in[LIMIT - 1:BASE]; 22 | 23 | assign out_different = {in[0] ^ in[99], in[LIMIT - 1 + 1:BASE + 1] ^ in[LIMIT - 1:BASE]}; 24 | 25 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s18_dualedge.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dualedge 4 | // 5 | // https://zhuanlan.zhihu.com/p/61695679 6 | // https://www.reddit.com/r/FPGA/comments/b8xtqm/a_dual_edge_triggered_flipflop_in_verilog/ek1tddc/ 7 | // 8 | 9 | `default_nettype none 10 | 11 | module top_module ( 12 | input clk, 13 | input d, 14 | output q 15 | ); 16 | 17 | reg reg_p; 18 | always @(posedge clk) begin 19 | reg_p <= d ^ reg_n; 20 | end 21 | 22 | reg reg_n; 23 | always @(negedge clk) begin 24 | reg_n <= d ^ reg_p; 25 | end 26 | 27 | assign q = reg_p ^ reg_n; 28 | 29 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s15_popcount3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Popcount3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [2:0] in, 11 | output [1:0] out 12 | ); 13 | 14 | reg [1:0] value; 15 | always @(*) begin 16 | case (in) 17 | 3'b000 : value = 2'd0; 18 | 3'b001 : value = 2'd1; 19 | 3'b010 : value = 2'd1; 20 | 3'b011 : value = 2'd2; 21 | 3'b100 : value = 2'd1; 22 | 3'b101 : value = 2'd2; 23 | 3'b110 : value = 2'd2; 24 | 3'b111 : value = 2'd3; 25 | endcase 26 | end 27 | 28 | assign out = value; 29 | 30 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s06_dff16e.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Dff16e 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input resetn, 12 | input [1:0] byteena, 13 | input [15:0] d, 14 | output [15:0] q 15 | ); 16 | 17 | reg [15:0] q_r; 18 | wire [15:0] q_next; 19 | always @(posedge clk) begin 20 | if (!resetn) 21 | q_r <= '0; 22 | else 23 | q_r <= q_next; 24 | end 25 | 26 | assign q_next = {byteena[1] ? d[15:8] : q_r[15:8], byteena[0] ? d[7:0] : q_r[7:0]}; 27 | 28 | assign q = q_r; 29 | 30 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s04_circuit4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output q 15 | ); 16 | 17 | // 18 | // ab 19 | // 20 | // cd q 00 01 11 10 21 | // 22 | // 00 0 1 1 0 23 | // 24 | // 01 0 1 1 0 25 | // 26 | // 11 1 1 1 1 27 | // 28 | // 10 1 1 1 1 29 | // 30 | // 31 | // q = b | c 32 | // 33 | assign q = b | c; 34 | 35 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s04_module_shift.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_shift 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input d, 12 | output q 13 | ); 14 | 15 | wire q0; 16 | my_dff my_dff_i0 ( 17 | .clk ( clk ), 18 | .d ( d ), 19 | .q ( q0 ) 20 | ); 21 | 22 | wire q1; 23 | my_dff my_dff_i1 ( 24 | .clk ( clk ), 25 | .d ( q0 ), 26 | .q ( q1 ) 27 | ); 28 | 29 | my_dff my_dff_i2 ( 30 | .clk ( clk ), 31 | .d ( q1 ), 32 | .q ( q ) 33 | ); 34 | 35 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s08_truthtable1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Truthtable1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input x3, 11 | input x2, 12 | input x1, 13 | output f 14 | ); 15 | 16 | reg value; 17 | always @(*) begin 18 | case ({x3, x2, x1}) 19 | 3'b000 : value = 1'b0; 20 | 3'b001 : value = 1'b0; 21 | 3'b010 : value = 1'b1; 22 | 3'b011 : value = 1'b1; 23 | 3'b100 : value = 1'b0; 24 | 3'b101 : value = 1'b1; 25 | 3'b110 : value = 1'b0; 26 | 3'b111 : value = 1'b1; 27 | endcase 28 | end 29 | 30 | assign f = value; 31 | 32 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s01_shift4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Shift4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input clk, 11 | input areset, 12 | input load, 13 | input ena, 14 | input [3:0] data, 15 | output reg [3:0] q 16 | ); 17 | 18 | wire [3:0] q_next; 19 | always @(posedge clk, posedge areset) begin 20 | if (areset) 21 | q <= '0; 22 | else 23 | q <= q_next; 24 | end 25 | 26 | 27 | assign q_next = (load) ? data : 28 | (ena ? {1'b0, q[3:1]} : q); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s05_circuit5.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit5 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [3:0] a, 11 | input [3:0] b, 12 | input [3:0] c, 13 | input [3:0] d, 14 | input [3:0] e, 15 | output [3:0] q 16 | ); 17 | 18 | reg [3:0] r; 19 | always @(*) begin 20 | case (c) 21 | 4'h0 : r = b; 22 | 4'h1 : r = e; 23 | 4'h2 : r = a; 24 | 4'h3 : r = d; 25 | default : r = 4'hf; 26 | endcase 27 | end 28 | 29 | assign q = r; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s04_fsmshift.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/exams/review2015_fsmshift 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module #( 10 | parameter MAX = 4, 11 | parameter N = $clog2(MAX + 1) 12 | )( 13 | input clk, 14 | input reset, 15 | output shift_ena 16 | ); 17 | 18 | reg [N - 1:0] counter; 19 | 20 | always @(posedge clk) begin 21 | if(reset) begin 22 | counter <= MAX[N - 1:0]; 23 | end else if (counter != '0) 24 | counter <= counter - 1'b1; 25 | end 26 | 27 | assign shift_ena = (counter != '0); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /p02_Cirucuits/c10_Latches_and_Flip_Flops/s17_edgecapture.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Edgecapture 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input [31:0] in, 13 | output [31:0] out 14 | ); 15 | 16 | reg [31:0] edge_r; 17 | always @(posedge clk) begin 18 | edge_r <= in; 19 | end 20 | 21 | wire [31:0] falling; 22 | assign falling = edge_r & ~in; 23 | 24 | reg [31:0] q_r; 25 | always @(posedge clk) begin 26 | if (reset) 27 | q_r <= '0; 28 | else 29 | q_r <= falling | q_r; 30 | end 31 | 32 | assign out = q_r; 33 | 34 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s06_adder100i.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Adder100i 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [99:0] a, 11 | input [99:0] b, 12 | input cin, 13 | output [99:0] cout, 14 | output [99:0] sum 15 | ); 16 | 17 | wire [100:0] cout_in; 18 | 19 | assign cout_in[0] = cin; 20 | 21 | genvar i; 22 | generate 23 | for (i = 0; i < 100; i = i + 1) begin : loop 24 | assign {cout[i], sum[i]} = a[i] + b[i] + cout_in[i]; 25 | 26 | assign cout_in[i+1] = cout[i]; 27 | end 28 | endgenerate 29 | 30 | wire unused_cout; 31 | assign unused_cout = cout_in[100]; 32 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s06_circuit6.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit6 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [2:0] a, 11 | output [15:0] q 12 | ); 13 | 14 | reg [15:0] r; 15 | always @(*) begin 16 | case (a) 17 | 3'd0 : r = 16'h1232; 18 | 3'd1 : r = 16'haee0; 19 | 3'd2 : r = 16'h27d4; 20 | 3'd3 : r = 16'h5a0e; 21 | 3'd4 : r = 16'h2066; 22 | 3'd5 : r = 16'h64ce; 23 | 3'd6 : r = 16'hc526; 24 | // 3'd7 25 | default : r = 16'h2f19; 26 | endcase 27 | end 28 | 29 | assign q = r; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s07_always_casez.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Always_casez 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input [7:0] in, 12 | output reg [2:0] pos 13 | ); 14 | 15 | always @(*) begin 16 | casez (in) 17 | 8'bzzzz_zzz1 : pos = 3'd0; 18 | 8'bzzzz_zz10 : pos = 3'd1; 19 | 8'bzzzz_z100 : pos = 3'd2; 20 | 8'bzzzz_1000 : pos = 3'd3; 21 | 8'bzzz1_0000 : pos = 3'd4; 22 | 8'bzz10_0000 : pos = 3'd5; 23 | 8'bz100_0000 : pos = 3'd6; 24 | 8'b1000_0000 : pos = 3'd7; 25 | default : pos = 3'd0; 26 | endcase 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c13_More_Circuits/s01_rule90.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Rule90 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input load, 12 | input [511:0] data, 13 | output [511:0] q 14 | ); 15 | 16 | reg [511:0] q_reg; 17 | wire [511:0] q_next; 18 | always @(posedge clk) begin 19 | if (load) 20 | q_reg <= data; 21 | else 22 | q_reg <= q_next; 23 | end 24 | 25 | localparam BASE = 1, 26 | LIMIT = 511; 27 | 28 | assign q_next = {1'b0 ^ q_reg[510], q_reg[LIMIT - 1 + 1:BASE + 1] ^ q_reg[LIMIT - 1 - 1:BASE - 1], q_reg[1] ^ 1'b0}; 29 | 30 | assign q = q_reg; 31 | 32 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s04_always_if2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Always_if2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input cpu_overheated, 12 | output reg shut_off_computer, 13 | input arrived, 14 | input gas_tank_empty, 15 | output reg keep_driving 16 | ); 17 | 18 | always @(*) begin 19 | if (cpu_overheated) 20 | shut_off_computer = 1'b1; 21 | else 22 | shut_off_computer = 1'b0; 23 | end 24 | 25 | always @(*) begin 26 | if (~arrived) 27 | keep_driving = ~gas_tank_empty; 28 | else 29 | keep_driving = 1'b0; 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s04_countslow.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Countslow 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input slowena, 12 | input reset, 13 | output [3:0] q 14 | ); 15 | 16 | reg [3:0] counter; 17 | always @(posedge clk) begin 18 | if (reset) 19 | counter <= '0; 20 | else if (slowena) 21 | if (counter == 4'd10 - 1'b1) 22 | counter <= '0; 23 | else 24 | counter <= counter + 1'b1; 25 | // Usually the last no-change else branch could be omitted 26 | else 27 | counter <= counter; 28 | end 29 | 30 | assign q = counter; 31 | 32 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s02_rotate100.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Rotate100 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input load, 12 | input [1:0] ena, 13 | input [99:0] data, 14 | output reg [99:0] q 15 | ); 16 | 17 | reg [99:0] q_next; 18 | always @(posedge clk) begin 19 | q <= q_next; 20 | end 21 | 22 | always @(*) begin 23 | if (load) 24 | q_next = data; 25 | else 26 | case (ena) 27 | 2'b01 : q_next = {q[0], q[99:1]}; 28 | 2'b10 : q_next = {q[98:0], q[99]}; 29 | default : q_next = q; 30 | endcase 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s06_module_add.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_add 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [31:0] a, 11 | input [31:0] b, 12 | output [31:0] sum 13 | ); 14 | 15 | wire cout_lo; 16 | add16 add16_i0 ( 17 | .a ( a[15:0] ), 18 | .b ( b[15:0] ), 19 | .cin ( 1'b0 ), 20 | .sum ( sum[15:0] ), 21 | .cout ( cout_lo ) 22 | ); 23 | 24 | wire unused_cout_hi; 25 | add16 add16_i1 ( 26 | .a ( a[31:16] ), 27 | .b ( b[31:16] ), 28 | .cin ( cout_lo ), 29 | .sum ( sum[31:16] ), 30 | .cout ( unused_cout_hi ) 31 | ); 32 | 33 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s08_always_nolatches.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Conditional 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input [15:0] scancode, 12 | output reg left, 13 | output reg down, 14 | output reg right, 15 | output reg up 16 | ); 17 | 18 | always @(*) begin 19 | left = 1'b0; 20 | down = 1'b0; 21 | right = 1'b0; 22 | up = 1'b0; 23 | 24 | case (scancode) 25 | 16'he06b : left = 1'b1; 26 | 16'he072 : down = 1'b1; 27 | 16'he074 : right = 1'b1; 28 | 16'he075 : up = 1'b1; 29 | default : ; 30 | endcase 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s06_fsm3onehot.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm3onehot 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input in, 11 | input [3:0] state, 12 | output [3:0] next_state, 13 | output out 14 | ); 15 | 16 | parameter A = 0, 17 | B = 1, 18 | C = 2, 19 | D = 3; 20 | 21 | // State transition logic: Derive an equation for each state flip-flop. 22 | assign next_state[A] = state[0] & ~in | state[2] & ~in; 23 | assign next_state[B] = state[0] & in | state[1] & in | state[3] & in; 24 | assign next_state[C] = state[1] & ~in | state[3] & ~in; 25 | assign next_state[D] = state[2] & in; 26 | 27 | // Output logic: 28 | assign out = state[3]; 29 | 30 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s05_always_case.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Always_case 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input [2:0] sel, 12 | input [3:0] data0, 13 | input [3:0] data1, 14 | input [3:0] data2, 15 | input [3:0] data3, 16 | input [3:0] data4, 17 | input [3:0] data5, 18 | output reg [3:0] out 19 | ); 20 | 21 | always@(*) begin 22 | case(sel) 23 | 3'b000 : out = data0; 24 | 3'b001 : out = data1; 25 | 3'b010 : out = data2; 26 | 3'b011 : out = data3; 27 | 3'b100 : out = data4; 28 | 3'b101 : out = data5; 29 | default : out = 4'b0; 30 | endcase 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s04_fsm2s.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input clk, 11 | input reset, // Synchronous reset to OFF 12 | input j, 13 | input k, 14 | output out 15 | ); 16 | 17 | parameter ON = 1'b1; 18 | parameter OFF = 1'b0; 19 | 20 | reg state; 21 | reg next_state; 22 | 23 | always @(*) begin 24 | case (state) 25 | ON : next_state = k ? OFF : ON; 26 | OFF : next_state = j ? ON : OFF; 27 | default : next_state = OFF; 28 | endcase 29 | end 30 | 31 | always @(posedge clk) begin 32 | if (reset) 33 | state <= OFF; 34 | else 35 | state <= next_state; 36 | end 37 | 38 | assign out = state; 39 | 40 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c16_Finding_bugs_in_code/s05_case.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bugs_case 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [7:0] code, 11 | output reg [3:0] out, 12 | output reg valid 13 | ); 14 | 15 | always @(*) begin 16 | out = 4'd0; 17 | valid = 1'b1; 18 | 19 | case (code) 20 | 8'h45 : out = 4'd0; 21 | 8'h16 : out = 4'd1; 22 | 8'h1e : out = 4'd2; 23 | 8'h26 : out = 4'd3; 24 | 8'h25 : out = 4'd4; 25 | 8'h2e : out = 4'd5; 26 | 8'h36 : out = 4'd6; 27 | 8'h3d : out = 4'd7; 28 | 8'h3e : out = 4'd8; 29 | 8'h46 : out = 4'd9; 30 | default : valid = 1'b0; 31 | endcase 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s01_fsm1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, // Asynchronous reset to state B 12 | input in, 13 | output out 14 | ); 15 | 16 | parameter A = 1'b0; 17 | parameter B = 1'b1; 18 | 19 | reg state; 20 | reg next_state; 21 | 22 | always @(*) begin 23 | case (state) 24 | A : next_state = in ? A : B; 25 | B : next_state = in ? B : A; 26 | default : next_state = B; 27 | endcase 28 | end 29 | 30 | always @(posedge clk, posedge areset) begin 31 | if (areset) 32 | state <= B; 33 | else 34 | state <= next_state; 35 | end 36 | 37 | // Output logic 38 | assign out = state; 39 | 40 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s03_fsm2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input clk, 11 | input areset, // Asynchronous reset to OFF 12 | input j, 13 | input k, 14 | output out 15 | ); 16 | 17 | parameter ON = 1'b1; 18 | parameter OFF = 1'b0; 19 | 20 | reg state; 21 | reg next_state; 22 | 23 | always @(*) begin 24 | case (state) 25 | ON : next_state = k ? OFF : ON; 26 | OFF : next_state = j ? ON : OFF; 27 | default : next_state = OFF; 28 | endcase 29 | end 30 | 31 | always @(posedge clk, posedge areset) begin 32 | if (areset) 33 | state <= OFF; 34 | else 35 | state <= next_state; 36 | end 37 | 38 | assign out = state; 39 | 40 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s09_module_addsub.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_addsub 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [31:0] a, 11 | input [31:0] b, 12 | input sub, 13 | output [31:0] sum 14 | ); 15 | 16 | wire [31:0] xored_b; 17 | assign xored_b = b ^ {32{sub}}; 18 | 19 | wire cout_lo; 20 | add16 add16_i0 ( 21 | .a ( a[15:0] ), 22 | .b ( xored_b[15:0] ), 23 | .cin ( sub ), 24 | .sum ( sum[15:0] ), 25 | .cout ( cout_lo ) 26 | ); 27 | 28 | wire unused_cout_hi; 29 | add16 add16_i1 ( 30 | .a ( a[31:16] ), 31 | .b ( xored_b[31:16] ), 32 | .cin ( cout_lo ), 33 | .sum ( sum[31:16] ), 34 | .cout ( unused_cout_hi ) 35 | ); 36 | 37 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s07_bcdadd4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bcdadd4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [15:0] a, 11 | input [15:0] b, 12 | input cin, 13 | output cout, 14 | output [15:0] sum 15 | ); 16 | 17 | wire [4:0] cin_vector; 18 | 19 | assign cin_vector[0] = cin; 20 | 21 | genvar i; 22 | generate 23 | for (i = 0; i < 4; i = i + 1) begin : loop 24 | bcd_fadd bcd_fadd_i ( 25 | .a ( a[4 * i + 3 : 4 * i] ), 26 | .b ( b[4 * i + 3 : 4 * i] ), 27 | .cin ( cin_vector[i] ), 28 | .cout ( cin_vector[i + 1] ), 29 | .sum ( sum[4 * i + 3 : 4 * i] ) 30 | ); 31 | end 32 | endgenerate 33 | 34 | assign cout = cin_vector[4]; 35 | 36 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s05_fsm3comb.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm3comb 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input in, 11 | input [1:0] state, 12 | output [1:0] next_state, 13 | output out 14 | ); 15 | 16 | parameter A = 2'd0, 17 | B = 2'd1, 18 | C = 2'd2, 19 | D = 2'd3; 20 | 21 | // State transition logic: Derive an equation for each state flip-flop. 22 | reg [1:0] state_next; 23 | always @(*) begin 24 | case (state) 25 | A : state_next = in ? B : A; 26 | B : state_next = in ? B : C; 27 | C : state_next = in ? D : A; 28 | D : state_next = in ? B : C; 29 | endcase 30 | end 31 | 32 | // Output logic: 33 | assign next_state = state_next; 34 | 35 | assign out = (state == D); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c05_More_Verilog_Features/s07_bcdadd100.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bcdadd100 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [399:0] a, 11 | input [399:0] b, 12 | input cin, 13 | output cout, 14 | output [399:0] sum 15 | ); 16 | 17 | wire [100:0] cin_in; 18 | 19 | assign cin_in[0] = cin; 20 | 21 | genvar i; 22 | generate 23 | for (i = 0; i < 100; i = i + 1) begin : loop 24 | bcd_fadd bcd_fadd_i ( 25 | .a ( a[4 * i + 3 : 4 * i] ), 26 | .b ( b[4 * i + 3 : 4 * i] ), 27 | .cin ( cin_in[i] ), 28 | .cout ( cin_in[i + 1] ), 29 | .sum ( sum[4 * i + 3 : 4 * i] ) 30 | ); 31 | end 32 | endgenerate 33 | 34 | assign cout = cin_in[100]; 35 | 36 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c04_Procedures/s06_always_case2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Always_case2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // synthesis verilog_input_version verilog_2001 10 | module top_module ( 11 | input [3:0] in, 12 | output reg [1:0] pos 13 | ); 14 | 15 | always @(*) begin 16 | case (in) 17 | 4'b0000 : pos = 2'd0; 18 | 4'b0001 : pos = 2'd0; 19 | 4'b0010 : pos = 2'd1; 20 | 4'b0011 : pos = 2'd0; 21 | 4'b0100 : pos = 2'd2; 22 | 4'b0101 : pos = 2'd0; 23 | 4'b0110 : pos = 2'd1; 24 | 4'b0111 : pos = 2'd0; 25 | 4'b1000 : pos = 2'd3; 26 | 4'b1001 : pos = 2'd0; 27 | 4'b1010 : pos = 2'd1; 28 | 4'b1011 : pos = 2'd0; 29 | 4'b1100 : pos = 2'd2; 30 | 4'b1101 : pos = 2'd0; 31 | 4'b1110 : pos = 2'd1; 32 | 4'b1111 : pos = 2'd0; 33 | endcase 34 | end 35 | 36 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s03_circuit3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output q 15 | ); 16 | 17 | // 18 | // ab 19 | // 20 | // cd q 00 01 11 10 21 | // 22 | // 00 0 0 0 0 23 | // 24 | // 01 0 1 1 1 25 | // 26 | // 11 0 1 1 1 27 | // 28 | // 10 0 1 1 1 29 | // 30 | // 31 | // q = ( b & d) | 32 | // ( a & d) | 33 | // ( b & c ) | 34 | // ( a & c ) 35 | // 36 | assign q = ( b & d) | 37 | ( a & d) | 38 | ( b & c ) | 39 | ( a & c ); 40 | 41 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s23_ece241_2014_q5b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input x, 13 | output z 14 | ); 15 | 16 | parameter SA = 2'b01, 17 | SB = 2'b10; 18 | 19 | reg [1:0] state; 20 | reg [1:0] state_next; 21 | 22 | always @(posedge clk, posedge areset) begin 23 | if (areset) 24 | state <= SA; 25 | else 26 | state <= state_next; 27 | end 28 | 29 | always @(*) begin 30 | case (state) 31 | SA : state_next = x ? SB : SA; 32 | SB : state_next = SB; 33 | default : state_next = SA; 34 | endcase 35 | end 36 | 37 | assign z = ((state == SA) & x ) | ((state == SB) & ~x); 38 | 39 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s06_lfsr32.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Lfsr32 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, // Active-high synchronous reset to 32'h1 12 | output [31:0] q 13 | ); 14 | 15 | reg [31:0] q_reg; 16 | wire [31:0] q_next; 17 | always @(posedge clk) begin 18 | if (reset) 19 | q_reg <= 32'h1; 20 | else 21 | q_reg <= q_next; 22 | end 23 | 24 | assign q_next = { 25 | 1'b0 ^ q_reg[0], // 31 26 | q_reg[31:23], // 30 : 22 27 | q_reg[22] ^ q_reg[0], // 21 28 | q_reg[21:3], // 20 : 2 29 | q_reg[2] ^ q_reg[0], // 1 30 | q_reg[1] ^ q_reg[0] // 0 31 | }; 32 | 33 | assign q = q_reg; 34 | 35 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c16_Finding_bugs_in_code/s03_mux4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Bugs_mux4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [1:0] sel, 11 | input [7:0] a, 12 | input [7:0] b, 13 | input [7:0] c, 14 | input [7:0] d, 15 | output [7:0] out 16 | ); 17 | 18 | wire [7:0] mux0; 19 | wire [7:0] mux1; 20 | 21 | mux2 mux_u0 ( 22 | .sel ( sel[0] ), 23 | .a ( a ), 24 | .b ( b ), 25 | .out ( mux0 ) 26 | ); 27 | 28 | mux2 mux_u1 ( 29 | .sel ( sel[0] ), 30 | .a ( c ), 31 | .b ( d ), 32 | .out ( mux1 ) 33 | ); 34 | 35 | mux2 mux_u2 ( 36 | .sel ( sel[1] ), 37 | .a ( mux0 ), 38 | .b ( mux1 ), 39 | .out ( out ) 40 | ); 41 | 42 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c07_Multiplexers/s03_mux9to1v.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mux9to1v 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [15:0] a, 11 | input [15:0] b, 12 | input [15:0] c, 13 | input [15:0] d, 14 | input [15:0] e, 15 | input [15:0] f, 16 | input [15:0] g, 17 | input [15:0] h, 18 | input [15:0] i, 19 | input [3:0] sel, 20 | output [15:0] out 21 | ); 22 | 23 | reg [15:0] value; 24 | 25 | always @(*) begin 26 | case (sel) 27 | 4'h0 : value = a; 28 | 4'h1 : value = b; 29 | 4'h2 : value = c; 30 | 4'h3 : value = d; 31 | 4'h4 : value = e; 32 | 4'h5 : value = f; 33 | 4'h6 : value = g; 34 | 4'h7 : value = h; 35 | 4'h8 : value = i; 36 | default : value = {16{1'b1}}; 37 | endcase 38 | end 39 | 40 | assign out = value; 41 | 42 | endmodule -------------------------------------------------------------------------------- /p04_Verification_Writing_Testbenches/s05_tff.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Tb/tff 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | `timescale 1ps/1ps 10 | 11 | module top_module ( ); 12 | 13 | localparam CLK_PERIOD = 10; 14 | 15 | reg clk; 16 | initial begin 17 | clk = 1'b0; 18 | 19 | forever 20 | #(CLK_PERIOD / 2) clk = ~clk; 21 | end 22 | 23 | reg reset; 24 | reg t; 25 | wire q; 26 | 27 | tff tff_u0 ( 28 | .clk ( clk ), 29 | .reset ( reset ), 30 | .t ( t ), 31 | .q ( q ) 32 | ); 33 | 34 | initial begin 35 | reset = 1'b0; 36 | t = 1'b0; 37 | 38 | @(negedge clk) 39 | reset = 1'b1; 40 | 41 | @(negedge clk) 42 | reset = 1'b0; 43 | t = 1'b1; 44 | 45 | @(negedge clk) 46 | t = 1'b0; 47 | 48 | end 49 | 50 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s03_shift18.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Shift18 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input load, 12 | input ena, 13 | input [1:0] amount, 14 | input [63:0] data, 15 | output reg [63:0] q 16 | ); 17 | 18 | reg [63:0] q_next; 19 | always @(posedge clk) begin 20 | q <= q_next; 21 | end 22 | 23 | always @(*) begin 24 | if (load) 25 | q_next = data; 26 | else 27 | if (ena) 28 | case (amount) 29 | 2'b00 : q_next = {q[62:0], 1'b0}; 30 | 2'b01 : q_next = {q[55:0], 8'b0}; 31 | 2'b10 : q_next = {q[63], q[63:1]}; 32 | 2'b11 : q_next = {{8{q[63]}}, q[63:8]}; 33 | endcase 34 | else 35 | q_next = q; 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s05_module_shift8.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_shift8 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [7:0] d, 12 | input [1:0] sel, 13 | output [7:0] q 14 | ); 15 | 16 | wire [7:0] q0; 17 | my_dff8 my_dff8_i0 ( 18 | .clk ( clk ), 19 | .d ( d ), 20 | .q ( q0 ) 21 | ); 22 | 23 | wire [7:0] q1; 24 | my_dff8 my_dff8_i1 ( 25 | .clk ( clk ), 26 | .d ( q0 ), 27 | .q ( q1 ) 28 | ); 29 | 30 | wire [7:0] q2; 31 | my_dff8 my_dff8_i2 ( 32 | .clk ( clk ), 33 | .d ( q1 ), 34 | .q ( q2 ) 35 | ); 36 | 37 | always @(*) begin 38 | case (sel) 39 | 2'b00 : q = d; 40 | 2'b01 : q = q0; 41 | 2'b10 : q = q1; 42 | 2'b11 : q = q2; 43 | endcase 44 | end 45 | 46 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s10_lemmings1.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Lemmings1 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input bump_left, 13 | input bump_right, 14 | output walk_left, 15 | output walk_right 16 | ); 17 | 18 | parameter LEFT = 1'b0, 19 | RIGHT = 1'b1; 20 | 21 | reg state; 22 | reg next_state; 23 | 24 | always @(*) begin 25 | case (state) 26 | LEFT : next_state = (bump_left) ? RIGHT : LEFT; 27 | RIGHT : next_state = (bump_right) ? LEFT : RIGHT; 28 | default : next_state = state; 29 | endcase 30 | end 31 | 32 | always @(posedge clk, posedge areset) begin 33 | if (areset) 34 | state <= LEFT; 35 | else 36 | state <= next_state; 37 | end 38 | 39 | assign walk_left = (state == LEFT); 40 | assign walk_right = (state == RIGHT); 41 | 42 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s22_ece241_2014_q5a.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5a 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input x, 13 | output z 14 | ); 15 | 16 | parameter S0 = 2'd0, 17 | S1 = 2'd1, 18 | S2 = 2'd2; 19 | 20 | reg [1:0] state; 21 | reg [1:0] state_next; 22 | 23 | always @(posedge clk, posedge areset) begin 24 | if (areset) 25 | state <= S0; 26 | else 27 | state <= state_next; 28 | end 29 | 30 | always @(*) begin 31 | case (state) 32 | S0 : state_next = x ? S1 : S0; 33 | S1 : state_next = x ? S2 : S1; 34 | S2 : state_next = x ? S2 : S1; 35 | default : state_next = S0; 36 | endcase 37 | end 38 | 39 | assign z = (state == S1); 40 | 41 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s08_fsm3s.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm3s 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input in, 12 | input reset, 13 | output out 14 | ); 15 | 16 | parameter A = 2'd0, 17 | B = 2'd1, 18 | C = 2'd2, 19 | D = 2'd3; 20 | 21 | reg [1:0] state; 22 | reg [1:0] next_state; 23 | 24 | // State transition logic 25 | always @(*) begin 26 | case (state) 27 | A : next_state = in ? B : A; 28 | B : next_state = in ? B : C; 29 | C : next_state = in ? D : A; 30 | D : next_state = in ? B : C; 31 | endcase 32 | end 33 | 34 | // State flip-flops with asynchronous reset 35 | always @(posedge clk) begin 36 | if (reset) 37 | state <= A; 38 | else 39 | state <= next_state; 40 | end 41 | 42 | // Output logic 43 | assign out = (state == D); 44 | 45 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s02_fsm1s.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm1s 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // Note the Verilog-1995 module declaration syntax here: 10 | module top_module (clk, reset, in, out); 11 | input clk; 12 | input reset; // Synchronous reset to state B 13 | input in; 14 | output out; 15 | 16 | // Fill in state name declarations 17 | localparam A=1'b0; 18 | localparam B=1'b1; 19 | 20 | reg present_state; 21 | reg next_state; 22 | 23 | always @(posedge clk) begin 24 | if (reset) begin 25 | present_state <= B; 26 | end else begin 27 | present_state <= next_state; 28 | end 29 | end 30 | 31 | always @(*) begin 32 | case (present_state) 33 | A : next_state = in ? A : B; 34 | B : next_state = in ? B : A; 35 | default : next_state = B; 36 | endcase 37 | end 38 | 39 | // Output logic 40 | assign out = present_state; 41 | 42 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s07_fsm3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input in, 12 | input areset, 13 | output out 14 | ); 15 | 16 | parameter A = 2'd0, 17 | B = 2'd1, 18 | C = 2'd2, 19 | D = 2'd3; 20 | 21 | reg [1:0] state; 22 | reg [1:0] next_state; 23 | 24 | // State transition logic 25 | always @(*) begin 26 | case (state) 27 | A : next_state = in ? B : A; 28 | B : next_state = in ? B : C; 29 | C : next_state = in ? D : A; 30 | D : next_state = in ? B : C; 31 | endcase 32 | end 33 | 34 | // State flip-flops with asynchronous reset 35 | always @(posedge clk, posedge areset) begin 36 | if (areset) 37 | state <= A; 38 | else 39 | state <= next_state; 40 | end 41 | 42 | // Output logic 43 | assign out = (state == D); 44 | 45 | endmodule -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s07_module_fadd.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_fadd 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [31:0] a, 11 | input [31:0] b, 12 | output [31:0] sum 13 | ); 14 | 15 | wire cout_lo; 16 | add16 add16_i0 ( 17 | .a ( a[15:0] ), 18 | .b ( b[15:0] ), 19 | .cin ( 1'b0 ), 20 | .sum ( sum[15:0] ), 21 | .cout ( cout_lo ) 22 | ); 23 | 24 | wire unused_cout_hi; 25 | add16 add16_i1 ( 26 | .a ( a[31:16] ), 27 | .b ( b[31:16] ), 28 | .cin ( cout_lo ), 29 | .sum ( sum[31:16] ), 30 | .cout ( unused_cout_hi ) 31 | ); 32 | 33 | endmodule 34 | 35 | // 36 | // Usually one module in a file is recommended. 37 | // 38 | module add1 ( 39 | input a, 40 | input b, 41 | input cin, 42 | output sum, 43 | output cout 44 | ); 45 | 46 | assign {cout, sum} = a + b + cin; 47 | 48 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s27_m2014_q6b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q6b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [3:1] y, 11 | input w, 12 | output Y2 13 | ); 14 | 15 | parameter SA = 3'b000, 16 | SB = 3'b001, 17 | SC = 3'b010, 18 | SD = 3'b011, 19 | SE = 3'b100, 20 | SF = 3'b101; 21 | 22 | reg [3:1] Y; 23 | 24 | always @(*) begin 25 | case (y) 26 | SA : Y = w ? SA : SB; 27 | SB : Y = w ? SD : SC; 28 | SC : Y = w ? SD : SE; 29 | SD : Y = w ? SA : SF; 30 | SE : Y = w ? SD : SE; 31 | SF : Y = w ? SD : SC; 32 | default : Y = SA; 33 | endcase 34 | end 35 | 36 | assign Y2 = Y[2]; 37 | 38 | /* verilator lint_off UNUSED */ 39 | wire [1:0] unused; 40 | assign unused = {Y[3], Y[1]}; 41 | /* verilator lint_on UNUSED */ 42 | 43 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s21_ece241_2013_q8.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q8 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input aresetn, 12 | input x, 13 | output z 14 | ); 15 | 16 | parameter INIT = 2'd0, 17 | SEQ_1 = 2'd1, 18 | SEQ_10 = 2'd2; 19 | 20 | reg [1:0] state; 21 | reg [1:0] state_next; 22 | 23 | always @(posedge clk, negedge aresetn) begin 24 | if (~aresetn) begin 25 | state <= INIT; 26 | end else begin 27 | state <= state_next; 28 | end 29 | end 30 | 31 | always @(*) begin 32 | case (state) 33 | INIT : state_next = x ? SEQ_1 : INIT; 34 | SEQ_1 : state_next = x ? SEQ_1 : SEQ_10; 35 | SEQ_10 : state_next = x ? SEQ_1 : INIT; 36 | default : state_next = INIT; 37 | endcase 38 | end 39 | 40 | assign z = (state == SEQ_10) & x; 41 | 42 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c13_More_Circuits/s02_rule110.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Rule110 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | 10 | module top_module ( 11 | input clk, 12 | input load, 13 | input [511:0] data, 14 | output [511:0] q 15 | ); 16 | 17 | reg [511:0] q_reg; 18 | wire [511:0] q_next; 19 | always @(posedge clk) begin 20 | if (load) 21 | q_reg <= data; 22 | else 23 | q_reg <= q_next; 24 | end 25 | 26 | // 27 | // C' = (~R & C) | (R & ~C) | (~L & C) 28 | // 29 | // Specially, C0' = C and C511' = C | R 30 | // 31 | localparam BASE = 1, 32 | LIMIT = 511; 33 | 34 | assign q_next = {q_reg[511] | q_reg[510], 35 | ((~q_reg[LIMIT - 1 - 1:BASE - 1] & q_reg[LIMIT - 1:BASE]) | 36 | ( q_reg[LIMIT - 1 - 1:BASE - 1] & ~q_reg[LIMIT - 1:BASE]) | 37 | (~q_reg[LIMIT - 1 + 1:BASE + 1] & q_reg[LIMIT - 1:BASE])), 38 | q_reg[0]}; 39 | 40 | assign q = q_reg; 41 | 42 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s26_2014_q3c.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2014_q3c 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [2:0] y, 12 | input x, 13 | output Y0, 14 | output z 15 | ); 16 | 17 | parameter S0 = 3'b000, 18 | S1 = 3'b001, 19 | S2 = 3'b010, 20 | S3 = 3'b011, 21 | S4 = 3'b100; 22 | 23 | reg [2:0] Y; 24 | 25 | always @(*) begin 26 | case (y) 27 | S0 : Y = x ? S1 : S0; 28 | S1 : Y = x ? S2 : S1; 29 | S2 : Y = x ? S1 : S2; 30 | S3 : Y = x ? S2 : S1; 31 | S4 : Y = x ? S4 : S3; 32 | default : Y = S0; 33 | endcase 34 | end 35 | 36 | assign z = (y == S3) | (y == S4); 37 | 38 | assign Y0 = Y[0]; 39 | 40 | 41 | /* verilator lint_off UNUSED */ 42 | wire [2:0] unused; 43 | assign unused = {clk, Y[2:1]}; 44 | /* verilator lint_on UNUSED */ 45 | 46 | endmodule -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Gao Ya'nan 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s25_2014_q3bfsm.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2014_q3bfsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input x, 13 | output z 14 | ); 15 | 16 | parameter S0 = 3'b000, 17 | S1 = 3'b001, 18 | S2 = 3'b010, 19 | S3 = 3'b011, 20 | S4 = 3'b100; 21 | 22 | reg [2:0] state; 23 | reg [2:0] state_next; 24 | 25 | always @(posedge clk) begin 26 | if (reset) 27 | state <= S0; 28 | else 29 | state <= state_next; 30 | end 31 | 32 | always @(*) begin 33 | case (state) 34 | S0 : state_next = x ? S1 : S0; 35 | S1 : state_next = x ? S4 : S1; 36 | S2 : state_next = x ? S1 : S2; 37 | S3 : state_next = x ? S2 : S1; 38 | S4 : state_next = x ? S4 : S3; 39 | default : state_next = S0; 40 | endcase 41 | end 42 | 43 | assign z = (state == S3) | (state == S4); 44 | 45 | endmodule -------------------------------------------------------------------------------- /p04_Verification_Writing_Testbenches/s04_tb2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Tb/tb2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | `timescale 1ps/1ps 10 | 11 | module top_module ( ); 12 | 13 | localparam CLK_PERIOD = 10; 14 | 15 | reg clk; 16 | initial begin 17 | clk = 1'b0; 18 | 19 | forever 20 | #(CLK_PERIOD / 2) clk = ~clk; 21 | end 22 | 23 | reg in; 24 | reg [2:0] s; 25 | wire out; 26 | 27 | q7 q7_u0 ( 28 | .clk ( clk ), 29 | .in ( in ), 30 | .s ( s ), 31 | .out ( out ) 32 | ); 33 | 34 | initial begin 35 | in = 1'b0; 36 | s = 3'd2; 37 | 38 | @(negedge clk) 39 | s = 3'd6; 40 | 41 | @(negedge clk) 42 | in = 1'b1; 43 | s = 3'd2; 44 | 45 | @(negedge clk) 46 | in = 1'b0; 47 | s = 3'd7; 48 | 49 | @(negedge clk) 50 | in = 1'b1; 51 | s = 3'd0; 52 | 53 | repeat (2) @(negedge clk) /* hold for 2 cycles */; 54 | 55 | @(negedge clk) 56 | in = 1'b0; 57 | 58 | end 59 | 60 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s06_ece241_2014_q7b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q7b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | output OneHertz, 13 | output [2:0] c_enable 14 | ); 15 | 16 | wire [3:0] bcd0; 17 | bcdcount counter0 ( 18 | .clk ( clk ), 19 | .reset ( reset ), 20 | .enable ( c_enable[0] ), 21 | .Q ( bcd0 ) 22 | ); 23 | 24 | wire [3:0] bcd1; 25 | bcdcount counter1 ( 26 | .clk ( clk ), 27 | .reset ( reset ), 28 | .enable ( c_enable[1] ), 29 | .Q ( bcd1 ) 30 | ); 31 | 32 | wire [3:0] bcd2; 33 | bcdcount counter2 ( 34 | .clk ( clk ), 35 | .reset ( reset ), 36 | .enable ( c_enable[2] ), 37 | .Q ( bcd2 ) 38 | ); 39 | 40 | assign c_enable[0] = 1'b1; 41 | assign c_enable[1] = (bcd0 == 4'd9); 42 | assign c_enable[2] = (bcd1 == 4'd9) & c_enable[1]; 43 | 44 | assign OneHertz = (bcd2 == 4'd9) && c_enable[2]; 45 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s10_circuit10.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit10 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input a, 12 | input b, 13 | output q, 14 | output state 15 | ); 16 | 17 | // 18 | // For state 19 | // 20 | // ab 21 | // 22 | // d d' 00 01 11 10 23 | // 24 | // 0 0 0 1 0 25 | // 26 | // 1 0 1 1 1 27 | // 28 | // 29 | // d' = (a & b) | (d & a ) | (d & b) 30 | // 31 | // For q 32 | // 33 | // ab 34 | // 35 | // d q 00 01 11 10 36 | // 37 | // 0 0 1 0 1 38 | // 39 | // 1 1 0 1 0 40 | // 41 | // 42 | // q = d ^~ (a ^~ b) 43 | // 44 | 45 | reg r_d; 46 | wire r_d_next; 47 | 48 | always @(posedge clk) begin 49 | r_d <= r_d_next; 50 | end 51 | 52 | assign r_d_next = (a & b) | 53 | (r_d & a) | 54 | (r_d & b); 55 | 56 | assign q = r_d ^~ (a ^~b); 57 | assign state = r_d; 58 | 59 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s09_ece241_2013_q12.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q12 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input enable, 12 | input S, 13 | input A, 14 | input B, 15 | input C, 16 | output reg Z 17 | ); 18 | 19 | reg [7:0] q_reg; 20 | always @(posedge clk) begin 21 | if (enable) 22 | q_reg <= {q_reg[6:0], S}; 23 | // Usually the last no-change else branch could be omitted 24 | else 25 | q_reg <= q_reg; 26 | end 27 | 28 | always @(*) begin 29 | case({A, B, C}) 30 | 3'b000 : Z = q_reg[0]; 31 | 3'b001 : Z = q_reg[1]; 32 | 3'b010 : Z = q_reg[2]; 33 | 3'b011 : Z = q_reg[3]; 34 | 3'b100 : Z = q_reg[4]; 35 | 3'b101 : Z = q_reg[5]; 36 | 3'b110 : Z = q_reg[6]; 37 | 3'b111 : Z = q_reg[7]; 38 | endcase 39 | end 40 | 41 | // 42 | // The following code also works : 43 | // 44 | // assign Z = q_reg[{A, B, C}]; 45 | // 46 | // I will check which one is better 47 | // 48 | 49 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s03_adder3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Adder3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module fadd ( 13 | input a, 14 | input b, 15 | input cin, 16 | output cout, 17 | output sum 18 | ); 19 | 20 | assign {cout, sum} = a + b + cin; 21 | 22 | endmodule 23 | 24 | module top_module ( 25 | input [2:0] a, 26 | input [2:0] b, 27 | input cin, 28 | output [2:0] cout, 29 | output [2:0] sum 30 | ); 31 | 32 | fadd fadd_i0 ( 33 | .a ( a[0] ), 34 | .b ( b[0] ), 35 | .cin ( cin ), 36 | .cout ( cout[0] ), 37 | .sum ( sum[0] ) 38 | ); 39 | 40 | fadd fadd_i1 ( 41 | .a ( a[1] ), 42 | .b ( b[1] ), 43 | .cin ( cout[0] ), 44 | .cout ( cout[1] ), 45 | .sum ( sum[1] ) 46 | ); 47 | 48 | fadd fadd_i2 ( 49 | .a ( a[2] ), 50 | .b ( b[2] ), 51 | .cin ( cout[1] ), 52 | .cout ( cout[2] ), 53 | .sum ( sum[2] ) 54 | ); 55 | 56 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s29_m2014_q6.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q6 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input w, 13 | output z 14 | ); 15 | 16 | parameter SA = 3'b000, 17 | SB = 3'b001, 18 | SC = 3'b010, 19 | SD = 3'b011, 20 | SE = 3'b100, 21 | SF = 3'b101; 22 | 23 | reg [2:0] state; 24 | reg [2:0] state_next; 25 | 26 | always @(posedge clk) begin 27 | if (reset) 28 | state <= SA; 29 | else 30 | state <= state_next; 31 | end 32 | 33 | always @(*) begin 34 | case (state) 35 | SA : state_next = w ? SA : SB; 36 | SB : state_next = w ? SD : SC; 37 | SC : state_next = w ? SD : SE; 38 | SD : state_next = w ? SA : SF; 39 | SE : state_next = w ? SD : SE; 40 | SF : state_next = w ? SD : SC; 41 | default : state_next = SA; 42 | endcase 43 | end 44 | 45 | assign z = (state == SE) | (state == SF); 46 | 47 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s30_2012_q2fsm.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2012_q2fsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input w, 13 | output z 14 | ); 15 | 16 | parameter SA = 3'b000, 17 | SB = 3'b001, 18 | SC = 3'b010, 19 | SD = 3'b011, 20 | SE = 3'b100, 21 | SF = 3'b101; 22 | 23 | reg [2:0] state; 24 | reg [2:0] state_next; 25 | 26 | always @(posedge clk) begin 27 | if (reset) 28 | state <= SA; 29 | else 30 | state <= state_next; 31 | end 32 | 33 | always @(*) begin 34 | case (state) 35 | SA : state_next = w ? SB : SA; 36 | SB : state_next = w ? SC : SD; 37 | SC : state_next = w ? SE : SD; 38 | SD : state_next = w ? SF : SA; 39 | SE : state_next = w ? SE : SD; 40 | SF : state_next = w ? SC : SD; 41 | default : state_next = SA; 42 | endcase 43 | end 44 | 45 | assign z = (state == SE) | (state == SF); 46 | 47 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s31_2012_q2b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2012_q2fsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input w, 13 | output z 14 | ); 15 | 16 | parameter SA = 3'b000, 17 | SB = 3'b001, 18 | SC = 3'b010, 19 | SD = 3'b011, 20 | SE = 3'b100, 21 | SF = 3'b101; 22 | 23 | reg [2:0] state; 24 | reg [2:0] state_next; 25 | 26 | always @(posedge clk) begin 27 | if (reset) 28 | state <= SA; 29 | else 30 | state <= state_next; 31 | end 32 | 33 | always @(*) begin 34 | case (state) 35 | SA : state_next = w ? SB : SA; 36 | SB : state_next = w ? SC : SD; 37 | SC : state_next = w ? SE : SD; 38 | SD : state_next = w ? SF : SA; 39 | SE : state_next = w ? SE : SD; 40 | SF : state_next = w ? SC : SD; 41 | default : state_next = SA; 42 | endcase 43 | end 44 | 45 | assign z = (state == SE) | (state == SF); 46 | 47 | endmodule -------------------------------------------------------------------------------- /p03_Verification_Reading_Simulations/c17_Build_a_circurt_from_a_simulation_waveform/s02_circuit2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Sim/circuit2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input a, 11 | input b, 12 | input c, 13 | input d, 14 | output q 15 | ); 16 | 17 | // 18 | // ab 19 | // 20 | // cd q 00 01 11 10 21 | // 22 | // 00 1 0 1 0 23 | // 24 | // 01 0 1 0 1 25 | // 26 | // 11 1 0 1 0 27 | // 28 | // 10 0 1 0 1 29 | // 30 | // 31 | // q = (~a & ~b & ~c & ~d) | 32 | // (~a & ~b & c & d) | 33 | // (~a & b & ~c & d) | 34 | // (~a & b & c & ~d) | 35 | // ( a & b & ~c & ~d) | 36 | // ( a & b & c & d) | 37 | // ( a & ~b & ~c & d) | 38 | // ( a & ~b & c & ~d) 39 | // 40 | assign q = (~a & ~b & ~c & ~d) | 41 | (~a & ~b & c & d) | 42 | (~a & b & ~c & d) | 43 | (~a & b & c & ~d) | 44 | ( a & b & ~c & ~d) | 45 | ( a & b & c & d) | 46 | ( a & ~b & ~c & d) | 47 | ( a & ~b & c & ~d); 48 | 49 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s03_fsmseq.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/review2015_fsmseq 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input data, 13 | output start_shifting 14 | ); 15 | 16 | parameter CHECK_D1 = 3'd0, 17 | CHECK_D2 = 3'd1, 18 | CHECK_D3 = 3'd2, 19 | CHECK_D4 = 3'd3, 20 | CHECK_DONE = 3'd4; 21 | 22 | reg [2:0] state; 23 | reg [2:0] next_state; 24 | 25 | always@(posedge clk) begin 26 | if(reset) 27 | state <= CHECK_D1; 28 | else 29 | state <= next_state; 30 | end 31 | 32 | always@(*) begin 33 | case(state) 34 | CHECK_D1 : next_state = data ? CHECK_D2 : CHECK_D1; 35 | CHECK_D2 : next_state = data ? CHECK_D3 : CHECK_D1; 36 | CHECK_D3 : next_state = data ? CHECK_D3 : CHECK_D4; 37 | CHECK_D4 : next_state = data ? CHECK_DONE : CHECK_D1; 38 | CHECK_DONE : next_state = CHECK_DONE; 39 | default : next_state = CHECK_D1; 40 | endcase 41 | end 42 | 43 | assign start_shifting = (state == CHECK_DONE); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /p01_Verilog_Language/c03_Modules/s08_module_cseladd.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Module_cseladd 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input [31:0] a, 11 | input [31:0] b, 12 | output [31:0] sum 13 | ); 14 | 15 | wire cout_lo; 16 | wire [15:0] sum_lo; 17 | add16 add16_i0 ( 18 | .a ( a[15:0] ), 19 | .b ( b[15:0] ), 20 | .cin ( 1'b0 ), 21 | .sum ( sum_lo ), 22 | .cout ( cout_lo ) 23 | ); 24 | 25 | wire unused_cout_hi0; 26 | wire [15:0] sum_hi0; 27 | add16 add16_i1 ( 28 | .a ( a[31:16] ), 29 | .b ( b[31:16] ), 30 | .cin ( 1'b0 ), 31 | .sum ( sum_hi0 ), 32 | .cout ( unused_cout_hi0 ) 33 | ); 34 | 35 | wire unused_cout_hi1; 36 | wire [15:0] sum_hi1; 37 | add16 add16_i2 ( 38 | .a ( a[31:16] ), 39 | .b ( b[31:16] ), 40 | .cin ( 1'b1 ), 41 | .sum ( sum_hi1 ), 42 | .cout ( unused_cout_hi1 ) 43 | ); 44 | 45 | wire [15:0] sum_hi; 46 | assign sum_hi = cout_lo ? sum_hi1 : sum_hi0; 47 | 48 | assign sum = {sum_hi, sum_lo}; 49 | 50 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c06_Basic_Gates/s12_mt2015_q4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mt2015_q4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module mt2015_q4a ( 13 | input x, 14 | input y, 15 | output z 16 | ); 17 | 18 | assign z = (x ^ y) & x; 19 | 20 | endmodule 21 | 22 | // 23 | // Usually one module in a file is recommended. 24 | // 25 | module mt2015_q4b ( 26 | input x, 27 | input y, 28 | output z 29 | ); 30 | 31 | assign z = (x == y); 32 | 33 | endmodule 34 | 35 | module top_module ( 36 | input x, 37 | input y, 38 | output z 39 | ); 40 | 41 | wire z0; 42 | mt2015_q4a mt2015_q4a_i0 ( 43 | .x ( x ), 44 | .y ( y ), 45 | .z ( z0 ) 46 | ); 47 | 48 | wire z1; 49 | mt2015_q4b mt2015_q4b_i0 ( 50 | .x ( x ), 51 | .y ( y ), 52 | .z ( z1 ) 53 | ); 54 | 55 | wire z2; 56 | mt2015_q4a mt2015_q4a_i1 ( 57 | .x ( x ), 58 | .y ( y ), 59 | .z ( z2 ) 60 | ); 61 | 62 | wire z3; 63 | mt2015_q4b mt2015_q4b_i1 ( 64 | .x ( x ), 65 | .y ( y ), 66 | .z ( z3 ) 67 | ); 68 | 69 | assign z = (z0 | z1) ^ (z2 & z3); 70 | 71 | 72 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s15_fsm_ps2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_ps2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [7:0] in, 12 | input reset, 13 | output done 14 | ); 15 | 16 | parameter WAIT_B1 = 4'b0001, 17 | WAIT_B2 = 4'b0010, 18 | WAIT_B3 = 4'b0100, 19 | DONE = 4'b1000; 20 | 21 | reg [3:0] state; 22 | reg [3:0] state_next; 23 | 24 | // State transition logic (combinational) 25 | always @(*) begin 26 | case (state) 27 | WAIT_B1 : state_next = in[3] ? WAIT_B2 : WAIT_B1; 28 | WAIT_B2 : state_next = WAIT_B3; 29 | WAIT_B3 : state_next = DONE; 30 | DONE : state_next = in[3] ? WAIT_B2 : WAIT_B1; 31 | default : state_next = WAIT_B1; 32 | endcase 33 | end 34 | 35 | // State flip-flops (sequential) 36 | always @(posedge clk) begin 37 | if(reset) begin 38 | state <= WAIT_B1; 39 | end else begin 40 | state <= state_next; 41 | end 42 | end 43 | 44 | // Output logic 45 | assign done = (state == DONE); 46 | 47 | wire [6:0] unused; 48 | assign unused = {in[7:4], in[2:0]}; 49 | 50 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s05_mt2015_lfsr.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Mt2015_lfsr 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module mux_dff ( 13 | input clk, 14 | input L, 15 | input r_in, 16 | input q_in, 17 | output reg Q 18 | ); 19 | 20 | always @(posedge clk) begin 21 | if (L) 22 | Q <= r_in; 23 | else 24 | Q <= q_in; 25 | end 26 | 27 | endmodule 28 | 29 | module top_module ( 30 | input [2:0] SW, // R 31 | input [1:0] KEY, // L and clk 32 | output [2:0] LEDR // Q 33 | ); 34 | 35 | mux_dff mux_dff_i0 ( 36 | .clk ( KEY[0] ), 37 | .L ( KEY[1] ), 38 | .r_in ( SW[0] ), 39 | .q_in ( LEDR[2] ), 40 | .Q ( LEDR[0] ) 41 | ); 42 | 43 | mux_dff mux_dff_i1 ( 44 | .clk ( KEY[0] ), 45 | .L ( KEY[1] ), 46 | .r_in ( SW[1] ), 47 | .q_in ( LEDR[0] ), 48 | .Q ( LEDR[1] ) 49 | ); 50 | 51 | mux_dff mux_dff_i2 ( 52 | .clk ( KEY[0] ), 53 | .L ( KEY[1] ), 54 | .r_in ( SW[2] ), 55 | .q_in ( LEDR[1] ^ LEDR[2] ), 56 | .Q ( LEDR[2] ) 57 | ); 58 | 59 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s32_2013_q2afsm.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2013_q2afsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input resetn, 12 | input [3:1] r, 13 | output [3:1] g 14 | ); 15 | 16 | parameter STATE_A = 4'b0001, 17 | STATE_B = 4'b0010, 18 | STATE_C = 4'b0100, 19 | STATE_D = 4'b1000; 20 | 21 | reg [3:0] state; 22 | reg [3:0] state_next; 23 | 24 | always @(posedge clk) begin 25 | if (~resetn) begin 26 | state <= STATE_A; 27 | end else begin 28 | state <= state_next; 29 | end 30 | end 31 | 32 | always @(*) begin 33 | case (state) 34 | STATE_A : state_next = r[1] ? STATE_B : 35 | r[2] ? STATE_C : 36 | r[3] ? STATE_D : STATE_A; 37 | STATE_B : state_next = r[1] ? STATE_B : STATE_A; 38 | STATE_C : state_next = r[2] ? STATE_C : STATE_A; 39 | STATE_D : state_next = r[3] ? STATE_D : STATE_A; 40 | default : state_next = STATE_A; 41 | endcase 42 | end 43 | 44 | assign g = {state == STATE_D, state == STATE_C, state == STATE_B}; 45 | 46 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s24_2014_q3fsm.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/exams/2014_q3fsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input s, 13 | input w, 14 | output z 15 | ); 16 | 17 | parameter SA = 2'b00, 18 | SB = 2'b01, 19 | SB1 = 2'b10, 20 | SB2 = 2'b11; 21 | 22 | reg [1:0] state; 23 | reg [1:0] state_next; 24 | 25 | always @(posedge clk) begin 26 | if (reset) 27 | state <= SA; 28 | else 29 | state <= state_next; 30 | end 31 | 32 | always @(*) begin 33 | case (state) 34 | SA : state_next = s ? SB : SA; 35 | SB : state_next = SB1; 36 | SB1 : state_next = SB2; 37 | SB2 : state_next = SB; 38 | default : state_next = SA; 39 | endcase 40 | end 41 | 42 | reg [2:0] reg_w; 43 | wire reg_en; 44 | 45 | always @(posedge clk) begin 46 | if(reset) 47 | reg_w <= '0; 48 | else if (reg_en) 49 | reg_w <= {w, reg_w[2:1]}; 50 | end 51 | 52 | assign reg_en = (state != SA); 53 | 54 | assign z = (state == SB) & (~^reg_w) & (|reg_w); 55 | 56 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c08_Arithmetic_Circuits/s04_m2014_q4j.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/m2014_q4j 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module fadd ( 13 | input a, 14 | input b, 15 | input cin, 16 | output cout, 17 | output sum 18 | ); 19 | 20 | assign {cout, sum} = a + b + cin; 21 | 22 | endmodule 23 | 24 | module top_module ( 25 | input [3:0] x, 26 | input [3:0] y, 27 | output [4:0] sum 28 | ); 29 | 30 | wire [2:0] cout; 31 | 32 | fadd fadd_i0 ( 33 | .a ( x[0] ), 34 | .b ( y[0] ), 35 | .cin ( 1'b0 ), 36 | .cout ( cout[0] ), 37 | .sum ( sum[0] ) 38 | ); 39 | 40 | fadd fadd_i1 ( 41 | .a ( x[1] ), 42 | .b ( y[1] ), 43 | .cin ( cout[0] ), 44 | .cout ( cout[1] ), 45 | .sum ( sum[1] ) 46 | ); 47 | 48 | fadd fadd_i2 ( 49 | .a ( x[2] ), 50 | .b ( y[2] ), 51 | .cin ( cout[1] ), 52 | .cout ( cout[2] ), 53 | .sum ( sum[2] ) 54 | ); 55 | 56 | fadd fadd_i3 ( 57 | .a ( x[3] ), 58 | .b ( y[3] ), 59 | .cin ( cout[2] ), 60 | .cout ( sum[4] ), 61 | .sum ( sum[3] ) 62 | ); 63 | 64 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s14_fsm_onehot.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_onehot 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | /* verilator lint_off DECLFILENAME */ 10 | module top_module ( 11 | /* verilator lint_on DECLFILENAME */ 12 | input in, 13 | input [9:0] state, 14 | output [9:0] next_state, 15 | output out1, 16 | output out2 17 | ); 18 | 19 | 20 | assign next_state[0] = state[0] & !in | 21 | state[1] & !in | 22 | state[2] & !in | 23 | state[3] & !in | 24 | state[4] & !in | 25 | state[7] & !in | 26 | state[8] & !in | 27 | state[9] & !in; 28 | assign next_state[1] = state[0] & in | 29 | state[8] & in | 30 | state[9] & in; 31 | assign next_state[2] = state[1] & in; 32 | assign next_state[3] = state[2] & in; 33 | assign next_state[4] = state[3] & in; 34 | assign next_state[5] = state[4] & in; 35 | assign next_state[6] = state[5] & in; 36 | assign next_state[7] = state[6] & in | 37 | state[7] & in; 38 | assign next_state[8] = state[5] & !in; 39 | assign next_state[9] = state[6] & !in; 40 | 41 | assign out1 = state[8] | state[9]; 42 | assign out2 = state[7] | state[9]; 43 | 44 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s16_fsm_ps2data.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_ps2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input [7:0] in, 12 | input reset, 13 | output [23:0] out_bytes, 14 | output done 15 | ); 16 | 17 | parameter WAIT_B1 = 4'b0001, 18 | WAIT_B2 = 4'b0010, 19 | WAIT_B3 = 4'b0100, 20 | DONE = 4'b1000; 21 | 22 | reg [3:0] state; 23 | reg [3:0] state_next; 24 | 25 | // State transition logic (combinational) 26 | always @(*) begin 27 | case (state) 28 | WAIT_B1 : state_next = in[3] ? WAIT_B2 : WAIT_B1; 29 | WAIT_B2 : state_next = WAIT_B3; 30 | WAIT_B3 : state_next = DONE; 31 | DONE : state_next = in[3] ? WAIT_B2 : WAIT_B1; 32 | default : state_next = WAIT_B1; 33 | endcase 34 | end 35 | 36 | // State flip-flops (sequential) 37 | always @(posedge clk) begin 38 | if(reset) begin 39 | state <= WAIT_B1; 40 | end else begin 41 | state <= state_next; 42 | end 43 | end 44 | 45 | // Output logic 46 | assign done = (state == DONE); 47 | 48 | reg [23:0] data; 49 | always @(posedge clk) begin 50 | if (reset) begin 51 | data <= '0; 52 | end else begin 53 | data <= {data[15:0], in}; 54 | end 55 | end 56 | 57 | assign out_bytes = data; 58 | 59 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s11_lemmings2.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Lemmings2 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input bump_left, 13 | input bump_right, 14 | input ground, 15 | output walk_left, 16 | output walk_right, 17 | output aaah 18 | ); 19 | 20 | parameter LEFT = 4'b0001, 21 | LEFT_FALL = 4'b0010, 22 | RIGHT = 4'b0100, 23 | RIGHT_FALL = 4'b1000; 24 | 25 | reg [3:0] state; 26 | reg [3:0] next_state; 27 | 28 | always @(*) begin 29 | case (state) 30 | LEFT : next_state = (~ground) ? LEFT_FALL : 31 | (bump_left) ? RIGHT : LEFT; 32 | LEFT_FALL : next_state = (ground) ? LEFT : state; 33 | RIGHT : next_state = (~ground) ? RIGHT_FALL : 34 | (bump_right) ? LEFT : RIGHT; 35 | RIGHT_FALL : next_state = (ground) ? RIGHT : state; 36 | default : next_state = state; 37 | endcase 38 | end 39 | 40 | always @(posedge clk, posedge areset) begin 41 | if (areset) 42 | state <= LEFT; 43 | else 44 | state <= next_state; 45 | end 46 | 47 | assign walk_left = (state == LEFT); 48 | assign walk_right = (state == RIGHT); 49 | assign aaah = (state == LEFT_FALL) | (state == RIGHT_FALL); 50 | 51 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c12_Shift_Registers/s08_2014_q4b.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2014_q4b 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module mux_dff ( 13 | input clk, 14 | input L, 15 | input r_in, 16 | input q_in, 17 | output reg Q 18 | ); 19 | 20 | always @(posedge clk) begin 21 | if (L) 22 | Q <= r_in; 23 | else 24 | Q <= q_in; 25 | end 26 | 27 | endmodule 28 | 29 | module top_module ( 30 | input [3:0] SW, 31 | input [3:0] KEY, 32 | output [3:0] LEDR 33 | ); 34 | 35 | wire [3:0] q_in; 36 | 37 | assign q_in = KEY[1] ? {KEY[3], LEDR[3:1]} : LEDR; 38 | 39 | mux_dff mux_dff_i0 ( 40 | .clk ( KEY[0] ), 41 | .L ( KEY[2] ), 42 | .r_in ( SW[0] ), 43 | .q_in ( q_in[0] ), 44 | .Q ( LEDR[0] ) 45 | ); 46 | 47 | mux_dff mux_dff_i1 ( 48 | .clk ( KEY[0] ), 49 | .L ( KEY[2] ), 50 | .r_in ( SW[1] ), 51 | .q_in ( q_in[1] ), 52 | .Q ( LEDR[1] ) 53 | ); 54 | 55 | mux_dff mux_dff_i2 ( 56 | .clk ( KEY[0] ), 57 | .L ( KEY[2] ), 58 | .r_in ( SW[2] ), 59 | .q_in ( q_in[2] ), 60 | .Q ( LEDR[2] ) 61 | ); 62 | 63 | mux_dff mux_dff_i3 ( 64 | .clk ( KEY[0] ), 65 | .L ( KEY[2] ), 66 | .r_in ( SW[3] ), 67 | .q_in ( q_in[3] ), 68 | .Q ( LEDR[3] ) 69 | ); 70 | 71 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s07_fsmonehot.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/review2015_fsmonehot 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input d, 11 | input done_counting, 12 | input ack, 13 | input [9:0] state, 14 | output B3_next, 15 | output S_next, 16 | output S1_next, 17 | output Count_next, 18 | output Wait_next, 19 | output done, 20 | output counting, 21 | output shift_ena 22 | ); 23 | 24 | parameter S = 0, 25 | S1 = 1, 26 | S11 = 2, 27 | S110 = 3, 28 | B0 = 4, 29 | B1 = 5, 30 | B2 = 6, 31 | B3 = 7, 32 | Count = 8, 33 | Wait = 9; 34 | 35 | assign B3_next = state[B2]; 36 | 37 | assign S_next = (state[S] & !d) | 38 | (state[S1] & !d) | 39 | (state[S110] & !d) | 40 | (state[Wait] & ack); 41 | 42 | assign S1_next = (state[S] & d); 43 | 44 | assign Count_next = (state[B3]) | 45 | (state[Count] & !done_counting); 46 | 47 | assign Wait_next = (state[Count] & done_counting) | 48 | (state[Wait] & !ack); 49 | 50 | assign done = state[Wait]; 51 | assign counting = state[Count]; 52 | assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3]; 53 | 54 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s05_ece241_2014_q7a.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q7a 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input enable, 13 | output [3:0] Q, 14 | output c_enable, 15 | output c_load, 16 | output [3:0] c_d 17 | ); 18 | 19 | wire [3:0] counter_next; 20 | wire counter_load; 21 | wire counter_enable; 22 | 23 | always @(*) begin 24 | counter_load = 1'b0; 25 | counter_enable = enable; 26 | 27 | if (reset) begin 28 | counter_load = 1'b1; 29 | 30 | counter_next = 4'd1; 31 | end 32 | else 33 | if (enable) 34 | if (Q == 4'hd - 1'b1) begin 35 | counter_load = 1'b1; 36 | 37 | counter_next = 4'd1; 38 | end 39 | else 40 | counter_next = Q + 1'b1; 41 | else 42 | counter_next = Q; 43 | end 44 | 45 | count4 the_counter ( 46 | .clk ( clk ), 47 | .enable ( counter_enable ), 48 | .load ( counter_load ), 49 | .d ( counter_next ), 50 | .Q ( Q ) 51 | ); 52 | 53 | assign c_enable = counter_enable; 54 | assign c_load = counter_load; 55 | // 56 | // I expected the following code would work before I failed to pass the tests 57 | // 58 | // assign c_d = counter_next; 59 | // 60 | // 61 | assign c_d = counter_load ? 4'b1 : '0; 62 | 63 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s17_fsm_serial.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_serial 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input clk, 11 | input in, 12 | input reset, 13 | output done 14 | ); 15 | 16 | parameter BIT_START = 4'd0, 17 | BIT_B0 = 4'd1, 18 | BIT_B1 = 4'd2, 19 | BIT_B2 = 4'd3, 20 | BIT_B3 = 4'd4, 21 | BIT_B4 = 4'd5, 22 | BIT_B5 = 4'd6, 23 | BIT_B6 = 4'd7, 24 | BIT_B7 = 4'd8, 25 | BIT_STOP = 4'd9, 26 | DONE = 4'd10, 27 | ERROR = 4'd11; 28 | 29 | reg [3:0] state; 30 | reg [3:0] state_next; 31 | 32 | always @(posedge clk) begin 33 | if (reset) begin 34 | state <= BIT_START; 35 | end else begin 36 | state <= state_next; 37 | end 38 | end 39 | 40 | always @(*) begin 41 | case (state) 42 | BIT_START : state_next = in ? BIT_START : BIT_B0; 43 | BIT_B0 , 44 | BIT_B1 , 45 | BIT_B2 , 46 | BIT_B3 , 47 | BIT_B4 , 48 | BIT_B5 , 49 | BIT_B6 , 50 | BIT_B7 : state_next = state + 1'b1; 51 | BIT_STOP : state_next = in ? DONE : ERROR; 52 | DONE : state_next = in ? BIT_START : BIT_B0; 53 | ERROR : state_next = in ? BIT_START : ERROR; 54 | default : state_next = BIT_START; 55 | endcase 56 | end 57 | 58 | assign done = (state == DONE); 59 | 60 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s33_2013_q2bfsm.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/2013_q2bfsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input resetn, 12 | input x, 13 | input y, 14 | output f, 15 | output g 16 | ); 17 | 18 | parameter STATE_A = 4'd0, 19 | OUTPUT_F1 = 4'd1, 20 | CHECK_X0 = 4'd2, 21 | CHECK_X1 = 4'd3, 22 | CHECK_X2 = 4'd4, 23 | OUTPUT_G1 = 4'd5, 24 | DONE_G1 = 4'd6, 25 | CHECK_Y = 4'd7, 26 | DONE_G0 = 4'd8; 27 | 28 | reg [3:0] state; 29 | reg [3:0] next_state; 30 | 31 | always@(posedge clk) begin 32 | if(~resetn) 33 | state <= STATE_A; 34 | else 35 | state <= next_state; 36 | end 37 | 38 | always@(*) begin 39 | case(state) 40 | STATE_A : next_state = resetn ? OUTPUT_F1 : STATE_A; 41 | OUTPUT_F1 : next_state = CHECK_X0; 42 | CHECK_X0 : next_state = x ? CHECK_X1 : CHECK_X0; 43 | CHECK_X1 : next_state = x ? CHECK_X1 : CHECK_X2; 44 | CHECK_X2 : next_state = x ? OUTPUT_G1 : CHECK_X0; 45 | OUTPUT_G1 : next_state = y ? DONE_G1 : CHECK_Y; 46 | CHECK_Y : next_state = y ? DONE_G1 : DONE_G0; 47 | DONE_G1 : next_state = resetn ? DONE_G1 : STATE_A; 48 | DONE_G0 : next_state = resetn ? DONE_G0 : STATE_A; 49 | default : next_state = STATE_A; 50 | endcase 51 | end 52 | 53 | assign f = (state == OUTPUT_F1); 54 | assign g = (state == OUTPUT_G1) | (state == CHECK_Y) | (state == DONE_G1); 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s20_fsm_hdlc.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_hdlc 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input in, 13 | output disc, 14 | output flag, 15 | output err 16 | ); 17 | 18 | parameter INIT = 4'd0, 19 | ONES_2 = 4'd1, 20 | ONES_3 = 4'd2, 21 | ONES_4 = 4'd3, 22 | ONES_5 = 4'd4, 23 | DISC = 4'd5, 24 | DISC_DONE = 4'd6, 25 | FLAG = 4'd7, 26 | FLAG_DONE = 4'd8, 27 | ERROR = 4'd9; 28 | 29 | reg [3:0] state; 30 | reg [3:0] state_next; 31 | 32 | always @(posedge clk) begin 33 | if (reset) begin 34 | state <= INIT; 35 | end else begin 36 | state <= state_next; 37 | end 38 | end 39 | 40 | always @(*) begin 41 | case (state) 42 | INIT , 43 | ONES_2 , 44 | ONES_3 , 45 | ONES_4 , 46 | ONES_5 : state_next = in ? (state + 1'b1) : INIT; 47 | DISC : state_next = in ? FLAG : DISC_DONE; 48 | DISC_DONE : state_next = in ? ONES_2 : INIT; 49 | FLAG : state_next = in ? ERROR : FLAG_DONE; 50 | FLAG_DONE : state_next = in ? ONES_2 : INIT; 51 | ERROR : state_next = in ? ERROR : INIT; 52 | default : state_next = INIT; 53 | endcase 54 | end 55 | 56 | assign disc = (state == DISC_DONE); 57 | assign flag = (state == FLAG_DONE); 58 | assign err = (state == ERROR); 59 | 60 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s07_countbcd.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Countbcd 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module bcd_counter ( 13 | input clk, 14 | input reset, 15 | input enable, 16 | output tick, 17 | output [3:0] bcd 18 | ); 19 | reg [3:0] counter; 20 | 21 | always @(posedge clk) begin 22 | if (reset) 23 | counter <= '0; 24 | else 25 | if (enable) 26 | if (counter == 4'd10 - 1'b1) 27 | counter <= '0; 28 | else 29 | counter <= counter + 1'b1; 30 | // Usually the last no-change else branch could be omitted 31 | else 32 | counter <= counter; 33 | end 34 | 35 | assign bcd = counter; 36 | assign tick = enable && (counter == 4'd10 - 1'b1); 37 | 38 | endmodule 39 | 40 | module top_module ( 41 | input clk, 42 | input reset, 43 | output [3:1] ena, 44 | output [15:0] q 45 | ); 46 | 47 | reg [4:0] enable; 48 | 49 | assign enable[0] = 1'b1; 50 | 51 | generate 52 | genvar i; 53 | for (i = 0; i < 4; i = i + 1) begin : loop 54 | bcd_counter bcd_counter_i ( 55 | .clk ( clk ), 56 | .reset ( reset ), 57 | .enable ( enable[i] ), 58 | .tick ( enable[i+1] ), 59 | .bcd ( q[4 * i + 3 : 4 * i] ) 60 | ); 61 | end 62 | endgenerate 63 | 64 | assign ena = enable[3:1]; 65 | 66 | /* verilator lint_off UNUSED */ 67 | wire [0:0] unused; 68 | assign unused = {enable[4]}; 69 | /* verilator lint_on UNUSED */ 70 | 71 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s09_ece241_2013_q4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input [3:1] s, 13 | output fr3, 14 | output fr2, 15 | output fr1, 16 | output dfr 17 | ); 18 | 19 | 20 | parameter BELOW_S1 = 6'b000001, 21 | S1_TO_S2 = 6'b000010, 22 | S2_TO_S3 = 6'b000100, 23 | ABOVE_S3 = 6'b001000, 24 | S3_TO_S2 = 6'b010000, 25 | S2_TO_S1 = 6'b100000; 26 | 27 | reg [5:0] state; 28 | reg [5:0] state_next; 29 | 30 | always @ (posedge clk) begin 31 | if(reset) 32 | state <= BELOW_S1; 33 | else 34 | state <= state_next; 35 | end 36 | 37 | always @ (*) begin 38 | case (state) 39 | BELOW_S1 : state_next = (s[3:1] == 3'b001) ? S1_TO_S2 : state; 40 | S1_TO_S2 : state_next = (s[3:1] == 3'b011) ? S2_TO_S3 : (s[3:1] == 3'b000) ? BELOW_S1 : state; 41 | S2_TO_S3 : state_next = (s[3:1] == 3'b111) ? ABOVE_S3 : (s[3:1] == 3'b001) ? S2_TO_S1 : state; 42 | ABOVE_S3 : state_next = (s[3:1] == 3'b011) ? S3_TO_S2 : state; 43 | S3_TO_S2 : state_next = (s[3:1] == 3'b001) ? S2_TO_S1 : (s[3:1] == 3'b111) ? ABOVE_S3 : state; 44 | S2_TO_S1 : state_next = (s[3:1] == 3'b000) ? BELOW_S1 : (s[3:1] == 3'b011) ? S2_TO_S3 : state; 45 | default : state_next = state; 46 | endcase 47 | end 48 | 49 | assign fr3 = (state == BELOW_S1); 50 | assign fr2 = (state == BELOW_S1) | (state == S1_TO_S2) | (state == S2_TO_S1); 51 | assign fr1 = (state != ABOVE_S3); 52 | assign dfr = (state == BELOW_S1) | (state == S3_TO_S2) | (state == S2_TO_S1); 53 | 54 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s18_fsm_serialdata.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_serialdata 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input clk, 11 | input in, 12 | input reset, 13 | output [7:0] out_byte, 14 | output done 15 | ); 16 | 17 | parameter BIT_START = 4'd0, 18 | BIT_B0 = 4'd1, 19 | BIT_B1 = 4'd2, 20 | BIT_B2 = 4'd3, 21 | BIT_B3 = 4'd4, 22 | BIT_B4 = 4'd5, 23 | BIT_B5 = 4'd6, 24 | BIT_B6 = 4'd7, 25 | BIT_B7 = 4'd8, 26 | BIT_STOP = 4'd9, 27 | DONE = 4'd10, 28 | ERROR = 4'd11; 29 | 30 | reg [3:0] state; 31 | reg [3:0] state_next; 32 | 33 | always @(posedge clk) begin 34 | if (reset) begin 35 | state <= BIT_START; 36 | end else begin 37 | state <= state_next; 38 | end 39 | end 40 | 41 | always @(*) begin 42 | case (state) 43 | BIT_START : state_next = in ? BIT_START : BIT_B0; 44 | BIT_B0 , 45 | BIT_B1 , 46 | BIT_B2 , 47 | BIT_B3 , 48 | BIT_B4 , 49 | BIT_B5 , 50 | BIT_B6 , 51 | BIT_B7 : state_next = state + 1'b1; 52 | BIT_STOP : state_next = in ? DONE : ERROR; 53 | DONE : state_next = in ? BIT_START : BIT_B0; 54 | ERROR : state_next = in ? BIT_START : ERROR; 55 | default : state_next = BIT_START; 56 | endcase 57 | end 58 | 59 | assign done = (state == DONE); 60 | 61 | reg [7:0] data; 62 | 63 | always @(posedge clk) begin 64 | if (state < BIT_STOP) 65 | data <= {in, data[7:1]}; 66 | end 67 | 68 | assign out_byte = data; 69 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s05_fsm.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/review2015_fsm 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, // Synchronous reset 12 | input data, 13 | output shift_ena, 14 | output counting, 15 | input done_counting, 16 | output done, 17 | input ack 18 | ); 19 | 20 | parameter CHECK_D1 = 4'd0, 21 | CHECK_D2 = 4'd1, 22 | CHECK_D3 = 4'd2, 23 | CHECK_D4 = 4'd3, 24 | STATUS_B0 = 4'd4, 25 | STATUS_B1 = 4'd5, 26 | STATUS_B2 = 4'd6, 27 | STATUS_B3 = 4'd7, 28 | COUNT_START = 4'd8, 29 | COUNT_WAIT = 4'd9; 30 | 31 | reg [3:0] state; 32 | reg [3:0] next_state; 33 | 34 | always@(posedge clk) begin 35 | if(reset) 36 | state <= CHECK_D1; 37 | else 38 | state <= next_state; 39 | end 40 | 41 | always@(*) begin 42 | case(state) 43 | CHECK_D1 : next_state = data ? CHECK_D2 : CHECK_D1; 44 | CHECK_D2 : next_state = data ? CHECK_D3 : CHECK_D1; 45 | CHECK_D3 : next_state = data ? CHECK_D3 : CHECK_D4; 46 | CHECK_D4 : next_state = data ? STATUS_B0 : CHECK_D1; 47 | STATUS_B0 : next_state = STATUS_B1; 48 | STATUS_B1 : next_state = STATUS_B2; 49 | STATUS_B2 : next_state = STATUS_B3; 50 | STATUS_B3 : next_state = COUNT_START; 51 | COUNT_START : next_state = done_counting ? COUNT_WAIT : COUNT_START; 52 | COUNT_WAIT : next_state = ack ? CHECK_D1 : COUNT_WAIT; 53 | default : next_state = CHECK_D1; 54 | endcase 55 | end 56 | 57 | assign shift_ena = (state == STATUS_B0) | (state == STATUS_B1) | (state == STATUS_B2) | (state == STATUS_B3); 58 | assign counting = (state == COUNT_START); 59 | assign done = (state == COUNT_WAIT); 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s12_lemmings3.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Lemmings3 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input bump_left, 13 | input bump_right, 14 | input ground, 15 | input dig, 16 | output walk_left, 17 | output walk_right, 18 | output aaah, 19 | output digging 20 | ); 21 | 22 | parameter LEFT = 6'b000001, 23 | LEFT_FALL = 6'b000010, 24 | LEFT_DIG = 6'b000100, 25 | RIGHT = 6'b001000, 26 | RIGHT_FALL = 6'b010000, 27 | RIGHT_DIG = 6'b100000; 28 | 29 | reg [5:0] state; 30 | reg [5:0] next_state; 31 | 32 | always @(*) begin 33 | case (state) 34 | LEFT : next_state = (~ground) ? LEFT_FALL : 35 | (dig) ? LEFT_DIG : 36 | (bump_left) ? RIGHT : LEFT; 37 | LEFT_FALL : next_state = (ground) ? LEFT : state; 38 | LEFT_DIG : next_state = (~ground) ? LEFT_FALL : state; 39 | RIGHT : next_state = (~ground) ? RIGHT_FALL : 40 | (dig) ? RIGHT_DIG : 41 | (bump_right) ? LEFT : RIGHT; 42 | RIGHT_FALL : next_state = (ground) ? RIGHT : state; 43 | RIGHT_DIG : next_state = (~ground) ? RIGHT_FALL : state; 44 | 45 | default : next_state = state; 46 | endcase 47 | end 48 | 49 | always @(posedge clk, posedge areset) begin 50 | if (areset) 51 | state <= LEFT; 52 | else 53 | state <= next_state; 54 | end 55 | 56 | assign walk_left = (state == LEFT); 57 | assign walk_right = (state == RIGHT); 58 | assign aaah = (state == LEFT_FALL) | (state == RIGHT_FALL); 59 | assign digging = (state == LEFT_DIG) | (state == RIGHT_DIG); 60 | 61 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s19_fsm_serialdp.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Fsm_serialdp 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module( 10 | input clk, 11 | input in, 12 | input reset, 13 | output [7:0] out_byte, 14 | output done 15 | ); 16 | 17 | parameter START = 4'd0, 18 | BIT_B0 = 4'd1, 19 | BIT_B1 = 4'd2, 20 | BIT_B2 = 4'd3, 21 | BIT_B3 = 4'd4, 22 | BIT_B4 = 4'd5, 23 | BIT_B5 = 4'd6, 24 | BIT_B6 = 4'd7, 25 | BIT_B7 = 4'd8, 26 | CHECK = 4'd9, 27 | STOP = 4'd10, 28 | IDLE = 4'd11, 29 | ERROR = 4'd12; 30 | 31 | reg [3:0] state; 32 | reg [3:0] state_next; 33 | 34 | always @(posedge clk) begin 35 | if (reset) 36 | state <= IDLE; 37 | else begin 38 | state <= state_next; 39 | end 40 | end 41 | 42 | always @(*) begin 43 | case (state) 44 | START , 45 | BIT_B0 , 46 | BIT_B1 , 47 | BIT_B2 , 48 | BIT_B3 , 49 | BIT_B4 , 50 | BIT_B5 , 51 | BIT_B6 , 52 | BIT_B7 : state_next = state + 1'b1; 53 | CHECK : state_next = in ? STOP : ERROR; 54 | STOP : state_next = in ? IDLE : START; 55 | IDLE : state_next = in ? IDLE : START; 56 | ERROR : state_next = in ? IDLE : ERROR; 57 | default : state_next = IDLE; 58 | endcase 59 | end 60 | 61 | wire parity_reset; 62 | wire odd; 63 | 64 | assign parity_reset = (state == IDLE) | (state == STOP); 65 | 66 | parity parity_u0 ( 67 | .clk ( clk ), 68 | .reset ( reset | parity_reset ), 69 | .in ( in ), 70 | .odd ( odd ) 71 | ); 72 | 73 | reg valid; 74 | 75 | always @(posedge clk) begin 76 | valid <= odd; 77 | end 78 | 79 | assign done = (valid & (state == STOP)); 80 | 81 | reg [7:0] data; 82 | 83 | always @(posedge clk) begin 84 | if (state < BIT_B7) 85 | data <= {in, data[7:1]}; 86 | end 87 | 88 | assign out_byte = data; 89 | 90 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c14_Finite_State_Machines/s13_lemmings4.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Lemmings4 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input areset, 12 | input bump_left, 13 | input bump_right, 14 | input ground, 15 | input dig, 16 | output walk_left, 17 | output walk_right, 18 | output aaah, 19 | output digging 20 | ); 21 | 22 | parameter LEFT = 7'b0000001, 23 | LEFT_FALL = 7'b0000010, 24 | LEFT_DIG = 7'b0000100, 25 | RIGHT = 7'b0001000, 26 | RIGHT_FALL = 7'b0010000, 27 | RIGHT_DIG = 7'b0100000, 28 | SPLATTER = 7'b1000000; 29 | 30 | reg [4:0] counter; 31 | reg counter_en; 32 | 33 | always @(posedge clk, posedge areset) begin 34 | if (areset) 35 | counter <= '0; 36 | else if (counter_en) 37 | if (counter == 5'd20 - 1'b1) 38 | counter <= '0; 39 | else 40 | counter <= counter + 1'b1; 41 | else 42 | counter <= '0; 43 | end 44 | 45 | reg fall_too_long; 46 | 47 | always @(posedge clk, posedge areset) begin 48 | if (areset) 49 | fall_too_long <= '0; 50 | else if (counter_en) 51 | if (counter == 5'd20 - 1'b1) 52 | fall_too_long <= 1'b1; 53 | end 54 | 55 | reg [6:0] state; 56 | reg [6:0] next_state; 57 | 58 | always @(*) begin 59 | counter_en = (state == LEFT_FALL) | (state == RIGHT_FALL); 60 | 61 | case (state) 62 | LEFT : next_state = (~ground) ? LEFT_FALL : 63 | (dig) ? LEFT_DIG : 64 | (bump_left) ? RIGHT : LEFT; 65 | LEFT_FALL : next_state = (~ground) ? state : 66 | (fall_too_long) ? SPLATTER : LEFT; 67 | LEFT_DIG : next_state = (~ground) ? LEFT_FALL : state; 68 | RIGHT : next_state = (~ground) ? RIGHT_FALL : 69 | (dig) ? RIGHT_DIG : 70 | (bump_right) ? LEFT : RIGHT; 71 | RIGHT_FALL : next_state = (~ground) ? state : 72 | (fall_too_long) ? SPLATTER : RIGHT; 73 | RIGHT_DIG : next_state = (~ground) ? RIGHT_FALL : state; 74 | 75 | SPLATTER : next_state = state; 76 | default : next_state = state; 77 | endcase 78 | end 79 | 80 | always @(posedge clk, posedge areset) begin 81 | if (areset) 82 | state <= LEFT; 83 | else 84 | state <= next_state; 85 | end 86 | 87 | assign walk_left = (state == LEFT); 88 | assign walk_right = (state == RIGHT); 89 | assign aaah = (state == LEFT_FALL) | (state == RIGHT_FALL); 90 | assign digging = (state == LEFT_DIG) | (state == RIGHT_DIG); 91 | 92 | endmodule -------------------------------------------------------------------------------- /p02_Cirucuits/c13_More_Circuits/s03_conwaylife.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Conwaylife 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | function integer NIBBLE; 10 | input integer i; 11 | begin 12 | NIBBLE = (i + 16) & 15; 13 | end 14 | endfunction 15 | 16 | function integer Y; 17 | input integer i; 18 | begin 19 | Y = i & 15; 20 | end 21 | endfunction 22 | 23 | function integer X; 24 | input integer i; 25 | begin 26 | X = (i >> 4 ) & 15; 27 | end 28 | endfunction 29 | 30 | function integer POS; 31 | input integer x; 32 | input integer y; 33 | begin 34 | POS = (x << 4) + y; 35 | end 36 | endfunction 37 | 38 | module cell_state ( 39 | input [8:0] bits, 40 | output reg alive 41 | ); 42 | 43 | always @(*) begin 44 | case ({bits[8:5], bits[3:0]}) 45 | 8'h03, 8'h05, 8'h06, 8'h09, 46 | 8'h0a, 8'h0c, 8'h11, 8'h12, 47 | 8'h14, 8'h18, 8'h21, 8'h22, 48 | 8'h24, 8'h28, 8'h30, 8'h41, 49 | 8'h42, 8'h44, 8'h48, 8'h50, 50 | 8'h60, 8'h81, 8'h82, 8'h84, 51 | 8'h88, 8'h90, 8'ha0, 8'hc0 : alive = bits[4]; 52 | 8'h07, 8'h0b, 8'h0d, 8'h0e, 53 | 8'h13, 8'h15, 8'h16, 8'h19, 54 | 8'h1a, 8'h1c, 8'h23, 8'h25, 55 | 8'h26, 8'h29, 8'h2a, 8'h2c, 56 | 8'h31, 8'h32, 8'h34, 8'h38, 57 | 8'h43, 8'h45, 8'h46, 8'h49, 58 | 8'h4a, 8'h4c, 8'h51, 8'h52, 59 | 8'h54, 8'h58, 8'h61, 8'h62, 60 | 8'h64, 8'h68, 8'h70, 8'h83, 61 | 8'h85, 8'h86, 8'h89, 8'h8a, 62 | 8'h8c, 8'h91, 8'h92, 8'h94, 63 | 8'h98, 8'ha1, 8'ha2, 8'ha4, 64 | 8'ha8, 8'hb0, 8'hc1, 8'hc2, 65 | 8'hc4, 8'hc8, 8'hd0, 8'he0 : alive = 1'b1; 66 | default : alive = 1'b0; 67 | endcase 68 | end 69 | 70 | endmodule 71 | 72 | module top_module ( 73 | input clk, 74 | input load, 75 | input [255:0] data, 76 | output [255:0] q 77 | ); 78 | 79 | reg [255:0] q_reg; 80 | wire [255:0] q_next; 81 | always @(posedge clk) begin 82 | if (load) 83 | q_reg <= data; 84 | else 85 | q_reg <= q_next; 86 | end 87 | 88 | // 89 | // 90 | // 91 | generate 92 | genvar i; 93 | for (i = 0; i < 256; i = i + 1) begin : loop 94 | wire [8:0] cells; 95 | 96 | assign cells = { 97 | q_reg[POS(NIBBLE(X(i) - 1), NIBBLE(Y(i) + 1))], 98 | q_reg[POS(NIBBLE(X(i) ), NIBBLE(Y(i) + 1))], 99 | q_reg[POS(NIBBLE(X(i) + 1), NIBBLE(Y(i) + 1))], 100 | q_reg[POS(NIBBLE(X(i) - 1), NIBBLE(Y(i) ))], 101 | q_reg[POS(NIBBLE(X(i) ), NIBBLE(Y(i) ))], 102 | q_reg[POS(NIBBLE(X(i) + 1), NIBBLE(Y(i) ))], 103 | q_reg[POS(NIBBLE(X(i) - 1), NIBBLE(Y(i) - 1))], 104 | q_reg[POS(NIBBLE(X(i) ), NIBBLE(Y(i) - 1))], 105 | q_reg[POS(NIBBLE(X(i) + 1), NIBBLE(Y(i) - 1))] 106 | }; 107 | 108 | cell_state cell_state_i( 109 | .bits ( cells ), 110 | .alive ( q_next[i] ) 111 | ); 112 | end 113 | endgenerate 114 | 115 | assign q = q_reg; 116 | 117 | endmodule 118 | -------------------------------------------------------------------------------- /p02_Cirucuits/c15_Building_Larger_Circuits/s06_fancytimer.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Exams/review2015_fancytimer 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | module top_module ( 10 | input clk, 11 | input reset, 12 | input data, 13 | output [3:0] count, 14 | output counting, 15 | output done, 16 | input ack 17 | ); 18 | 19 | 20 | localparam CHECK_D1 = 4'd0, 21 | CHECK_D2 = 4'd1, 22 | CHECK_D3 = 4'd2, 23 | CHECK_D4 = 4'd3, 24 | SHIFT_B0 = 4'd4, 25 | SHIFT_B1 = 4'd5, 26 | SHIFT_B2 = 4'd6, 27 | SHIFT_B3 = 4'd7, 28 | COUNT_DOWN = 4'd8, 29 | WAIT_ACK = 4'd9; 30 | 31 | reg [3:0] state; 32 | reg [3:0] next_state; 33 | 34 | always@(posedge clk) begin 35 | if(reset) 36 | state <= CHECK_D1; 37 | else 38 | state <= next_state; 39 | end 40 | 41 | always@(*) begin 42 | case(state) 43 | CHECK_D1 : next_state = data ? CHECK_D2 : CHECK_D1; 44 | CHECK_D2 : next_state = data ? CHECK_D3 : CHECK_D1; 45 | CHECK_D3 : next_state = data ? CHECK_D3 : CHECK_D4; 46 | CHECK_D4 : next_state = data ? SHIFT_B0 : CHECK_D1; 47 | SHIFT_B0 : next_state = SHIFT_B1; 48 | SHIFT_B1 : next_state = SHIFT_B2; 49 | SHIFT_B2 : next_state = SHIFT_B3; 50 | SHIFT_B3 : next_state = COUNT_DOWN; 51 | COUNT_DOWN : next_state = counter_done ? WAIT_ACK : COUNT_DOWN; 52 | WAIT_ACK : next_state = ack ? CHECK_D1 : WAIT_ACK; 53 | default : next_state = CHECK_D1; 54 | endcase 55 | end 56 | 57 | // 58 | // Shift stage 59 | // 60 | reg [3:0] delay; 61 | reg [3:0] delay_next; 62 | 63 | always@(posedge clk) begin 64 | if (reset) 65 | delay <= '0; 66 | else 67 | delay <= delay_next; 68 | end 69 | 70 | always@(*) begin 71 | case (state) 72 | SHIFT_B0 , 73 | SHIFT_B1 , 74 | SHIFT_B2 , 75 | SHIFT_B3 : delay_next = {delay[2:0], data}; 76 | default : delay_next = delay; 77 | endcase 78 | end 79 | 80 | // 81 | // Counter 82 | // 83 | wire counter_load; 84 | 85 | assign counter_load = (state == SHIFT_B3); 86 | 87 | reg [3:0] counter; 88 | 89 | always@(posedge clk) begin 90 | if(reset) 91 | counter <= '0; 92 | else if (counter_load) 93 | counter <= delay_next; 94 | else if (timer_tick) 95 | if (counter == '0) 96 | counter <= '0; 97 | else 98 | counter <= counter - 1'b1; 99 | end 100 | 101 | // 102 | // mod-1000 timer 103 | // 104 | reg [9:0] timer; 105 | wire timer_tick; 106 | wire timer_en; 107 | 108 | assign timer_en = (state == COUNT_DOWN); 109 | 110 | always@(posedge clk) begin 111 | if(reset) 112 | timer <= '0; 113 | else if (timer_en) 114 | if (timer == 10'd1000 - 1'b1) 115 | timer <= '0; 116 | else 117 | timer <= timer + 1'b1; 118 | else 119 | timer <= '0; 120 | end 121 | 122 | assign timer_tick = (timer == 10'd1000 - 1'b1); 123 | 124 | // 125 | // Output 126 | // 127 | wire counter_done; 128 | 129 | assign counter_done = (~|counter) & timer_tick; 130 | 131 | assign done = (state == WAIT_ACK); 132 | assign count = counter; 133 | assign counting = (state == COUNT_DOWN); 134 | endmodule 135 | -------------------------------------------------------------------------------- /p02_Cirucuits/c11_Counters/s08_count_clock.v: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // https://hdlbits.01xz.net/wiki/Count_clock 4 | // 5 | // 6 | 7 | `default_nettype none 8 | 9 | // 10 | // Usually one module in a file is recommended. 11 | // 12 | module mod_n_counter #( 13 | parameter N = 10 14 | ) 15 | ( 16 | input clk, 17 | input reset, 18 | input enable, 19 | output tick, 20 | output [$clog2(N) - 1:0] value 21 | ); 22 | reg [$clog2(N) - 1:0] counter; 23 | 24 | always @(posedge clk) begin 25 | if (reset) 26 | counter <= '0; 27 | else 28 | if (enable) 29 | if (counter == N - 1'b1) 30 | counter <= '0; 31 | else 32 | counter <= counter + 1'b1; 33 | // Usually the last no-change else branch could be omitted 34 | else 35 | counter <= counter; 36 | end 37 | 38 | assign value = counter; 39 | assign tick = enable && (counter == N - 1'b1); 40 | 41 | endmodule 42 | 43 | // 44 | // Usually one module in a file is recommended. 45 | // 46 | module nibble2bcd ( 47 | input [3:0] nibble, 48 | output [7:0] bcd 49 | ); 50 | 51 | assign bcd = (nibble > 9) ? ({4'b0, nibble} + 8'd6) : {4'b0, nibble}; 52 | 53 | endmodule 54 | 55 | module top_module ( 56 | input clk, 57 | input reset, 58 | input ena, 59 | output pm, 60 | output [7:0] hh, 61 | output [7:0] mm, 62 | output [7:0] ss 63 | ); 64 | 65 | wire [5:0] tick; 66 | 67 | // 68 | // For BCD numbers for second 69 | // 70 | assign tick[0] = ena; 71 | 72 | wire [3:0] ss_low; 73 | mod_n_counter #( 74 | .N ( 10 ) 75 | ) mod_n_counter_i0 ( 76 | .clk ( clk ), 77 | .reset ( reset ), 78 | .enable ( tick[0] ), 79 | .tick ( tick[1] ), 80 | .value ( ss_low ) 81 | ); 82 | 83 | wire [2:0] ss_high; 84 | mod_n_counter #( 85 | .N ( 6 ) 86 | ) mod_n_counter_i1 ( 87 | .clk ( clk ), 88 | .reset ( reset ), 89 | .enable ( tick[1] ), 90 | .tick ( tick[2] ), 91 | .value ( ss_high ) 92 | ); 93 | 94 | assign ss = {1'b0, ss_high, ss_low}; 95 | 96 | // 97 | // For BCD numbers for minute 98 | // 99 | wire [3:0] mm_low; 100 | mod_n_counter #( 101 | .N ( 10 ) 102 | ) mod_n_counter_i2 ( 103 | .clk ( clk ), 104 | .reset ( reset ), 105 | .enable ( tick[2] ), 106 | .tick ( tick[3] ), 107 | .value ( mm_low ) 108 | ); 109 | 110 | wire [2:0] mm_high; 111 | mod_n_counter #( 112 | .N ( 6 ) 113 | ) mod_n_counter_i3 ( 114 | .clk ( clk ), 115 | .reset ( reset ), 116 | .enable ( tick[3] ), 117 | .tick ( tick[4] ), 118 | .value ( mm_high ) 119 | ); 120 | 121 | assign mm = {1'b0, mm_high, mm_low}; 122 | 123 | // 124 | // For BCD numbers for hour 125 | // 126 | wire [3:0] hh_nibble; 127 | mod_n_counter #( 128 | .N ( 12 ) 129 | ) mod_n_counter_i4 ( 130 | .clk ( clk ), 131 | .reset ( reset ), 132 | .enable ( tick[4] ), 133 | .tick ( tick[5] ), 134 | .value ( hh_nibble ) 135 | ); 136 | 137 | wire [3:0] hh_fixed; 138 | assign hh_fixed = (hh_nibble == '0) ? 4'd12 : hh_nibble; 139 | 140 | wire [7:0] hh_bcd; 141 | nibble2bcd nibble2bcd_i0 ( 142 | .nibble ( hh_fixed ), 143 | .bcd ( hh_bcd ) 144 | ); 145 | 146 | assign hh = hh_bcd; 147 | 148 | // 149 | // For AM/PM 150 | // 151 | reg pm_reg; 152 | always @(posedge clk ) begin 153 | if (reset) 154 | pm_reg <= 1'b0; 155 | else 156 | if (tick[5]) 157 | pm_reg <= ~pm_reg; 158 | // Usually the last no-change else branch could be omitted 159 | else 160 | pm_reg <= pm_reg; 161 | end 162 | 163 | assign pm = pm_reg; 164 | 165 | endmodule --------------------------------------------------------------------------------