├── Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df ├── About Xilinx Vitis & Vivado 9c717476fe74459a972744223cbfbfe2.md ├── Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621.md ├── Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621 │ ├── Untitled 1.png │ ├── Untitled 2.png │ ├── Untitled 3.png │ └── Untitled.png ├── Hello World FPGA Programming 134381bda24048adaea5400037bf2b0d.md ├── Hello World FPGA Programming 134381bda24048adaea5400037bf2b0d │ ├── Untitled 1.png │ ├── Untitled 2.png │ ├── Untitled 3.png │ ├── Untitled 4.png │ ├── Untitled 5.png │ └── Untitled.png ├── Hello World Vitis Application Project 8ba381eb01434224a2484ee99320ffab.md ├── Hello World Vitis Application Project 8ba381eb01434224a2484ee99320ffab │ ├── Untitled 1.png │ ├── Untitled 2.png │ ├── Untitled 3.png │ ├── Untitled 4.png │ ├── Untitled 5.png │ └── Untitled.png ├── Hello World Vitis Platform Project 6e821637549a4c8594de431972e4c5aa.md ├── Hello World Vitis Platform Project 6e821637549a4c8594de431972e4c5aa │ ├── Untitled 1.png │ ├── Untitled 2.png │ ├── Untitled 3.png │ ├── Untitled 4.png │ ├── Untitled 5.png │ ├── Untitled 6.png │ └── Untitled.png ├── Hello World Vivado c20603a3721a4c98b040b835a77d0eda.md ├── Hello World Vivado c20603a3721a4c98b040b835a77d0eda │ ├── Untitled 1.png │ └── Untitled.png ├── Untitled 1.png ├── Untitled.png ├── Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b.md └── Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b │ ├── Untitled 1.png │ ├── Untitled 2.png │ └── Untitled.png ├── Lab05 Hello World with Vitis and Vivado.md ├── Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae ├── DoGain Run and Result 1c25629f71614592aa3a9e6c01e608e2.md ├── DoGain Run and Result 1c25629f71614592aa3a9e6c01e608e2 │ └── Untitled.png ├── DoGain Vitis 730de75150cc4347a751df26522589f8.md ├── DoGain Vitis 730de75150cc4347a751df26522589f8 │ ├── Untitled 1.png │ └── Untitled.png ├── DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b.md ├── DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b │ ├── Untitled 1.png │ └── Untitled.png ├── DoGain Vivado 1d3d4c6d96114c08854ec7c709328057.md ├── Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628.md └── Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628 │ ├── Untitled 1.png │ └── Untitled.png ├── Lab06 Working with HLS.md ├── Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72 ├── HLS Coding 9304323a42f44b2a98e1a2ce09e4db40.md ├── HLS Coding 9304323a42f44b2a98e1a2ce09e4db40 │ ├── Untitled 1.png │ ├── Untitled.png │ └── solution1-syn-report.zip ├── IMPORTANT Changes to the Lab Materials a28c99d190d6425482cf195a967e08b6.md ├── IMPORTANT Changes to the Lab Materials a28c99d190d6425482cf195a967e08b6 │ ├── Lab08srcs.zip │ ├── Lab_08_Preset.tcl │ ├── Makefile.zip │ ├── lib_xmmult_hw.c │ ├── lib_xmmult_hw.h │ ├── main.c │ ├── mmult.h │ ├── mmult_accel.cpp │ └── mmult_test.cpp ├── Lab08 Reference (May Important) 2bc8d6f00fd541448751c08daad2c929.md ├── Matrix Multiplication 270d36ef3b7e4c0e839f0bd5c8628e64.md ├── Matrix Multiplication 270d36ef3b7e4c0e839f0bd5c8628e64 │ ├── Matrix Multiplication C C++ Implementation 13a5cf77b60241638179bf7f82114c6b.md │ └── Matrix Multiplication C C++ Implementation 13a5cf77b60241638179bf7f82114c6b │ │ └── Untitled.png ├── Test Run Running and Result 1ee1dab735f541278da9724059617203.md ├── Test Run Running and Result 1ee1dab735f541278da9724059617203 │ └── Untitled.png ├── Test Run Vitis Project 79e9f1d9a50c48739d2832392b327f9d.md └── Vivado Block Design fdbd44813e8949518cd0702ed1495737.md ├── Lab08 Matrix Multiplier Design.md ├── Lab08 srcs ├── Vitis │ ├── Makefile │ ├── Makefile.zip │ ├── lib_xmmult_hw.c │ ├── lib_xmmult_hw.h │ └── main.c ├── Vitis_HLS │ ├── mmult.h │ ├── mmult_accel.cpp │ └── mmult_test.cpp └── Vivado │ └── Lab_08_Preset.tcl ├── Makefile ├── README.md ├── Troubleshootings f43673650b7c4eb5b83fa2b7a80452e2 ├── Makefile Problem b266174a19ec426eba6e8e8b3119c7d0.md ├── Makefile Problem b266174a19ec426eba6e8e8b3119c7d0 │ ├── Makefile.zip │ ├── Untitled 1.png │ ├── Untitled 2.png │ ├── Untitled 3.png │ ├── Untitled 4.png │ └── Untitled.png ├── Troubleshooting Bad file descriptor in nativeDrain 14395223566f4413ad25f0e44b7288e4.md ├── Troubleshooting Bad file descriptor in nativeDrain 14395223566f4413ad25f0e44b7288e4 │ ├── Untitled 1.png │ └── Untitled.png ├── Troubleshooting Cypress driver error problem (Viti 9c61286cfd0e4f0bbe4892d0abcdbb78.md ├── Troubleshooting In Device Manager, can't find the 6de02b931fe342b1b5319725c4dc9c8e.md ├── Troubleshooting Terminal shows nothing c63dca91cb0e48d7b072dd1c72faf51e.md └── Troubleshooting Terminal shows nothing c63dca91cb0e48d7b072dd1c72faf51e │ ├── Untitled 1.png │ ├── Untitled 2.png │ └── Untitled.png └── Troubleshootings.md /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/About Xilinx Vitis & Vivado 9c717476fe74459a972744223cbfbfe2.md: -------------------------------------------------------------------------------- 1 | # About Xilinx Vitis & Vivado 2 | 3 | ### Vitis 4 | 5 | - unified software development tool 6 | - which software works on programmable device 7 | - mainly for embedded and acceleration 8 | 9 | ### Vivado 10 | 11 | - integrated design environment (IDE) 12 | - including system-to-IC level tools 13 | - for synthesis and analysis of HDL designs 14 | 15 | ### Notable Reference for Who Aren't familiar with Xilinx Tools 16 | 17 | - 'Xilinx', "Xilinx Announces Vitis - a Unified Software Platform Unlocking a New Design Experience for All Developers", [https://www.xilinx.com/news/press/2019/xilinx-announces-vitis--a-unified-software-platform-unlocking-a-new-design-experience-for-all-developers.html](https://www.xilinx.com/news/press/2019/xilinx-announces-vitis--a-unified-software-platform-unlocking-a-new-design-experience-for-all-developers.html) 18 | - 'Xilinx', "Introducing Vitis", [https://www.xilinx.com/products/design-tools/vitis.html](https://www.xilinx.com/products/design-tools/vitis.html) 19 | - 'Xilinx', "2019.2 install - What is the difference between Vitis and Vivado?", [https://www.xilinx.com/support/answers/73053.html](https://www.xilinx.com/support/answers/73053.html) 20 | - 'Xilinx', "Bringing Ultra High Productivity to Mainstream Systems & Platform Designers", [https://www.xilinx.com/support/documentation/backgrounders/vivado-hlx.pdf](https://www.xilinx.com/support/documentation/backgrounders/vivado-hlx.pdf) 21 | Pdf file. 22 | - 'Wikipedia', "Xilinx Vivado", [https://en.wikipedia.org/wiki/Xilinx_Vivado](https://en.wikipedia.org/wiki/Xilinx_Vivado) 23 | - 'KIPost', "자일링스, 하드웨어-소프트웨어 개발 간 장벽 없앴다… '바이티스(Vitis)' 공개", [https://www.kipost.net/news/articleView.html?idxno=201918](https://www.kipost.net/news/articleView.html?idxno=201918) -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621.md: -------------------------------------------------------------------------------- 1 | # Alternative: Direct Creation of Vitis Application Project from Vivado Hardware 2 | 3 | We can directly create an application project from the hardware (.xsa) file. 4 | 5 | First, try to create a new application project. 6 | 7 | At the below window, choose not **Select a platform**, but **Create a new platform**. 8 | 9 | ![Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled.png](Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled.png) 10 | 11 | 1. Chose **Create a new platform from hardware (XSA)**. 12 | 2. Click **Browse** button and find your ***{$DESIGN_NAME}_wrapper.xsa*** file exported. 13 | 3. Set on the Generate boot components option. 14 | 4. Set platform name to ***{$PROJECT_NAME}_platform***. 15 | 5. Click Next. 16 | 17 | ![Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled%201.png](Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled%201.png) 18 | 19 | - Set project name to ***{$PROJECT_NAME}*** 20 | (Use the project name directly) 21 | 22 | ![Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled%202.png](Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled%202.png) 23 | 24 | - Next. 25 | 26 | ![Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled%203.png](Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621/Untitled%203.png) 27 | 28 | - Choose Hello World. 29 | - Finish. 30 | 31 | Now done. 32 | 33 | ## Makefile Problem 34 | 35 | If you are doing **Lab06 or later**, see also: 36 | 37 | [Makefile Problem](https://github.com/hajin-kim/FPGA_Tutorial_with_HLS/blob/main/Troubleshootings%20f43673650b7c4eb5b83fa2b7a80452e2/Makefile%20Problem%20b266174a19ec426eba6e8e8b3119c7d0.md) 38 | -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled 1.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled 2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled 2.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled 3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled 3.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Alternative Direct Creation of Vitis Application P c3733968f81641d19b17885f5466a621/Untitled.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World FPGA Programming 134381bda24048adaea5400037bf2b0d.md: -------------------------------------------------------------------------------- 1 | # Hello World: FPGA Programming 2 | 3 | ## Connecting Board with Computer 4 | 5 | Resume to the ppt **page 42**. Do **page 42~45**. The SDK Terminal was replaced by **Window-Show View-Terminal-Terminal**. 6 | 7 | ### Troubleshooting: In Device Manager, can't find the Cypress USB port 8 | 9 | [Troubleshooting: In Device Manager, can't find the Cypress USB port](https://github.com/hajin-kim/FPGA_Tutorial_with_HLS/blob/main/Troubleshootings%20f43673650b7c4eb5b83fa2b7a80452e2/Troubleshooting%20In%20Device%20Manager%2C%20can't%20find%20the%20%206de02b931fe342b1b5319725c4dc9c8e.md) 10 | 11 | ## Programming the Board 12 | 13 | ### Build the system project (result of the application project creation) 14 | 15 | Select the system project and build. 16 | 17 | ![Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled.png](Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled.png) 18 | 19 | ### Run 20 | 21 | ![Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%201.png](Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%201.png) 22 | 23 | ![Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%202.png](Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%202.png) 24 | 25 | ![Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%203.png](Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%203.png) 26 | 27 | ![Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%204.png](Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%204.png) 28 | 29 | ## Result 30 | 31 | ![Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%205.png](Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d/Untitled%205.png) 32 | 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![Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled.png](Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled.png) 6 | 7 | ![Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled%201.png](Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled%201.png) 8 | 9 | ![Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled%202.png](Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled%202.png) 10 | 11 | - Recommended name: ***{$PROJECT_NAME}*** 12 | (Use the same as project name) 13 | 14 | ![Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled%203.png](Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab/Untitled%203.png) 15 | 16 | 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Project 8ba381eb01434224a2484ee99320ffab/Untitled.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World Vitis Platform Project 6e821637549a4c8594de431972e4c5aa.md: -------------------------------------------------------------------------------- 1 | # Hello World: Vitis Platform Project 2 | 3 | ## Vitis 4 | 5 | ### Running Vitis 6 | 7 | When you do **Launch SDK** at the ppt **page 32**, please note that this is replaced by Vitis. 8 | It is at **Toos-Launch Vitis IDE**. 9 | 10 | - Ref: [https://forums.xilinx.com/t5/Embedded-Development-Tools/launch-sdk-missing-in-vivado/td-p/1124186](https://forums.xilinx.com/t5/Embedded-Development-Tools/launch-sdk-missing-in-vivado/td-p/1124186) 11 | 12 | Or, you can run Vitis manually by double-clicking the desktop icon or the Vitis execution file. 13 | 14 | ## Creating a Vitis Platform Project 15 | 16 | Now you are seeing a Vitis window. 17 | 18 | Browse **File-New-Platform Project** (shortcut **Alt Shift N and then P**). Then you can create a new platform project. 19 | 20 | If the below window is shown, then enter the project name. 21 | 22 | - Recommended name: ***{$PROJECT_NAME}_platform*** 23 | 24 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled.png) 25 | 26 | And then, click next. Then the below window will be shown. 27 | 28 | Click the **Browse** button. And find your ***{$DESIGN_NAME}_wrapper.xsa*** file exported. This file will be located in your project folder if you followed the ppt file. 29 | 30 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%201.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%201.png) 31 | 32 | After adding your file, keep the below option. 33 | 34 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%202.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%202.png) 35 | 36 | And click **finish** button. 37 | 38 | After a while, the new platform project is created. 39 | 40 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%203.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%203.png) 41 | 42 | ### Browsing project components 43 | 44 | See the left **Explorer** view 45 | 46 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%204.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%204.png) 47 | 48 | Expand the top-level ***{$PROJECT_NAME}_platform***. May be expanded as default. 49 | 50 | - Expand **(top)/export/*{$PROJECT_NAME}_platform*/hw** 51 | You can find the exported Hardware Specification file (.xsa file), and the top-level platform XML file (.xpfm file). 52 | - Open **(top)/platform.spr** to see the platform view and **build**. 53 | 54 | ### Build 55 | 56 | Open **platform.spr** file and click the hammer button. 57 | 58 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%205.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%205.png) 59 | 60 | ![Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%206.png](Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa/Untitled%206.png) -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World Vitis Platform Project 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The process is almost the same. Using **part xc7z020clg484-1**. Nothing special. 8 | 9 | ![Hello%20World%20Vivado%20c20603a3721a4c98b040b835a77d0eda/Untitled.png](Hello%20World%20Vivado%20c20603a3721a4c98b040b835a77d0eda/Untitled.png) 10 | 11 | ![Hello%20World%20Vivado%20c20603a3721a4c98b040b835a77d0eda/Untitled%201.png](Hello%20World%20Vivado%20c20603a3721a4c98b040b835a77d0eda/Untitled%201.png) 12 | 13 | When you do Generate Bitstream at the ppt **page 25~28**, the process bar popup will suddenly disappear. But the process is still running in the background. So just wait for a while, until the complete popup is shown. 14 | You can see the process at the **Design Runs** tab at the bottom window. 15 | 16 | If you reached at **page 32**, then testing Vivado may be done. Now, it is the time for Vitis. -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World Vivado c20603a3721a4c98b040b835a77d0eda/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World Vivado c20603a3721a4c98b040b835a77d0eda/Untitled 1.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World Vivado c20603a3721a4c98b040b835a77d0eda/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Hello World Vivado c20603a3721a4c98b040b835a77d0eda/Untitled.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Untitled 1.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Untitled.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b.md: -------------------------------------------------------------------------------- 1 | # Xilinx 2020-2 Installation 2 | 3 | Xilinx integrated installation of Vitis and Vivado 4 | 5 | ## Downloading Package File 6 | 7 | ### Package download link 8 | 9 | - [https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html) 10 | - [https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.2_1118_1232_Win64.exe](https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.2_1118_1232_Win64.exe) 11 | 12 | ### Contacts 13 | 14 | When you try to download the package, 15 | 16 | ![Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b/Untitled.png](Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b/Untitled.png) 17 | 18 | ## Installation 19 | 20 | ### Note of Unified Installation 21 | 22 | If you download the installer, it would be the UNIFIED installer for Xilinx tools. 23 | Vitis includes Vivado. Therefore, *if you install Vitis, Vivado will be automatically installed together*. 24 | 25 | **Note**: Vitis installation requires more storage. (130GB) 26 | 27 | ![Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b/Untitled%201.png](Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b/Untitled%201.png) 28 | 29 | This is only one difference between the ppt. (**page 9**) 30 | 31 | ### Note of Post-Installation 32 | 33 | There is no **license management process** shown at the ppt **page 15~24**. (Be not automatically shown up) 34 | 35 | ### Other notes 36 | 37 | 1. Version: Xilinx Unified 2020.2 (latest) 38 | 2. Environment: Windows 10 Education (latest) 39 | 3. 설치 꽤 오래걸려요 7~8시간 40 | 4. Processing 중에 다른 component 설치 확인 창이 뜰 수 있습니다. (약 7시간 차) 41 | 42 | ## Validation 43 | 44 | The result of running Vivado and Vitis HLS is: 45 | 46 | ![Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b/Untitled%202.png](Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b/Untitled%202.png) -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b/Untitled 1.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b/Untitled 2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b/Untitled 2.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab05 Hello World with Vitis and Vivado d3897032db324f5d9531e5ab0a9af6df/Xilinx 2020-2 Installation fb8017b485024f3b8d5cca20f7daba8b/Untitled.png -------------------------------------------------------------------------------- /Lab05 Hello World with Vitis and Vivado.md: -------------------------------------------------------------------------------- 1 | # Lab05: Hello World with Vitis and Vivado 2 | 3 | ### Reference 4 | 5 | - ***[ESD19-2] 05. Hello World with Vivado.pptx*** 6 | - The ppt file is really helpful. Please follow this as major. 7 | - Official document ***UG1165 Zynq-7000 SoC: Embedded Design Tutorial***, (v2020.1) June 10, 2020. 8 | - You may refer to v2020.2. It would be better. 9 | 10 | ### Notes 11 | 12 | - Using Zedboard 13 | - xc7z020clg484-1 14 | - Handle with care (50만원) 15 | - Requires 2 USB A plug-USB 2.0 micro B plug cables. 16 | - Requries an adapter. 17 | 18 | ![Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Untitled.png](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Untitled.png) 19 | 20 | ![Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Untitled%201.png](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Untitled%201.png) 21 | 22 | --- 23 | 24 | [About Xilinx Vitis & Vivado](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/About%20Xilinx%20Vitis%20&%20Vivado%209c717476fe74459a972744223cbfbfe2.md) 25 | 26 | [Xilinx 2020-2 Installation](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Xilinx%202020-2%20Installation%20fb8017b485024f3b8d5cca20f7daba8b.md) 27 | 28 | [Hello World: Vivado ](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Hello%20World%20Vivado%20c20603a3721a4c98b040b835a77d0eda.md) 29 | 30 | [Hello World: Vitis Platform Project](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Hello%20World%20Vitis%20Platform%20Project%206e821637549a4c8594de431972e4c5aa.md) 31 | 32 | [Hello World: Vitis Application Project](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Hello%20World%20Vitis%20Application%20Project%208ba381eb01434224a2484ee99320ffab.md) 33 | 34 | [Hello World: FPGA Programming](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Hello%20World%20FPGA%20Programming%20134381bda24048adaea5400037bf2b0d.md) 35 | 36 | [Alternative: Direct Creation of Vitis Application Project from Vivado Hardware](Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621.md) 37 | 38 | --- -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Run and Result 1c25629f71614592aa3a9e6c01e608e2.md: -------------------------------------------------------------------------------- 1 | # DoGain: Run and Result 2 | 3 | ## Build and run 4 | 5 | ### Troubleshooting: "Bad file descriptor in nativeDrain" 6 | 7 | [Troubleshooting: "Bad file descriptor in nativeDrain"](https://github.com/hajin-kim/FPGA_Tutorial_with_HLS/blob/main/Troubleshootings%20f43673650b7c4eb5b83fa2b7a80452e2/Troubleshooting%20Bad%20file%20descriptor%20in%20nativeDrain%2014395223566f4413ad25f0e44b7288e4.md) 8 | 9 | ## Result 10 | 11 | ![DoGain%20Run%20and%20Result%201c25629f71614592aa3a9e6c01e608e2/Untitled.png](DoGain%20Run%20and%20Result%201c25629f71614592aa3a9e6c01e608e2/Untitled.png) 12 | 13 | It works correctly. 14 | -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Run and Result 1c25629f71614592aa3a9e6c01e608e2/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Run and Result 1c25629f71614592aa3a9e6c01e608e2/Untitled.png -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis 730de75150cc4347a751df26522589f8.md: -------------------------------------------------------------------------------- 1 | # DoGain: Vitis 2 | 3 | ## Connecting the board 4 | 5 | ### Turning on the board 6 | 7 | Make sure that the board is power-on and connected. 8 | 9 | ### Troubleshooting: Cypress "driver error" problem (Vitis can't find the port) 10 | 11 | [Troubleshooting: Cypress "driver error" problem (Vitis can't find the port)](https://github.com/hajin-kim/FPGA_Tutorial_with_HLS/blob/main/Troubleshootings%20f43673650b7c4eb5b83fa2b7a80452e2/Troubleshooting%20Cypress%20driver%20error%20problem%20\(Viti%209c61286cfd0e4f0bbe4892d0abcdbb78.md) 12 | 13 | ## Creating Vitis application project 14 | 15 | Ppt **page 49~50**. The Launch SDK is replaced by Tool-Launch Vitis, and there are additional changes. You have to do: 16 | 17 | 1. Launch Vitis. 18 | 2. Create an Platform and Application Project. 19 | 20 | We can directly create an application project from the hardware (.xsa) file. See: 21 | [Alternative: Direct Creation of Vitis Application Project from Vivado Hardware](https://github.com/hajin-kim/FPGA_Tutorial_with_HLS/blob/main/Lab05%20Hello%20World%20with%20Vitis%20and%20Vivado%20d3897032db324f5d9531e5ab0a9af6df/Alternative%20Direct%20Creation%20of%20Vitis%20Application%20P%20c3733968f81641d19b17885f5466a621.md) 22 | 23 | There may be problems related to Makefile. Please refer to [Makefile Problem](https://github.com/hajin-kim/FPGA_Tutorial_with_HLS/blob/main/Troubleshootings%20f43673650b7c4eb5b83fa2b7a80452e2/Makefile%20Problem%20b266174a19ec426eba6e8e8b3119c7d0.md) 24 | 25 | ### Setting the source file 26 | 27 | Ppt **page 51**. Open ***{$WORKSPACE_DIR}\{$PROJECT_NAME}\src***. 28 | 29 | ![DoGain%20Vitis%20730de75150cc4347a751df26522589f8/Untitled.png](DoGain%20Vitis%20730de75150cc4347a751df26522589f8/Untitled.png) 30 | 31 | 1. Add the given ***main.c*** to the ***src*** folder. 32 | 2. Remove ***helloworld.c*** file. 33 | 34 | ### Setting the run configuration 35 | 36 | Ppt **page 52**. 37 | 38 | 1. Right click on your system project. 39 | 2. Run As-Run Configurations. The below window will pop up. 40 | 3. Create a new configuration by double clicking **System Project Debug**. 41 | 4. Select it. 42 | 5. Nothing more to do. Run. 43 | 44 | ![DoGain%20Vitis%20730de75150cc4347a751df26522589f8/Untitled%201.png](DoGain%20Vitis%20730de75150cc4347a751df26522589f8/Untitled%201.png) 45 | -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis 730de75150cc4347a751df26522589f8/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis 730de75150cc4347a751df26522589f8/Untitled 1.png -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis 730de75150cc4347a751df26522589f8/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis 730de75150cc4347a751df26522589f8/Untitled.png -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b.md: -------------------------------------------------------------------------------- 1 | # DoGain: Vitis HLS 2 | 3 | Covers ppt page 4~20. 4 | 5 | ### Creating Vitis HLS project 6 | 7 | Follow ppt. 8 | 9 | Ppt **page 8~10**. **xc7z020clg484-1**. I chose **Vivado IP Flow Target** for the Flow Target option. 10 | 11 | ![DoGain%20Vitis%20HLS%20357afad1bccd433e8d9f66c7e9826b6b/Untitled.png](DoGain%20Vitis%20HLS%20357afad1bccd433e8d9f66c7e9826b6b/Untitled.png) 12 | 13 | Ppt **Page 12**. At the below directory, go into the project folder. And then create **core.cpp** 14 | 15 | ![DoGain%20Vitis%20HLS%20357afad1bccd433e8d9f66c7e9826b6b/Untitled%201.png](DoGain%20Vitis%20HLS%20357afad1bccd433e8d9f66c7e9826b6b/Untitled%201.png) 16 | 17 | Ppt **page 20**. The Export RTL button is at **Solution-Export RTL**. The Format Selection-IP Catalog is replaced by **Vivado IP (zip)**. -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b/Untitled 1.png -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vitis HLS 357afad1bccd433e8d9f66c7e9826b6b/Untitled.png -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/DoGain Vivado 1d3d4c6d96114c08854ec7c709328057.md: -------------------------------------------------------------------------------- 1 | # DoGain: Vivado 2 | 3 | Covers ppt page 21~49. 4 | 5 | ## ZYNQ Configuration 6 | 7 | Ppt **page 23**. Do **lab05 ppt page 10~14**. 8 | 9 | Ppt **page 27**. Load the given ***Lab06_Preset.tcl*** file to the **Recent Directories**. Or, choose the directory by **Look in**. 10 | 11 | ## Connecting a Custom IP to ZYNQ 12 | 13 | Ppt **page 32**. Note that the project is Vitis HLS project, NOT Vivado project what you have been dealing with by now. 14 | 15 | Ppt **page 34**. You can add **doGain** IP by hitting the **+** button and then finding **Dogain**. Next, click the green-highlighted **run connection automation** button. 16 | 17 | Ppt **page 40**. Typo: S_AXIS_MM2s → M_AXIS_MM2S 18 | 19 | Ppt **page 43**. Your design may differ from the ppt. Sometimes, auto-connection makes 2 AXI Interconnects, instead of one of these and 1 AXI SmartConnect. 20 | 21 | Ppt **page 44**. 22 | 23 | - In0 → mm2s_introut @ axi_dma_0 24 | - In1 → s2mm_introut @ axi_dma_0 25 | - In2 → interrupt @ doGain_0 26 | 27 | Ppt **page 45**. Do **lab05 ppt page 22~31**. 28 | 29 | ## Export and Launch SDK -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628.md: -------------------------------------------------------------------------------- 1 | # Workflow from HLS to FPGA Programming 2 | 3 | ![Workflow%20from%20HLS%20to%20FPGA%20Programming%20670bfaa114c64b479cc325d3c1922628/Untitled.png](Workflow%20from%20HLS%20to%20FPGA%20Programming%20670bfaa114c64b479cc325d3c1922628/Untitled.png) 4 | 5 | ![Workflow%20from%20HLS%20to%20FPGA%20Programming%20670bfaa114c64b479cc325d3c1922628/Untitled%201.png](Workflow%20from%20HLS%20to%20FPGA%20Programming%20670bfaa114c64b479cc325d3c1922628/Untitled%201.png) 6 | 7 | ## Terminologies 8 | 9 | ### What is IP? 10 | 11 | Pre-configured logic functions that can be used in your design. 12 | 13 | - [https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_intellectual_property_cores.htm](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_intellectual_property_cores.htm) 14 | - [https://whatis.techtarget.com/definition/IP-core-intellectual-property-core](https://whatis.techtarget.com/definition/IP-core-intellectual-property-core) 15 | 16 | ### HLS and RTL 17 | 18 | - HLS: High-Level Synthesis 19 | - high level language(C, C++) 20 | - describes IP and its action 21 | - RTL: register-transfer level 22 | - includes HDL(VHDL or Verilog) and others 23 | 24 | --- 25 | 26 | # Workflow 27 | 28 | 1. Vitis HLS 29 | 2. Vivado 30 | 3. Vitis IDE platform 31 | 4. Vitis IDE system and application 32 | 5. program FPAG and test 33 | 34 | ## 1. Vitis HLS 35 | 36 | Agenda: generate RTL of our own IP by doing HLS 37 | 38 | ## 2. Vivado 39 | 40 | Agenda: generate hardware by placing IPs and connecting them 41 | 42 | - generate XSA 43 | 44 | ### Workflow 45 | 46 | 1. Load our IP 47 | - Synthesized by HLS, or coded in RTL 48 | 2. Implement our design 49 | - Place IPs and connect them 50 | - Use Validate Design to verify the design 51 | 3. Create a design wrapper 52 | 4. Synthesis and generate bitstream 53 | 5. Export hardware as .xsa file 54 | 55 | ## 3. Vitis IDE Platform Project 56 | 57 | Agenda: compile Vivado hardware written in C language, in order to program our device 58 | 59 | ## 4. Vitis IDE Application Project 60 | 61 | Agenda: final step for programming our device -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628/Untitled 1.png -------------------------------------------------------------------------------- /Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab06 Working with HLS 9b2ebc09d3614613aae2553700d082ae/Workflow from HLS to FPGA Programming 670bfaa114c64b479cc325d3c1922628/Untitled.png -------------------------------------------------------------------------------- /Lab06 Working with HLS.md: -------------------------------------------------------------------------------- 1 | # Lab06: Working with HLS 2 | 3 | ### Reference 4 | 5 | - ***[ESD19-2] 06. Working with HLS.pptx*** 6 | - The ppt file is really helpful. Please follow this as major. 7 | 8 | ### Notes 9 | 10 | - eTL may mean "given lecture materials". This sometimes occurs in the given ppt material. 11 | 12 | --- 13 | 14 | [Workflow from HLS to FPGA Programming](Lab06%20Working%20with%20HLS%209b2ebc09d3614613aae2553700d082ae/Workflow%20from%20HLS%20to%20FPGA%20Programming%20670bfaa114c64b479cc325d3c1922628.md) 15 | 16 | [DoGain: Vitis HLS](Lab06%20Working%20with%20HLS%209b2ebc09d3614613aae2553700d082ae/DoGain%20Vitis%20HLS%20357afad1bccd433e8d9f66c7e9826b6b.md) 17 | 18 | [DoGain: Vivado](Lab06%20Working%20with%20HLS%209b2ebc09d3614613aae2553700d082ae/DoGain%20Vivado%201d3d4c6d96114c08854ec7c709328057.md) 19 | 20 | [DoGain: Vitis](Lab06%20Working%20with%20HLS%209b2ebc09d3614613aae2553700d082ae/DoGain%20Vitis%20730de75150cc4347a751df26522589f8.md) 21 | 22 | [DoGain: Run and Result](Lab06%20Working%20with%20HLS%209b2ebc09d3614613aae2553700d082ae/DoGain%20Run%20and%20Result%201c25629f71614592aa3a9e6c01e608e2.md) 23 | 24 | --- -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40.md: -------------------------------------------------------------------------------- 1 | # HLS Coding 2 | 3 | Ppt **page 3**. Typo: Lab07 → Lab08. 4 | There are some changes to the source codes. Please refer to [IMPORTANT Changes to the Lab Materials](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6.md) 5 | 6 | Ppt **page 4**. We also have to choose our part **xc7z020clg484-1**. 7 | 8 | Ppt **page 7**. Refer to [IMPORTANT Changes to the Lab Materials](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6.md) 9 | 10 | ## Synthesis 11 | 12 | Ppt **page 8**. 13 | 14 | The synthesis result is: 15 | 16 | ![HLS%20Coding%209304323a42f44b2a98e1a2ce09e4db40/Untitled.png](HLS%20Coding%209304323a42f44b2a98e1a2ce09e4db40/Untitled.png) 17 | 18 | [solution1-syn-report.zip](HLS%20Coding%209304323a42f44b2a98e1a2ce09e4db40/solution1-syn-report.zip) 19 | 20 | ## C/RTL co-simulation 21 | 22 | Ppt **page 9~10**. If you have not edited the source codes, the COSIM may fail, while the CSIM works well. Please refer to [IMPORTANT Changes to the Lab Materials](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6.md) 23 | 24 | The COSIM result is: 25 | 26 | ![HLS%20Coding%209304323a42f44b2a98e1a2ce09e4db40/Untitled%201.png](HLS%20Coding%209304323a42f44b2a98e1a2ce09e4db40/Untitled%201.png) 27 | 28 | We can see the Pass state. The simulation is successful. -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40/Untitled 1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40/Untitled 1.png -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40/Untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40/Untitled.png -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40/solution1-syn-report.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/HLS Coding 9304323a42f44b2a98e1a2ce09e4db40/solution1-syn-report.zip -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/IMPORTANT Changes to the Lab Materials a28c99d190d6425482cf195a967e08b6.md: -------------------------------------------------------------------------------- 1 | # IMPORTANT Changes to the Lab Materials 2 | 3 | ## Integrated zip file 4 | 5 | [Lab08srcs.zip](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/Lab08srcs.zip) 6 | 7 | ## Common notes 8 | 9 | All files contain answers to Lab08. Original files have some FIXME parts, but since we have to make some changes, I attached with including all of the answers. 10 | It may good to implement the FIXMEs on your own first, and then refer to the below files. 11 | 12 | ## Vitis HLS 13 | 14 | [mmult.h](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/mmult.h) 15 | 16 | - Changed **ap_axiu** array to **hls::stream**&. 17 | - Implemented FIXME part at **matrix_multiply_ref**. 18 | - Implemented FIXME part at **mmult_hw**. 19 | - Added pipelining and array partition to **mmult_hw**. 20 | - Added **volatile** keywords to **pop_stream**. 21 | - Fixed **wrapped_mmult_hw** so that we can properly handle the **hls::stream**. 22 | - Fixed **test_matrix_mult** so that we can properly handle the **hls::stream**. (NOT TESTED) 23 | 24 | [mmult_accel.cpp](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/mmult_accel.cpp) 25 | 26 | - Changed the order of **INPUT_STREAM** and **OUTPUT_STREAM** pragmas. 27 | - Changed **ap_axiu** array to **hls::stream**&. 28 | 29 | [mmult_test.cpp](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/mmult_test.cpp) 30 | 31 | - Added the **HLS_accel** call to **main**. 32 | - Fixed **main** so that we can properly handle the **hls::stream**. 33 | - Added some global **const** variables. 34 | 35 | ## Vivado 36 | 37 | [Lab_08_Preset.tcl](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/Lab_08_Preset.tcl) 38 | 39 | - No changes. Just for convenience. 40 | 41 | ## Vitis 42 | 43 | [lib_xmmult_hw.c](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/lib_xmmult_hw.c) 44 | 45 | - Implemented **hidden FIXME**. 46 | 47 | [lib_xmmult_hw.h](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/lib_xmmult_hw.h) 48 | 49 | - No changes. Just for convenience. 50 | 51 | [main.c](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/main.c) 52 | 53 | - Implemented FIXME. 54 | 55 | [Makefile.zip](IMPORTANT%20Changes%20to%20the%20Lab%20Materials%20a28c99d190d6425482cf195a967e08b6/Makefile.zip) 56 | 57 | - Example Makefile. Unzip it. 58 | - Fixed problems related to Vitis HLS Makefile. 59 | 60 | --- -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/IMPORTANT Changes to the Lab Materials a28c99d190d6425482cf195a967e08b6/Lab08srcs.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hajin-kim/FPGA_Tutorial_with_HLS/eb8a651a545c0584d90ebab2a0145f7e346dbf4d/Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/IMPORTANT Changes to the Lab Materials a28c99d190d6425482cf195a967e08b6/Lab08srcs.zip -------------------------------------------------------------------------------- /Lab08 Matrix Multiplier Design bff4b30c2e0441339caf0ed55f0aed72/IMPORTANT Changes to the Lab Materials a28c99d190d6425482cf195a967e08b6/Lab_08_Preset.tcl: -------------------------------------------------------------------------------- 1 | proc getPresetInfo {} { 2 | return [dict create name {lab6 preset} description {lab6 preset} vlnv xilinx.com:ip:processing_system7:5.5 display_name {lab6 preset} ] 3 | } 4 | 5 | proc validate_preset {IPINST} { return true } 6 | 7 | 8 | proc apply_preset {IPINST} { 9 | return [dict create \ 10 | CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ 11 | CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ 12 | CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ 13 | CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ 14 | CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ 15 | CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ 16 | CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ 17 | CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ 18 | CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ 19 | CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ 20 | CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ 21 | CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ 22 | CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ 23 | CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ 24 | CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ 25 | CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ 26 | CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ 27 | CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ 28 | CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ 29 | CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ 30 | CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ 31 | CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ 32 | CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ 33 | CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ 34 | CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ 35 | CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ 36 | CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ 37 | CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ 38 | CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ 39 | CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ 40 | CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ 41 | CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ 42 | CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ 43 | CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ 44 | CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ 45 | CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ 46 | CONFIG.PCW_FCLK_CLK0_BUF {true} \ 47 | CONFIG.PCW_FCLK_CLK1_BUF {false} \ 48 | CONFIG.PCW_FCLK_CLK2_BUF {false} \ 49 | CONFIG.PCW_FCLK_CLK3_BUF {false} \ 50 | CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333313} \ 51 | CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ 52 | CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \ 53 | CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ 54 | CONFIG.PCW_UIPARAM_DDR_CL {7} \ 55 | CONFIG.PCW_UIPARAM_DDR_CWL {6} \ 56 | CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ 57 | CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ 58 | CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \ 59 | CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \ 60 | CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} \ 61 | CONFIG.PCW_UIPARAM_DDR_AL {0} \ 62 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \ 63 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} \ 64 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 65 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} \ 66 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.41} \ 67 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} \ 68 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \ 69 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} \ 70 | CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \ 71 | CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \ 72 | CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ 73 | CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ 74 | CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \ 75 | CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \ 76 | CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ 77 | CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ 78 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \ 79 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \ 80 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ 81 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ 82 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {68.4725} \ 83 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {71.086} \ 84 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {66.794} \ 85 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {108.7385} \ 86 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {64.1705} \ 87 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.686} \ 88 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {68.46} \ 89 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {105.4895} \ 90 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {61.0905} \ 91 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {61.0905} \ 92 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {61.0905} \ 93 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {61.0905} \ 94 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ 95 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ 96 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ 97 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ 98 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ 99 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ 100 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ 101 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ 102 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ 103 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ 104 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ 105 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ 106 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \ 107 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \ 108 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \ 109 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \ 110 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \ 111 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \ 112 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \ 113 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \ 114 | CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ 115 | CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \ 116 | CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666667} \ 117 | CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ 118 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ 119 | CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ 120 | CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ 121 | CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ 122 | CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ 123 | CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} \ 124 | CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ 125 | CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ 126 | CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ 127 | CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ 128 | CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ 129 | CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ 130 | CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ 131 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 132 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 133 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 134 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 135 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 136 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 137 | CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ 138 | CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ 139 | CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 140 | CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150.000000} \ 141 | CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ 142 | CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ 143 | CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ 144 | CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ 145 | CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158731} \ 146 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ 147 | CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ 148 | CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ 149 | CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ 150 | CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ 151 | CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ 152 | CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ 153 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \ 154 | CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ 155 | CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ 156 | CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ 157 | CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ 158 | CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ 159 | CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ 160 | CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ 161 | CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ 162 | CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ 163 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 164 | CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {142.857132} \ 165 | CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {50.000000} \ 166 | CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {50.000000} \ 167 | CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ 168 | CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ 169 | CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ 170 | CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ 171 | CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ 172 | CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ 173 | CONFIG.PCW_CLK0_FREQ {100000000} \ 174 | CONFIG.PCW_CLK1_FREQ {142857132} \ 175 | CONFIG.PCW_CLK2_FREQ {50000000} \ 176 | CONFIG.PCW_CLK3_FREQ {50000000} \ 177 | CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ 178 | CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ 179 | CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ 180 | CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ 181 | CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ 182 | CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ 183 | CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \ 184 | CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ 185 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ 186 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ 187 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \ 188 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {7} \ 189 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {20} \ 190 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {20} \ 191 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \ 192 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ 193 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ 194 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ 195 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ 196 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ 197 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ 198 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ 199 | CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ 200 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {35} \ 201 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {3} \ 202 | CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ 203 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ 204 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ 205 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ 206 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ 207 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ 208 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ 209 | CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ 210 | CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ 211 | CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ 212 | CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ 213 | CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ 214 | CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ 215 | CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ 216 | CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ 217 | CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ 218 | CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ 219 | CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ 220 | CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ 221 | CONFIG.PCW_EN_EMIO_CAN0 {0} \ 222 | CONFIG.PCW_EN_EMIO_CAN1 {0} \ 223 | CONFIG.PCW_EN_EMIO_ENET0 {0} \ 224 | CONFIG.PCW_EN_EMIO_ENET1 {0} \ 225 | CONFIG.PCW_EN_PTP_ENET0 {0} \ 226 | CONFIG.PCW_EN_PTP_ENET1 {0} \ 227 | CONFIG.PCW_EN_EMIO_GPIO {0} \ 228 | CONFIG.PCW_EN_EMIO_I2C0 {0} \ 229 | CONFIG.PCW_EN_EMIO_I2C1 {0} \ 230 | CONFIG.PCW_EN_EMIO_PJTAG {0} \ 231 | CONFIG.PCW_EN_EMIO_SDIO0 {0} \ 232 | CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ 233 | CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ 234 | CONFIG.PCW_EN_EMIO_SDIO1 {0} \ 235 | CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ 236 | CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ 237 | CONFIG.PCW_EN_EMIO_SPI0 {0} \ 238 | CONFIG.PCW_EN_EMIO_SPI1 {0} \ 239 | CONFIG.PCW_EN_EMIO_UART0 {0} \ 240 | CONFIG.PCW_EN_EMIO_UART1 {0} \ 241 | CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ 242 | CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ 243 | CONFIG.PCW_EN_EMIO_TTC0 {0} \ 244 | CONFIG.PCW_EN_EMIO_TTC1 {0} \ 245 | CONFIG.PCW_EN_EMIO_WDT {0} \ 246 | CONFIG.PCW_EN_EMIO_TRACE {0} \ 247 | CONFIG.PCW_USE_AXI_NONSECURE {0} \ 248 | CONFIG.PCW_USE_M_AXI_GP0 {1} \ 249 | CONFIG.PCW_USE_M_AXI_GP1 {0} \ 250 | CONFIG.PCW_USE_S_AXI_GP0 {0} \ 251 | CONFIG.PCW_USE_S_AXI_GP1 {0} \ 252 | CONFIG.PCW_USE_S_AXI_ACP {1} \ 253 | CONFIG.PCW_USE_S_AXI_HP0 {0} \ 254 | CONFIG.PCW_USE_S_AXI_HP1 {0} \ 255 | CONFIG.PCW_USE_S_AXI_HP2 {0} \ 256 | CONFIG.PCW_USE_S_AXI_HP3 {0} \ 257 | CONFIG.PCW_M_AXI_GP0_FREQMHZ {100} \ 258 | CONFIG.PCW_M_AXI_GP1_FREQMHZ {10} \ 259 | CONFIG.PCW_S_AXI_GP0_FREQMHZ {10} \ 260 | CONFIG.PCW_S_AXI_GP1_FREQMHZ {10} \ 261 | CONFIG.PCW_S_AXI_ACP_FREQMHZ {10} \ 262 | CONFIG.PCW_S_AXI_HP0_FREQMHZ {100} \ 263 | CONFIG.PCW_S_AXI_HP1_FREQMHZ {10} \ 264 | CONFIG.PCW_S_AXI_HP2_FREQMHZ {10} \ 265 | CONFIG.PCW_S_AXI_HP3_FREQMHZ {10} \ 266 | CONFIG.PCW_USE_DMA0 {0} \ 267 | CONFIG.PCW_USE_DMA1 {0} \ 268 | CONFIG.PCW_USE_DMA2 {0} \ 269 | CONFIG.PCW_USE_DMA3 {0} \ 270 | CONFIG.PCW_USE_TRACE {0} \ 271 | CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ 272 | CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ 273 | CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ 274 | CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ 275 | CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ 276 | CONFIG.PCW_USE_CROSS_TRIGGER {0} \ 277 | CONFIG.PCW_FTM_CTI_IN0 {} \ 279 | CONFIG.PCW_FTM_CTI_IN2 {} \ 281 | CONFIG.PCW_FTM_CTI_OUT0 {} \ 283 | CONFIG.PCW_FTM_CTI_OUT2 {} \ 285 | CONFIG.PCW_USE_DEBUG {0} \ 286 | CONFIG.PCW_USE_CR_FABRIC {1} \ 287 | CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ 288 | CONFIG.PCW_USE_DDR_BYPASS {0} \ 289 | CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ 290 | CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ 291 | CONFIG.PCW_USE_EXPANDED_IOP {0} \ 292 | CONFIG.PCW_USE_HIGH_OCM {0} \ 293 | CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ 294 | CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ 295 | CONFIG.PCW_USE_CORESIGHT {0} \ 296 | CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ 297 | CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ 298 | CONFIG.PCW_UART0_BAUD_RATE {115200} \ 299 | CONFIG.PCW_UART1_BAUD_RATE {115200} \ 300 | CONFIG.PCW_EN_4K_TIMER {0} \ 301 | CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ 302 | CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ 303 | CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ 304 | CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ 305 | CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ 306 | CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ 307 | CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ 308 | CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ 309 | CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ 310 | CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ 311 | CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ 312 | CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ 313 | CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ 314 | CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ 315 | CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ 316 | CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ 317 | CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ 318 | CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ 319 | CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ 320 | CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ 321 | CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ 322 | CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ 323 | CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ 324 | CONFIG.PCW_EN_DDR {1} \ 325 | CONFIG.PCW_EN_SMC {0} \ 326 | CONFIG.PCW_EN_QSPI {1} \ 327 | CONFIG.PCW_EN_CAN0 {0} \ 328 | CONFIG.PCW_EN_CAN1 {0} \ 329 | CONFIG.PCW_EN_ENET0 {1} \ 330 | CONFIG.PCW_EN_ENET1 {0} \ 331 | CONFIG.PCW_EN_GPIO {1} \ 332 | CONFIG.PCW_EN_I2C0 {0} \ 333 | CONFIG.PCW_EN_I2C1 {0} \ 334 | CONFIG.PCW_EN_PJTAG {0} \ 335 | CONFIG.PCW_EN_SDIO0 {1} \ 336 | CONFIG.PCW_EN_SDIO1 {0} \ 337 | CONFIG.PCW_EN_SPI0 {0} \ 338 | CONFIG.PCW_EN_SPI1 {0} \ 339 | CONFIG.PCW_EN_UART0 {0} \ 340 | CONFIG.PCW_EN_UART1 {1} \ 341 | CONFIG.PCW_EN_MODEM_UART0 {0} \ 342 | CONFIG.PCW_EN_MODEM_UART1 {0} \ 343 | CONFIG.PCW_EN_TTC0 {0} \ 344 | CONFIG.PCW_EN_TTC1 {0} \ 345 | CONFIG.PCW_EN_WDT {0} \ 346 | CONFIG.PCW_EN_TRACE {0} \ 347 | CONFIG.PCW_EN_USB0 {0} \ 348 | CONFIG.PCW_EN_USB1 {0} \ 349 | CONFIG.PCW_DQ_WIDTH {32} \ 350 | CONFIG.PCW_DQS_WIDTH {4} \ 351 | CONFIG.PCW_DM_WIDTH {4} \ 352 | CONFIG.PCW_MIO_PRIMITIVE {54} \ 353 | CONFIG.PCW_EN_CLK0_PORT {1} \ 354 | CONFIG.PCW_EN_CLK1_PORT {0} \ 355 | CONFIG.PCW_EN_CLK2_PORT {0} \ 356 | CONFIG.PCW_EN_CLK3_PORT {0} \ 357 | CONFIG.PCW_EN_RST0_PORT {1} \ 358 | CONFIG.PCW_EN_RST1_PORT {0} \ 359 | CONFIG.PCW_EN_RST2_PORT {0} \ 360 | CONFIG.PCW_EN_RST3_PORT {0} \ 361 | CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ 362 | CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ 363 | CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ 364 | CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ 365 | CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ 366 | CONFIG.PCW_P2F_DMAC0_INTR {0} \ 367 | CONFIG.PCW_P2F_DMAC1_INTR {0} \ 368 | CONFIG.PCW_P2F_DMAC2_INTR {0} \ 369 | CONFIG.PCW_P2F_DMAC3_INTR {0} \ 370 | CONFIG.PCW_P2F_DMAC4_INTR {0} \ 371 | CONFIG.PCW_P2F_DMAC5_INTR {0} \ 372 | CONFIG.PCW_P2F_DMAC6_INTR {0} \ 373 | CONFIG.PCW_P2F_DMAC7_INTR {0} \ 374 | CONFIG.PCW_P2F_SMC_INTR {0} \ 375 | CONFIG.PCW_P2F_QSPI_INTR {0} \ 376 | CONFIG.PCW_P2F_CTI_INTR {0} \ 377 | CONFIG.PCW_P2F_GPIO_INTR {0} \ 378 | CONFIG.PCW_P2F_USB0_INTR {0} \ 379 | CONFIG.PCW_P2F_ENET0_INTR {0} \ 380 | CONFIG.PCW_P2F_SDIO0_INTR {0} \ 381 | CONFIG.PCW_P2F_I2C0_INTR {0} \ 382 | CONFIG.PCW_P2F_SPI0_INTR {0} \ 383 | CONFIG.PCW_P2F_UART0_INTR {0} \ 384 | CONFIG.PCW_P2F_CAN0_INTR {0} \ 385 | CONFIG.PCW_P2F_USB1_INTR {0} \ 386 | CONFIG.PCW_P2F_ENET1_INTR {0} \ 387 | CONFIG.PCW_P2F_SDIO1_INTR {0} \ 388 | CONFIG.PCW_P2F_I2C1_INTR {0} \ 389 | CONFIG.PCW_P2F_SPI1_INTR {0} \ 390 | CONFIG.PCW_P2F_UART1_INTR {0} \ 391 | CONFIG.PCW_P2F_CAN1_INTR {0} \ 392 | CONFIG.PCW_IRQ_F2P_INTR {1} \ 393 | CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ 394 | CONFIG.PCW_CORE0_FIQ_INTR {0} \ 395 | CONFIG.PCW_CORE0_IRQ_INTR {0} \ 396 | CONFIG.PCW_CORE1_FIQ_INTR {0} \ 397 | CONFIG.PCW_CORE1_IRQ_INTR {0} \ 398 | CONFIG.PCW_VALUE_SILVERSION {3} \ 399 | CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ 400 | CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ 401 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 402 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ 403 | CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ 404 | CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ 405 | CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ 406 | CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ 407 | CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \ 408 | CONFIG.PCW_UIPARAM_DDR_BL {8} \ 409 | CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ 410 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \ 411 | CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ 412 | CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \ 413 | CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ 414 | CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 415 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ 416 | CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 417 | CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ 418 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ 419 | CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {} \ 421 | CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {} \ 423 | CONFIG.PCW_DDR_PRIORITY_READPORT_0 {} \ 425 | CONFIG.PCW_DDR_PRIORITY_READPORT_2 {} \ 427 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 428 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 429 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 430 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 431 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 432 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 433 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 434 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 435 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 436 | CONFIG.PCW_NAND_NAND_IO {} \ 439 | CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ 440 | CONFIG.PCW_NOR_NOR_IO {} \ 443 | CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ 444 | CONFIG.PCW_NOR_GRP_CS0_IO {} \ 447 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 448 | CONFIG.PCW_NOR_GRP_CS1_IO {} \ 451 | CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ 452 | CONFIG.PCW_NOR_GRP_SRAM_INT_IO {} \ 459 | CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ 460 | CONFIG.PCW_QSPI_GRP_IO1_IO {} \ 463 | CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ 464 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ 465 | CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 466 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ 467 | CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 468 | CONFIG.PCW_ENET_RESET_ENABLE {1} \ 469 | CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ 470 | CONFIG.PCW_ENET0_RESET_ENABLE {0} \ 471 | CONFIG.PCW_ENET0_RESET_IO {} \ 474 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 475 | CONFIG.PCW_ENET1_GRP_MDIO_IO {} \ 478 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ 479 | CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 480 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ 481 | CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 482 | CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \ 483 | CONFIG.PCW_SD0_GRP_WP_IO {MIO 46} \ 484 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 485 | CONFIG.PCW_SD0_GRP_POW_IO {} \ 488 | CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ 489 | CONFIG.PCW_SD1_GRP_CD_IO {} \ 492 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 493 | CONFIG.PCW_SD1_GRP_POW_IO {} \ 496 | CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ 497 | CONFIG.PCW_UART0_GRP_FULL_IO {} \ 502 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 503 | CONFIG.PCW_SPI0_SPI0_IO {} \ 506 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 507 | CONFIG.PCW_SPI0_GRP_SS1_IO {} \ 510 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 511 | CONFIG.PCW_SPI1_SPI1_IO {} \ 514 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 515 | CONFIG.PCW_SPI1_GRP_SS1_IO {} \ 518 | CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ 519 | CONFIG.PCW_CAN0_CAN0_IO {} \ 522 | CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ 523 | CONFIG.PCW_CAN1_CAN1_IO {} \ 526 | CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ 527 | CONFIG.PCW_TRACE_TRACE_IO {} \ 530 | CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ 531 | CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ 534 | CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \ 535 | CONFIG.PCW_TRACE_GRP_16BIT_IO {} \ 538 | CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ 539 | CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ 540 | CONFIG.PCW_WDT_WDT_IO {} \ 543 | CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ 544 | CONFIG.PCW_TTC1_TTC1_IO {} \ 547 | CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \ 548 | CONFIG.PCW_USB0_USB0_IO {} \ 551 | CONFIG.PCW_USB0_RESET_ENABLE {0} \ 552 | CONFIG.PCW_USB0_RESET_IO {} \ 555 | CONFIG.PCW_USB1_RESET_ENABLE {0} \ 556 | CONFIG.PCW_USB1_RESET_IO {} \ 559 | CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ 560 | CONFIG.PCW_I2C0_GRP_INT_IO {} \ 563 | CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ 564 | CONFIG.PCW_I2C1_I2C1_IO {} \ 567 | CONFIG.PCW_I2C_RESET_ENABLE {1} \ 568 | CONFIG.PCW_I2C_RESET_SELECT {} \ 571 | CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ 572 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ 573 | CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 574 | CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ 575 | CONFIG.PCW_GPIO_EMIO_GPIO_IO {} \ 279 | CONFIG.PCW_FTM_CTI_IN2 {} \ 281 | CONFIG.PCW_FTM_CTI_OUT0 {} \ 283 | CONFIG.PCW_FTM_CTI_OUT2 {} \ 285 | CONFIG.PCW_USE_DEBUG {0} \ 286 | CONFIG.PCW_USE_CR_FABRIC {1} \ 287 | CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ 288 | CONFIG.PCW_USE_DDR_BYPASS {0} \ 289 | CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ 290 | CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ 291 | CONFIG.PCW_USE_EXPANDED_IOP {0} \ 292 | CONFIG.PCW_USE_HIGH_OCM {0} \ 293 | CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ 294 | CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ 295 | CONFIG.PCW_USE_CORESIGHT {0} \ 296 | CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ 297 | CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ 298 | CONFIG.PCW_UART0_BAUD_RATE {115200} \ 299 | CONFIG.PCW_UART1_BAUD_RATE {115200} \ 300 | CONFIG.PCW_EN_4K_TIMER {0} \ 301 | CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ 302 | CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ 303 | CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ 304 | CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ 305 | CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ 306 | CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ 307 | CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ 308 | CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ 309 | CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ 310 | CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ 311 | CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ 312 | CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ 313 | CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ 314 | CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ 315 | CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ 316 | CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ 317 | CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ 318 | CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ 319 | CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ 320 | CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ 321 | CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ 322 | CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ 323 | CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ 324 | CONFIG.PCW_EN_DDR {1} \ 325 | CONFIG.PCW_EN_SMC {0} \ 326 | CONFIG.PCW_EN_QSPI {1} \ 327 | CONFIG.PCW_EN_CAN0 {0} \ 328 | CONFIG.PCW_EN_CAN1 {0} \ 329 | CONFIG.PCW_EN_ENET0 {1} \ 330 | CONFIG.PCW_EN_ENET1 {0} \ 331 | CONFIG.PCW_EN_GPIO {1} \ 332 | CONFIG.PCW_EN_I2C0 {0} \ 333 | CONFIG.PCW_EN_I2C1 {0} \ 334 | CONFIG.PCW_EN_PJTAG {0} \ 335 | CONFIG.PCW_EN_SDIO0 {1} \ 336 | CONFIG.PCW_EN_SDIO1 {0} \ 337 | CONFIG.PCW_EN_SPI0 {0} \ 338 | CONFIG.PCW_EN_SPI1 {0} \ 339 | CONFIG.PCW_EN_UART0 {0} \ 340 | CONFIG.PCW_EN_UART1 {1} \ 341 | CONFIG.PCW_EN_MODEM_UART0 {0} \ 342 | CONFIG.PCW_EN_MODEM_UART1 {0} \ 343 | CONFIG.PCW_EN_TTC0 {0} \ 344 | CONFIG.PCW_EN_TTC1 {0} \ 345 | CONFIG.PCW_EN_WDT {0} \ 346 | CONFIG.PCW_EN_TRACE {0} \ 347 | CONFIG.PCW_EN_USB0 {0} \ 348 | CONFIG.PCW_EN_USB1 {0} \ 349 | CONFIG.PCW_DQ_WIDTH {32} \ 350 | CONFIG.PCW_DQS_WIDTH {4} \ 351 | CONFIG.PCW_DM_WIDTH {4} \ 352 | CONFIG.PCW_MIO_PRIMITIVE {54} \ 353 | CONFIG.PCW_EN_CLK0_PORT {1} \ 354 | CONFIG.PCW_EN_CLK1_PORT {0} \ 355 | CONFIG.PCW_EN_CLK2_PORT {0} \ 356 | CONFIG.PCW_EN_CLK3_PORT {0} \ 357 | CONFIG.PCW_EN_RST0_PORT {1} \ 358 | CONFIG.PCW_EN_RST1_PORT {0} \ 359 | CONFIG.PCW_EN_RST2_PORT {0} \ 360 | CONFIG.PCW_EN_RST3_PORT {0} \ 361 | CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ 362 | CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ 363 | CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ 364 | CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ 365 | CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ 366 | CONFIG.PCW_P2F_DMAC0_INTR {0} \ 367 | CONFIG.PCW_P2F_DMAC1_INTR {0} \ 368 | CONFIG.PCW_P2F_DMAC2_INTR {0} \ 369 | CONFIG.PCW_P2F_DMAC3_INTR {0} \ 370 | CONFIG.PCW_P2F_DMAC4_INTR {0} \ 371 | CONFIG.PCW_P2F_DMAC5_INTR {0} \ 372 | CONFIG.PCW_P2F_DMAC6_INTR {0} \ 373 | CONFIG.PCW_P2F_DMAC7_INTR {0} \ 374 | CONFIG.PCW_P2F_SMC_INTR {0} \ 375 | CONFIG.PCW_P2F_QSPI_INTR {0} \ 376 | CONFIG.PCW_P2F_CTI_INTR {0} \ 377 | CONFIG.PCW_P2F_GPIO_INTR {0} \ 378 | CONFIG.PCW_P2F_USB0_INTR {0} \ 379 | CONFIG.PCW_P2F_ENET0_INTR {0} \ 380 | CONFIG.PCW_P2F_SDIO0_INTR {0} \ 381 | CONFIG.PCW_P2F_I2C0_INTR {0} \ 382 | CONFIG.PCW_P2F_SPI0_INTR {0} \ 383 | CONFIG.PCW_P2F_UART0_INTR {0} \ 384 | CONFIG.PCW_P2F_CAN0_INTR {0} \ 385 | CONFIG.PCW_P2F_USB1_INTR {0} \ 386 | CONFIG.PCW_P2F_ENET1_INTR {0} \ 387 | CONFIG.PCW_P2F_SDIO1_INTR {0} \ 388 | CONFIG.PCW_P2F_I2C1_INTR {0} \ 389 | CONFIG.PCW_P2F_SPI1_INTR {0} \ 390 | CONFIG.PCW_P2F_UART1_INTR {0} \ 391 | CONFIG.PCW_P2F_CAN1_INTR {0} \ 392 | CONFIG.PCW_IRQ_F2P_INTR {1} \ 393 | CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ 394 | CONFIG.PCW_CORE0_FIQ_INTR {0} \ 395 | CONFIG.PCW_CORE0_IRQ_INTR {0} \ 396 | CONFIG.PCW_CORE1_FIQ_INTR {0} \ 397 | CONFIG.PCW_CORE1_IRQ_INTR {0} \ 398 | CONFIG.PCW_VALUE_SILVERSION {3} \ 399 | CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ 400 | CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ 401 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 402 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ 403 | CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ 404 | CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ 405 | CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ 406 | CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ 407 | CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \ 408 | CONFIG.PCW_UIPARAM_DDR_BL {8} \ 409 | CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ 410 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \ 411 | CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ 412 | CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \ 413 | CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ 414 | CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 415 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ 416 | CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 417 | CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ 418 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ 419 | CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {} \ 421 | CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {} \ 423 | CONFIG.PCW_DDR_PRIORITY_READPORT_0 {} \ 425 | CONFIG.PCW_DDR_PRIORITY_READPORT_2 {} \ 427 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 428 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 429 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 430 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 431 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 432 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 433 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 434 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 435 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 436 | CONFIG.PCW_NAND_NAND_IO {} \ 439 | CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ 440 | CONFIG.PCW_NOR_NOR_IO {} \ 443 | CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ 444 | CONFIG.PCW_NOR_GRP_CS0_IO {} \ 447 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 448 | CONFIG.PCW_NOR_GRP_CS1_IO {} \ 451 | CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ 452 | CONFIG.PCW_NOR_GRP_SRAM_INT_IO {} \ 459 | CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ 460 | CONFIG.PCW_QSPI_GRP_IO1_IO {} \ 463 | CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ 464 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ 465 | CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 466 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ 467 | CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 468 | CONFIG.PCW_ENET_RESET_ENABLE {1} \ 469 | CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ 470 | CONFIG.PCW_ENET0_RESET_ENABLE {0} \ 471 | CONFIG.PCW_ENET0_RESET_IO {} \ 474 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 475 | CONFIG.PCW_ENET1_GRP_MDIO_IO {} \ 478 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ 479 | CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 480 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ 481 | CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 482 | CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \ 483 | CONFIG.PCW_SD0_GRP_WP_IO {MIO 46} \ 484 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 485 | CONFIG.PCW_SD0_GRP_POW_IO {} \ 488 | CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ 489 | CONFIG.PCW_SD1_GRP_CD_IO {} \ 492 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 493 | CONFIG.PCW_SD1_GRP_POW_IO {} \ 496 | CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ 497 | CONFIG.PCW_UART0_GRP_FULL_IO {} \ 502 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 503 | CONFIG.PCW_SPI0_SPI0_IO {} \ 506 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 507 | CONFIG.PCW_SPI0_GRP_SS1_IO {} \ 510 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 511 | CONFIG.PCW_SPI1_SPI1_IO {} \ 514 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 515 | CONFIG.PCW_SPI1_GRP_SS1_IO {} \ 518 | CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ 519 | CONFIG.PCW_CAN0_CAN0_IO {} \ 522 | CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ 523 | CONFIG.PCW_CAN1_CAN1_IO {} \ 526 | CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ 527 | CONFIG.PCW_TRACE_TRACE_IO {} \ 530 | CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ 531 | CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ 534 | CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \ 535 | CONFIG.PCW_TRACE_GRP_16BIT_IO {} \ 538 | CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ 539 | CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ 540 | CONFIG.PCW_WDT_WDT_IO {} \ 543 | CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ 544 | CONFIG.PCW_TTC1_TTC1_IO {} \ 547 | CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \ 548 | CONFIG.PCW_USB0_USB0_IO {} \ 551 | CONFIG.PCW_USB0_RESET_ENABLE {0} \ 552 | CONFIG.PCW_USB0_RESET_IO {} \ 555 | CONFIG.PCW_USB1_RESET_ENABLE {0} \ 556 | CONFIG.PCW_USB1_RESET_IO {} \ 559 | CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ 560 | CONFIG.PCW_I2C0_GRP_INT_IO {} \ 563 | CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ 564 | CONFIG.PCW_I2C1_I2C1_IO {} \ 567 | CONFIG.PCW_I2C_RESET_ENABLE {1} \ 568 | CONFIG.PCW_I2C_RESET_SELECT {} \ 571 | CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ 572 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ 573 | CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 574 | CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ 575 | CONFIG.PCW_GPIO_EMIO_GPIO_IO {