├── Lab_09
    ├── pictures
    │   ├── Screen Shot 2021-07-25 at 8.26.44 PM.png
    │   └── Screen Shot 2021-07-25 at 8.26.55 PM.png
    ├── debounce.v
    ├── sram.v
    ├── README.md
    ├── lab9.v
    ├── load_data.v
    └── LCD_module.v
├── Lab_07
    ├── matrix_data.mem
    ├── debounce.v
    ├── README.md
    ├── sram.v
    ├── read_mem.v
    ├── matrix_cal.v
    ├── uart.v
    ├── lab7.v
    └── lab7.xdc
├── Lab_08
    ├── BCDAdder.v
    ├── README.md
    ├── crack_partial.v
    ├── lab8.v
    ├── md5.v
    └── crack_top.v
├── Lab_01
    ├── README.md
    ├── SeqMultiplierTA_tb.v
    └── SeqMultiplierTA.v
├── Lab_02
    ├── README.md
    ├── mmult_tb.v
    └── mmult.v
├── LICENSE
├── Lab_10
    ├── clk_divider.v
    ├── sram.v
    ├── sram_firework.v
    ├── README.md
    ├── sram_moon.v
    ├── vga_sync.v
    ├── lab10.v
    └── arty_lab10.xdc
├── Lab_03
    ├── README.md
    └── lab3.v
├── Lab_05
    ├── README.md
    ├── debounce.v
    ├── sieve_algorithm.v
    ├── lab5.v
    └── LCD_module.v
├── README.md
├── Lab_04
    ├── gcd_calculator.v
    ├── README.md
    ├── uart.v
    └── lab4.xdc
└── CODE_OF_CONDUCT.md


/Lab_09/pictures/Screen Shot 2021-07-25 at 8.26.44 PM.png:
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https://raw.githubusercontent.com/hankshyu/Digital-Design/HEAD/Lab_09/pictures/Screen Shot 2021-07-25 at 8.26.44 PM.png


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/Lab_09/pictures/Screen Shot 2021-07-25 at 8.26.55 PM.png:
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https://raw.githubusercontent.com/hankshyu/Digital-Design/HEAD/Lab_09/pictures/Screen Shot 2021-07-25 at 8.26.55 PM.png


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/Lab_07/matrix_data.mem:
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 1 | E1
 2 | 6B
 3 | D7
 4 | 1D
 5 | B6
 6 | 0C
 7 | 55
 8 | 2D
 9 | 1E
10 | E8
11 | 80
12 | 27
13 | A6
14 | 34
15 | DB
16 | B7
17 | B9
18 | 0A
19 | 8E
20 | 98
21 | 73
22 | 99
23 | B0
24 | F8
25 | 38
26 | 76
27 | 0B
28 | A0
29 | 6E
30 | BC
31 | 02
32 | D3


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/Lab_08/BCDAdder.v:
--------------------------------------------------------------------------------
 1 | module BCDAdder #(parameter SIZE = 8)
 2 |                  (input [SIZE*4-1:0] A,
 3 |                   input [SIZE*4-1:0] B,
 4 |                   output [SIZE*4-1:0] Answer);
 5 |     
 6 |     wire [SIZE-1:0] carry;
 7 |     genvar i;
 8 |     BCDUnitAdder A0(
 9 |         .A(A[3:0]),
10 |         .B(B[3:0]),
11 |         .Cin(0),
12 |         .Sum(Answer[3:0]),
13 |         .Carry(carry[0])
14 |     );
15 |     for (i=1;i<SIZE;i=i+1)begin
16 |         BCDUnitAdder unit(
17 |         .A(A[4*i+:4]),
18 |         .B(B[4*i+:4]),
19 |         .Cin(carry[i-1]),
20 |         .Sum(Answer[4*i+:4]),
21 |         .Carry(carry[i])
22 |     );
23 |     end
24 |     
25 | endmodule
26 | 


--------------------------------------------------------------------------------
/Lab_01/README.md:
--------------------------------------------------------------------------------
 1 | # Lab1 Tasks
 2 | 
 3 | ## In this lab, you must design an 8-bit sequential binary multiplier and use the Vivado Simulator to verify your design
 4 | - You must design your multiplier using only adder, shifter, multiplexor, and gate-level operators. You can not use the multiplication operator of Verilog.
 5 | - The behavior of sequential binary multiplication of 10111 and 10011 is as follows:
 6 | 
 7 | <pre><code>      00010111 -> multiplicand  ́ 
 8 |    x  00010011 -> multiplier
 9 | ---------------      
10 |       00010111
11 |      00010111
12 |     00000000
13 |    00000000
14 | + 00010111
15 | ---------------
16 |   000110110101 -> product</pre></code>
17 | 
18 | ## Module Specification
19 | 
20 | <pre><code>module SeqMultiplier(
21 |     input wire clk,
22 |     input wire enable,
23 |     input wire [7:0] A,
24 |     input wire [7:0] B,
25 |     
26 |     output wire [15:0] C
27 |     );
28 | </code></pre>
29 | 


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/Lab_07/debounce.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 2021/07/29 15:21:33
 7 | // Design Name: 
 8 | // Module Name: debounce
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module debounce(input clk, input btn_input, output btn_output);
24 | 
25 | parameter DEBOUNCE_PERIOD = 2_000_000; /* 20 msec = (100,000,000*0.2) ticks @100MHz */
26 | 
27 | reg [$clog2(DEBOUNCE_PERIOD):0] counter;
28 | 
29 | assign btn_output = (counter == DEBOUNCE_PERIOD);
30 | 
31 | always@(posedge clk) begin
32 |   if (btn_input == 0)
33 |     counter <= 0;
34 |   else
35 |     counter <= counter + (counter != DEBOUNCE_PERIOD);
36 | end
37 | 
38 | endmodule
39 | 


--------------------------------------------------------------------------------
/Lab_02/README.md:
--------------------------------------------------------------------------------
 1 | # Lab2 Tasks
 2 | 
 3 | ## In this lab, you will design a circuit to do a 3x3 matrix multiplication on Vivado Simulator.
 4 | - Two register arrays with of 3x3 matrices will be given to you in the sample Verilog simulation project.
 5 | - You must design a Verilog program to compute their multiplication, and print the result from the testbench.
 6 | - You must use no more than 9 multipliers to implement your circuit
 7 | <br/><br/>
 8 | 
 9 | - A 3x3 matrix multiplication is composed of 9 inner products:
10 | 
11 | - Computation of AxB: </t></t> <strong>  Cij = Sigma(Aik * Bkj)</strong>
12 | 
13 | <pre><code>|a00 a01 a02|   |b00 b01 b02|   |c00 c01 c02|
14 | |a10 a11 a12| x |b10 b11 b12| = |c10 c11 c12|
15 | |a20 a21 a22|   |b20 b21 b22|   |c20 c21 c22|</code></pre>
16 | 
17 | 
18 | 
19 | 
20 | 
21 | ## Module Specification
22 | <pre><code>module mmult(
23 |   input  clk,
24 |   input  reset_n,
25 |   input  enable,
26 |   input  [0:9*8-1] A_mat,
27 |   input  [0:9*8-1] B_mat,
28 |   output valid,
29 | 
30 |   output reg [0:9*17-1] C_mat 
31 | );
32 | </code></pre>
33 | 


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/Lab_09/debounce.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: Dept. of Computer Science, National Chiao Tung University
 4 | // Engineer: Chun-Jen Tsai
 5 | // 
 6 | // Create Date:    09:43:16 10/20/2015 
 7 | // Design Name: 
 8 | // Module Name:    debounce
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool versions: 
12 | // Description: 
13 | //
14 | // Dependencies: 
15 | //
16 | // Revision: 
17 | // Revision 0.01 - File Created
18 | // Additional Comments: 
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module debounce(input clk, input btn_input, output btn_output);
22 | 
23 | parameter DEBOUNCE_PERIOD = 2_000_000; /* 20 msec = (100,000,000*0.2) ticks @100MHz */
24 | 
25 | reg [$clog2(DEBOUNCE_PERIOD):0] counter;
26 | 
27 | assign btn_output = (counter == DEBOUNCE_PERIOD);
28 | 
29 | always@(posedge clk) begin
30 |   if (btn_input == 0)
31 |     counter <= 0;
32 |   else
33 |     counter <= counter + (counter != DEBOUNCE_PERIOD);
34 | end
35 | 
36 | endmodule
37 | 


--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
 1 | MIT License
 2 | 
 3 | Copyright (c) 2022 Tzu-Han Hsu
 4 | 
 5 | Permission is hereby granted, free of charge, to any person obtaining a copy
 6 | of this software and associated documentation files (the "Software"), to deal
 7 | in the Software without restriction, including without limitation the rights
 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 | 
12 | The above copyright notice and this permission notice shall be included in all
13 | copies or substantial portions of the Software.
14 | 
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 | SOFTWARE.
22 | 


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/Lab_10/clk_divider.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date:    15:03:25 11/12/2015 
 7 | // Design Name: 
 8 | // Module Name:    clk_divider 
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool versions: 
12 | // Description:     Divide the input clock by 'divider'.
13 | //
14 | // Dependencies: 
15 | //
16 | // Revision: 
17 | // Revision 0.01 - File Created
18 | // Additional Comments: 
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module clk_divider#(parameter divider = 16)(input clk, input reset, output reg clk_out);
22 | 
23 | localparam half_divider = divider/2;
24 | localparam divider_minus_one = divider-1;
25 | 
26 | reg [7:0] counter;
27 | 
28 | always @(posedge clk)
29 | begin
30 |   if (reset)
31 |     clk_out <= 0;
32 |   else
33 |     clk_out <= (counter < half_divider)? 1 : 0;
34 | end
35 | 
36 | always @(posedge clk)
37 | begin
38 |   if (reset)
39 |     counter <= 0;
40 |   else
41 |     counter <= (counter == divider_minus_one)? 0 : counter + 1;
42 | end
43 | 
44 | endmodule
45 | 


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/Lab_07/README.md:
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 1 | # Lab7 Tasks
 2 | 
 3 | 
 4 | ## In this lab, you will design a circuit to do 4 x 4 matrix multiplications.
 5 | - The user press BTN1 to start the circuit
 6 | - The circuit reads two 4 x 4 matrices from the SRAM, perform the multiplication, and print the output matrix through the UART to a terminal window
 7 | - Design Constraints: You must use no more than 16 multipliers to implement your circuit
 8 | - Each Atrix-7 35T FPGA on the Arty board has 90 20 ́18-bit multipliers
 9 | 
10 | ## Timing issues on Combinational Path
11 | - A long arithmetic equation will be synthesized into a multi-level combinational circuit path
12 | - You can divide a long combinational path into two or more always blocks to meet the timing constraint
13 | 
14 | ## Setup Time and Hold Time
15 | - To store values into flip-flops (registers) properly, the minimum allowable clock period Tmin is computed by Tmin = Tpath_delay + Tsetup
16 | - Tpath_delay is the propagation delay through logics and wires
17 | - Tsetup is the minimum time data must arrive at D before the next rising edge of clock (setup time)
18 | 
19 | 
20 | ## Module Specification
21 | ### Top module: lab7
22 | <pre><code>module lab7(
23 |   input  clk,
24 |   input  reset_n,
25 |   input  [3:0] usr_btn,
26 |   output [3:0] usr_led,
27 |   input  uart_rx,
28 |   output uart_tx
29 | );</code></pre>
30 | 


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/Lab_10/sram.v:
--------------------------------------------------------------------------------
 1 | //
 2 | // This module show you how to infer an initialized SRAM block
 3 | // in your circuit using the standard Verilog code.  The initial
 4 | // values of the SRAM cells is defined in the text file "image.dat"
 5 | // Each line defines a cell value. The number of data in image.dat
 6 | // must match the size of the sram block exactly.
 7 | 
 8 | module sram
 9 | #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
10 |  (input clk, input we, input en,
11 |   input  [ADDR_WIDTH-1 : 0] addr,
12 |   input  [DATA_WIDTH-1 : 0] data_i,
13 |   output reg [DATA_WIDTH-1 : 0] data_o);
14 | 
15 | // Declareation of the memory cells
16 | (* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
17 | 
18 | integer idx;
19 | 
20 | // ------------------------------------
21 | // SRAM cell initialization
22 | // ------------------------------------
23 | // Initialize the sram cells with the values defined in "image.dat."
24 | initial begin
25 |     $readmemh("images.mem", RAM);
26 | end
27 | 
28 | // ------------------------------------
29 | // SRAM read operation
30 | // ------------------------------------
31 | always@(posedge clk)
32 | begin
33 |   if (en & we)
34 |     data_o <= data_i;
35 |   else
36 |     data_o <= RAM[addr];
37 | end
38 | 
39 | // ------------------------------------
40 | // SRAM write operation
41 | // ------------------------------------
42 | always@(posedge clk)
43 | begin
44 |   if (en & we)
45 |     RAM[addr] <= data_i;
46 | end
47 | 
48 | endmodule
49 | 


--------------------------------------------------------------------------------
/Lab_01/SeqMultiplierTA_tb.v:
--------------------------------------------------------------------------------
 1 | `define CYCLE_TIME 10
 2 | 
 3 | module SeqMultiplierTA_tb;
 4 | 
 5 |     integer SEED = 0;
 6 | 
 7 |     reg         clk;
 8 |     reg         enable;
 9 |     reg  [7:0]  A, B;
10 |     reg  [15:0] golden_C;
11 |     wire [15:0] C;
12 | 
13 |     integer pat_idx;
14 |     integer i;
15 | 
16 |     always #(`CYCLE_TIME / 2.0) clk = ~clk;
17 |     initial clk = 0;
18 | 
19 |     SeqMultiplierTA DUT(
20 |         .clk(clk),
21 |         .enable(enable),
22 |         .A(A),
23 |         .B(B),
24 |         .C(C)
25 |     );
26 | 
27 | 
28 |     initial begin
29 | 
30 |         A = 0;
31 |         B = 0;
32 |         enable = 0;
33 |         @(negedge clk);
34 | 
35 | 
36 |         for (pat_idx = 0; pat_idx < 10000; pat_idx = pat_idx + 1) begin
37 |             // in pat
38 |             A = $random(SEED);
39 |             B = $random(SEED);
40 |             $display("* Input pattern: ");
41 |             $display("    - A: %d", A);
42 |             $display("    - B: %d", B);
43 |             enable = 1;
44 |             @(negedge clk);
45 |             // wait for 8 cycles
46 |             for (i = 0; i < 8; i = i + 1) @(negedge clk);
47 |             // check ans
48 |             golden_C = A * B;
49 |             $display("    - C v.s Golden C: %d v.s %d", C, golden_C);
50 |             if (C !== golden_C) begin
51 |                 $display("Wrong!");
52 |                 $finish;
53 |             end
54 |             $display("--------------------------------");
55 |             enable = 0;
56 |             @(negedge clk);
57 | 
58 |         end
59 |         $display("Pass");
60 | 
61 |         $finish;
62 |     end
63 | 
64 | endmodule
65 | 


--------------------------------------------------------------------------------
/Lab_07/sram.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 2021/07/29 14:43:36
 7 | // Design Name: 
 8 | // Module Name: sram
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | module sram
23 | #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
24 |  (input clk, input we, input en,
25 |   input  [ADDR_WIDTH-1 : 0] addr,
26 |   input  [DATA_WIDTH-1 : 0] data_i,
27 |   output reg [DATA_WIDTH-1 : 0] data_o);
28 | 
29 | // Declareation of the memory cells
30 | (* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
31 | 
32 | integer idx;
33 | 
34 | // ------------------------------------
35 | // SRAM cell initialization
36 | // ------------------------------------
37 | // Initialize the sram cells with the values defined in "image.dat."
38 | initial begin
39 |     $readmemh("matrix_data.mem", RAM);
40 | end
41 | 
42 | // ------------------------------------
43 | // SRAM read operation
44 | // ------------------------------------
45 | always@(posedge clk)
46 | begin
47 |   if (en & we)
48 |     data_o <= data_i;
49 |   else
50 |     data_o <= RAM[addr];
51 | end
52 | 
53 | // ------------------------------------
54 | // SRAM write operation
55 | // ------------------------------------
56 | always@(posedge clk)
57 | begin
58 |   if (en & we)
59 |     RAM[addr] <= data_i;
60 | end
61 | 
62 | endmodule
63 | 


--------------------------------------------------------------------------------
/Lab_03/README.md:
--------------------------------------------------------------------------------
 1 | # Lab3 Tasks
 2 | 
 3 | ## In this lab, you will use the FPGA development board “Arty” to implement a simple I/O control circuit
 4 | 
 5 | 👉 Your circuit should have a 4-bit counter register
 6 | - The counter value is set to zero upon reset
 7 | - he counter value is a signed value in 2’complement format n The 4 LEDs display the 4 counter bits at all time
 8 | <br/>
 9 | 👉 Push-buttons #0 and #1 are used to decrease/increase the counter value: 
10 | 
11 | - Push the BTN1/BTN0 increases/decreases the counter by 1
12 | - If the counter value becomes grater than 7, it is truncated to 7;
13 | - If the value is smaller than –8, it is set to –8
14 | <br/>
15 | 👉 Push-buttons #2 and #3 are used to control the brightness of the LEDs
16 | 
17 | - BTN3 makes the LED brighter and BTN2 makes it darker
18 | 
19 | 
20 | ## In reality, however, the signal value oscillates between 0 and 1 several times before it stabilizes. This is called the bouncing behavior of a hardware button.
21 | - We may set a timer to wait out the bouncing period
22 | 
23 | ## The LED device in the Arty board can only be fully lit (full power) or turned off (zero power).
24 | - To trick your eyes to see different levels of brightness, you can send a PWM signal to its power input
25 | - A PWM input to the LED turns it on-an-off quickly
26 | - The persistence of human visions will not see flickering but only different levels of brightness, as long as your PWM frequency is high enough
27 | 
28 | 
29 | ## Module Specification
30 | <pre><code>module lab3(
31 |   input  clk,            // System clock at 100 MHz
32 |   input  reset_n,        // System negative reset signal
33 |   input  [3:0] usr_btn,  // Four user pushbuttons
34 |   output [3:0] usr_led   // Four yellow LEDs
35 | );
36 | 
37 | </code></pre>
38 | 


--------------------------------------------------------------------------------
/Lab_05/README.md:
--------------------------------------------------------------------------------
 1 | # Lab5 Tasks
 2 | 
 3 | ## In this lab, you will use the sieve algorithm to find all the primes from 2 to 1021, and use the standard 1602 character LCD to display the prime numbers
 4 | 
 5 | ## Memory Map of the LCD
 6 | - The LCD device can be treated as a 32-byte memory
 7 | <br/> -> Each memory cell corresponds to a character on the display
 8 | <br/> -> Writing an ASCII code to a cell will display the character on the corresponding location on the LCD
 9 | 
10 | ## The Sieve Algorithm
11 | - The sieve algorithm is an interesting algorithm to find prime numbers using only addition operations:
12 | <pre><code>#define LIMIT 1024
13 | unsigned char primes[LIMIT];
14 | memset((void *) primes, 1, sizeof(primes));
15 | 
16 | /* sieve algorithm */
17 | for (idx = 2; idx < LIMIT; idx++)
18 | {
19 |     if (primes[idx])
20 |     {
21 |         for (jdx = idx+idx; jdx < LIMIT; jdx += idx)
22 |         {
23 |             primes[jdx] = 0;
24 |          } 
25 |      }
26 | }</code></pre>
27 | 
28 | - After running the Sieve algorithm, the array primes[ ] contains flags of whether a number is a prime or not
29 | - primes[n] == 1 means n is a prime number
30 | - primes[n] == 0 means n is not a prime number
31 | 
32 | 
33 | ## What to Do in Lab 5
34 | - Design a circuit to implement the sieve algorithm
35 | - Once all primes between 0 and 1023 are found, the LCD will start to display prime numbers in the following format
36 | - Roughly every 0.7 sec, the LCD scrolls up one number cyclically - If BTN3 is pressed, the scrolling direction will be reversed (scroll-up becomes scroll-down, and vice versa)
37 | 
38 | ## Module Specification
39 | ### Top module: lab5
40 | <pre><code>module lab5(input clk,
41 |   input reset_n,
42 |   input [3:0] usr_btn,
43 |   output [3:0] usr_led,
44 |   output LCD_RS,
45 |   output LCD_RW,
46 |   output LCD_E,
47 |   output [3:0] LCD_D
48 |   );</code></pre>
49 | 
50 | 


--------------------------------------------------------------------------------
/Lab_08/README.md:
--------------------------------------------------------------------------------
 1 | # Lab8 Tasks
 2 | 
 3 | ## In this lab, you will design a circuit to guess an 8-digit password scrambled with the MD5 Message-Digest Algorithm
 4 | - The password is composed of eight decimal digits coded in ASCII codes
 5 | - he MD5 hash code of the password will be given to you
 6 | - Your circuit must crack it, and display the original password and the time it takes for you to crack the password on the LCD module
 7 | - In order to crack the code as fast as possible, you should try to instantiate multiple copies of md5 circuit blocks and compute the hash code in parallel
 8 | - 
 9 | ## MD5 Message-Digest Algorithm
10 | - The algorithm takes as input a message of arbitrary length and produces as output a 128-bit "message digest" of the input.
11 | - MD5 was developed by Ronald Rivest in 1991, and became a standard known as IETF RFC-1321
12 | - [Memo about MD5 from IETF](https://www.ietf.org/rfc/rfc1321.txt)
13 | 
14 | 
15 | ## What to Do in Lab8
16 | - You must rewrite the md5 function and the cracker code using Verilog and implement it on the Arty board
17 | - In your circuit, the password hash code should be declared as follows:
18 | <pre><code>reg [0:127] passwd_hash = 128’hE9982EC5CA981BD365603623CF4B2277;</code></pre>
19 | - Once the user press BTN3, your circuit will crack the password and show it on the LCD module
20 | 
21 | 
22 | ## Module Specification
23 | ### Top module: lab8
24 | <pre><code>module lab8(
25 |   input clk,
26 |   input reset_n,
27 |   input [3:0] usr_btn,
28 |   output [3:0] usr_led,
29 |   output LCD_RS,
30 |   output LCD_RW,
31 |   output LCD_E,
32 |   output [3:0] LCD_D
33 | );</code></pre>
34 | 
35 | ## Experiments
36 | 
37 | Device          | Time  (us)
38 | --------------|:-----
39 | CPU i5-8259u   | 16,804,558 
40 | CPU i7-4770 (given)  | 10,000,000
41 | Single decode core on Arty| 21048
42 | 5 decode cores on Arty| 6699
43 | 10 decode cores on Arty| 939
44 | 25 decode cores on Arty| 0.35
45 | 32 decode cores on Arty| 0.35
46 | 
47 | 
48 | 
49 | 


--------------------------------------------------------------------------------
/Lab_09/sram.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 2017/12/06 20:47:51
 7 | // Design Name: 
 8 | // Module Name: sram
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // This module show you how to infer an initialized SRAM block
15 | // in your circuit using the standard Verilog code.  The initial
16 | // values of the SRAM cells is defined in the text file "signals.dat"
17 | // Each line defines a cell value. The number of data in signals.dat
18 | // must match the size of the sram block exactly.
19 | //
20 | // Dependencies: 
21 | // 
22 | // Revision:
23 | // Revision 0.01 - File Created
24 | // Additional Comments:
25 | // 
26 | //////////////////////////////////////////////////////////////////////////////////
27 | 
28 | 
29 | module sram
30 | #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 11, RAM_SIZE = 2048)
31 |  (input clk, input we, input en,
32 |   input  [ADDR_WIDTH-1 : 0] addr,
33 |   input  [DATA_WIDTH-1 : 0] data_i,
34 |   output reg [DATA_WIDTH-1 : 0] data_o);
35 | 
36 | // Declareation of the memory cells
37 | reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
38 | 
39 | // ------------------------------------
40 | // SRAM cell initialization
41 | // ------------------------------------
42 | // Initialize the sram cells with the values defined in "image.dat."
43 | initial begin
44 |     $readmemh("signals.mem", RAM);
45 | end
46 | 
47 | // ------------------------------------
48 | // SRAM read operation
49 | // ------------------------------------
50 | always@(posedge clk)
51 | begin
52 |   if (en & we)
53 |     data_o <= data_i;
54 |   else
55 |     data_o <= RAM[addr];
56 | end
57 | 
58 | // ------------------------------------
59 | // SRAM write operation
60 | // ------------------------------------
61 | always@(posedge clk)
62 | begin
63 |   if (en & we)
64 |     RAM[addr] <= data_i;
65 | end
66 | 
67 | endmodule
68 | 


--------------------------------------------------------------------------------
/Lab_01/SeqMultiplierTA.v:
--------------------------------------------------------------------------------
 1 | module SeqMultiplierTA (
 2 |     input  wire           clk,
 3 |     input  wire           enable,
 4 |     input  wire [7:0]     A,
 5 |     input  wire [7:0]     B,
 6 |     output wire [15:0]    C
 7 | );
 8 | 
 9 |     localparam [1:0] M_IDEL = 0,
10 |                      M_MUL  = 1,
11 |                      M_OUT  = 2;
12 | 
13 |     reg [1:0] c_state, n_state;
14 |     reg [3:0] idx;
15 |     reg [7:0] A_reg, B_reg;
16 |     reg [15:0] C_reg;
17 | 
18 |     wire mul_fin;
19 | 
20 |     // FSM
21 | 
22 |     always @(posedge clk) begin
23 |         if (~enable) c_state <= M_IDEL;
24 |         else c_state <= n_state;
25 |     end
26 | 
27 |     always @(*) begin
28 |         case (c_state) 
29 |             M_IDEL:
30 |                 if (enable) n_state = M_MUL;
31 |                 else n_state = M_IDEL;
32 |             M_MUL:
33 |                 if (mul_fin) n_state = M_OUT;
34 |                 else n_state = M_MUL;
35 |             M_OUT:
36 |                 n_state = M_IDEL;
37 |             default: n_state = M_IDEL;
38 |         endcase
39 |     end
40 | 
41 |     always @(posedge clk) begin
42 |         if (c_state == M_IDEL) idx <= 7;
43 |         else if (c_state == M_MUL) idx <= idx - 1;
44 |     end
45 | 
46 |     assign mul_fin = (idx == 0);
47 |     
48 |     // MUL Logic
49 |     wire C_accumulate;
50 |     wire [15:0] C_sl_one;
51 | 
52 |     assign C_accumulate = (B_reg & 8'h80) == 8'h80;
53 |     assign C_sl_one = C_reg << 1;
54 | 
55 |     always @(posedge clk) begin
56 |         if (c_state == M_IDEL && enable) A_reg <= A;
57 |     end
58 | 
59 |     always @(posedge clk) begin
60 |         if (c_state == M_IDEL && enable) B_reg <= B;
61 |         else if (c_state == M_MUL) B_reg <= B_reg << 1; 
62 |     end
63 | 
64 |     always @(posedge clk) begin
65 |         if (c_state == M_IDEL && enable) C_reg <= 0;
66 |         else if (c_state == M_MUL) C_reg <= C_accumulate ? C_sl_one + A_reg : C_sl_one;
67 |     end
68 | 
69 |     // Output Logic 
70 | 
71 |     assign C = C_reg;
72 | 
73 | endmodule


--------------------------------------------------------------------------------
/Lab_10/sram_firework.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 2021/07/27 21:14:59
 7 | // Design Name: 
 8 | // Module Name: sram_firework
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | //
24 | // This module show you how to infer an initialized SRAM block
25 | // in your circuit using the standard Verilog code.  The initial
26 | // values of the SRAM cells is defined in the text file "image.dat"
27 | // Each line defines a cell value. The number of data in image.dat
28 | // must match the size of the sram block exactly.
29 | 
30 | module sram_firework
31 | #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 12000)
32 |  (input clk, input we, input en,
33 |   input  [ADDR_WIDTH-1 : 0] addr,
34 |   input  [DATA_WIDTH-1 : 0] data_i,
35 |   output reg [DATA_WIDTH-1 : 0] data_o);
36 | 
37 | // Declareation of the memory cells
38 | (* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
39 | 
40 | integer idx;
41 | 
42 | // ------------------------------------
43 | // SRAM cell initialization
44 | // ------------------------------------
45 | // Initialize the sram cells with the values defined in "image.dat."
46 | initial begin
47 |     $readmemh("firework6.mem", RAM);
48 | end
49 | 
50 | // ------------------------------------
51 | // SRAM read operation
52 | // ------------------------------------
53 | always@(posedge clk)
54 | begin
55 |   if (en & we)
56 |     data_o <= data_i;
57 |   else
58 |     data_o <= RAM[addr];
59 | end
60 | 
61 | // ------------------------------------
62 | // SRAM write operation
63 | // ------------------------------------
64 | always@(posedge clk)
65 | begin
66 |   if (en & we)
67 |     RAM[addr] <= data_i;
68 | end
69 | 
70 | endmodule
71 | 
72 | 


--------------------------------------------------------------------------------
/Lab_05/debounce.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company:
 4 | // Engineer:
 5 | //
 6 | // Create Date: 2021/07/12 20:55:58
 7 | // Design Name:
 8 | // Module Name: debounce
 9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module debounce(input clk,
24 |                 input btn_input,
25 |                 output btn_output);
26 |     
27 |     parameter DE_BOUNCE_CYCLE = 15_000_000 ; //0.15 sec wait time
28 |     
29 |     reg[$clog2(DE_BOUNCE_CYCLE):0] debounce_counter;
30 |     wire debounce_counter_expire;
31 |     
32 |     localparam ZERO        = 0;
33 |     localparam ZERO_TO_ONE = 1;
34 |     localparam ONE         = 2;
35 |     localparam ONE_TO_ZERO = 3;
36 |     
37 |     reg [1:0] current_state,next_state;
38 |  
39 |     
40 |     initial begin
41 |         {current_state[1],current_state[0]} <= {1'b0,1'b0};
42 |     end
43 |     
44 |     always @(posedge clk) begin
45 |         current_state <= next_state;
46 |     end
47 |     
48 |     always @(*) begin
49 |         case(current_state)
50 |             ZERO: next_state       = (btn_input)?ZERO_TO_ONE:ZERO;
51 |             ZERO_TO_ONE: next_state = (debounce_counter_expire)?ONE:ZERO_TO_ONE;
52 |             ONE: next_state         = (!btn_input)?ONE_TO_ZERO:ONE;
53 |             ONE_TO_ZERO: next_state = (debounce_counter_expire)?ZERO:ONE_TO_ZERO;
54 |             
55 |         endcase
56 |     end
57 |     
58 |     always @(posedge clk) begin
59 |         case(current_state)
60 |             ZERO: debounce_counter<=0;
61 |             ZERO_TO_ONE:debounce_counter<=debounce_counter+1;
62 |             ONE:debounce_counter<=0;
63 |             ONE_TO_ZERO:debounce_counter<=debounce_counter+1;
64 |         endcase
65 |         
66 |     end
67 |     
68 |     assign debounce_counter_expire = (debounce_counter >= DE_BOUNCE_CYCLE);
69 |     
70 |     assign btn_output = (current_state == ZERO_TO_ONE || current_state == ONE);
71 |     
72 |     
73 |     
74 | endmodule
75 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
 1 | # Digital-Design
 2 | 
 3 | <img alt="GitHub" src="https://img.shields.io/github/license/hankshyu/Digital_Design?color=orange&logo=github"> <img alt="GitHub release (latest SemVer)" src="https://img.shields.io/github/v/release/hankshyu/Digital_Design?color=orange&logo=github"> <img alt="GitHub language count" src="https://img.shields.io/github/languages/count/hankshyu/Digital_Design"> <img alt="GitHub top language" src="https://img.shields.io/github/languages/top/hankshyu/Digital_Design"> <img alt="GitHub code size in bytes" src="https://img.shields.io/github/languages/code-size/hankshyu/Digital_Design"> <img alt="GitHub contributors" src="https://img.shields.io/github/contributors/hankshyu/Digital_Design?logo=git&color=green"> <img alt="GitHub commit activity" src="https://img.shields.io/github/commit-activity/y/hankshyu/Digital_Design?logo=git&color=green">  <img alt="GitHub last commit" src="https://img.shields.io/github/last-commit/hankshyu/Digital_Design?logo=git&color=green">
 4 | 
 5 | 
 6 | ### Circuit implementations on the Artix-7 FPGA Development Board
 7 | 
 8 | 
 9 | ## Xilinx Artix-35T FPGA:
10 | - 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-flops)
11 | - 1,800 Kbits of fast block RAM
12 | - Five clock management tiles, each with a phase-locked loop (PLL)
13 | - 90 DSP slices
14 | - Internal clock speeds exceeding 450MHz
15 | - On-chip analog-to-digital converter (XADC)
16 | - Programmable over JTAG and Quad-SPI Flash
17 | 
18 | ## System Features
19 | - 256MB DDR3L with a 16-bit bus @ 667MHz
20 | - 16MB Quad-SPI Flash
21 | - UART,SPI,I2C,10/100 Ethernet
22 | - 4 Switches, 4 Buttons, 8 LEDs(4 RGB)
23 | - USB-JTAG Programming circuitry (USB Micro cable 
24 | 
25 | ## Self Added Features
26 | - Video Graphics Array(VGA) connection
27 | - 1602 Character LCD Display
28 | - SD Card connection
29 | 
30 | 
31 | ## Labs
32 |  Lab   | Descriptions
33 | --------|:-----
34 | [Lab1][l1]|Sequential binary multiplier
35 | [Lab2][l2]|3x3 matrix multiplier
36 | [Lab3][l3]|Simple I/O control circuit
37 | [Lab4][l4]|UART I/O circuit
38 | [Lab5][l5]|Sieve algorithm & Standard 1602 character LCD display
39 | [Lab7][l7]|4 x 4 pipelined matrix multiplier
40 | [Lab8][l8]|MD5 password cracking circuit
41 | [Lab9][l9]|Correlation filter circuit
42 | [Lab10][l10]|VGA video interface circuit
43 | 
44 | 
45 | 
46 | [l1]: Lab_01
47 | [l2]: Lab_02
48 | [l3]: Lab_03
49 | [l4]: Lab_04
50 | [l5]: Lab_05
51 | [l7]: Lab_07
52 | [l8]: Lab_08
53 | [l9]: Lab_09
54 | [l10]: Lab_10
55 | 
56 | 
57 | 


--------------------------------------------------------------------------------
/Lab_10/README.md:
--------------------------------------------------------------------------------
 1 | # Lab10 Tasks
 2 | 
 3 | ## In this lab, you will implement a circuit that shows some graphics using the VGA video interface, your circuit must do the following things:
 4 | - Animates the moon to move across the picture with green- screen removal
 5 | - Adds fireworks animations to the picture
 6 | 
 7 | ## VGA 
 8 | 1. VGA stands for Video Graphics Array; it’s a video interface originally designed for CRT display
 9 | 2. A VGA screen displays the entire screen pixel-by-pixel:
10 | - The pixels of the screen are illuminated following a one- dimensional scanning path
11 | - When pixel at (x, y) are “scanned,” your circuit must tell the screen what RGB color it should display
12 | 
13 | 3. VGA is an analog interface
14 | - 0v stands for the darkest pixel, 0.7v stands for the brightest
15 | - The transition from darkest pixel to brightest pixel is not linear
16 | - A video digital-to-analog converter (DAC) IC is usually used to convert digital pictures to analog VGA signals
17 | - The most popular DAC is the ADV 7125 IC by Analog Devices
18 | 
19 | ## Computer Graphics and Video Buffer
20 | 1. Processors are too slow to directly generate pixel data for video display
21 | - Old arcade games are built using dedicated circuit to produce graphics
22 | 2. A break-through idea that enables software-based computer graphics is the concept of frame buffers (FB)
23 | 3. Computer systems usually use a single-port memory for video frame buffer
24 | - Most memory bandwidth will be used by the video controller 
25 | - CPU cannot make significant update to the content of the frame buffer without interrupting the video controller
26 | - Double frame buffers can be used to solve this problem
27 | 4. Cycle Stealing from the Retrace Time
28 | - Some systems do not have enough memory for double-buffering, other tricks must be used to modify the FB without interfering the video controller
29 | - During the horizontal or vertical retrace periods, the video controller is NOT reading the FB
30 | - FB data modifications during the sync periods will not corrupt video
31 | 
32 | 
33 | ## What to Do in Lab 10
34 | - First, you must replace the green pixels of the moon image by the co-located background pixels
35 | - Secondly, you must use your imaginations to createsome fireworks animations in the sky area
36 | 
37 | ## Module Specification
38 | ### Top module: lab10
39 | <pre><code>module lab10(
40 |   input clk,
41 |   input reset_n,
42 |   input [3:0] usr_btn,
43 |   output [3:0] usr_led,
44 |   output VGA_HSYNC,
45 |   output VGA_VSYNC,
46 |   output [3:0] VGA_RED,
47 |   output [3:0] VGA_GREEN,
48 |   output [3:0] VGA_BLUE
49 | );</code></pre>
50 | 
51 | 


--------------------------------------------------------------------------------
/Lab_10/sram_moon.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 2021/07/27 21:43:04
 7 | // Design Name: 
 8 | // Module Name: sram_moon
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | `timescale 1ns / 1ps
24 | //////////////////////////////////////////////////////////////////////////////////
25 | // Company: 
26 | // Engineer: 
27 | // 
28 | // Create Date: 2021/07/27 21:14:59
29 | // Design Name: 
30 | // Module Name: sram_firework
31 | // Project Name: 
32 | // Target Devices: 
33 | // Tool Versions: 
34 | // Description: 
35 | // 
36 | // Dependencies: 
37 | // 
38 | // Revision:
39 | // Revision 0.01 - File Created
40 | // Additional Comments:
41 | // 
42 | //////////////////////////////////////////////////////////////////////////////////
43 | 
44 | 
45 | //
46 | // This module show you how to infer an initialized SRAM block
47 | // in your circuit using the standard Verilog code.  The initial
48 | // values of the SRAM cells is defined in the text file "image.dat"
49 | // Each line defines a cell value. The number of data in image.dat
50 | // must match the size of the sram block exactly.
51 | 
52 | module sram_moon
53 | #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 2560)
54 |  (input clk, input we, input en,
55 |   input  [ADDR_WIDTH-1 : 0] addr,
56 |   input  [DATA_WIDTH-1 : 0] data_i,
57 |   output reg [DATA_WIDTH-1 : 0] data_o);
58 | 
59 | // Declareation of the memory cells
60 | (* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
61 | 
62 | integer idx;
63 | 
64 | // ------------------------------------
65 | // SRAM cell initialization
66 | // ------------------------------------
67 | // Initialize the sram cells with the values defined in "image.dat."
68 | initial begin
69 |     $readmemh("moon.mem", RAM);
70 | end
71 | 
72 | // ------------------------------------
73 | // SRAM read operation
74 | // ------------------------------------
75 | always@(posedge clk)
76 | begin
77 |   if (en & we)
78 |     data_o <= data_i;
79 |   else
80 |     data_o <= RAM[addr];
81 | end
82 | 
83 | // ------------------------------------
84 | // SRAM write operation
85 | // ------------------------------------
86 | always@(posedge clk)
87 | begin
88 |   if (en & we)
89 |     RAM[addr] <= data_i;
90 | end
91 | 
92 | endmodule
93 | 
94 | 
95 | 


--------------------------------------------------------------------------------
/Lab_09/README.md:
--------------------------------------------------------------------------------
 1 | # Lab9 Tasks
 2 | 
 3 | ## In this lab, you will design a correlation filter circuit and use it to detect the presence of a waveform
 4 | - Your circuit has an SRAM that stores a 1-D waveform f[×] of 1024 data samples and a 1-D pattern g[×] of 64 data samples; each sample in f[×] and g[×] is an 8-bit signed number
 5 | - When the user hit BTN0, your circuit will compute the cross- correlation function Cfg[×] between f[×] and g[×], and display the maximal value of Cfg[×] and its position on the 1602 LCD
 6 | 
 7 | ## Correlation filter
 8 | 1. Mathematically, a correlation filter is the sliding inner product between two signals f(x) and g(x):
 9 | - cross-correlation function Cfg[×] between f[×] and g[×] is defined as:
10 | <img src="https://github.com/hankshyu/Digital_Design/blob/main/Lab9/pictures/Screen%20Shot%202021-07-25%20at%208.26.44%20PM.png" alt="correlation formula" width="500" />
11 | 
12 | - a digital version of the correlation filter is:
13 | <img src="https://github.com/hankshyu/Digital_Design/blob/main/Lab9/pictures/Screen%20Shot%202021-07-25%20at%208.26.55%20PM.png" alt="correlation formula" width="500" />
14 | 
15 | 
16 | 
17 | 3. If f(x) and g(x) are the same signal, it is called auto-correlation
18 | 
19 | - the distances between the peaks of the auto-correlation function of a noisy periodic signals can be used to estimate the period of the signal
20 | 3. If f(x) and g(x) are different signals, it is called cross-correlation
21 | 
22 | - the maximal location of the cross-correlation function between g(x) and f(x) means that a signal most similar to g(x) is located at x0 of f(x)
23 | 4. C Model of Correlation:
24 | <pre><code>char f[1024] = { ... };
25 | char g[64] = { ... };
26 | int  c[960];
27 | int x, y, k, sum, max, max_pos;
28 | max = max_pos = 0;
29 | for (x = 0; x < 1024 - 64; x++)
30 | {
31 |     sum = 0;
32 |     for (k = 0; k < 64; k++)
33 |     {
34 |         sum += f[k+x] * g[k];
35 |     }
36 |     c[x] = sum;
37 |     if (sum > max) max = sum, max_pos = x;
38 | }</code></pre>
39 | ## What to Do in Lab 9
40 | - In this lab, f[0:1023] and g[0:63] are 8-bit signed arrays stored in an SRAM block, and the correlation function cfg[0:959] has 960 elements
41 | - You can use a chain of shift registers to read data from the SRAM, begin at address 0 and ends at 1023
42 | - If the user presses BTN0, the correlation circuit should be activated. When the circuit is done, the maximal value of the correlation and its location should be displayed on the LCD
43 | 
44 | 
45 | 
46 | 
47 | ## Module Specification
48 | ### Top module: lab9
49 | <pre><code>module lab9(
50 |   input clk,
51 |   input reset_n,
52 |   input [3:0] usr_btn,
53 |   output [3:0] usr_led,
54 |   output LCD_RS,
55 |   output LCD_RW,
56 |   output LCD_E,
57 |   output [3:0] LCD_D
58 | );</code></pre>
59 | 
60 | 
61 | 
62 | 
63 | 
64 | 


--------------------------------------------------------------------------------
/Lab_04/gcd_calculator.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company:
 4 | // Engineer:
 5 | //
 6 | // Create Date: 2021/07/09 22:46:30
 7 | // Design Name:
 8 | // Module Name: gcd_calculator
 9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module gcd_calculator(input clk,
24 |                       input rst_n,
25 |                       input enable,
26 |                       input [15:0] A,
27 |                       input [15:0] B,
28 |                       output [15:0] answer,
29 |                       output answer_available);
30 |     
31 |     reg [15:0] A_store;
32 |     reg [15:0] B_store;
33 |     reg reg_answer_available;
34 |     
35 |     localparam [2:0] S_INIT      = 0;
36 |     localparam [2:0] S_JUDGE     = 1;
37 |     localparam [2:0] S_A_GREATER = 2;
38 |     localparam [2:0] S_A_SMALLER = 3;
39 |     localparam [2:0] S_EQUAL     = 4;
40 | 
41 |     reg [2:0] current_state, next_state;
42 |     
43 |     always @(posedge clk ,negedge rst_n) begin
44 |         if (!rst_n) current_state <= S_INIT;
45 |         else current_state        <= next_state;
46 |     end
47 |     
48 |     always @(*) begin
49 |         case(current_state)
50 |             S_INIT: next_state = (enable)?S_JUDGE:S_INIT;
51 |             S_JUDGE:begin
52 |                 if (A_store > B_store) next_state       = S_A_GREATER;
53 |                 else if (A_store < B_store) next_state  = S_A_SMALLER;
54 |                 else if (A_store == B_store) next_state = S_EQUAL;
55 |             end
56 |             S_A_GREATER:next_state = S_JUDGE;
57 |             S_A_SMALLER:next_state = S_JUDGE;
58 |             S_EQUAL:next_state     = S_EQUAL;
59 |             default:next_state     = S_INIT;
60 |         endcase
61 |     end
62 |     
63 |     always @(posedge clk) begin
64 |         if (!rst_n)A_store <= 0;
65 |         else if (current_state == S_INIT)A_store <= A;
66 |         else if (current_state == S_A_GREATER) A_store <= A_store-B_store;
67 |     end
68 |     
69 |     always @(posedge clk) begin
70 |         if (!rst_n)B_store <= 0;
71 |         else if (current_state == S_INIT) B_store <= B;
72 |         else if (current_state == S_A_SMALLER) B_store <= B_store-A_store;
73 |     end
74 |     
75 |     always @(posedge clk) begin
76 |         if(!rst_n) reg_answer_available<=0;
77 |         else if (current_state == S_JUDGE && next_state == S_EQUAL) reg_answer_available       <= 1;
78 |         //else reg_answer_available = 0;
79 |     end
80 |     
81 | 
82 |     //output logic
83 |     assign answer_available = reg_answer_available;
84 |     assign answer           = A_store;
85 |     
86 | endmodule
87 | 


--------------------------------------------------------------------------------
/Lab_07/read_mem.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 2021/07/29 16:57:08
  7 | // Design Name: 
  8 | // Module Name: read_mem
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module read_mem(
 23 |     input clk,
 24 |     input rst_n,
 25 |     input [3:0] btn,
 26 |     output reg [127:0] A,
 27 |     output reg [127:0] B,
 28 |     output done);
 29 | 
 30 |     localparam S_INIT = 0;
 31 |     localparam S_READ_A = 1;
 32 |     localparam S_DONE_A = 2;
 33 |     localparam S_READ_B = 3;
 34 |     localparam S_DONE_B = 4;
 35 |     reg [2:0] current_state, next_state;
 36 | 
 37 |     reg [4:0] A_counter;
 38 |     reg [5:0] B_counter;
 39 |     wire a_done;
 40 |     wire b_done;
 41 | 
 42 |     //ram variables
 43 |     reg [5:0] ram_addr;
 44 |     wire [7:0] ram_data_o;
 45 | 
 46 |     sram #(.DATA_WIDTH(8),.ADDR_WIDTH(6),.RAM_SIZE(32))ram(
 47 |         .clk(clk),
 48 |         .we(btn[3]),
 49 |         .en(1),
 50 |         .addr(ram_addr),
 51 |         .data_i(0),
 52 |         .data_o(ram_data_o)
 53 |     );
 54 | 
 55 |     assign a_done = (A_counter == 17);
 56 |     assign b_done = (B_counter == 34);
 57 | 
 58 |     always @(posedge clk ) begin
 59 |         if(!rst_n)current_state <= S_INIT;
 60 |         else current_state <= next_state;
 61 |     end
 62 | 
 63 |     always @(*) begin
 64 |         case(current_state)
 65 |         S_INIT:next_state = S_READ_A;
 66 | 
 67 |         S_READ_A:next_state = (a_done)?S_DONE_A:S_READ_A;
 68 | 
 69 |         S_DONE_A:next_state = S_READ_B;
 70 | 
 71 |         S_READ_B:next_state = (b_done)?S_DONE_B:S_READ_B;
 72 | 
 73 |         S_DONE_B:next_state = S_DONE_B;
 74 |         default:next_state = S_INIT;
 75 |         endcase 
 76 |     end
 77 | 
 78 |     always @(posedge clk ) begin
 79 |         if(current_state == S_READ_A)
 80 |             A_counter <= A_counter + 1;
 81 |         else 
 82 |             A_counter <= 0;
 83 |     end
 84 | 
 85 |     always @(posedge clk ) begin
 86 |         if(current_state == S_READ_B)
 87 |             B_counter <= B_counter + 1;
 88 |         else 
 89 |             B_counter <= 16;
 90 |     end
 91 | 
 92 |     always @(posedge clk ) begin
 93 |         if(current_state == S_INIT || current_state == S_DONE_A)
 94 |             ram_addr <= 0;
 95 |         else if(current_state == S_READ_A)
 96 |             ram_addr <= A_counter;
 97 |         else if(current_state == S_READ_B)
 98 |             ram_addr <= B_counter;
 99 |         
100 |     end
101 |     //output logic
102 | 
103 |     always @(posedge clk ) begin
104 |         if(current_state == S_INIT)
105 |             A <= 0;
106 |         else if(current_state == S_READ_A && A_counter >= 2)
107 |             A[(A_counter-2)*8 +: 8] <= ram_data_o;
108 |     end
109 | 
110 |     always @(posedge clk ) begin
111 |         if(current_state == S_INIT)
112 |             B <= 0;
113 |         else if(current_state == S_READ_B && B_counter >= 18)
114 |             B[(B_counter - 18)*8 +: 8] <= ram_data_o;
115 |     end
116 | 
117 |     assign done = (current_state == S_DONE_B);
118 | 
119 | endmodule
120 | 


--------------------------------------------------------------------------------
/Lab_08/crack_partial.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 2021/07/21 22:05:48
  7 | // Design Name: 
  8 | // Module Name: crack_partial
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | module crack_partial(
 24 |     input clk,
 25 |     input rst_n,
 26 |     input [31:0]lower_bound,
 27 |     input [31:0]upper_bound,
 28 |     input [127:0]hash_answer,
 29 |     output [31:0]answer,
 30 |     output reg answer_found,
 31 |     output done);
 32 |    
 33 |     reg [31:0] i;
 34 | 
 35 |     //reg [0:127] hash_answer = 128'hE9982EC5CA981BD365603623CF4B2277;
 36 |     //reg [0:127] hash_answer=128'h7353b5dc1e564801ff4ddd40293b12ec;
 37 |     localparam S_IDLE = 0;
 38 |     localparam S_CHECK = 1;
 39 |     localparam S_CRACK = 2;
 40 |     localparam S_DONE = 3;
 41 |     reg [1:0] current_state, next_state;
 42 | 
 43 | 
 44 |     //md5 signals
 45 |     reg md5_rst_n;
 46 |     wire [63:0] md5_pwd;
 47 |     wire [127:0] md5_hash;
 48 |     wire md5_done;
 49 |     
 50 |     assign md5_pwd = {
 51 |         4'd0,i[28+:4],4'd0,i[24+:4],4'd0,i[20+:4],4'd0,i[16+:4],4'd0,i[12+:4],4'd0,i[8+:4],4'd0,i[4+:4],4'd0,i[0+:4]
 52 |         };
 53 | 
 54 |     md5 md5(
 55 |     .clk(clk),
 56 |     .reset_n(md5_rst_n),
 57 |     .pwd(md5_pwd),
 58 |     .hash(md5_hash),
 59 |     .done(md5_done)
 60 |     );
 61 | 
 62 |     //BCDAdder signals
 63 | 
 64 |     // reg [31:0] A;
 65 |     // reg [31:0] B;
 66 |     wire [31:0] BCD_Answer;
 67 | 
 68 |     BCDAdder BCDAdder(
 69 |      .A(i),
 70 |      .B(1),
 71 |      .Answer(BCD_Answer)
 72 |     );
 73 |     
 74 | 
 75 | 
 76 | 
 77 |     always @(posedge clk ) begin
 78 |         if(!rst_n)current_state<=S_IDLE;
 79 |         else current_state<=next_state;
 80 |     end
 81 | 
 82 |     always @(*) begin
 83 |         case(current_state)
 84 |         S_IDLE:next_state=S_CHECK;
 85 | 
 86 |         S_CHECK:next_state=(i>upper_bound)?S_DONE:S_CRACK;
 87 | 
 88 |         S_CRACK:begin
 89 |             if(md5_done && md5_hash != hash_answer) next_state = S_CHECK;
 90 |             else if(md5_done && md5_hash == hash_answer) next_state = S_DONE;
 91 |             else next_state = S_CRACK;
 92 |         end
 93 | 
 94 |         S_DONE:next_state= S_DONE;
 95 | 
 96 |         endcase
 97 |     end
 98 |     
 99 |     // always @(posedge clk ) begin
100 |     //     if (current_state == S_CRACK && next_state ==S_CHECK)begin
101 |     //         A<=i;
102 | 
103 |     //     end
104 |     // end
105 | 
106 |     always @(posedge clk ) begin
107 |         if(current_state == S_IDLE) i<=lower_bound;
108 |         else if(current_state == S_CRACK && next_state ==S_CHECK) i<=BCD_Answer;
109 |     end
110 | 
111 |     always @(posedge clk ) begin
112 |         if(current_state == S_CRACK && next_state == S_CHECK)  md5_rst_n <=0;
113 |         else if(current_state == S_IDLE && next_state == S_CHECK) md5_rst_n <= 0;
114 |         else md5_rst_n<=1;
115 |     end
116 | 
117 |     assign done =(current_state == S_DONE);
118 |     assign answer = i;
119 |     always @(posedge clk ) begin
120 |         if(current_state == S_IDLE) answer_found <= 0;
121 |         else if(current_state == S_CRACK && next_state == S_DONE) answer_found <= 1;
122 |     end
123 | 
124 | 
125 | 
126 | endmodule
127 | 


--------------------------------------------------------------------------------
/Lab_02/mmult_tb.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company:
  4 | // Engineer:
  5 | //
  6 | // Create Date: 2017/09/19 13:54:59
  7 | // Design Name:
  8 | // Module Name: mmult_tb
  9 | // Project Name:
 10 | // Target Devices:
 11 | // Tool Versions:
 12 | // Description:
 13 | //
 14 | // Dependencies:
 15 | //
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module mmult_tb; 
 23 |   reg clk = 1;
 24 |   reg reset_n = 1;
 25 |   
 26 |   always #5 clk = !clk; 
 27 |     event reset_trigger;
 28 |      initial begin
 29 |         forever begin
 30 |             @ (reset_trigger);
 31 |             @ (negedge clk);
 32 |             reset_n = 0;
 33 |             @ (negedge clk);
 34 |             reset_n = 1;
 35 |         end
 36 |     end
 37 |     
 38 |     //  End of simulation code for clock and reset_n signals
 39 |     // ---------------------------------------------------------------------
 40 |     
 41 |     // ---------------------------------------------------------------------
 42 |     // Begin of the testbench code
 43 |     //
 44 |     reg  [0:9*8-1]  A, B;   // 3x3 matrices
 45 |     wire [0:9*17-1] C;
 46 |     reg  enable;
 47 |     wire valid;
 48 |     
 49 |     reg  [0:9*17-1] result; // The output matrix, 3x3 entries of 17-bit numbers
 50 |     
 51 |     integer idx;
 52 |     
 53 |     // Instiantiates a 3x3 matrix multiplier
 54 |     mmult uut(
 55 |     .clk(clk),
 56 |     .reset_n(reset_n),
 57 |     .enable(enable),
 58 |     .A_mat(A),
 59 |     .B_mat(B),
 60 |     .valid(valid),
 61 |     .C_mat(C)
 62 |     );
 63 |     
 64 |     initial begin
 65 |         // Add stimulus here
 66 |         A = 72'h_4F_7E_57_0F_14_7B_21_4C_54;
 67 |         B = 72'h_17_28_3A_40_2F_33_6C_22_77;
 68 |         
 69 |         // Issue a reset signal
 70 |         #10 -> reset_trigger;
 71 |         
 72 |         // Wait 100 ns for global reset to finish
 73 |         #100 enable = 1;
 74 |     end
 75 |     
 76 |     // The matrices multiplication is done. Display the result.
 77 |     always @(*) begin
 78 |         @(posedge valid);
 79 |         
 80 |         // Wait one clock cycle so that the output is saved in the result[] register
 81 |         #10 $display ("\nMatrix A is:\n");
 82 |         
 83 |         for (idx = 0; idx < 9; idx = idx+1)
 84 |         begin
 85 |             $write (" %d ", A[idx*8 +: 8]);
 86 |             if (idx%3 == 2) $write("\n");
 87 |         end
 88 |         
 89 |         #10 $display ("\nMatrix B is:\n");
 90 |         
 91 |         for (idx = 0; idx < 9; idx = idx+1)
 92 |         begin
 93 |             $write (" %d ", B[idx*8 +: 8]);
 94 |             if (idx%3 == 2) $write("\n");
 95 |         end
 96 |         
 97 |         $display ("\nThe result of C = A x B is:\n");
 98 |         
 99 |         for (idx = 0; idx < 9; idx = idx+1)
100 |         begin
101 |             $write (" %d ", result[idx*17 +: 17]);
102 |             if (idx%3 == 2) $write("\n");
103 |         end
104 |         
105 |         $write("\n");
106 |     end
107 |     
108 |     // Save output C matrix in the result register when (valid == 1)
109 |     always @(posedge clk) begin
110 |         if (~reset_n)
111 |             result <= 0;
112 |         else if (valid)
113 |             result <= C;
114 |         else
115 |             result <= result;
116 |     end
117 |     //
118 |     //  End of the testbench code
119 |     // ---------------------------------------------------------------------
120 |     
121 | endmodule
122 | 


--------------------------------------------------------------------------------
/Lab_04/README.md:
--------------------------------------------------------------------------------
 1 | # Lab4 Tasks
 2 | 
 3 | ## In this lab, you will design a circuit to perform UART I/O. Your circuit will do the following things:
 4 | 
 5 | - Read two decimal number inputs from the UART/JTAG port connected to a PC terminal window. The number ranges from 0 to 65535.
 6 | - Compute the Greatest Common Divider (GCD) of the two numbers, and print the GCD to the UART terminal in hexadecimal format
 7 | 
 8 | 
 9 | ## UART Physical Layer
10 | - UART is a asynchronous transmission standard, thus, there is no common clock signal for synchronization
11 | - The most popular physical layer for the UART transmission line is the RS-232 standard
12 | <br/> -> Common baud rates for RS-232 signals range from 4800 bps to 115200 bps
13 | <br/> -> RS-232 voltages are (–15V, –3V) for ‘1’ and (3V, 15V) for ‘0’
14 | 
15 | ## UART Link Layer
16 | - The serial line is 1 when it is idle
17 | - The transmission starts with a start bit, which is 0, followed by data bits and an optional parity bit, and ends with stop bits, which are 1
18 | - The number of data bits can be 6, 7, or 8
19 | </br> -> The optional parity bit is used for error detection
20 | </br> -> For odd parity, it is set to 0 when the data bits have an odd number of 1’s
21 | </br> -> For even parity, it is set to 0 when the data bits have an even number of 1 's
22 | - The number of stop bits can be 1, 1.5, or 2
23 | 
24 | ## UART Controller
25 | - A UART controller performs the following tasks
26 | </br> -> Convert 8-bit parallel data to a serial bit stream and vice versa
27 | </br> -> Insert (or remove) start bit, parity bit, and stop bit for every 8 bits of data
28 | </br> -> Maintain a local clock for data transmission at correct rate
29 | - A UART controller includes a transmitter, a receiver, and a baud rate generator
30 | </br> -> The transmitter is essentially a special shift register that loads data in parallel and then shifts it out bit by bit at a specific rate
31 | </br> -> The receiver, on the other hand, shifts in data bit by bit and then reassembles the data
32 | 
33 | ## Out-of-Band Parameter Setting
34 | 
35 | - UART control parameters such as: bit-rate, #data bits, #stop bits, and types of parity-check must be set on both side of the serial transmission line before the communication begins
36 | - Implicit clocks must be generated on both sides for correct transmission
37 | </br> -> Bit rate per second (bps), or baud rate, is used to imply the clock on both end of the transmission line
38 | </br> -> Baud rates must be two’s multiples of 1200, e.g., 2400, 4800, 9600, ..., 115200, etc.
39 | </br> -> This clock is often called the baud rate generator
40 | 
41 | ## Module Specification
42 | ### Top module: lab4
43 | <pre><code>module lab4(
44 |   input clk,
45 |   input reset_n,
46 |   input [3:0] usr_btn,
47 |   output [3:0] usr_led,
48 |   input uart_rx,
49 |   output uart_tx
50 |   );</code></pre>
51 | ### Sub-module: gcd_calculator
52 | <pre><code>module gcd_calculator(
53 |   input clk,
54 |   input rst_n,
55 |   input enable,
56 |   input [15:0] A,
57 |   input [15:0] B,
58 |   output [15:0] answer,
59 |   output answer_available
60 |   );</code></pre>
61 | ### Sub-module: uart
62 | 
63 | 
64 | <pre><code>module uart(
65 |   input clk,              // The master clock for this module
66 |   input rst,              // Synchronous reset.
67 |   input rx,               // Incoming serial line
68 |   output tx,              // Outgoing serial line
69 |   input transmit,         // Signal to transmit
70 |   input [7:0] tx_byte,    // Byte to transmit
71 |   output received,        // Indicated that a byte has been received.
72 |   output [7:0] rx_byte,   // Byte received
73 |   output is_receiving,    // Low when receive line is idle.
74 |   output is_transmitting, // Low when transmit line is idle.
75 |   output recv_error       // Indicates error in receiving packet.
76 |   );</code></pre>
77 | 


--------------------------------------------------------------------------------
/Lab_03/lab3.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module lab3(input clk,
 4 |             input reset_n,
 5 |             input [3:0] usr_btn,
 6 |             output [3:0] usr_led);
 7 |     
 8 |     
 9 |     reg signed [3:0] number, reg_usr_led;
10 |     
11 |     reg[31:0] bouncing_counter, freq_counter, freq_threshold;
12 |     
13 |     reg[6:0] CURRENT_STATE, NEXT_STATE;
14 |     
15 |     localparam S_IDLE         = 7'd1 ;
16 |     localparam S_RST          = 7'd2 ;
17 |     localparam S_RESET_BOUNCE = 7'd4 ;
18 |     localparam S_NUM_UP       = 7'd8 ;
19 |     localparam S_NUM_DOWN     = 7'd16 ;
20 |     localparam S_FREQ_UP      = 7'd32 ;
21 |     localparam S_FREQ_DOWN    = 7'd64 ;
22 |     
23 |     localparam BOUNCING_WINDOW = 15_000_000 ;//0.15 second window
24 |     localparam PWM_100         = 1_000_000;//100hertz pwm pulse
25 |     localparam PWM_50          = 500_000;
26 |     localparam PWM_25          = 250_000;
27 |     localparam PWM_5           = 50_000;
28 |     
29 |     //FSM
30 |     always @(posedge clk, negedge reset_n) begin
31 |         if (!reset_n)CURRENT_STATE <= S_RST;
32 |         else CURRENT_STATE         <= NEXT_STATE;
33 |     end
34 |     
35 |     wire bouncing_counter_ends;
36 |     assign bouncing_counter_ends = (bouncing_counter == 0);
37 |     
38 |     always @(*) begin
39 |         
40 |         case(CURRENT_STATE)
41 |             S_IDLE:begin
42 |                 if (!reset_n)NEXT_STATE                                 = S_RST;
43 |                 else if (usr_btn[0] && bouncing_counter_ends)NEXT_STATE = S_NUM_DOWN;
44 |                 else if (usr_btn[1] && bouncing_counter_ends)NEXT_STATE = S_NUM_UP;
45 |                 else if (usr_btn[2] && bouncing_counter_ends)NEXT_STATE = S_FREQ_DOWN;
46 |                 else if (usr_btn[3] && bouncing_counter_ends)NEXT_STATE = S_FREQ_UP;
47 |                 else NEXT_STATE                                         = S_IDLE ;
48 |             end
49 |             S_RST:NEXT_STATE           = S_IDLE;
50 |             S_RESET_BOUNCE: NEXT_STATE = S_IDLE;
51 |             S_NUM_UP: NEXT_STATE       = S_RESET_BOUNCE;
52 |             S_NUM_DOWN: NEXT_STATE     = S_RESET_BOUNCE;
53 |             S_FREQ_UP: NEXT_STATE      = S_RESET_BOUNCE;
54 |             S_FREQ_DOWN: NEXT_STATE    = S_RESET_BOUNCE;
55 |             default: NEXT_STATE        = S_IDLE;
56 |         endcase
57 |     end
58 |     
59 |     always @(posedge clk) begin
60 |         if (CURRENT_STATE == S_RST)number      <= 0;
61 |         else if (CURRENT_STATE == S_NUM_UP && number <7) number <= number+1;
62 |         else if (CURRENT_STATE == S_NUM_DOWN && number >-8) number <= number -1;
63 |         
64 |     end
65 |     
66 |     always @(posedge clk) begin
67 |         if (CURRENT_STATE == S_RST || CURRENT_STATE == S_RESET_BOUNCE) bouncing_counter <= BOUNCING_WINDOW;
68 |         else if (bouncing_counter >0) bouncing_counter <= bouncing_counter-1;
69 |         
70 |     end
71 |     
72 |     always @(posedge clk) begin
73 |         if (CURRENT_STATE == S_RST || freq_counter == 0) freq_counter <= 1_000_000;
74 |         else if (freq_counter>0) freq_counter <= freq_counter-1;
75 |         
76 |     end
77 |     
78 |     always @(posedge clk) begin
79 |         if (CURRENT_STATE == S_RST) freq_threshold <= PWM_50;
80 |         else if (CURRENT_STATE == S_FREQ_UP && freq_threshold == PWM_5) freq_threshold <= PWM_25;
81 |         else if (CURRENT_STATE == S_FREQ_UP && freq_threshold <PWM_100) freq_threshold <= freq_threshold+PWM_25;
82 |         else if (CURRENT_STATE == S_FREQ_DOWN && freq_threshold == PWM_25) freq_threshold <= PWM_5;
83 |         else if (CURRENT_STATE == S_FREQ_DOWN && freq_threshold > PWM_25) freq_threshold <= freq_threshold-PWM_25;
84 |         
85 |     end
86 |     //output logic
87 | 
88 |     always @(posedge clk) begin
89 |         if(freq_counter>freq_threshold)reg_usr_led<=0;
90 |         else reg_usr_led<=number;
91 |         
92 |     end
93 |     
94 |     assign usr_led = reg_usr_led;
95 | endmodule
96 |     
97 | 


--------------------------------------------------------------------------------
/Lab_09/lab9.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | 
  3 | module lab9(input clk,
  4 |             input reset_n,
  5 |             input [3:0] usr_btn,
  6 |             output [3:0] usr_led,
  7 |             output LCD_RS,
  8 |             output LCD_RW,
  9 |             output LCD_E,
 10 |             output [3:0] LCD_D);
 11 |     
 12 |     localparam S_INIT = 3'b001;
 13 |     localparam S_CAL  = 3'b010;
 14 |     localparam S_SHOW = 3'b100;
 15 |     reg  [2:0]        P;
 16 |     reg  [2:0]        P_next;
 17 |     
 18 |     // declare system variables
 19 |     wire         btn_level, btn_pressed;
 20 |     reg          prev_btn_level;
 21 |     
 22 |     reg  [127:0] row_A;
 23 |     reg  [127:0] row_B;
 24 |     
 25 |     reg ld_rst_n;
 26 |     wire signed[21:0] ld_maxproduct;
 27 |     wire [$clog2(960):0] ld_maxproductlocation;
 28 |     wire ld_done;
 29 |     
 30 |     
 31 |     LCD_module lcd0(
 32 |     .clk(clk),
 33 |     .reset(~reset_n),
 34 |     .row_A(row_A),
 35 |     .row_B(row_B),
 36 |     .LCD_E(LCD_E),
 37 |     .LCD_RS(LCD_RS),
 38 |     .LCD_RW(LCD_RW),
 39 |     .LCD_D(LCD_D)
 40 |     );
 41 |     
 42 |     debounce btn_db0(
 43 |     .clk(clk),
 44 |     .btn_input(usr_btn[0]),
 45 |     .btn_output(btn_level)
 46 |     );
 47 |     
 48 |     load_data ld(
 49 |     .clk(clk),
 50 |     .rst_n(ld_rst_n),
 51 |     .usr_btn(usr_btn),
 52 |     .maxproduct_out(ld_maxproduct),
 53 |     .maxproductlocation_out(ld_maxproductlocation),
 54 |     .done(ld_done)
 55 |     );
 56 |     
 57 |     assign usr_led = 4'h00;//turn off the led
 58 |     
 59 |     //
 60 |     // Enable one cycle of btn_pressed per each button hit
 61 |     //
 62 |     always @(posedge clk) begin
 63 |         if (~reset_n)
 64 |             prev_btn_level <= 0;
 65 |         else
 66 |             prev_btn_level <= btn_level;
 67 |     end
 68 |     
 69 |     assign btn_pressed = (btn_level & ~prev_btn_level);
 70 |     
 71 |     // ------------------------------------------------------------------------
 72 |     // FSM of the main controller
 73 |     always @(posedge clk) begin
 74 |         if (~reset_n) begin
 75 |             P <= S_INIT;
 76 |         end
 77 |         else begin
 78 |             P <= P_next;
 79 |         end
 80 |     end
 81 |     
 82 |     always @(*) begin // FSM next-state logic
 83 |         case (P)
 84 |             S_INIT:P_next = (btn_pressed)?S_CAL:S_INIT;
 85 |             
 86 |             S_CAL:P_next = (ld_done)?S_SHOW:S_CAL;
 87 |             
 88 |             S_SHOW:P_next = S_SHOW;
 89 |             
 90 |             default:P_next = S_INIT;
 91 |         endcase
 92 |     end
 93 |     
 94 |     // End of the main controller
 95 |     // ------------------------------------------------------------------------
 96 |     always @(posedge clk) begin
 97 |         if (P == S_INIT)ld_rst_n <= 0;
 98 |         else ld_rst_n <= 1;
 99 |     end
100 |     // ------------------------------------------------------------------------
101 |     // The following code updates the 1602 LCD text messages.
102 |     
103 |     always @(posedge clk) begin
104 |         if (P == S_INIT)begin
105 |             row_A <= "Press BTN0 to do";
106 |             row_B <= "x-correlation...";
107 |         end
108 |         else if (P == S_SHOW)begin
109 |             row_A <= {"Max value ",
110 |             binarytoAscii(ld_maxproduct[21:20]),binarytoAscii(ld_maxproduct[16+:4]),binarytoAscii(ld_maxproduct[12+:4])
111 |             ,binarytoAscii(ld_maxproduct[8+:4]),binarytoAscii(ld_maxproduct[4+:4]),binarytoAscii(ld_maxproduct[0+:4])
112 |             };
113 |             row_B <= {"Max location ",
114 |             binarytoAscii(ld_maxproductlocation[9:8]),binarytoAscii(ld_maxproductlocation[7:4]),binarytoAscii(ld_maxproductlocation[3:0])
115 |             };
116 |         end
117 |     end
118 |             
119 |     function [7:0] binarytoAscii;
120 |         input [3:0] x;
121 |         begin
122 |             binarytoAscii = (x>9)?"A"+x-10:"0"+x;
123 |         end
124 |         
125 |     endfunction
126 |     
127 |     endmodule
128 | 


--------------------------------------------------------------------------------
/Lab_05/sieve_algorithm.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company:
  4 | // Engineer:
  5 | //
  6 | // Create Date: 2021/07/13 18:50:54
  7 | // Design Name:
  8 | // Module Name: sieve_algorithm
  9 | // Project Name:
 10 | // Target Devices:
 11 | // Tool Versions:
 12 | // Description:
 13 | //
 14 | // Dependencies:
 15 | //
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | module sieve_algorithm(input clk,
 24 |                        input rst,
 25 |                        output [1719:0] primes,
 26 |                        output answer_available);
 27 |     
 28 |     parameter UPPER_BOUND      = 1023 ;
 29 |     parameter HALF_UPPER_BOUND = 511;
 30 |     parameter WORD_WIDTH       = 10;
 31 |     
 32 |     localparam S_INIT           = 0;
 33 |     localparam S_PRE_SEIVE      = 1;
 34 |     localparam S_PRE_SEIVE_WAIT = 5;
 35 |     localparam S_SEIVE          = 2;
 36 |     localparam S_COLLECT        = 3;
 37 |     localparam S_DONE           = 4;
 38 |     reg[2:0] current_state, next_state;
 39 |     
 40 |     
 41 |     
 42 |     reg [10:0] in_counter;
 43 |     reg [10:0] out_counter;
 44 |     reg [1023:0] candidates;
 45 |     reg [1719:0] reg_prime_out;
 46 |     reg[10:0] i,j;
 47 |     
 48 |     always @(posedge clk) begin
 49 |         if (rst)current_state <= S_INIT;
 50 |         else current_state    <= next_state;
 51 |     end
 52 |     
 53 |     always @(*) begin
 54 |         case(current_state)
 55 |             S_INIT:next_state = S_PRE_SEIVE;
 56 |             S_PRE_SEIVE:begin
 57 |                 if (sieve_done) next_state                            = S_COLLECT;
 58 |                 else if (candidates[i]&&(i+i)<UPPER_BOUND) next_state = S_SEIVE;
 59 |                 else next_state                                       = S_PRE_SEIVE;
 60 |             end
 61 |             
 62 |             S_SEIVE: next_state = (j+i>UPPER_BOUND)?S_PRE_SEIVE:S_SEIVE;
 63 |             
 64 |             S_COLLECT:next_state = (collect_done)?S_DONE:S_COLLECT;
 65 |             S_DONE:next_state    = S_DONE;
 66 |             default:next_state   = S_INIT;
 67 |         endcase
 68 |     end
 69 |     
 70 |     
 71 |     assign sieve_done   = (i == 512);
 72 |     assign collect_done = (in_counter >= 1023);
 73 |     
 74 |     
 75 |     always @(posedge clk) begin
 76 |         if (current_state == S_INIT) i <= 1;
 77 |         else if (current_state == S_PRE_SEIVE) i <= i+1;
 78 |     end
 79 |     
 80 |     always @(posedge clk) begin
 81 |         if (current_state == S_INIT) j <= 0;
 82 |         else if (current_state == S_PRE_SEIVE) j <= i+i;
 83 |         else if (current_state == S_SEIVE) j <= j+i-1;
 84 |         else j <= 0;
 85 |     end
 86 |     
 87 |     always@(posedge clk)begin
 88 |         if (current_state == S_INIT) candidates <= {{1022{1'b1}},2'b00};
 89 |         else if (current_state == S_SEIVE)begin
 90 |         if (j<UPPER_BOUND)candidates[j] = 0;
 91 |     end
 92 |     end
 93 |     
 94 |     
 95 |     assign found_prime = (candidates[in_counter]);
 96 |     
 97 |     always @(posedge clk) begin
 98 |         if (current_state == S_INIT)in_counter <= 0;
 99 |         else if (current_state == S_COLLECT) in_counter <= in_counter+1;
100 |     end
101 |     
102 |     always @(posedge clk) begin
103 |         if (current_state == S_INIT)out_counter <= 0;
104 |         else if (current_state == S_COLLECT && found_prime)out_counter <= out_counter+WORD_WIDTH;
105 |     end
106 |     
107 |     always @(posedge clk) begin
108 |         if (current_state == S_INIT)reg_prime_out <= {1720{1'd0}};
109 |         else if (current_state == S_COLLECT && found_prime) reg_prime_out[out_counter +:10]<= in_counter;
110 |     end
111 |     
112 |     
113 |     
114 |     assign primes = reg_prime_out;
115 |     
116 |     assign answer_available = (current_state == S_DONE);
117 |     
118 | endmodule
119 | 


--------------------------------------------------------------------------------
/Lab_10/vga_sync.v:
--------------------------------------------------------------------------------
  1 | //############################################################################
  2 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  3 | //   (C) Copyright Laboratory System Integration and Silicon Implementation
  4 | //   All Right Reserved
  5 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  6 | //
  7 | //   2012 DLAB Course
  8 | //   Lab08      : PING_PONG_GAME
  9 | //   Author     : Szu-Chi, Chung (phonchi@si2lab.org) (v1.0)
 10 | //                
 11 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 12 | //
 13 | //   File Name   : vga_sync.v
 14 | //   Module Name : vga_sync
 15 | //   Release version : v1.0 (Release Date: Apr-2012)
 16 | //
 17 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 18 | //############################################################################
 19 | module vga_sync(
 20 |   input clk, 
 21 |   input reset,
 22 |   output wire oHS, 
 23 |   output wire oVS, 
 24 |   output wire visible, 
 25 |   output wire p_tick,
 26 |   output wire [9:0] pixel_x, 
 27 |   output wire [9:0] pixel_y
 28 |   );
 29 | 
 30 |    // VGA 640-by-480 sync parameters
 31 |    parameter HD = 640; // horizontal display area
 32 |    parameter HF = 48 ; // h. front (left) border
 33 |    parameter HB = 16 ; // h. back (right) border
 34 |    parameter HR = 96 ; // h. retrace
 35 |    parameter VD = 480; // vertical display area
 36 |    parameter VF = 10;  // v. front (top) border
 37 |    parameter VB = 33;  // v. back (bottom) border
 38 |    parameter VR = 2;   // v. retrace
 39 | 
 40 |    // mod-2 counter
 41 |    reg mod2_reg;
 42 |    wire mod2_next;
 43 |    // sync counters
 44 |    reg [9:0] h_count_reg, h_count_next;
 45 |    reg [9:0] v_count_reg, v_count_next;
 46 |    // output buffer
 47 |    reg v_sync_reg, h_sync_reg;
 48 |    wire v_sync_next, h_sync_next;
 49 |    // status signal
 50 |    wire h_end, v_end, pixel_tick;
 51 | 
 52 |    // registers
 53 |    always @(posedge clk) begin
 54 |       if (reset)
 55 |          begin
 56 |             mod2_reg <= 1'b0;
 57 |             v_count_reg <= 0;
 58 |             h_count_reg <= 0;
 59 |             v_sync_reg <= 1'b0;
 60 |             h_sync_reg <= 1'b0;
 61 |          end
 62 |       else
 63 |          begin
 64 |             mod2_reg <= mod2_next;
 65 |             v_count_reg <= v_count_next;
 66 |             h_count_reg <= h_count_next;
 67 |             v_sync_reg <= v_sync_next;
 68 |             h_sync_reg <= h_sync_next;
 69 |          end
 70 | 	end
 71 |    // mod-2 circuit to generate 25 MHz enable tick
 72 |    assign mod2_next = ~mod2_reg;
 73 |    assign pixel_tick = mod2_reg;
 74 | 
 75 |    // end of horizontal counter (799)
 76 |    assign h_end = (h_count_reg==(HD+HF+HB+HR-1));
 77 |    // end of vertical counter (524)
 78 |    assign v_end = (v_count_reg==(VD+VF+VB+VR-1));
 79 | 
 80 |    // next-state logic of mod-800 horizontal sync counter
 81 |    always @(*) begin
 82 |       if (pixel_tick) begin  // 25 MHz pulse
 83 |          if (h_end)
 84 |             h_count_next = 0;
 85 |          else
 86 |             h_count_next = h_count_reg + 1;
 87 |       end
 88 | 	  else
 89 |          h_count_next = h_count_reg;
 90 | 	end
 91 |    // next-state logic of mod-525 vertical sync counter
 92 |    always @(*) begin
 93 |       if (pixel_tick & h_end) begin // 25 MHz pulse
 94 |          if (v_end)
 95 |             v_count_next = 0;
 96 |          else
 97 |             v_count_next = v_count_reg + 1;
 98 | 	  end
 99 |       else
100 |          v_count_next = v_count_reg;
101 | 	end
102 |    // horizontal and vertical sync, buffered to avoid glitch
103 |    // h_sync_next asserted between 656 and 751
104 |    assign h_sync_next = (h_count_reg>=(HD+HB) &&
105 |                          h_count_reg<=(HD+HB+HR-1));
106 |    // vh_sync_next asserted between 490 and 491
107 |    assign v_sync_next = (v_count_reg>=(VD+VB) &&
108 |                          v_count_reg<=(VD+VB+VR-1));
109 | 
110 |    // video on/off
111 |    assign visible = (h_count_reg<HD) && (v_count_reg<VD);
112 | 
113 |    // output
114 |    assign oHS = h_sync_reg;
115 |    assign oVS = v_sync_reg;
116 |    assign pixel_x = h_count_reg;
117 |    assign pixel_y = v_count_reg;
118 |    assign p_tick = pixel_tick;
119 | 
120 | endmodule
121 | 


--------------------------------------------------------------------------------
/Lab_08/lab8.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 2021/07/19 20:53:20
  7 | // Design Name: 
  8 | // Module Name: lab8
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module lab8(
 23 |   input clk,
 24 |   input reset_n,
 25 |   input [3:0] usr_btn,
 26 |   output [3:0] usr_led,
 27 |   output LCD_RS,
 28 |   output LCD_RW,
 29 |   output LCD_E,
 30 |   output [3:0] LCD_D
 31 | );
 32 | 
 33 | // turn off all the LEDs
 34 | assign usr_led = 4'b0000;
 35 | 
 36 | wire btn_level, btn_pressed;
 37 | reg prev_btn_level;
 38 | reg [127:0] row_A = "Press BTN3 to   "; // Initialize the text of the first row. 
 39 | reg [127:0] row_B = "show a message.."; // Initialize the text of the second row.
 40 | 
 41 | localparam S_INIT = 3'b001;
 42 | localparam S_CRACK = 3'b010;
 43 | localparam S_SHOW = 3'b100;
 44 | 
 45 | parameter MEASURE_CLOCK_CYCLES=1 ;
 46 | 
 47 | 
 48 | reg [2:0] current_state,next_state;
 49 | 
 50 | 
 51 | LCD_module lcd0(
 52 |   .clk(clk),
 53 |   .reset(~reset_n),
 54 |   .row_A(row_A),
 55 |   .row_B(row_B),
 56 |   .LCD_E(LCD_E),
 57 |   .LCD_RS(LCD_RS),
 58 |   .LCD_RW(LCD_RW),
 59 |   .LCD_D(LCD_D)
 60 | );
 61 |     
 62 | debounce btn_db0(
 63 |   .clk(clk),
 64 |   .btn_input(usr_btn[3]),
 65 |   .btn_output(btn_level)
 66 | );
 67 | 
 68 | reg ct_rst_n;
 69 | 
 70 | wire [31:0] ct_answer;
 71 | wire ct_done;
 72 | 
 73 | wire [63:0]display_ct_answer;
 74 | assign display_ct_answer={
 75 |  "0"+ct_answer[28+:4],"0"+ct_answer[24+:4],"0"+ct_answer[20+:4],"0"+ct_answer[16+:4],
 76 |  "0"+ct_answer[12+:4],"0"+ct_answer[ 8+:4],"0"+ct_answer[ 4+:4],"0"+ct_answer[ 0+:4]};
 77 | 
 78 | 
 79 | reg [$clog2(MEASURE_CLOCK_CYCLES):0] counter;
 80 | 
 81 | reg [31:0] ct_time_BCD_Adder;
 82 | 
 83 | wire [31:0] BCDAdder_Answer;
 84 | 
 85 | wire [63:0]display_ct_time;
 86 | assign display_ct_time = {
 87 |   "0"+ct_time_BCD_Adder[28+:4],"0"+ct_time_BCD_Adder[24+:4],"0"+ct_time_BCD_Adder[20+:4],"0"+ct_time_BCD_Adder[16+:4],
 88 |   "0"+ct_time_BCD_Adder[12+:4],"0"+ct_time_BCD_Adder[ 8+:4],"0"+ct_time_BCD_Adder[ 4+:4],"0"+ct_time_BCD_Adder[ 0+:4]};
 89 | 
 90 | crack_top ct(
 91 |   .clk(clk),
 92 |   .rst_n(ct_rst_n),
 93 |   .answer(ct_answer),
 94 |   .done(ct_done)
 95 | );
 96 | always @(posedge clk ) begin
 97 |   if(current_state == S_INIT) ct_rst_n=0;
 98 |   else ct_rst_n=1;
 99 | end
100 | 
101 | BCDAdder BCDAdder(
102 |   .A(ct_time_BCD_Adder),
103 |   .B(1),
104 |   .Answer(BCDAdder_Answer)
105 | );
106 | 
107 | always @(posedge clk ) begin
108 |   if(current_state ==S_INIT) counter <=0;
109 |   else if(current_state == S_CRACK) counter<=(counter ==MEASURE_CLOCK_CYCLES)?0:counter+1;
110 |   
111 | end
112 | always @(posedge clk ) begin
113 |   if(current_state ==S_INIT)ct_time_BCD_Adder<=0;
114 |   else if(current_state == S_CRACK && counter ==MEASURE_CLOCK_CYCLES) ct_time_BCD_Adder<=BCDAdder_Answer;
115 |   
116 | end
117 |     
118 | always @(posedge clk) begin
119 |   if (~reset_n)
120 |     prev_btn_level <= 1;
121 |   else
122 |     prev_btn_level <= btn_level;
123 | end
124 | 
125 | assign btn_pressed = (btn_level == 1 && prev_btn_level == 0);
126 | 
127 | always @(posedge clk ) begin
128 |   if(!reset_n)current_state <=S_INIT;
129 |   else current_state<=next_state;
130 | end
131 | 
132 | always @(*) begin
133 |   case(current_state)
134 |   S_INIT:next_state=(btn_pressed)?S_CRACK:S_INIT;
135 | 
136 |   S_CRACK:next_state=(ct_done)?S_SHOW:S_CRACK;
137 | 
138 |   S_SHOW:next_state=S_SHOW;
139 |   endcase
140 | 
141 | end
142 | 
143 | always @(posedge clk) begin
144 |   if (current_state == S_INIT) begin
145 |     // Initialize the text when the user hit the reset button
146 |     row_A <= "Press BTN3 to   ";
147 |     row_B <= "crack password!!";
148 |   end else if (current_state ==S_CRACK) begin
149 |     row_A <= "Cracking........";
150 |     row_B <= "Please wait!    ";
151 |   end
152 |   else if(current_state == S_SHOW)begin
153 |     row_A <= {"Passwd: ",display_ct_answer};
154 |     row_B <= {"Time:",display_ct_time,"0ns"};
155 |   end
156 |   else begin
157 |     row_A <= "ERROR!!!ERROR!!!";
158 |     row_B <= "ERROR!!!ERROR!!!";
159 |   end
160 | end
161 | 
162 | endmodule
163 | 


--------------------------------------------------------------------------------
/CODE_OF_CONDUCT.md:
--------------------------------------------------------------------------------
  1 | # Contributor Covenant Code of Conduct
  2 | 
  3 | ## Our Pledge
  4 | 
  5 | We as members, contributors, and leaders pledge to make participation in our
  6 | community a harassment-free experience for everyone, regardless of age, body
  7 | size, visible or invisible disability, ethnicity, sex characteristics, gender
  8 | identity and expression, level of experience, education, socio-economic status,
  9 | nationality, personal appearance, race, religion, or sexual identity
 10 | and orientation.
 11 | 
 12 | We pledge to act and interact in ways that contribute to an open, welcoming,
 13 | diverse, inclusive, and healthy community.
 14 | 
 15 | ## Our Standards
 16 | 
 17 | Examples of behavior that contributes to a positive environment for our
 18 | community include:
 19 | 
 20 | * Demonstrating empathy and kindness toward other people
 21 | * Being respectful of differing opinions, viewpoints, and experiences
 22 | * Giving and gracefully accepting constructive feedback
 23 | * Accepting responsibility and apologizing to those affected by our mistakes,
 24 |   and learning from the experience
 25 | * Focusing on what is best not just for us as individuals, but for the
 26 |   overall community
 27 | 
 28 | Examples of unacceptable behavior include:
 29 | 
 30 | * The use of sexualized language or imagery, and sexual attention or
 31 |   advances of any kind
 32 | * Trolling, insulting or derogatory comments, and personal or political attacks
 33 | * Public or private harassment
 34 | * Publishing others' private information, such as a physical or email
 35 |   address, without their explicit permission
 36 | * Other conduct which could reasonably be considered inappropriate in a
 37 |   professional setting
 38 | 
 39 | ## Enforcement Responsibilities
 40 | 
 41 | Community leaders are responsible for clarifying and enforcing our standards of
 42 | acceptable behavior and will take appropriate and fair corrective action in
 43 | response to any behavior that they deem inappropriate, threatening, offensive,
 44 | or harmful.
 45 | 
 46 | Community leaders have the right and responsibility to remove, edit, or reject
 47 | comments, commits, code, wiki edits, issues, and other contributions that are
 48 | not aligned to this Code of Conduct, and will communicate reasons for moderation
 49 | decisions when appropriate.
 50 | 
 51 | ## Scope
 52 | 
 53 | This Code of Conduct applies within all community spaces, and also applies when
 54 | an individual is officially representing the community in public spaces.
 55 | Examples of representing our community include using an official e-mail address,
 56 | posting via an official social media account, or acting as an appointed
 57 | representative at an online or offline event.
 58 | 
 59 | ## Enforcement
 60 | 
 61 | Instances of abusive, harassing, or otherwise unacceptable behavior may be
 62 | reported to the community leaders responsible for enforcement at
 63 | hankshyu@gmail.com.
 64 | All complaints will be reviewed and investigated promptly and fairly.
 65 | 
 66 | All community leaders are obligated to respect the privacy and security of the
 67 | reporter of any incident.
 68 | 
 69 | ## Enforcement Guidelines
 70 | 
 71 | Community leaders will follow these Community Impact Guidelines in determining
 72 | the consequences for any action they deem in violation of this Code of Conduct:
 73 | 
 74 | ### 1. Correction
 75 | 
 76 | **Community Impact**: Use of inappropriate language or other behavior deemed
 77 | unprofessional or unwelcome in the community.
 78 | 
 79 | **Consequence**: A private, written warning from community leaders, providing
 80 | clarity around the nature of the violation and an explanation of why the
 81 | behavior was inappropriate. A public apology may be requested.
 82 | 
 83 | ### 2. Warning
 84 | 
 85 | **Community Impact**: A violation through a single incident or series
 86 | of actions.
 87 | 
 88 | **Consequence**: A warning with consequences for continued behavior. No
 89 | interaction with the people involved, including unsolicited interaction with
 90 | those enforcing the Code of Conduct, for a specified period of time. This
 91 | includes avoiding interactions in community spaces as well as external channels
 92 | like social media. Violating these terms may lead to a temporary or
 93 | permanent ban.
 94 | 
 95 | ### 3. Temporary Ban
 96 | 
 97 | **Community Impact**: A serious violation of community standards, including
 98 | sustained inappropriate behavior.
 99 | 
100 | **Consequence**: A temporary ban from any sort of interaction or public
101 | communication with the community for a specified period of time. No public or
102 | private interaction with the people involved, including unsolicited interaction
103 | with those enforcing the Code of Conduct, is allowed during this period.
104 | Violating these terms may lead to a permanent ban.
105 | 
106 | ### 4. Permanent Ban
107 | 
108 | **Community Impact**: Demonstrating a pattern of violation of community
109 | standards, including sustained inappropriate behavior,  harassment of an
110 | individual, or aggression toward or disparagement of classes of individuals.
111 | 
112 | **Consequence**: A permanent ban from any sort of public interaction within
113 | the community.
114 | 
115 | ## Attribution
116 | 
117 | This Code of Conduct is adapted from the [Contributor Covenant][homepage],
118 | version 2.0, available at
119 | https://www.contributor-covenant.org/version/2/0/code_of_conduct.html.
120 | 
121 | Community Impact Guidelines were inspired by [Mozilla's code of conduct
122 | enforcement ladder](https://github.com/mozilla/diversity).
123 | 
124 | [homepage]: https://www.contributor-covenant.org
125 | 
126 | For answers to common questions about this code of conduct, see the FAQ at
127 | https://www.contributor-covenant.org/faq. Translations are available at
128 | https://www.contributor-covenant.org/translations.
129 | 


--------------------------------------------------------------------------------
/Lab_05/lab5.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: Dept. of CS, National Chiao Tung University
  4 | // Engineer: Chun-Jen Tsai, hankshyu
  5 | //
  6 | // Create Date: 2017/10/16 14:21:33
  7 | // Design Name:
  8 | // Module Name: lab5
  9 | // Project Name:
 10 | // Target Devices: Xilinx FPGA @ 100MHz
 11 | // Tool Versions:
 12 | // Description:
 13 | //
 14 | // Dependencies:
 15 | //
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module lab5(input clk,
 23 |             input reset_n,
 24 |             input [3:0] usr_btn,
 25 |             output [3:0] usr_led,
 26 |             output LCD_RS,
 27 |             output LCD_RW,
 28 |             output LCD_E,
 29 |             output [3:0] LCD_D);
 30 |     
 31 |     // turn off all the LEDs
 32 |     assign usr_led = 4'b0000;
 33 |     
 34 |     reg [2:0] current_state, next_state;
 35 |     localparam [2:0]S_INIT            = 0;
 36 |     localparam [2:0]S_CALCULATE_PRIME = 1;
 37 |     localparam [2:0]S_DISPLAY_UP      = 2;
 38 |     localparam [2:0]S_DISPLAY_DOWN    = 3;
 39 |     localparam [2:0]S_UP_TO_DOWN      = 4;
 40 |     localparam [2:0]S_DOWN_TO_UP      = 5;
 41 |     
 42 |     parameter DISPLAY_DELAY = 70_000_000;
 43 |     reg [$clog2(DISPLAY_DELAY):0] display_delay_counter;
 44 |     
 45 |     wire btn_level;
 46 |     reg prev_btn_level;
 47 |     wire btn_pressed;
 48 |     
 49 |     reg [127:0] row_A;
 50 |     reg [127:0] row_B;
 51 |     reg [9:0] A_pointer;
 52 |     reg [9:0] A_pointer_next;
 53 |     reg [9:0] B_pointer;
 54 |     reg [9:0] B_pointer_next;
 55 |     reg [7:0] A_number;
 56 |     reg [7:0] B_number;
 57 |     
 58 |     
 59 |     wire prime_answer_available;
 60 |     
 61 |     reg prime_collect_enable;
 62 |     wire prime_available;
 63 |  
 64 | 
 65 |     reg [1719:0] reg_prime;
 66 |     wire [1719:0] prime_collect_out;
 67 |     
 68 |     LCD_module lcd0(
 69 |     .clk(clk),
 70 |     .reset(~reset_n),
 71 |     .row_A(row_A),
 72 |     .row_B(row_B),
 73 |     .LCD_E(LCD_E),
 74 |     .LCD_RS(LCD_RS),
 75 |     .LCD_RW(LCD_RW),
 76 |     .LCD_D(LCD_D)
 77 |     );
 78 |     
 79 |     debounce btn_db0(
 80 |     .clk(clk),
 81 |     .btn_input(usr_btn[3]),
 82 |     .btn_output(btn_level)
 83 |     );
 84 |     
 85 |     sieve_algorithm sieve_algorithm(
 86 |     .clk(clk),
 87 |     .rst(~reset_n),
 88 |     .primes(prime_collect_out),
 89 |     .answer_available(prime_answer_available)
 90 |     );
 91 | 
 92 | 
 93 |     always @(*) reg_prime = prime_collect_out;
 94 |     
 95 |     always @(posedge clk) begin
 96 |         if (~reset_n)
 97 |             prev_btn_level <= 1;
 98 |         else
 99 |             prev_btn_level <= btn_level;
100 |     end
101 |     
102 |     assign btn_pressed = (btn_level == 1 && prev_btn_level == 0);
103 | 
104 |     wire [10:0]reg_prime_index_A,reg_prime_index_B;
105 |     assign reg_prime_index_A=10*(A_number-1);
106 |     assign reg_prime_index_B=10*(B_number-1);
107 |    
108 |     always @(posedge clk) begin
109 |         row_A <= {"Prime #",binaryToAscii(.binary(A_number[7:4])),binaryToAscii(.binary(A_number[3:0]))," is "
110 |         ,binaryToAscii(.binary(reg_prime[reg_prime_index_A+8 +:2])),binaryToAscii(.binary(reg_prime[reg_prime_index_A+4 +:4])),
111 |         binaryToAscii(.binary(reg_prime[reg_prime_index_A +:4]))};
112 |     end
113 | 
114 |     always @(posedge clk) begin
115 |         row_B <= {"Prime #",binaryToAscii(.binary(B_number[7:4])),binaryToAscii(.binary(B_number[3:0]))," is "
116 |         ,binaryToAscii(.binary(reg_prime[reg_prime_index_B+8 +:2])),binaryToAscii(.binary(reg_prime[reg_prime_index_B+4 +:4])),
117 |         binaryToAscii(.binary(reg_prime[reg_prime_index_B +:4]))};
118 |     end
119 |     
120 |     always @(posedge clk) begin
121 |         if (!reset_n)current_state <= S_INIT;
122 |         else current_state         <= next_state;
123 |     end
124 |     
125 |     always @(*) begin
126 |         case(current_state)
127 |             S_INIT:next_state = S_CALCULATE_PRIME;
128 |             
129 |             S_CALCULATE_PRIME:next_state = (prime_answer_available)?S_DISPLAY_UP:S_CALCULATE_PRIME;
130 |             
131 |             S_DISPLAY_UP:next_state      = (btn_pressed)?S_UP_TO_DOWN:S_DISPLAY_UP;
132 |             S_UP_TO_DOWN:next_state      = S_DISPLAY_DOWN;
133 |             S_DISPLAY_DOWN:next_state    = (btn_pressed)?S_DOWN_TO_UP:S_DISPLAY_DOWN;
134 |             S_DOWN_TO_UP:next_state      = S_DISPLAY_UP;
135 |             default:next_state           = S_INIT;
136 |         endcase
137 |         
138 |     end
139 | 
140 |     always @(posedge clk) begin
141 |         if (current_state == S_DISPLAY_UP || current_state == S_DISPLAY_DOWN)
142 |             display_delay_counter      <= (display_delay_counter>DISPLAY_DELAY)? 0 :display_delay_counter+1;
143 |         else display_delay_counter <= 0;
144 |         
145 |     end
146 |     wire display_delay_counter_expire;
147 |     assign display_delay_counter_expire = (display_delay_counter == DISPLAY_DELAY);
148 |     
149 |     always@(posedge clk) begin
150 |         if (current_state == S_CALCULATE_PRIME) A_number <= 1;
151 |         else if (display_delay_counter_expire && current_state == S_DISPLAY_UP) A_number <= B_number;
152 |         else if (display_delay_counter_expire && current_state == S_DISPLAY_DOWN) A_number <= (A_number == 1)?8'hAC:A_number-1;
153 | 
154 |     end
155 |     
156 |     always@(posedge clk) begin
157 |         if (current_state == S_CALCULATE_PRIME) B_number <= 3;
158 |         else if (display_delay_counter_expire && current_state == S_DISPLAY_UP) B_number <= (B_number == 8'hAC)?1:B_number+1;
159 |         else if (display_delay_counter_expire && current_state == S_DISPLAY_DOWN) B_number <= A_number;
160 | 
161 |     end
162 | 
163 |     function [7:0] binaryToAscii;
164 |         input [7:0] binary;
165 | 
166 |         binaryToAscii=(binary>=10)?binary-10+"A":binary+"0";
167 |         
168 |     endfunction
169 |   
170 | endmodule
171 |     
172 | 


--------------------------------------------------------------------------------
/Lab_02/mmult.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | 
  3 | 
  4 | module mmult#(parameter MATRIX_SIZE = 3,
  5 |               parameter INPUT_UNIT_LEN = 8,
  6 |               parameter OUTPUT_UNIT_LEN = INPUT_UNIT_LEN*2+1)
  7 |              (input clk,                                      // Clock signal
  8 |               input reset_n,                                  // Reset signal (negative logic)
  9 |               input enable,                                   // Activation signal for matrix multiplication
 10 |               input [0:9*INPUT_UNIT_LEN-1] A_mat,             // A matrix
 11 |               input [0:9*INPUT_UNIT_LEN-1] B_mat,             // B matrix
 12 |               output valid,                                   // Signals that the output is valid to read
 13 |               output wire [0:9*OUTPUT_UNIT_LEN-1] C_mat);     // The result of A x B
 14 |     
 15 |     reg valid_store;
 16 |     reg [0:9*INPUT_UNIT_LEN-1] A_store,B_store;
 17 |     reg [0:9*OUTPUT_UNIT_LEN-1] C_store;
 18 |     
 19 |     reg[1:0] idx;
 20 |     reg[1:0] current_state,next_state;
 21 |     localparam S_IDLE = 0, S_ADD = 1, S_OUT = 2;
 22 |     
 23 |     integer i;
 24 |     
 25 |     //FSM
 26 |     always @(posedge clk,negedge reset_n) begin
 27 |         if (!reset_n)current_state                <= S_IDLE;
 28 |         else if (reset_n && enable) current_state <= next_state;
 29 |         else current_state                        <= S_IDLE;
 30 |         
 31 |     end
 32 |     
 33 |     wire add_done;
 34 |     assign add_done = (idx == 0);
 35 |     
 36 |     always @(*) begin
 37 |         case(current_state)
 38 |             S_IDLE: next_state = (enable)? S_ADD : S_IDLE;
 39 |             S_ADD: next_state  = (add_done)? S_OUT:S_ADD;
 40 |             S_OUT: next_state  = S_IDLE;
 41 |             default:next_state = S_IDLE;
 42 |             
 43 |         endcase
 44 |     end
 45 |     
 46 |     
 47 |     
 48 |     always @(posedge clk) begin
 49 |         if (!reset_n)idx <= 0;
 50 |         else if (enable && current_state == S_IDLE) idx <= MATRIX_SIZE-1;
 51 |         else if (enable && current_state == S_ADD) idx <= idx-1;
 52 |         else idx <= idx;
 53 |     end
 54 |     
 55 |     always @(posedge clk) begin
 56 |         if (!reset_n)A_store <= 0;
 57 |         else if (enable && current_state == S_IDLE) A_store<= A_mat;
 58 |         else A_store <= A_store;
 59 |     end
 60 |     
 61 |     always @(posedge clk) begin
 62 |         if (!reset_n)B_store <= 0;
 63 |         else if (enable && current_state == S_IDLE) B_store <= B_mat;
 64 |         else B_store <= B_store;
 65 |     end
 66 |     integer  k;
 67 |     always @(posedge clk) begin
 68 |         if (!reset_n)C_store <= 0;
 69 |         else if (enable && current_state == S_ADD) begin
 70 |         for (k = 0; k<3; k = k+1) begin
 71 |             if ((2-k) == idx)begin
 72 |                 for(i = 0;i<MATRIX_SIZE;i = i+1)begin
 73 |                     C_store[OUTPUT_UNIT_LEN*(3*k+i)+:OUTPUT_UNIT_LEN] <= add_sum(
 74 |                     .a1(A_store[(3*k+0)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
 75 |                     .a2(A_store[(3*k+1)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
 76 |                     .a3(A_store[(3*k+2)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
 77 |                     .b1(B_store[INPUT_UNIT_LEN*(0+i)+:INPUT_UNIT_LEN]),
 78 |                     .b2(B_store[INPUT_UNIT_LEN*(3+i)+:INPUT_UNIT_LEN]),
 79 |                     .b3(B_store[INPUT_UNIT_LEN*(6+i)+:INPUT_UNIT_LEN])
 80 |                     );
 81 |                     
 82 |                 end
 83 |                 
 84 |             end
 85 |             
 86 |         end
 87 |         
 88 |         //case(idx)
 89 |         
 90 |         // 2'd2:begin
 91 |         //   for(i = 0;i<MATRIX_SIZE;i = i+1)begin
 92 |         //     C_store[OUTPUT_UNIT_LEN*(0+i)+:OUTPUT_UNIT_LEN] <= add_sum(
 93 |         //       .a1(A_store[(0+0)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
 94 |         //       .a2(A_store[(0+1)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
 95 |         //       .a3(A_store[(0+2)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
 96 |         //       .b1(B_store[INPUT_UNIT_LEN*(0+i)+:INPUT_UNIT_LEN]),
 97 |         //       .b2(B_store[INPUT_UNIT_LEN*(3+i)+:INPUT_UNIT_LEN]),
 98 |         //       .b3(B_store[INPUT_UNIT_LEN*(6+i)+:INPUT_UNIT_LEN])
 99 |         //     );
100 |         
101 |         //   end
102 |         // end
103 |         // 2'd1:begin
104 |         //   for(i = 0;i<MATRIX_SIZE;i = i+1)begin
105 |         //     C_store[OUTPUT_UNIT_LEN*(3+i)+:OUTPUT_UNIT_LEN] <= add_sum(
106 |         //       .a1(A_store[(3+0)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
107 |         //       .a2(A_store[(3+1)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
108 |         //       .a3(A_store[(3+2)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
109 |         //       .b1(B_store[INPUT_UNIT_LEN*(0+i)+:INPUT_UNIT_LEN]),
110 |         //       .b2(B_store[INPUT_UNIT_LEN*(3+i)+:INPUT_UNIT_LEN]),
111 |         //       .b3(B_store[INPUT_UNIT_LEN*(6+i)+:INPUT_UNIT_LEN])
112 |         //     );
113 |         
114 |         //   end
115 |         // end
116 |         // 2'd0:begin
117 |         //   for(i = 0;i<MATRIX_SIZE;i = i+1)begin
118 |         //     C_store[OUTPUT_UNIT_LEN*(6+i)+:OUTPUT_UNIT_LEN] <= add_sum(
119 |         //       .a1(A_store[(6+0)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
120 |         //       .a2(A_store[(6+1)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
121 |         //       .a3(A_store[(6+2)*INPUT_UNIT_LEN+:INPUT_UNIT_LEN]),
122 |         //       .b1(B_store[INPUT_UNIT_LEN*(0+i)+:INPUT_UNIT_LEN]),
123 |         //       .b2(B_store[INPUT_UNIT_LEN*(3+i)+:INPUT_UNIT_LEN]),
124 |         //       .b3(B_store[INPUT_UNIT_LEN*(6+i)+:INPUT_UNIT_LEN])
125 |         //     );
126 |         
127 |         //   end
128 |         // end
129 |         
130 |         //default:C_store <= C_store;
131 |         
132 |         //endcase
133 |         
134 |     end
135 |     else C_store <= C_store;
136 |     
137 |     end
138 |     
139 |     function [OUTPUT_UNIT_LEN-1:0] add_sum;
140 |         input [INPUT_UNIT_LEN-1:0] a1 ,a2 ,a3, b1, b2, b3;
141 |         
142 |         reg [OUTPUT_UNIT_LEN-2:0] temp1, temp2, temp3;
143 |         begin
144 |             temp1   = a1*b1;
145 |             temp2   = a2*b2;
146 |             temp3   = a3*b3;
147 |             add_sum = temp1+temp2+temp3;
148 |         end
149 |     endfunction
150 |     
151 |     
152 |     always @(posedge clk) begin
153 |         if (!reset_n)valid_store <= 0;
154 |         else if (enable && current_state == S_OUT) valid_store <= 1;
155 |         else valid_store <= 0;
156 |     end
157 |     
158 |     //output
159 |     assign C_mat = C_store;
160 |     assign valid = valid_store;
161 |     
162 | endmodule
163 | 


--------------------------------------------------------------------------------
/Lab_09/load_data.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company:
  4 | // Engineer:
  5 | //
  6 | // Create Date: 2021/07/24 15:08:05
  7 | // Design Name:
  8 | // Module Name: load_data
  9 | // Project Name:
 10 | // Target Devices:
 11 | // Tool Versions:
 12 | // Description:
 13 | //
 14 | // Dependencies:
 15 | //
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | module load_data(input clk,
 24 |                  input rst_n,
 25 |                  input [3:0] usr_btn,
 26 |                  output signed[21:0] maxproduct_out,
 27 |                  output [$clog2(960):0] maxproductlocation_out, output done);
 28 |     
 29 |     
 30 |     reg signed[21:0] maxproduct;
 31 |     reg [$clog2(960):0] maxproductlocation;
 32 |     reg signed [21:0] productfg;
 33 |     reg signed [7:0] reg_f [63:0];
 34 |     reg signed [7:0] reg_g [63:0];
 35 |     
 36 |     
 37 |     reg [$clog2(64):0] g_counter;
 38 |     reg [$clog2(64):0] f_counter;
 39 |     reg [$clog2(1024):0] shift_counter;
 40 |     reg [$clog2(64):0] add_counter;
 41 |     
 42 |     localparam S_IDLE       = 0;
 43 |     localparam S_LOAD_G     = 1;
 44 |     localparam S_DONE_G     = 2;
 45 |     localparam S_LOAD_F     = 3;
 46 |     localparam S_DONE_F     = 4;
 47 |     localparam S_SHIFT_ADDR = 5;
 48 |     localparam S_SHIFT      = 6;
 49 |     localparam S_ADD        = 7;
 50 |     localparam S_COMP       = 8;
 51 |     localparam S_DONE       = 9;
 52 |     reg [3:0] current_state, next_state;
 53 |     
 54 |     //sram related variable
 55 |     reg  [11:0] sample_addr;
 56 |     wire [10:0] sram_addr;
 57 |     wire [7:0]  data_in;
 58 |     wire [7:0]  data_out;
 59 |     wire        sram_we, sram_en;
 60 |     
 61 |     sram sram(
 62 |     .clk(clk),
 63 |     .we(sram_we),
 64 |     .en(sram_en),
 65 |     .addr(sram_addr),
 66 |     .data_i(data_in),
 67 |     .data_o(data_out)
 68 |     );
 69 |     
 70 |     assign sram_we   = usr_btn[3];
 71 |     assign sram_addr = sample_addr;
 72 |     assign sram_en   = (current_state == S_LOAD_G || current_state == S_LOAD_F);
 73 |     assign data_in   = 0;
 74 |     
 75 |     assign g_state_ok     = (g_counter == 64);
 76 |     assign f_state_ok     = (f_counter == 64);
 77 |     assign add_ok         = (add_counter == 63);
 78 |     assign shift_state_ok = (shift_counter == 1024);
 79 |     
 80 |     always @(posedge clk) begin
 81 |         if (!rst_n)current_state <= S_IDLE;
 82 |         else current_state       <= next_state;
 83 |     end
 84 |     
 85 |     always @(*) begin
 86 |         case(current_state)
 87 |             S_IDLE:next_state = S_LOAD_G;
 88 |             
 89 |             S_LOAD_G:next_state = (g_state_ok)?S_DONE_G:S_LOAD_G;
 90 |             
 91 |             S_DONE_G:next_state = S_LOAD_F;
 92 |             
 93 |             S_LOAD_F:next_state = (f_state_ok)?S_DONE_F:S_LOAD_F;
 94 |             
 95 |             S_DONE_F:next_state = S_SHIFT_ADDR;
 96 |             
 97 |             S_SHIFT_ADDR:next_state = S_SHIFT;
 98 |             
 99 |             S_SHIFT:next_state = S_ADD;
100 |             
101 |             S_ADD:next_state = (add_ok)?S_COMP:S_ADD;
102 |             
103 |             S_COMP:next_state = (shift_state_ok)?S_DONE:S_SHIFT_ADDR;
104 |             
105 |             S_DONE:next_state = S_DONE;
106 |             
107 |             default: next_state = S_IDLE;
108 |             
109 |         endcase
110 |     end
111 |     
112 |     always @(posedge clk) begin
113 |         if (current_state == S_IDLE) g_counter <= 0;
114 |         else if (current_state == S_LOAD_G) g_counter <= g_counter+1;
115 |     end
116 |     
117 |     always @(posedge clk) begin
118 |         if (current_state == S_IDLE) f_counter <= 0;
119 |         else if (current_state == S_LOAD_F) f_counter <= f_counter+1;
120 |     end
121 |     
122 |     always @(posedge clk) begin
123 |         if (current_state == S_IDLE)shift_counter<= 64;
124 |         else if (current_state == S_COMP) shift_counter <= shift_counter+1;
125 |     end
126 |     
127 |     always @(posedge clk) begin
128 |         if (current_state == S_SHIFT) add_counter <= 0;
129 |         else if (current_state == S_ADD) add_counter <= add_counter+1;
130 |     end
131 |     
132 |     always @(posedge clk) begin
133 |         if (current_state == S_IDLE) sample_addr <= 1024;
134 |         else if (current_state == S_DONE_G)sample_addr <= 0;
135 |         else if (current_state == S_DONE_F)sample_addr <= 64;
136 |         else if (current_state == S_LOAD_G || current_state == S_LOAD_F) sample_addr <= sample_addr+1;
137 |         else if (current_state == S_SHIFT_ADDR) sample_addr <= shift_counter;
138 |     end
139 |     
140 |     always @(posedge clk) begin
141 |         if (current_state == S_SHIFT) productfg<= 0;
142 |         else if (current_state == S_ADD) productfg <= productfg+(reg_f[add_counter] * reg_g[add_counter]);
143 |     end
144 |     
145 |     always @(posedge clk) begin
146 |         if (current_state == S_IDLE)begin
147 |             maxproduct         <= 0;
148 |             maxproductlocation <= 0;
149 |             
150 |         end
151 |         else if (current_state == S_COMP)begin
152 |             if (shift_counter == 64 || productfg > maxproduct)begin
153 |                 maxproduct         <= productfg;
154 |                 maxproductlocation <= shift_counter-64;
155 |             end
156 |         end
157 |             
158 |     end
159 |               
160 |     reg [6:0] m;
161 |     always @(posedge clk) begin
162 |         if (current_state == S_IDLE)begin
163 |             for(m = 0; m<64; m = m+1)begin
164 |                 reg_g[m] <= 0;
165 |             end
166 |         end
167 |         else if (current_state == S_LOAD_G && g_counter != 0)begin
168 |             reg_g[g_counter-1] <= data_out;
169 |         end
170 |     end
171 |     reg [6:0] n,q;
172 |     
173 |     always @(posedge clk) begin
174 |         if (current_state == S_IDLE)begin
175 |             for(n = 0; n<64; n = n+1)begin
176 |                 reg_f[n] <= 0;
177 |             end
178 |         end
179 |         else if (current_state == S_LOAD_F && f_counter != 0)begin
180 |             reg_f[f_counter-1] <= data_out;
181 |         end
182 |         else if (current_state == S_SHIFT)begin
183 |             for(q = 1; q<64; q = q+1)begin
184 |                 reg_f[q-1] <= reg_f[q];
185 |             end
186 |             reg_f[63] <= data_out;
187 |         end
188 |     end
189 |                             
190 |     //output
191 |     
192 |     assign done                   = (current_state == S_DONE);
193 |     assign maxproduct_out         = maxproduct;
194 |     assign maxproductlocation_out = maxproductlocation;
195 |     
196 | endmodule
197 |                             
198 | 


--------------------------------------------------------------------------------
/Lab_05/LCD_module.v:
--------------------------------------------------------------------------------
  1 | /* ------------------------------------------------------------------- */
  2 | /*  Modified from a Xilinx 1602 LCD controller by Chun-Jen Tsai.       */
  3 | /*  The timing of the original Xilinx controller does not work for the */
  4 | /*  majority of the inexpensive 1602 LCD modules in Taiwan.            */
  5 | /* ------------------------------------------------------------------- */
  6 | /*  The clock input 'clk' to the 1602 LCD controller shall be 100 MHz. */
  7 | /*  The controller only uses the 4-bit command mode to control the     */
  8 | /*  1602 LCD module. The output ports LCD_D[3:0] shall be physically   */
  9 | /*  connected to the module pins D7 ~ D4, respectively.                */
 10 | /*                                                           9/28/2016 */
 11 | /* ------------------------------------------------------------------- */
 12 | 
 13 | module LCD_module(
 14 |   input clk,
 15 |   input reset,
 16 |   input [127:0] row_A,
 17 |   input [127:0] row_B,
 18 |   output LCD_E,
 19 |   output LCD_RS,     // register select 
 20 |   output LCD_RW,     // read/write the lcd module 
 21 |   output [3:0] LCD_D // 1602 lcd data
 22 |   );
 23 | 
 24 | reg lcd_initialized = 0;
 25 | reg [25:0] init_count;
 26 | reg [3:0] init_d, icode;
 27 | reg init_e, init_rs, init_rw;
 28 | 
 29 | reg [24:0] text_count;
 30 | reg [3:0] text_d, tcode;
 31 | reg text_e, text_rs, text_rw;
 32 | 
 33 | // Signal drivers for the 1602 LCD module
 34 | assign LCD_E  = (lcd_initialized)? text_e  : init_e;
 35 | assign LCD_RS = (lcd_initialized)? text_rs : init_rs;
 36 | assign LCD_RW = (lcd_initialized)? text_rw : init_rw;
 37 | assign LCD_D  = (lcd_initialized)? text_d  : init_d;
 38 | 
 39 | // The initialization sequence (Run once at boot up).
 40 | always @(posedge clk) begin
 41 |   if (reset) begin
 42 |     lcd_initialized <= 0;
 43 |     init_count <= 0;
 44 |     init_d  <= 4'h0;
 45 |     init_e  <= 0;
 46 |     init_rs <= 0;
 47 |     init_rw <= 1;
 48 |   end
 49 |   else if (!lcd_initialized) begin
 50 |     init_count <= init_count + 1;
 51 | 
 52 |     // Enable the LCD when bit 21 of the init_count is 1
 53 |     // The command clock frequency is 100MHz/(2^22) = 23.84 Hz
 54 |     init_e  <= init_count[21];
 55 |     init_rs <= 0;
 56 |     init_rw <= 0;
 57 |     init_d  <= icode;
 58 | 
 59 |     case (init_count[25:22])
 60 |      0: icode <= 4'h3; // Power-on init sequence. It cause the LCD
 61 |      1: icode <= 4'h3; // to flicker if there are characters on the
 62 |      2: icode <= 4'h3; // display. So only do this once at the
 63 |      3: icode <= 4'h2; // begining.
 64 | 
 65 |     // Function Set. Set to 4-bit mode, 2 text lines, and 5x8 text
 66 |      4: icode <= 4'h2; // Upper nibble 0010
 67 |      5: icode <= 4'h8; // Lower nibble 1000
 68 | 
 69 |     // Entry Mode Set. Upper nibble: 0000, lower nibble: 0 1 I/D S
 70 |     // upper nibble: I/D bit (Incr 1, Decr 0), S bit (Shift 1, no shift 0)
 71 |      6: icode <= 4'h0; // Upper nibble 0000
 72 |      7: icode <= 4'h6; // Lower nibble 0110: Incr, Shift disabled
 73 | 
 74 |     // Display On/Off. Upper nibble: 0000, lower nibble 1 D C B
 75 |     // D: 1, display on, 0 off
 76 |     // C: 1, show cursor, 0 don't
 77 |     // B: 1, cursor blinks (if shown), 0 don't blink (if shown)
 78 |      8: icode <= 4'h0; // Upper nibble 0000
 79 |      9: icode <= 4'hC; // Lower nibble 1100
 80 | 
 81 |     // Clear Display. Upper nibble 0000, lower nibble 0001
 82 |     10: icode <= 4'h0; // Upper nibble 0000
 83 |     11: icode <= 4'h1; // Lower nibble 0001
 84 | 
 85 |     // We should read the Busy Flag and Address after each command
 86 |     // to determine whether we can move on to the next command.
 87 |     // However, our init counter runs quite slowly that most 1602
 88 |     // LCDs should have plenty of time to finish each command.
 89 |     default: lcd_initialized <= 1;
 90 |     endcase
 91 |   end
 92 | end
 93 | 
 94 | // The text refreshing sequence.
 95 | always @(posedge clk) begin
 96 |   if (reset) begin
 97 |     text_count <= 0;
 98 |     text_d  <= 4'h0;
 99 |     text_e  <= 0;
100 |     text_rs <= 0;
101 |     text_rw <= 0;
102 |   end
103 |   else if (lcd_initialized) begin
104 |     text_count <= (text_count[24:18] < 68)? text_count + 1 : 0;
105 | 
106 |     // Refresh (enable) the LCD when bit 17 of the text_count is 1
107 |     // The command clock frequency is 100MHz/(2^18) = 381.47 Hz
108 |     // The screen refresh frequency is 381.47Hz/68 = 5.60 Hz
109 |     text_e  <= text_count[17];
110 |     text_rs <= 1;
111 |     text_rw <= 0;
112 |     text_d <= tcode;
113 | 
114 |     case (text_count[24:18])
115 |     // Position the cursor to the start of the first line.
116 |     // Upper nibble is 1???, where ??? is the highest 3 bits of
117 |     // the RAM address to move the cursor to.
118 |     // Lower nibble is the lower 4 bits of the RAM address.
119 |      0: { text_rs, text_rw, tcode } <= 6'b001000;
120 |      1: { text_rs, text_rw, tcode } <= 6'b000000;
121 | 
122 |     // Print chararters by writing data to DD RAM (or CG RAM).
123 |     // The cursor will advance to the right end of the screen.
124 |      2: tcode <= row_A[127:124];
125 |      3: tcode <= row_A[123:120];
126 |      4: tcode <= row_A[119:116];
127 |      5: tcode <= row_A[115:112];
128 |      6: tcode <= row_A[111:108];
129 |      7: tcode <= row_A[107:104];
130 |      8: tcode <= row_A[103:100];
131 |      9: tcode <= row_A[99 :96 ];
132 |     10: tcode <= row_A[95 :92 ];
133 |     11: tcode <= row_A[91 :88 ];
134 |     12: tcode <= row_A[87 :84 ];
135 |     13: tcode <= row_A[83 :80 ];
136 |     14: tcode <= row_A[79 :76 ];
137 |     15: tcode <= row_A[75 :72 ];
138 |     16: tcode <= row_A[71 :68 ];
139 |     17: tcode <= row_A[67 :64 ];
140 |     18: tcode <= row_A[63 :60 ];
141 |     19: tcode <= row_A[59 :56 ];
142 |     20: tcode <= row_A[55 :52 ];
143 |     21: tcode <= row_A[51 :48 ];
144 |     22: tcode <= row_A[47 :44 ];
145 |     23: tcode <= row_A[43 :40 ];
146 |     24: tcode <= row_A[39 :36 ];
147 |     25: tcode <= row_A[35 :32 ];
148 |     26: tcode <= row_A[31 :28 ];
149 |     27: tcode <= row_A[27 :24 ];
150 |     28: tcode <= row_A[23 :20 ];
151 |     29: tcode <= row_A[19 :16 ];
152 |     30: tcode <= row_A[15 :12 ];
153 |     31: tcode <= row_A[11 :8  ];
154 |     32: tcode <= row_A[7  :4  ];
155 |     33: tcode <= row_A[3  :0  ];
156 | 
157 |     // position the cursor to the start of the 2nd line
158 |     34: { text_rs, text_rw, tcode } <= 6'b001100;
159 |     35: { text_rs, text_rw, tcode } <= 6'b000000;
160 | 
161 |     // Print chararters by writing data to DD RAM (or CG RAM).
162 |     // The cursor will advance to the right end of the screen.
163 |     36: tcode <= row_B[127:124];
164 |     37: tcode <= row_B[123:120];
165 |     38: tcode <= row_B[119:116];
166 |     39: tcode <= row_B[115:112];
167 |     40: tcode <= row_B[111:108];
168 |     41: tcode <= row_B[107:104];
169 |     42: tcode <= row_B[103:100];
170 |     43: tcode <= row_B[99 :96 ];
171 |     44: tcode <= row_B[95 :92 ];
172 |     45: tcode <= row_B[91 :88 ];
173 |     46: tcode <= row_B[87 :84 ];
174 |     47: tcode <= row_B[83 :80 ];
175 |     48: tcode <= row_B[79 :76 ];
176 |     49: tcode <= row_B[75 :72 ];
177 |     50: tcode <= row_B[71 :68 ];
178 |     51: tcode <= row_B[67 :64 ];
179 |     52: tcode <= row_B[63 :60 ];
180 |     53: tcode <= row_B[59 :56 ];
181 |     54: tcode <= row_B[55 :52 ];
182 |     55: tcode <= row_B[51 :48 ];
183 |     56: tcode <= row_B[47 :44 ];
184 |     57: tcode <= row_B[43 :40 ];
185 |     58: tcode <= row_B[39 :36 ];
186 |     59: tcode <= row_B[35 :32 ];
187 |     60: tcode <= row_B[31 :28 ];
188 |     61: tcode <= row_B[27 :24 ];
189 |     62: tcode <= row_B[23 :20 ];
190 |     63: tcode <= row_B[19 :16 ];
191 |     64: tcode <= row_B[15 :12 ];
192 |     65: tcode <= row_B[11 :8  ];
193 |     66: tcode <= row_B[7  :4  ];
194 |     67: tcode <= row_B[3  :0  ];
195 |     default: { text_rs, text_rw, tcode } <= 6'h10; // default to read mode.
196 |     endcase
197 |   end
198 | end
199 | 
200 | endmodule
201 | 
202 | 


--------------------------------------------------------------------------------
/Lab_07/matrix_cal.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: hankshyu
  5 | // 
  6 | // Create Date: 2021/07/29 16:57:08
  7 | // Design Name: 
  8 | // Module Name: matrix_cal
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | module matrix_cal(
 24 |     input clk,
 25 |     input rst_n,
 26 |     input [3:0] btn,
 27 |     output [287:0] answer,
 28 |     output done);
 29 | 
 30 |     localparam [2:0] S_INIT = 0;
 31 |     localparam [2:0] S_READ_MEM = 1;
 32 |     localparam [2:0] S_OUTER_LOOP = 2;
 33 |     localparam [2:0] S_INNER_LOOP = 3;
 34 |     localparam [2:0] S_DONE = 4;
 35 |     reg [2:0] current_state, next_state;
 36 | 
 37 |     integer i,j;
 38 |     reg [2:0] inner_counter;
 39 |     reg [2:0] outer_counter;
 40 | 
 41 |     wire [4:0] A_index [3:0];
 42 |     wire [4:0] B_index [3:0];
 43 | 
 44 |     wire [7:0] A_index_pointing_num[3:0];
 45 |     wire [7:0] B_index_pointing_num[3:0];
 46 |     reg [15:0] multiply [3:0];
 47 |     reg [17:0] half_add_answer_1;
 48 |     reg [17:0] half_add_answer_2;
 49 |     reg [17:0] add_answer;
 50 |     
 51 |     reg [17:0] reg_answer[15:0];
 52 | 
 53 |     //memory realted parameters
 54 |     wire [127:0] read_mem_A;
 55 |     wire [127:0] read_mem_B;
 56 |     reg [7:0] reg_A [15:0];
 57 |     reg [7:0] reg_B [15:0];
 58 | 
 59 |     read_mem read_mem(
 60 |         .clk(clk),
 61 |         .rst_n(read_mem_rst_n),
 62 |         .btn(btn[3]),
 63 |         .A(read_mem_A),
 64 |         .B(read_mem_B),
 65 |         .done(read_mem_done)
 66 |     );
 67 |     assign read_mem_rst_n = (current_state!=S_INIT);
 68 |     
 69 |     always @(posedge clk ) begin
 70 |         if(!rst_n)current_state <= S_INIT;
 71 |         else current_state <= next_state;
 72 |     end
 73 | 
 74 |     always @(*) begin
 75 |         case(current_state)
 76 |         S_INIT:next_state=S_READ_MEM;
 77 | 
 78 |         S_READ_MEM:next_state = (read_mem_done)?S_OUTER_LOOP:S_READ_MEM;
 79 | 
 80 |         S_OUTER_LOOP:next_state=(outer_loop_end)?S_DONE:S_INNER_LOOP;
 81 | 
 82 |         S_INNER_LOOP:next_state=(inner_loop_end)?S_OUTER_LOOP:S_INNER_LOOP;
 83 | 
 84 |         S_DONE:next_state=S_DONE;
 85 |         default: next_state = S_INIT;
 86 |         endcase
 87 |     end
 88 |     genvar m;
 89 |     generate
 90 |         for(m=0;m<4;m=m+1)begin
 91 |             assign A_index_pointing_num[m] = reg_A[A_index[m]];
 92 |         end
 93 |     endgenerate
 94 | 
 95 |     genvar n;
 96 |     generate
 97 |         for(n=0; n<4 ;n=n+1)begin
 98 |             assign B_index_pointing_num[n] = reg_B[B_index[n]];
 99 |         end
100 |     endgenerate
101 | 
102 | 
103 |     integer k;
104 |     always @(posedge clk ) begin
105 |         if(current_state == S_INNER_LOOP)
106 |             for (k = 0; k<=3; k=k+1) begin
107 |                 multiply[k] <= A_index_pointing_num[k]*B_index_pointing_num[k];
108 |             end
109 |     end
110 | 
111 |     always @(posedge clk ) begin
112 |         if(current_state == S_INNER_LOOP)
113 |             half_add_answer_1 <= multiply[0] + multiply[1];
114 |     end
115 | 
116 |     always @(posedge clk ) begin
117 |         if(current_state == S_INNER_LOOP)
118 |             half_add_answer_2 <= multiply[2] + multiply[3];
119 |     end
120 |     
121 |     always @(posedge clk ) begin
122 |         if(current_state == S_INNER_LOOP)
123 |             add_answer <= half_add_answer_1 + half_add_answer_2;
124 |     end
125 | 
126 |     genvar g;
127 |     generate
128 |         for(g=0; g<4; g=g+1)begin
129 |             assign A_index[g] = (outer_counter<<2) + g; 
130 |         end
131 |     endgenerate 
132 | 
133 |     genvar h;
134 |     generate
135 |         for(h=0; h<4 ;h=h+1)begin
136 |             assign B_index[h] = (h<<2) + inner_counter;
137 |         end
138 |     endgenerate
139 | 
140 | 
141 |     assign outer_loop_end = (outer_counter==4);
142 |     assign inner_loop_end = (inner_counter==7);
143 | 
144 |     always @(posedge clk ) begin
145 |         if(current_state == S_READ_MEM) 
146 |             outer_counter <= 0;
147 |         else if(current_state ==S_INNER_LOOP && next_state == S_OUTER_LOOP)
148 |             outer_counter <= outer_counter + 1;
149 |     end
150 | 
151 |     always @(posedge clk ) begin
152 |         if(current_state == S_OUTER_LOOP)
153 |             inner_counter <= 0;
154 |         else if(current_state == S_INNER_LOOP)
155 |             inner_counter <= inner_counter + 1;
156 | 
157 |     end
158 | 
159 |     always @(posedge clk ) begin
160 |         if(current_state == S_INIT)
161 |             for (i=0; i<16 ;i=i+1)begin
162 |                 reg_A[i] <= 0;
163 |             end
164 |         else if(current_state == S_READ_MEM)begin
165 |             
166 |             reg_A[ 0] <= read_mem_A[  0+:8];
167 |             reg_A[ 1] <= read_mem_A[ 32+:8];
168 |             reg_A[ 2] <= read_mem_A[ 64+:8];
169 |             reg_A[ 3] <= read_mem_A[ 96+:8];
170 |             reg_A[ 4] <= read_mem_A[  8+:8];
171 |             reg_A[ 5] <= read_mem_A[ 40+:8];
172 |             reg_A[ 6] <= read_mem_A[ 72+:8];
173 |             reg_A[ 7] <= read_mem_A[104+:8];
174 |             reg_A[ 8] <= read_mem_A[ 16+:8];
175 |             reg_A[ 9] <= read_mem_A[ 48+:8];
176 |             reg_A[10] <= read_mem_A[ 80+:8];
177 |             reg_A[11] <= read_mem_A[112+:8];
178 |             reg_A[12] <= read_mem_A[ 24+:8];
179 |             reg_A[13] <= read_mem_A[ 56+:8];
180 |             reg_A[14] <= read_mem_A[ 88+:8];
181 |             reg_A[15] <= read_mem_A[120+:8];
182 |         end
183 | 
184 |     end
185 | 
186 |     always @(posedge clk ) begin
187 |         if(current_state == S_INIT)
188 |             for (j=0; j<16 ;j=j+1)begin
189 |                 reg_B[j] <= 0;
190 |             end
191 |         else if(current_state == S_READ_MEM)begin
192 | 
193 |             reg_B[ 0] <= read_mem_B[  0+:8];
194 |             reg_B[ 1] <= read_mem_B[ 32+:8];
195 |             reg_B[ 2] <= read_mem_B[ 64+:8];
196 |             reg_B[ 3] <= read_mem_B[ 96+:8];
197 |             reg_B[ 4] <= read_mem_B[  8+:8];
198 |             reg_B[ 5] <= read_mem_B[ 40+:8];
199 |             reg_B[ 6] <= read_mem_B[ 72+:8];
200 |             reg_B[ 7] <= read_mem_B[104+:8];
201 |             reg_B[ 8] <= read_mem_B[ 16+:8];
202 |             reg_B[ 9] <= read_mem_B[ 48+:8];
203 |             reg_B[10] <= read_mem_B[ 80+:8];
204 |             reg_B[11] <= read_mem_B[112+:8];
205 |             reg_B[12] <= read_mem_B[ 24+:8];
206 |             reg_B[13] <= read_mem_B[ 56+:8];
207 |             reg_B[14] <= read_mem_B[ 88+:8];
208 |             reg_B[15] <= read_mem_B[120+:8];
209 | 
210 |         end
211 | 
212 |     end
213 |     //output logic
214 |     wire [3:0] answer_write_idx;
215 |     assign answer_write_idx = (outer_counter<<2) + inner_counter - 2;
216 |     integer a;
217 |     always @(posedge clk ) begin
218 |         if(current_state == S_INIT)
219 |             for(a=0;a<16;a=a+1)
220 |                 reg_answer[a] <= 0;
221 |         else if(current_state == S_INNER_LOOP && outer_counter ==3 &&inner_counter ==6)
222 |             reg_answer[15] <= add_answer;
223 |         else if(current_state == S_INNER_LOOP && inner_counter >= 3 && inner_counter <= 6)
224 |             reg_answer[answer_write_idx -1] <= add_answer;
225 |     end
226 | 
227 |     assign done = (current_state == S_DONE);
228 |     assign answer = 
229 |     {
230 |         reg_answer[15],reg_answer[14],reg_answer[13],reg_answer[12],
231 |         reg_answer[11],reg_answer[10],reg_answer[ 9],reg_answer[ 8],
232 |         reg_answer[ 7],reg_answer[ 6],reg_answer[ 5],reg_answer[ 4],
233 |         reg_answer[ 3],reg_answer[ 2],reg_answer[ 1],reg_answer[ 0]
234 |     };
235 | 
236 | endmodule
237 | 


--------------------------------------------------------------------------------
/Lab_09/LCD_module.v:
--------------------------------------------------------------------------------
  1 | /* ------------------------------------------------------------------- */
  2 | /*  Modified from a Xilinx 1602 LCD controller by Chun-Jen Tsai.       */
  3 | /*  The timing of the original Xilinx controller does not work for the */
  4 | /*  majority of the inexpensive 1602 LCD modules in Taiwan.            */
  5 | /* ------------------------------------------------------------------- */
  6 | /*  The clock input 'clk' to the 1602 LCD controller shall be 100 MHz. */
  7 | /*  The controller only uses the 4-bit command mode to control the     */
  8 | /*  1602 LCD module. The output ports LCD_D[3:0] shall be physically   */
  9 | /*  connected to the module pins D7 ~ D4, respectively.                */
 10 | /*                                                           9/28/2016 */
 11 | /* ------------------------------------------------------------------- */
 12 | 
 13 | module LCD_module(
 14 |   input clk,
 15 |   input reset,
 16 |   input [127:0] row_A,
 17 |   input [127:0] row_B,
 18 |   output LCD_E,
 19 |   output LCD_RS,     // register select 
 20 |   output LCD_RW,     // read/write the lcd module 
 21 |   output [3:0] LCD_D // 1602 lcd data
 22 |   );
 23 | 
 24 | reg lcd_initialized = 0;
 25 | reg [25:0] init_count;
 26 | reg [3:0] init_d, icode;
 27 | reg init_e, init_rs, init_rw;
 28 | 
 29 | reg [24:0] text_count;
 30 | reg [3:0] text_d, tcode;
 31 | reg text_e, text_rs, text_rw;
 32 | 
 33 | // Signal drivers for the 1602 LCD module
 34 | assign LCD_E  = (lcd_initialized)? text_e  : init_e;
 35 | assign LCD_RS = (lcd_initialized)? text_rs : init_rs;
 36 | assign LCD_RW = (lcd_initialized)? text_rw : init_rw;
 37 | assign LCD_D  = (lcd_initialized)? text_d  : init_d;
 38 | 
 39 | // The initialization sequence (Run once at boot up).
 40 | always @(posedge clk) begin
 41 |   if (reset) begin
 42 |     lcd_initialized <= 0;
 43 |     init_count <= 0;
 44 |     init_d  <= 4'h0;
 45 |     init_e  <= 0;
 46 |     init_rs <= 0;
 47 |     init_rw <= 1;
 48 |   end
 49 |   else if (!lcd_initialized) begin
 50 |     init_count <= init_count + 1;
 51 | 
 52 |     // Enable the LCD when bit 21 of the init_count is 1
 53 |     // The command clock frequency is 100MHz/(2^22) = 23.84 Hz
 54 |     init_e  <= init_count[21];
 55 |     init_rs <= 0;
 56 |     init_rw <= 0;
 57 |     init_d  <= icode;
 58 | 
 59 |     case (init_count[25:22])
 60 |      0: icode <= 4'h3; // Power-on init sequence. It cause the LCD
 61 |      1: icode <= 4'h3; // to flicker if there are characters on the
 62 |      2: icode <= 4'h3; // display. So only do this once at the
 63 |      3: icode <= 4'h2; // begining.
 64 | 
 65 |     // Function Set. Set to 4-bit mode, 2 text lines, and 5x8 text
 66 |      4: icode <= 4'h2; // Upper nibble 0010
 67 |      5: icode <= 4'h8; // Lower nibble 1000
 68 | 
 69 |     // Entry Mode Set. Upper nibble: 0000, lower nibble: 0 1 I/D S
 70 |     // upper nibble: I/D bit (Incr 1, Decr 0), S bit (Shift 1, no shift 0)
 71 |      6: icode <= 4'h0; // Upper nibble 0000
 72 |      7: icode <= 4'h6; // Lower nibble 0110: Incr, Shift disabled
 73 | 
 74 |     // Display On/Off. Upper nibble: 0000, lower nibble 1 D C B
 75 |     // D: 1, display on, 0 off
 76 |     // C: 1, show cursor, 0 don't
 77 |     // B: 1, cursor blinks (if shown), 0 don't blink (if shown)
 78 |      8: icode <= 4'h0; // Upper nibble 0000
 79 |      9: icode <= 4'hC; // Lower nibble 1100
 80 | 
 81 |     // Clear Display. Upper nibble 0000, lower nibble 0001
 82 |     10: icode <= 4'h0; // Upper nibble 0000
 83 |     11: icode <= 4'h1; // Lower nibble 0001
 84 | 
 85 |     // We should read the Busy Flag and Address after each command
 86 |     // to determine whether we can move on to the next command.
 87 |     // However, our init counter runs quite slowly that most 1602
 88 |     // LCDs should have plenty of time to finish each command.
 89 |     default: lcd_initialized <= 1;
 90 |     endcase
 91 |   end
 92 | end
 93 | 
 94 | // The text refreshing sequence.
 95 | always @(posedge clk) begin
 96 |   if (reset) begin
 97 |     text_count <= 0;
 98 |     text_d  <= 4'h0;
 99 |     text_e  <= 0;
100 |     text_rs <= 0;
101 |     text_rw <= 0;
102 |   end
103 |   else if (lcd_initialized) begin
104 |     text_count <= (text_count[24:18] < 68)? text_count + 1 : 0;
105 | 
106 |     // Refresh (enable) the LCD when bit 17 of the text_count is 1
107 |     // The command clock frequency is 100MHz/(2^18) = 381.47 Hz
108 |     // The screen refresh frequency is 381.47Hz/68 = 5.60 Hz
109 |     text_e  <= text_count[17];
110 |     text_rs <= 1;
111 |     text_rw <= 0;
112 |     text_d <= tcode;
113 | 
114 |     case (text_count[24:18])
115 |     // Position the cursor to the start of the first line.
116 |     // Upper nibble is 1???, where ??? is the highest 3 bits of
117 |     // the RAM address to move the cursor to.
118 |     // Lower nibble is the lower 4 bits of the RAM address.
119 |      0: { text_rs, text_rw, tcode } <= 6'b001000;
120 |      1: { text_rs, text_rw, tcode } <= 6'b000000;
121 | 
122 |     // Print chararters by writing data to DD RAM (or CG RAM).
123 |     // The cursor will advance to the right end of the screen.
124 |      2: tcode <= row_A[127:124];
125 |      3: tcode <= row_A[123:120];
126 |      4: tcode <= row_A[119:116];
127 |      5: tcode <= row_A[115:112];
128 |      6: tcode <= row_A[111:108];
129 |      7: tcode <= row_A[107:104];
130 |      8: tcode <= row_A[103:100];
131 |      9: tcode <= row_A[99 :96 ];
132 |     10: tcode <= row_A[95 :92 ];
133 |     11: tcode <= row_A[91 :88 ];
134 |     12: tcode <= row_A[87 :84 ];
135 |     13: tcode <= row_A[83 :80 ];
136 |     14: tcode <= row_A[79 :76 ];
137 |     15: tcode <= row_A[75 :72 ];
138 |     16: tcode <= row_A[71 :68 ];
139 |     17: tcode <= row_A[67 :64 ];
140 |     18: tcode <= row_A[63 :60 ];
141 |     19: tcode <= row_A[59 :56 ];
142 |     20: tcode <= row_A[55 :52 ];
143 |     21: tcode <= row_A[51 :48 ];
144 |     22: tcode <= row_A[47 :44 ];
145 |     23: tcode <= row_A[43 :40 ];
146 |     24: tcode <= row_A[39 :36 ];
147 |     25: tcode <= row_A[35 :32 ];
148 |     26: tcode <= row_A[31 :28 ];
149 |     27: tcode <= row_A[27 :24 ];
150 |     28: tcode <= row_A[23 :20 ];
151 |     29: tcode <= row_A[19 :16 ];
152 |     30: tcode <= row_A[15 :12 ];
153 |     31: tcode <= row_A[11 :8  ];
154 |     32: tcode <= row_A[7  :4  ];
155 |     33: tcode <= row_A[3  :0  ];
156 | 
157 |     // position the cursor to the start of the 2nd line
158 |     34: { text_rs, text_rw, tcode } <= 6'b001100;
159 |     35: { text_rs, text_rw, tcode } <= 6'b000000;
160 | 
161 |     // Print chararters by writing data to DD RAM (or CG RAM).
162 |     // The cursor will advance to the right end of the screen.
163 |     36: tcode <= row_B[127:124];
164 |     37: tcode <= row_B[123:120];
165 |     38: tcode <= row_B[119:116];
166 |     39: tcode <= row_B[115:112];
167 |     40: tcode <= row_B[111:108];
168 |     41: tcode <= row_B[107:104];
169 |     42: tcode <= row_B[103:100];
170 |     43: tcode <= row_B[99 :96 ];
171 |     44: tcode <= row_B[95 :92 ];
172 |     45: tcode <= row_B[91 :88 ];
173 |     46: tcode <= row_B[87 :84 ];
174 |     47: tcode <= row_B[83 :80 ];
175 |     48: tcode <= row_B[79 :76 ];
176 |     49: tcode <= row_B[75 :72 ];
177 |     50: tcode <= row_B[71 :68 ];
178 |     51: tcode <= row_B[67 :64 ];
179 |     52: tcode <= row_B[63 :60 ];
180 |     53: tcode <= row_B[59 :56 ];
181 |     54: tcode <= row_B[55 :52 ];
182 |     55: tcode <= row_B[51 :48 ];
183 |     56: tcode <= row_B[47 :44 ];
184 |     57: tcode <= row_B[43 :40 ];
185 |     58: tcode <= row_B[39 :36 ];
186 |     59: tcode <= row_B[35 :32 ];
187 |     60: tcode <= row_B[31 :28 ];
188 |     61: tcode <= row_B[27 :24 ];
189 |     62: tcode <= row_B[23 :20 ];
190 |     63: tcode <= row_B[19 :16 ];
191 |     64: tcode <= row_B[15 :12 ];
192 |     65: tcode <= row_B[11 :8  ];
193 |     66: tcode <= row_B[7  :4  ];
194 |     67: tcode <= row_B[3  :0  ];
195 |     default: { text_rs, text_rw, tcode } <= 6'h10; // default to read mode.
196 |     endcase
197 |   end
198 | end
199 | 
200 | endmodule
201 | 


--------------------------------------------------------------------------------
/Lab_10/lab10.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: Dept. of Computer Science, National Chiao Tung University
  4 | // Engineer: Chun-Jen Tsai
  5 | //
  6 | // Create Date: 2017/08/25 14:29:54
  7 | // Design Name:
  8 | // Module Name: lab10
  9 | // Project Name:
 10 | // Target Devices:
 11 | // Tool Versions:
 12 | // Description: A circuit that show the animation of a moon moving across a city
 13 | //              night view on a screen through the VGA interface of Arty I/O card.
 14 | //
 15 | // Dependencies: vga_sync, clk_divider, sram
 16 | //
 17 | // Revision:
 18 | // Revision 0.01 - File Created
 19 | // Additional Comments:
 20 | //
 21 | //////////////////////////////////////////////////////////////////////////////////
 22 | 
 23 | module lab10(input clk,
 24 |              input reset_n,
 25 |              input [3:0] usr_btn,
 26 |              output [3:0] usr_led,
 27 |              output VGA_HSYNC,
 28 |              output VGA_VSYNC,
 29 |              output [3:0] VGA_RED,
 30 |              output [3:0] VGA_GREEN,
 31 |              output [3:0] VGA_BLUE);
 32 |     
 33 |     // Declare system variables
 34 |     reg  [33:0] moon_clock;
 35 |     reg  [28:0] firework_clock;
 36 |     wire [9:0]  pos;
 37 |     wire [2:0]  firework_count;
 38 |     wire        moon_region;
 39 |     
 40 |     // declare SRAM control signals
 41 |     wire [16:0] sram_addr;
 42 |     wire [11:0] data_in;
 43 |     wire [11:0] data_out;
 44 |     wire        sram_we, sram_en;
 45 | 
 46 |     //SRAM control signals of moon and the firework
 47 |     wire [11:0] sram_moon_addr;
 48 |     wire [11:0] data_moon_out;
 49 |     wire [13:0] sram_firework_addr;
 50 |     wire [11:0] data_firework_out;
 51 |     
 52 |     // General VGA control signals
 53 |     wire vga_clk;       // 50MHz clock for VGA control
 54 |     wire video_on;      // when video_on is 0, the VGA controller is sending
 55 |     // synchronization signals to the display device.
 56 |     
 57 |     wire pixel_tick;    // when pixel tick is 1, we must update the RGB value
 58 |     // based for the new coordinate (pixel_x, pixel_y)
 59 |     
 60 |     wire [9:0] pixel_x; // x coordinate of the next pixel (between 0 ~ 639)
 61 |     wire [9:0] pixel_y; // y coordinate of the next pixel (between 0 ~ 479)
 62 |     
 63 |     reg  [11:0] rgb_reg;  // RGB value for the current pixel
 64 |     reg  [11:0] rgb_next; // RGB value for the next pixel
 65 |     
 66 |     // Application-specific VGA signals
 67 |     reg  [16:0] pixel_addr;
 68 |     reg  [11:0] pixel_moon_addr;
 69 |     reg  [13:0] pixel_firework_addr ;
 70 |     
 71 |     // Declare the video buffer size
 72 |     localparam VBUF_W = 320; // video buffer width
 73 |     localparam VBUF_H = 240; // video buffer height
 74 |     
 75 |     // Instiantiate a VGA sync signal generator
 76 |     vga_sync vs0(
 77 |       .clk(vga_clk), 
 78 |       .reset(~reset_n), 
 79 |       .oHS(VGA_HSYNC), 
 80 |       .oVS(VGA_VSYNC),
 81 |       .visible(video_on), 
 82 |       .p_tick(pixel_tick),
 83 |       .pixel_x(pixel_x), 
 84 |       .pixel_y(pixel_y)
 85 |     );
 86 |     
 87 |     clk_divider#(2) clk_divider0(
 88 |       .clk(clk),
 89 |       .reset(~reset_n),
 90 |       .clk_out(vga_clk)
 91 |     );
 92 |     
 93 |     // ------------------------------------------------------------------------
 94 |     // The following code describes an initialized SRAM memory block that
 95 |     // stores an 320x240 12-bit city image, plus a 64x40 moon image.
 96 |     sram #(
 97 |       .DATA_WIDTH(12),
 98 |       .ADDR_WIDTH(17),
 99 |       .RAM_SIZE(VBUF_W*VBUF_H)
100 |     )ram_backbround(
101 |       .clk(clk), 
102 |       .we(sram_we), 
103 |       .en(sram_en),
104 |       .addr(sram_addr), 
105 |       .data_i(data_in), 
106 |       .data_o(data_out)
107 |     );
108 | 
109 |     sram_moon #(
110 |       .DATA_WIDTH(12),
111 |       .ADDR_WIDTH(12),
112 |       .RAM_SIZE(64*40)
113 |     )ram_moon(
114 |       .clk(clk), 
115 |       .we(sram_we), 
116 |       .en(sram_en),
117 |       .addr(sram_moon_addr), 
118 |       .data_i(data_in), 
119 |       .data_o(data_moon_out)
120 |     );
121 | 
122 |     sram_firework #(
123 |       .DATA_WIDTH(12),
124 |       .ADDR_WIDTH(14),
125 |       .RAM_SIZE(6*50*40)
126 |     )ram_firework(
127 |       .clk(clk), 
128 |       .we(sram_we), 
129 |       .en(sram_en),
130 |       .addr(sram_firework_addr), 
131 |       .data_i(data_in), 
132 |       .data_o(data_firework_out)
133 |     );
134 | 
135 |     assign sram_we = usr_btn[3]; // In this demo, we do not write the SRAM. However,if you set 'we' to 0, Vivado fails to synthesize
136 |     //ram0 as a BRAM -- this is a bug in Vivado.
137 |     assign sram_en   = 1;          // Here, we always enable the SRAM block.
138 |     assign sram_addr = pixel_addr;
139 |     assign data_in   = 12'h000; // SRAM is read-only so we tie inputs to zeros.
140 |     // End of the SRAM memory block.
141 | 
142 |     assign sram_moon_addr = pixel_moon_addr;
143 |     assign sram_firework_addr = pixel_firework_addr;
144 | 
145 |     // ------------------------------------------------------------------------
146 |     
147 |     // VGA color pixel generator
148 |     assign {VGA_RED, VGA_GREEN, VGA_BLUE} = rgb_reg;
149 |     
150 |     // ------------------------------------------------------------------------
151 |     // An animation clock for the motion of the moon, upper bits of the
152 |     // moon clock is the x position of the moon in the VGA screen
153 |     assign pos = moon_clock[33:24];
154 | 
155 |     assign firework_count = firework_clock[28:26];
156 | 
157 |     
158 |     always @(posedge clk) begin
159 |         if (~reset_n || moon_clock[33:25] > VBUF_W + 64)
160 |             moon_clock <= 0;
161 |         else
162 |             moon_clock <= moon_clock + 1;
163 |     end
164 | 
165 |     always @(posedge clk) begin
166 |       if (~reset_n || firework_count > 5 || moon_clock == 0)
167 |           firework_clock <= 0;
168 |       else
169 |           firework_clock <= firework_clock + 1;
170 |     end
171 | 
172 |     // End of the animation clock code.
173 |     // ------------------------------------------------------------------------
174 |     
175 |     // ------------------------------------------------------------------------
176 |     // Video frame buffer address generation unit (AGU) with scaling control
177 |     // Note that the width x height of the moon image is 64x40, when scaled
178 |     // up to the screen, it becomes 128x80
179 |     assign moon_region = pixel_y >= 0 && pixel_y < 80 &&
180 |     (pixel_x + 127) >= pos && pixel_x < pos + 1;
181 | 
182 |     assign firework_region = pixel_y >= 40 && pixel_y <= 120 &&
183 |     pixel_x >= 320 && pixel_x <= 420;
184 |     
185 |     always @ (posedge clk) begin
186 |         if (~reset_n)
187 |             pixel_addr <= 0;
188 |         else
189 |         // Scale up a 320x240 image for the 640x480 display.
190 |         // (pixel_x, pixel_y) ranges from (0,0) to (639, 379)
191 |           pixel_addr <= (pixel_y >> 1) * VBUF_W + (pixel_x >> 1);
192 |     end
193 | 
194 | 
195 |     always @(posedge clk ) begin
196 |       if(~reset_n)
197 |         pixel_moon_addr <= 0;
198 |       else
199 |         pixel_moon_addr <= ((pixel_y&10'h3FE)<<5) + ((pixel_x-pos+127)>>1);
200 |     end
201 | 
202 |     always @ (posedge clk) begin
203 |       if (~reset_n)
204 |         pixel_firework_addr <= 0;
205 |       else
206 |         pixel_firework_addr <= firework_count*50*40 + ((pixel_y-40) >> 1) * 50 + ((pixel_x-320) >> 1);
207 |     end
208 | 
209 |     // End of the AGU code.
210 |     // ------------------------------------------------------------------------
211 |     
212 |     // ------------------------------------------------------------------------
213 |     // Send the video data in the sram to the VGA controller
214 |     
215 |     always @(posedge clk) begin
216 |         if (pixel_tick) rgb_reg <= rgb_next;
217 |     end
218 |     
219 |     always @(*) begin
220 |         if (~video_on)
221 |             rgb_next = 12'h000; // Synchronization period, must set RGB values to zero.
222 |         else if(firework_region && data_firework_out != 12'h000)
223 |           rgb_next = data_firework_out;           
224 |         
225 |         else if(moon_region && data_moon_out != 12'h0f0)
226 |           rgb_next = data_moon_out;
227 |         else 
228 |           rgb_next = data_out;
229 |     end
230 |     // End of the video data display code.
231 |     // ------------------------------------------------------------------------
232 |     
233 | endmodule
234 | 


--------------------------------------------------------------------------------
/Lab_07/uart.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 2021/07/29 14:49:43
  7 | // Design Name: 
  8 | // Module Name: uart
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | `timescale 1ns / 1ps
 24 | // Documented Verilog UART
 25 | // Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz)
 26 | // Distributed under the MIT licence.
 27 | //
 28 | // Permission is hereby granted, free of charge, to any person obtaining a copy
 29 | // of this software and associated documentation files (the "Software"), to deal
 30 | // in the Software without restriction, including without limitation the rights
 31 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 32 | // copies of the Software, and to permit persons to whom the Software is
 33 | // furnished to do so, subject to the following conditions:
 34 | // 
 35 | // The above copyright notice and this permission notice shall be included in
 36 | // all copies or substantial portions of the Software.
 37 | // 
 38 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 39 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 40 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 41 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 42 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 43 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 44 | // THE SOFTWARE.
 45 | // 
 46 | module uart(
 47 |     input clk, // The master clock for this module
 48 |     input rst, // Synchronous reset.
 49 |     input rx, // Incoming serial line
 50 |     output tx, // Outgoing serial line
 51 |     input transmit, // Signal to transmit
 52 |     input [7:0] tx_byte, // Byte to transmit
 53 |     output received, // Indicated that a byte has been received.
 54 |     output [7:0] rx_byte, // Byte received
 55 |     output is_receiving, // Low when receive line is idle.
 56 |     output is_transmitting, // Low when transmit line is idle.
 57 |     output recv_error // Indicates error in receiving packet.
 58 |     );
 59 | 
 60 | parameter CLOCK_DIVIDE = 651; // clock rate (100Mhz) / (baud rate (9600) * 16)
 61 | 
 62 | // States for the receiving state machine.
 63 | // These are just constants, not parameters to override.
 64 | parameter RX_IDLE = 0;
 65 | parameter RX_CHECK_START = 1;
 66 | parameter RX_READ_BITS = 2;
 67 | parameter RX_CHECK_STOP = 3;
 68 | parameter RX_DELAY_RESTART = 4;
 69 | parameter RX_ERROR = 5;
 70 | parameter RX_RECEIVED = 6;
 71 | 
 72 | // States for the transmitting state machine.
 73 | // Constants - do not override.
 74 | parameter TX_IDLE = 0;
 75 | parameter TX_SENDING = 1;
 76 | parameter TX_DELAY_RESTART = 2;
 77 | 
 78 | reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
 79 | reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
 80 | 
 81 | reg [2:0] recv_state = RX_IDLE;
 82 | reg [5:0] rx_countdown;
 83 | reg [3:0] rx_bits_remaining;
 84 | reg [7:0] rx_data;
 85 | 
 86 | reg tx_out = 1;
 87 | reg [1:0] tx_state = TX_IDLE;
 88 | reg [5:0] tx_countdown;
 89 | reg [3:0] tx_bits_remaining;
 90 | reg [7:0] tx_data;
 91 | 
 92 | assign received = (recv_state == RX_RECEIVED);
 93 | assign recv_error = (recv_state == RX_ERROR);
 94 | assign is_receiving = (recv_state != RX_IDLE);
 95 | assign rx_byte = rx_data;
 96 | 
 97 | assign tx = tx_out;
 98 | assign is_transmitting = tx_state != TX_IDLE;
 99 | 
100 | always @(posedge clk) begin
101 |   if (rst) begin
102 |     recv_state = RX_IDLE;
103 |     tx_state = TX_IDLE;
104 |   end
105 | 
106 |   // The clk_divider counter counts down from the CLOCK_DIVIDE constant.
107 |   // Whenever it reaches 0, 1/16 of the bit period has elapsed. Countdown
108 |   // timers for the receiving and transmitting state machines are decremented.
109 |   rx_clk_divider = rx_clk_divider - 1;
110 |   if (!rx_clk_divider) begin
111 |     rx_clk_divider = CLOCK_DIVIDE;
112 |     rx_countdown = rx_countdown - 1;
113 |   end
114 |   tx_clk_divider = tx_clk_divider - 1;
115 |   if (!tx_clk_divider) begin
116 |     tx_clk_divider = CLOCK_DIVIDE;
117 |     tx_countdown = tx_countdown - 1;
118 |   end
119 | 
120 |   // Receive state machine
121 |   case (recv_state)
122 |     RX_IDLE: begin
123 |       // A low pulse on the receive line indicates the start of data.
124 |       if (!rx) begin
125 |         // Wait half the period - should resume
126 |         // in the middle of this first pulse.
127 |         rx_clk_divider = CLOCK_DIVIDE;
128 |         rx_countdown = 8;
129 |         recv_state = RX_CHECK_START;
130 |       end
131 |     end
132 | 
133 |     RX_CHECK_START: begin
134 |       if (!rx_countdown) begin
135 |         // Check the pulse is still there
136 |         if (!rx) begin
137 |           // Pulse still there - good
138 |           // Wait the bit period to resume half-way through the first bit.
139 |           rx_countdown = 16;
140 |           rx_bits_remaining = 8;
141 |           recv_state = RX_READ_BITS;
142 |         end else begin
143 |           // Pulse lasted less than half the period -
144 |           // not a valid transmission.
145 |           recv_state = RX_ERROR;
146 |         end
147 |       end
148 |     end
149 | 
150 |     RX_READ_BITS: begin
151 |       if (!rx_countdown) begin
152 |         // Should be half-way through a bit pulse here.
153 |         // Read this bit in, wait for the next if we have more to get.
154 |         rx_data = {rx, rx_data[7:1]};
155 |         rx_countdown = 16;
156 |         rx_bits_remaining = rx_bits_remaining - 1;
157 |         recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
158 |       end
159 |     end
160 | 
161 |     RX_CHECK_STOP: begin
162 |       if (!rx_countdown) begin
163 |         // Should resume half-way through the stop bit. This should
164 |         // be high - if not, reject the transmission and signal an error.
165 |         recv_state = rx ? RX_RECEIVED : RX_ERROR;
166 |       end
167 |     end
168 | 
169 |     RX_DELAY_RESTART: begin
170 |       // Waits a set number of cycles before accepting another transmission.
171 |       recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
172 |     end
173 | 
174 |     RX_ERROR: begin
175 |       // There was an error receiving.
176 |       // Raises the recv_error flag for one clock cycle while in this state
177 |       // and then waits 2 bit periods before accepting another transmission.
178 |       rx_countdown = 32;
179 |       recv_state = RX_DELAY_RESTART;
180 |     end
181 | 
182 |     RX_RECEIVED: begin
183 |       // Successfully received a byte.
184 |       // Raises the received flag for one clock cycle while in this state.
185 |       recv_state = RX_IDLE;
186 |     end
187 | 
188 |     default: recv_state = RX_IDLE;
189 |   endcase
190 | 
191 |   // Transmit state machine
192 |   case (tx_state)
193 |     TX_IDLE: begin
194 |       if (transmit) begin
195 |         // If the transmit flag is raised in the idle
196 |         // state, start transmitting the current content of the tx_byte input.
197 |         tx_data = tx_byte;
198 |         // Send the initial, low pulse of 1 bit period
199 |         // to signal the start, followed by the data
200 |         tx_clk_divider = CLOCK_DIVIDE;
201 |         tx_countdown = 16;
202 |         tx_out = 0;
203 |         tx_bits_remaining = 8;
204 |         tx_state = TX_SENDING;
205 |       end
206 |     end
207 | 
208 |     TX_SENDING: begin
209 |       if (!tx_countdown) begin
210 |         if (tx_bits_remaining) begin
211 |           tx_bits_remaining = tx_bits_remaining - 1;
212 |           tx_out = tx_data[0];
213 |           tx_data = {1'b0, tx_data[7:1]};
214 |           tx_countdown = 16;
215 |           tx_state = TX_SENDING;
216 |         end else begin
217 |           // Set delay to send out 2 stop bits.
218 |           tx_out = 1;
219 |           tx_countdown = 32;
220 |           tx_state = TX_DELAY_RESTART;
221 |         end
222 |       end
223 |     end
224 | 
225 |     TX_DELAY_RESTART: begin
226 |       // Wait until tx_countdown reaches the end before
227 |       // we send another transmission. This covers the "stop bit" delay.
228 |       tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
229 |     end
230 | 
231 |     default: tx_state = TX_IDLE;
232 |   endcase
233 | end
234 | 
235 | endmodule
236 | 
237 | 


--------------------------------------------------------------------------------
/Lab_08/md5.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company:
  4 | // Engineer:
  5 | //
  6 | // Create Date: 2021/07/19 21:05:52
  7 | // Design Name:
  8 | // Module Name: md5
  9 | // Project Name:
 10 | // Target Devices:
 11 | // Tool Versions:
 12 | // Description:
 13 | //
 14 | // Dependencies:
 15 | //
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module md5 (input clk,
 23 |             input reset_n,
 24 |             input [63:0] pwd,
 25 |             output [127:0] hash,
 26 |             output done);
 27 |     
 28 |     function [31:0] LeftRotate;
 29 |         input [31:0]x;
 30 |         input [4:0]c;
 31 |         LeftRotate = (((x) << (c)) | ((x) >> (32'd32 - (c))));
 32 |     endfunction
 33 |     
 34 |     reg [31:0] r [63:0];
 35 |     reg [31:0] k [63:0];
 36 |     wire [31:0] w [15:0];
 37 |     
 38 |     reg [31:0] h0 = 32'h67452301;
 39 |     reg [31:0] h1 = 32'hefcdab89;
 40 |     reg [31:0] h2 = 32'h98badcfe;
 41 |     reg [31:0] h3 = 32'h10325476;
 42 |     reg [31:0] a;
 43 |     reg [31:0] b;
 44 |     reg [31:0] c;
 45 |     reg [31:0] d;
 46 |     wire [31:0] h0_a;
 47 |     wire [31:0] h1_b;
 48 |     wire [31:0] h2_c;
 49 |     wire [31:0] h3_d;
 50 |     
 51 |     reg [31:0] f;
 52 |     reg [8:0] g;
 53 |     wire[31:0] k_show;
 54 |     wire [31:0] w_show;
 55 |     wire [31:0] r_show;
 56 |     
 57 |     reg [7:0] msg [63:0];
 58 |     
 59 |     
 60 |     parameter PAD_LEN = 56;
 61 |     
 62 |     localparam S_IDLE = 0;
 63 |     localparam S_LOOP = 1;
 64 |     localparam S_DONE = 2;
 65 |     reg [1:0]current_state, next_state;
 66 |     
 67 |     reg[6:0]loop_idx;
 68 |     
 69 |     
 70 |     //initialize r,k
 71 |     initial begin
 72 |         {
 73 |         r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7], r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15],
 74 |         r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23], r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31],
 75 |         r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39], r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47],
 76 |         r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55], r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63]
 77 |         }
 78 |  <= {
 79 |         32'd7, 32'd12, 32'd17, 32'd22, 32'd7, 32'd12, 32'd17, 32'd22, 32'd7, 32'd12, 32'd17, 32'd22, 32'd7, 32'd12, 32'd17, 32'd22,
 80 |         32'd5, 32'd9, 32'd14, 32'd20, 32'd5,  32'd9, 32'd14, 32'd20, 32'd5,  32'd9, 32'd14, 32'd20, 32'd5, 32'd9, 32'd14, 32'd20,
 81 |         32'd4, 32'd11, 32'd16, 32'd23, 32'd4, 32'd11, 32'd16, 32'd23, 32'd4, 32'd11, 32'd16, 32'd23, 32'd4, 32'd11, 32'd16, 32'd23,
 82 |         32'd6, 32'd10, 32'd15, 32'd21, 32'd6, 32'd10, 32'd15, 32'd21, 32'd6, 32'd10, 32'd15, 32'd21, 32'd6, 32'd10, 32'd15, 32'd21
 83 |         };
 84 |     end
 85 |     
 86 |     initial begin
 87 |         {
 88 |         k[0], k[1], k[2], k[3], k[4], k[5], k[6], k[7], k[8], k[9], k[10], k[11], k[12], k[13], k[14], k[15],
 89 |         k[16], k[17], k[18], k[19], k[20], k[21], k[22], k[23], k[24], k[25], k[26], k[27], k[28], k[29], k[30], k[31],
 90 |         k[32], k[33], k[34], k[35], k[36], k[37], k[38], k[39], k[40], k[41], k[42], k[43], k[44], k[45], k[46], k[47],
 91 |         k[48], k[49], k[50], k[51], k[52], k[53], k[54], k[55], k[56], k[57], k[58], k[59], k[60], k[61], k[62], k[63]
 92 |         
 93 |         }
 94 |  <= {
 95 |         32'hd76aa478, 32'he8c7b756, 32'h242070db, 32'hc1bdceee, 32'hf57c0faf, 32'h4787c62a, 32'ha8304613, 32'hfd469501,
 96 |         32'h698098d8, 32'h8b44f7af, 32'hffff5bb1, 32'h895cd7be, 32'h6b901122, 32'hfd987193, 32'ha679438e, 32'h49b40821,
 97 |         32'hf61e2562, 32'hc040b340, 32'h265e5a51, 32'he9b6c7aa, 32'hd62f105d, 32'h02441453, 32'hd8a1e681, 32'he7d3fbc8,
 98 |         32'h21e1cde6, 32'hc33707d6, 32'hf4d50d87, 32'h455a14ed, 32'ha9e3e905, 32'hfcefa3f8, 32'h676f02d9, 32'h8d2a4c8a,
 99 |         32'hfffa3942, 32'h8771f681, 32'h6d9d6122, 32'hfde5380c, 32'ha4beea44, 32'h4bdecfa9, 32'hf6bb4b60, 32'hbebfbc70,
100 |         32'h289b7ec6, 32'heaa127fa, 32'hd4ef3085, 32'h04881d05, 32'hd9d4d039, 32'he6db99e5, 32'h1fa27cf8, 32'hc4ac5665,
101 |         32'hf4292244, 32'h432aff97, 32'hab9423a7, 32'hfc93a039, 32'h655b59c3, 32'h8f0ccc92, 32'hffeff47d, 32'h85845dd1,
102 |         32'h6fa87e4f, 32'hfe2ce6e0, 32'ha3014314, 32'h4e0811a1, 32'hf7537e82, 32'hbd3af235, 32'h2ad7d2bb, 32'heb86d391
103 |         };
104 |     end
105 |     
106 |     //initialize msg to 0
107 |     initial begin
108 |         {
109 |         msg[0], msg[1], msg[2], msg[3], msg[4], msg[5], msg[6], msg[7], msg[8], msg[9], msg[10], msg[11], msg[12], msg[13], msg[14], msg[15],
110 |         msg[16], msg[17], msg[18], msg[19], msg[20], msg[21], msg[22], msg[23], msg[24], msg[25], msg[26], msg[27], msg[28], msg[29], msg[30], msg[31],
111 |         msg[32], msg[33], msg[34], msg[35], msg[36], msg[37], msg[38], msg[39], msg[40], msg[41], msg[42], msg[43], msg[44], msg[45], msg[46], msg[47],
112 |         msg[48], msg[49], msg[50], msg[51], msg[52], msg[53], msg[54], msg[55], msg[56], msg[57], msg[58], msg[59], msg[60], msg[61], msg[62], msg[63]
113 |         
114 |         }
115 |  <= {
116 |         8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,
117 |         8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,
118 |         8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,
119 |         8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0
120 |         };
121 |     end
122 |     
123 |     assign {w[0],w[1],w[2],w[3],w[4],w[5],w[6],w[7],w[8],w[9],w[10],w[11],w[12],w[13],w[14],w[15]}
124 |     = {
125 |     {msg[3],msg[2],msg[1],msg[0]},
126 |     {msg[7],msg[6],msg[5],msg[4]},
127 |     {msg[11],msg[10],msg[9],msg[8]},
128 |     {msg[15],msg[14],msg[13],msg[12]},
129 |     {msg[19],msg[18],msg[17],msg[16]},
130 |     {msg[23],msg[22],msg[21],msg[20]},
131 |     {msg[27],msg[26],msg[25],msg[24]},
132 |     {msg[31],msg[30],msg[29],msg[28]},
133 |     {msg[35],msg[34],msg[33],msg[32]},
134 |     {msg[39],msg[38],msg[37],msg[36]},
135 |     {msg[43],msg[42],msg[41],msg[40]},
136 |     {msg[47],msg[46],msg[45],msg[44]},
137 |     {msg[51],msg[50],msg[49],msg[48]},
138 |     {msg[55],msg[54],msg[53],msg[52]},
139 |     {msg[59],msg[58],msg[57],msg[56]},
140 |     {msg[63],msg[62],msg[61],msg[60]}
141 |     };
142 |     
143 |     always @(posedge clk) begin
144 |         if (current_state == S_IDLE)begin
145 |             msg[7]       <= pwd[ 0+:8]+"0";
146 |             msg[6]       <= pwd[ 8+:8]+"0";
147 |             msg[5]       <= pwd[16+:8]+"0";
148 |             msg[4]       <= pwd[24+:8]+"0";
149 |             msg[3]       <= pwd[32+:8]+"0";
150 |             msg[2]       <= pwd[40+:8]+"0";
151 |             msg[1]       <= pwd[48+:8]+"0";
152 |             msg[0]       <= pwd[56+:8]+"0";
153 |             msg[8]       <= 8'h80;
154 |             msg[PAD_LEN] <= 8'd64;
155 |             
156 |         end
157 |     end
158 |     
159 |     always @(posedge clk) begin
160 |         if (!reset_n)current_state <= S_IDLE;
161 |         else current_state         <= next_state;
162 |     end
163 |     
164 |     always @(*) begin
165 |         case(current_state)
166 |             S_IDLE:next_state = S_LOOP;
167 |             S_LOOP:next_state = (loop_idx == 63)?S_DONE:S_LOOP;
168 |             S_DONE:next_state = S_DONE;
169 |             default next_state =S_IDLE;
170 |             
171 |         endcase
172 |     end
173 |     
174 |     always @(posedge clk) begin
175 |         if (current_state == S_IDLE) loop_idx      <= 0;
176 |         else if (current_state == S_LOOP) loop_idx <= loop_idx+1;
177 |     end
178 |     
179 |     always @(*) begin
180 |         if (current_state == S_IDLE)f = 0;
181 |         else if (current_state == S_LOOP)begin
182 |         if (loop_idx< 16)f         = (b & c) | ((~b) & d);
183 |         else if (loop_idx<32)f     = (d & b) | ((~d) & c);
184 |         else if (loop_idx<48)f = b ^ c ^ d;
185 |         else f                 = c ^ (b | (~d));
186 |             end
187 |         else f = 0;
188 |     end
189 |         
190 |     always @(*) begin
191 |         if (current_state == S_IDLE) g = 0;
192 |         else if (current_state == S_LOOP)begin
193 |             if (loop_idx< 16)g = loop_idx;
194 |             else if (loop_idx<32)g = (5*loop_idx + 1) % 16;
195 |             else if (loop_idx<48)g = (3*loop_idx + 5) % 16;
196 |             else g                 = (7*loop_idx) % 16;
197 |         end
198 |         else g = 0;
199 |     end
200 |     always @(posedge clk) begin
201 |         if (current_state == S_IDLE)begin
202 |             a <= h0;
203 |             b <= h1;
204 |             c <= h2;
205 |             d <= h3;
206 |         end
207 |         else if (current_state == S_LOOP)begin
208 |             a <= d;
209 |             d <= c;
210 |             c <= b;
211 |             b <= b+LeftRotate(.x(a+f+k_show+w_show),.c(r_show));
212 |         end        
213 |     end
214 |             
215 |     assign k_show = k[loop_idx%64];
216 |     assign w_show = w[g%64];
217 |     assign r_show = r[loop_idx%64];
218 |         
219 |     assign h0_a = h0+a;
220 |     assign h1_b = h1+b;
221 |     assign h2_c = h2+c;
222 |     assign h3_d = h3+d;
223 |     
224 |     assign hash = {
225 |     h0_a[7:0],h0_a[15:8],h0_a[23:16],h0_a[31:24],
226 |     h1_b[0+:8],h1_b[8+:8],h1_b[16+:8],h1_b[24+:8],
227 |     h2_c[0+:8],h2_c[8+:8],h2_c[16+:8],h2_c[24+:8],
228 |     h3_d[0+:8],h3_d[8+:8],h3_d[16+:8],h3_d[24+:8]
229 |     };
230 |     
231 |     assign done = (current_state == S_DONE);
232 |     
233 | endmodule
234 | 
235 | //------------------------------
236 | 


--------------------------------------------------------------------------------
/Lab_04/uart.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | // Documented Verilog UART
  3 | // Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz)
  4 | // Distributed under the MIT licence.
  5 | //
  6 | // Permission is hereby granted, free of charge, to any person obtaining a copy
  7 | // of this software and associated documentation files (the "Software"), to deal
  8 | // in the Software without restriction, including without limitation the rights
  9 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 10 | // copies of the Software, and to permit persons to whom the Software is
 11 | // furnished to do so, subject to the following conditions:
 12 | //
 13 | // The above copyright notice and this permission notice shall be included in
 14 | // all copies or substantial portions of the Software.
 15 | //
 16 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 19 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 20 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 21 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 22 | // THE SOFTWARE.
 23 | //
 24 | module uart(input clk,              // The master clock for this module
 25 |             input rst,              // Synchronous reset.
 26 |             input rx,               // Incoming serial line
 27 |             output tx,              // Outgoing serial line
 28 |             input transmit,         // Signal to transmit
 29 |             input [7:0] tx_byte,    // Byte to transmit
 30 |             output received,        // Indicated that a byte has been received.
 31 |             output [7:0] rx_byte,   // Byte received
 32 |             output is_receiving,    // Low when receive line is idle.
 33 |             output is_transmitting, // Low when transmit line is idle.
 34 |             output recv_error);     // Indicates error in receiving packet.
 35 |     
 36 |     parameter CLOCK_DIVIDE = 651; // clock rate (100Mhz) / (baud rate (9600) * 16)
 37 |     
 38 |     // States for the receiving state machine.
 39 |     // These are just constants, not parameters to override.
 40 |     parameter RX_IDLE          = 0;
 41 |     parameter RX_CHECK_START   = 1;
 42 |     parameter RX_READ_BITS     = 2;
 43 |     parameter RX_CHECK_STOP    = 3;
 44 |     parameter RX_DELAY_RESTART = 4;
 45 |     parameter RX_ERROR         = 5;
 46 |     parameter RX_RECEIVED      = 6;
 47 |     
 48 |     // States for the transmitting state machine.
 49 |     // Constants - do not override.
 50 |     parameter TX_IDLE          = 0;
 51 |     parameter TX_SENDING       = 1;
 52 |     parameter TX_DELAY_RESTART = 2;
 53 |     
 54 |     reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
 55 |     reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
 56 |     
 57 |     reg [2:0] recv_state = RX_IDLE;
 58 |     reg [5:0] rx_countdown;
 59 |     reg [3:0] rx_bits_remaining;
 60 |     reg [7:0] rx_data;
 61 |     
 62 |     reg tx_out         = 1;
 63 |     reg [1:0] tx_state = TX_IDLE;
 64 |     reg [5:0] tx_countdown;
 65 |     reg [3:0] tx_bits_remaining;
 66 |     reg [7:0] tx_data;
 67 |     
 68 |     assign received     = (recv_state == RX_RECEIVED);
 69 |     assign recv_error   = (recv_state == RX_ERROR);
 70 |     assign is_receiving = (recv_state != RX_IDLE);
 71 |     assign rx_byte      = rx_data;
 72 |     
 73 |     assign tx              = tx_out;
 74 |     assign is_transmitting = tx_state != TX_IDLE;
 75 |     
 76 |     always @(posedge clk) begin
 77 |         if (rst) begin
 78 |             recv_state = RX_IDLE;
 79 |             tx_state   = TX_IDLE;
 80 |         end
 81 |         
 82 |         // The clk_divider counter counts down from the CLOCK_DIVIDE constant.
 83 |         // Whenever it reaches 0, 1/16 of the bit period has elapsed. Countdown
 84 |         // timers for the receiving and transmitting state machines are decremented.
 85 |         rx_clk_divider = rx_clk_divider - 1;
 86 |         if (!rx_clk_divider) begin
 87 |             rx_clk_divider = CLOCK_DIVIDE;
 88 |             rx_countdown   = rx_countdown - 1;
 89 |         end
 90 |         tx_clk_divider = tx_clk_divider - 1;
 91 |         if (!tx_clk_divider) begin
 92 |             tx_clk_divider = CLOCK_DIVIDE;
 93 |             tx_countdown   = tx_countdown - 1;
 94 |         end
 95 |         
 96 |         // Receive state machine
 97 |         case (recv_state)
 98 |             RX_IDLE: begin
 99 |                 // A low pulse on the receive line indicates the start of data.
100 |                 if (!rx) begin
101 |                     // Wait half the period - should resume
102 |                     // in the middle of this first pulse.
103 |                     rx_clk_divider = CLOCK_DIVIDE;
104 |                     rx_countdown   = 8;
105 |                     recv_state     = RX_CHECK_START;
106 |                 end
107 |             end
108 |             
109 |             RX_CHECK_START: begin
110 |                 if (!rx_countdown) begin
111 |                     // Check the pulse is still there
112 |                     if (!rx) begin
113 |                         // Pulse still there - good
114 |                         // Wait the bit period to resume half-way through the first bit.
115 |                         rx_countdown      = 16;
116 |                         rx_bits_remaining = 8;
117 |                         recv_state        = RX_READ_BITS;
118 |                         end else begin
119 |                             // Pulse lasted less than half the period -
120 |                             // not a valid transmission.
121 |                             recv_state = RX_ERROR;
122 |                         end
123 |                     end
124 |                 end
125 |                 
126 |                 RX_READ_BITS: begin
127 |                     if (!rx_countdown) begin
128 |                         // Should be half-way through a bit pulse here.
129 |                         // Read this bit in, wait for the next if we have more to get.
130 |                         rx_data           = {rx, rx_data[7:1]};
131 |                         rx_countdown      = 16;
132 |                         rx_bits_remaining = rx_bits_remaining - 1;
133 |                         recv_state        = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
134 |                     end
135 |                 end
136 |                 
137 |                 RX_CHECK_STOP: begin
138 |                     if (!rx_countdown) begin
139 |                         // Should resume half-way through the stop bit. This should
140 |                         // be high - if not, reject the transmission and signal an error.
141 |                         recv_state = rx ? RX_RECEIVED : RX_ERROR;
142 |                     end
143 |                 end
144 |                 
145 |                 RX_DELAY_RESTART: begin
146 |                     // Waits a set number of cycles before accepting another transmission.
147 |                     recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
148 |                 end
149 |                 
150 |                 RX_ERROR: begin
151 |                     // There was an error receiving.
152 |                     // Raises the recv_error flag for one clock cycle while in this state
153 |                     // and then waits 2 bit periods before accepting another transmission.
154 |                     rx_countdown = 32;
155 |                     recv_state   = RX_DELAY_RESTART;
156 |                 end
157 |                 
158 |                 RX_RECEIVED: begin
159 |                     // Successfully received a byte.
160 |                     // Raises the received flag for one clock cycle while in this state.
161 |                     recv_state = RX_IDLE;
162 |                 end
163 |                 
164 |                 default: recv_state = RX_IDLE;
165 |         endcase
166 |         
167 |         // Transmit state machine
168 |         case (tx_state)
169 |             TX_IDLE: begin
170 |                 if (transmit) begin
171 |                     // If the transmit flag is raised in the idle
172 |                     // state, start transmitting the current content of the tx_byte input.
173 |                     tx_data = tx_byte;
174 |                     // Send the initial, low pulse of 1 bit period
175 |                     // to signal the start, followed by the data
176 |                     tx_clk_divider    = CLOCK_DIVIDE;
177 |                     tx_countdown      = 16;
178 |                     tx_out            = 0;
179 |                     tx_bits_remaining = 8;
180 |                     tx_state          = TX_SENDING;
181 |                 end
182 |             end
183 |             
184 |             TX_SENDING: begin
185 |                 if (!tx_countdown) begin
186 |                     if (tx_bits_remaining) begin
187 |                         tx_bits_remaining = tx_bits_remaining - 1;
188 |                         tx_out            = tx_data[0];
189 |                         tx_data           = {1'b0, tx_data[7:1]};
190 |                         tx_countdown      = 16;
191 |                         tx_state          = TX_SENDING;
192 |                         end else begin
193 |                             // Set delay to send out 2 stop bits.
194 |                             tx_out       = 1;
195 |                             tx_countdown = 32;
196 |                             tx_state     = TX_DELAY_RESTART;
197 |                         end
198 |                     end
199 |                 end
200 |                 
201 |                 TX_DELAY_RESTART: begin
202 |                     // Wait until tx_countdown reaches the end before
203 |                     // we send another transmission. This covers the "stop bit" delay.
204 |                     tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
205 |                 end
206 |                 
207 |                 default: tx_state = TX_IDLE;
208 |         endcase
209 |     end
210 |     
211 | endmodule
212 |     
213 | 


--------------------------------------------------------------------------------
/Lab_08/crack_top.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 2021/07/22 11:20:15
  7 | // Design Name: 
  8 | // Module Name: crack_top
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | module crack_top(
 24 |     input clk,
 25 |     input rst_n,
 26 |     output reg [31:0] answer,
 27 |     output done);
 28 | 
 29 |     reg [127:0] cp_hash_answer = 128'hE9982EC5CA981BD365603623CF4B2277;
 30 |     parameter NUM_OF_DECODER = 32;
 31 | 
 32 |     reg [31:0] cp_lower_bound [NUM_OF_DECODER-1:0];
 33 |     reg [31:0] cp_upper_bound [NUM_OF_DECODER-1:0];
 34 |     wire [31:0] cp_answer [NUM_OF_DECODER-1:0];
 35 |     wire[NUM_OF_DECODER-1:0] cp_answer_found;
 36 |     wire [NUM_OF_DECODER-1:0] cp_done ;
 37 |     
 38 |     //     initial begin
 39 |     //     {
 40 |     //         cp_lower_bound[0],cp_lower_bound[1],cp_lower_bound[2],cp_lower_bound[3],cp_lower_bound[4],
 41 |     //         cp_lower_bound[5],cp_lower_bound[6],cp_lower_bound[7],cp_lower_bound[8],cp_lower_bound[9]
 42 |     //     }<=
 43 |     //     {
 44 |     //         32'h0000_0000,32'h1000_0000,32'h2000_0000,32'h3000_0000,32'h4000_0000,
 45 |     //         32'h5000_0000,32'h6000_0000,32'h7000_0000,32'h8000_0000,32'h9000_0000
 46 | 
 47 |     //     };
 48 |     // end
 49 | 
 50 |     // initial begin
 51 |     //     {
 52 |     //         cp_upper_bound[0],cp_upper_bound[1],cp_upper_bound[2],cp_upper_bound[3],cp_upper_bound[4],
 53 |     //         cp_upper_bound[5],cp_upper_bound[6],cp_upper_bound[7],cp_upper_bound[8],cp_upper_bound[9]
 54 |     //     }<=
 55 |     //     {
 56 |     //         32'h0999_9999,32'h1999_9999,32'h2999_9999,32'h3999_9999,32'h4999_9999,
 57 |     //         32'h5999_9999,32'h6999_9999,32'h7999_9999,32'h8999_9999,32'h9999_9999
 58 |     //     };
 59 |     // end
 60 | 
 61 | 
 62 | 
 63 | 
 64 | 
 65 | 
 66 |       initial begin
 67 |         {
 68 |             cp_lower_bound[ 0],cp_lower_bound[ 1],cp_lower_bound[ 2],cp_lower_bound[ 3],cp_lower_bound[ 4],cp_lower_bound[ 5],cp_lower_bound[ 6],cp_lower_bound[ 7],
 69 |             cp_lower_bound[ 8],cp_lower_bound[ 9],cp_lower_bound[10],cp_lower_bound[11],cp_lower_bound[12],cp_lower_bound[13],cp_lower_bound[15],cp_lower_bound[15],
 70 |             cp_lower_bound[16],cp_lower_bound[17],cp_lower_bound[18],cp_lower_bound[19],cp_lower_bound[20],cp_lower_bound[21],cp_lower_bound[22],cp_lower_bound[23],
 71 |             cp_lower_bound[24],cp_lower_bound[25],cp_lower_bound[26],cp_lower_bound[27],cp_lower_bound[28],cp_lower_bound[29],cp_lower_bound[30],cp_lower_bound[31]
 72 |         }<=
 73 |         {
 74 |             32'h0000_0000,32'h0312_0000,32'h0625_0000,32'h0937_0000,32'h1250_0000,32'h1562_0000,32'h1875_0000,32'h2187_0000,
 75 |             32'h2500_0000,32'h2812_0000,32'h3125_0000,32'h3437_0000,32'h3750_0000,32'h4062_0000,32'h4375_0000,32'h4687_0000,
 76 |             32'h5000_0000,32'h5312_0000,32'h5625_0000,32'h5937_0000,32'h6250_0000,32'h6562_0000,32'h6875_0000,32'h7187_0000,
 77 |             32'h7500_0000,32'h7812_0000,32'h8125_0000,32'h8437_0000,32'h8750_0000,32'h9062_0000,32'h9375_0000,32'h9687_0000
 78 |             
 79 | 
 80 |         };
 81 |     end
 82 | 
 83 |     initial begin
 84 |     {
 85 |         cp_upper_bound[ 0],cp_upper_bound[ 1],cp_upper_bound[ 2],cp_upper_bound[ 3],cp_upper_bound[ 4],cp_upper_bound[ 5],cp_upper_bound[ 6],cp_upper_bound[ 7],
 86 |         cp_upper_bound[ 8],cp_upper_bound[ 9],cp_upper_bound[10],cp_upper_bound[11],cp_upper_bound[12],cp_upper_bound[13],cp_upper_bound[15],cp_upper_bound[15],
 87 |         cp_upper_bound[16],cp_upper_bound[17],cp_upper_bound[18],cp_upper_bound[19],cp_upper_bound[20],cp_upper_bound[21],cp_upper_bound[22],cp_upper_bound[23],
 88 |         cp_upper_bound[24],cp_upper_bound[25],cp_upper_bound[26],cp_upper_bound[27],cp_upper_bound[28],cp_upper_bound[29],cp_upper_bound[30],cp_upper_bound[31]
 89 |     }<=
 90 |     {
 91 |         32'h0311_9999,32'h0624_9999,32'h0936_9999,32'h1249_9999,32'h1561_9999,32'h1874_9999,32'h2186_9999,32'h2499_9999,
 92 |         32'h2811_9999,32'h3124_9999,32'h3436_9999,32'h3749_9999,32'h4061_9999,32'h4374_9999,32'h4686_9999,32'h4999_9999,
 93 |         32'h5311_9999,32'h5624_9999,32'h5936_9999,32'h6249_9999,32'h6561_9999,32'h6874_9999,32'h7186_9999,32'h7499_9999,
 94 |         32'h7811_9999,32'h8124_9999,32'h8436_9999,32'h8749_9999,32'h9061_9999,32'h9374_9999,32'h9686_9999,32'h9999_9999
 95 |         
 96 | 
 97 |     };
 98 |     end
 99 | 
100 | //     initial begin
101 | //         {
102 | //             cp_lower_bound[ 0],cp_lower_bound[ 1],cp_lower_bound[ 2],cp_lower_bound[ 3],cp_lower_bound[ 4],cp_lower_bound[ 5],cp_lower_bound[ 6],cp_lower_bound[ 7],
103 | //             cp_lower_bound[ 8],cp_lower_bound[ 9],cp_lower_bound[10],cp_lower_bound[11],cp_lower_bound[12],cp_lower_bound[13],cp_lower_bound[15],cp_lower_bound[15],
104 | //             cp_lower_bound[16],cp_lower_bound[17],cp_lower_bound[18],cp_lower_bound[19],cp_lower_bound[20],cp_lower_bound[21],cp_lower_bound[22],cp_lower_bound[23],
105 | //             cp_lower_bound[24]
106 | //         }<=
107 | //         {
108 | //         32'h0000_0000,32'h0400_0000,32'h0800_0000,32'h1200_0000,32'h1600_0000,
109 | //         32'h2000_0000,32'h2400_0000,32'h2800_0000,32'h3200_0000,32'h3600_0000,
110 | //         32'h4000_0000,32'h4400_0000,32'h4800_0000,32'h5200_0000,32'h5600_0000,
111 | //         32'h6000_0000,32'h6400_0000,32'h6800_0000,32'h7200_0000,32'h7600_0000,
112 | //         32'h8000_0000,32'h8400_0000,32'h8800_0000,32'h9200_0000,32'h9600_0000
113 |             
114 | 
115 | //         };
116 | //     end
117 | 
118 | //     initial begin
119 | //     {
120 | //         cp_upper_bound[ 0],cp_upper_bound[ 1],cp_upper_bound[ 2],cp_upper_bound[ 3],cp_upper_bound[ 4],cp_upper_bound[ 5],cp_upper_bound[ 6],cp_upper_bound[ 7],
121 | //         cp_upper_bound[ 8],cp_upper_bound[ 9],cp_upper_bound[10],cp_upper_bound[11],cp_upper_bound[12],cp_upper_bound[13],cp_upper_bound[15],cp_upper_bound[15],
122 | //         cp_upper_bound[16],cp_upper_bound[17],cp_upper_bound[18],cp_upper_bound[19],cp_upper_bound[20],cp_upper_bound[21],cp_upper_bound[22],cp_upper_bound[23],
123 | //         cp_upper_bound[24]
124 | //     }<=
125 | //     {
126 | // 32'h0399_9999,32'h0799_9999,32'h1199_9999,32'h1599_9999,32'h1999_9999,
127 | // 32'h2399_9999,32'h2799_9999,32'h3199_9999,32'h3599_9999,32'h3999_9999,
128 | // 32'h4399_9999,32'h4799_9999,32'h5199_9999,32'h5599_9999,32'h5999_9999,
129 | // 32'h6399_9999,32'h6799_9999,32'h7199_9999,32'h7599_9999,32'h7999_9999,
130 | // 32'h8399_9999,32'h8799_9999,32'h9199_9999,32'h9599_9999,32'h9999_9999
131 |         
132 | 
133 | //     };
134 | //     end
135 | 
136 | 
137 | 
138 | 
139 |     
140 |     genvar i;
141 |     generate
142 |         for (i=0;i<NUM_OF_DECODER;i=i+1)begin
143 |             crack_partial cp(
144 |                 .clk(clk),
145 |                 .rst_n(rst_n),
146 |                 .lower_bound(cp_lower_bound[i]),
147 |                 .upper_bound(cp_upper_bound[i]),
148 |                 .hash_answer(cp_hash_answer),
149 |                 .answer(cp_answer[i]),
150 |                 .answer_found(cp_answer_found[i]),
151 |                 .done(cp_done[i])
152 |             );
153 |         end
154 |         
155 |     endgenerate
156 |     // crack_partial cp(
157 |     //             .clk(clk),
158 |     //             .rst_n(rst_n),
159 |     //             .lower_bound(cp_lower_bound[0]),
160 |     //             .upper_bound(cp_upper_bound[9]),
161 |     //             .hash_answer(cp_hash_answer),
162 |     //             .answer(cp_answer[0]),
163 |     //             .answer_found(cp_answer_found[0]),
164 |     //             .done(cp_done[0])
165 |     //         );
166 | 
167 |     assign done = |cp_done;
168 | 
169 |     always @(*) begin
170 |         if      (cp_answer_found[0])answer  = cp_answer[ 0];
171 |         else if(cp_answer_found[ 1])answer  = cp_answer[ 1];
172 |         else if(cp_answer_found[ 2])answer  = cp_answer[ 2];
173 |         else if(cp_answer_found[ 3])answer  = cp_answer[ 3];
174 |         else if(cp_answer_found[ 4])answer  = cp_answer[ 4];
175 |         else if(cp_answer_found[ 5])answer  = cp_answer[ 5];
176 |         else if(cp_answer_found[ 6])answer  = cp_answer[ 6];
177 |         else if(cp_answer_found[ 7])answer  = cp_answer[ 7];
178 |         else if(cp_answer_found[ 8])answer  = cp_answer[ 8];
179 |         else if(cp_answer_found[ 9])answer  = cp_answer[ 9];
180 |         else if(cp_answer_found[10])answer  = cp_answer[10];
181 |         else if(cp_answer_found[11])answer  = cp_answer[11];
182 |         else if(cp_answer_found[12])answer  = cp_answer[12];
183 |         else if(cp_answer_found[13])answer  = cp_answer[13];
184 |         else if(cp_answer_found[14])answer  = cp_answer[14];
185 |         else if(cp_answer_found[15])answer  = cp_answer[15];
186 |         else if(cp_answer_found[16])answer  = cp_answer[16];
187 |         else if(cp_answer_found[17])answer  = cp_answer[17];
188 |         else if(cp_answer_found[18])answer  = cp_answer[18];
189 |         else if(cp_answer_found[19])answer  = cp_answer[19];
190 |         else if(cp_answer_found[20])answer  = cp_answer[20];
191 |         else if(cp_answer_found[21])answer  = cp_answer[21];
192 |         else if(cp_answer_found[22])answer  = cp_answer[22];
193 |         else if(cp_answer_found[23])answer  = cp_answer[23];
194 |         else if(cp_answer_found[24])answer  = cp_answer[24];
195 |         else if(cp_answer_found[25])answer  = cp_answer[25];
196 |         else if(cp_answer_found[26])answer  = cp_answer[26];
197 |         else if(cp_answer_found[27])answer  = cp_answer[27];
198 |         else if(cp_answer_found[28])answer  = cp_answer[28];
199 |         else if(cp_answer_found[29])answer  = cp_answer[29];
200 |         else if(cp_answer_found[30])answer  = cp_answer[30];
201 |         else if(cp_answer_found[31])answer  = cp_answer[31];
202 |         else answer = 32'hffff_ffff;
203 |     end
204 | 
205 | 
206 | endmodule
207 | 


--------------------------------------------------------------------------------
/Lab_10/arty_lab10.xdc:
--------------------------------------------------------------------------------
  1 | ## This file is a general .xdc for the ARTY Rev. A
  2 | ## To use it in a project:
  3 | ## - uncomment the lines corresponding to used pins
  4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
  5 | 
  6 | 
  7 | # Clock signal
  8 | 
  9 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk];
 10 | create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk];
 11 | 
 12 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports reset_n];
 13 | 
 14 | #Switches
 15 | 
 16 | #set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { usr_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0];
 17 | #set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { usr_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1];
 18 | #set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { usr_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2];
 19 | #set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { usr_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3];
 20 | 
 21 | 
 22 | # LEDs
 23 | 
 24 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {usr_led[0]}];
 25 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {usr_led[1]}];
 26 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {usr_led[2]}];
 27 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {usr_led[3]}];
 28 | 
 29 | 
 30 | #Buttons
 31 | 
 32 | set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[0]}];
 33 | set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[1]}];
 34 | set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[2]}];
 35 | set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS33} [get_ports {usr_btn[3]}];
 36 | 
 37 | #UART
 38 | #set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
 39 | #set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
 40 | 
 41 | ##ChipKit Digital I/O Low
 42 | 
 43 | #set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
 44 | #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
 45 | #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
 46 | #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
 47 | #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
 48 | #set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
 49 | #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
 50 | #set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LCD_RS   }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
 51 | #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LCD_RW   }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
 52 | #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LCD_E    }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
 53 | #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[0] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
 54 | #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[1] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
 55 | #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[2] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
 56 | #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[3] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
 57 | 
 58 | ##ChipKit Digital I/O High
 59 | 
 60 | #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
 61 | #set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
 62 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { VGA_HSYNC }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
 63 | set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { VGA_VSYNC }]; #IO_25_14 Sch=ck_io[29]
 64 | set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[0] }]; #IO_0_14 Sch=ck_io[30]
 65 | set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[1] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
 66 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[2] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
 67 | set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[3] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
 68 | set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[0] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
 69 | set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[1] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
 70 | set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[2] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
 71 | set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[3] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
 72 | set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[0] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
 73 | set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[1] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
 74 | set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[2] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
 75 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[3] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
 76 | 
 77 | ##Misc. ChipKit signals
 78 | 
 79 | #set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
 80 | #set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
 81 | 
 82 | ## ChipKit SPI
 83 | 
 84 | #set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { spi_miso }]; #IO_L17N_T2_35 Sch=ck_miso
 85 | #set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { spi_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
 86 | #set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { spi_sck }]; #IO_L18P_T2_35 Sch=ck_sck
 87 | #set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { spi_ss }]; #IO_L16N_T2_35 Sch=ck_ss
 88 | 
 89 | ## ChipKit I2C
 90 | 
 91 | #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
 92 | #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
 93 | #set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
 94 | #set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
 95 | 
 96 | 
 97 | ##SMSC Ethernet PHY
 98 | 
 99 | #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
100 | #set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
101 | #set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
102 | #set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
103 | #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
104 | #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
105 | #set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
106 | #set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
107 | #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
108 | #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
109 | #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
110 | #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
111 | #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
112 | #set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
113 | #set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
114 | #set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
115 | #set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
116 | #set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
117 | #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
118 | 
119 | 
120 | ##Quad SPI Flash
121 | 
122 | #set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
123 | #set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
124 | #set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
125 | #set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
126 | #set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
127 | 
128 | 
129 | ##Power Analysis
130 | 
131 | #set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { sns0v_n[95] }]; #IO_L8N_T1_AD10N_15 Sch=sns0v_n[95]
132 | #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { sns0v_p[95] }]; #IO_L8P_T1_AD10P_15 Sch=sns0v_p[95]
133 | #set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { sns5v_n[0] }]; #IO_L5N_T0_AD9N_15 Sch=sns5v_n[0]
134 | #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { sns5v_p[0] }]; #IO_L5P_T0_AD9P_15 Sch=sns5v_p[0]
135 | #set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { vsns5v[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=vsns5v[0]
136 | #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { vsnsvu }]; #IO_L7P_T1_AD2P_15 Sch=vsnsvu
137 | 
138 | set_property CONFIG_VOLTAGE 3.3 [current_design]
139 | set_property CFGBVS VCCO [current_design]
140 | 


--------------------------------------------------------------------------------
/Lab_07/lab7.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: Dept. of CS, National Chiao Tung University
  4 | // Engineer: Chun-Jen Tsai
  5 | // 
  6 | // Create Date: 2017/04/27 15:06:57
  7 | // Design Name: UART I/O example for Arty
  8 | // Module Name: lab4
  9 | // Project Name: 
 10 | // Target Devices: Xilinx FPGA @ 100MHz
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // The parameters for the UART controller are 9600 baudrate, 8-N-1-N
 15 | //
 16 | // Dependencies: 
 17 | // 
 18 | // Revision:
 19 | // Revision 0.01 - File Created
 20 | // Additional Comments:
 21 | // 
 22 | //////////////////////////////////////////////////////////////////////////////////
 23 | 
 24 | module lab7(
 25 |   input  clk,
 26 |   input  reset_n,
 27 |   input  [3:0] usr_btn,
 28 |   output [3:0] usr_led,
 29 |   input  uart_rx,
 30 |   output uart_tx);
 31 | 
 32 | localparam [2:0] S_MAIN_INIT = 0;
 33 | localparam [2:0] S_MAIN_PROMPT = 1;
 34 | localparam [2:0] S_MAIN_WAIT_KEY = 2;
 35 | localparam [2:0] S_MAIN_CAL = 3;
 36 | localparam [2:0] S_MAIN_WRITE = 4;
 37 | localparam [2:0] S_MAIN_HELLO = 5;
 38 | 
 39 | localparam [1:0] S_UART_IDLE = 0, S_UART_WAIT = 1,
 40 |                  S_UART_SEND = 2, S_UART_INCR = 3;
 41 | localparam INIT_DELAY = 100_000; // 1 msec @ 100 MHz
 42 | localparam MEM_SIZE = 169;
 43 | localparam PROMPT_STR = 0;
 44 | localparam HELLO_STR = 22;
 45 | 
 46 | // declare system variables
 47 | wire print_enable, print_done;
 48 | reg [$clog2(MEM_SIZE):0] send_counter;
 49 | reg [2:0] P, P_next;
 50 | reg [1:0] Q, Q_next;
 51 | reg [$clog2(INIT_DELAY):0] init_counter;
 52 | reg [7:0] data[0:MEM_SIZE-1];
 53 | 
 54 | // declare UART signals
 55 | wire transmit;
 56 | wire received;
 57 | wire [7:0] rx_byte;
 58 | wire [7:0] tx_byte;
 59 | wire is_receiving;
 60 | wire is_transmitting;
 61 | wire recv_error;
 62 | 
 63 | //declare btn related signals
 64 | wire btn_level;
 65 | wire btn_pressed;
 66 | reg  prev_btn_level;
 67 | 
 68 |   // declare matrix_cal signals
 69 |   wire [287:0] matrix_cal_answer;
 70 |   wire matrix_cal_done;
 71 | /* The UART device takes a 100MHz clock to handle I/O at 9600 baudrate */
 72 | uart uart(
 73 |   .clk(clk),
 74 |   .rst(~reset_n),
 75 |   .rx(uart_rx),
 76 |   .tx(uart_tx),
 77 |   .transmit(transmit),
 78 |   .tx_byte(tx_byte),
 79 |   .received(received),
 80 |   .rx_byte(rx_byte),
 81 |   .is_receiving(is_receiving),
 82 |   .is_transmitting(is_transmitting),
 83 |   .recv_error(recv_error)
 84 | );
 85 | 
 86 | matrix_cal matrix_cal(
 87 | .clk(clk),
 88 | .rst_n(reset_n),
 89 | .btn(usr_btn),
 90 | .answer(matrix_cal_answer),
 91 | .done(matrix_cal_done)
 92 | );
 93 | 
 94 | debounce debounce(
 95 | .clk(clk),
 96 | .btn_input(usr_btn[1]),
 97 | .btn_output(btn_level)
 98 | );
 99 | 
100 | always @(posedge clk) begin
101 |     if (~reset_n)
102 |         prev_btn_level <= 0;
103 |     else
104 |         prev_btn_level <= btn_level;
105 | end
106 | 
107 | assign btn_pressed = (btn_level == 1 && prev_btn_level == 0)? 1 : 0;
108 | // Initializes some strings.
109 | // System Verilog has an easier way to initialize an array,
110 | // but we are using Verilog 2005 :(
111 | //
112 | initial begin
113 | 
114 |     { data[ 0], data[ 1], data[ 2], data[ 3], data[ 4], data[ 5], data[ 6], data[ 7],
115 |       data[ 8], data[ 9], data[10], data[11], data[12], data[13], data[14], data[15],
116 |       data[16], data[17], data[18], data[19], data[20], data[21] }
117 |     <= { 8'h0D, 8'h0A, "Press BTN1 to start", 8'h00 };
118 | 
119 | 
120 |     { data[ 22], data[ 23], data[ 24], data[ 25], data[ 26], data[ 27], data[ 28], data[ 29], 
121 |       data[ 30], data[ 31], data[ 32], data[ 33], data[ 34], data[ 35], data[ 36], data[ 37], 
122 |       data[ 38], data[ 39], data[ 40], data[ 41], data[ 42], data[ 43], data[ 44], data[ 45], 
123 |       data[ 46], data[ 47], data[ 48], data[ 49], data[ 50], data[ 51], data[ 52], data[ 53], 
124 |       data[ 54], data[ 55], data[ 56], data[ 57], data[ 58], data[ 59], data[ 60], data[ 61], 
125 |       data[ 62], data[ 63], data[ 64], data[ 65], data[ 66], data[ 67], data[ 68], data[ 69], 
126 |       data[ 70], data[ 71], data[ 72], data[ 73], data[ 74], data[ 75], data[ 76], data[ 77],
127 |       data[ 78], data[ 79], data[ 80], data[ 81], data[ 82], data[ 83], data[ 84], data[ 85], 
128 |       data[ 86], data[ 87], data[ 88], data[ 89], data[ 90], data[ 91], data[ 92], data[ 93], 
129 |       data[ 94], data[ 95], data[ 96], data[ 97], data[ 98], data[ 99], data[100], data[101], 
130 |       data[102], data[103], data[104], data[105], data[106], data[107], data[108], data[109], 
131 |       data[110], data[111], data[112], data[113], data[114], data[115], data[116], data[117], 
132 |       data[118], data[119], data[120], data[121], data[122], data[123], data[124], data[125],
133 |       data[126], data[127], data[128], data[129], data[130], data[131], data[132], data[133], 
134 |       data[134], data[135], data[136], data[137], data[138], data[139], data[140], data[141], 
135 |       data[142], data[143], data[144], data[145], data[146], data[147], data[148], data[149], 
136 |       data[150], data[151], data[152], data[153], data[154], data[155], data[156], data[157], 
137 |       data[158], data[159], data[160], data[161], data[162], data[163], data[164], data[165], 
138 |       data[166], data[167], data[168] }
139 |     <= { 8'h0D, 8'h0A, "The result is:", 8'h0D, 8'h0A,
140 |         "[ ", "00001, ", "00002, ", "00003, ", "00004", " ]", 8'h0D, 8'h0A,
141 |         "[ ", "00005, ", "00006, ", "00007, ", "00008", " ]", 8'h0D, 8'h0A,
142 |         "[ ", "00009, ", "00010, ", "00011, ", "00012", " ]", 8'h0D, 8'h0A,
143 |         "[ ", "00013, ", "00014, ", "00015, ", "00016", " ]", 8'h0D, 8'h0A, 8'h00 };
144 | 
145 |   end
146 | 
147 |   always @(posedge clk ) begin
148 |       if(P == S_MAIN_WRITE)
149 |         { data[ 42], data[ 43], data[ 44], data[ 45], data[ 46] } <= BtoA(matrix_cal_answer[  0+:18]);
150 |         { data[ 49], data[ 50], data[ 51], data[ 52], data[ 53] } <= BtoA(matrix_cal_answer[ 18+:18]);
151 |         { data[ 56], data[ 57], data[ 58], data[ 59], data[ 60] } <= BtoA(matrix_cal_answer[ 36+:18]);
152 |         { data[ 63], data[ 64], data[ 65], data[ 66], data[ 67] } <= BtoA(matrix_cal_answer[ 54+:18]);
153 |         { data[ 74], data[ 75], data[ 76], data[ 77], data[ 78] } <= BtoA(matrix_cal_answer[ 72+:18]);
154 |         { data[ 81], data[ 82], data[ 83], data[ 84], data[ 85] } <= BtoA(matrix_cal_answer[ 90+:18]);
155 |         { data[ 88], data[ 89], data[ 90], data[ 91], data[ 92] } <= BtoA(matrix_cal_answer[108+:18]);
156 |         { data[ 95], data[ 96], data[ 97], data[ 98], data[ 99] } <= BtoA(matrix_cal_answer[126+:18]);
157 |         { data[106], data[107], data[108], data[109], data[110] } <= BtoA(matrix_cal_answer[144+:18]);
158 |         { data[113], data[114], data[115], data[116], data[117] } <= BtoA(matrix_cal_answer[162+:18]);
159 |         { data[120], data[121], data[122], data[123], data[124] } <= BtoA(matrix_cal_answer[180+:18]);
160 |         { data[127], data[128], data[129], data[130], data[131] } <= BtoA(matrix_cal_answer[198+:18]);
161 |         { data[138], data[139], data[140], data[141], data[142] } <= BtoA(matrix_cal_answer[216+:18]);
162 |         { data[145], data[146], data[147], data[148], data[149] } <= BtoA(matrix_cal_answer[234+:18]);
163 |         { data[152], data[153], data[154], data[155], data[156] } <= BtoA(matrix_cal_answer[252+:18]);
164 |         { data[159], data[160], data[161], data[162], data[163] } <= BtoA(matrix_cal_answer[270+:18]);
165 |   end 
166 | 
167 | 
168 | function [39:0] BtoA;
169 |   input[17:0] binary;
170 | 
171 |   begin
172 |   BtoA[ 0+:8] = binarytoAscii(binary[0+:4]);
173 |   BtoA[ 8+:8] = binarytoAscii(binary[4+:4]);
174 |   BtoA[16+:8] = binarytoAscii(binary[8+:4]);
175 |   BtoA[24+:8] = binarytoAscii(binary[12+:4]);
176 |   BtoA[32+:8] = binarytoAscii(binary[17:16]);
177 | end
178 | 
179 | endfunction
180 | 
181 | function[7:0] binarytoAscii;
182 |   input [3:0] binary;
183 |   begin
184 |   binarytoAscii = (binary>9)?"A"+binary-10:"0"+binary;
185 |   end
186 | endfunction
187 | 
188 | // Combinational I/O logics
189 | assign usr_led = usr_btn;
190 | assign tx_byte = data[send_counter];
191 | 
192 | // ------------------------------------------------------------------------
193 | // Main FSM that reads the UART input and triggers
194 | // the output of the string "Hello, World!".
195 | always @(posedge clk) begin
196 |   if (~reset_n) P <= S_MAIN_INIT;
197 |   else P <= P_next;
198 | end
199 | 
200 | always @(*) begin // FSM next-state logic
201 |   case (P)
202 |     S_MAIN_INIT: // Wait for initial delay of the circuit.
203 | 	   if (init_counter < INIT_DELAY) P_next = S_MAIN_INIT;
204 | 		else P_next = S_MAIN_PROMPT;
205 |     S_MAIN_PROMPT: // Print the prompt message.
206 |       if (print_done) P_next = S_MAIN_WAIT_KEY;
207 |       else P_next = S_MAIN_PROMPT;
208 |     S_MAIN_WAIT_KEY: // wait for <Enter> key.
209 |       if (btn_pressed) P_next = S_MAIN_CAL;
210 |       else P_next = S_MAIN_WAIT_KEY;
211 | 
212 |     S_MAIN_CAL:P_next = (matrix_cal_done)?S_MAIN_WRITE:S_MAIN_CAL;
213 | 
214 |     S_MAIN_WRITE:P_next = S_MAIN_HELLO;
215 | 
216 |     S_MAIN_HELLO: // Print the hello message.
217 |       if (print_done) P_next = S_MAIN_INIT;
218 |       else P_next = S_MAIN_HELLO;
219 |   endcase
220 | end
221 | 
222 | // FSM output logics: print string control signals.
223 | 
224 | assign print_enable = (P != S_MAIN_PROMPT && P_next == S_MAIN_PROMPT) ||
225 |                   (P == S_MAIN_WRITE && P_next == S_MAIN_HELLO);
226 | assign print_done = (tx_byte == 8'h0);
227 | 
228 | // Initialization counter.
229 | always @(posedge clk) begin
230 |   if (P == S_MAIN_INIT) init_counter <= init_counter + 1;
231 |   else init_counter <= 0;
232 | end
233 | // End of the FSM of the print string controller
234 | // ------------------------------------------------------------------------
235 | 
236 | // ------------------------------------------------------------------------
237 | // FSM of the controller to send a string to the UART.
238 | always @(posedge clk) begin
239 |   if (~reset_n) Q <= S_UART_IDLE;
240 |   else Q <= Q_next;
241 | end
242 | 
243 | always @(*) begin // FSM next-state logic
244 |   case (Q)
245 |     S_UART_IDLE: // wait for the print_string flag
246 |       if (print_enable) Q_next = S_UART_WAIT;
247 |       else Q_next = S_UART_IDLE;
248 |     S_UART_WAIT: // wait for the transmission of current data byte begins
249 |       if (is_transmitting == 1) Q_next = S_UART_SEND;
250 |       else Q_next = S_UART_WAIT;
251 |     S_UART_SEND: // wait for the transmission of current data byte finishes
252 |       if (is_transmitting == 0) Q_next = S_UART_INCR; // transmit next character
253 |       else Q_next = S_UART_SEND;
254 |     S_UART_INCR:
255 |       if (tx_byte == 8'h0) Q_next = S_UART_IDLE; // string transmission ends
256 |       else Q_next = S_UART_WAIT;
257 |   endcase
258 | end
259 | 
260 | // FSM output logics
261 | assign transmit = (Q_next == S_UART_WAIT || print_enable);
262 | assign tx_byte = data[send_counter];
263 | 
264 | // UART send_counter control circuit
265 | always @(posedge clk) begin
266 |   case (P_next)
267 |     S_MAIN_INIT: send_counter <= PROMPT_STR;
268 |     S_MAIN_WAIT_KEY: send_counter <= HELLO_STR;
269 |     default: send_counter <= send_counter + (Q_next == S_UART_INCR);
270 |   endcase
271 | end
272 | // End of the FSM of the print string controller
273 | 
274 | 
275 | endmodule
276 | 


--------------------------------------------------------------------------------
/Lab_04/lab4.xdc:
--------------------------------------------------------------------------------
  1 | ## This file is a general .xdc for the ARTY Rev. A
  2 | ## To use it in a project:
  3 | ## - uncomment the lines corresponding to used pins
  4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
  5 | 
  6 | 
  7 | # Clock signal
  8 | 
  9 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
 10 | create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
 11 | 
 12 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports reset_n]
 13 | 
 14 | #Switches
 15 | 
 16 | #set_property -dict { PACKAGE_PIN A8  IOSTANDARD LVCMOS33 } [get_ports { usr_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
 17 | #set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { usr_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
 18 | #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { usr_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
 19 | #set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { usr_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
 20 | 
 21 | 
 22 | # LEDs
 23 | 
 24 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {usr_led[0]}]
 25 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {usr_led[1]}]
 26 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {usr_led[2]}]
 27 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {usr_led[3]}]
 28 | #set_property -dict { PACKAGE_PIN E1  IOSTANDARD LVCMOS33 } [get_ports { rgb_led[0] }]; #IO_L18N_T2_35 Sch=led0_b
 29 | #set_property -dict { PACKAGE_PIN F6  IOSTANDARD LVCMOS33 } [get_ports { rgb_led[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
 30 | #set_property -dict { PACKAGE_PIN G6  IOSTANDARD LVCMOS33 } [get_ports { rgb_led[2] }]; #IO_L19P_T3_35 Sch=led0_r
 31 | #set_property -dict { PACKAGE_PIN G4  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_b[1] }]; #IO_L20P_T3_35 Sch=led1_b
 32 | #set_property -dict { PACKAGE_PIN J4  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_g[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
 33 | #set_property -dict { PACKAGE_PIN G3  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_r[1] }]; #IO_L20N_T3_35 Sch=led1_r
 34 | #set_property -dict { PACKAGE_PIN H4  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_b[2] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
 35 | #set_property -dict { PACKAGE_PIN J2  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_g[2] }]; #IO_L22N_T3_35 Sch=led2_g
 36 | #set_property -dict { PACKAGE_PIN J3  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_r[2] }]; #IO_L22P_T3_35 Sch=led2_r
 37 | #set_property -dict { PACKAGE_PIN K2  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_b[3] }]; #IO_L23P_T3_35 Sch=led3_b
 38 | #set_property -dict { PACKAGE_PIN H6  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_g[3] }]; #IO_L24P_T3_35 Sch=led3_g
 39 | #set_property -dict { PACKAGE_PIN K1  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_r[3] }]; #IO_L23N_T3_35 Sch=led3_r
 40 | 
 41 | 
 42 | #Buttons
 43 | 
 44 | set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[0]}]
 45 | set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[1]}]
 46 | set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[2]}]
 47 | set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS33} [get_ports {usr_btn[3]}]
 48 | 
 49 | #UART
 50 | set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_tx]
 51 | set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_rx]
 52 | 
 53 | ##ChipKit Digital I/O Low
 54 | 
 55 | #set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
 56 | #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
 57 | #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
 58 | #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
 59 | #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
 60 | #set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
 61 | #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
 62 | #set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LCD_E }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
 63 | #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LCD_RW }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
 64 | #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LCD_RS }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
 65 | #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[3] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
 66 | #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[2] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
 67 | #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[1] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
 68 | #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[0] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
 69 | 
 70 | ##ChipKit Digital I/O High
 71 | 
 72 | #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
 73 | #set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
 74 | #set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { VGA_HSYNC }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
 75 | #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { VGA_VSYNC }]; #IO_25_14 Sch=ck_io[29]
 76 | #set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[0] }]; #IO_0_14 Sch=ck_io[30]
 77 | #set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[1] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
 78 | #set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[2] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
 79 | #set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[3] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
 80 | #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[0] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
 81 | #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[1] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
 82 | #set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[2] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
 83 | #set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[3] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
 84 | #set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[0] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
 85 | #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[1] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
 86 | #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[2] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
 87 | #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[3] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
 88 | 
 89 | ##Misc. ChipKit signals
 90 | 
 91 | #set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
 92 | #set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
 93 | 
 94 | ## ChipKit SPI
 95 | 
 96 | #set_property -dict { PACKAGE_PIN G1  IOSTANDARD LVCMOS33 } [get_ports { spi_miso }]; #IO_L17N_T2_35 Sch=ck_miso
 97 | #set_property -dict { PACKAGE_PIN H1  IOSTANDARD LVCMOS33 } [get_ports { spi_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
 98 | #set_property -dict { PACKAGE_PIN F1  IOSTANDARD LVCMOS33 } [get_ports { spi_sck }]; #IO_L18P_T2_35 Sch=ck_sck
 99 | #set_property -dict { PACKAGE_PIN C1  IOSTANDARD LVCMOS33 } [get_ports { spi_ss }]; #IO_L16N_T2_35 Sch=ck_ss
100 | 
101 | 
102 | ## ChipKit I2C
103 | 
104 | #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
105 | #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
106 | #set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
107 | #set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
108 | 
109 | 
110 | ##SMSC Ethernet PHY
111 | 
112 | #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
113 | #set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
114 | #set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
115 | #set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
116 | #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
117 | #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
118 | #set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
119 | #set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
120 | #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
121 | #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
122 | #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
123 | #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
124 | #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
125 | #set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
126 | #set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
127 | #set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
128 | #set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
129 | #set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
130 | #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
131 | 
132 | 
133 | ##Quad SPI Flash
134 | 
135 | #set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
136 | #set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
137 | #set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
138 | #set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
139 | #set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
140 | 
141 | 
142 | ##Power Analysis
143 | 
144 | #set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { sns0v_n[95] }]; #IO_L8N_T1_AD10N_15 Sch=sns0v_n[95]
145 | #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { sns0v_p[95] }]; #IO_L8P_T1_AD10P_15 Sch=sns0v_p[95]
146 | #set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { sns5v_n[0] }]; #IO_L5N_T0_AD9N_15 Sch=sns5v_n[0]
147 | #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { sns5v_p[0] }]; #IO_L5P_T0_AD9P_15 Sch=sns5v_p[0]
148 | #set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { vsns5v[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=vsns5v[0]
149 | #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { vsnsvu }]; #IO_L7P_T1_AD2P_15 Sch=vsnsvu
150 | 
151 | set_property CONFIG_VOLTAGE 3.3 [current_design]
152 | set_property CFGBVS VCCO [current_design]
153 | 
154 | 
155 | 
156 | 


--------------------------------------------------------------------------------
/Lab_07/lab7.xdc:
--------------------------------------------------------------------------------
  1 | ## This file is a general .xdc for the ARTY Rev. A
  2 | ## To use it in a project:
  3 | ## - uncomment the lines corresponding to used pins
  4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
  5 | 
  6 | 
  7 | # Clock signal
  8 | 
  9 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
 10 | create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
 11 | 
 12 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports reset_n]
 13 | 
 14 | #Switches
 15 | 
 16 | #set_property -dict { PACKAGE_PIN A8  IOSTANDARD LVCMOS33 } [get_ports { usr_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
 17 | #set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { usr_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
 18 | #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { usr_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
 19 | #set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { usr_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
 20 | 
 21 | 
 22 | # LEDs
 23 | 
 24 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {usr_led[0]}]
 25 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {usr_led[1]}]
 26 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {usr_led[2]}]
 27 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {usr_led[3]}]
 28 | #set_property -dict { PACKAGE_PIN E1  IOSTANDARD LVCMOS33 } [get_ports { rgb_led[0] }]; #IO_L18N_T2_35 Sch=led0_b
 29 | #set_property -dict { PACKAGE_PIN F6  IOSTANDARD LVCMOS33 } [get_ports { rgb_led[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
 30 | #set_property -dict { PACKAGE_PIN G6  IOSTANDARD LVCMOS33 } [get_ports { rgb_led[2] }]; #IO_L19P_T3_35 Sch=led0_r
 31 | #set_property -dict { PACKAGE_PIN G4  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_b[1] }]; #IO_L20P_T3_35 Sch=led1_b
 32 | #set_property -dict { PACKAGE_PIN J4  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_g[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
 33 | #set_property -dict { PACKAGE_PIN G3  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_r[1] }]; #IO_L20N_T3_35 Sch=led1_r
 34 | #set_property -dict { PACKAGE_PIN H4  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_b[2] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
 35 | #set_property -dict { PACKAGE_PIN J2  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_g[2] }]; #IO_L22N_T3_35 Sch=led2_g
 36 | #set_property -dict { PACKAGE_PIN J3  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_r[2] }]; #IO_L22P_T3_35 Sch=led2_r
 37 | #set_property -dict { PACKAGE_PIN K2  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_b[3] }]; #IO_L23P_T3_35 Sch=led3_b
 38 | #set_property -dict { PACKAGE_PIN H6  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_g[3] }]; #IO_L24P_T3_35 Sch=led3_g
 39 | #set_property -dict { PACKAGE_PIN K1  IOSTANDARD LVCMOS33 } [get_ports { rgb_led_r[3] }]; #IO_L23N_T3_35 Sch=led3_r
 40 | 
 41 | 
 42 | #Buttons
 43 | 
 44 | set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[0]}]
 45 | set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[1]}]
 46 | set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS33} [get_ports {usr_btn[2]}]
 47 | set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS33} [get_ports {usr_btn[3]}]
 48 | 
 49 | #UART
 50 | set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_tx]
 51 | set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_rx]
 52 | 
 53 | ##ChipKit Digital I/O Low
 54 | 
 55 | #set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
 56 | #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
 57 | #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
 58 | #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
 59 | #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
 60 | #set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
 61 | #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
 62 | #set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LCD_E }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
 63 | #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LCD_RW }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
 64 | #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LCD_RS }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
 65 | #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[3] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
 66 | #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[2] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
 67 | #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[1] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
 68 | #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { LCD_D[0] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
 69 | 
 70 | ##ChipKit Digital I/O High
 71 | 
 72 | #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
 73 | #set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
 74 | #set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { VGA_HSYNC }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
 75 | #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { VGA_VSYNC }]; #IO_25_14 Sch=ck_io[29]
 76 | #set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[0] }]; #IO_0_14 Sch=ck_io[30]
 77 | #set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[1] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
 78 | #set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[2] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
 79 | #set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { VGA_GREEN[3] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
 80 | #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[0] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
 81 | #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[1] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
 82 | #set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[2] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
 83 | #set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { VGA_BLUE[3] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
 84 | #set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[0] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
 85 | #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[1] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
 86 | #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[2] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
 87 | #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { VGA_RED[3] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
 88 | 
 89 | ##Misc. ChipKit signals
 90 | 
 91 | #set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
 92 | #set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
 93 | 
 94 | ## ChipKit SPI
 95 | 
 96 | #set_property -dict { PACKAGE_PIN G1  IOSTANDARD LVCMOS33 } [get_ports { spi_miso }]; #IO_L17N_T2_35 Sch=ck_miso
 97 | #set_property -dict { PACKAGE_PIN H1  IOSTANDARD LVCMOS33 } [get_ports { spi_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
 98 | #set_property -dict { PACKAGE_PIN F1  IOSTANDARD LVCMOS33 } [get_ports { spi_sck }]; #IO_L18P_T2_35 Sch=ck_sck
 99 | #set_property -dict { PACKAGE_PIN C1  IOSTANDARD LVCMOS33 } [get_ports { spi_ss }]; #IO_L16N_T2_35 Sch=ck_ss
100 | 
101 | 
102 | ## ChipKit I2C
103 | 
104 | #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
105 | #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
106 | #set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
107 | #set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
108 | 
109 | 
110 | ##SMSC Ethernet PHY
111 | 
112 | #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
113 | #set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
114 | #set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
115 | #set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
116 | #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
117 | #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
118 | #set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
119 | #set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
120 | #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
121 | #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
122 | #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
123 | #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
124 | #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
125 | #set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
126 | #set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
127 | #set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
128 | #set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
129 | #set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
130 | #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
131 | 
132 | 
133 | ##Quad SPI Flash
134 | 
135 | #set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
136 | #set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
137 | #set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
138 | #set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
139 | #set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
140 | 
141 | 
142 | ##Power Analysis
143 | 
144 | #set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { sns0v_n[95] }]; #IO_L8N_T1_AD10N_15 Sch=sns0v_n[95]
145 | #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { sns0v_p[95] }]; #IO_L8P_T1_AD10P_15 Sch=sns0v_p[95]
146 | #set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { sns5v_n[0] }]; #IO_L5N_T0_AD9N_15 Sch=sns5v_n[0]
147 | #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { sns5v_p[0] }]; #IO_L5P_T0_AD9P_15 Sch=sns5v_p[0]
148 | #set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { vsns5v[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=vsns5v[0]
149 | #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { vsnsvu }]; #IO_L7P_T1_AD2P_15 Sch=vsnsvu
150 | 
151 | set_property CONFIG_VOLTAGE 3.3 [current_design]
152 | set_property CFGBVS VCCO [current_design]
153 | 
154 | 
155 | 
156 | 
157 | 
158 | 
159 | 
160 | 
161 | 
162 | 
163 | 


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