├── .gitignore ├── Documentation └── spi_driver.docx ├── Kbuild ├── Makefile ├── README.md ├── bitmain-asic-drv.c ├── bitmain-asic.h ├── dts ├── am335x-ants5.dts ├── am335x-ants7.dts └── am335x-bitmain.dtsi ├── firmware ├── spitop_noncerev_ants5.fw └── spitop_noncerev_ants7.fw ├── fpga.c ├── fpga.h ├── set_pll.h ├── sha2.c ├── sha2.h ├── spi.c └── spi.h /.gitignore: -------------------------------------------------------------------------------- 1 | # 2 | # NOTE! Don't add files that are generated in specific 3 | # subdirectories here. Add them in the ".gitignore" file 4 | # in that subdirectory instead. 5 | # 6 | # NOTE! Please use 'git ls-files -i --exclude-standard' 7 | # command after changing this file, to see if there are 8 | # any tracked files which get ignored after the change. 9 | # 10 | # Normal rules 11 | # 12 | *.a 13 | *.bin 14 | *.bz2 15 | *.dtb 16 | *.dwo 17 | *.elf 18 | *.gcno 19 | *.gz 20 | *.i 21 | *.ko 22 | *.lst 23 | *.lz4 24 | *.lzma 25 | *.lzo 26 | *.mod.c 27 | *.o 28 | *.o.* 29 | *.order 30 | *.patch 31 | *.s 32 | *.so 33 | *.so.dbg 34 | *.su 35 | *.symtypes 36 | *.tar 37 | *.xz 38 | .* 39 | Module.symvers 40 | modules.builtin 41 | 42 | # 43 | # Top-level generic files 44 | # 45 | /Module.markers 46 | /System.map 47 | /TAGS 48 | /linux 49 | /tags 50 | /vmlinux 51 | /vmlinux-gdb.py 52 | /vmlinux.32 53 | /vmlinuz 54 | 55 | # 56 | # Debian directory (make deb-pkg) 57 | # 58 | /debian/ 59 | 60 | # 61 | # tar directory (make tar*-pkg) 62 | # 63 | /tar-install/ 64 | 65 | # 66 | # git files that we don't want to ignore even if they are dot-files 67 | # 68 | !.gitignore 69 | !.mailmap 70 | 71 | # 72 | # Generated include files 73 | # 74 | arch/*/include/generated 75 | include/config 76 | include/generated 77 | 78 | # stgit generated dirs 79 | patches-* 80 | 81 | # quilt's files 82 | patches 83 | series 84 | 85 | # cscope files 86 | cscope.* 87 | ncscope.* 88 | 89 | # gnu global files 90 | GPATH 91 | GRTAGS 92 | GSYMS 93 | GTAGS 94 | 95 | # id-utils files 96 | ID 97 | 98 | *.orig 99 | *~ 100 | \#*# 101 | 102 | # 103 | # Leavings from module signing 104 | # 105 | extra_certificates 106 | signing_key.pem 107 | signing_key.priv 108 | signing_key.x509 109 | x509.genkey 110 | 111 | # Kconfig presets 112 | all.config 113 | 114 | # Kdevelop4 115 | *.kdev4 116 | -------------------------------------------------------------------------------- /Documentation/spi_driver.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hashrabbit/bitmain-spi/ef008a051dda5aa7dcb4c1aa4856d33b79258765/Documentation/spi_driver.docx -------------------------------------------------------------------------------- /Kbuild: -------------------------------------------------------------------------------- 1 | obj-m := bitmain_spi.o 2 | bitmain_spi-y := bitmain-asic-drv.o fpga.o sha2.o spi.o 3 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for bitmain-spi 2 | # 3 | # Copyright (C) 2016 HashRabbit, Inc. - https://hashrabbit.co 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License version 2 as 7 | # published by the Free Software Foundation. 8 | 9 | DTC ?= dtc 10 | 11 | KERNEL_DIR ?= /lib/modules/$(shell uname -r)/build 12 | 13 | KERNEL_MAKE_OPTS += -C $(KERNEL_DIR) \ 14 | ARCH="$(ARCH)" \ 15 | CROSS_COMPILE="$(CROSS_COMPILE)" \ 16 | INSTALL_MOD_PATH="$(DESTDIR)" \ 17 | M="$(CURDIR)" 18 | 19 | .PHONY: all 20 | all: modules dtbs 21 | 22 | .PHONY: modules 23 | modules: 24 | make $(KERNEL_MAKE_OPTS) modules 25 | 26 | dtbs_SOURCES := $(wildcard dts/*.dts) 27 | dtbs_OBJECTS := $(dtbs_SOURCES:.dts=.dtb) 28 | 29 | .PHONY: dtbs 30 | dtbs: $(dtbs_OBJECTS) 31 | 32 | %.dtb: %.dts 33 | $(DTC) -i $(KERNEL_DIR)/arch/arm/boot/dts -I dts -O dtb -o $@ $^ 34 | 35 | .PHONY: install 36 | install: modules_install firmware_install 37 | 38 | .PHONY: modules_install 39 | modules_install: 40 | make $(KERNEL_MAKE_OPTS) modules_install 41 | 42 | .PHONY: firmware_install 43 | firmware_install: 44 | mkdir -p $(DESTDIR)/lib/firmware/bitmain 45 | cp -a firmware/* $(DESTDIR)/lib/firmware/bitmain/ 46 | 47 | .PHONY: clean 48 | clean: 49 | $(RM) dts/*.dtb 50 | make $(KERNEL_MAKE_OPTS) clean 51 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Bitmain SPI driver 2 | 3 | ## Supported Hardware 4 | 5 | * Antminer S5 6 | * Antminer S7 7 | 8 | Other models might be functional but haven't been tested. 9 | 10 | ## Building 11 | 12 | Build with: 13 | 14 | ``` 15 | make \ 16 | ARCH=arm \ 17 | CROSS_COMPILE=/path/to/toolchain/usr/bin/arm-none-linux-gnueabi- \ 18 | KERNEL_DIR=/path/to/linux-3.8.13/source 19 | ``` 20 | 21 | Install with: 22 | 23 | ``` 24 | make install \ 25 | DESTDIR=/path/to/target \ 26 | KERNEL_DIR=/path/to/linux-3.8.13/source 27 | ``` 28 | -------------------------------------------------------------------------------- /bitmain-asic-drv.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Bitmain asic driver 3 | * 4 | * Copyright (C) 2007-2008 Gabor Juhos 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License version 2 as 8 | * published by the Free Software Foundation. 9 | * 10 | * --------------------------------------------------------------------------- 11 | * 12 | */ 13 | 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | 31 | #include 32 | #include 33 | #include 34 | 35 | #include 36 | #include 37 | #include 38 | 39 | //#include 40 | //#include 41 | //#include 42 | #include "spi.h" 43 | #include "bitmain-asic.h" 44 | #include "sha2.h" 45 | #include "fpga.h" 46 | 47 | bool fpga_ret_prnt = false; 48 | bool rx_st_prnt = false; 49 | int check_state = 10; 50 | 51 | module_param(fpga_ret_prnt,bool,S_IRUGO); 52 | module_param(rx_st_prnt,bool,S_IRUGO); 53 | 54 | unsigned int hardware_version = 0; 55 | static unsigned long Prnt_time_out = 0; 56 | unsigned int GREEN, RED; 57 | static void Prnt(unsigned long data); 58 | static bool fan_custom = false; 59 | static uint8_t custom_fan = 0; 60 | void ChangePWM(BT_AS_INFO dev, unsigned int pwm_percent); 61 | 62 | #define DRV_NAME "bitmain-asic" 63 | #define DRV_DESC "Bitmain asic driver" 64 | #define DRV_VERSION "0.1.1" 65 | 66 | #define PRNT_TIMER_EN 1 67 | #define CHAIN_POWER_TIME_INTERAL 5 68 | 69 | 70 | #define TIMER_NUM 2 71 | #define TIMER_INTERRUPT (15 + TIMER_NUM) 72 | 73 | #define RESET_BASE (0x18000000 + 0x00060000) 74 | #define RESET_SIZE 0x100 75 | 76 | #define GENERAL_TIMER (0x94+8*(TIMER_NUM-1)) 77 | #define GENERAL_TIMER_RELOAD (GENERAL_TIMER + 0x04) 78 | //AHB 时钟200 MHz 79 | #define TIME_40MS (40*200*1000) 80 | 81 | //extern struct file_operations *bitmain_fops_p; 82 | 83 | 84 | // Add by Fazio, state machine 85 | enum TEMP_STATE{TEMP_NORMAL,TEMP_WARN,TEMP_OUT_STATE}; 86 | enum FAN_STATE{FAN_NORMAL,FAN_WARN,FAN_ERROR}; 87 | enum FIFO_STATE{FIFO_NORMAL,ALLFIFO_EMPTY}; 88 | enum CHAIN_STATE{CHAIN_NO_NONCE_TO,CHAIN_ERROR,CHAIN_NORMAL}; 89 | typedef void (* actiontype)(BT_AS_INFO); 90 | 91 | static bool if_temp_out_stop = false; 92 | 93 | 94 | unsigned int gNonce_num = 0, gNonce_Err = 0, gNonce_miss = 0, gDiff_nonce_num = 0, gSubmit_nonce_num = 0; 95 | uint32_t last_read_nonce_jiffies = 0; 96 | 97 | uint16_t gTotal_asic_num = 0; 98 | uint8_t gChain_Asic_Check_bit[CHAIN_SIZE] = {0}; 99 | uint8_t gChain_Asic_Interval[CHAIN_SIZE] = {0}; 100 | uint8_t gChain_Asic_num[CHAIN_SIZE] = {0}; 101 | uint32_t gChain_Asic_status[CHAIN_SIZE][256/32]; 102 | uint32_t gAsic_cnt[CHAIN_SIZE][256]; 103 | uint32_t Chain_nonce_nu[CHAIN_SIZE] = {0}; 104 | uint32_t Chain_nonce_nu_last[CHAIN_SIZE] = {0}; 105 | 106 | 107 | static unsigned char config_fpga = 0; 108 | 109 | #if PRNT_TIMER_EN 110 | static struct timer_list prnt_timer; 111 | #endif 112 | 113 | #if 0 114 | typedef struct __BT_AS_info 115 | { 116 | spinlock_t lock; 117 | struct mutex result_lock; 118 | void __iomem *virt_addr; 119 | unsigned irq; 120 | struct workqueue_struct *usb_wq; 121 | struct work_struct usb_sdata_work; 122 | struct delayed_work usb_rdata_work; 123 | ASIC_TASK_P task_buffer; 124 | unsigned char task_last_num; 125 | unsigned char task_current_num; 126 | unsigned int task_buffer_size; 127 | unsigned int task_buffer_wr; 128 | unsigned int task_buffer_rd; 129 | bool task_buffer_full; 130 | bool usb_opened; 131 | bool get_status; 132 | ASIC_CONFIGURE asic_configure; 133 | struct BITMAIN_STATUS_DATA asic_status_data; 134 | }*BT_AS_INFO; 135 | #endif 136 | 137 | struct __BT_AS_info bitmain_asic_dev; 138 | struct inode bitmain_inode; 139 | struct file bitmain_file; 140 | 141 | static unsigned long bitmain_is_open; 142 | static void *gpio1_vaddr; 143 | void *gpio0_vaddr; 144 | uint8_t asic_return_bytes = 5; 145 | // -------------------------------------------------------------- 146 | // CRC16 check table 147 | // -------------------------------------------------------------- 148 | const uint8_t chCRCHTalbe[] = // CRC high byte table 149 | { 150 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 151 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 152 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 153 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 154 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 155 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 156 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 157 | 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 158 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 159 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 160 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 161 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 162 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 163 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 164 | 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 165 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 166 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 167 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 168 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 169 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 170 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 171 | 0x00, 0xC1, 0x81, 0x40 172 | }; 173 | 174 | const uint8_t chCRCLTalbe[] = // CRC low byte table 175 | { 176 | 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, 177 | 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 178 | 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 179 | 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, 180 | 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, 181 | 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, 182 | 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 183 | 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 184 | 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, 185 | 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, 186 | 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, 187 | 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 188 | 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 189 | 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, 190 | 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, 191 | 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, 192 | 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 193 | 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 194 | 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 195 | 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, 196 | 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, 197 | 0x41, 0x81, 0x80, 0x40 198 | }; 199 | uint16_t CRC16(const uint8_t* p_data, uint16_t w_len) 200 | { 201 | uint8_t chCRCHi = 0xFF; // CRC high byte initialize 202 | uint8_t chCRCLo = 0xFF; // CRC low byte initialize 203 | uint16_t wIndex = 0; // CRC cycling index 204 | 205 | while (w_len--) { 206 | wIndex = chCRCLo ^ *p_data++; 207 | chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex]; 208 | chCRCHi = chCRCLTalbe[wIndex]; 209 | } 210 | return ((chCRCHi << 8) | chCRCLo); 211 | } 212 | 213 | int cmd_check(uint8_t *data)//OK 1; failure 0 214 | { 215 | BITMAIN_TASK_P bt = (BITMAIN_TASK_P)data; 216 | uint16_t r_crc = 0; 217 | uint16_t crc = bt->crc; 218 | uint16_t length = 0; 219 | if(bt->token_type == BM_TX_TASK) 220 | { 221 | #if HAVE_NUM 222 | uint16_t len = 4 + bt->work_num*sizeof(struct ASIC_TASK); 223 | #else 224 | uint16_t len = le16_to_cpu(bt->length)+ 4 - 2; 225 | #endif 226 | crc = data[len] | (data[len+1]<<8); 227 | length = le16_to_cpu(bt->length) + 2; 228 | } 229 | else if(bt->token_type == BM_TX_CONF) 230 | { 231 | BITMAIN_CONFIGURE_P btc = (BITMAIN_CONFIGURE_P)data; 232 | length = btc->length+2; 233 | crc = cpu_to_le16(btc->crc); 234 | } 235 | else if(bt->token_type == BM_GET_STATUS) 236 | { 237 | BITMAIN_GET_STATUS_P bgs = (BITMAIN_GET_STATUS_P)data; 238 | length = bgs->length+2; 239 | crc = cpu_to_le16(bgs->crc); 240 | } 241 | else 242 | { 243 | printk_ratelimited("Tx token err {%#x}\n", bt->token_type); 244 | return 0; 245 | } 246 | if(crc == (r_crc=CRC16(data, length)))//length 去除了type和length 247 | { 248 | //rintf("OK: crc{%#x}r_crc{%#x}\n", crc, r_crc); 249 | return 1; 250 | } 251 | else 252 | { 253 | printk_ratelimited("Err:token{%#x} crc{%#x}r_crc{%#x}len{%#x}\n", 254 | bt->token_type, crc, r_crc,length); 255 | if(bt->token_type == BM_TX_TASK) 256 | { 257 | #if HAVE_NUM 258 | printk_ratelimited("work_num {%d}\n", bt->work_num); 259 | #else 260 | printk_ratelimited("work_num {%d}\n", (le16_to_cpu(bt->length) - 6)/sizeof(struct ASIC_TASK)); 261 | #endif 262 | } 263 | return 0; 264 | } 265 | } 266 | inline void increase_variable_rehead_U32(uint32_t *num, uint32_t all_size) 267 | { 268 | *num = *num + 1; 269 | if (*num >= all_size) 270 | *num = 0; 271 | return; 272 | } 273 | 274 | extern void dump_hex(uint8_t *data, uint16_t len) 275 | { 276 | uint16_t i; 277 | for(i = 0; i < len; i++) 278 | { 279 | if(0 == (i%16)) 280 | printk_ratelimited("\n0x%04x: ", i); 281 | printk_ratelimited("0x%02x ", data[i]); 282 | } 283 | printk_ratelimited("\n"); 284 | } 285 | 286 | static __inline void flip80(void *dest_p, const void *src_p) 287 | { 288 | uint32_t *dest = dest_p; 289 | const uint32_t *src = src_p; 290 | int i; 291 | 292 | for (i = 0; i < 20; i++) 293 | dest[i] = swab32(src[i]); 294 | } 295 | 296 | static __inline void flip32(void *dest_p, const void *src_p) 297 | { 298 | uint32_t *dest = dest_p; 299 | const uint32_t *src = src_p; 300 | int i; 301 | 302 | for (i = 0; i < 8; i++) 303 | dest[i] = swab32(src[i]); 304 | } 305 | 306 | static __inline void flip_swab(void *dest_p, const void *src_p, unsigned int length) 307 | { 308 | uint32_t *dest = dest_p; 309 | const uint32_t *src = src_p; 310 | int i; 311 | 312 | for (i = 0; i < length/4; i++) 313 | dest[i] = swab32(src[i]); 314 | } 315 | 316 | #if 1 317 | const char g_full_data[] = { "0000000258007a06037bb0c899e253afc369f10c9e7762a8aa73d33b00000034000000009d5146878f7fda9f7f7f76f1c1aa6751f679e3aff3f722b2030b0eac" 318 | "814f5d975201f3ba1972dbf2" 319 | "ae319135" 320 | "000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000" 321 | }; 322 | #if 0 323 | //midstate data向芯片发送不需要反 324 | const char g_midstate[] = {"2e26c4440504a801393d373204e87cc02828ba7fd6f191add1b0ff01a9302ac0"};//需要反序 (现在左侧为高位，右侧为低位 ) 325 | const char g_data[] = {"f2db7219baf30152975d4f81"}; 326 | //asic return 35 91 31 ae反序比较 327 | const char g_nonce[] = {"359131ae"}; 328 | #else 329 | const char g_midstate[] = {"4679ba4ec99876bf4bfe086082b400254df6c356451471139a3afa71e48f544a"}; 330 | const char g_data[] = {"87320b1a1426674f2fa722ce"}; 331 | //asic return 00 01 87 a2 332 | const char g_nonce[] = "000187a2"; 333 | #endif 334 | #else 335 | const char g_full_data[] = { "0000000258007a06037bb0c899e253afc369f10c9e7762a8aa73d33b00000034000000009d5146878f7fda9f7f7f76f1c1aa6751f679e3aff3f722b2030b0eac" 336 | "814f5d975201f3ba1972dbf2" 337 | "ae319135" 338 | "000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000" 339 | }; 340 | const char g_midstate[] = {"9a91ac02214239593aadae3e0e1ce8c6c8a7509542148383653981d2698b67c1"};//需要反序 (现在左侧为高位，右侧为低位 ) 341 | const char g_data[] = {"29a4001a4edce351072fb87f"}; 342 | const char g_nonce[] = {"92ec9b6e"}; 343 | #endif 344 | 345 | #define test_DHASH 0 346 | 347 | // Returns 1 if meets current buffer work, 0 if last buffer work 348 | extern int hashtest(ASIC_TASK_P asic_task, uint32_t nonce) 349 | { 350 | BT_AS_INFO dev = &bitmain_asic_dev; 351 | unsigned char hash1[32]; 352 | unsigned char hash2[32]; 353 | unsigned char i; 354 | uint32_t *hash2_32 = (uint32_t *)hash1; 355 | __attribute__ ((aligned (4))) sha2_context ctx; 356 | memcpy(ctx.state, (void*)asic_task->midstate, 32); 357 | #if test_DHASH 358 | rev((unsigned char*)ctx.state, sizeof(ctx.state)); 359 | #endif 360 | ctx.total[0] = 80; 361 | ctx.total[1] = 00; 362 | memcpy(hash1, (void*)asic_task->data, 12); 363 | #if test_DHASH 364 | rev(hash1, 12); 365 | #endif 366 | flip_swab(ctx.buffer, hash1, 12); 367 | memcpy(hash1, &nonce, 4); 368 | #if test_DHASH 369 | rev(hash1, 4); 370 | #endif 371 | flip_swab(ctx.buffer + 12, hash1, 4); 372 | 373 | sha2_finish( &ctx, hash1); 374 | 375 | memset( &ctx, 0, sizeof( sha2_context ) ); 376 | sha2(hash1, 32, hash2); 377 | 378 | flip32(hash1, hash2); 379 | if (hash2_32[7] != 0) { 380 | //printk_ratelimited("nonce error\n"); 381 | return 0; 382 | } 383 | else if( dev->nonce_diff !=0 ) 384 | { 385 | for(i=0; i < dev->asic_configure.diff_sh_bit/32; i++) 386 | { 387 | if(be32toh(hash2_32[6 - i]) != 0) 388 | break; 389 | } 390 | if(i == dev->asic_configure.diff_sh_bit/32) 391 | if(be32toh(hash2_32[6 - dev->asic_configure.diff_sh_bit/32]) < ((uint32_t)0xffffffff >> (dev->asic_configure.diff_sh_bit%32))) 392 | //if((hash2_32[6 - dev->asic_configure.diff_sh_bit/32] & ((0x01 << ((dev->asic_configure.diff_sh_bit)%32 + 1))-1)) == 0x00) 393 | { 394 | //printk_ratelimited(KERN_ERR "match diff %d hash2_32[%d]{0x%08x}\n", dev->asic_configure.diff_sh_bit, 395 | //6 - dev->asic_configure.diff_sh_bit/32,be32toh(hash2_32[6 - dev->asic_configure.diff_sh_bit/32])); 396 | //printk_ratelimited("diff cpare {0x%08x}\n", ((0x01 << ((dev->asic_configure.diff_sh_bit - 1)%32 + 1))-1)); 397 | gDiff_nonce_num++; 398 | dev->diff1_num += (0x01UL << dev->nonce_diff); 399 | dev->total_nonce_num++; 400 | if(dev->net_diff_sh_bit != 0) 401 | { 402 | 403 | for(i=0; i < dev->net_diff_sh_bit/32; i++) 404 | { 405 | if(be32toh(hash2_32[6 - i]) != 0) 406 | break; 407 | } 408 | if(i == dev->net_diff_sh_bit/32) 409 | { 410 | if(be32toh(hash2_32[6 - dev->net_diff_sh_bit/32]) < ((uint32_t)0xffffffff >> (dev->net_diff_sh_bit%32))) 411 | { 412 | printk_ratelimited(KERN_ERR "\n###Get Block##\n"); 413 | dev->get_blk_num++; 414 | struct timex txc; 415 | struct rtc_time tm; 416 | struct file *fp_pwerr; 417 | mm_segment_t old_fs; 418 | char wr_buf[1024]; 419 | unsigned int wr_len = 0; 420 | do_gettimeofday(&(txc.time)); 421 | rtc_time_to_tm(txc.time.tv_sec,&tm); 422 | printk_ratelimited("UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec); 423 | fp_pwerr = filp_open("/config/getblk", O_RDWR | O_CREAT | O_APPEND, 0644); 424 | wr_len = sprintf(wr_buf, "UTC time:%d-%d-%d %d:%d:%d %08x%08x%08x%08x%08x%08x%08x%08x\n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec, 425 | be32toh(hash2_32[7]),be32toh(hash2_32[6]),be32toh(hash2_32[5]),be32toh(hash2_32[4]), 426 | be32toh(hash2_32[3]),be32toh(hash2_32[2]),be32toh(hash2_32[1]),be32toh(hash2_32[0])); 427 | old_fs = get_fs(); 428 | set_fs(KERNEL_DS); 429 | fp_pwerr->f_op->write(fp_pwerr, (char *)wr_buf, wr_len, &fp_pwerr->f_pos); 430 | set_fs(old_fs); 431 | filp_close(fp_pwerr, NULL); 432 | } 433 | } 434 | } 435 | return 2; 436 | } 437 | else if(be32toh(hash2_32[6 - dev->nonce_diff/32]) < ((uint32_t)0xffffffff >> (dev->nonce_diff%32))) 438 | { 439 | dev->diff1_num += (0x01UL << dev->nonce_diff); 440 | dev->total_nonce_num++; 441 | } 442 | else 443 | printk_ratelimited(KERN_ERR "match1 diff %d hash2_32{0x%08x}\n", dev->nonce_diff, be32toh(hash2_32[6 - dev->nonce_diff/32])); 444 | return 1; 445 | } 446 | else 447 | { 448 | dev->diff1_num += (0x01UL << dev->asic_configure.diff_sh_bit); 449 | dev->total_nonce_num++; 450 | return 1; 451 | } 452 | if((dev->total_nonce_num & 0xffffffff) == 0xffffffff) 453 | dev->cgminer_start_time = jiffies; 454 | #if 0 455 | else if( dev->asic_configure.diff_sh_bit !=0 ) 456 | { 457 | if(htonl(hash2_32[6 - dev->asic_configure.diff_sh_bit/32]) < ((uint32_t)0xffffffff >> (dev->asic_configure.diff_sh_bit%32))) 458 | //if((hash2_32[6 - dev->asic_configure.diff_sh_bit/32] & ((0x01 << ((dev->asic_configure.diff_sh_bit)%32 + 1))-1)) == 0x00) 459 | { 460 | printk_ratelimited(KERN_ERR "match diff %d hash2_32[%d]{0x%08x}\n", dev->asic_configure.diff_sh_bit, 461 | 6 - dev->asic_configure.diff_sh_bit/32,htonl(hash2_32[6 - dev->asic_configure.diff_sh_bit/32])); 462 | //printk_ratelimited("diff cpare {0x%08x}\n", ((0x01 << ((dev->asic_configure.diff_sh_bit - 1)%32 + 1))-1)); 463 | gDiff_nonce_num++; 464 | dev->total_nonce_num += 0x01 << dev->asic_configure.diff_sh_bit; 465 | return 2; 466 | } 467 | else 468 | return 1; 469 | } 470 | else 471 | dev->total_nonce_num++; 472 | return 1; 473 | #endif 474 | #if 0 475 | unsigned char hash1[32]; 476 | unsigned char hash2[32]; 477 | uint32_t *hash2_32 = (uint32_t *)hash1; 478 | //uint8_t i; 479 | __attribute__ ((aligned (4))) sha2_context ctx; 480 | 481 | //memcpy(ctx.state, asic_task->midstate, 32); 482 | //rev((unsigned char*)ctx.state, sizeof(ctx.state)); 483 | 484 | memcpy(hash1, asic_task->midstate, 32); 485 | //rev(hash1, 32); 486 | //flip_swab(ctx.state, hash1, 32);// 487 | flip32(ctx.state, hash1); 488 | ctx.total[0] = 80; 489 | ctx.total[1] = 0; 490 | memcpy(hash1, (void*)asic_task->data, 12); 491 | //rev(hash1, 12); 492 | flip_swab(ctx.buffer, hash1, 12); 493 | memcpy(hash1, &nonce, 4); 494 | 495 | flip_swab(ctx.buffer + 12, hash1, 4); 496 | printk_ratelimited("ctx:"); 497 | dump_hex(&ctx,sizeof(ctx)); 498 | sha2_finish( &ctx, hash1); 499 | printk_ratelimited("hash1 in hashtest\n"); 500 | memset( &ctx, 0, sizeof( sha2_context ) ); 501 | sha2(hash1, 32, hash2); 502 | 503 | flip32(hash1, hash2); 504 | //printk_ratelimited("hash2_32[7]{%#x}hash2_32[0]{%#x}\n", hash2_32[7], hash2_32[0]); 505 | if (be32toh(hash2_32[7]) != 0) { 506 | printk_ratelimited("not work{%#x} nonce\n", le32_to_cpu(asic_task->work_id)); 507 | return 0; 508 | } 509 | return 1; 510 | #endif 511 | } 512 | 513 | 514 | 515 | /* Returns 1 if meets current buffer work, 0 if last buffer work 516 | extern int hashtest(ASIC_TASK_P asic_task, uint32_t nonce) 517 | { 518 | BT_AS_INFO dev = &bitmain_asic_dev; 519 | 520 | gDiff_nonce_num++; 521 | dev->diff1_num += (0x01UL << dev->nonce_diff); 522 | dev->total_nonce_num++; 523 | return 2; 524 | 525 | if((dev->total_nonce_num & 0xffffffff) == 0xffffffff) 526 | dev->cgminer_start_time = jiffies; 527 | } 528 | */ 529 | 530 | static int bitmain_asic_open(struct inode *inode, struct file *file) 531 | { 532 | struct file *fp_hwver; 533 | mm_segment_t old_fs; 534 | char wr_buf[512]; 535 | unsigned int wr_len = 0; 536 | BT_AS_INFO dev = &bitmain_asic_dev; 537 | void *gpio3_virtual, *gpio1_virtual; 538 | void *ctl_md_vaddr; 539 | uint32_t value32; 540 | uint32_t detect_ver = 0; 541 | uint32_t save_ver = 0; 542 | uint8_t i; 543 | /* only allow one at a time */ 544 | if (test_and_set_bit(0, &bitmain_is_open)) 545 | return -EBUSY; 546 | file->private_data = dev; 547 | memset(dev, 0, sizeof(bitmain_asic_dev)); 548 | #if 1 549 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 550 | //vesion ctl gpio3_19:bit 0 gpio3_21:bit1 gpio1_18 bit2 551 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9a4); //bit0 552 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9ac); //bit1 553 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x848); //bit2 554 | gpio3_virtual = ioremap_nocache(GPIO3_BASE, GPIO3_SIZE); 555 | gpio1_virtual = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE); 556 | value32 = ioread32(gpio3_virtual + GPIO_OE); 557 | iowrite32(value32 | (((0x01<<19) | (0x01<<21))), gpio3_virtual + GPIO_OE); //set input 558 | value32 = ioread32(gpio1_virtual + GPIO_OE); 559 | iowrite32(value32 | (0x01<<18), gpio1_virtual + GPIO_OE); //set input 560 | hardware_version = 0; 561 | value32 = ioread32(gpio3_virtual+ GPIO_DATAIN ); 562 | detect_ver |= ((value32 >> 19)&0x01)<<0x00; 563 | detect_ver |= ((value32 >> 21)&0x01)<<0x01; 564 | value32 = ioread32(gpio1_virtual+ GPIO_DATAIN ); 565 | detect_ver |= ((value32 >> 18)&0x01)<<0x02; 566 | printk_ratelimited("Detect hardware version = %d\n", detect_ver); 567 | hardware_version = detect_ver; 568 | #ifdef FIX_HARDWARE_VER 569 | printk_ratelimited("fix hardware version\n"); 570 | #if defined C1_02 || defined S5 571 | if((detect_ver == 0x03) || ((detect_ver == 0x04))) 572 | hardware_version = 0x01; 573 | else 574 | hardware_version = FIX_HARDWARE_VER; 575 | #elif defined S2 576 | ; 577 | #else 578 | hardware_version = FIX_HARDWARE_VER; 579 | #endif 580 | #endif 581 | save_ver = hardware_version; 582 | hardware_version = detect_ver; 583 | printk_ratelimited("hardware_version = %#x\n", hardware_version); 584 | 585 | fp_hwver = filp_open("/tmp/hwver", O_RDWR | O_CREAT | O_TRUNC, 0644); 586 | wr_len = sprintf(wr_buf, "hardware_ver = 0x%02x\n", hardware_version); 587 | old_fs = get_fs(); 588 | set_fs(KERNEL_DS); 589 | fp_hwver->f_op->write(fp_hwver, (char *)wr_buf, wr_len, &fp_hwver->f_pos); 590 | set_fs(old_fs); 591 | filp_close(fp_hwver, NULL); 592 | 593 | iounmap(gpio3_virtual); 594 | iounmap(gpio1_virtual); 595 | #if defined S2 596 | printk_ratelimited("S2 ctrl board V1.0\n"); 597 | #endif 598 | hardware_version = save_ver; 599 | if(hardware_version == 0x01) 600 | { 601 | //Set GPIO1_13(Green) GPIO0_23(Red) to GPIO mode 602 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x834); //Green 603 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x824); //Red 604 | #if defined C1_02 || defined S5 605 | //Set GPIO1_13(Red) GPIO0_23(Green) to GPIO mode 606 | if(detect_ver == 0x03) 607 | { 608 | GREEN = 0x01<<23; 609 | RED = 0x01<<13; 610 | printk_ratelimited("S5 ctrl board V1.0\n"); 611 | } 612 | else if(detect_ver == 0x04) 613 | { 614 | GREEN = 0x01<<23; 615 | RED = 0x01<<13; 616 | printk_ratelimited("S5 ctrl board test V1.1\n"); 617 | iowrite32(PAD_PULLUP | PAD_REV | 0x7, ctl_md_vaddr + 0x828); //ip sig key gpio0_26 618 | } 619 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x820); //hash test gpio0-22 620 | #else 621 | #if defined S4_PLUS 622 | iowrite32(PAD_PULLUP | PAD_REV | 0x7, ctl_md_vaddr + 0x828); //ip sig key gpio0_26 623 | #endif 624 | GREEN = 0x01<<13; 625 | RED = 0x01<<23; 626 | #endif 627 | } 628 | else if(hardware_version == 0x02) 629 | { 630 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x890); //Green 631 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x89C); //Red 632 | GREEN = 0x01<<5; 633 | RED = 0x01<<2; 634 | } 635 | else 636 | { 637 | //Set GPIO2_2(Green) GPIO2_5(Red) to GPIO mode 638 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x890); //Green 639 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x89C); //Red 640 | GREEN = 0x01<<2; 641 | RED = 0x01<<5; 642 | } 643 | #if defined C1_02 644 | if(hardware_version == 0x02) //GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3 645 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x894); //recovery key 646 | else 647 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x838); //recovery key 648 | #else 649 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x838); //recovery key 650 | #endif 651 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x950); //test key 652 | //iounmap(ctl_md_vaddr); 653 | #endif 654 | if(hardware_version == 0x01) 655 | { 656 | #if defined C1_02 || defined S5 657 | if((detect_ver == 0x03) || (detect_ver == 0x04)) 658 | { 659 | dev->led_virtual1 = ioremap_nocache(GPIO0_BASE, GPIO0_SIZE); //green 660 | value32 = ioread32(dev->led_virtual1 + GPIO_OE); 661 | iowrite32(value32 & (~(GREEN)), dev->led_virtual1 + GPIO_OE); //set output 662 | dev->led_virtual = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE); //red 663 | value32 = ioread32(dev->led_virtual + GPIO_OE); 664 | iowrite32(value32 & (~(RED)), dev->led_virtual + GPIO_OE); //set output 665 | } 666 | else 667 | #endif 668 | { 669 | dev->led_virtual1 = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE); 670 | value32 = ioread32(dev->led_virtual1 + GPIO_OE); 671 | iowrite32(value32 & (~(GREEN)), dev->led_virtual1 + GPIO_OE); //set output 672 | dev->led_virtual = ioremap_nocache(GPIO0_BASE, GPIO0_SIZE); 673 | value32 = ioread32(dev->led_virtual + GPIO_OE); 674 | iowrite32(value32 & (~(RED)), dev->led_virtual + GPIO_OE); //set output 675 | } 676 | } 677 | else 678 | { 679 | dev->led_virtual = ioremap_nocache(GPIO2_BASE, GPIO2_SIZE); 680 | value32 = ioread32(dev->led_virtual + GPIO_OE); 681 | iowrite32(value32 & (~(GREEN)), dev->led_virtual + GPIO_OE); //set output 682 | value32 = ioread32(dev->led_virtual + GPIO_OE); 683 | iowrite32(value32 & (~(RED)), dev->led_virtual + GPIO_OE); //set output 684 | } 685 | dev->task_buffer_size = TASK_BUFFER_NUMBER + TASK_PRE_LEFT; 686 | dev->task_buffer = (ASIC_TASK_P)kmalloc(sizeof(*dev->task_buffer)*dev->task_buffer_size, GFP_KERNEL); 687 | //dev->task_buffer_wr = 10; 688 | dev->asic_status_data.data_type = BM_STATUS_DATA; 689 | dev->asic_status_data.version= 0x00; 690 | dev->asic_status_data.chain_num = CHAIN_SIZE; 691 | dev->asic_configure.diff_sh_bit = 0; 692 | dev->send_to_fpga_interval = 500; 693 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 694 | dev->asic_status_data.chain_asic_num[i] = 32; 695 | spin_lock_init(&dev->lock); 696 | mutex_init(&dev->result_lock); 697 | mutex_init(&dev->to_work_lock); 698 | dev->asic_configure.timeout_data = 7; 699 | ChangePWM(dev, 0); 700 | //bitmain_set_voltage(dev, 0x0750); 701 | dev->last_nonce_timeout = 0; //挖矿时会响一下 702 | //detect_chain_num(dev); 703 | dev->send_to_fpga_work_wq = create_singlethread_workqueue(DRV_NAME); 704 | INIT_WORK(&dev->send_to_fpga_work, send_to_pfga_work); 705 | #if PRNT_TIMER_EN 706 | init_timer(&prnt_timer); 707 | prnt_timer.function = Prnt; 708 | prnt_timer.expires = jiffies + 500*HZ/1000; 709 | //add_timer(&prnt_timer); 710 | #endif 711 | init_beep(dev); 712 | 713 | value32 = ioread32(gpio0_vaddr + GPIO_OE); 714 | //iowrite32(0x01<<22, gpio0_vaddr + GPIO_SETDATAOUT); 715 | iowrite32(value32 & (~(0x01<<22)), gpio0_vaddr + GPIO_OE); //set output 716 | if(detect_ver == 0x04) 717 | { 718 | value32 = ioread32(gpio0_vaddr + GPIO_OE); 719 | //iowrite32(0x01<<22, gpio0_vaddr + GPIO_SETDATAOUT); 720 | iowrite32(value32 | (0x01<<26), gpio0_vaddr + GPIO_OE); //set input 721 | } 722 | 723 | printk_ratelimited(KERN_ERR "bitmain_asic_open ok\n"); 724 | return 0; 725 | } 726 | 727 | static int bitmain_asic_close(struct inode *inode, struct file *file) 728 | { 729 | BT_AS_INFO dev = &bitmain_asic_dev; 730 | //uint32_t i; 731 | //struct ASIC_TASK asic_task; 732 | wait_queue_head_t timeout_wq; 733 | init_waitqueue_head(&timeout_wq); 734 | #if PRNT_TIMER_EN 735 | del_timer(&prnt_timer); 736 | #endif 737 | destroy_workqueue(dev->send_to_fpga_work_wq); 738 | if(1) 739 | { 740 | #if 0 741 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 742 | { 743 | memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate)); 744 | memset(asic_task.data, 0x00, sizeof(asic_task.data)); 745 | if(i == 0) 746 | send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task); 747 | else 748 | send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task); 749 | } 750 | #endif 751 | stop_work_to_all_chain(dev); 752 | } 753 | //send_work_to_fpga(true, 0, dev, &asic_task); 754 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 755 | sleep_on_timeout(&timeout_wq, 100 * HZ/1000);//100ms 756 | dev->asic_configure.timeout_data = 7; 757 | dev->timeout_valid = true; 758 | ChangePWM(dev, 0); 759 | nonce_query(dev); 760 | dev->timeout_valid = false; 761 | if( dev->asic_configure.bauddiv != 26) 762 | { 763 | //iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 764 | set_baud(dev, 26); 765 | //iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 766 | bitmain_set_voltage(dev,0x0725); 767 | } 768 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 769 | //test 770 | iowrite32(0x01<<22, gpio0_vaddr + GPIO_CLEARDATAOUT); 771 | //close beep 772 | iowrite32(0x01<<20, gpio0_vaddr + GPIO_CLEARDATAOUT); 773 | iounmap(dev->beep_virtual_addr); 774 | clear_bit(0, &bitmain_is_open); 775 | //bitmain_asic_open_usb(dev); 776 | kfree((void*)(dev->task_buffer)); 777 | //free_irq(TIMER_INTERRUPT, NULL); 778 | //spi_close(); 779 | printk_ratelimited(KERN_ERR "bitmain_asic_close\n"); 780 | return 0; 781 | } 782 | 783 | void stop_work_to_all_chain(BT_AS_INFO dev) 784 | { 785 | uint32_t i; 786 | struct ASIC_TASK asic_task; 787 | printk_ratelimited(KERN_ERR "stop send work to all chain\n"); 788 | memset(&asic_task, 0x00, sizeof(asic_task)); 789 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 790 | { 791 | memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate)); 792 | memset(asic_task.data, 0x00, sizeof(asic_task.data)); 793 | if(i == 0) 794 | send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task); 795 | else 796 | send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task); 797 | } 798 | } 799 | void check_chain_power(BT_AS_INFO dev) 800 | { 801 | uint32_t bgNonce_average; 802 | uint32_t time_elasp_ms = 0; 803 | uint32_t i; 804 | uint8_t chain_nu; 805 | //struct ASIC_TASK asic_task; 806 | static unsigned long simulate_power_err_time = 0; 807 | wait_queue_head_t timeout_wq; 808 | unsigned char cmd_buf[4] = {0}; 809 | if((dev->cgminer_start == true)) 810 | { 811 | if(simulate_power_err_time == 0) 812 | { 813 | simulate_power_err_time = jiffies + 5 * 60 * 1000 * HZ/1000; 814 | } 815 | time_elasp_ms = jiffies_to_msecs(jiffies - dev->cgminer_start_time); 816 | //printk_ratelimited("time_elasp_jiffies{%ld}\n", jiffies - dev->cgminer_start_time); 817 | //printk_ratelimited("jiffies{%ld}dev->cgminer_start_time{%ld}", jiffies, dev->cgminer_start_time); 818 | //printk_ratelimited("time_elasp_ms =%ldms dev->total_nonce_num{%ld}\n", time_elasp_ms, dev->total_nonce_num); 819 | //bgNonce_average = ((uint32_t)dev->total_nonce_num / (time_elasp_ms / 1000)) * (CHAIN_POWER_TIME_INTERAL*60);//平均5分钟 820 | if(dev->asic_status_data.chain_num !=0 ) 821 | bgNonce_average = (uint32_t)dev->total_nonce_num/dev->asic_status_data.chain_num; 822 | else 823 | bgNonce_average = (uint32_t)dev->total_nonce_num; 824 | if((time_elasp_ms / (1000 * CHAIN_POWER_TIME_INTERAL*60)) == 0) 825 | { 826 | if(bgNonce_average < 8) 827 | bgNonce_average = 1; 828 | else 829 | bgNonce_average /= 8; 830 | } 831 | else 832 | { 833 | bgNonce_average = bgNonce_average / (time_elasp_ms / (1000 * CHAIN_POWER_TIME_INTERAL*60));//平均5分钟 834 | bgNonce_average /= 8; 835 | } 836 | for (i = 0; i < dev->asic_status_data.chain_num; i++) 837 | { 838 | chain_nu = dev->chain_map[i]; 839 | //printk_ratelimited("bgNonce_average{%d}\n", bgNonce_average); 840 | //printk_ratelimited("chain%d Chain_nonce_nu[%ld] Chain_nonce_nu_last[%ld]\n", chain_nu,Chain_nonce_nu[chain_nu],Chain_nonce_nu_last[chain_nu]); 841 | if(Chain_nonce_nu[chain_nu] >= Chain_nonce_nu_last[chain_nu]) 842 | { 843 | if(((Chain_nonce_nu[chain_nu] - Chain_nonce_nu_last[chain_nu]) < bgNonce_average) || (bgNonce_average == 0)) 844 | //if(time_after(jiffies, simulate_power_err_time)) 845 | { 846 | struct timex txc; 847 | struct rtc_time tm; 848 | struct file *fp_pwerr; 849 | mm_segment_t old_fs; 850 | char wr_buf[512]; 851 | unsigned int wr_len = 0; 852 | do_gettimeofday(&(txc.time)); 853 | rtc_time_to_tm(txc.time.tv_sec,&tm); 854 | //printk_ratelimited("UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec); 855 | fp_pwerr = filp_open("/config/power_rst", O_RDWR | O_CREAT | O_APPEND, 0644); 856 | wr_len = sprintf(wr_buf, "UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec); 857 | old_fs = get_fs(); 858 | set_fs(KERNEL_DS); 859 | fp_pwerr->f_op->write(fp_pwerr, (char *)wr_buf, wr_len, &fp_pwerr->f_pos); 860 | set_fs(old_fs); 861 | filp_close(fp_pwerr, NULL); 862 | dev->restarting_hash = true; 863 | mod_timer(&prnt_timer, jiffies + 5 * 1000 * HZ/1000); 864 | i = 0; 865 | while(timer_pending(&prnt_timer)) 866 | { 867 | del_timer(&prnt_timer); 868 | if(i++ > 200) 869 | break; 870 | } 871 | if(bgNonce_average == 0) 872 | printk_ratelimited("!!!!!!!!!!----no hash power OK\n\n"); 873 | printk_ratelimited("remap chain%d(hardware chain%d) power err\n", i, chain_nu); 874 | printk_ratelimited("bgNonce_average{%d}chain_nonce_nu{%d}last{%d}\n", bgNonce_average, Chain_nonce_nu[chain_nu], Chain_nonce_nu_last[chain_nu]); 875 | #if 0 876 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 877 | { 878 | memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate)); 879 | memset(asic_task.data, 0x00, sizeof(asic_task.data)); 880 | if(i == 0) 881 | send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task); 882 | else 883 | send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task); 884 | } 885 | #endif 886 | stop_work_to_all_chain(dev); 887 | set_baud(dev, 26); 888 | printk_ratelimited(KERN_ERR "Detect device for anyone power err\n"); 889 | 890 | cmd_buf[0] = 9; 891 | cmd_buf[1] = 0x10; //16-23 892 | cmd_buf[2] = 0x1f; //8-13 893 | cmd_buf[0] |= 0x80; 894 | //cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5); 895 | cmd_buf[3] = 0x00; //故意错误crc 只是修改fpga 波特率 896 | send_BC_to_fpga(i, cmd_buf); 897 | 898 | rst_hash_asic(dev); 899 | //send_work_to_fpga(true, dev, &asic_task); 900 | clear_fpga_nonce_buffer(dev); 901 | init_waitqueue_head(&timeout_wq); 902 | interruptible_sleep_on_timeout(&timeout_wq, 1000 * HZ/1000);//300ms 903 | #if 1 904 | rst_hash_asic(dev); 905 | //send_work_to_fpga(true, dev, &asic_task); 906 | clear_fpga_nonce_buffer(dev); 907 | init_waitqueue_head(&timeout_wq); 908 | interruptible_sleep_on_timeout(&timeout_wq, 1100 * HZ/1000);//300ms 909 | #endif 910 | //detect_chain_num(dev); 911 | set_frequency(dev, dev->asic_configure.freq_vlaue); 912 | asic_result_status_rd = asic_result_status_wr = asic_result_status_full = 0; 913 | asic_result_rd = asic_result_wr = asic_result_full = 0; 914 | //gDiff_nonce_num = gNonce_num = gNonce_Err = gNonce_miss = 0; 915 | //gSubmit_nonce_num = 0; 916 | dev->restarting_hash = false; 917 | prnt_timer.expires = jiffies + dev->send_to_fpga_interval* HZ/1000; 918 | add_timer(&prnt_timer); 919 | mod_timer(&prnt_timer, jiffies + dev->send_to_fpga_interval* HZ/1000); 920 | simulate_power_err_time = 0; 921 | break; 922 | } 923 | } 924 | Chain_nonce_nu_last[chain_nu] = Chain_nonce_nu[chain_nu]; 925 | } 926 | } 927 | } 928 | 929 | #define MAX_ASIC_NUM 64 930 | 931 | void check_asic_status(BT_AS_INFO dev) 932 | { 933 | uint32_t bgNonce_average; 934 | uint32_t i, j; 935 | static uint32_t last_asic_nonce[CHAIN_SIZE][MAX_ASIC_NUM] = {0}; 936 | static uint32_t last_gNonce_num = 0; 937 | if ((dev->cgminer_start == true) && (gTotal_asic_num !=0)) 938 | { 939 | //printk_ratelimited(KERN_ERR "check_asic_status\n"); 940 | if (gNonce_num > gTotal_asic_num * 8) 941 | { 942 | if (gNonce_num > 0x7fffffff) 943 | { 944 | for (i = 0; i < CHAIN_SIZE; i++) 945 | { 946 | for (j = 0; j < gChain_Asic_num[i]; j++) 947 | { 948 | gAsic_cnt[i][j] >>= 2; 949 | last_asic_nonce[i][j] >>=2; 950 | } 951 | } 952 | gNonce_num >>= 2; 953 | last_gNonce_num >>=2; 954 | } 955 | 956 | bgNonce_average = (gNonce_num - last_gNonce_num )/ gTotal_asic_num / 8; 957 | last_gNonce_num = gNonce_num; 958 | for (i = 0; i < CHAIN_SIZE; i++) 959 | { 960 | for (j = 0; j < gChain_Asic_num[i]; j++) 961 | { 962 | if ((gAsic_cnt[i][j] - last_asic_nonce[i][j]) < bgNonce_average) 963 | { 964 | gChain_Asic_status[i][j/32] &= ~(0x01 << (j%32)); 965 | //printk_ratelimited("gNonce_num{%d}gAsic_cnt[%d][%d]{%d}\n", gNonce_num, i, j, gAsic_cnt[i][j]); 966 | } 967 | else 968 | { 969 | gChain_Asic_status[i][j/32] |= (0x01 << (j%32)); 970 | if((dev->chain_asic_exist[i][j/32] & (0x01 << (j%32))) == 0) 971 | dev->chain_asic_exist[i][j/32] |= (0x01 << (j%32)); 972 | } 973 | 974 | if((gAsic_cnt[i][j] !=0) && ((dev->chain_asic_exist[i][j/32] & (0x01 << (j%32))) == 0)) 975 | { 976 | dev->chain_asic_exist[i][j/32] |= (0x01 << (j%32)); 977 | } 978 | last_asic_nonce[i][j] = gAsic_cnt[i][j]; 979 | } 980 | } 981 | } 982 | } 983 | 984 | } 985 | 986 | #define LOW_PWM_PERCENT 20 //10、40 987 | #define TEMP_INTERVAL 2 //温度变化多少 调整 PWM 988 | //60度对应100，35度对应0吧, 实际为3； 989 | #define PWM_ADJUST_FACTOR ((100 - LOW_PWM_PERCENT)/(60-35)) 990 | 991 | //#define PWM_SCALE 1250 //25M=40ns 20KHz 周期 992 | #define PWM_SCALE 50 //1M=1us 20KHz 周期 993 | //#define PWM_ADJ_SCALE (12/10) // 1 normal 994 | #define PWM_ADJ_SCALE 9/10 // 1 normal 995 | 996 | 997 | void ChangePWM(BT_AS_INFO dev, unsigned int pwm_percent) 998 | { 999 | if (fan_custom) 1000 | { 1001 | dev->pwm_percent = custom_fan; 1002 | pwm_percent = custom_fan; 1003 | //printk_ratelimited("Customized fan speed {%d}\n", pwm_percent); 1004 | } 1005 | else 1006 | { 1007 | dev->pwm_percent = pwm_percent; 1008 | } 1009 | 1010 | if (pwm_percent > 100) 1011 | pwm_percent = 100; 1012 | if(pwm_percent < LOW_PWM_PERCENT) 1013 | pwm_percent = LOW_PWM_PERCENT; 1014 | //printk_ratelimited("pwm_percent{%d}\n", pwm_percent); 1015 | dev->pwm_high_value = pwm_percent * PWM_SCALE/100; //百分比 1016 | dev->pwm_low_value = (100 - pwm_percent) * PWM_SCALE/100; 1017 | } 1018 | 1019 | #ifndef TEMP_OUT 1020 | #define TEMP_OUT 80 1021 | #endif 1022 | #define TEMP_OUT_HIGHT (TEMP_OUT + 5) 1023 | #define TEST_TEMP_CNT 5 1024 | void adjust_pwm_from_temp(BT_AS_INFO dev) 1025 | { 1026 | uint8_t i; 1027 | static uint8_t last_temperature = 35; 1028 | static uint8_t llast_temperature = 35; 1029 | static uint8_t temp_out_pool_cnt = 0, temp_out_high_cnt = 0; 1030 | uint8_t temp_highest = dev->temp[dev->chain_map[0]]; 1031 | uint8_t wchain_highest = 0; 1032 | uint8_t temper_change; 1033 | int pwm_percent; 1034 | for(i = 1;i < dev->temp_num; i++) 1035 | { 1036 | if(dev->temp[dev->chain_map[i]] == 0xff) 1037 | continue; 1038 | if((dev->temp[dev->chain_map[i]] > temp_highest) && (dev->chain_exist & (0x01 << dev->chain_map[i]))) 1039 | { 1040 | temper_change = dev->temp[dev->chain_map[i]] - last_temperature; 1041 | temp_highest = dev->temp[dev->chain_map[i]]; 1042 | if (((temper_change > 0) && (temper_change <= 60)) || 1043 | ((temper_change < 0) && (temper_change >= -60))) 1044 | { 1045 | temp_highest = dev->temp[dev->chain_map[i]]; 1046 | wchain_highest = i; 1047 | } 1048 | } 1049 | } 1050 | if ((temp_highest & 0xff) >= TEMP_OUT) 1051 | { 1052 | if((temp_out_pool_cnt++ >= TEST_TEMP_CNT) && (dev->temp_out_fool == false)) 1053 | dev->temp_out_fool = true; 1054 | printk_ratelimited(KERN_ERR "chain %d temp highest{%d}\n", wchain_highest, temp_highest); 1055 | } 1056 | else 1057 | { 1058 | dev->temp_out_fool = false; 1059 | temp_out_pool_cnt = 0; 1060 | } 1061 | 1062 | if ((temp_highest & 0xff) >= TEMP_OUT_HIGHT) 1063 | { 1064 | if((temp_out_high_cnt++ >= TEST_TEMP_CNT) && (dev->temp_out_high == false)) 1065 | dev->temp_out_high = true; 1066 | printk_ratelimited(KERN_ERR "chain %d temp out highest{%d}\n", wchain_highest, temp_highest); 1067 | } 1068 | else 1069 | { 1070 | dev->temp_out_high = false; 1071 | temp_out_high_cnt = 0; 1072 | } 1073 | dev->temp_highest = temp_highest; 1074 | temper_change = temp_highest - last_temperature; 1075 | if (((temper_change > 0) && (temper_change >= TEMP_INTERVAL)) || 1076 | ((temper_change < 0) && (temper_change <= -TEMP_INTERVAL))) 1077 | { 1078 | if(temp_highest == llast_temperature) 1079 | { 1080 | if(temper_change > 0) 1081 | temp_highest -= 1; 1082 | else if(temper_change < 0) 1083 | temp_highest += 1; 1084 | } 1085 | pwm_percent = LOW_PWM_PERCENT + (temp_highest - 35) * PWM_ADJUST_FACTOR; 1086 | if (pwm_percent < 0) 1087 | pwm_percent = 0; 1088 | //printk_ratelimited("temp_highest{%d}\n", temp_highest); 1089 | ChangePWM(dev, pwm_percent); 1090 | llast_temperature = last_temperature; 1091 | last_temperature = temp_highest; 1092 | } 1093 | } 1094 | 1095 | //Timer7 pwm 1096 | #define DMTIMER7 0x4804a000 1097 | #define DMTIMER7_SIZE (4 * 1024) 1098 | 1099 | #define BEEP_PER (25*1000*1000/1000) //25M 1KHz 1100 | #define TCLR 0x38 1101 | #define TIMER_ST 0x01 1102 | #define TCRR 0x3c 1103 | #define TLDR 0x40 1104 | #define TMAR 0x4c 1105 | 1106 | #if 0 1107 | void init_beep(BT_AS_INFO dev) 1108 | { 1109 | void *cm_per_vaddr, *ctl_md_vaddr; 1110 | cm_per_vaddr = ioremap_nocache(CM_PER_BASE, CM_PER_Size); 1111 | iowrite32(0x02 , cm_per_vaddr + 0x7c); //Enable clk 1112 | iounmap(cm_per_vaddr); 1113 | 1114 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 1115 | iowrite32(PAD_PULLUP | 0x4, ctl_md_vaddr + 0x9B4); //Timer7 pwm out 1116 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9A8); //MCASP0_AXR1 gpio in 1117 | iounmap(ctl_md_vaddr); 1118 | dev->beep_virtual_addr = ioremap_nocache(DMTIMER7, DMTIMER7_SIZE); 1119 | iowrite32(0xffffffff - BEEP_PER, dev->beep_virtual_addr + TLDR); //Timer load reg 1120 | iowrite32(BEEP_PER + (0xffffffff - BEEP_PER) >> 1, dev->beep_virtual_addr + TMAR); //Timer load reg 1121 | //CLKSEL_TIMER7_CLK default CLK_M_OSC 1122 | iowrite32((0x01<<12) | (0x02<<10) | (0x01<<1), dev->beep_virtual_addr + TCLR); 1123 | dev->beep_status = false; 1124 | } 1125 | /********************************** 1126 | 1-200Hz声音很小 1127 | 200-300有声音 1128 | 400嘟 1129 | 500滴 1130 | 600音调变高 1131 | 700音调变高 1132 | 800音调变高 1133 | 2730Hz适合做滴的一声 1134 | 3000最剌耳,声音大 1135 | ***********************************/ 1136 | void beep(BT_AS_INFO dev) 1137 | { 1138 | static unsigned long beep_on_timeout = 0; 1139 | if(dev->beep_ctrl == true) 1140 | { 1141 | if(beep_on_timeout == 0) 1142 | beep_on_timeout = jiffies; 1143 | if(time_after(jiffies, beep_on_timeout)) 1144 | { 1145 | if(dev->beep_status == false) 1146 | { 1147 | beep_on_timeout = jiffies + 1000 * HZ/1000;// 1 s 1148 | iowrite32(ioread32(dev->beep_virtual_addr + TCLR) | TIMER_ST, dev->beep_virtual_addr + TCLR); 1149 | dev->beep_status = true; 1150 | printk_ratelimited("Beep on\n"); 1151 | } 1152 | else 1153 | { 1154 | beep_on_timeout = jiffies + 2 * 1000 * HZ/1000;// 2 s 1155 | iowrite32(ioread32(dev->beep_virtual_addr + TCLR) & (~TIMER_ST), dev->beep_virtual_addr + TCLR); 1156 | dev->beep_status = false; 1157 | } 1158 | } 1159 | } 1160 | else if(dev->beep_status == true) 1161 | { 1162 | iowrite32(ioread32(dev->beep_virtual_addr + TCLR) & (~TIMER_ST), dev->beep_virtual_addr + TCLR); 1163 | dev->beep_status = false; 1164 | } 1165 | return; 1166 | } 1167 | #else 1168 | /*有源*/ 1169 | //beep gpio0_20 1170 | void init_beep(BT_AS_INFO dev) 1171 | { 1172 | void *cm_per_vaddr, *ctl_md_vaddr; 1173 | cm_per_vaddr = ioremap_nocache(CM_PER_BASE, CM_PER_Size); 1174 | iowrite32(0x02 , cm_per_vaddr + 0x7c); //Enable clk 1175 | iounmap(cm_per_vaddr); 1176 | 1177 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 1178 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9B4); //GPIO0_20 out 1179 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9A8); //MCASP0_AXR1 gpio in 1180 | iounmap(ctl_md_vaddr); 1181 | gpio0_vaddr = ioremap_nocache(GPIO0_BASE, GPIO0_SIZE); 1182 | iowrite32(0x01<<20, gpio0_vaddr + GPIO_CLEARDATAOUT); 1183 | iowrite32(ioread32(gpio0_vaddr + GPIO_OE) & (~((0x01<<20))), gpio0_vaddr + GPIO_OE); 1184 | dev->beep_status = false; 1185 | } 1186 | 1187 | void beep(BT_AS_INFO dev) 1188 | { 1189 | static unsigned long beep_on_timeout = 0; 1190 | if(dev->beep_ctrl == true) 1191 | { 1192 | if(beep_on_timeout == 0) 1193 | beep_on_timeout = jiffies; 1194 | if(time_after(jiffies, beep_on_timeout)) 1195 | { 1196 | if(dev->beep_status == false) 1197 | { 1198 | beep_on_timeout = jiffies + 500 * HZ/1000;//500ms 1199 | iowrite32(0x01<<20, gpio0_vaddr + GPIO_SETDATAOUT); 1200 | dev->beep_status = true; 1201 | //printk_ratelimited("Beep on\n"); 1202 | } 1203 | else 1204 | { 1205 | beep_on_timeout = jiffies + 2 * 1000 * HZ/1000;// 2 s 1206 | iowrite32(0x01<<20, gpio0_vaddr + GPIO_CLEARDATAOUT); 1207 | dev->beep_status = false; 1208 | } 1209 | } 1210 | } 1211 | else if(dev->beep_status == true) 1212 | { 1213 | iowrite32(0x01<<20, gpio0_vaddr + GPIO_CLEARDATAOUT); 1214 | dev->beep_status = false; 1215 | } 1216 | return; 1217 | } 1218 | 1219 | #endif 1220 | 1221 | void check_fan_speed(BT_AS_INFO dev) 1222 | { 1223 | uint32_t i = 0; 1224 | for(i = 0; i < dev->fan_num; i++) 1225 | { 1226 | if(dev->fan_speed[dev->fan_map[i]]) 1227 | break; 1228 | } 1229 | if( i == dev->fan_num ) 1230 | dev->all_fan_stop = true; 1231 | else 1232 | dev->all_fan_stop = false; 1233 | 1234 | for(i = 0; i < dev->fan_num; i++) 1235 | { 1236 | if(((dev->fan_speed[dev->fan_map[i]] * 60) < 1000) && (dev->fan_speed[dev->fan_map[i]] != 0)) 1237 | break; 1238 | } 1239 | if( i == dev->fan_num ) 1240 | { 1241 | dev->any_fan_fail = false; 1242 | if(dev->all_fan_stop == true) 1243 | dev->any_fan_fail = true; 1244 | } 1245 | else 1246 | dev->any_fan_fail = true; 1247 | } 1248 | 1249 | uint32_t snd_to_fpga_work = 0, ret_nonce_num = 0; 1250 | uint32_t fifo_space; 1251 | //#define CTRL_OFF 1252 | //#define send_new_bl_CTRL 1253 | //void send_to_pfga_work(BT_AS_INFO dev) 1254 | enum TEMP_STATE check_temp_state(BT_AS_INFO dev) 1255 | { 1256 | uint8_t i; 1257 | 1258 | static uint8_t last_temperature = 35; 1259 | 1260 | static uint8_t temp_out_pool_cnt = 0, temp_out_high_cnt = 0; 1261 | uint8_t temp_highest = dev->temp[dev->chain_map[0]]; 1262 | uint8_t wchain_highest = 0; 1263 | uint8_t temper_change; 1264 | 1265 | for(i = 1;i < dev->temp_num; i++) 1266 | { 1267 | if(dev->temp[dev->chain_map[i]] == 0xff) 1268 | continue; 1269 | if((dev->temp[dev->chain_map[i]] > temp_highest) && (dev->chain_exist & (0x01 << dev->chain_map[i]))) 1270 | { 1271 | temper_change = dev->temp[dev->chain_map[i]] - last_temperature; 1272 | temp_highest = dev->temp[dev->chain_map[i]]; 1273 | if (((temper_change > 0) && (temper_change <= 60)) || 1274 | ((temper_change < 0) && (temper_change >= -60))) 1275 | { 1276 | temp_highest = dev->temp[dev->chain_map[i]]; 1277 | wchain_highest = i; 1278 | } 1279 | } 1280 | } 1281 | last_temperature = temp_highest; 1282 | if ((temp_highest & 0xff) >= TEMP_OUT && (temp_highest & 0xff) < TEMP_OUT_HIGHT) 1283 | { 1284 | if(temp_out_pool_cnt++ >= TEST_TEMP_CNT) 1285 | printk_ratelimited(KERN_ERR "chain %d temp highest{%d}\n", wchain_highest, temp_highest); 1286 | return TEMP_WARN; 1287 | 1288 | } 1289 | else 1290 | { 1291 | temp_out_pool_cnt = 0; 1292 | } 1293 | 1294 | if ((temp_highest & 0xff) >= TEMP_OUT_HIGHT) 1295 | { 1296 | check_state = 2; 1297 | if(temp_out_high_cnt++ >= TEST_TEMP_CNT) 1298 | { 1299 | check_state = 10; 1300 | printk_ratelimited(KERN_ERR "chain %d temp out highest{%d}\n", wchain_highest, temp_highest); 1301 | return TEMP_OUT_STATE; 1302 | } 1303 | } 1304 | else 1305 | { 1306 | check_state = 10; 1307 | temp_out_high_cnt = 0; 1308 | } 1309 | 1310 | 1311 | return TEMP_NORMAL; 1312 | } 1313 | 1314 | #ifndef FAN_MAX_SPEED 1315 | #define FAN_MAX_SPEED 4320 1316 | #endif 1317 | 1318 | #ifndef MAX_FAN_NUM 1319 | #define MAX_FAN_NUM 6 1320 | #endif 1321 | 1322 | enum FAN_STATE check_fan_state(BT_AS_INFO dev) 1323 | { 1324 | uint32_t i; 1325 | uint32_t error_fan = 0; 1326 | uint32_t normal_fan = 0; 1327 | uint32_t fan_speed = 0; 1328 | 1329 | static uint32_t fan_error_cnt = 0; 1330 | 1331 | unsigned int pwm_percent = dev->pwm_percent; 1332 | static uint32_t fan_num = 0; 1333 | 1334 | if(fan_num == 0) 1335 | { 1336 | for(i = 0; i < dev->fan_num; i++) 1337 | { 1338 | if(dev->fan_speed[dev->fan_map[i]] == 0) 1339 | continue; 1340 | fan_num++; 1341 | } 1342 | 1343 | if(fan_num == 0 ) 1344 | return FAN_ERROR; 1345 | } 1346 | 1347 | if(dev->fan_ctrl_type)//home 1348 | { 1349 | pwm_percent *=2; 1350 | pwm_percent /=6; 1351 | } 1352 | if (pwm_percent > 100) 1353 | pwm_percent = 100; 1354 | if(pwm_percent < LOW_PWM_PERCENT) 1355 | pwm_percent = LOW_PWM_PERCENT; 1356 | 1357 | for(i = 0; i < dev->fan_num; i++) 1358 | { 1359 | fan_speed = dev->fan_speed[dev->fan_map[i]] * 60; 1360 | if(fan_speed < (FAN_MAX_SPEED * pwm_percent / 100 / 2)) 1361 | error_fan ++; 1362 | else if(fan_speed > (FAN_MAX_SPEED * pwm_percent *8/ 100 /10)) 1363 | normal_fan ++; 1364 | 1365 | //printk_ratelimited("Fan%d speed %d, pwm_percent %d ", i, fan_speed, pwm_percent); 1366 | } 1367 | if( normal_fan == fan_num ) 1368 | return FAN_NORMAL; 1369 | 1370 | printk_ratelimited("\n error_fan %d, normal_fan %d, fan_num %d \n", error_fan, normal_fan, fan_num); 1371 | 1372 | if( error_fan == dev->fan_num ) 1373 | { 1374 | if ( fan_error_cnt++ > TEST_TEMP_CNT ) 1375 | return FAN_ERROR; 1376 | } 1377 | else 1378 | fan_error_cnt = 0; 1379 | 1380 | return FAN_WARN; 1381 | } 1382 | 1383 | enum FIFO_STATE check_fifo_state(BT_AS_INFO dev) 1384 | { 1385 | 1386 | if(dev->task_buffer_rd == dev->task_buffer_wr) 1387 | { 1388 | if((dev->fifo_empt_cnt++ %100) == 0) 1389 | printk_ratelimited(KERN_ERR "drv fifo empty\n"); 1390 | return ALLFIFO_EMPTY; 1391 | } 1392 | return FIFO_NORMAL; 1393 | } 1394 | 1395 | 1396 | #ifndef CHAIN_NONCE_AVG 1397 | #define CHAIN_NONCE_AVG 75 1398 | #endif 1399 | enum CHAIN_STATE check_chain_state(BT_AS_INFO dev) 1400 | { 1401 | uint32_t bgNonce_average; 1402 | uint32_t time_elasp_ms = 0; 1403 | uint32_t i; 1404 | uint8_t chain_nu; 1405 | //struct ASIC_TASK asic_task; 1406 | static unsigned long simulate_power_err_time = 0; 1407 | wait_queue_head_t timeout_wq; 1408 | unsigned char cmd_buf[4] = {0}; 1409 | 1410 | if((dev->cgminer_start == true)) 1411 | { 1412 | if(simulate_power_err_time == 0) 1413 | { 1414 | simulate_power_err_time = jiffies + 5 * 60 * 1000 * HZ/1000; 1415 | } 1416 | time_elasp_ms = jiffies_to_msecs(jiffies - dev->cgminer_start_time); 1417 | //printk_ratelimited("time_elasp_jiffies{%ld}\n", jiffies - dev->cgminer_start_time); 1418 | //printk_ratelimited("jiffies{%ld}dev->cgminer_start_time{%ld}", jiffies, dev->cgminer_start_time); 1419 | //printk_ratelimited("time_elasp_ms =%ldms dev->total_nonce_num{%ld}\n", time_elasp_ms, dev->total_nonce_num); 1420 | //bgNonce_average = ((uint32_t)dev->total_nonce_num / (time_elasp_ms / 1000)) * (CHAIN_POWER_TIME_INTERAL*60);//平均5分钟 1421 | 1422 | if((time_elasp_ms / (1000 * CHAIN_POWER_TIME_INTERAL*60)) == 0) 1423 | { 1424 | if(bgNonce_average < 8) 1425 | bgNonce_average = 1; 1426 | else 1427 | bgNonce_average /= 8; 1428 | } 1429 | else 1430 | { 1431 | bgNonce_average = CHAIN_NONCE_AVG; 1432 | 1433 | } 1434 | for (i = 0; i < dev->asic_status_data.chain_num; i++) 1435 | { 1436 | chain_nu = dev->chain_map[i]; 1437 | 1438 | if(Chain_nonce_nu[chain_nu] >= Chain_nonce_nu_last[chain_nu]) 1439 | { 1440 | if(((Chain_nonce_nu[chain_nu] - Chain_nonce_nu_last[chain_nu]) < bgNonce_average) || (bgNonce_average == 0)) 1441 | { 1442 | printk_ratelimited("bgNonce_average{%d}\n", bgNonce_average); 1443 | printk_ratelimited("chain%d Chain_nonce_nu[%ld] Chain_nonce_nu_last[%ld]\n", chain_nu,Chain_nonce_nu[chain_nu],Chain_nonce_nu_last[chain_nu]); 1444 | return CHAIN_ERROR; 1445 | } 1446 | } 1447 | Chain_nonce_nu_last[chain_nu] = Chain_nonce_nu[chain_nu]; 1448 | } 1449 | } 1450 | return CHAIN_NORMAL; 1451 | } 1452 | 1453 | enum CHAIN_STATE check_no_nonce_to(BT_AS_INFO dev) 1454 | { 1455 | if(time_after(jiffies, dev->last_nonce_timeout + 60 * 1000 * HZ/1000))// 1 分钟 1456 | { 1457 | return CHAIN_NO_NONCE_TO; 1458 | } 1459 | return CHAIN_NORMAL; 1460 | } 1461 | 1462 | void reset_chain(BT_AS_INFO dev) 1463 | { 1464 | uint32_t bgNonce_average; 1465 | uint32_t time_elasp_ms = 0; 1466 | uint32_t i; 1467 | uint8_t chain_nu; 1468 | //struct ASIC_TASK asic_task; 1469 | static unsigned long simulate_power_err_time = 0; 1470 | wait_queue_head_t timeout_wq; 1471 | unsigned char cmd_buf[4] = {0}; 1472 | 1473 | struct timex txc; 1474 | struct rtc_time tm; 1475 | struct file *fp_pwerr; 1476 | mm_segment_t old_fs; 1477 | char wr_buf[512]; 1478 | unsigned int wr_len = 0; 1479 | do_gettimeofday(&(txc.time)); 1480 | rtc_time_to_tm(txc.time.tv_sec,&tm); 1481 | printk_ratelimited("UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec); 1482 | fp_pwerr = filp_open("/config/power_rst", O_RDWR | O_CREAT | O_APPEND, 0644); 1483 | wr_len = sprintf(wr_buf, "UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec); 1484 | old_fs = get_fs(); 1485 | set_fs(KERNEL_DS); 1486 | fp_pwerr->f_op->write(fp_pwerr, (char *)wr_buf, wr_len, &fp_pwerr->f_pos); 1487 | set_fs(old_fs); 1488 | filp_close(fp_pwerr, NULL); 1489 | dev->restarting_hash = true; 1490 | mod_timer(&prnt_timer, jiffies + 5 * 1000 * HZ/1000); 1491 | i = 0; 1492 | while(timer_pending(&prnt_timer)) 1493 | { 1494 | del_timer(&prnt_timer); 1495 | if(i++ > 200) 1496 | break; 1497 | } 1498 | if(bgNonce_average == 0) 1499 | printk_ratelimited("!!!!!!!!!!----no hash power OK\n\n"); 1500 | printk_ratelimited("remap chain%d(hardware chain%d) power err\n", i, chain_nu); 1501 | printk_ratelimited("bgNonce_average{%d}chain_nonce_nu{%d}last{%d}\n", bgNonce_average, Chain_nonce_nu[chain_nu], Chain_nonce_nu_last[chain_nu]); 1502 | #if 0 1503 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 1504 | { 1505 | memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate)); 1506 | memset(asic_task.data, 0x00, sizeof(asic_task.data)); 1507 | if(i == 0) 1508 | send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task); 1509 | else 1510 | send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task); 1511 | } 1512 | #endif 1513 | stop_work_to_all_chain(dev); 1514 | set_baud(dev, 26); 1515 | printk_ratelimited(KERN_ERR "Detect device for anyone power err\n"); 1516 | 1517 | cmd_buf[0] = 9; 1518 | cmd_buf[1] = 0x10; //16-23 1519 | cmd_buf[2] = 0x1f; //8-13 1520 | cmd_buf[0] |= 0x80; 1521 | //cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5); 1522 | cmd_buf[3] = 0x00; //故意错误crc 只是修改fpga 波特率 1523 | send_BC_to_fpga(i, cmd_buf); 1524 | 1525 | rst_hash_asic(dev); 1526 | //send_work_to_fpga(true, dev, &asic_task); 1527 | clear_fpga_nonce_buffer(dev); 1528 | init_waitqueue_head(&timeout_wq); 1529 | interruptible_sleep_on_timeout(&timeout_wq, 1000 * HZ/1000);//300ms 1530 | #if 1 1531 | rst_hash_asic(dev); 1532 | //send_work_to_fpga(true, dev, &asic_task); 1533 | clear_fpga_nonce_buffer(dev); 1534 | init_waitqueue_head(&timeout_wq); 1535 | interruptible_sleep_on_timeout(&timeout_wq, 1100 * HZ/1000);//300ms 1536 | #endif 1537 | //detect_chain_num(dev); 1538 | set_frequency(dev, dev->asic_configure.freq_vlaue); 1539 | asic_result_status_rd = asic_result_status_wr = asic_result_status_full = 0; 1540 | asic_result_rd = asic_result_wr = asic_result_full = 0; 1541 | //gDiff_nonce_num = gNonce_num = gNonce_Err = gNonce_miss = 0; 1542 | //gSubmit_nonce_num = 0; 1543 | dev->restarting_hash = false; 1544 | prnt_timer.expires = jiffies + dev->send_to_fpga_interval* HZ/1000; 1545 | add_timer(&prnt_timer); 1546 | mod_timer(&prnt_timer, jiffies + dev->send_to_fpga_interval* HZ/1000); 1547 | simulate_power_err_time = 0; 1548 | } 1549 | 1550 | #define LED_RED 2 1551 | #define LED_GREEN 1 1552 | 1553 | void led_action(BT_AS_INFO dev ,int led, bool if_blink) 1554 | { 1555 | static unsigned long blink_timeout = 0; 1556 | 1557 | if (blink_timeout == 0) 1558 | blink_timeout = jiffies + 1 * 1000 * HZ/1000; 1559 | 1560 | if(time_after(jiffies, blink_timeout)) 1561 | { 1562 | blink_timeout = jiffies + 1 * 1000 * HZ/1000; //1秒钟后超时 1563 | 1564 | switch (led) 1565 | { 1566 | case LED_RED: 1567 | if(hardware_version == 0x01) 1568 | { 1569 | iowrite32(GREEN, dev->led_virtual1 + GPIO_CLEARDATAOUT); 1570 | } 1571 | else 1572 | { 1573 | iowrite32(GREEN, dev->led_virtual + GPIO_CLEARDATAOUT); 1574 | 1575 | } 1576 | if(if_blink) 1577 | { 1578 | if(ioread32(dev->led_virtual + GPIO_DATAOUT) & RED) 1579 | iowrite32(RED, dev->led_virtual + GPIO_CLEARDATAOUT); 1580 | else 1581 | iowrite32(RED, dev->led_virtual + GPIO_SETDATAOUT); 1582 | } 1583 | else 1584 | iowrite32(RED, dev->led_virtual + GPIO_SETDATAOUT); 1585 | break; 1586 | case LED_GREEN: 1587 | iowrite32(RED, dev->led_virtual + GPIO_CLEARDATAOUT); 1588 | if(hardware_version == 0x01) 1589 | { 1590 | if(ioread32(dev->led_virtual1 + GPIO_DATAOUT) & GREEN) 1591 | { 1592 | iowrite32(GREEN, dev->led_virtual1 + GPIO_CLEARDATAOUT); 1593 | } 1594 | else 1595 | { 1596 | iowrite32(GREEN, dev->led_virtual1 + GPIO_SETDATAOUT); 1597 | } 1598 | } 1599 | else 1600 | { 1601 | if(ioread32(dev->led_virtual + GPIO_DATAOUT) & GREEN) 1602 | iowrite32(GREEN, dev->led_virtual + GPIO_CLEARDATAOUT); 1603 | else 1604 | iowrite32(GREEN, dev->led_virtual + GPIO_SETDATAOUT); 1605 | } 1606 | break; 1607 | } 1608 | } 1609 | } 1610 | 1611 | void do_send_work(BT_AS_INFO dev) 1612 | { 1613 | int ret = -1; 1614 | uint8_t work_num = 0; 1615 | 1616 | 1617 | while(g_FPGA_FIFO_SPACE > g_FPGA_RESERVE_FIFO_SPACE && dev->task_buffer_rd != dev->task_buffer_wr) 1618 | { 1619 | bool new_block = false; 1620 | 1621 | if(dev->new_block) 1622 | { 1623 | dev->new_block = false; 1624 | new_block = true; 1625 | } 1626 | 1627 | dev->last_nonce_timeout = jiffies; 1628 | snd_to_fpga_work++; 1629 | dev->snding_work = true; 1630 | ret = send_work_to_fpga(new_block, 0, dev, &dev->task_buffer[dev->task_buffer_rd]); 1631 | dev->snding_work = false; 1632 | dev->save_send_work = dev->task_buffer_rd; 1633 | increase_variable_rehead_U32((uint32_t*) & dev->task_buffer_rd, dev->task_buffer_size); 1634 | if(work_num++ == g_TOTAL_FPGA_FIFO*4/48) 1635 | break; 1636 | //--g_FPGA_FIFO_SPACE; in send update g_FPGA_FIFO_SPACE 1637 | if(ret == -1)//只在query出nonce 1638 | { 1639 | g_FPGA_FIFO_SPACE--; 1640 | ret = 5; 1641 | if((work_num%(g_FPGA_RESERVE_FIFO_SPACE<<1)) == 0)//每路4个work时，取一次nonce 1642 | nonce_query(dev); 1643 | } 1644 | } 1645 | while( ret == 5) 1646 | { 1647 | ret = nonce_query(dev); 1648 | } 1649 | 1650 | } 1651 | bool set_beep(BT_AS_INFO dev, bool state) 1652 | { 1653 | if(dev->asic_configure.beep_on_en) 1654 | { 1655 | dev->beep_ctrl = state; 1656 | } 1657 | else 1658 | dev->beep_ctrl = false; 1659 | } 1660 | void action_normal(BT_AS_INFO dev) 1661 | { 1662 | do_send_work(dev); 1663 | adjust_pwm_from_temp(dev); 1664 | led_action(dev,LED_GREEN,true); 1665 | set_beep(dev,false); 1666 | } 1667 | void action_temp_warn(BT_AS_INFO dev) 1668 | { 1669 | do_send_work(dev); 1670 | adjust_pwm_from_temp(dev); 1671 | led_action(dev,LED_RED,true); 1672 | set_beep(dev,false); 1673 | } 1674 | 1675 | void action_fifo_empty(BT_AS_INFO dev) 1676 | { 1677 | do_send_work(dev); 1678 | adjust_pwm_from_temp(dev); 1679 | led_action(dev,LED_RED,false); 1680 | set_beep(dev,false); 1681 | } 1682 | 1683 | 1684 | 1685 | void action_fifo_stop(BT_AS_INFO dev) 1686 | { 1687 | stop_work_to_all_chain(dev); 1688 | adjust_pwm_from_temp(dev); 1689 | led_action(dev,LED_RED,false); 1690 | set_beep(dev,true); 1691 | 1692 | } 1693 | 1694 | void action_after_temp_stop(BT_AS_INFO dev) 1695 | { 1696 | adjust_pwm_from_temp(dev); 1697 | led_action(dev,LED_RED,false); 1698 | set_beep(dev,true); 1699 | } 1700 | 1701 | 1702 | void action_stop(BT_AS_INFO dev) 1703 | { 1704 | action_fifo_stop(dev); 1705 | if_temp_out_stop = true; 1706 | } 1707 | 1708 | 1709 | void action_stop_after_last_nonce(BT_AS_INFO dev) 1710 | { 1711 | led_action(dev,LED_RED,false); 1712 | set_beep(dev,true); 1713 | if(dev->pwm_percent !=0 ) 1714 | ChangePWM(dev, 0); 1715 | nonce_query(dev); 1716 | } 1717 | 1718 | void action_reset_chain(BT_AS_INFO dev) 1719 | { 1720 | reset_chain(dev); 1721 | } 1722 | 1723 | void action_no(BT_AS_INFO dev){} 1724 | 1725 | 1726 | actiontype transition_table[3][3] = 1727 | { 1728 | action_normal,action_temp_warn,action_stop, 1729 | action_temp_warn,action_temp_warn,action_stop, 1730 | action_stop,action_stop,action_stop 1731 | }; 1732 | 1733 | 1734 | void step(BT_AS_INFO dev) 1735 | { 1736 | static enum TEMP_STATE temp_state = TEMP_NORMAL; 1737 | static enum FAN_STATE fan_state = FAN_NORMAL; 1738 | static enum FIFO_STATE fifo_state = FIFO_NORMAL; 1739 | static enum CHAIN_STATE chain_state = CHAIN_NORMAL; 1740 | 1741 | static bool fifo_once_empty = false; 1742 | static bool chain_once_reset = false; 1743 | 1744 | static unsigned long check_chain_power_timeout = 0; 1745 | static unsigned long check_status_timeout = 0; 1746 | static unsigned long S1_timeout = 0; 1747 | static unsigned long fifo_empty_timeout = 0; 1748 | 1749 | static uint32_t prnt_chin_nu = 0, prnt_aisc_nu = 0; 1750 | 1751 | actiontype miner_action = action_no; 1752 | actiontype chain_action = action_no; 1753 | actiontype no_nonce_action = action_no; 1754 | 1755 | nonce_query(dev); 1756 | 1757 | 1758 | 1759 | fifo_state = check_fifo_state(dev); 1760 | 1761 | if (fifo_state == FIFO_NORMAL) 1762 | { 1763 | fifo_empty_timeout = jiffies + 30 * 1000 * HZ/1000; 1764 | } 1765 | 1766 | if(check_status_timeout == 0) 1767 | { 1768 | check_chain_power_timeout = jiffies + 90 * 1000 * HZ/1000; 1769 | check_status_timeout = jiffies + 10 * HZ/1000; //10ms后超时 1770 | fifo_empty_timeout = jiffies + 120 * 1000 * HZ/1000; 1771 | } 1772 | 1773 | if(time_after(jiffies, check_status_timeout)) 1774 | { 1775 | check_status_timeout = jiffies + check_state * 1000 * HZ/1000; 1776 | temp_state = check_temp_state(dev); 1777 | fan_state = check_fan_state(dev); 1778 | /* 1779 | printk_ratelimited("\nchain exist: %x, g_TOTAL_FPGA_FIFO %#x,g_FPGA_RESERVE_FIFO_SPACE{%d}\n",dev->chain_exist, g_TOTAL_FPGA_FIFO, g_FPGA_RESERVE_FIFO_SPACE); 1780 | printk_ratelimited("g_FPGA_FIFO_SPACE %d, fifo_space{%d}\n",g_FPGA_FIFO_SPACE, fifo_space); 1781 | printk_ratelimited("ret_nonce_num = %d, snd_to_fpga_work{%d}\n",ret_nonce_num, snd_to_fpga_work); 1782 | printk_ratelimited("total ret nonce num = %llu, diff1_nonce num = %llu\n", dev->total_nonce_num, dev->diff1_num); 1783 | printk_ratelimited("gDiff_nonce_num{%d}gNonce_Err{%d}\n", gDiff_nonce_num, gNonce_Err); 1784 | printk_ratelimited("gSubmit_nonce_num{%d}\n", gSubmit_nonce_num); 1785 | printk_ratelimited("chain%1d asic%02d ret nonce_num{%d}\n", prnt_chin_nu, prnt_aisc_nu, gAsic_cnt[prnt_chin_nu][prnt_aisc_nu]); 1786 | printk_ratelimited("dev->net_diff_sh_bit{%d}dev->get_blk_num{%d}\n", dev->net_diff_sh_bit, dev->get_blk_num); 1787 | printk_ratelimited("dev->temp_out_ctrl{%d}\n\n", dev->temp_out_ctrl); 1788 | printk_ratelimited("fifo_state %d temp_state %d fan_state %d \n", fifo_state,temp_state,fan_state);*/ 1789 | if(++prnt_aisc_nu >= gChain_Asic_num[dev->chain_map[prnt_chin_nu]]) 1790 | { 1791 | prnt_aisc_nu = 0; 1792 | if(++prnt_chin_nu >= dev->asic_status_data.chain_num) 1793 | prnt_chin_nu = 0; 1794 | } 1795 | } 1796 | 1797 | chain_state = check_no_nonce_to(dev); 1798 | if(chain_state == CHAIN_NO_NONCE_TO && chain_once_reset == false ) 1799 | { 1800 | no_nonce_action = action_stop_after_last_nonce; 1801 | } 1802 | 1803 | 1804 | 1805 | switch(fifo_state) 1806 | { 1807 | case ALLFIFO_EMPTY: 1808 | if (!fifo_once_empty) 1809 | { 1810 | miner_action = action_fifo_empty; 1811 | chain_action = action_no; 1812 | no_nonce_action = action_no; 1813 | 1814 | } 1815 | if (time_after(jiffies, fifo_empty_timeout) && fifo_once_empty == false) 1816 | { 1817 | fifo_empty_timeout = jiffies + 30 * 1000 * HZ/1000; 1818 | fifo_once_empty = true; 1819 | chain_once_reset == false; 1820 | miner_action = action_fifo_stop; 1821 | } 1822 | break; 1823 | case FIFO_NORMAL: 1824 | miner_action = transition_table[temp_state][fan_state]; 1825 | if(fifo_once_empty) 1826 | { 1827 | fifo_once_empty = false; 1828 | chain_action = action_reset_chain; 1829 | chain_once_reset = true; 1830 | check_chain_power_timeout = jiffies + CHAIN_POWER_TIME_INTERAL * 60 * 1000 * HZ/1000; 1831 | 1832 | } 1833 | else if (chain_state != CHAIN_NO_NONCE_TO) 1834 | { 1835 | chain_once_reset = false; 1836 | if((temp_state == TEMP_NORMAL || temp_state == TEMP_WARN) && (fan_state == FAN_NORMAL|| fan_state == FAN_WARN)) 1837 | { 1838 | #ifdef S5_S_VL 1839 | if(time_after(jiffies, check_chain_power_timeout)) 1840 | { 1841 | check_chain_power_timeout = jiffies + CHAIN_POWER_TIME_INTERAL * 60 * 1000 * HZ/1000; //60秒钟后超时 1842 | chain_state = check_chain_state(dev); 1843 | if (chain_state == CHAIN_ERROR && chain_once_reset == false) 1844 | { 1845 | chain_action = action_reset_chain; 1846 | } 1847 | } 1848 | #endif 1849 | } 1850 | } 1851 | break; 1852 | } 1853 | 1854 | if(if_temp_out_stop) 1855 | { 1856 | miner_action = action_after_temp_stop; 1857 | chain_action = action_no; 1858 | } 1859 | 1860 | miner_action(dev); 1861 | chain_action(dev); 1862 | no_nonce_action(dev); 1863 | beep(dev); 1864 | } 1865 | 1866 | void send_to_pfga_work(struct work_struct *work) 1867 | { 1868 | BT_AS_INFO dev= container_of(work, struct __BT_AS_info, send_to_fpga_work); 1869 | 1870 | 1871 | static unsigned long check_asic_status_timeout = 0; 1872 | 1873 | static uint32_t prnt_chin_nu = 0, prnt_aisc_nu = 0; 1874 | uint32_t i,j, k = 0; 1875 | 1876 | if((dev->fpga_ok == false)) 1877 | return; 1878 | 1879 | if((g_FPGA_FIFO_SPACE <= g_FPGA_RESERVE_FIFO_SPACE)) 1880 | { 1881 | nonce_query(dev); 1882 | } 1883 | 1884 | step(dev); 1885 | 1886 | if(time_after(jiffies, check_asic_status_timeout)) 1887 | { 1888 | check_asic_status_timeout = jiffies + 60 * 1000 * HZ/1000; //60秒钟后超时 1889 | check_asic_status(dev); 1890 | } 1891 | 1892 | return; 1893 | } 1894 | #if PRNT_TIMER_EN 1895 | static void Prnt(unsigned long data) 1896 | { 1897 | BT_AS_INFO dev = &bitmain_asic_dev; 1898 | uint8_t work_num = 0; 1899 | unsigned long interval; 1900 | //printk_ratelimited("wr{%#d}rd{%d}\n", dev->task_buffer_wr, dev->task_buffer_rd); 1901 | Prnt_time_out = jiffies + 1000 * HZ/1000; // 1s 1902 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 1903 | //send_to_pfga_work(dev); 1904 | if(queue_work(dev->send_to_fpga_work_wq, &dev->send_to_fpga_work) != 1) 1905 | { 1906 | //printk_ratelimited("send_to_fpga_work in queue\n"); 1907 | if(dev->restarting_hash == true) 1908 | del_timer(&prnt_timer); 1909 | } 1910 | //if(dev->task_buffer_rd != dev->task_buffer_wr)// not empty 1911 | { 1912 | prnt_timer.expires = jiffies + dev->send_to_fpga_interval* HZ/1000; 1913 | if(dev->restarting_hash == false) 1914 | add_timer(&prnt_timer); 1915 | } 1916 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 1917 | } 1918 | #endif 1919 | static ssize_t bitmain_asic_write(struct file *file, const char __user *user_buffer, 1920 | size_t writesize, loff_t *ppos) 1921 | { 1922 | BT_AS_INFO dev = file->private_data; 1923 | struct BITMAIN_TASK txtask_data; 1924 | struct BITMAIN_TASK *txtask = &txtask_data; 1925 | uint8_t reg_addr; 1926 | uint8_t task_work_num, need_cpy_task_work; 1927 | int retval = 0; 1928 | bool asic_reset = false; 1929 | //spin_lock(&dev->lock); 1930 | //bitmain_asic_open_usb(dev); 1931 | //printk_ratelimited("enter bitmain_asic_write\n"); 1932 | if (copy_from_user((void*)txtask, user_buffer, writesize)) 1933 | { 1934 | retval = -EFAULT; 1935 | goto error; 1936 | } 1937 | //printk data 1938 | /* 1939 | printk_ratelimited("asic_writ data is:"); 1940 | for(retval = 0; retval < writesize; retval++) 1941 | { 1942 | if(0 == (retval %16)) 1943 | printk_ratelimited("\n 0x%02x: ", retval); 1944 | printk_ratelimited("0x%02x, ", *((char*)txtask + retval)); 1945 | } 1946 | printk_ratelimited("\n"); 1947 | */ 1948 | if (cmd_check((uint8_t*)txtask)) //crc16 ok 1949 | { 1950 | switch (txtask->token_type) 1951 | { 1952 | case BM_TX_TASK: 1953 | //printk_ratelimited(KERN_ERR "TX TASK\n"); 1954 | if (txtask->new_block) 1955 | { 1956 | dev->task_buffer_wr = dev->task_buffer_rd; 1957 | dev->task_buffer_full = false; 1958 | if(dev->snding_work == true) 1959 | increase_variable_rehead_U32((uint32_t*) & dev->task_buffer_wr, dev->task_buffer_size); 1960 | dev->new_block = true; 1961 | asic_result_rd = asic_result_wr; 1962 | asic_result_full = 0; 1963 | //printk_ratelimited(KERN_ERR "New blok\n"); 1964 | } 1965 | if(dev->cgminer_start == false) 1966 | //bitmain_asic_get_status(NULL,dev->chain_map[0], 1, 0, 4); //CHIP_ADDR_REG 4 PLL reg 1967 | bitmain_asic_get_status(NULL,dev->chain_map[0], 1, 0, 0x00); //CHIP_ADDR_REG 4 PLL reg 1968 | #if HAVE_NUM 1969 | task_work_num = txtask.work_num; 1970 | #else 1971 | task_work_num = (le16_to_cpu(txtask->length) - 6) / sizeof (*dev->task_buffer); 1972 | #endif 1973 | if(fifo_space < task_work_num) 1974 | { 1975 | task_work_num = fifo_space; 1976 | //printk_ratelimited(KERN_ERR "cgminer send too data!!!!\n"); 1977 | } 1978 | if ((dev->task_buffer_wr + task_work_num) >= dev->task_buffer_size) 1979 | { 1980 | need_cpy_task_work = dev->task_buffer_size - dev->task_buffer_wr; 1981 | memcpy(dev->task_buffer + dev->task_buffer_wr, &txtask->asic_task[0], 1982 | need_cpy_task_work * sizeof (*dev->task_buffer)); 1983 | task_work_num -= need_cpy_task_work; 1984 | memcpy(dev->task_buffer, &txtask->asic_task[need_cpy_task_work], task_work_num * sizeof (*dev->task_buffer)); 1985 | dev->task_buffer_wr = task_work_num; 1986 | //printk_ratelimited("split asic_task[0].work_id %#x wr{%d}\n", le32_to_cpu(txtask.asic_task[0].work_id), dev->task_buffer_wr); 1987 | } 1988 | else 1989 | { 1990 | memcpy(dev->task_buffer + dev->task_buffer_wr, &txtask->asic_task[0], 1991 | task_work_num * sizeof (*dev->task_buffer)); 1992 | dev->task_buffer_wr += task_work_num; 1993 | //printk_ratelimited("asic_task[0].work_id %#x wr{%d}rd{%d}\n", le32_to_cpu(txtask.asic_task[0].work_id), dev->task_buffer_wr,dev->task_buffer_rd); 1994 | } 1995 | if(dev->hw_error_eft == true) 1996 | { 1997 | if(dev->asic_configure.diff_sh_bit != txtask->diff) 1998 | { 1999 | printk_ratelimited(KERN_ERR "Change diff to %d\n", txtask->diff); 2000 | dev->asic_configure.diff_sh_bit = txtask->diff; 2001 | dev->nonce_diff = dev->asic_configure.diff_sh_bit; 2002 | #if defined S4_Board || defined C1_Board || defined S5 || defined S4_PLUS 2003 | if(dev->nonce_diff > AISC_RT_DIFF) 2004 | { 2005 | dev->nonce_diff = AISC_RT_DIFF; 2006 | printk_ratelimited(KERN_ERR "diff fix to %d\n", dev->nonce_diff); 2007 | } 2008 | #endif 2009 | } 2010 | if(dev->net_diff_sh_bit != txtask->net_diff) 2011 | { 2012 | printk_ratelimited(KERN_ERR "Change net_diff to %d\n", txtask->net_diff); 2013 | dev->net_diff_sh_bit = txtask->net_diff; 2014 | } 2015 | } 2016 | else 2017 | dev->asic_configure.diff_sh_bit = 0; 2018 | if(dev->cgminer_start == false) 2019 | { 2020 | dev->cgminer_start = true; 2021 | dev->cgminer_start_time = jiffies; 2022 | } 2023 | #if 0 2024 | if(g_FPGA_FIFO_SPACE <= g_FPGA_RESERVE_FIFO_SPACE) 2025 | nonce_query(dev); 2026 | if((g_FPGA_FIFO_SPACE > g_FPGA_RESERVE_FIFO_SPACE) || (dev->new_block == true)) 2027 | { 2028 | send_to_pfga_work(dev); 2029 | } 2030 | #endif 2031 | 2032 | if ((timer_pending(&prnt_timer) == 0) || (dev->new_block == true))//不存在 2033 | { 2034 | //printk_ratelimited(KERN_ERR "start timer\n"); 2035 | mod_timer(&prnt_timer, jiffies + 1*HZ/1000); //Start Timer 1ms 2036 | dev->cgminer_start = true; 2037 | } 2038 | /**/ 2039 | break; 2040 | case BM_TX_CONF: 2041 | { 2042 | BITMAIN_CONFIGURE_P bt_conf = (BITMAIN_CONFIGURE_P) txtask; 2043 | dev->asic_configure.asic_num = bt_conf->asic_num; 2044 | dev->asic_configure.chain_num = bt_conf->chain_num; 2045 | dev->asic_status_data.chain_num = dev->asic_configure.chain_num; 2046 | dev->asic_configure.diff_sh_bit = dev->nonce_diff = 0; 2047 | dev->asic_configure.beep_on_en = bt_conf->beeper_ctrl; 2048 | dev->temp_out_ctrl = bt_conf->temp_over_ctrl; 2049 | dev->fan_ctrl_type = bt_conf->fan_ctrl_type; 2050 | //test 2051 | //dev->fan_ctrl_type = true; 2052 | //dev->temp_out_ctrl = false; 2053 | dev->total_nonce_num = dev->fpga_nonce1_num; 2054 | printk_ratelimited("btm_tx_conf\n"); 2055 | if (bt_conf->reset) 2056 | { 2057 | asic_reset = true; 2058 | } 2059 | if (bt_conf->fan_eft) 2060 | { 2061 | fan_custom = true; 2062 | custom_fan = bt_conf->fan_pwm_data; 2063 | dev->asic_configure.fan_pwm_data = bt_conf->fan_pwm_data; 2064 | printk_ratelimited("fan pwm valid {%d}\n", dev->asic_configure.fan_pwm_data); 2065 | //ChangePWM(dev->asic_configure.fan_pwm_data); 2066 | } 2067 | if (bt_conf->frequency_eft) 2068 | { 2069 | dev->asic_configure.frequency = bt_conf->frequency; 2070 | //set_frequency(dev->asic_configure.frequency); 2071 | printk_ratelimited("Set asic frequency {%d}\n", dev->asic_configure.frequency); 2072 | } 2073 | if (bt_conf->voltage_eft) 2074 | { 2075 | dev->asic_configure.voltage = htons(bt_conf->voltage); //voltage 需修改为16bit 2076 | if(dev->asic_configure.voltage < 0x0600) 2077 | dev->asic_configure.voltage = 0x0600; 2078 | else if(dev->asic_configure.voltage > 0x0900) 2079 | dev->asic_configure.voltage = 0x0900; 2080 | bitmain_set_voltage(dev, dev->asic_configure.voltage); 2081 | } 2082 | if (bt_conf->chain_check_time_eft) 2083 | { 2084 | dev->asic_configure.chain_check_time = bt_conf->chain_check_time; 2085 | } 2086 | 2087 | if (bt_conf->timeout_eft) 2088 | { 2089 | dev->asic_configure.timeout_data = bt_conf->timeout_data; 2090 | } 2091 | 2092 | if (bt_conf->chip_config_eft) 2093 | { 2094 | dev->asic_configure.chip_address = bt_conf->chip_address; 2095 | dev->asic_configure.reg_address = bt_conf->reg_address; 2096 | printk_ratelimited("Set chip_addr{%#x}reg_address{%#x}value{%#x}\n", 2097 | dev->asic_configure.chip_address, dev->asic_configure.reg_address, 2098 | bt_conf->reg_data); 2099 | reg_addr = dev->asic_configure.reg_address; 2100 | dev->asic_configure.reg_address = 0x0; 2101 | dev->asic_configure.reg_address = reg_addr; 2102 | if (dev->asic_configure.reg_address == 0x04)//频率寄存器地址 2103 | { 2104 | dev->asic_configure.freq_vlaue = bt_conf->reg_data; 2105 | #if defined BM1385 2106 | printk_ratelimited("pll reg_data %#x\n", bt_conf->reg_data); 2107 | dev->asic_configure.freq_vlaue = bt_conf->reg_data = dev->asic_configure.frequency; 2108 | #endif 2109 | set_frequency(dev, bt_conf->reg_data); 2110 | } 2111 | #ifndef S5_S_VL 2112 | //if(dev->asic_configure.timeout_data < 7) 2113 | set_baud(dev,10); 2114 | //set_baud(dev,5); 2115 | reg_addr = dev->asic_configure.reg_address; 2116 | dev->asic_configure.reg_address = 0x0; 2117 | sw_addr(dev); 2118 | dev->asic_configure.reg_address = reg_addr; 2119 | #endif 2120 | } 2121 | //先频率再设置timeout 2122 | if (bt_conf->timeout_eft) 2123 | { 2124 | dev->asic_configure.timeout_data = bt_conf->timeout_data; 2125 | #if defined BM1385 2126 | dev->asic_configure.timeout_data = 0xffffffff/64/64/dev->asic_configure.frequency/1000; 2127 | #endif 2128 | printk_ratelimited(KERN_ERR "Timeout {%d}\n", dev->asic_configure.timeout_data); 2129 | #ifndef S5_S_VL 2130 | dev->timeout_valid = true; 2131 | nonce_query(dev); 2132 | dev->timeout_valid = false; 2133 | #endif 2134 | dev->send_to_fpga_interval = (dev->asic_configure.timeout_data * g_TOTAL_FPGA_FIFO * 4)/ dev->asic_status_data.chain_num / (sizeof(FPGA_WORK) - 4); 2135 | dev->send_to_fpga_interval /=4; 2136 | printk_ratelimited(KERN_ERR "Snd Time Interval {%d}ms\n", dev->send_to_fpga_interval); 2137 | if(dev->send_to_fpga_interval > 200) 2138 | { 2139 | //dev->send_to_fpga_interval = 200; 2140 | dev->send_to_fpga_interval = 100; 2141 | printk_ratelimited(KERN_ERR "Adj Snd Time Interval {%d}ms\n", dev->send_to_fpga_interval); 2142 | } 2143 | is_started = true; 2144 | } 2145 | dev->hw_error_eft = bt_conf->hw_error_eft; 2146 | //dev->cgminer_start = true; 2147 | printk_ratelimited("Set bitmain configure\n"); 2148 | } 2149 | break; 2150 | case BM_GET_STATUS: 2151 | { 2152 | BITMAIN_GET_STATUS_P bt_gt_status = (BITMAIN_GET_STATUS_P) txtask; 2153 | if (bt_gt_status->detect_get) 2154 | { 2155 | asic_reset = true; 2156 | dev->asic_configure.bauddiv = 26; 2157 | printk_ratelimited(KERN_ERR "Detect device\n"); 2158 | detect_chain_num(dev); 2159 | } 2160 | if (bt_gt_status->chip_status_eft) 2161 | { 2162 | dev->asic_configure.chip_address = bt_gt_status->chip_address; 2163 | dev->asic_configure.reg_address = bt_gt_status->reg_addr; 2164 | //bitmain_asic_get_status(NULL, 1, 0, 4); //CHIP_ADDR_REG 4 PLL reg 2165 | } 2166 | if(bt_gt_status->test_hash == 0xba) 2167 | nonce_query(dev); 2168 | dev->get_status = true; 2169 | //printk_ratelimited("Get status\n"); 2170 | } 2171 | break; 2172 | default: 2173 | break; 2174 | } 2175 | if (asic_reset) 2176 | { 2177 | //clear fpga nonce buffer 2178 | clear_fpga_nonce_buffer(dev); 2179 | //T4CONCLR = 0x8000; //Stop Timer 2180 | dev->cgminer_start = false; 2181 | asic_result_status_rd = asic_result_status_wr = asic_result_status_full = 0; 2182 | asic_result_rd = asic_result_wr = asic_result_full = 0; 2183 | gDiff_nonce_num = gNonce_num = gNonce_Err = gNonce_miss = 0; 2184 | gSubmit_nonce_num = 0; 2185 | dev->task_buffer_full = false; 2186 | dev->task_buffer_rd = dev->task_buffer_wr; 2187 | #if 0 2188 | printk_ratelimited("Clear Nonce count\n"); 2189 | for (i = 0; i < CHAIN_SIZE; i++) 2190 | { 2191 | for (j = 0; j < 32; j++) 2192 | { 2193 | gAsic_cnt[i][j] = 0; 2194 | } 2195 | } 2196 | #endif 2197 | } 2198 | } 2199 | 2200 | else 2201 | { 2202 | retval = -EINVAL; 2203 | } 2204 | //spin_unlock(&dev->lock); 2205 | return writesize; 2206 | error: 2207 | //spin_unlock(&dev->lock); 2208 | return retval; 2209 | } 2210 | 2211 | static int create_rx_status_struct(struct BITMAIN_STATUS_DATA *rx_status_data, bool chip_value_eft, uint32_t reg_value, 2212 | uint16_t fifo_sapce, char *temp, int temp_num, char* fan, int fan_num) 2213 | { 2214 | uint16_t crc16; 2215 | uint8_t i, j; 2216 | uint16_t pos = 0; 2217 | BT_AS_INFO dev = &bitmain_asic_dev; 2218 | rx_status_data->chip_value_eft = chip_value_eft; 2219 | rx_status_data->reg_value = reg_value; 2220 | rx_status_data->fifo_space = fifo_sapce; 2221 | rx_status_data->nonce_err = gNonce_Err; 2222 | rx_status_data->hw_version = (DRIVER_VER <<16)|(dev->fpga_version<<8)|(dev->pcb_version); 2223 | rx_status_data->get_blk_num = dev->get_blk_num & 0x0f; 2224 | pos = 28; 2225 | //pos += rx_status_data->chain_num * sizeof(rx_status_data->chain_asic_exist[0]); 2226 | //printk_ratelimited("rx_status_data->chain_num{%d}\n", rx_status_data->chain_num); 2227 | for (i = 0; i < rx_status_data->chain_num; i++) 2228 | { 2229 | #if 0 //S2 FPGA pin debug 添加 2230 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 2231 | continue; 2232 | #endif 2233 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 2234 | gChain_Asic_num[dev->chain_map[i]] = 1; 2235 | for(j = 0; j < (((gChain_Asic_num[dev->chain_map[i]] -1)>>5) + 1); j++) 2236 | { 2237 | *((uint32_t*)((uint8_t*)rx_status_data + pos)) = dev->chain_asic_exist[dev->chain_map[i]][j]; 2238 | pos += sizeof (uint32_t); 2239 | } 2240 | } 2241 | for (i = 0; i < rx_status_data->chain_num; i++) 2242 | { 2243 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 2244 | continue; 2245 | for(j = 0; j < (((gChain_Asic_num[dev->chain_map[i]]-1)>>5) + 1); j++) 2246 | { 2247 | *((uint32_t*)((uint8_t*)rx_status_data + pos)) = gChain_Asic_status[dev->chain_map[i]][j]; 2248 | pos += sizeof (uint32_t); 2249 | } 2250 | } 2251 | for (i = 0; i < rx_status_data->chain_num; i++) 2252 | { 2253 | *((char*) rx_status_data + pos) = gChain_Asic_num[dev->chain_map[i]]; 2254 | pos++; 2255 | } 2256 | rx_status_data->temp_num = temp_num; 2257 | if ((rx_status_data->temp_num != 0) && (temp != NULL)) 2258 | { 2259 | for (i = 0; i < rx_status_data->temp_num; i++) 2260 | { 2261 | *((char*) rx_status_data + pos) = dev->temp[dev->chain_map[i]]; 2262 | pos++; 2263 | } 2264 | } 2265 | rx_status_data->fan_num = fan_num; 2266 | if ((rx_status_data->fan_num != 0) && (fan != NULL)) 2267 | { 2268 | for (i = 0; i < rx_status_data->fan_num; i++) 2269 | { 2270 | *((char*) rx_status_data + pos) = dev->fan_speed[dev->fan_map[i]]; 2271 | pos++; 2272 | } 2273 | } 2274 | rx_status_data->length = pos + 2 - 4;//加crc 两个字节去除前四个字节 2275 | crc16 = CRC16((const uint8_t*)rx_status_data, pos); 2276 | *((char*) rx_status_data + pos) = crc16 & 0xff; 2277 | *((char*) rx_status_data + pos + 1) = (char) (crc16 >> 8); 2278 | return rx_status_data->length + 4; 2279 | } 2280 | 2281 | static ssize_t bitmain_asic_read(struct file *file, char __user *userbuf, 2282 | size_t count, loff_t *ppos) 2283 | { 2284 | BT_AS_INFO dev = file->private_data; 2285 | int retval = 0, i; 2286 | static unsigned long ret_ttn_timeout = 0; 2287 | if(dev->fpga_ok == false) 2288 | { 2289 | wait_queue_head_t timeout_wq; 2290 | init_waitqueue_head(&timeout_wq); 2291 | interruptible_sleep_on_timeout(&timeout_wq, 10 * HZ/1000);//10ms 2292 | return -EIO; 2293 | } 2294 | if(ret_ttn_timeout == 0) 2295 | ret_ttn_timeout = jiffies; 2296 | spin_lock(&dev->lock); 2297 | //bitmain_asic_open_usb(dev); 2298 | mutex_lock(&dev->result_lock); 2299 | #if 0 2300 | if(1/*time_after(jiffies, Prnt_time_out) && (dev->cgminer_start)*/) 2301 | { 2302 | local_bh_disable(); 2303 | while( 4 == nonce_query(dev)) ; 2304 | //mod_timer(&prnt_timer, jiffies + 20*HZ/1000); //Start Timer 20ms 2305 | local_bh_enable(); 2306 | } 2307 | if(g_FPGA_FIFO_SPACE > g_FPGA_RESERVE_FIFO_SPACE) 2308 | send_to_pfga_work(dev); 2309 | #endif 2310 | //printk_ratelimited(KERN_ERR "33work_id{%d}addr{%#x}\n",asic_result[33].work_id, &(asic_result[33].work_id)); 2311 | if (dev->task_buffer_full) 2312 | { 2313 | fifo_space = 0; 2314 | } 2315 | else 2316 | { 2317 | if (dev->task_buffer_wr >= dev->task_buffer_rd) 2318 | { 2319 | fifo_space = dev->task_buffer_size - (dev->task_buffer_wr - dev->task_buffer_rd); 2320 | } 2321 | else 2322 | { 2323 | fifo_space = dev->task_buffer_rd - dev->task_buffer_wr; 2324 | } 2325 | //防止full，预留位置，存储已发送的上几个数据 2326 | if (fifo_space >= TASK_PRE_LEFT) 2327 | fifo_space -= TASK_PRE_LEFT; 2328 | else 2329 | fifo_space = 0; 2330 | } 2331 | //dev->get_status = true; 2332 | if ((asic_result_full || (asic_result_rd != asic_result_wr))/* && ((T4CON & 0x8000) != 0)*/)//正在task work 2333 | { 2334 | struct BITMAIN_RESULT bitmain_result; 2335 | uint8_t nonce_num = 0; 2336 | uint16_t crc16; 2337 | bitmain_result.data_type = BM_RX_NONCE; 2338 | bitmain_result.version = 0x00; 2339 | bitmain_result.nonce_diff = dev->nonce_diff; 2340 | bitmain_result.total_nonce_num = dev->total_nonce_num; 2341 | //bitmain_result.total_nonce_num = dev->diff1_num; //cgminer 不通过nonce diff计算时 2342 | do 2343 | { 2344 | memcpy(&bitmain_result.nonce[nonce_num], (void*)&asic_result[asic_result_rd], sizeof (asic_result[0])); 2345 | nonce_num++; 2346 | //printk_ratelimited(KERN_ERR "work_id{%d}rd{%d}wr{%d}\n",asic_result[asic_result_rd].work_id, asic_result_rd, asic_result_wr); 2347 | increase_variable_rehead_U16(&asic_result_rd, ASIC_RESULT_NUM); 2348 | gSubmit_nonce_num++; 2349 | } 2350 | //while ((asic_result_rd != asic_result_wr) && (nonce_num < 7));//为了不超过64字节 2351 | while ((asic_result_rd != asic_result_wr) && (nonce_num < 128)); 2352 | asic_result_full = 0; 2353 | if(sizeof(bitmain_result.fifo_space) == 1) 2354 | { 2355 | if(fifo_space >= 0x100) 2356 | fifo_space = 0xff; 2357 | bitmain_result.fifo_space = (uint8_t)fifo_space; 2358 | } 2359 | else 2360 | bitmain_result.fifo_space = fifo_space; 2361 | //bitmain_result.nonce_num = nonce_num; 2362 | bitmain_result.length = nonce_num * (sizeof (asic_result[0])) + 6 + 8; 2363 | crc16 = CRC16((const uint8_t*) &bitmain_result, bitmain_result.length + 2); 2364 | *((char*) &bitmain_result + bitmain_result.length + 2) = crc16 & 0xff; 2365 | *((char*) &bitmain_result + bitmain_result.length + 2 + 1) = (char) (crc16 >> 8); 2366 | retval = bitmain_result.length + 4; 2367 | last_read_nonce_jiffies = jiffies; 2368 | //printk_ratelimited("read %d nonce\n", nonce_num); 2369 | //gNonce_num += nonce_num; 2370 | if (0 != copy_to_user(userbuf, (void*)&bitmain_result, retval)) 2371 | { 2372 | retval = -EFAULT; 2373 | } 2374 | } 2375 | else if (dev->get_status) 2376 | { 2377 | dev->get_status = false; 2378 | if (asic_result_status_full || (asic_result_status_rd != asic_result_status_wr)) 2379 | { 2380 | asic_result_status_full = 0; 2381 | //printk_ratelimited("status return\n"); 2382 | retval = create_rx_status_struct(&dev->asic_status_data, true, asic_result_status[asic_result_status_rd], 2383 | fifo_space, dev->temp, dev->temp_num, dev->fan_speed, dev->fan_num); 2384 | increase_variable_rehead_U16(& asic_result_status_rd, ASIC_RESULT_STATUS_NUM); 2385 | } 2386 | else 2387 | { 2388 | retval = create_rx_status_struct(&dev->asic_status_data, false, 0, 2389 | fifo_space, dev->temp, dev->temp_num, dev->fan_speed, dev->fan_num); 2390 | } 2391 | //printk_ratelimited("get_status:fifo_space %d rd(%d)wr(%d)\n",fifo_space,dev->task_buffer_rd,dev->task_buffer_wr); 2392 | if(retval > count) 2393 | { 2394 | retval = count; 2395 | printk_ratelimited(KERN_ERR "count too small in %s\n", __func__); 2396 | } 2397 | 2398 | if (0 != copy_to_user(userbuf, (void*)& dev->asic_status_data, retval)) 2399 | { 2400 | retval = -EFAULT; 2401 | } 2402 | if((retval >0 ) && (rx_st_prnt)) 2403 | { 2404 | printk_ratelimited("rx_status data is:\n"); 2405 | for(i = 0; i < retval; i++) 2406 | { 2407 | if(0 == (i %16)) 2408 | printk_ratelimited("\n 0x%02x: ", i); 2409 | printk_ratelimited("0x%02x, ", *((char*)&dev->asic_status_data + i)); 2410 | } 2411 | printk_ratelimited("\n"); 2412 | } 2413 | } 2414 | #if 1 2415 | else if((dev->cgminer_start == true) && time_after(jiffies, ret_ttn_timeout)) 2416 | { 2417 | struct BITMAIN_RESULT bitmain_result; 2418 | uint16_t crc16; 2419 | bitmain_result.data_type = BM_RX_NONCE; 2420 | bitmain_result.version = 0x00; 2421 | bitmain_result.nonce_diff = dev->nonce_diff; 2422 | bitmain_result.total_nonce_num = dev->total_nonce_num; 2423 | if(sizeof(bitmain_result.fifo_space) == 1) 2424 | { 2425 | if(fifo_space >= 0x100) 2426 | fifo_space = 0xff; 2427 | bitmain_result.fifo_space = (uint8_t)fifo_space; 2428 | } 2429 | else 2430 | bitmain_result.fifo_space = fifo_space; 2431 | //bitmain_result.nonce_num = 0; 2432 | bitmain_result.length = 6 + 8; 2433 | crc16 = CRC16((const uint8_t*) &bitmain_result, bitmain_result.length + 2); 2434 | *((char*) &bitmain_result + bitmain_result.length + 2) = crc16 & 0xff; 2435 | *((char*) &bitmain_result + bitmain_result.length + 2 + 1) = (char) (crc16 >> 8); 2436 | retval = bitmain_result.length + 4; 2437 | //printk_ratelimited("fifo_space %d rd(%d)wr(%d)\n",fifo_space,dev->task_buffer_rd,dev->task_buffer_wr); 2438 | if (0 != copy_to_user(userbuf, (void*)&bitmain_result, retval)) 2439 | { 2440 | retval = -EFAULT; 2441 | } 2442 | //printk_ratelimited(KERN_ERR "ttn %llu\n", dev->total_nonce_num); 2443 | ret_ttn_timeout = jiffies + 1000 * HZ/1000;//1000ms; 2444 | } 2445 | #endif 2446 | mutex_unlock(&dev->result_lock); 2447 | spin_unlock(&dev->lock); 2448 | //printk_ratelimited("out read{%d}\n", retval); 2449 | return retval; 2450 | } 2451 | /* 2452 | * Handle commands from user-space. 2453 | */ 2454 | 2455 | typedef struct __FPGA_DATA { 2456 | unsigned int data_len; 2457 | unsigned char *pdata; 2458 | unsigned int nStatus; 2459 | } FPGA_DATA; 2460 | 2461 | #define FPGA_DL_IOC_MAGIC 'p' 2462 | 2463 | #define START_CONFIG _IOWR(FPGA_DL_IOC_MAGIC, 0, unsigned int) 2464 | #define CONFIG_DATA _IOWR(FPGA_DL_IOC_MAGIC, 1, FPGA_DATA) 2465 | #define CONFIG_DONE _IOWR(FPGA_DL_IOC_MAGIC, 2, unsigned int) 2466 | 2467 | /*************************** 2468 | DCLK gpio2_6 gpio70 P8 45 2469 | nConfig gpio2_8 gpio72 P8 43 in 2470 | nStatus gpio2_10 gpio74 P8 41 2471 | CONF_DONE gpio2_12 gpio76 P8 39 in 2472 | Data gpio3_15 gpio111 P9 29 out 2473 | ***************************/ 2474 | static unsigned char data_buffer[1024*8]; 2475 | #if 0 2476 | static long bitmain_asic_ioctl(struct file *file, 2477 | unsigned int cmd, unsigned long arg) 2478 | { 2479 | int ret = -ENOTTY; 2480 | FPGA_DATA fdata; 2481 | unsigned int i, j; 2482 | unsigned char fpga_data; 2483 | //void __user *argp = (void __user *)arg; 2484 | unsigned int nStatus = 1; 2485 | static void *ctl_md_vaddr; 2486 | switch (cmd) { 2487 | case START_CONFIG: 2488 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 2489 | //Set SPI1 D0 to GPIO mode 2490 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + conf_mcasp0_fsx); //D0 MISO 2491 | //Dclk 2492 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8a0); 2493 | //nConfig 2494 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8a8); 2495 | //nStatus 2496 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8b0); 2497 | //Config_Don 2498 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8b8); 2499 | gpio2_vaddr = ioremap_nocache(GPIO2_BASE, GPIO2_SIZE); 2500 | gpio3_vaddr = ioremap_nocache(GPIO3_BASE, GPIO3_SIZE); 2501 | // set Dclk nConfig out 2502 | iowrite32(ioread32(gpio2_vaddr + GPIO_OE) & (~((0x01<<6) | (0x01<<8))), gpio2_vaddr + GPIO_OE); 2503 | iowrite32(ioread32(gpio3_vaddr + GPIO_OE)& (~(0x01<<15)), gpio3_vaddr + GPIO_OE); 2504 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_CLEARDATAOUT); 2505 | // nCONFIG="0"，使FPGA进入配置状态 2506 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 2507 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 2508 | udelay(5); 2509 | // 检测nSTATUS，如果为"0"，表明FPGA已响应配置要求，可开始进行配置。否则报错 2510 | if ((ioread32(gpio2_vaddr + GPIO_DATAIN) & (0x01 << 10))!= 0) 2511 | { 2512 | printk_ratelimited(KERN_ERR "FPGA don't responed config{%#x}\n", ioread32(gpio2_vaddr + GPIO_DATAIN)); 2513 | nStatus = 0; 2514 | } 2515 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 2516 | copy_to_user((unsigned char*)arg, (unsigned char*)&nStatus, sizeof(unsigned int)); 2517 | break; 2518 | case CONFIG_DATA: 2519 | copy_from_user((unsigned char*)&fdata, (unsigned char*)arg, sizeof(fdata)); 2520 | printk_ratelimited("fdata.pdata{%#x}len{%d}\n", (unsigned int)fdata.pdata, fdata.data_len); 2521 | copy_from_user(data_buffer, (unsigned char*)fdata.pdata, fdata.data_len); 2522 | for(j = 0; j < fdata.data_len; j++) 2523 | { 2524 | fpga_data = data_buffer[j]; 2525 | //printf("fpga_data %#x\n", fpga_data); 2526 | for (i=0; i<8; i++) 2527 | { // DCLK="0"时，在Data0上放置数据（LSB first） 2528 | if(fpga_data&0x01) 2529 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_SETDATAOUT); 2530 | else 2531 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_CLEARDATAOUT); 2532 | // DCLK->"1"，使FPGA读入数据 2533 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 2534 | fpga_data >>= 1; // 准备下一位数据 2535 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 2536 | //if (get_gpio(pnSt) == 0) 2537 | if ((ioread32(gpio2_vaddr + GPIO_DATAIN) & (0x01 << 10))== 0) 2538 | { // 检测nSTATUS，如果为"0"，表明FPGA配置出错 2539 | printk_ratelimited(KERN_ERR "FPGA config err {%#x}\n", ioread32(gpio2_vaddr + GPIO_DATAIN)); 2540 | nStatus = 0; 2541 | break; 2542 | } 2543 | } 2544 | if(nStatus == 0) 2545 | break; 2546 | } 2547 | fdata.nStatus = nStatus; 2548 | copy_to_user((unsigned char*)arg, (unsigned char*)&fdata, sizeof(fdata)); 2549 | break; 2550 | case CONFIG_DONE: 2551 | for(i=0; i<10; i++) 2552 | { 2553 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 2554 | udelay(5); 2555 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 2556 | udelay(5); 2557 | } 2558 | //ctrl_gpio(pData, false); 2559 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_CLEARDATAOUT); 2560 | if ((ioread32(gpio2_vaddr + GPIO_DATAIN) & (0x01 << 12)) == 0) 2561 | { // 检测nCONF_Done，如果为"0"，表明FPGA配置未成功 2562 | printk_ratelimited(KERN_ERR "Configure failure\n"); 2563 | nStatus = 0; 2564 | } 2565 | //Set SPI1 D0 to GPIO mode 2566 | iowrite32(PAD_REV | PAD_PULLUP | 0x3, ctl_md_vaddr + conf_mcasp0_fsx); //D0 MISO 2567 | iounmap(ctl_md_vaddr); 2568 | copy_to_user((unsigned char*)arg, (unsigned char*)&nStatus, sizeof(unsigned int)); 2569 | break; 2570 | default: 2571 | printk_ratelimited("IOCTL cmd not surpport{%#x}{%d}\n", cmd,_IOC_NR(cmd)); 2572 | return -ENOTTY; 2573 | } 2574 | if(nStatus == 0) 2575 | { 2576 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 2577 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 2578 | iounmap(gpio2_vaddr); 2579 | } 2580 | return ret; 2581 | } 2582 | #else 2583 | 2584 | /********************************************************* 2585 | DCLK gpio0_4 gpio04 P9 18 out I2C1_SDA/SPI0_D1 2586 | nConfig gpio1_19 gpio51 P9 16 in EHRPWM1B/GPMC_A3 2587 | nStatus gpio0_12 gpio12 P9 20 out I2C2_SDA/UART1_CTSN 2588 | CONF_DONE gpio0_7 gpio07 P9 42 in GPIO0_7/ECAP0_IN_PWM0_OUT 2589 | Data gpio3_15 gpio111 P9 29 out SPI1_D0 2590 | FPGA_rst gpio1_28 gpio50 P9 12 out GPMC_BE1N 2591 | ***********************************************************/ 2592 | static long bitmain_asic_ioctl(struct file *file, 2593 | unsigned int cmd, unsigned long arg) 2594 | { 2595 | int ret = -ENOTTY; 2596 | FPGA_DATA fdata; 2597 | unsigned int i, j; 2598 | unsigned char fpga_data; 2599 | //void __user *argp = (void __user *)arg; 2600 | unsigned int nStatus = 1; 2601 | static void *ctl_md_vaddr; 2602 | wait_queue_head_t timeout_wq; 2603 | switch (cmd) { 2604 | case START_CONFIG: 2605 | config_fpga = 1; 2606 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 2607 | //Set SPI1 D0 to GPIO mode 2608 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + conf_mcasp0_fsx); //D0 MISO 2609 | //Dclk 2610 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x958); 2611 | //nConfig 2612 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x84C); 2613 | //nStatus 2614 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x978); 2615 | //Config_Don 2616 | iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x964); 2617 | //FPGA_rst 2618 | iowrite32(PAD_PULL_DIS| 0x7, ctl_md_vaddr + 0x878); 2619 | //net check led 2620 | //iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x878); 2621 | //gpio0_vaddr = ioremap_nocache(GPIO0_BASE, GPIO0_SIZE); 2622 | gpio1_vaddr = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE); 2623 | gpio3_vaddr = ioremap_nocache(GPIO3_BASE, GPIO3_SIZE); 2624 | // set Dclk nConfig out 2625 | iowrite32(ioread32(gpio0_vaddr + GPIO_OE) & (~((0x01<<4))), gpio0_vaddr + GPIO_OE); 2626 | iowrite32(ioread32(gpio1_vaddr + GPIO_OE) & (~((0x01<<19))) & (~((0x01<<28))), gpio1_vaddr + GPIO_OE); 2627 | iowrite32(ioread32(gpio3_vaddr + GPIO_OE)& (~(0x01<<15)), gpio3_vaddr + GPIO_OE); 2628 | //FPGA_rst high 2629 | iowrite32(0x01<<28, gpio1_vaddr + GPIO_SETDATAOUT); 2630 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_CLEARDATAOUT); 2631 | // nCONFIG="0"，使FPGA进入配置状态 2632 | iowrite32(0x01<<19, gpio1_vaddr + GPIO_CLEARDATAOUT); 2633 | iowrite32(0x01<<4, gpio0_vaddr + GPIO_CLEARDATAOUT); 2634 | udelay(5); 2635 | // 检测nSTATUS，如果为"0"，表明FPGA已响应配置要求，可开始进行配置。否则报错 2636 | if ((ioread32(gpio0_vaddr + GPIO_DATAIN) & (0x01 << 12))!= 0) 2637 | { 2638 | printk_ratelimited(KERN_ERR "FPGA don't responed config{%#x}\n", ioread32(gpio0_vaddr + GPIO_DATAIN)); 2639 | nStatus = 0; 2640 | } 2641 | iowrite32(0x01<<19, gpio1_vaddr + GPIO_SETDATAOUT); 2642 | copy_to_user((unsigned char*)arg, (unsigned char*)&nStatus, sizeof(unsigned int)); 2643 | break; 2644 | case CONFIG_DATA: 2645 | copy_from_user((unsigned char*)&fdata, (unsigned char*)arg, sizeof(fdata)); 2646 | //printk_ratelimited("fdata.pdata{%#x}len{%d}\n", (unsigned int)fdata.pdata, fdata.data_len); 2647 | copy_from_user(data_buffer, (unsigned char*)fdata.pdata, fdata.data_len); 2648 | for(j = 0; j < fdata.data_len; j++) 2649 | { 2650 | fpga_data = data_buffer[j]; 2651 | //printf("fpga_data %#x\n", fpga_data); 2652 | for (i=0; i<8; i++) 2653 | { // DCLK="0"时，在Data0上放置数据（LSB first） 2654 | if(fpga_data&0x01) 2655 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_SETDATAOUT); 2656 | else 2657 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_CLEARDATAOUT); 2658 | // DCLK->"1"，使FPGA读入数据 2659 | iowrite32(0x01<<4, gpio0_vaddr + GPIO_SETDATAOUT); 2660 | fpga_data >>= 1; // 准备下一位数据 2661 | iowrite32(0x01<<4, gpio0_vaddr + GPIO_CLEARDATAOUT); 2662 | //if (get_gpio(pnSt) == 0) 2663 | if ((ioread32(gpio0_vaddr + GPIO_DATAIN) & (0x01 << 12))== 0) 2664 | { // 检测nSTATUS，如果为"0"，表明FPGA配置出错 2665 | printk_ratelimited(KERN_ERR "FPGA config err {%#x}\n", ioread32(gpio0_vaddr + GPIO_DATAIN)); 2666 | nStatus = 0; 2667 | break; 2668 | } 2669 | } 2670 | if(nStatus == 0) 2671 | break; 2672 | } 2673 | fdata.nStatus = nStatus; 2674 | copy_to_user((unsigned char*)arg, (unsigned char*)&fdata, sizeof(fdata)); 2675 | break; 2676 | case CONFIG_DONE: 2677 | init_waitqueue_head(&timeout_wq); 2678 | for(i=0; i<10; i++) 2679 | { 2680 | iowrite32(0x01<<4, gpio0_vaddr + GPIO_SETDATAOUT); 2681 | udelay(1); 2682 | iowrite32(0x01<<4, gpio0_vaddr + GPIO_CLEARDATAOUT); 2683 | udelay(1); 2684 | } 2685 | //ctrl_gpio(pData, false); 2686 | iowrite32(0x01<<15, gpio3_vaddr + GPIO_CLEARDATAOUT); 2687 | if ((ioread32(gpio0_vaddr + GPIO_DATAIN) & (0x01 << 7)) == 0) 2688 | { // 检测nCONF_Done，如果为"0"，表明FPGA配置未成功 2689 | printk_ratelimited(KERN_ERR "Configure failure\n"); 2690 | nStatus = 0; 2691 | } 2692 | //Set SPI1 D0 to GPIO mode 2693 | iowrite32(PAD_REV | PAD_PULLUP | 0x3, ctl_md_vaddr + conf_mcasp0_fsx); //D0 MISO 2694 | iounmap(ctl_md_vaddr); 2695 | //iounmap(gpio0_vaddr); 2696 | iowrite32(0x01<<28, gpio1_vaddr + GPIO_CLEARDATAOUT); 2697 | interruptible_sleep_on_timeout(&timeout_wq, 100 * HZ/1000);//100ms 2698 | iowrite32(0x01<<28, gpio1_vaddr + GPIO_SETDATAOUT); 2699 | iounmap(gpio1_vaddr); 2700 | copy_to_user((unsigned char*)arg, (unsigned char*)&nStatus, sizeof(unsigned int)); 2701 | break; 2702 | default: 2703 | printk_ratelimited("IOCTL cmd not surpport{%#x}{%d}\n", cmd,_IOC_NR(cmd)); 2704 | return -ENOTTY; 2705 | } 2706 | if(nStatus == 0) 2707 | { 2708 | iowrite32(0x01<<4, gpio0_vaddr + GPIO_SETDATAOUT); 2709 | iowrite32(0x01<<19, gpio1_vaddr + GPIO_SETDATAOUT); 2710 | iounmap(gpio0_vaddr); 2711 | iounmap(gpio1_vaddr); 2712 | } 2713 | return ret; 2714 | } 2715 | 2716 | #endif 2717 | 2718 | static const struct file_operations bitmain_asic_fops = { 2719 | .owner = THIS_MODULE, 2720 | .read = bitmain_asic_read, 2721 | .write = bitmain_asic_write, 2722 | .open = bitmain_asic_open, 2723 | .release = bitmain_asic_close, 2724 | .unlocked_ioctl = bitmain_asic_ioctl, 2725 | }; 2726 | 2727 | static struct miscdevice bitmain_asic = { 2728 | .minor = MISC_DYNAMIC_MINOR, 2729 | .name = DRV_NAME, 2730 | .fops = &bitmain_asic_fops, 2731 | }; 2732 | 2733 | static int __init bitmain_asic_init(void) 2734 | { 2735 | struct ASIC_TASK asic_task; 2736 | uint32_t nonce; 2737 | 2738 | pr_info("%s v%s (built %s %s)\n", DRV_DESC, DRV_VERSION, __DATE__, 2739 | __TIME__); 2740 | 2741 | spi_init(); 2742 | 2743 | asic_task.work_id = 0xffffffff; 2744 | 2745 | hex2bin(asic_task.midstate, g_midstate, sizeof(asic_task.midstate)); 2746 | hex2bin(asic_task.data, g_data, sizeof(asic_task.data)); 2747 | hex2bin((uint8_t *)&nonce, g_nonce, sizeof(nonce)); 2748 | 2749 | rev(asic_task.midstate, sizeof(asic_task.midstate)); 2750 | rev(asic_task.data, sizeof(asic_task.data)); 2751 | rev((uint8_t *)&nonce, sizeof(nonce)); 2752 | 2753 | if (hashtest(&asic_task, nonce)) 2754 | pr_info("hashtest OK\n"); 2755 | else 2756 | pr_err("hashtest failed\n"); 2757 | 2758 | if (misc_register(&bitmain_asic)) { 2759 | pr_err("%s: misc_register failed\n", DRV_NAME); 2760 | return -1; 2761 | } 2762 | return 0; 2763 | } 2764 | module_init(bitmain_asic_init); 2765 | 2766 | static void __exit bitmain_asic_exit(void) 2767 | { 2768 | spi_close(); 2769 | if (misc_deregister(&bitmain_asic) < 0) 2770 | pr_err("%s: misc_deregister failed\n", DRV_NAME); 2771 | } 2772 | module_exit(bitmain_asic_exit); 2773 | 2774 | MODULE_LICENSE("GPL v2"); 2775 | MODULE_AUTHOR("Xuelei "); 2776 | MODULE_DESCRIPTION(DRV_DESC); 2777 | MODULE_VERSION(DRV_VERSION); 2778 | 2779 | 2780 | 2781 | -------------------------------------------------------------------------------- /bitmain-asic.h: -------------------------------------------------------------------------------- 1 | #ifndef __BITMAIN_ASIC_H__ 2 | #define __BITMAIN_ASIC_H__ 3 | 4 | #define HAVE_NUM 0 5 | #define PACKED __attribute__( ( packed, aligned(4) ) ) 6 | 7 | #define CHAIN_SIZE 16 8 | 9 | #define BM_TX_CONF 0x51 10 | #define BM_TX_TASK 0x52 11 | #define BM_GET_STATUS 0x53 12 | #define BM_STATUS_DATA 0xa1 13 | #define BM_RX_NONCE 0xa2 14 | 15 | #define CNF_REST (0x01<<0) 16 | 17 | #define CNF_FAN (0x01<<1) 18 | #define CNF_TIMEOUT (0x01<<2) 19 | #define CNF_FREQUENCY (0x01<<3) 20 | #define CNF_VOLTAGE (0x01<<4) 21 | #define CNF_CCHECKT (0x01<<5) 22 | #define CNF_CHIP_CNF (0x01<<6) 23 | 24 | struct BITMAIN_CONFIGURE { 25 | uint8_t token_type; 26 | uint8_t version; 27 | uint16_t length; 28 | /* 29 | uint8_t rccvftfr; 30 | */ 31 | uint8_t reset : 1; 32 | uint8_t fan_eft : 1; 33 | uint8_t timeout_eft : 1; 34 | uint8_t frequency_eft : 1; 35 | uint8_t voltage_eft : 1; 36 | uint8_t chain_check_time_eft : 1; 37 | uint8_t chip_config_eft : 1; 38 | uint8_t hw_error_eft : 1; 39 | uint8_t beeper_ctrl : 1; 40 | uint8_t temp_over_ctrl : 1; 41 | uint8_t fan_ctrl_type : 1; //0: normal 1: home 42 | uint8_t reserved1 : 5; 43 | 44 | uint8_t chain_check_time; 45 | uint8_t reserved2; 46 | uint8_t chain_num; 47 | uint8_t asic_num; 48 | uint8_t fan_pwm_data; 49 | uint8_t timeout_data; 50 | 51 | uint16_t frequency; 52 | uint16_t voltage; 53 | 54 | uint32_t reg_data; 55 | 56 | uint8_t chip_address; 57 | uint8_t reg_address; 58 | uint16_t crc; 59 | } PACKED; 60 | 61 | typedef struct BITMAIN_CONFIGURE* BITMAIN_CONFIGURE_P; 62 | 63 | 64 | struct ASIC_TASK 65 | { 66 | uint32_t work_id; 67 | uint8_t midstate[32]; 68 | uint8_t data[12]; 69 | }PACKED; 70 | typedef struct ASIC_TASK* ASIC_TASK_P; 71 | 72 | #define NEW_BLK 0x01 73 | struct BITMAIN_TASK { 74 | uint8_t token_type; 75 | uint8_t version; 76 | uint16_t length; 77 | uint8_t new_block :1; 78 | uint8_t reserved :7; 79 | uint8_t diff; 80 | uint16_t net_diff; 81 | struct ASIC_TASK asic_task[64]; 82 | uint16_t crc; 83 | }PACKED; 84 | 85 | #if 0 86 | struct BITMAIN_TASK { 87 | uint8_t token_type; 88 | #if HAVE_NUM 89 | uint8_t length; 90 | uint8_t new_block :1; 91 | uint8_t reserved1 :7; 92 | 93 | /*uint8_t rnew_block;*/ 94 | uint8_t work_num; 95 | #else 96 | uint16_t length; 97 | uint8_t new_block :1; 98 | uint8_t reserved1 :7; 99 | #endif 100 | struct ASIC_TASK asic_task[8]; 101 | uint16_t crc; 102 | }PACKED; 103 | #endif 104 | typedef struct BITMAIN_TASK* BITMAIN_TASK_P; 105 | 106 | #define DETECT_GET 0x02 107 | #define GET_CHIP_ST 0x01 108 | struct BITMAIN_GET_STATUS { 109 | uint8_t token_type; 110 | uint8_t version; 111 | uint16_t length; 112 | 113 | uint8_t chip_status_eft :1; 114 | uint8_t detect_get :1; 115 | uint8_t reserved1 :6; 116 | 117 | /*uint8_t rchipd_eft;*/ 118 | uint8_t test_hash; //0xba 119 | uint8_t reserved[2]; 120 | //uint32_t reg_data; 121 | uint8_t chip_address; 122 | uint8_t reg_addr; 123 | uint16_t crc; 124 | }PACKED; 125 | typedef struct BITMAIN_GET_STATUS* BITMAIN_GET_STATUS_P; 126 | #if 0 127 | struct BITMAIN_STATUS_DATA_HEADER { 128 | uint8_t data_type; 129 | uint8_t length; 130 | /* 131 | uint8_t chip_reg_value_eft :1; 132 | uint8_t reserved1 :7; 133 | */ 134 | uint8_t rchipregval_eft; 135 | uint8_t reserved; 136 | uint32_t reg_value; 137 | uint8_t core_num; 138 | uint8_t asic_num; 139 | uint8_t temp_sensor_num; 140 | uint8_t fan_num; 141 | uint32_t fifo_space; 142 | /* 143 | uint8_t temp[temp_sensor_num]; 144 | uint8_t fan[fan_num]; 145 | uint16_t crc; 146 | */ 147 | }PACKED; 148 | #endif 149 | struct BITMAIN_STATUS_DATA { 150 | //struct BITMAIN_STATUS_DATA_HEADER status_header; 151 | uint8_t data_type; 152 | uint8_t version; 153 | uint16_t length; 154 | 155 | uint8_t chip_value_eft : 1; 156 | uint8_t reserved1 : 3; 157 | uint8_t get_blk_num : 4; 158 | uint8_t chain_num; 159 | uint16_t fifo_space; 160 | uint32_t hw_version; 161 | uint8_t fan_num; 162 | uint8_t temp_num; 163 | uint16_t fan_exist; 164 | uint32_t temp_exist; 165 | /*uint8_t rchipregval_eft;*/ 166 | //uint8_t fifo_space; 167 | uint32_t nonce_err; 168 | uint32_t reg_value; 169 | uint32_t chain_asic_exist[CHAIN_SIZE][8]; 170 | uint32_t chain_asic_status[CHAIN_SIZE][8]; 171 | uint8_t chain_asic_num[CHAIN_SIZE]; 172 | uint8_t temp[16]; 173 | uint8_t fan[16]; 174 | uint16_t crc; 175 | } PACKED; 176 | 177 | struct ASIC_RESULT{ 178 | uint32_t work_id; 179 | uint32_t nonce; 180 | }; 181 | 182 | struct BITMAIN_RESULT { 183 | uint8_t data_type; 184 | uint8_t version; 185 | uint16_t length; 186 | uint16_t fifo_space; 187 | uint16_t nonce_diff; 188 | uint64_t total_nonce_num; 189 | struct ASIC_RESULT nonce[128]; 190 | uint16_t crc; 191 | } PACKED; 192 | 193 | struct ASIC_WORK 194 | { 195 | uint8_t midstate[32]; 196 | uint8_t pad[64-32-12]; 197 | uint8_t data[12]; 198 | uint32_t nonce2; 199 | }PACKED; 200 | typedef struct ASIC_WORK* ASIC_WORK_P; 201 | 202 | #define be32toh be32_to_cpu 203 | 204 | 205 | typedef struct { 206 | uint8_t chain_num; 207 | uint8_t asic_num; 208 | uint8_t fan_pwm_data; 209 | uint8_t timeout_data; 210 | uint8_t diff_sh_bit; 211 | uint8_t bauddiv; 212 | uint16_t voltage; 213 | uint16_t frequency; 214 | uint16_t freq_vlaue; 215 | 216 | uint8_t chain_check_time; 217 | uint8_t chip_address; 218 | uint8_t reg_address; 219 | bool beep_on_en; 220 | bool snd_work_when_temp_h; 221 | } ASIC_CONFIGURE; 222 | 223 | typedef struct __BT_AS_info { 224 | int64_t diff1_num; 225 | uint64_t total_nonce_num; 226 | spinlock_t lock; 227 | struct mutex result_lock; 228 | struct mutex to_work_lock; 229 | void __iomem *virt_addr; 230 | unsigned irq; 231 | void *beep_virtual_addr; 232 | void *led_virtual; 233 | void *led_virtual1; 234 | struct workqueue_struct *send_to_fpga_work_wq; 235 | struct work_struct send_to_fpga_work; 236 | struct delayed_work usb_rdata_work; 237 | ASIC_TASK_P task_buffer; 238 | uint32_t fifo_empt_cnt; 239 | uint16_t fpga_version; 240 | uint16_t pcb_version; 241 | uint16_t fpga_fifo_st; 242 | uint8_t fan_num; 243 | uint8_t temp_num; 244 | uint32_t chain_exist; 245 | uint32_t chain_asic_exist[CHAIN_SIZE][8]; 246 | uint8_t chain_map[CHAIN_SIZE]; 247 | 248 | uint8_t fan_exist; 249 | uint8_t fan_map[CHAIN_SIZE]; 250 | uint8_t fan_speed[CHAIN_SIZE]; 251 | 252 | uint8_t temp[CHAIN_SIZE]; 253 | uint8_t temp_highest; 254 | uint8_t pwm_percent; 255 | uint32_t pwm_high_value; 256 | uint32_t pwm_low_value; 257 | uint32_t send_to_fpga_interval; 258 | unsigned long last_nonce_timeout; 259 | unsigned long cgminer_start_time; 260 | #if 0 261 | unsigned int task_lllast_num[CHAIN_SIZE]; 262 | unsigned int task_llast_num[CHAIN_SIZE]; 263 | unsigned int task_last_num[CHAIN_SIZE]; 264 | unsigned int task_current_num[CHAIN_SIZE]; 265 | #endif 266 | //unsigned int save_send_work[CHAIN_SIZE][SAVE_SEND_SIZE]; 267 | unsigned int save_send_work; 268 | unsigned int task_buffer_size; 269 | unsigned int task_buffer_wr; 270 | unsigned int task_buffer_rd; 271 | bool task_buffer_full; 272 | bool fpga_ok; 273 | bool get_status; 274 | bool new_block; 275 | bool snding_work; 276 | bool cgminer_start; 277 | bool clear_fpga_fifo; 278 | bool hw_error_eft; 279 | bool timeout_valid; 280 | bool fan_ctrl_type; //0: nomarl 1: home 281 | bool temp_out_fool; 282 | bool temp_out_high; 283 | bool temp_out_ctrl; 284 | bool all_fan_stop; 285 | bool any_fan_fail; 286 | bool beep_ctrl; 287 | bool beep_status; 288 | bool wait_timeout; 289 | bool restarting_hash; 290 | uint16_t net_diff_sh_bit; 291 | uint8_t get_blk_num; 292 | uint16_t nonce_diff; 293 | uint32_t fpga_nonce1_num; 294 | ASIC_CONFIGURE asic_configure; 295 | struct BITMAIN_STATUS_DATA asic_status_data; 296 | } *BT_AS_INFO; 297 | #if SPI_USE_INTERRUPT 298 | #define DRIVER_VER 0x02 299 | #else 300 | #define DRIVER_VER 0x01 301 | #endif 302 | 303 | /***************************************** 304 | version2: using spi interrupt 305 | version3: s3 nand boot 兼容S2 sd boot harward_version =001 306 | ******************************************/ 307 | #undef DRIVER_VER 308 | #define DRIVER_VER 0x03 309 | #define BM_1382 310 | 311 | #define S4_Board 312 | #define AISC_RT_DIFF 0x06 //diff = 2^6 = 64 313 | //不定义时，由硬件自动判断 314 | //sd start lcd无调整 0x7 315 | //sd start lcd调整 0x0 316 | //nand flash start 0x01 317 | //C1 53 54 green led 不兼容nand flash 0x02 318 | //C1.1 兼容nand flash start 0x01，焊接为0x06 319 | #define FIX_HARDWARE_VER 0x1 320 | 321 | #if defined C1_02 322 | #undef FIX_HARDWARE_VER 323 | #define FIX_HARDWARE_VER 0x2 324 | #undef S4_Board 325 | #define C1_Board 326 | #elif defined S5 || defined S4_PLUS 327 | #undef S4_Board 328 | #define S5_S_VL 329 | #define CTL_ASIC_CORE 330 | #endif 331 | 332 | #if defined BM1384 333 | #define BMSC_CORE 55 334 | #endif 335 | 336 | #define BM1385 1 337 | 338 | #if defined BM1385 339 | #define BMSC_CORE 50 340 | #endif 341 | 342 | 343 | //防止full，预留位置，存储已发送的上几个数据 344 | //#define TASK_BUFFER_NUMBER (64*CHAIN_SIZE) 345 | #define TASK_BUFFER_NUMBER (2*8192) 346 | 347 | //#define CHECK_WORK_NUM (32 * 3) 348 | #define CHECK_WORK_NUM (32 * 2) 349 | 350 | //#define TASK_PRE_LEFT (0x800 * 4 /48 + CHECK_WORK_NUM) 351 | #define TASK_PRE_LEFT (1024) 352 | 353 | extern unsigned int gNonce_num, gNonce_Err, gNonce_miss, gDiff_nonce_num; 354 | extern uint32_t gAsic_cnt[CHAIN_SIZE][256]; 355 | extern uint32_t Chain_nonce_nu[CHAIN_SIZE]; 356 | 357 | extern uint16_t gTotal_asic_num; 358 | extern uint8_t gChain_Asic_Check_bit[CHAIN_SIZE]; 359 | extern uint8_t gChain_Asic_Interval[CHAIN_SIZE]; 360 | 361 | extern uint8_t gChain_Asic_num[CHAIN_SIZE]; 362 | extern uint32_t gChain_Asic_status[CHAIN_SIZE][256/32]; 363 | 364 | extern uint32_t ret_nonce_num; 365 | extern uint32_t snd_to_fpga_work; 366 | extern bool fpga_ret_prnt; 367 | 368 | //GPIO2_2(Green) GPIO2_5(Red) 369 | //#define GREEN (0x01<<2) 370 | //#define RED (0x01<<5) 371 | 372 | extern unsigned int GREEN, RED; 373 | extern struct __BT_AS_info bitmain_asic_dev; 374 | extern void *gpio0_vaddr; 375 | 376 | extern int hashtest(ASIC_TASK_P asic_task, uint32_t nonce); 377 | extern void dump_hex(uint8_t *data, uint16_t len); 378 | void send_to_pfga_work(struct work_struct *work); 379 | void init_beep(BT_AS_INFO dev); 380 | void stop_work_to_all_chain(BT_AS_INFO dev); 381 | 382 | 383 | static inline void decrease_variable_rehead_U32(uint32_t *num, uint32_t all_size) 384 | { 385 | if(*num == 0) 386 | *num = all_size; 387 | *num = *num - 1; 388 | return; 389 | } 390 | static inline void increase_variable_rehead_U16(uint16_t *num, uint16_t all_size) 391 | { 392 | *num = *num + 1; 393 | if (*num >= all_size) 394 | *num = 0; 395 | return; 396 | } 397 | 398 | static inline void increase_variable_rehead_U8(uint8_t *num, uint8_t all_size) 399 | { 400 | *num = *num + 1; 401 | if (*num >= all_size) 402 | *num = 0; 403 | return; 404 | } 405 | 406 | #endif 407 | -------------------------------------------------------------------------------- /dts/am335x-ants5.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2016 HashRabbit, Inc. - https://hashrabbit.co 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | 10 | /include/ "am335x-bitmain.dtsi" 11 | 12 | / { 13 | bitmain_spi { 14 | model = "Antminer S5"; 15 | compatible = "bitmain,ants5"; 16 | bm,firmware = "spitop_noncerev_ants5.fw"; 17 | }; 18 | }; 19 | -------------------------------------------------------------------------------- /dts/am335x-ants7.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2016 HashRabbit, Inc. - https://hashrabbit.co 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License version 2 as 6 | * published by the Free Software Foundation. 7 | */ 8 | /dts-v1/; 9 | 10 | /include/ "am335x-bitmain.dtsi" 11 | 12 | / { 13 | bitmain_spi { 14 | model = "Antminer S7"; 15 | compatible = "bitmain,ants7"; 16 | bm,firmware = "spitop_noncerev_ants7.fw"; 17 | }; 18 | }; 19 | -------------------------------------------------------------------------------- /dts/am335x-bitmain.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2015-2016 HashRabbit, Inc. - https://hashrabbit.co/ 3 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 4 | * 5 | * This program is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License version 2 as 7 | * published by the Free Software Foundation. 8 | */ 9 | 10 | /include/ "am33xx.dtsi" 11 | 12 | /include/ "am335x-bone-common.dtsi" 13 | 14 | &am33xx_pinmux { 15 | rstctl_pins: pinmux_rstctl_pins { 16 | pinctrl-single,pins = < 17 | /* eMMC_RSTn */ 18 | 0x50 0x17 /* gpmc_a4.gpio1_20, OUTPUT | MODE7 | PULLUP */ 19 | >; 20 | }; 21 | 22 | nandflash_pins_s0: nandflash_pins_s0 { 23 | pinctrl-single,pins = < 24 | 0x0 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad0.gpmc_ad0 */ 25 | 0x4 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad1.gpmc_ad1 */ 26 | 0x8 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad2.gpmc_ad2 */ 27 | 0xc 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad3.gpmc_ad3 */ 28 | 0x10 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad4.gpmc_ad4 */ 29 | 0x14 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad5.gpmc_ad5 */ 30 | 0x18 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad6.gpmc_ad6 */ 31 | 0x1c 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_ad7.gpmc_ad7 */ 32 | 0x70 0x30 /*(PIN_INPUT_PULLUP | MUX_MODE0) gpmc_wait0.gpmc_wait0 */ 33 | 0x74 0x37 /*(PIN_INPUT_PULLUP | MUX_MODE7) gpmc_wpn.gpio0_30 */ 34 | 0x7c 0x08 /*(PIN_OUTPUT | MUX_MODE0) gpmc_csn0.gpmc_csn0 */ 35 | 0x90 0x08 /*(PIN_OUTPUT | MUX_MODE0) gpmc_advn_ale.gpmc_advn_ale */ 36 | 0x94 0x08 /*(PIN_OUTPUT | MUX_MODE0) gpmc_oen_ren.gpmc_oen_ren */ 37 | 0x98 0x08 /*(PIN_OUTPUT | MUX_MODE0) gpmc_wen.gpmc_wen */ 38 | 0x9c 0x08 /*(PIN_OUTPUT | MUX_MODE0) gpmc_be0n_cle.gpmc_be0n_cle */ 39 | >; 40 | }; 41 | }; 42 | 43 | &ldo3_reg { 44 | regulator-min-microvolt = <1800000>; 45 | regulator-max-microvolt = <1800000>; 46 | regulator-always-on; 47 | }; 48 | 49 | &rstctl { 50 | status = "okay"; 51 | compatible = "gpio-rctrl"; 52 | pinctrl-names = "default"; 53 | pinctrl-0 = <&rstctl_pins>; 54 | 55 | #reset-cells = <2>; 56 | 57 | gpios = <&gpio2 20 0x00>; 58 | gpio-names = "eMMC_RSTn"; 59 | }; 60 | 61 | &mmc1 { 62 | vmmc-supply = <&vmmcsd_fixed>; 63 | }; 64 | 65 | &mmc2 { 66 | vmmc-supply = <&vmmcsd_fixed>; 67 | bus-width = <8>; 68 | ti,non-removable; 69 | status = "disabled"; 70 | 71 | reset = <&rstctl 0 0>; 72 | reset-names = "eMMC_RSTn-CONSUMER"; 73 | }; 74 | 75 | &cpu { 76 | /* 77 | * To consider voltage drop between PMIC and SoC, 78 | * tolerance value is reduced to 2% from 4% and 79 | * voltage value is increased as a precaution. 80 | */ 81 | operating-points = < 82 | /* kHz uV */ 83 | 1000000 1350000 84 | 800000 1300000 85 | 600000 1112000 86 | 300000 969000 87 | >; 88 | }; 89 | 90 | &gpmc { 91 | status = "okay"; 92 | pinctrl-names = "default"; 93 | pinctrl-0 = <&nandflash_pins_s0>; 94 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 95 | nand: nand@0,0 { 96 | gpmc,device-nand; 97 | reg = <0 0 0>; /* CS0, offset 0 */ 98 | nand-bus-width = <8>; 99 | gpmc,device-width = <1>; 100 | /**/ 101 | gpmc,sync-clk-ps = <0>; 102 | gpmc,cs-on-ns = <0>; 103 | gpmc,cs-rd-off-ns = <280>; 104 | gpmc,cs-wr-off-ns = <280>; 105 | gpmc,adv-on-ns = <50>; 106 | gpmc,adv-rd-off-ns = <280>; 107 | gpmc,adv-wr-off-ns = <280>; 108 | gpmc,we-on-ns = <50>; 109 | gpmc,we-off-ns = <200>; 110 | gpmc,oe-on-ns = <50>; 111 | gpmc,oe-off-ns = <150>; 112 | gpmc,access-ns = <200>; 113 | gpmc,rd-cycle-ns = <300>; 114 | gpmc,wr-cycle-ns = <300>; 115 | gpmc,wait-on-read = "true"; 116 | gpmc,wait-on-write = "true"; 117 | gpmc,bus-turnaround-ns = <0>; 118 | gpmc,cycle2cycle-delay-ns = <120>; 119 | gpmc,cycle2cycle-samecsen = "true"; 120 | gpmc,clk-activation-ns = <0>; 121 | gpmc,wait-monitoring-ns = <0>; 122 | gpmc,wr-access-ns = <40>; 123 | gpmc,wr-data-mux-bus-ns = <0>; 124 | 125 | /* 126 | gpmc,sync-clk-ps = <0>; 127 | gpmc,cs-on-ns = <0>; 128 | gpmc,cs-rd-off-ns = <44>; 129 | gpmc,cs-wr-off-ns = <44>; 130 | gpmc,adv-on-ns = <10>; 131 | gpmc,adv-rd-off-ns = <44>; 132 | gpmc,adv-wr-off-ns = <44>; 133 | gpmc,we-on-ns = <5>; 134 | gpmc,we-off-ns = <30>; 135 | gpmc,oe-on-ns = <5>; 136 | gpmc,oe-off-ns = <25>; 137 | gpmc,access-ns = <30>; 138 | gpmc,rd-cycle-ns = <50>; 139 | gpmc,wr-cycle-ns = <50>; 140 | gpmc,wait-on-read = "true"; 141 | gpmc,wait-on-write = "true"; 142 | gpmc,bus-turnaround-ns = <0>; 143 | gpmc,cycle2cycle-delay-ns = <20>; 144 | gpmc,cycle2cycle-samecsen = "true"; 145 | gpmc,clk-activation-ns = <0>; 146 | gpmc,wait-monitoring-ns = <0>; 147 | gpmc,wr-access-ns = <40>; 148 | gpmc,wr-data-mux-bus-ns = <0>; 149 | */ 150 | /* 151 | gpmc,sync-clk-ps = <0>; 152 | gpmc,cs-on-ns = <0>; 153 | gpmc,cs-rd-off-ns = <88>; 154 | gpmc,cs-wr-off-ns = <88>; 155 | gpmc,adv-on-ns = <10>; 156 | gpmc,adv-rd-off-ns = <88>; 157 | gpmc,adv-wr-off-ns = <88>; 158 | gpmc,we-on-ns = <10>; 159 | gpmc,we-off-ns = <60>; 160 | gpmc,oe-on-ns = <10>; 161 | gpmc,oe-off-ns = <50>; 162 | gpmc,access-ns = <60>; 163 | gpmc,rd-cycle-ns = <100>; 164 | gpmc,wr-cycle-ns = <100>; 165 | gpmc,wait-on-read = "true"; 166 | gpmc,wait-on-write = "true"; 167 | gpmc,bus-turnaround-ns = <0>; 168 | gpmc,cycle2cycle-delay-ns = <40>; 169 | gpmc,cycle2cycle-samecsen = "true"; 170 | gpmc,clk-activation-ns = <0>; 171 | gpmc,wait-monitoring-ns = <0>; 172 | gpmc,wr-access-ns = <40>; 173 | gpmc,wr-data-mux-bus-ns = <0>; 174 | */ 175 | ti,nand-ecc-opt= "bch8"; 176 | //ti,elm-id = <&elm>; 177 | #address-cells = <1>; 178 | #size-cells = <1>; 179 | 180 | partition@0 { 181 | label = "spl"; 182 | reg = <0x0 0x20000>; 183 | }; 184 | 185 | partition@1 { 186 | label = "spl_backup1"; 187 | reg = <0x20000 0x20000>; 188 | }; 189 | 190 | partition@2 { 191 | label = "spl_backup2"; 192 | reg = <0x40000 0x20000>; 193 | }; 194 | 195 | partition@3 { 196 | label = "spl_backup3"; 197 | reg = <0x60000 0x20000>; 198 | }; 199 | 200 | partition@4 { 201 | label = "u-boot"; 202 | reg = <0x80000 0x1c0000>; 203 | }; 204 | 205 | partition@5 { 206 | label = "bootenv"; 207 | reg = <0x240000 0x20000>; 208 | }; 209 | 210 | partition@6 { 211 | label = "fdt"; 212 | reg = <0x260000 0x20000>; 213 | }; 214 | 215 | partition@7 { 216 | label = "kernel"; 217 | reg = <0x280000 0x500000>; 218 | }; 219 | 220 | partition@8 { 221 | label = "root"; 222 | reg = <0x800000 0x1400000>; 223 | }; 224 | 225 | partition@9 { 226 | label = "config"; 227 | reg = <0x1c00000 0x1400000>; 228 | }; 229 | }; 230 | }; 231 | -------------------------------------------------------------------------------- /firmware/spitop_noncerev_ants5.fw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hashrabbit/bitmain-spi/ef008a051dda5aa7dcb4c1aa4856d33b79258765/firmware/spitop_noncerev_ants5.fw -------------------------------------------------------------------------------- /firmware/spitop_noncerev_ants7.fw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hashrabbit/bitmain-spi/ef008a051dda5aa7dcb4c1aa4856d33b79258765/firmware/spitop_noncerev_ants7.fw -------------------------------------------------------------------------------- /fpga.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | 9 | #include 10 | #include 11 | 12 | #include "bitmain-asic.h" 13 | #include "sha2.h" 14 | #include "spi.h" 15 | #include "fpga.h" 16 | #include "set_pll.h" 17 | 18 | volatile struct ASIC_RESULT asic_result[512]; 19 | uint16_t asic_result_wr = 0, asic_result_rd = 0, asic_result_full = 0; 20 | bool is_started = false; 21 | uint32_t asic_result_status[512]; 22 | uint16_t asic_result_status_wr = 0, asic_result_status_rd = 0, asic_result_status_full = 0; 23 | 24 | static uint8_t g_rx_data[sizeof(FPGA_RETURN)]; 25 | uint16_t g_FPGA_FIFO_SPACE = 100; 26 | uint16_t g_TOTAL_FPGA_FIFO; 27 | uint16_t g_FPGA_RESERVE_FIFO_SPACE = 1; 28 | unsigned long open_core_time = 0; 29 | 30 | void rev(unsigned char *s, size_t l) 31 | { 32 | size_t i, j; 33 | unsigned char t; 34 | 35 | for (i = 0, j = l - 1; i < j; i++, j--) { 36 | t = s[i]; 37 | s[i] = s[j]; 38 | s[j] = t; 39 | } 40 | } 41 | unsigned char CRC5(unsigned char *ptr, unsigned char len) 42 | { 43 | unsigned char i, j, k; 44 | unsigned char crc = 0x1f; 45 | 46 | unsigned char crcin[5] = {1, 1, 1, 1, 1}; 47 | unsigned char crcout[5] = {1, 1, 1, 1, 1}; 48 | unsigned char din = 0; 49 | 50 | j = 0x80; 51 | k = 0; 52 | for (i = 0; i < len; i++) 53 | { 54 | if (*ptr & j) { 55 | din = 1; 56 | } else { 57 | din = 0; 58 | } 59 | crcout[0] = crcin[4] ^ din; 60 | crcout[1] = crcin[0]; 61 | crcout[2] = crcin[1] ^ crcin[4] ^ din; 62 | crcout[3] = crcin[2]; 63 | crcout[4] = crcin[3]; 64 | 65 | j = j >> 1; 66 | k++; 67 | if (k == 8) 68 | { 69 | j = 0x80; 70 | k = 0; 71 | ptr++; 72 | } 73 | memcpy(crcin, crcout, 5); 74 | } 75 | crc = 0; 76 | if(crcin[4]) { 77 | crc |= 0x10; 78 | } 79 | if(crcin[3]) { 80 | crc |= 0x08; 81 | } 82 | if(crcin[2]) { 83 | crc |= 0x04; 84 | } 85 | if(crcin[1]) { 86 | crc |= 0x02; 87 | } 88 | if(crcin[0]) { 89 | crc |= 0x01; 90 | } 91 | return crc; 92 | } 93 | 94 | extern int bitmain_asic_get_status(char* buf, char chain, char mode, char chip_addr, char reg_addr) 95 | { 96 | unsigned char cmd_buf[4]; 97 | if (buf == NULL) 98 | buf = cmd_buf; 99 | memset(buf, 0, 4); 100 | buf[0] = 4; 101 | buf[1] = chip_addr; 102 | buf[2] = reg_addr; 103 | if (mode)//all 104 | buf[0] |= 0x80; 105 | buf[3] = CRC5(buf, 4*8 - 5); 106 | printk_ratelimited(KERN_ERR "get chain%d reg%#x\n", chain, reg_addr); 107 | send_BC_to_fpga(chain, buf); 108 | return 4; 109 | } 110 | 111 | int bitmain_asic_inactive(char* buf, char chain) 112 | { 113 | unsigned char cmd_buf[4]; 114 | if (buf == NULL) 115 | buf = cmd_buf; 116 | memset(buf, 0, 4); 117 | buf[0] = 5; 118 | buf[0] |= 0x80; 119 | buf[3] = CRC5(buf, 4*8 - 5); 120 | printk_ratelimited(KERN_ERR "chain%d inactive\n", chain); 121 | send_BC_to_fpga(chain, buf); 122 | return 4; 123 | } 124 | 125 | int bitmain_asic_set_addr(char* buf, char chain, char mode, char chip_addr) 126 | { 127 | unsigned char cmd_buf[4]; 128 | if (buf == NULL) 129 | buf = cmd_buf; 130 | memset(buf, 0, 4); 131 | buf[0] = 1; 132 | buf[1] = chip_addr; 133 | if (mode)//all 134 | buf[0] |= 0x80; 135 | buf[3] = CRC5(buf, 4*8 - 5); 136 | send_BC_to_fpga(chain, buf); 137 | return 4; 138 | } 139 | 140 | void bitmain_set_voltage(BT_AS_INFO dev, unsigned short voltage) 141 | { 142 | unsigned char cmd_buf[4]; 143 | char* buf = NULL; 144 | unsigned char i; 145 | wait_queue_head_t timeout_wq; 146 | init_waitqueue_head(&timeout_wq); 147 | if (buf == NULL) 148 | buf = cmd_buf; 149 | memset(buf, 0, 4); 150 | buf[0] = 0xaa; 151 | buf[1] = (unsigned char )((voltage>>8) & 0xff); 152 | buf[1] &=0x0f; 153 | buf[1] |=0xb0; 154 | buf[2]= (unsigned char )(voltage & 0xff); 155 | buf[3] = CRC5(buf, 4*8 - 5); 156 | buf[3] |=0xc0; 157 | printk_ratelimited(KERN_ERR "set_voltage cmd_buf[0]{%#x}cmd_buf[1]{%#x}cmd_buf[2]{%#x}cmd_buf[3]{%#x}\n", 158 | cmd_buf[0], cmd_buf[1], cmd_buf[2], cmd_buf[3]); 159 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 160 | { 161 | if((dev->chain_exist) & (0x01 << i)) 162 | send_BC_to_fpga(i, cmd_buf); 163 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 164 | } 165 | } 166 | 167 | int bitmain_asic_set_frequency(char* buf, char mode, char chip_addr , char reg_addr, char reg_value) 168 | { 169 | memset(buf, 0, 4); 170 | buf[0] = 2; 171 | buf[1] = chip_addr; 172 | buf[3] = CRC5(buf, 4); 173 | if(mode)//all 174 | buf[0] |= 0x80; 175 | return 4; 176 | } 177 | 178 | /*************************************************************** 179 | freq = 25M / (NR+1) *(M+1) / 2^OD reg default 0xc01e0002 193MHz 180 | ****************************************************************/ 181 | 182 | #ifdef S5_S_VL 183 | void set_frequency(BT_AS_INFO dev, unsigned int freq) 184 | { 185 | unsigned char cmd_buf[4] = {0}; 186 | unsigned char gateblk[4] = {0}; 187 | struct ASIC_TASK asic_work; 188 | unsigned char chain_num = 0; 189 | unsigned char chain_id; 190 | unsigned int i,j,k; 191 | unsigned int cnt; 192 | unsigned char chip_addr = 0; 193 | unsigned char chip_interval = 2; 194 | unsigned char bauddiv = 0; 195 | unsigned char save_timeout = 0; 196 | unsigned char have_clear_fifo = false; 197 | bool send_new_block = false; 198 | wait_queue_head_t timeout_wq; 199 | init_waitqueue_head(&timeout_wq); 200 | //bitmain_asic_set_frequency(cmd_buf, 1, freq); 201 | bauddiv = 26; 202 | gateblk[0] = 6; 203 | gateblk[1] = 00;//0x10; //16-23 204 | //gateblk[2] = 26 | 0x80; //8-15 gateblk=1 205 | gateblk[2] = bauddiv | 0x80; //8-15 gateblk=1 206 | gateblk[0] |= 0x80; 207 | gateblk[3] = CRC5(gateblk, 4*8 - 5); 208 | memset(asic_work.midstate, 0x00, sizeof(asic_work.midstate)); 209 | memset(asic_work.data, 0x00, sizeof(asic_work.data)); 210 | dev->timeout_valid = true; 211 | save_timeout = dev->asic_configure.timeout_data; 212 | dev->asic_configure.timeout_data = 7; 213 | nonce_query(dev); 214 | dev->timeout_valid = false; 215 | dev->asic_configure.timeout_data = save_timeout; 216 | iowrite32(0x01<<22, gpio0_vaddr + GPIO_SETDATAOUT); //set test 217 | udelay(100); // test transfer delay 218 | #ifndef BM1385 219 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 220 | { 221 | if((dev->chain_exist) & (0x01 << i)) 222 | { 223 | printk_ratelimited(KERN_ERR "close chain%d core\n", i); 224 | cmd_buf[0] = 2; 225 | cmd_buf[1] = (freq)&0xff; //16-23 226 | cmd_buf[2] = (freq >> 8)&0xff; //8-15 227 | cmd_buf[0] |= 0x80; 228 | cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5); 229 | printk_ratelimited(KERN_ERR "set_frequency cmd_buf[0]{%#x}cmd_buf[1]{%#x}cmd_buf[2]{%#x}cmd_buf[3]{%#x}\n", 230 | cmd_buf[0], cmd_buf[1], cmd_buf[2], cmd_buf[3]); 231 | send_BC_to_fpga(i, cmd_buf); 232 | interruptible_sleep_on_timeout(&timeout_wq, 2 * HZ/1000);//2ms 233 | chip_addr = 0; 234 | bitmain_asic_inactive(cmd_buf, i); 235 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 236 | if(gChain_Asic_Interval[i] !=0 ) 237 | chip_interval = gChain_Asic_Interval[i]; 238 | for(j = 0; j < 0x100/chip_interval; j++) 239 | { 240 | bitmain_asic_set_addr(cmd_buf, i, 0, chip_addr); 241 | chip_addr += chip_interval; 242 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 243 | } 244 | 245 | #ifdef CTL_ASIC_CORE 246 | for(j = 0; j < 1; j++) 247 | { 248 | send_BC_to_fpga(i, gateblk); 249 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//2ms 250 | chain_id = 0xc0 | i; 251 | for(k = 0; k < BMSC_CORE/* j < 10000000*/; k++) 252 | { 253 | if(k <= j) 254 | asic_work.data[0] = 0; 255 | else 256 | asic_work.data[0] = 0; 257 | if(g_FPGA_FIFO_SPACE <= g_FPGA_RESERVE_FIFO_SPACE) 258 | { 259 | cnt = 0; 260 | do 261 | { 262 | interruptible_sleep_on_timeout(&timeout_wq, 50 * HZ/1000);// 50 = ms 263 | nonce_query(dev); 264 | if( cnt++ > 100) //100 * 50ms = 5s; 265 | { 266 | printk_ratelimited(KERN_ERR "close croe timeout1 g_FPGA_FIFO_SPACE{%d}\n", g_FPGA_FIFO_SPACE); 267 | return; 268 | break; 269 | } 270 | }while(g_FPGA_FIFO_SPACE < (g_FPGA_RESERVE_FIFO_SPACE + BMSC_CORE)); 271 | } 272 | if((k == 0) && (j == 0) && (have_clear_fifo == false)) 273 | { 274 | send_work_to_fpga(true, chain_id, dev, &asic_work); 275 | nonce_query(dev); 276 | have_clear_fifo == true; 277 | } 278 | else 279 | send_work_to_fpga(false, chain_id, dev, &asic_work); 280 | g_FPGA_FIFO_SPACE--; 281 | //if(j == 1) 282 | // break; 283 | } 284 | //interruptible_sleep_on_timeout(&timeout_wq, 1 * 1000 * HZ/1000);// 1 *1000 = 1s 285 | //wait all send to asic 286 | cnt = 0; 287 | do 288 | { 289 | interruptible_sleep_on_timeout(&timeout_wq, 50 * HZ/1000);// 50 = ms 290 | nonce_query(dev); 291 | if( cnt++ > 100) //100 * 200ms = 20s; 292 | { 293 | printk_ratelimited(KERN_ERR "close core timeout2 g_FPGA_FIFO_SPACE{%d}\n", g_FPGA_FIFO_SPACE); 294 | break; 295 | } 296 | }while(g_FPGA_FIFO_SPACE < (g_TOTAL_FPGA_FIFO * 4/48 - 1)); 297 | #ifdef S4_PLUS 298 | send_work_to_fpga(false, 0xc0 | i, dev, &asic_work); 299 | #else 300 | send_work_to_fpga(false, 0x80 | i, dev, &asic_work); 301 | #endif 302 | } 303 | #endif 304 | chain_num++; 305 | } 306 | } 307 | #else 308 | // BM1385 set_frequency 309 | #if 1 310 | uint32_t reg_data_pll = 0; 311 | uint16_t reg_data_pll2 = 0; 312 | printk_ratelimited("set freq = %d\n", freq); 313 | get_plldata(1385,freq,®_data_pll,®_data_pll2); 314 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 315 | { 316 | if((dev->chain_exist) & (0x01 << i)) 317 | { 318 | #if 1 319 | //set plldivider1 320 | //memcpy((char *)cmd_buf,®_data_pll,sizeof(reg_data_pll)); 321 | cmd_buf[0] = 0; 322 | cmd_buf[0] |= 0x7;//cmd 323 | cmd_buf[1] = (reg_data_pll >> 16) & 0xff; 324 | cmd_buf[2] = (reg_data_pll >> 8) & 0xff; 325 | cmd_buf[3] = (reg_data_pll >> 0) & 0xff; 326 | cmd_buf[3] |= CRC5(cmd_buf, 4*8 - 5); 327 | 328 | printk_ratelimited(KERN_ERR "plldivider1 cmd_buf[0]{%#x}cmd_buf[1]{%#x}cmd_buf[2]{%#x}cmd_buf[3]{%#x}\n", 329 | cmd_buf[0], cmd_buf[1], cmd_buf[2], cmd_buf[3]); 330 | send_BC_to_fpga(i, cmd_buf); 331 | 332 | interruptible_sleep_on_timeout(&timeout_wq, 2 * HZ/1000);//2ms 333 | //set plldivider2 334 | memset(cmd_buf,0,sizeof(cmd_buf)); 335 | cmd_buf[0] = 0x2; //cmd 336 | cmd_buf[0] |= 0x80; //all 337 | cmd_buf[1] = 0; //addr 338 | cmd_buf[2] = reg_data_pll2 >> 8; 339 | cmd_buf[3] = reg_data_pll2& 0x0ff; 340 | //memcpy((char *)cmd_buf + 2,®_data_pll2,sizeof(reg_data_pll2)); //postdiv data 341 | cmd_buf[3] |= CRC5(cmd_buf, 4*8 - 5); 342 | 343 | printk_ratelimited(KERN_ERR "plldivider2 cmd_buf[0]{%#x}cmd_buf[1]{%#x}cmd_buf[2]{%#x}cmd_buf[3]{%#x}\n", 344 | cmd_buf[0], cmd_buf[1], cmd_buf[2], cmd_buf[3]); 345 | send_BC_to_fpga(i, cmd_buf); 346 | 347 | interruptible_sleep_on_timeout(&timeout_wq, 2 * HZ/1000);//2ms 348 | #endif 349 | #if 1 350 | chip_addr = 0; 351 | bitmain_asic_inactive(cmd_buf, i); 352 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 353 | if(gChain_Asic_Interval[i] !=0 ) 354 | chip_interval = gChain_Asic_Interval[i]; 355 | chip_interval = 4; 356 | for(j = 0; j < 0x100/chip_interval; j++) 357 | { 358 | bitmain_asic_set_addr(cmd_buf, i, 0, chip_addr); 359 | chip_addr += chip_interval; 360 | interruptible_sleep_on_timeout(&timeout_wq, 10 * HZ/1000);//5ms 361 | } 362 | #endif 363 | chain_num++; 364 | } 365 | } 366 | #endif 367 | #endif 368 | iowrite32(0x01<<22, gpio0_vaddr + GPIO_CLEARDATAOUT); //clear test 369 | //interruptible_sleep_on_timeout(&timeout_wq, 20* 1000 * HZ/1000); 370 | #if 1 371 | //modify baud 372 | bauddiv = get_baud(freq);; 373 | cmd_buf[0] = 6; 374 | cmd_buf[1] = 0x10; //16-23 375 | cmd_buf[2] = bauddiv & 0x1f; //8-13 376 | cmd_buf[0] |= 0x80; 377 | cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5); 378 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 379 | { 380 | if((dev->chain_exist) & (0x01 << i)) 381 | { 382 | send_BC_to_fpga(i, cmd_buf); 383 | interruptible_sleep_on_timeout(&timeout_wq, 2 * HZ/1000);//2ms 384 | } 385 | } 386 | dev->asic_configure.bauddiv = bauddiv; 387 | cmd_buf[3] = CRC5(gateblk, 4*8 - 5); //故意错误crc 只是修改fpga 波特率 388 | send_BC_to_fpga(i, cmd_buf); 389 | //interruptible_sleep_on_timeout(&timeout_wq, 2 * HZ/1000);//2ms 390 | #endif 391 | //interruptible_sleep_on_timeout(&timeout_wq, 50 * HZ/1000);//2ms 392 | //bitmain_asic_get_status(NULL,dev->chain_map[0], 1, 0, 0x00); //CHIP_ADDR_REG 4 PLL reg 393 | // 从新计算getblck命令 394 | gateblk[0] = 6; 395 | gateblk[1] = 00;//0x10; //16-23 396 | gateblk[2] = bauddiv | 0x80; //8-15 gateblk=1 397 | gateblk[0] |= 0x80; 398 | gateblk[3] = 0x00; 399 | gateblk[3] = CRC5(gateblk, 4*8 - 5); 400 | 401 | printk_ratelimited(KERN_ERR "bauddiv %d ",bauddiv); 402 | printk_ratelimited(KERN_ERR "gateblk2 %x\n",gateblk[2]); 403 | 404 | /**/ 405 | #if 1 406 | #ifdef CTL_ASIC_CORE 407 | save_timeout = dev->asic_configure.timeout_data; 408 | dev->asic_configure.timeout_data *=32; 409 | dev->asic_configure.timeout_data = 130; 410 | dev->timeout_valid = true; 411 | nonce_query(dev); 412 | dev->timeout_valid = false; 413 | dev->wait_timeout = false; 414 | //\BF\AAcore 415 | memset(asic_work.midstate, 0xff, sizeof(asic_work.midstate)); 416 | memset(asic_work.data, 0xff, sizeof(asic_work.data)); 417 | printk_ratelimited(KERN_ERR "open core\n"); 418 | for(j = 0; j < /*55*/1; j++) 419 | { 420 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 421 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 422 | { 423 | if((dev->chain_exist) & (0x01 << i)) 424 | { 425 | send_BC_to_fpga(i, gateblk); 426 | interruptible_sleep_on_timeout(&timeout_wq, 10 * HZ/1000);//2ms 427 | } 428 | } 429 | for(k = 0; k < 64; k++) 430 | { 431 | if(k <= j) 432 | { 433 | asic_work.data[0] = 0xff; 434 | asic_work.data[11] = 0xff; 435 | } 436 | else 437 | { 438 | asic_work.data[0] = 0xff; 439 | asic_work.data[11] = 0xff; 440 | } 441 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 442 | { 443 | if((dev->chain_exist) & (0x01 << i)) 444 | { 445 | chain_id = 0x80 | i; 446 | if(g_FPGA_FIFO_SPACE <= g_FPGA_RESERVE_FIFO_SPACE) 447 | { 448 | cnt = 0; 449 | do 450 | { 451 | interruptible_sleep_on_timeout(&timeout_wq, 50 * HZ/1000);// 50 = ms 452 | nonce_query(dev); 453 | if( cnt++ > 100) //100 * 50ms = 5s; 454 | { 455 | printk_ratelimited(KERN_ERR "open core timeout1 g_FPGA_FIFO_SPACE{%d}\n", g_FPGA_FIFO_SPACE); 456 | //return; 457 | break; 458 | } 459 | }while(g_FPGA_FIFO_SPACE < (g_FPGA_RESERVE_FIFO_SPACE /*+ 63 - k *//*+ BMSC_CORE*/)); 460 | } 461 | if(k == 63) 462 | chain_id = 0xc0 | i; 463 | if((k == 0) && (send_new_block == false)) 464 | { 465 | send_new_block = true; 466 | send_work_to_fpga(true, chain_id, dev, &asic_work); 467 | } 468 | else 469 | send_work_to_fpga(false, chain_id, dev, &asic_work); 470 | g_FPGA_FIFO_SPACE--; 471 | } 472 | } 473 | //printk_ratelimited("k = %d\n", k); 474 | } 475 | //printk_ratelimited("j = %d\n", j); 476 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 477 | //interruptible_sleep_on_timeout(&timeout_wq, 1 * 1000 * HZ/1000);// 2 *1000 = 1s 478 | //wait all send to asic 479 | /* 480 | cnt = 0; 481 | do 482 | { 483 | interruptible_sleep_on_timeout(&timeout_wq, 50 * HZ/1000);// 50 = ms 484 | nonce_query(dev); 485 | if( cnt++ > 100) //100 * 200ms = 20s; 486 | { 487 | printk_ratelimited(KERN_ERR "open core timeout2 g_FPGA_FIFO_SPACE{%d}\n", g_FPGA_FIFO_SPACE); 488 | return; 489 | break; 490 | } 491 | }while(g_FPGA_FIFO_SPACE < (g_TOTAL_FPGA_FIFO * 4/48 - 1)); 492 | */ 493 | //if(!((k==55) && (j==54))) 494 | // send_work_to_fpga(false, 0x80 | i, dev, &asic_work); 495 | } 496 | open_core_time = jiffies; 497 | /* 498 | for(i = 0; i < sizeof(asic_work.midstate); i++) 499 | { 500 | asic_work.midstate[i] = i%4; 501 | } 502 | for(i = 0; i < sizeof(asic_work.data); i++) 503 | { 504 | asic_work.data[i] = i%4; 505 | } 506 | 507 | 508 | for(k = 0; k < 15000; k++) 509 | { 510 | if(g_FPGA_FIFO_SPACE <= g_FPGA_RESERVE_FIFO_SPACE) 511 | { 512 | cnt = 0; 513 | do 514 | { 515 | interruptible_sleep_on_timeout(&timeout_wq, 50 * HZ/1000);// 50 = ms 516 | nonce_query(dev); 517 | if( cnt++ > 100) //100 * 50ms = 5s; 518 | { 519 | printk_ratelimited(KERN_ERR "open core timeout1 g_FPGA_FIFO_SPACE{%d}\n", g_FPGA_FIFO_SPACE); 520 | return; 521 | break; 522 | } 523 | }while(g_FPGA_FIFO_SPACE < (g_FPGA_RESERVE_FIFO_SPACE + 55)); 524 | } 525 | send_work_to_fpga(false, chain_id, dev, &asic_work); 526 | g_FPGA_FIFO_SPACE--; 527 | printk_ratelimited("k = %d\n", k); 528 | } 529 | */ 530 | 531 | dev->wait_timeout = true; 532 | dev->asic_configure.timeout_data = save_timeout; 533 | //printk_ratelimited(KERN_ERR "FPGA start null work\n"); 534 | //interruptible_sleep_on_timeout(&timeout_wq, 40 * 1000 * HZ/1000); 535 | #endif 536 | #endif 537 | } 538 | #else 539 | void set_frequency(BT_AS_INFO dev, unsigned int freq) 540 | { 541 | unsigned char cmd_buf[4] = {0}; 542 | unsigned char i; 543 | wait_queue_head_t timeout_wq; 544 | init_waitqueue_head(&timeout_wq); 545 | //bitmain_asic_set_frequency(cmd_buf, 1, freq); 546 | cmd_buf[0] = 2; 547 | cmd_buf[1] = (freq)&0xff; //16-23 548 | cmd_buf[2] = (freq >> 8)&0xff; //8-15 549 | cmd_buf[0] |= 0x80; 550 | cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5); 551 | printk_ratelimited(KERN_ERR "set_frequency cmd_buf[0]{%#x}cmd_buf[1]{%#x}cmd_buf[2]{%#x}cmd_buf[3]{%#x}\n", 552 | cmd_buf[0], cmd_buf[1], cmd_buf[2], cmd_buf[3]); 553 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 554 | { 555 | if((dev->chain_exist) & (0x01 << i)) 556 | send_BC_to_fpga(i, cmd_buf); 557 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 558 | } 559 | } 560 | #endif 561 | void set_baud(BT_AS_INFO dev, unsigned char bauddiv) 562 | { 563 | unsigned char cmd_buf[4] = {0}; 564 | unsigned char i; 565 | wait_queue_head_t timeout_wq; 566 | init_waitqueue_head(&timeout_wq); 567 | if(dev->asic_configure.bauddiv == bauddiv) 568 | { 569 | printk_ratelimited(KERN_ERR "baud same don't to change\n"); 570 | return; 571 | } 572 | //bitmain_asic_set_frequency(cmd_buf, 1, freq); 573 | cmd_buf[0] = 6; 574 | cmd_buf[1] = 0x10; //16-23 575 | cmd_buf[2] = bauddiv & 0x1f; //8-13 576 | cmd_buf[0] |= 0x80; 577 | cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5); 578 | printk_ratelimited(KERN_ERR "set_baud cmd_buf[0]{%#x}cmd_buf[1]{%#x}cmd_buf[2]{%#x}cmd_buf[3]{%#x}\n", 579 | cmd_buf[0], cmd_buf[1], cmd_buf[2], cmd_buf[3]); 580 | for(i = 0; (i < sizeof(dev->chain_exist) * 8); i++) 581 | { 582 | if((dev->chain_exist) & (0x01 << i)) 583 | send_BC_to_fpga(i, cmd_buf); 584 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 585 | } 586 | dev->asic_configure.bauddiv = bauddiv; 587 | } 588 | 589 | unsigned char get_baud(uint16_t frequency) 590 | { 591 | uint32_t toctl; 592 | unsigned char i; 593 | toctl = 1000000; 594 | toctl /= (0xffffffff/64/64/frequency); 595 | for (i=0;i<32;i++) 596 | { 597 | if(toctl < (25000000/((i+1)*8)/1000) && toctl > (25000000/((i+2)*8)/1000) ) 598 | return i; 599 | } 600 | return 4; 601 | } 602 | 603 | void bitmain_sw_addr(BT_AS_INFO dev) 604 | { 605 | unsigned char cmd_buf[4] = {0}; 606 | unsigned char i, j; 607 | wait_queue_head_t timeout_wq; 608 | init_waitqueue_head(&timeout_wq); 609 | unsigned char chip_addr = 0; 610 | unsigned char chip_interval = 2; 611 | unsigned char chain_nu; 612 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 613 | { 614 | chip_addr = 0; 615 | chain_nu = dev->chain_map[i]; 616 | printk_ratelimited(KERN_ERR "sw addr start\n"); 617 | bitmain_asic_inactive(cmd_buf, chain_nu); 618 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 619 | if(gChain_Asic_Interval[chain_nu] !=0 ) 620 | chip_interval = gChain_Asic_Interval[chain_nu]; 621 | for(j = 0; j < 0x100/chip_interval; j++) 622 | { 623 | bitmain_asic_set_addr(cmd_buf, chain_nu, 0, chip_addr); 624 | chip_addr += chip_interval; 625 | interruptible_sleep_on_timeout(&timeout_wq, 5 * HZ/1000);//5ms 626 | } 627 | } 628 | } 629 | 630 | extern void rst_hash_asic(BT_AS_INFO dev) 631 | { 632 | uint16_t rx_size; 633 | FPGA_QUERY fpga_query; 634 | fpga_query.cmd_type = QEURY_FPGA; 635 | fpga_query.reserved1[0] = 0x55; 636 | fpga_query.reserved1[1] = 0xaa; 637 | #if defined S5 || defined S2 || defined S4_PLUS 638 | fpga_query.rst_time = 50; 639 | fpga_query.rst_valid = 1; 640 | printk_ratelimited(KERN_ERR "soft ctrl rst time\n"); 641 | #else 642 | fpga_query.rst_time = 0x55; 643 | #endif 644 | 645 | //fpga_query.pwm_h = htons(12500); //25M=40ns 1Khz = 10^6ns 25000 646 | //fpga_query.pwm_l = htons(12500); 647 | fpga_query.pwm_h = htons(0x0b3f); //25M=40ns 1Khz = 10^6ns 25000 648 | fpga_query.pwm_l = htons(0x0fff); 649 | rx_size = sizeof(g_rx_data); 650 | spi_tranfer(0x01, (uint8_t*)&fpga_query, sizeof(fpga_query), g_rx_data, &rx_size); 651 | /* 652 | printk_ratelimited("query send data:"); 653 | dump_hex((uint8_t*)&fpga_query,sizeof(fpga_query)); 654 | */ 655 | //printk_ratelimited(KERN_ERR "query\n"); 656 | printk_ratelimited(KERN_ERR "reset hash asic\n"); 657 | return; 658 | 659 | } 660 | 661 | #define TEST_ASIC 0 662 | int parse_return_nonce(BT_AS_INFO dev, uint8_t *rx_data, uint16_t rx_len) 663 | { 664 | uint16_t i, j; 665 | int ret = 0; 666 | int nonce_num = 0; 667 | unsigned int fifa_have_work_num = 0; 668 | uint32_t task_buffer_match_adj = 0; 669 | FPGA_RETURN *fpga_ret_q = (FPGA_RETURN*)rx_data; 670 | FPGA_RET_NONCE *fpga_ret_nonce_q = (FPGA_RET_NONCE *)&rx_data[12]; 671 | static FPGA_RET_NONCE last_nonce_full, llast_nonce_full; 672 | static uint32_t last_nonce = 0, llast_nonce = 0; 673 | static uint32_t last_nonce1_num = 0; 674 | 675 | static uint32_t chain_hw[16]={0}; 676 | uint16_t chain_loop = 0; 677 | /* 678 | printk_ratelimited("return nonce data\n"); 679 | dump_hex(rx_data, rx_len); 680 | */ 681 | if(rx_data[0] != 0x55)//\CE\DE\C1\AC\BD\D3 682 | { 683 | printk_ratelimited(KERN_ERR "FPGA return data error\n"); 684 | return -1; 685 | } 686 | dev->fpga_version = fpga_ret_q->fpga_version; 687 | dev->pcb_version = fpga_ret_q->pc_version; 688 | dev->chain_exist = ntohs(fpga_ret_q->chain_exist); 689 | #if 0 690 | dev->fan_exist = fpga_ret_q->fan_exist; 691 | memcpy(dev->fan_speed, fpga_ret_q->fan_speed, sizeof(fpga_ret_q->fan_speed)); 692 | #else 693 | if(fpga_ret_q->fan_index > CHAIN_SIZE) 694 | { 695 | printk_ratelimited(KERN_ERR "fan_index%d err\n", fpga_ret_q->fan_index); 696 | } 697 | else 698 | { 699 | dev->fan_exist |= 0x01<fan_index; 700 | //dev->fan_speed[fpga_ret_q->fan_index] = fpga_ret_q->fan_speed; 701 | //adjust fpga fan_speed err 702 | dev->fan_speed[fpga_ret_q->fan_index] = fpga_ret_q->fan_speed << 1; 703 | } 704 | //dev->fpga_fifo_st = (rx_data[8]<<8) | rx_data[9]; 705 | #endif 706 | //dev->fpga_nonce1_num = ntohl(fpga_ret_q->nonce1_num); 707 | g_FPGA_FIFO_SPACE = (ntohs(fpga_ret_q->fifo_total) - ntohs(fpga_ret_q->have_bytes)) * 4/ 48; 708 | g_TOTAL_FPGA_FIFO = ntohs(fpga_ret_q->fifo_total); 709 | fifa_have_work_num = ntohs(fpga_ret_q->have_bytes)*4/48; 710 | //printk_ratelimited("have_bytes: %d\n", fpga_ret_q->have_bytes); 711 | //printk_ratelimited("chain exist: %x, g_FPGA_FIFO_SPACE %#x\n",dev->chain_exist, g_FPGA_FIFO_SPACE); 712 | //printk_ratelimited("total nonce num = %d, snd_to_fpga_work{%d}\n", ret_nonce_num, snd_to_fpga_work); 713 | 714 | if(fpga_ret_prnt) 715 | { 716 | printk_ratelimited("return_nonce:"); 717 | dump_hex(rx_data,rx_len); 718 | } 719 | 720 | task_buffer_match_adj = dev->save_send_work; 721 | for(i = 0; i < fifa_have_work_num; i++) 722 | decrease_variable_rehead_U32(&task_buffer_match_adj, dev->task_buffer_size); 723 | for(j = 0; j < sizeof(fpga_ret_q->nonce)/sizeof(*fpga_ret_nonce_q); j++) //\B1\A3\B4\E6nonce \CA\FD?? 724 | { 725 | uint8_t data; 726 | uint16_t work_id; 727 | uint32_t task_buffer_match = 0; 728 | uint8_t which_asic_nonce = 0; 729 | uint8_t which_array = fpga_ret_nonce_q->chain_num; 730 | 731 | //\B3\F6\B4\ED\B4\A6\C0\ED 732 | if(which_array > CHAIN_SIZE) 733 | { 734 | printk_ratelimited(KERN_ERR "Chain ret err\n"); 735 | continue; 736 | } 737 | if(fpga_ret_nonce_q->temp_valid) 738 | { 739 | if((fpga_ret_nonce_q->temp <= 0xa0) && (fpga_ret_nonce_q->temp >= 00)) 740 | dev->temp[fpga_ret_nonce_q->chain_num] = fpga_ret_nonce_q->temp; 741 | } 742 | if(fpga_ret_nonce_q->nonce_valid == true) 743 | { 744 | nonce_num++; 745 | if(dev->clear_fpga_fifo) 746 | continue; 747 | work_id = htons(fpga_ret_nonce_q->work_id); 748 | data = (work_id>>8) & 0xff; 749 | if (((work_id & 0x8000) == 0x8000) && (fpga_ret_nonce_q->nonce != last_nonce) && (fpga_ret_nonce_q->nonce != llast_nonce))//nonce && 非相同nonce 750 | { 751 | ret_nonce_num++; 752 | gNonce_num ++; 753 | //nonce_num++; 754 | 755 | if(asic_result_full == 1) 756 | { 757 | printk_ratelimited(KERN_ERR "No sp for ret nonce!!wr{%d}rd{%d}\n",asic_result_wr, asic_result_rd); 758 | break; 759 | } 760 | //printk_ratelimited(KERN_ERR "llast_nonce{%x}last_nonce{%x}\n", llast_nonce, last_nonce); 761 | llast_nonce = last_nonce; 762 | last_nonce = fpga_ret_nonce_q->nonce; 763 | rev((uint8_t*)&fpga_ret_nonce_q->nonce, 4); 764 | //asic_result[asic_result_wr].nonce = fpga_ret_nonce_q->nonce; 765 | task_buffer_match = work_id & 0x7fff; 766 | /* 767 | printk_ratelimited(KERN_ERR "task_buffer_match{%d}work_id{%d}task_buffer_rd{%d}wr{%d}\n", task_buffer_match, dev->task_buffer[task_buffer_match].work_id&0x1f, 768 | dev->task_buffer_rd, dev->task_buffer_wr); 769 | */ 770 | which_asic_nonce = (last_nonce & 0xff) >> (3 + 5 - gChain_Asic_Check_bit[which_array])& 0xff; 771 | if(gChain_Asic_Interval[which_array] !=0 ) 772 | which_asic_nonce = (last_nonce & 0xff)/gChain_Asic_Interval[which_array] ; 773 | //which_asic_nonce = ((last_nonce & 0xff)>> (3)) & 0x1f; 774 | /* 775 | data = last_nonce & 0xff; 776 | if( data >= 0xe4) 777 | printk_ratelimited(KERN_ERR "nonce high byte %#x\n", data); 778 | */ 779 | //printk_ratelimited(KERN_ERR "which_array{%d}which_asic_nonce{%d}nonce[%#x]\n", which_array, which_asic_nonce, last_nonce & 0xff); 780 | gAsic_cnt[which_array][which_asic_nonce]++; 781 | Chain_nonce_nu[which_array]++; 782 | if ((dev->hw_error_eft == false) || /**/((ret = hashtest(&dev->task_buffer[task_buffer_match], fpga_ret_nonce_q->nonce)) != 0)) 783 | { 784 | if((dev->hw_error_eft == false) || ((dev->asic_configure.diff_sh_bit != 0 ) && (ret == 2)) || (dev->asic_configure.diff_sh_bit == 0)) 785 | { 786 | asic_result[asic_result_wr].work_id= dev->task_buffer[task_buffer_match].work_id; 787 | asic_result[asic_result_wr].nonce = fpga_ret_nonce_q->nonce; 788 | increase_variable_rehead_U16(&asic_result_wr, ASIC_RESULT_NUM); 789 | if (asic_result_wr == asic_result_rd) 790 | { 791 | asic_result_full = 1; 792 | } 793 | } 794 | else 795 | { 796 | ;//diff ==1 797 | } 798 | } 799 | else //if(is_started) 800 | { 801 | //if((gNonce_Err++ % 100) == 0) 802 | gNonce_Err++; 803 | printk_ratelimited(KERN_ERR "ch%d-as%d: dev->task_buffer_wr{0x%08x}rd{0x%08x}ret work_id{0x%04x} don't match task_buffer_match{0x%04x} \n", 804 | which_array, which_asic_nonce, dev->task_buffer_wr,dev->task_buffer_rd, work_id, task_buffer_match); 805 | if(which_array-1 < 16) 806 | chain_hw[which_array-1] ++; 807 | } 808 | } 809 | else if ((work_id & 0x8000) == 0x0000)//status 810 | { 811 | uint8_t crc_reslut; 812 | printk_ratelimited(KERN_ERR "asic cmd return %08x\n", fpga_ret_nonce_q->nonce); 813 | crc_reslut = CRC5((uint8_t*)&fpga_ret_nonce_q->nonce, 5 * 8 - 5); 814 | if (crc_reslut == (data & 0x1f)) 815 | { 816 | rev((uint8_t*)&fpga_ret_nonce_q->nonce, 4); 817 | asic_result_status[asic_result_status_wr] = fpga_ret_nonce_q->nonce; 818 | if (dev->asic_configure.reg_address == 4) //PLL parameter 819 | { 820 | printk_ratelimited("Chain%d PLL: {%#x}\n", which_array, asic_result_status[asic_result_status_wr]); 821 | } 822 | if (dev->get_status == true) 823 | { 824 | increase_variable_rehead_U16(&asic_result_status_wr, ASIC_RESULT_STATUS_NUM); 825 | if (asic_result_status_wr == asic_result_status_rd) 826 | asic_result_status_full = 1; 827 | } 828 | } 829 | else 830 | { 831 | uint8_t *pdata; 832 | printk_ratelimited(KERN_ERR "chain%d reg crc_r{%#x}crc{%#x} Err ret{0x%08x}\n", which_array, crc_reslut, data, fpga_ret_nonce_q->nonce); 833 | gNonce_Err++; 834 | #if 1 835 | if(fpga_ret_nonce_q->chain_num == 14) 836 | { 837 | pdata = (uint8_t*)&last_nonce_full; 838 | printk_ratelimited(KERN_ERR "last nonce full\n"); 839 | for(i = 0; i < sizeof(last_nonce_full); i++) 840 | { 841 | printk_ratelimited(KERN_ERR "0x%02x ", pdata[i]); 842 | } 843 | printk_ratelimited(KERN_ERR "\n"); 844 | pdata = (uint8_t*)&llast_nonce_full; 845 | printk_ratelimited(KERN_ERR "llast nonce full\n"); 846 | for(i = 0; i < sizeof(last_nonce_full); i++) 847 | { 848 | printk_ratelimited(KERN_ERR "0x%02x ", pdata[i]); 849 | } 850 | printk_ratelimited(KERN_ERR "\n"); 851 | } 852 | #endif 853 | } 854 | } 855 | #if 1 856 | if(fpga_ret_nonce_q->chain_num == 14) 857 | { 858 | rev((uint8_t*)&fpga_ret_nonce_q->nonce, 4); 859 | memcpy(&llast_nonce_full, &last_nonce_full, sizeof(last_nonce_full)); 860 | memcpy(&last_nonce_full, fpga_ret_nonce_q, sizeof(last_nonce_full)); 861 | } 862 | #endif 863 | } 864 | else 865 | { 866 | for( i = 0; i< sizeof(*fpga_ret_nonce_q); i++) 867 | { 868 | if( *((uint8_t*)fpga_ret_nonce_q + i) != 0) 869 | { 870 | printk_ratelimited(KERN_ERR "Nonce invalid but all not zero\n"); 871 | dump_hex((uint8_t*)fpga_ret_q,sizeof(*fpga_ret_q)); 872 | break; 873 | } 874 | } 875 | } 876 | fpga_ret_nonce_q++; 877 | } 878 | /* 879 | if( nonce_num != (dev->fpga_nonce1_num - last_nonce1_num)) 880 | { 881 | printk_ratelimited("nonce_num{%d}last{%#x}dev->fpga_nonce1_num{%#x}\n", nonce_num, last_nonce1_num, dev->fpga_nonce1_num); 882 | printk_ratelimited("return_nonce:"); 883 | dump_hex(rx_data,rx_len); 884 | } 885 | last_nonce1_num = dev->fpga_nonce1_num; 886 | */ 887 | /* 888 | if((dev->fpga_nonce1_num != 0) && ((dev->fpga_nonce1_num - (uint32_t)(dev->total_nonce_num&0xffffffff)) > 150)) 889 | { 890 | printk_ratelimited(KERN_ERR "fpga-nc{%d}drv-nc{%ld} = {%ld}\n",dev->fpga_nonce1_num, dev->total_nonce_num, dev->fpga_nonce1_num - (uint32_t)(dev->total_nonce_num &0xffffffff)); 891 | } 892 | */ 893 | return nonce_num; 894 | } 895 | extern int nonce_query(BT_AS_INFO dev) 896 | { 897 | uint16_t rx_size; 898 | uint32_t toctl = 0; 899 | static FPGA_QUERY fpga_query; 900 | fpga_query.cmd_type = QEURY_FPGA; 901 | fpga_query.reserved1[0] = 0x55; 902 | fpga_query.reserved1[1] = 0xaa; 903 | 904 | //fpga_query.pwm_h = htons(12500); //25M=40ns 1Khz = 10^6ns 25000 905 | //fpga_query.pwm_l = htons(12500); 906 | //fpga_query.pwm_h = htons(0x0b3f); //25M=40ns 1Khz = 10^6ns 25000 907 | //fpga_query.pwm_l = htons(0x0fff); 908 | fpga_query.pwm_h = htons(dev->pwm_high_value); 909 | fpga_query.pwm_l = htons(dev->pwm_low_value); 910 | if(dev->timeout_valid) 911 | { 912 | //toctl = (dev->asic_configure.timeout_data * 1000000/ 40) - 1; 913 | toctl = (dev->asic_configure.timeout_data*1000*9/10) - 1;//1us 914 | if (dev->asic_configure.frequency > 0) 915 | toctl += (0xffffffff/64/64/dev->asic_configure.frequency % 1000 *9 / 10); 916 | printk_ratelimited(KERN_ERR "timeout {%#x}\n", toctl); 917 | toctl |= (0x01<<31); 918 | fpga_query.toctl = htonl(toctl); 919 | printk_ratelimited(KERN_ERR "rev timeout {%#x}\n", fpga_query.toctl); 920 | /* 921 | uint16_t i; 922 | uint8_t *data = (uint8_t *)&fpga_query; 923 | for(i = 0; i < sizeof(fpga_query); i++) 924 | { 925 | if(0 == (i%16)) 926 | printk_ratelimited(KERN_ERR "\n0x%04x: ", i); 927 | printk_ratelimited(KERN_ERR "0x%02x ", data[i]); 928 | } 929 | printk_ratelimited(KERN_ERR "\n"); 930 | */ 931 | } 932 | else 933 | fpga_query.toctl = 0; 934 | fpga_query.tm = htonl((0x01 << dev->nonce_diff)-1); 935 | //printk_ratelimited(KERN_ERR "fpga_query.tm0x%08x ", fpga_query.tm); 936 | if(gChain_Asic_num[dev->chain_map[0]] != 0) 937 | { 938 | //fpga_query.hcn = htonl(0xffffffff/256 * (256/gChain_Asic_num[dev->chain_map[0]])); 939 | fpga_query.hcn = 0; 940 | } 941 | rx_size = sizeof(g_rx_data); 942 | spi_tranfer(0x01, (uint8_t*)&fpga_query, sizeof(fpga_query), g_rx_data, &rx_size); 943 | /* 944 | printk_ratelimited("query send data:"); 945 | dump_hex((uint8_t*)&fpga_query,sizeof(fpga_query)); 946 | */ 947 | //printk_ratelimited(KERN_ERR "query\n"); 948 | return parse_return_nonce(dev, g_rx_data, rx_size); 949 | } 950 | 951 | extern const char g_midstate[], g_data[]; 952 | extern int send_work_to_fpga(bool new_block, unsigned char chain_id, BT_AS_INFO dev, ASIC_TASK_P asic_work) 953 | { 954 | FPGA_WORK fpga_work; 955 | static uint32_t TO_FPGA_ID = 0; 956 | static bool new_block_flg = false; 957 | uint16_t rx_size; 958 | int ret = -1; 959 | fpga_work.block_type = NOR_BLOCK; 960 | fpga_work.chain_id = chain_id; 961 | if((time_after(jiffies, open_core_time + dev->asic_configure.timeout_data * 32 * 64 * HZ/1000)) 962 | && ( dev->wait_timeout ))//40s 963 | { 964 | //printk_ratelimited("jiffies{%ld}, open{%ld},dev->wait_timeout{%d}\n",jiffies, open_core_time, dev->wait_timeout); 965 | dev->timeout_valid = true; 966 | nonce_query(dev); 967 | dev->timeout_valid = false; 968 | dev->wait_timeout = false; 969 | } 970 | if(new_block) 971 | { 972 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 973 | if(time_after(jiffies, open_core_time + dev->asic_configure.timeout_data * 32 * 64 * HZ/1000))//40s 974 | fpga_work.block_type = NEW_BLOCK; 975 | else 976 | printk_ratelimited("Sending open core work\n"); 977 | printk_ratelimited("Send new block cmd\n"); 978 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 979 | new_block_flg = true; 980 | TO_FPGA_ID = 0; 981 | } 982 | if(new_block_flg) 983 | { 984 | if(TO_FPGA_ID++ > 500) 985 | { 986 | new_block_flg = false; 987 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 988 | } 989 | } 990 | #if TEST_ASIC 991 | hex2bin(asic_work->midstate, g_midstate, sizeof(asic_work->midstate)); 992 | hex2bin(asic_work->data, g_data, sizeof(asic_work->data)); 993 | rev(asic_work->midstate, sizeof(fpga_work.midstate)); 994 | rev(asic_work->data, sizeof(fpga_work.data)); 995 | #endif 996 | memcpy(fpga_work.midstate, asic_work->midstate, sizeof(fpga_work.midstate)); 997 | memcpy(fpga_work.data, asic_work->data, sizeof(fpga_work.data)); 998 | rev(fpga_work.midstate, sizeof(fpga_work.midstate)); 999 | rev(fpga_work.data, sizeof(fpga_work.data)); 1000 | #if TEST_ASIC 1001 | asic_work->work_id = TO_FPGA_ID; 1002 | TO_FPGA_ID +=2; 1003 | #endif 1004 | /* 1005 | printk_ratelimited(KERN_ERR "rd{%d}work_id 0x%08x\n", dev->task_buffer_rd, asic_work->work_id); 1006 | */ 1007 | //printk_ratelimited("asic_work->midstate:"); 1008 | //dump_hex((uint8_t*)asic_work->midstate,sizeof(fpga_work.midstate)); 1009 | 1010 | //fpga_work.work_id = htonl(asic_work->work_id & 0x1f); 1011 | //fpga_work.work_id = htonl(dev->task_buffer_rd & 0x1f); 1012 | fpga_work.work_id = htonl(dev->task_buffer_rd & 0x7fff); 1013 | //fpga_work.work_id = 0x15 | (0x15 << 24); 1014 | rx_size = sizeof(g_rx_data); 1015 | /* 1016 | printk_ratelimited("send data:"); 1017 | dump_hex((uint8_t*)&fpga_work,sizeof(fpga_work)); 1018 | */ 1019 | 1020 | 1021 | //printk_ratelimited("send work\n"); 1022 | if(-1 != spi_tranfer(0x02, (uint8_t*)&fpga_work, sizeof(fpga_work), g_rx_data, &rx_size)) 1023 | ret = parse_return_nonce(dev, g_rx_data, rx_size); 1024 | else 1025 | ret = -1; 1026 | return ret; 1027 | } 1028 | extern int send_BC_to_fpga(uint8_t chain_num, uint8_t *cmd) 1029 | { 1030 | FPGA_ASIC_CMD asic_cmd; 1031 | BT_AS_INFO dev = &bitmain_asic_dev; 1032 | uint16_t rx_size = sizeof(g_rx_data); 1033 | memset(&asic_cmd, 0x00, sizeof(asic_cmd)); 1034 | asic_cmd.cmd_type = ASIC_CMD; 1035 | asic_cmd.chain_num = chain_num; 1036 | asic_cmd.bauddiv = dev->asic_configure.bauddiv; 1037 | memcpy(&asic_cmd.cmd, cmd, sizeof(asic_cmd.cmd)); 1038 | 1039 | printk_ratelimited("send BC data:"); 1040 | dump_hex((uint8_t*)&asic_cmd,sizeof(asic_cmd)); 1041 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 1042 | spi_tranfer(0x00, (uint8_t*)&asic_cmd, sizeof(asic_cmd), g_rx_data, &rx_size); 1043 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 1044 | return 0; 1045 | } 1046 | 1047 | extern void clear_fpga_nonce_buffer(BT_AS_INFO dev) 1048 | { 1049 | uint32_t cnt = 0; 1050 | int ret; 1051 | printk_ratelimited(KERN_ERR "clear FPGA nonce buffer\n"); 1052 | dev->clear_fpga_fifo = true; 1053 | while(1) 1054 | { 1055 | if((ret = nonce_query(dev)) == 0) 1056 | { 1057 | nonce_query(dev); 1058 | dev->fpga_ok = true; 1059 | break; 1060 | } 1061 | else if(ret < 0) 1062 | { 1063 | printk_ratelimited(KERN_ERR "FPGA don't code\n"); 1064 | dev->fpga_ok = false; 1065 | break; 1066 | } 1067 | if(cnt++ > 100) 1068 | { 1069 | printk_ratelimited(KERN_ERR "clear FPGA nonce buffer err\n"); 1070 | break; 1071 | } 1072 | } 1073 | dev->clear_fpga_fifo = false; 1074 | //dev->total_nonce_num = dev->fpga_nonce1_num; 1075 | ret_nonce_num = 0; 1076 | return; 1077 | } 1078 | void sort_array(unsigned char *a, unsigned int count) 1079 | { 1080 | unsigned int i,j; 1081 | unsigned char temp; 1082 | for(i=1;itemp && j>=0) 1087 | { 1088 | a[j+1]=a[j]; 1089 | j--; 1090 | } 1091 | if(j!=(i-1)) 1092 | a[j+1]=temp; 1093 | } 1094 | } 1095 | extern void detect_chain_num(BT_AS_INFO dev) 1096 | { 1097 | unsigned long last_jiffies; 1098 | wait_queue_head_t timeout_wq; 1099 | unsigned char asic_addr[256]; 1100 | unsigned char addr_pos = 0; 1101 | uint32_t i = 0, j, n; 1102 | uint8_t Asic_num; 1103 | uint8_t chain_remap = 0; 1104 | uint8_t one_cnt, detect_cnt = 0; 1105 | uint8_t addr_interval; 1106 | uint8_t actual_chip_num[CHAIN_SIZE] = {0}; 1107 | struct ASIC_TASK asic_work = {0}; 1108 | #if defined S2 1109 | printk_ratelimited("S2 reset hash board\n"); 1110 | iowrite32(0x01<<7, gpio2_vaddr + GPIO_CLEARDATAOUT); 1111 | init_waitqueue_head(&timeout_wq); 1112 | interruptible_sleep_on_timeout(&timeout_wq, 1000 * HZ/1000);//300ms 1113 | iowrite32(0x01<<7, gpio2_vaddr + GPIO_SETDATAOUT); 1114 | iowrite32(0x01<<7, gpio2_vaddr + GPIO_CLEARDATAOUT); 1115 | init_waitqueue_head(&timeout_wq); 1116 | interruptible_sleep_on_timeout(&timeout_wq, 1000 * HZ/1000);//300ms 1117 | iowrite32(0x01<<7, gpio2_vaddr + GPIO_SETDATAOUT); 1118 | clear_fpga_nonce_buffer(dev); 1119 | #else 1120 | //clear fpga work fifo 1121 | rst_hash_asic(dev); 1122 | //send_work_to_fpga(true, dev, &asic_task); 1123 | clear_fpga_nonce_buffer(dev); 1124 | init_waitqueue_head(&timeout_wq); 1125 | interruptible_sleep_on_timeout(&timeout_wq, 1000 * HZ/1000);//300ms 1126 | #if 1 1127 | rst_hash_asic(dev); 1128 | //send_work_to_fpga(true, dev, &asic_work); 1129 | clear_fpga_nonce_buffer(dev); 1130 | init_waitqueue_head(&timeout_wq); 1131 | interruptible_sleep_on_timeout(&timeout_wq, 1100 * HZ/1000);//300ms 1132 | #endif 1133 | #endif 1134 | //init_waitqueue_head(&timeout_wq); 1135 | //clear_fpga_nonce_buffer(dev); 1136 | //interruptible_sleep_on_timeout(&timeout_wq, 10000 * HZ/1000);//3000ms 1137 | start_dect: 1138 | chain_remap = 0; 1139 | for (i = 0; i < CHAIN_SIZE; i++) 1140 | { 1141 | for(j = 0; j < sizeof(asic_addr); j++) 1142 | asic_addr[j] = 0; 1143 | if((dev->chain_exist & (0x01 << i)) == 0) 1144 | continue; 1145 | //clear_fpga_nonce_buffer(dev); 1146 | bitmain_asic_get_status(NULL, i, 1, 0, 0); //CHIP_ADDR_REG 0 1147 | last_jiffies = jiffies + 100*HZ/1000;//100ms detect 1148 | asic_result_status_wr = asic_result_status_rd = 0; 1149 | dev->get_status = true; 1150 | /* 1151 | while(1) 1152 | { 1153 | if(time_after(jiffies, last_jiffies)) 1154 | break; 1155 | if(nonce_query(dev) != 0) 1156 | break; 1157 | }*/ 1158 | interruptible_sleep_on_timeout(&timeout_wq, 100 * HZ/1000);//500ms 1159 | nonce_query(dev); 1160 | addr_pos = 0; 1161 | /* 1162 | printk_ratelimited(KERN_ERR "wait rev\n"); 1163 | while(1) 1164 | { 1165 | while(asic_result_status_wr != asic_result_status_rd)//此链有芯片 1166 | { 1167 | while(asic_result_status_wr != asic_result_status_rd) 1168 | asic_addr[addr_pos++] = asic_result_status[asic_result_status_rd++] & 0xff; 1169 | asic_result_status_wr = asic_result_status_rd = 0; 1170 | nonce_query(dev); 1171 | } 1172 | if ( 0 != interruptible_sleep_on_timeout(&timeout_wq, 100 * HZ/1000))//500ms 1173 | break; 1174 | nonce_query(dev); 1175 | } 1176 | */ 1177 | while(asic_result_status_wr != asic_result_status_rd)//此链有芯片 1178 | { 1179 | while(asic_result_status_wr != asic_result_status_rd) 1180 | asic_addr[addr_pos++] = asic_result_status[asic_result_status_rd++] & 0xff; 1181 | asic_result_status_wr = asic_result_status_rd = 0; 1182 | nonce_query(dev); 1183 | } 1184 | printk_ratelimited(KERN_ERR "chain%d total asic:%d\n", i, addr_pos); 1185 | gChain_Asic_num[i] = addr_pos; 1186 | actual_chip_num[i] = addr_pos; 1187 | //remap chain from chain_exist 1188 | if(dev->chain_exist&(0x01 << i)) 1189 | dev->chain_map[chain_remap++] = i; 1190 | //调整2^n个芯片 1191 | calculate_check_bit: 1192 | j = 0; 1193 | one_cnt = 0; 1194 | Asic_num = gChain_Asic_num[i]; 1195 | while (1) 1196 | { 1197 | if (Asic_num != 0) 1198 | { 1199 | j++; 1200 | if (Asic_num & 0x01) 1201 | one_cnt++; 1202 | Asic_num >>= 1; 1203 | } 1204 | else 1205 | break; 1206 | } 1207 | gChain_Asic_Check_bit[i] = j; 1208 | if (one_cnt == 1) 1209 | gChain_Asic_Check_bit[i] -= 1; 1210 | //printk_ratelimited(KERN_ERR "gChain%d_Asic_Check_bit = %d\n", i, gChain_Asic_Check_bit[i]); 1211 | for(j = 0; j< 8; j++) 1212 | { 1213 | gChain_Asic_status[i][j] = 0; 1214 | //dev->asic_status_data.chain_asic_exist[dev->chain_map[chain_remap-1]][j] = 0; 1215 | dev->chain_asic_exist[i][j] = 0; 1216 | } 1217 | if(gChain_Asic_num[i] != 0) 1218 | gChain_Asic_num[i] = 0x01 << gChain_Asic_Check_bit[i]; 1219 | else 1220 | continue; 1221 | addr_interval = 0x100 / gChain_Asic_num[i]; 1222 | gChain_Asic_Interval[i] = addr_interval; 1223 | sort_array(asic_addr, addr_pos); 1224 | n = 0; 1225 | for (j = 0; j < addr_pos; j++) 1226 | { 1227 | if((j >= 1) && ((asic_addr[j] - asic_addr[j-1]) < addr_interval) && (asic_addr[j] != asic_addr[j-1])) 1228 | { 1229 | addr_interval = asic_addr[j] - asic_addr[j-1]; 1230 | gChain_Asic_num[i] = 0x100/addr_interval; 1231 | printk_ratelimited("Chain %d modify exist Asic_num[%d]\n", i, gChain_Asic_num[i]); 1232 | goto calculate_check_bit; 1233 | } 1234 | if(actual_chip_num[i] != 0) 1235 | { 1236 | if((j>=1) && ((asic_addr[j] - asic_addr[j-1]) == 0x100/actual_chip_num[i])) 1237 | addr_interval = 0x100/actual_chip_num[i]; 1238 | } 1239 | if(asic_addr[j] != asic_addr[0]) 1240 | { 1241 | while ((n * addr_interval) != asic_addr[j]) 1242 | { 1243 | gChain_Asic_status[i][n/32] &= ~(0x1 << n%32); 1244 | //dev->asic_status_data.chain_asic_exist[i][j/32] &= ~(0x1 << n%32); 1245 | dev->chain_asic_exist[i][n/32] &= ~(0x1 << n%32); 1246 | if (++n >= gChain_Asic_num[i]) 1247 | break; 1248 | } 1249 | } 1250 | gChain_Asic_status[i][n/32] |= (0x1 << n%32); 1251 | dev->chain_asic_exist[i][n/32] |= (0x1 << n%32); 1252 | printk_ratelimited(KERN_ERR "pos%d--addr:%02x\n", j, asic_addr[j]); 1253 | n++; 1254 | } 1255 | printk_ratelimited(KERN_ERR "chain%d_asic_exist{0x%08x}\n", i, dev->chain_asic_exist[i][0]); 1256 | } 1257 | 1258 | dev->asic_configure.chain_num = chain_remap; 1259 | dev->asic_status_data.chain_num = dev->asic_configure.chain_num; 1260 | gTotal_asic_num = 0; 1261 | for (i = 0; i < CHAIN_SIZE; i++) 1262 | { 1263 | gTotal_asic_num += gChain_Asic_num[i]; 1264 | } 1265 | printk_ratelimited(KERN_ERR "total chain_num{%d}\n", dev->asic_status_data.chain_num); 1266 | g_FPGA_RESERVE_FIFO_SPACE = dev->asic_status_data.chain_num * 2; 1267 | if(gTotal_asic_num == 0) 1268 | { 1269 | printk_ratelimited(KERN_ERR "FPGA detect asic addr err\n\n"); 1270 | if(detect_cnt ++ < 3) 1271 | { 1272 | printk_ratelimited(KERN_ERR "\n\n!!!!Restart%d detect asic addr!!!\n\n", detect_cnt); 1273 | goto start_dect; 1274 | } 1275 | 1276 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 1277 | { 1278 | //dev->chain_map[i] = i; 1279 | #ifdef S4_Board 1280 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1281 | gChain_Asic_num[dev->chain_map[i]] = 40; 1282 | #else 1283 | #ifdef C1_Board 1284 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1285 | gChain_Asic_num[dev->chain_map[i]] = 16; 1286 | #else 1287 | #ifdef S5 1288 | printk_ratelimited(KERN_ERR "S5 board\n"); 1289 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1290 | gChain_Asic_num[dev->chain_map[i]] = 48; 1291 | #endif 1292 | #endif 1293 | #endif 1294 | dev->chain_asic_exist[dev->chain_map[i]][0] = 0xffffffff; 1295 | dev->chain_asic_exist[dev->chain_map[i]][1] = 0xffffffff; 1296 | gChain_Asic_status[dev->chain_map[i]][0] = 0xffffffff; 1297 | gChain_Asic_status[dev->chain_map[i]][1] = 0xffffffff; 1298 | gChain_Asic_Interval[dev->chain_map[i]] = 0x100/gChain_Asic_num[dev->chain_map[i]]; 1299 | } 1300 | printk_ratelimited(KERN_ERR "\n\n!!!!soft set defult asic num %d!!!\n\n", gChain_Asic_num[0]); 1301 | gTotal_asic_num = gChain_Asic_num[0] * dev->asic_status_data.chain_num; 1302 | dev->temp_num = dev->asic_status_data.chain_num; 1303 | dev->fan_num = 6;//CHAIN_SIZE; 1304 | for(i = 0; i < dev->fan_num; i++) 1305 | { 1306 | dev->fan_map[i] = i; 1307 | } 1308 | } 1309 | else 1310 | { 1311 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 1312 | { 1313 | printk_ratelimited(KERN_ERR "chain%d chain_map %d\n", i, dev->chain_map[i]); 1314 | printk_ratelimited(KERN_ERR "chain%d asic_num--%d actual--%d\n", i, gChain_Asic_num[dev->chain_map[i]], actual_chip_num[dev->chain_map[i]]); 1315 | gChain_Asic_num[dev->chain_map[i]] = actual_chip_num[dev->chain_map[i]]; 1316 | #ifdef S4_Board 1317 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1318 | gChain_Asic_num[dev->chain_map[i]] = 40; 1319 | #else 1320 | #ifdef C1_Board 1321 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1322 | gChain_Asic_num[dev->chain_map[i]] = 16; 1323 | #else 1324 | #ifdef S5 1325 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1326 | gChain_Asic_num[dev->chain_map[i]] = 30; 1327 | #endif 1328 | #endif 1329 | #endif 1330 | if(gChain_Asic_num[dev->chain_map[i]] !=0 ) 1331 | gChain_Asic_Interval[dev->chain_map[i]] = 0x100/gChain_Asic_num[dev->chain_map[i]]; 1332 | printk_ratelimited(KERN_ERR "chain%d sw addr interval %d\n", i, gChain_Asic_Interval[dev->chain_map[i]]); 1333 | if(gChain_Asic_num[dev->chain_map[i]] == 0) 1334 | { 1335 | printk_ratelimited(KERN_ERR "chain%d actual 0 addr Adjust\n", i); 1336 | if(i != 0) 1337 | { 1338 | gChain_Asic_num[dev->chain_map[i]] = gChain_Asic_num[dev->chain_map[i-1]]; 1339 | gChain_Asic_Check_bit[dev->chain_map[i]] = gChain_Asic_Check_bit[dev->chain_map[i-1]]; 1340 | } 1341 | else 1342 | { 1343 | gChain_Asic_num[dev->chain_map[i]] = gChain_Asic_num[dev->chain_map[i+1]]; 1344 | gChain_Asic_Check_bit[dev->chain_map[i]] = gChain_Asic_Check_bit[dev->chain_map[i+1]]; 1345 | } 1346 | } 1347 | } 1348 | dev->temp_num = dev->asic_status_data.chain_num; 1349 | 1350 | #if 0 1351 | dev->fan_num = 0; 1352 | for(i = 0; i < sizeof(dev->fan_exist); i++) 1353 | { 1354 | if(dev->fan_exist & (0x01 << i)) 1355 | { 1356 | dev->fan_map[dev->fan_num] = i; 1357 | dev->fan_num++; 1358 | } 1359 | } 1360 | #endif 1361 | dev->fan_num = 6;//CHAIN_SIZE; 1362 | for(i = 0; i < dev->fan_num; i++) 1363 | { 1364 | dev->fan_map[i] = i; 1365 | } 1366 | //dev->fan_num = 0; 1367 | } 1368 | #if 0 1369 | bitmain_sw_addr(dev); 1370 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 1371 | clear_fpga_nonce_buffer(dev); 1372 | bitmain_asic_get_status(NULL, 0, 1, 0, 0); //CHIP_ADDR_REG 0 1373 | interruptible_sleep_on_timeout(&timeout_wq, 100 * HZ/1000);//500ms 1374 | asic_result_status_wr = asic_result_status_rd = 0; 1375 | nonce_query(dev); 1376 | while(asic_result_status_wr != asic_result_status_rd)//此链有芯片 1377 | { 1378 | asic_result_status_wr = asic_result_status_rd = 0; 1379 | nonce_query(dev); 1380 | } 1381 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 1382 | #endif 1383 | dev->get_status = false; 1384 | } 1385 | 1386 | void sw_addr(BT_AS_INFO dev) 1387 | { 1388 | uint32_t i; 1389 | wait_queue_head_t timeout_wq; 1390 | init_waitqueue_head(&timeout_wq); 1391 | struct ASIC_TASK asic_work = {0}; 1392 | #ifndef S5_S_VL 1393 | bitmain_sw_addr(dev); 1394 | #endif 1395 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 1396 | clear_fpga_nonce_buffer(dev); 1397 | dev->get_status = true; 1398 | bitmain_asic_get_status(NULL, dev->chain_map[0], 1, 0, 0); //CHIP_ADDR_REG 0 1399 | interruptible_sleep_on_timeout(&timeout_wq, 100 * HZ/1000);//500ms 1400 | asic_result_status_wr = asic_result_status_rd = 0; 1401 | nonce_query(dev); 1402 | while(asic_result_status_wr != asic_result_status_rd)//此链有芯片 1403 | { 1404 | asic_result_status_wr = asic_result_status_rd = 0; 1405 | nonce_query(dev); 1406 | } 1407 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 1408 | dev->get_status = false; 1409 | #ifndef S5_S_VL 1410 | for(i = 0; i < dev->asic_status_data.chain_num; i++) 1411 | { 1412 | memset(asic_work.midstate, 0x00, sizeof(asic_work.midstate)); 1413 | memset(asic_work.data, 0x00, sizeof(asic_work.data)); 1414 | send_work_to_fpga(false, 0xc0|dev->chain_map[i], dev, &asic_work); 1415 | } 1416 | #endif 1417 | return; 1418 | } 1419 | -------------------------------------------------------------------------------- /fpga.h: -------------------------------------------------------------------------------- 1 | #ifndef __FPGA_H__ 2 | #define __FPGA_H__ 3 | //To fpga type 4 | #define NOR_BLOCK 0x01 5 | #define NEW_BLOCK 0x11 6 | #define ASIC_CMD 0x03 7 | #define QEURY_FPGA 0x02 8 | 9 | typedef struct { 10 | uint8_t block_type; 11 | uint8_t chain_id; 12 | uint8_t reserved1[2]; 13 | uint8_t midstate[32]; 14 | uint32_t work_id; 15 | uint8_t data[12]; 16 | } FPGA_WORK; 17 | typedef struct { 18 | uint8_t cmd_type; 19 | uint8_t chain_num; 20 | uint8_t reserved1[1]; 21 | /* 22 | 115.200 115.740 26 216 23 | 460.800 446.429 6 56 24 | 921.600 1.041.666 2 24 25 | 1.500.000 1.562.500 1 16 26 | */ 27 | uint8_t bauddiv; //5-3: res 4:0 28 | uint8_t cmd[4]; 29 | } FPGA_ASIC_CMD; 30 | 31 | typedef struct { 32 | uint8_t cmd_type; 33 | uint8_t reserved1[2]; 34 | uint8_t rst_time : 7; 35 | uint8_t rst_valid : 1; 36 | uint16_t pwm_h; 37 | uint16_t pwm_l; 38 | uint32_t toctl; 39 | uint32_t tm; //12-15 40 | uint32_t hcn; //16-19 41 | uint32_t sno;//20-23 42 | uint8_t reserved2[48 - 8 -12]; 43 | } FPGA_QUERY; 44 | 45 | #if 0 46 | typedef struct { 47 | uint8_t type; 48 | uint8_t reserved0; 49 | uint8_t fpga_version; 50 | uint8_t pc_version; 51 | uint8_t nonce[32]; // 4-35 52 | //uint32_t fifo_space; 53 | uint16_t fifo_total; 54 | uint16_t have_bytes; 55 | uint8_t reserved1; 56 | uint8_t fan_exist; 57 | uint16_t chain_exist; 58 | uint8_t fan_speed[4]; 59 | uint32_t nonce1_num; 60 | } FPGA_RETURN; 61 | #else 62 | typedef struct { 63 | uint8_t type; 64 | uint8_t reserved0; 65 | uint8_t fpga_version; 66 | uint8_t pc_version; 67 | uint16_t fifo_total; 68 | uint16_t have_bytes; 69 | uint8_t fan_index : 3; 70 | uint8_t reserved1 : 5; 71 | uint8_t fan_speed; 72 | uint16_t chain_exist; 73 | uint8_t nonce[40]; // 12-51 74 | } FPGA_RETURN; 75 | 76 | #endif 77 | /******************************* 78 | Byte0~3 Byte 4 Byte 5 Byte 6 Byte 7 79 | nonce Work count temperature Reserved ChainNumber 80 | ChainNumber的格式如下表所示： 81 | Bit[7] :Nonce indicator: 82 | 0: invalid 83 | 1: valid 84 | Bit[6]:Temperature indicator: 85 | 0: invalid 86 | 1: valid 87 | Bit[5:4] Reserved 88 | Bit[3:0] number 89 | **********************************/ 90 | typedef struct { 91 | uint32_t nonce; 92 | uint16_t work_id; 93 | //uint8_t reserved; 94 | uint8_t temp;; 95 | //uint8_t chain_num; 96 | uint8_t chain_num : 4; 97 | uint8_t reserved1 : 2; 98 | uint8_t temp_valid: 1; 99 | uint8_t nonce_valid:1; 100 | } FPGA_RET_NONCE; 101 | 102 | extern uint16_t g_FPGA_FIFO_SPACE, g_TOTAL_FPGA_FIFO; 103 | extern uint16_t g_FPGA_RESERVE_FIFO_SPACE; 104 | extern bool is_started; 105 | extern uint16_t asic_result_wr, asic_result_rd, asic_result_full; 106 | extern uint16_t asic_result_status_wr, asic_result_status_rd, asic_result_status_full; 107 | extern volatile struct ASIC_RESULT asic_result[512]; 108 | #define ASIC_RESULT_NUM (sizeof(asic_result)/sizeof(asic_result[0])) 109 | extern uint32_t asic_result_status[512]; 110 | #define ASIC_RESULT_STATUS_NUM (sizeof(asic_result_status)/sizeof(asic_result_status[0])) 111 | 112 | extern int nonce_query(BT_AS_INFO dev); 113 | extern int send_work_to_fpga(bool new_block, unsigned char chain_id, BT_AS_INFO dev, ASIC_TASK_P asic_work); 114 | extern int send_BC_to_fpga(uint8_t chain_num, uint8_t *cmd); 115 | extern void clear_fpga_nonce_buffer(BT_AS_INFO dev); 116 | extern void set_frequency(BT_AS_INFO dev, unsigned int freq); 117 | extern void rev(unsigned char *s, size_t l); 118 | extern void rst_hash_asic(BT_AS_INFO dev); 119 | extern void detect_chain_num(BT_AS_INFO dev); 120 | extern int bitmain_asic_get_status(char* buf, char chain, char mode, char chip_addr, char reg_addr); 121 | extern void bitmain_set_voltage(BT_AS_INFO dev, unsigned short voltage); 122 | extern void set_baud(BT_AS_INFO dev, unsigned char bauddiv); 123 | extern unsigned char get_baud(uint16_t frequency); 124 | extern void sw_addr(BT_AS_INFO dev); 125 | 126 | #endif 127 | -------------------------------------------------------------------------------- /set_pll.h: -------------------------------------------------------------------------------- 1 | #ifndef __SET_PLL_H__ 2 | #define __SET_PLL_H__ 3 | 4 | #include 5 | 6 | struct freq_pll 7 | { 8 | const char *freq; 9 | unsigned int fildiv1; 10 | unsigned int fildiv2; 11 | unsigned int vilpll; 12 | }; 13 | 14 | static struct freq_pll freq_pll_1385[] = { 15 | {"100",0x020040, 0x0420, 0x200241}, 16 | {"125",0x028040, 0x0420, 0x280241}, 17 | {"150",0x030040, 0x0420, 0x300241}, 18 | {"175",0x038040, 0x0420, 0x380241}, 19 | {"200",0x040040, 0x0420, 0x400241}, 20 | {"225",0x048040, 0x0420, 0x480241}, 21 | {"250",0x050040, 0x0420, 0x500241}, 22 | {"275",0x058040, 0x0420, 0x580241}, 23 | {"300",0x060040, 0x0420, 0x600241}, 24 | {"325",0x068040, 0x0420, 0x680241}, 25 | {"350",0x070040, 0x0420, 0x700241}, 26 | {"375",0x078040, 0x0420, 0x780241}, 27 | {"400",0x080040, 0x0420, 0x800241}, 28 | {"404",0x061040, 0x0320, 0x610231}, 29 | {"406",0x041040, 0x0220, 0x410221}, 30 | {"408",0x062040, 0x0320, 0x620231}, 31 | {"412",0x042040, 0x0220, 0x420221}, 32 | {"416",0x064040, 0x0320, 0x640231}, 33 | {"418",0x043040, 0x0220, 0x430221}, 34 | {"420",0x065040, 0x0320, 0x650231}, 35 | {"425",0x044040, 0x0220, 0x440221}, 36 | {"429",0x067040, 0x0320, 0x670231}, 37 | {"431",0x045040, 0x0220, 0x450221}, 38 | {"433",0x068040, 0x0320, 0x680231}, 39 | {"437",0x046040, 0x0220, 0x460221}, 40 | {"441",0x06a040, 0x0320, 0x6a0231}, 41 | {"443",0x047040, 0x0220, 0x470221}, 42 | {"445",0x06b040, 0x0320, 0x6b0231}, 43 | {"450",0x048040, 0x0220, 0x480221}, 44 | {"454",0x06d040, 0x0320, 0x6d0231}, 45 | {"456",0x049040, 0x0220, 0x490221}, 46 | {"458",0x06e040, 0x0320, 0x6e0231}, 47 | {"462",0x04a040, 0x0220, 0x4a0221}, 48 | {"466",0x070040, 0x0320, 0x700231}, 49 | {"468",0x04b040, 0x0220, 0x4b0221}, 50 | {"470",0x071040, 0x0320, 0x710231}, 51 | {"475",0x04c040, 0x0220, 0x4c0221}, 52 | {"479",0x073040, 0x0320, 0x730231}, 53 | {"481",0x04d040, 0x0220, 0x4d0221}, 54 | {"483",0x074040, 0x0320, 0x740231}, 55 | {"487",0x04e040, 0x0220, 0x4e0221}, 56 | {"491",0x076040, 0x0320, 0x760231}, 57 | {"493",0x04f040, 0x0220, 0x4f0221}, 58 | {"495",0x077040, 0x0320, 0x770231}, 59 | {"500",0x050040, 0x0220, 0x500221}, 60 | {"504",0x079040, 0x0320, 0x790231}, 61 | {"506",0x051040, 0x0220, 0x510221}, 62 | {"508",0x07a040, 0x0320, 0x7a0231}, 63 | {"512",0x052040, 0x0220, 0x520221}, 64 | {"516",0x07c040, 0x0320, 0x7c0231}, 65 | {"518",0x053040, 0x0220, 0x530221}, 66 | {"520",0x07d040, 0x0320, 0x7d0231}, 67 | {"525",0x054040, 0x0220, 0x540221}, 68 | {"529",0x07f040, 0x0320, 0x7f0231}, 69 | {"531",0x055040, 0x0220, 0x550221}, 70 | {"533",0x080040, 0x0320, 0x800231}, 71 | {"537",0x056040, 0x0220, 0x560221}, 72 | {"543",0x057040, 0x0220, 0x570221}, 73 | {"550",0x058040, 0x0220, 0x580221}, 74 | {"556",0x059040, 0x0220, 0x590221}, 75 | {"562",0x05a040, 0x0220, 0x5a0221}, 76 | {"568",0x05b040, 0x0220, 0x5b0221}, 77 | {"575",0x05c040, 0x0220, 0x5c0221}, 78 | {"581",0x05d040, 0x0220, 0x5d0221}, 79 | {"587",0x05e040, 0x0220, 0x5e0221}, 80 | {"593",0x05f040, 0x0220, 0x5f0221}, 81 | {"600",0x060040, 0x0220, 0x600221}, 82 | {"606",0x061040, 0x0220, 0x610221}, 83 | {"612",0x062040, 0x0220, 0x620221}, 84 | {"618",0x063040, 0x0220, 0x630221}, 85 | {"625",0x064040, 0x0220, 0x640221}, 86 | {"631",0x065040, 0x0220, 0x650221}, 87 | {"637",0x066040, 0x0220, 0x660221}, 88 | {"643",0x067040, 0x0220, 0x670221}, 89 | {"650",0x068040, 0x0220, 0x680221}, 90 | {"656",0x069040, 0x0220, 0x690221}, 91 | {"662",0x06a040, 0x0220, 0x6a0221}, 92 | {"668",0x06b040, 0x0220, 0x6b0221}, 93 | {"675",0x06c040, 0x0220, 0x6c0221}, 94 | {"681",0x06d040, 0x0220, 0x6d0221}, 95 | {"687",0x06e040, 0x0220, 0x6e0221}, 96 | {"693",0x06f040, 0x0220, 0x6f0221}, 97 | {"700",0x070040, 0x0220, 0x700221}, 98 | {"706",0x071040, 0x0220, 0x710221}, 99 | {"712",0x072040, 0x0220, 0x720221}, 100 | {"718",0x073040, 0x0220, 0x730221}, 101 | {"725",0x074040, 0x0220, 0x740221}, 102 | {"731",0x075040, 0x0220, 0x750221}, 103 | {"737",0x076040, 0x0220, 0x760221}, 104 | {"743",0x077040, 0x0220, 0x770221}, 105 | {"750",0x078040, 0x0220, 0x780221}, 106 | {"756",0x079040, 0x0220, 0x790221}, 107 | {"762",0x07a040, 0x0220, 0x7a0221}, 108 | {"768",0x07b040, 0x0220, 0x7b0221}, 109 | {"775",0x07c040, 0x0220, 0x7c0221}, 110 | {"781",0x07d040, 0x0220, 0x7d0221}, 111 | {"787",0x07e040, 0x0220, 0x7e0221}, 112 | {"793",0x07f040, 0x0220, 0x7f0221}, 113 | {"800",0x080040, 0x0220, 0x800221}, 114 | {"825",0x042040, 0x0120, 0x420211}, 115 | }; 116 | 117 | static const int hex2bin_tbl[256] = { 118 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 119 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 120 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 121 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, -1, -1, -1, -1, -1, -1, 122 | -1, 10, 11, 12, 13, 14, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1, 123 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 124 | -1, 10, 11, 12, 13, 14, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1, 125 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 126 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 127 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 128 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 129 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 130 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 131 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 132 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 133 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 134 | }; 135 | 136 | static void get_plldata(int type,int freq,uint32_t * reg_data,uint16_t * reg_data2) 137 | { 138 | uint32_t i; 139 | char freq_str[10]; 140 | sprintf(freq_str,"%d", freq); 141 | char plldivider1[32] = {0}; 142 | char plldivider2[32] = {0}; 143 | 144 | if(type == 1385) 145 | { 146 | for(i=0; i < sizeof(freq_pll_1385)/sizeof(freq_pll_1385[0]); i++) 147 | { 148 | if( memcmp(freq_pll_1385[i].freq, freq_str, sizeof(freq_pll_1385[i].freq)) == 0) 149 | break; 150 | } 151 | } 152 | 153 | if(i == sizeof(freq_pll_1385)/sizeof(freq_pll_1385[0])) 154 | { 155 | printk_ratelimited(KERN_ERR "Freq set Err!!!!\n"); 156 | printk_ratelimited(KERN_ERR "Using 200M\n"); 157 | i = 4; 158 | } 159 | 160 | sprintf(plldivider1, "%08x", freq_pll_1385[i].fildiv1); 161 | sprintf(plldivider2, "%04x", freq_pll_1385[i].fildiv2); 162 | 163 | printk_ratelimited("Freq %s, PLL1 %s, PLL2 %s\n", freq_str, plldivider1, plldivider2); 164 | 165 | *reg_data = freq_pll_1385[i].fildiv1; 166 | *reg_data2 = freq_pll_1385[i].fildiv2; 167 | 168 | printk_ratelimited(KERN_ERR "PLL1 %#x, PLL2 %#x\n",*reg_data, *reg_data2); 169 | } 170 | 171 | #endif 172 | -------------------------------------------------------------------------------- /sha2.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FIPS-180-2 compliant SHA-256 implementation 3 | * 4 | * Copyright (C) 2011, Con Kolivas 5 | * Copyright (C) 2006-2010, Brainspark B.V. 6 | * 7 | * This file is part of PolarSSL (http://www.polarssl.org) 8 | * Lead Maintainer: Paul Bakker 9 | * 10 | * All rights reserved. 11 | * 12 | * This program is free software; you can redistribute it and/or modify 13 | * it under the terms of the GNU General Public License as published by 14 | * the Free Software Foundation; either version 3 of the License, or 15 | * (at your option) any later version. 16 | * 17 | * This program is distributed in the hope that it will be useful, 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 | * GNU General Public License for more details. 21 | * 22 | * You should have received a copy of the GNU General Public License along 23 | * with this program; if not, write to the Free Software Foundation, Inc., 24 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 25 | */ 26 | /* 27 | * The SHA-256 Secure Hash Standard was published by NIST in 2002. 28 | * 29 | * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf 30 | */ 31 | #include 32 | #include 33 | #include 34 | 35 | #include "sha2.h" 36 | 37 | extern void dump_hex(uint8_t *data, uint16_t len); 38 | /* 39 | * 32-bit integer manipulation macros (big endian) 40 | */ 41 | #ifndef GET_ULONG_BE 42 | #define GET_ULONG_BE(n,b,i) \ 43 | { \ 44 | (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ 45 | | ( (uint32_t) (b)[(i) + 1] << 16 ) \ 46 | | ( (uint32_t) (b)[(i) + 2] << 8 ) \ 47 | | ( (uint32_t) (b)[(i) + 3] ); \ 48 | } 49 | #endif 50 | 51 | #ifndef PUT_ULONG_BE 52 | #define PUT_ULONG_BE(n,b,i) \ 53 | { \ 54 | (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ 55 | (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ 56 | (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ 57 | (b)[(i) + 3] = (unsigned char) ( (n) ); \ 58 | } 59 | #endif 60 | 61 | /* 62 | * SHA-256 context setup 63 | */ 64 | void sha2_starts( sha2_context *ctx ) 65 | { 66 | ctx->total[0] = 0; 67 | ctx->total[1] = 0; 68 | 69 | ctx->state[0] = 0x6A09E667; 70 | ctx->state[1] = 0xBB67AE85; 71 | ctx->state[2] = 0x3C6EF372; 72 | ctx->state[3] = 0xA54FF53A; 73 | ctx->state[4] = 0x510E527F; 74 | ctx->state[5] = 0x9B05688C; 75 | ctx->state[6] = 0x1F83D9AB; 76 | ctx->state[7] = 0x5BE0CD19; 77 | } 78 | 79 | void sha2_process( sha2_context *ctx, const unsigned char data[64] ) 80 | { 81 | uint32_t temp1, temp2, W[64]; 82 | uint32_t A, B, C, D, E, F, G, H; 83 | 84 | GET_ULONG_BE( W[ 0], data, 0 ); 85 | GET_ULONG_BE( W[ 1], data, 4 ); 86 | GET_ULONG_BE( W[ 2], data, 8 ); 87 | GET_ULONG_BE( W[ 3], data, 12 ); 88 | GET_ULONG_BE( W[ 4], data, 16 ); 89 | GET_ULONG_BE( W[ 5], data, 20 ); 90 | GET_ULONG_BE( W[ 6], data, 24 ); 91 | GET_ULONG_BE( W[ 7], data, 28 ); 92 | GET_ULONG_BE( W[ 8], data, 32 ); 93 | GET_ULONG_BE( W[ 9], data, 36 ); 94 | GET_ULONG_BE( W[10], data, 40 ); 95 | GET_ULONG_BE( W[11], data, 44 ); 96 | GET_ULONG_BE( W[12], data, 48 ); 97 | GET_ULONG_BE( W[13], data, 52 ); 98 | GET_ULONG_BE( W[14], data, 56 ); 99 | GET_ULONG_BE( W[15], data, 60 ); 100 | 101 | #define SHR(x,n) ((x & 0xFFFFFFFF) >> n) 102 | #define ROTR(x,n) (SHR(x,n) | (x << (32 - n))) 103 | 104 | #define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3)) 105 | #define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10)) 106 | 107 | #define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22)) 108 | #define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25)) 109 | 110 | #define F0(x,y,z) ((x & y) | (z & (x | y))) 111 | #define F1(x,y,z) (z ^ (x & (y ^ z))) 112 | 113 | #define R(t) \ 114 | ( \ 115 | W[t] = S1(W[t - 2]) + W[t - 7] + \ 116 | S0(W[t - 15]) + W[t - 16] \ 117 | ) 118 | 119 | #define P(a,b,c,d,e,f,g,h,x,K) \ 120 | { \ 121 | temp1 = h + S3(e) + F1(e,f,g) + K + x; \ 122 | temp2 = S2(a) + F0(a,b,c); \ 123 | d += temp1; h = temp1 + temp2; \ 124 | } 125 | 126 | A = ctx->state[0]; 127 | B = ctx->state[1]; 128 | C = ctx->state[2]; 129 | D = ctx->state[3]; 130 | E = ctx->state[4]; 131 | F = ctx->state[5]; 132 | G = ctx->state[6]; 133 | H = ctx->state[7]; 134 | 135 | P( A, B, C, D, E, F, G, H, W[ 0], 0x428A2F98 ); 136 | P( H, A, B, C, D, E, F, G, W[ 1], 0x71374491 ); 137 | P( G, H, A, B, C, D, E, F, W[ 2], 0xB5C0FBCF ); 138 | P( F, G, H, A, B, C, D, E, W[ 3], 0xE9B5DBA5 ); 139 | P( E, F, G, H, A, B, C, D, W[ 4], 0x3956C25B ); 140 | P( D, E, F, G, H, A, B, C, W[ 5], 0x59F111F1 ); 141 | P( C, D, E, F, G, H, A, B, W[ 6], 0x923F82A4 ); 142 | P( B, C, D, E, F, G, H, A, W[ 7], 0xAB1C5ED5 ); 143 | P( A, B, C, D, E, F, G, H, W[ 8], 0xD807AA98 ); 144 | P( H, A, B, C, D, E, F, G, W[ 9], 0x12835B01 ); 145 | P( G, H, A, B, C, D, E, F, W[10], 0x243185BE ); 146 | P( F, G, H, A, B, C, D, E, W[11], 0x550C7DC3 ); 147 | P( E, F, G, H, A, B, C, D, W[12], 0x72BE5D74 ); 148 | P( D, E, F, G, H, A, B, C, W[13], 0x80DEB1FE ); 149 | P( C, D, E, F, G, H, A, B, W[14], 0x9BDC06A7 ); 150 | P( B, C, D, E, F, G, H, A, W[15], 0xC19BF174 ); 151 | P( A, B, C, D, E, F, G, H, R(16), 0xE49B69C1 ); 152 | P( H, A, B, C, D, E, F, G, R(17), 0xEFBE4786 ); 153 | P( G, H, A, B, C, D, E, F, R(18), 0x0FC19DC6 ); 154 | P( F, G, H, A, B, C, D, E, R(19), 0x240CA1CC ); 155 | P( E, F, G, H, A, B, C, D, R(20), 0x2DE92C6F ); 156 | P( D, E, F, G, H, A, B, C, R(21), 0x4A7484AA ); 157 | P( C, D, E, F, G, H, A, B, R(22), 0x5CB0A9DC ); 158 | P( B, C, D, E, F, G, H, A, R(23), 0x76F988DA ); 159 | P( A, B, C, D, E, F, G, H, R(24), 0x983E5152 ); 160 | P( H, A, B, C, D, E, F, G, R(25), 0xA831C66D ); 161 | P( G, H, A, B, C, D, E, F, R(26), 0xB00327C8 ); 162 | P( F, G, H, A, B, C, D, E, R(27), 0xBF597FC7 ); 163 | P( E, F, G, H, A, B, C, D, R(28), 0xC6E00BF3 ); 164 | P( D, E, F, G, H, A, B, C, R(29), 0xD5A79147 ); 165 | P( C, D, E, F, G, H, A, B, R(30), 0x06CA6351 ); 166 | P( B, C, D, E, F, G, H, A, R(31), 0x14292967 ); 167 | P( A, B, C, D, E, F, G, H, R(32), 0x27B70A85 ); 168 | P( H, A, B, C, D, E, F, G, R(33), 0x2E1B2138 ); 169 | P( G, H, A, B, C, D, E, F, R(34), 0x4D2C6DFC ); 170 | P( F, G, H, A, B, C, D, E, R(35), 0x53380D13 ); 171 | P( E, F, G, H, A, B, C, D, R(36), 0x650A7354 ); 172 | P( D, E, F, G, H, A, B, C, R(37), 0x766A0ABB ); 173 | P( C, D, E, F, G, H, A, B, R(38), 0x81C2C92E ); 174 | P( B, C, D, E, F, G, H, A, R(39), 0x92722C85 ); 175 | P( A, B, C, D, E, F, G, H, R(40), 0xA2BFE8A1 ); 176 | P( H, A, B, C, D, E, F, G, R(41), 0xA81A664B ); 177 | P( G, H, A, B, C, D, E, F, R(42), 0xC24B8B70 ); 178 | P( F, G, H, A, B, C, D, E, R(43), 0xC76C51A3 ); 179 | P( E, F, G, H, A, B, C, D, R(44), 0xD192E819 ); 180 | P( D, E, F, G, H, A, B, C, R(45), 0xD6990624 ); 181 | P( C, D, E, F, G, H, A, B, R(46), 0xF40E3585 ); 182 | P( B, C, D, E, F, G, H, A, R(47), 0x106AA070 ); 183 | P( A, B, C, D, E, F, G, H, R(48), 0x19A4C116 ); 184 | P( H, A, B, C, D, E, F, G, R(49), 0x1E376C08 ); 185 | P( G, H, A, B, C, D, E, F, R(50), 0x2748774C ); 186 | P( F, G, H, A, B, C, D, E, R(51), 0x34B0BCB5 ); 187 | P( E, F, G, H, A, B, C, D, R(52), 0x391C0CB3 ); 188 | P( D, E, F, G, H, A, B, C, R(53), 0x4ED8AA4A ); 189 | P( C, D, E, F, G, H, A, B, R(54), 0x5B9CCA4F ); 190 | P( B, C, D, E, F, G, H, A, R(55), 0x682E6FF3 ); 191 | P( A, B, C, D, E, F, G, H, R(56), 0x748F82EE ); 192 | P( H, A, B, C, D, E, F, G, R(57), 0x78A5636F ); 193 | P( G, H, A, B, C, D, E, F, R(58), 0x84C87814 ); 194 | P( F, G, H, A, B, C, D, E, R(59), 0x8CC70208 ); 195 | P( E, F, G, H, A, B, C, D, R(60), 0x90BEFFFA ); 196 | P( D, E, F, G, H, A, B, C, R(61), 0xA4506CEB ); 197 | P( C, D, E, F, G, H, A, B, R(62), 0xBEF9A3F7 ); 198 | P( B, C, D, E, F, G, H, A, R(63), 0xC67178F2 ); 199 | 200 | ctx->state[0] += A; 201 | ctx->state[1] += B; 202 | ctx->state[2] += C; 203 | ctx->state[3] += D; 204 | ctx->state[4] += E; 205 | ctx->state[5] += F; 206 | ctx->state[6] += G; 207 | ctx->state[7] += H; 208 | } 209 | 210 | /* 211 | * SHA-256 process buffer 212 | */ 213 | void sha2_update( sha2_context *ctx, const unsigned char *input, int ilen ) 214 | { 215 | int fill; 216 | uint32_t left; 217 | 218 | if( ilen <= 0 ) 219 | return; 220 | 221 | left = ctx->total[0] & 0x3F; 222 | fill = 64 - left; 223 | 224 | ctx->total[0] += ilen; 225 | ctx->total[0] &= 0xFFFFFFFF; 226 | 227 | if( ctx->total[0] < (uint32_t) ilen ) 228 | ctx->total[1]++; 229 | 230 | if( left && ilen >= fill ) 231 | { 232 | memcpy( (void *) (ctx->buffer + left), 233 | (void *) input, fill ); 234 | sha2_process( ctx, ctx->buffer ); 235 | input += fill; 236 | ilen -= fill; 237 | left = 0; 238 | } 239 | 240 | while( ilen >= 64 ) 241 | { 242 | sha2_process( ctx, input ); 243 | input += 64; 244 | ilen -= 64; 245 | } 246 | 247 | if( ilen > 0 ) 248 | { 249 | memcpy( (void *) (ctx->buffer + left), 250 | (void *) input, ilen ); 251 | } 252 | /* 253 | printk_ratelimited("ctx sha2_update:"); 254 | dump_hex((uint8_t*)ctx,sizeof(*ctx)); 255 | */ 256 | } 257 | 258 | static const unsigned char sha2_padding[64] = 259 | { 260 | 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 261 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 262 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 263 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 264 | }; 265 | 266 | /* 267 | * SHA-256 final digest 268 | */ 269 | void sha2_finish( sha2_context *ctx, unsigned char output[32] ) 270 | { 271 | uint32_t last, padn; 272 | uint32_t high, low; 273 | unsigned char msglen[8]; 274 | #if 0 275 | uint8_t i; 276 | printk_ratelimited("ctx->state\n"); 277 | for(i=0; istate); i++) 278 | { 279 | printk_ratelimited("{%d}{%#x}, \n", i, *((uint8_t*)ctx->state +i)); 280 | } 281 | printk_ratelimited("ctx->buffer\n"); 282 | for(i=0; ibuffer); i++) 283 | { 284 | printk_ratelimited("{%d}{%#x}, \n", i, *((uint8_t*)ctx->buffer+i)); 285 | } 286 | 287 | printk_ratelimited("ctx->total[0]{%#x}ctx->total[1]{%#x}\n", ctx->total[0], ctx->total[1]); 288 | #endif 289 | high = ( ctx->total[0] >> 29 ) 290 | | ( ctx->total[1] << 3 ); 291 | low = ( ctx->total[0] << 3 ); 292 | 293 | PUT_ULONG_BE( high, msglen, 0 ); 294 | PUT_ULONG_BE( low, msglen, 4 ); 295 | 296 | last = ctx->total[0] & 0x3F; 297 | padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); 298 | 299 | sha2_update( ctx, (unsigned char *) sha2_padding, padn ); 300 | sha2_update( ctx, msglen, 8 ); 301 | 302 | PUT_ULONG_BE( ctx->state[0], output, 0 ); 303 | PUT_ULONG_BE( ctx->state[1], output, 4 ); 304 | PUT_ULONG_BE( ctx->state[2], output, 8 ); 305 | PUT_ULONG_BE( ctx->state[3], output, 12 ); 306 | PUT_ULONG_BE( ctx->state[4], output, 16 ); 307 | PUT_ULONG_BE( ctx->state[5], output, 20 ); 308 | PUT_ULONG_BE( ctx->state[6], output, 24 ); 309 | 310 | PUT_ULONG_BE( ctx->state[7], output, 28 ); 311 | } 312 | 313 | /* 314 | * output = SHA-256( input buffer ) 315 | */ 316 | void sha2( const unsigned char *input, int ilen, 317 | unsigned char output[32] ) 318 | { 319 | sha2_context ctx; 320 | 321 | sha2_starts( &ctx ); 322 | sha2_update( &ctx, input, ilen ); 323 | sha2_finish( &ctx, output ); 324 | 325 | memset(&ctx, 0, sizeof(sha2_context)); 326 | } 327 | -------------------------------------------------------------------------------- /sha2.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file sha2.h 3 | * 4 | * Copyright (C) 2011, Con Kolivas 5 | * Copyright (C) 2006-2010, Brainspark B.V. 6 | * 7 | * This file is part of PolarSSL (http://www.polarssl.org) 8 | * Lead Maintainer: Paul Bakker 9 | * 10 | * All rights reserved. 11 | * 12 | * This program is free software; you can redistribute it and/or modify 13 | * it under the terms of the GNU General Public License as published by 14 | * the Free Software Foundation; either version 2 of the License, or 15 | * (at your option) any later version. 16 | * 17 | * This program is distributed in the hope that it will be useful, 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 | * GNU General Public License for more details. 21 | * 22 | * You should have received a copy of the GNU General Public License along 23 | * with this program; if not, write to the Free Software Foundation, Inc., 24 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 25 | */ 26 | #ifndef POLARSSL_SHA2_H 27 | #define POLARSSL_SHA2_H 28 | 29 | /** 30 | * \brief SHA-256 context structure 31 | */ 32 | typedef struct 33 | { 34 | uint32_t total[2]; /*!< number of bytes processed */ 35 | uint32_t state[8]; /*!< intermediate digest state */ 36 | unsigned char buffer[64]; /*!< data block being processed */ 37 | 38 | unsigned char ipad[64]; /*!< HMAC: inner padding */ 39 | unsigned char opad[64]; /*!< HMAC: outer padding */ 40 | } 41 | sha2_context; 42 | 43 | #ifdef __cplusplus 44 | extern "C" { 45 | #endif 46 | 47 | /** 48 | * \brief SHA-256 context setup 49 | * 50 | * \param ctx context to be initialized 51 | */ 52 | void sha2_starts( sha2_context *ctx); 53 | 54 | /** 55 | * \brief SHA-256 process buffer 56 | * 57 | * \param ctx SHA-256 context 58 | * \param input buffer holding the data 59 | * \param ilen length of the input data 60 | */ 61 | void sha2_update( sha2_context *ctx, const unsigned char *input, int ilen ); 62 | 63 | /** 64 | * \brief SHA-256 final digest 65 | * 66 | * \param ctx SHA-256 context 67 | * \param output SHA-256 checksum result 68 | */ 69 | void sha2_finish( sha2_context *ctx, unsigned char output[32] ); 70 | 71 | /** 72 | * \brief Output = SHA-256( input buffer ) 73 | * 74 | * \param input buffer holding the data 75 | * \param ilen length of the input data 76 | * \param output SHA-256 checksum result 77 | */ 78 | void sha2( const unsigned char *input, int ilen, 79 | unsigned char output[32]); 80 | 81 | 82 | void sha2_process( sha2_context *ctx, const unsigned char data[64] ); 83 | 84 | #ifdef __cplusplus 85 | } 86 | #endif 87 | 88 | #endif /* sha2.h */ 89 | 90 | -------------------------------------------------------------------------------- /spi.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #include "spi.h" 12 | 13 | void *spi_vaddr, *gpio3_vaddr, *gpio2_vaddr; 14 | McSPI spi_dev; 15 | #if SPI_USE_INTERRUPT 16 | static irqreturn_t mspi_interrupt(int irq, void *dev_id) 17 | { 18 | McSPI *p_spi_dev = (McSPI *)dev_id; 19 | unsigned int intCode = 0; 20 | uint8_t data = 0; 21 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 22 | //printk_ratelimited(KERN_ERR "enter spi intterrupt\n"); 23 | //printk_ratelimited(KERN_ERR "11OMAP2_MCSPI_IRQSTATUS{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS)); 24 | //printk_ratelimited(KERN_ERR "11OMAP2_MCSPI_CHSTAT0{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 25 | intCode = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 26 | //& ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 27 | //disable tx0_empty interrupt 28 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) & (~ (EOW | TX0_EMPTY)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 29 | //clear tx empty 30 | iowrite32(EOW | 0x0f, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 31 | #if 0 32 | //no empty 33 | while( 00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5))) 34 | { 35 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 36 | if(data++ >32) 37 | { 38 | printk_ratelimited(KERN_ERR "detect spi rx err\n"); 39 | break; 40 | } 41 | } 42 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 43 | #endif 44 | //printk_ratelimited(KERN_ERR "OMAP2_MCSPI_CHSTAT0{%#x}spi_dev.rev_len{%d}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0), spi_dev.rev_len); 45 | //wake_up_interruptible(&p_spi_dev->wait_transfer_complete); 46 | spi_dev.have_wake_up = true; 47 | wake_up_interruptible(&spi_dev.wait_transfer_complete); 48 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 49 | return IRQ_HANDLED; 50 | } 51 | #endif 52 | void spi_init(void) 53 | { 54 | void *cm_per_vaddr, *ctl_md_vaddr; 55 | int32_t value32; 56 | int32_t i; 57 | int ret; 58 | //uint8_t value8 = 0x55; 59 | uint8_t rddata[0x110] = {0x55}, txdata[0x110] = {0x33}; 60 | uint16_t rx_len; 61 | cm_per_vaddr = ioremap_nocache(CM_PER_BASE, CM_PER_Size); 62 | iowrite32(0x02 , cm_per_vaddr + CM_PER_SPI1_CLKCTRL); //Enable clk 63 | iowrite32(0x02 , cm_per_vaddr + CM_PER_GPIO3_CLKCTRL); //Enable clk 64 | iowrite32(0x02 , cm_per_vaddr + CM_PER_GPIO2_CLKCTRL); //Enable clk 65 | printk_ratelimited("CM_PER_SPI1_CLKCTRL %#x\n", ioread32(cm_per_vaddr + CM_PER_SPI1_CLKCTRL)); 66 | while(ioread32(cm_per_vaddr + CM_PER_SPI1_CLKCTRL) & (0x03 << 16)) ; 67 | iounmap(cm_per_vaddr); 68 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 69 | iowrite32(PAD_REV | PAD_PULLUP | 0x3, ctl_md_vaddr + conf_mcasp0_fsx); //D0 MISO 70 | iowrite32(PAD_REV | PAD_PULLUP | 0x3, ctl_md_vaddr + conf_mcasp0_axr0); //D1 MOSI 71 | iowrite32(PAD_PULLUP | 0x3, ctl_md_vaddr + conf_mcasp0_ahclkr); //cs0 72 | iowrite32(PAD_REV | PAD_PULLUP | 0x3, ctl_md_vaddr + conf_mcasp0_aclkx); //clk need input to feedback 73 | //iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + conf_mcasp0_fsr); //GPIO3_19 74 | //iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + conf_mcasp0_ahclkx); //GPIO3_21 75 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8a0); //GPIO2_6 lcd data0 76 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8a8); //GPIO2_8 lcd data2 77 | #if defined S2 78 | iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x8a4); //GPIO2_7 lcd data1 79 | #endif 80 | iounmap(ctl_md_vaddr); 81 | gpio2_vaddr = ioremap_nocache(GPIO2_BASE, GPIO2_SIZE); 82 | value32 = ioread32(gpio2_vaddr + GPIO_OE); 83 | iowrite32(value32 & (~(0x01 << 6)), gpio2_vaddr + GPIO_OE); //set output 84 | value32 = ioread32(gpio2_vaddr + GPIO_OE); 85 | iowrite32(value32 & (~(0x01 << 8)), gpio2_vaddr + GPIO_OE); //set output 86 | #if defined S2 87 | value32 = ioread32(gpio2_vaddr + GPIO_OE); 88 | iowrite32(value32 & (~(0x01 << 7)), gpio2_vaddr + GPIO_OE); //set output 89 | #endif 90 | spi_vaddr = ioremap_nocache(McSpi1_Base, McSpi1_Size); 91 | printk_ratelimited("spi_vaddr %#x\n", (uint32_t)spi_vaddr); 92 | printk_ratelimited("version %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_REVISION)); 93 | //reset don't sleep 94 | iowrite32((0x01<<3) | (0x01 << 1), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_SYSSCTL); 95 | value32 = 0; 96 | while((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_SYSSTATUS) & 0x01) == 0) 97 | { 98 | if(value32++ == 0xffff) 99 | { 100 | printk_ratelimited("Reset spi module timeout\n"); 101 | break; 102 | } 103 | } 104 | printk_ratelimited("OMAP2_MCSPI_SYSSTATUS %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_SYSSTATUS)); 105 | //4针模式（CLK，D0，D1，CS）,即CS使能 106 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL); 107 | iowrite32(value32 & (~(0x01 << 1)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL); 108 | //主模式 109 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL); 110 | iowrite32(value32 & (~(0x01 << 2)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL); 111 | //配置单通道模式，发送/接收模式 112 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL); 113 | iowrite32(value32 | (0x01 << 0), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL);//单通道 114 | printk_ratelimited("OMAP2_MCSPI_MODULCTRL %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_MODULCTRL)); 115 | //set dir: clk out, d0 MISO, d1 MOSI 116 | //value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_SYST); 117 | //iowrite32((value32 & (~(0x01 << 10))) | (0x01 << 8) | (0x01 << 5), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_SYST); 118 | 119 | //DEP1 transmission IS=d0 120 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 121 | iowrite32((value32 & (~(0x01 << 18)) & (~(0x01 << 17))) | (0x01 << 16), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 122 | //spi总线时钟配置: 1 =2 分频1clk精度mode1: clk平时高，上升沿采样 123 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 124 | iowrite32(((((value32 & (~(0x0f << 2))) | (0x01 << 2)) /*& (~(0x03 << 0))*/ & (~(0x01 << 29))) & (~(0x03 << 0)))|(0x01 << 0), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 125 | //mcspi字长 8bit 126 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 127 | iowrite32(value32 | (0x07 << 7), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 128 | //spics 极性low ative TCS=0.5 129 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 130 | iowrite32(value32 | (0x00 << 25) | (0x01 << 6), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 131 | //使能FIFO Transmit/receive modes 132 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 133 | iowrite32((value32 | (0x03 << 27)) & (~(0x03 << 12)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 134 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 135 | printk_ratelimited("OMAP2_MCSPI_CHCONF0 %#x\n", value32); 136 | //iowrite32((27<<8) | (27), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL); 137 | //interrupt rx full 138 | iowrite32((31<<8) | (31), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL); 139 | #if SPI_USE_INTERRUPT 140 | spi_dev.irq = 125 + NR_IRQS_LEGACY; 141 | if (ret = request_irq(spi_dev.irq, mspi_interrupt, IRQF_TRIGGER_LOW, "mspi", (void*)&spi_dev)) { 142 | printk_ratelimited(KERN_ERR 143 | "mspi: Failed req IRQ %d, error{%d}\n", spi_dev.irq, ret); 144 | } 145 | mutex_init(&spi_dev.transfer_lock); 146 | init_waitqueue_head(&spi_dev.wait_transfer_complete); 147 | printk_ratelimited("Initial OMAP2_MCSPI_IRQSTATUS{%#x}OMAP2_MCSPI_IRQENABLE{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS), 148 | ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE)); 149 | #endif 150 | #if 0 151 | iowrite32(CH_ENA, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 152 | printk_ratelimited("OMAP2_MCSPI_CHCTRL0 %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0)); 153 | //cs low FORCE==1 154 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) | (0x01 << 20), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 155 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 156 | printk_ratelimited("OMAP2_MCSPI_CHCONF0 %#x\n", value32); 157 | printk_ratelimited( "000status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 158 | for(i=0; i< 0x0ff; i++) 159 | { 160 | iowrite32(0x01<<19, gpio3_vaddr + GPIO_SETDATAOUT); 161 | iowrite32(i, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 162 | //printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 163 | //wait rev 164 | cnt = 0; 165 | while( 00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<0))) 166 | { 167 | if(cnt++ == 0xff) 168 | { 169 | printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 170 | break; 171 | } 172 | } 173 | rddata[i]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 174 | //printk_ratelimited("OMAP2_MCSPI_RX0 %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0)); 175 | iowrite32(0x01<<19, gpio3_vaddr + GPIO_CLEARDATAOUT); 176 | } 177 | for(i=0; i< 0x0ff; i++) 178 | { 179 | if(0 == (i%16)) 180 | printk_ratelimited("\n 0x%02x: ", i); 181 | printk_ratelimited("%#x, ", rddata[i]); 182 | } 183 | //cs high 184 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) & (~(0x01 << 20)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 185 | iowrite32(0, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 186 | #endif 187 | //while(1) 188 | { 189 | for(i= 0; i< 0x100; i++) 190 | { 191 | txdata[i] = i; 192 | } 193 | i = spi_tranfer(0x55, txdata, 52, rddata, &rx_len); 194 | } 195 | } 196 | void spi_close(void) 197 | { 198 | void *ctl_md_vaddr; 199 | iowrite32(0, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 200 | ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size); 201 | iowrite32(PAD_PULL_DIS | 0x7, ctl_md_vaddr + conf_mcasp0_fsx); //D0 MISO 202 | iounmap(ctl_md_vaddr); 203 | #if SPI_USE_INTERRUPT 204 | free_irq(spi_dev.irq, &spi_dev); 205 | #endif 206 | } 207 | #if 0 208 | int spi_tranfer(uint8_t cmd, uint8_t *tx_data, uint16_t tx_len, uint8_t *rx_data, uint16_t *rx_len) 209 | { 210 | uint16_t i, j; 211 | uint32_t cnt; 212 | int32_t value32; 213 | uint16_t h_tx_len; 214 | unsigned long flags; 215 | iowrite32(CH_ENA, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 216 | //printk_ratelimited("OMAP2_MCSPI_CHCTRL0 %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0)); 217 | //cs low FORCE==1 218 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) | (0x01 << 20), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 219 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 220 | //printk_ratelimited("OMAP2_MCSPI_CHCONF0 %#x\n", value32); 221 | //printk_ratelimited( "000status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 222 | #if SPI_USE_INTERRUPT 223 | spi_dev.p_rx = rx_data; 224 | spi_dev.p_tx = tx_data; 225 | spi_dev.length = tx_len; 226 | spi_dev.rev_len = 0; 227 | spi_dev.have_wake_up = false; 228 | h_tx_len = tx_len < 32 ? tx_len: tx_len - 32; 229 | while((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5)) == 0) 230 | { 231 | spi_dev.p_rx[spi_dev.rev_len]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 232 | } 233 | cnt = 0; 234 | while((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<4)) != 0) 235 | { 236 | if(cnt++ == 0xff) 237 | { 238 | printk_ratelimited(KERN_ERR "wait tx fifo empty timeout\n"); 239 | return 0; 240 | } 241 | } 242 | local_irq_save(flags); 243 | for(i = 0; i < 32; i++)//32字节 FIFO, 数据长度52字节 244 | { 245 | iowrite32(tx_data[i], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 246 | /* 247 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<4)) != 0) 248 | { 249 | printk_ratelimited(KERN_ERR "fifo full status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 250 | } 251 | if(i == (tx_len - 1)) //total < 32 252 | break; 253 | */ 254 | } 255 | //while((spi_dev.rev_len < tx_len ) && (spi_dev.rev_len < (tx_len - 32))) 256 | while(spi_dev.rev_len < h_tx_len) 257 | { 258 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5)) == 0) 259 | { 260 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 261 | cnt = 0; 262 | } 263 | else if(cnt++ == 0xff) 264 | { 265 | printk_ratelimited(KERN_ERR "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 266 | break; 267 | } 268 | } 269 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 270 | if(spi_dev.rev_len != tx_len) 271 | { 272 | for(; i< tx_len; i++) 273 | { 274 | iowrite32(tx_data[i], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 275 | /* 276 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<4)) != 0) 277 | { 278 | printk_ratelimited(KERN_ERR "fifo full status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 279 | } 280 | */ 281 | } 282 | //clear tx empty 283 | iowrite32(0x0f, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 284 | //enable interrupt 285 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) | (TX0_EMPTY), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 286 | local_irq_restore(flags); 287 | iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 288 | //printk_ratelimited(KERN_ERR "OMAP2_MCSPI_IRQENABLE{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS),\ 289 | ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE)); 290 | #if 0 291 | if(spi_dev.have_wake_up == false) 292 | { 293 | //if(0 == interruptible_sleep_on_timeout(&spi_dev.wait_transfer_complete, 10 * HZ/1000))//10ms 294 | if(0 == wait_event_interruptible_timeout(&spi_dev.wait_transfer_complete, spi_dev.have_wake_up == true, 10 * HZ/1000))//10ms 295 | { 296 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 297 | printk_ratelimited(KERN_ERR "spi transfer timeout spi_dev.rev_len{%d}\n", spi_dev.rev_len); 298 | //*rx_len = 0; 299 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 300 | } 301 | } 302 | #endif 303 | if(0 == wait_event_interruptible_timeout(spi_dev.wait_transfer_complete, spi_dev.have_wake_up == true, 10 * HZ/1000))//10ms 304 | { 305 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 306 | printk_ratelimited(KERN_ERR "spi transfer timeout spi_dev.rev_len{%d}\n", spi_dev.rev_len); 307 | //*rx_len = 0; 308 | iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 309 | } 310 | *rx_len = spi_dev.rev_len; 311 | //printk_ratelimited(KERN_ERR "tx_len %d\n", i); 312 | } 313 | else 314 | { 315 | local_irq_restore(flags); 316 | *rx_len = tx_len; 317 | } 318 | #elif 1 319 | //iowrite32(0x01<<19, gpio3_vaddr + GPIO_SETDATAOUT); 320 | //clear RX0_FULL 321 | iowrite32(0x01<<2, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 322 | for(i = 0, j =0; i< tx_len; i++) 323 | { 324 | iowrite32(tx_data[i], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 325 | //printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 326 | //receive fifo almost full 327 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS) & (0x01<<2))) 328 | { 329 | //no empty 330 | while( 00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5))) 331 | { 332 | rx_data[j++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 333 | // transfer fifo almost empty 334 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<3))) 335 | { 336 | break; 337 | } 338 | } 339 | iowrite32(0x01<<2, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 340 | } 341 | //printk_ratelimited("OMAP2_MCSPI_RX0 %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0)); 342 | } 343 | cnt = 0; 344 | while(j < tx_len) 345 | { 346 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<0))) 347 | { 348 | rx_data[j++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 349 | cnt = 0; 350 | } 351 | else if(cnt++ == 0xff) 352 | { 353 | printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 354 | break; 355 | } 356 | } 357 | *rx_len = i; 358 | //iowrite32(0x01<<19, gpio3_vaddr + GPIO_CLEARDATAOUT); 359 | #else 360 | i = 0; 361 | iowrite32(cmd, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 362 | //printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 363 | //wait rev 364 | cnt = 0; 365 | while( 00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<0))) 366 | { 367 | if(cnt++ == 0xff) 368 | { 369 | printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 370 | break; 371 | } 372 | } 373 | rx_data[i]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 374 | //tx rx data; 375 | //printk_ratelimited("tx_len %#x\n", tx_len); 376 | for(i = 1; i< (tx_len + 1); i++) 377 | { 378 | iowrite32(0x01<<19, gpio3_vaddr + GPIO_SETDATAOUT); 379 | iowrite32(tx_data[i - 1], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 380 | //printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 381 | //wait rev 382 | cnt = 0; 383 | while( 00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<0))) 384 | { 385 | if(cnt++ == 0xff) 386 | { 387 | printk_ratelimited( "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 388 | break; 389 | } 390 | } 391 | rx_data[i]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 392 | //printk_ratelimited("OMAP2_MCSPI_RX0 %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0)); 393 | iowrite32(0x01<<19, gpio3_vaddr + GPIO_CLEARDATAOUT); 394 | } 395 | *rx_len = i; 396 | #endif 397 | //cs high 398 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) & (~(0x01 << 20)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 399 | iowrite32(0, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 400 | #if 0//SPI_USE_INTERRUPT 401 | printk_ratelimited(KERN_ERR "rx_len %#x\n", *rx_len); 402 | for(i = 0; i < *rx_len; i++) 403 | { 404 | if(0 == (i%16)) 405 | printk_ratelimited(KERN_ERR "\n 0x%02x: ", i); 406 | printk_ratelimited(KERN_ERR "0x%02x, ", rx_data[i]); 407 | } 408 | printk_ratelimited(KERN_ERR "\n"); 409 | #endif 410 | #if 0 411 | if(*rx_len != (tx_len + 1))// 1 cmd 412 | return -1; 413 | #else 414 | if(*rx_len != tx_len) 415 | { 416 | printk_ratelimited(KERN_ERR "SPI Transfer error\n"); 417 | return -1; 418 | } 419 | #endif 420 | return *rx_len; 421 | } 422 | #else 423 | int spi_tranfer(uint8_t cmd, uint8_t *tx_data, uint16_t tx_len, uint8_t *rx_data, uint16_t *rx_len) 424 | { 425 | uint16_t i, j; 426 | uint32_t cnt, cnt1; 427 | int32_t value32; 428 | uint16_t h_tx_len; 429 | unsigned long flags; 430 | int ret; 431 | mutex_lock(&spi_dev.transfer_lock); 432 | spi_dev.have_wake_up = false; 433 | switch(cmd) 434 | { 435 | case 1: //query 436 | spi_dev.p_rx = rx_data; 437 | spi_dev.p_tx = tx_data; 438 | spi_dev.length = tx_len; 439 | spi_dev.rev_len = 0; 440 | spi_dev.have_wake_up = false; 441 | h_tx_len = tx_len < 32 ? tx_len: tx_len - 32; 442 | //使能Transmit and rx FIFO 443 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 444 | value32 &= ~((0x03<<27) | (0x03<<12)); 445 | iowrite32(value32 | (0x03 << 27) | (0x00 << 12), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 446 | iowrite32((tx_len << 16) | (31<<8) | 31, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL); 447 | //cs low FORCE==1 448 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) | (0x01 << 20), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 449 | iowrite32(EOW | 0x0f, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 450 | //enable EOW interrupt 451 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) | (EOW), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 452 | iowrite32(CH_ENA, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 453 | local_irq_save(flags); 454 | for(i = 0; i < 32; i++)//32字节 FIFO, 数据长度52字节 455 | //for(i = 0; i < h_tx_len; i++) 456 | { 457 | iowrite32(tx_data[i], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 458 | } 459 | while(spi_dev.rev_len < h_tx_len) 460 | { 461 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5)) == 0) 462 | { 463 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 464 | cnt = 0; 465 | } 466 | else if(cnt++ == 0xff) 467 | { 468 | printk_ratelimited(KERN_ERR "status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 469 | break; 470 | } 471 | } 472 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 473 | if(spi_dev.rev_len != tx_len) 474 | { 475 | //iowrite32((31<<8) | h_tx_len, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL); 476 | for(; i< tx_len; i++) 477 | { 478 | iowrite32(tx_data[i], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 479 | 480 | if((ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<4)) != 0) 481 | { 482 | printk_ratelimited(KERN_ERR "fifo full status %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 483 | } 484 | /* */ 485 | } 486 | local_irq_restore(flags); 487 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 488 | //printk_ratelimited(KERN_ERR "OMAP2_MCSPI_IRQENABLE{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS),\ 489 | ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE)); 490 | if(0 == wait_event_interruptible_timeout(spi_dev.wait_transfer_complete, spi_dev.have_wake_up == true, 10 * HZ/1000))//10ms 491 | { 492 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) & (~ (EOW|TX0_EMPTY)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 493 | //iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 494 | cnt = 0; 495 | while(00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5))) 496 | { 497 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 498 | if(cnt++ >32) 499 | { 500 | printk_ratelimited(KERN_ERR "detect spi rx err\n"); 501 | break; 502 | } 503 | } 504 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 505 | if(spi_dev.have_wake_up == false) 506 | printk_ratelimited(KERN_ERR "22spi transfer timeout IRQSTATUS{%#x}XFERLEVEL{%#x}tx_len{%d}CHSTAT0{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS), 507 | ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL), i ,ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 508 | else 509 | printk_ratelimited("22wk up err\n"); 510 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) & (~EOW), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 511 | //*rx_len = 0; 512 | //iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 513 | } 514 | else 515 | { 516 | cnt = 0; 517 | cnt1 = 0; 518 | while(1) 519 | { 520 | //no empty 521 | while(00 == (ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0) & (0x01<<5))) 522 | { 523 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 524 | if(cnt++ >32) 525 | { 526 | printk_ratelimited(KERN_ERR "detect spi rx err\n"); 527 | break; 528 | } 529 | cnt1 = 0; 530 | } 531 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0); 532 | //发送接收完成 533 | if((value32 & (TXFFE | RXFFE)) == (TXFFE | RXFFE)) 534 | { 535 | spi_dev.p_rx[spi_dev.rev_len++]= ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_RX0); 536 | break; 537 | } 538 | if(cnt1++ >10000) 539 | { 540 | printk_ratelimited(KERN_ERR "detect spi rx tx empty err{%#x}\n", value32); 541 | break; 542 | } 543 | } 544 | } 545 | *rx_len = spi_dev.rev_len; 546 | if(*rx_len != tx_len) 547 | { 548 | printk_ratelimited(KERN_ERR "SPI Transfer error *rx_len{%d}\n", *rx_len); 549 | while(*rx_len < tx_len) 550 | { 551 | spi_dev.p_rx[*rx_len++] = 0; 552 | } 553 | } 554 | } 555 | else 556 | { 557 | local_irq_restore(flags); 558 | *rx_len = tx_len; 559 | } 560 | ret = *rx_len; 561 | /* 562 | printk_ratelimited(KERN_ERR "rx_len %#x\n", *rx_len); 563 | for(i = 0; i < *rx_len; i++) 564 | { 565 | if(0 == (i%16)) 566 | printk_ratelimited(KERN_ERR "\n 0x%02x: ", i); 567 | printk_ratelimited(KERN_ERR "0x%02x, ", rx_data[i]); 568 | } 569 | printk_ratelimited(KERN_ERR "\n"); 570 | */ 571 | break; 572 | case 0: //to asic cmd 573 | default: //tw 574 | ret = -1; //don't care return data 575 | //使能only Transmit FIFO 576 | value32 = ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 577 | value32 &= ~((0x03<<27) | (0x03<<12)); 578 | iowrite32((value32 | (0x01 << 27)) | (0x02 << 12), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 579 | iowrite32(((tx_len-1)<<16) | (tx_len-1), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL); 580 | //cs low FORCE==1 581 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) | (0x01 << 20), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 582 | iowrite32(EOW | 0x0f, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS); 583 | //enable EOW interrupt 584 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) | (EOW), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 585 | iowrite32(CH_ENA, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 586 | //printk_ratelimited("OMAP2_MCSPI_CHCTRL0 %#x\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0)); 587 | local_irq_save(flags); 588 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT); 589 | for(i = 0; i < tx_len; i++) 590 | { 591 | iowrite32(tx_data[i], spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_TX0); 592 | } 593 | //iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT); 594 | local_irq_restore(flags); 595 | if(cmd == 0) 596 | udelay(10); 597 | //printk_ratelimited("tx_len = %d\n", tx_len); 598 | if(0 == wait_event_interruptible_timeout(spi_dev.wait_transfer_complete, spi_dev.have_wake_up == true, 10 * HZ/1000))//10ms 599 | { 600 | //iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT); 601 | if(spi_dev.have_wake_up == false) 602 | printk_ratelimited(KERN_ERR "111spi transfer timeout IRQSTATUS{%#x}IRQENABLE{%#x}XFERLEVEL{%#x}CHSTAT0{%#x}\n", ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQSTATUS), 603 | ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE),ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_XFERLEVEL),ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHSTAT0)); 604 | else 605 | printk_ratelimited("11wk up err\n"); 606 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE) & (~EOW), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_IRQENABLE); 607 | //iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT); 608 | } 609 | break; 610 | } 611 | //cs high 612 | iowrite32(ioread32(spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0) & (~(0x01 << 20)), spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCONF0); 613 | iowrite32(0, spi_vaddr + OMAP2_MCSPI_OFFSET + OMAP2_MCSPI_CHCTRL0); 614 | mutex_unlock(&spi_dev.transfer_lock); 615 | return ret; 616 | } 617 | 618 | #endif 619 | -------------------------------------------------------------------------------- /spi.h: -------------------------------------------------------------------------------- 1 | #ifndef __OMAP2_SPI_H__ 2 | #define __OMAP2_SPI_H__ 3 | 4 | #define CM_PER_BASE 0x44E00000 5 | #define CM_PER_Size 1024 //1K 6 | 7 | #define CM_PER_SPI1_CLKCTRL 0x50 8 | #define CM_PER_GPIO2_CLKCTRL 0xB0 9 | #define CM_PER_GPIO3_CLKCTRL 0xB4 10 | 11 | #define CONTROL_MODULE_BASE 0x44E10000 12 | #define CONTROL_MODULE_Size (128 * 1024) //128K 13 | #define conf_uart0_ctsn 0x968 //SP1 D0 mode=4 14 | #define conf_uart0_rtsn 0x96c //SP1 D1 mode=4 15 | #define conf_uart1_ctsn 0x978 //SP1 CS0 mode=4 16 | #define conf_uart1_rtsn 0x97c //SP1 CS1 mode=4 17 | #define conf_mcasp0_aclkx 0x990 //SP1 clk mode=3 18 | #define conf_mcasp0_fsx 0x994 //SP1 d0 mode=3 19 | #define conf_mcasp0_axr0 0x998 //SP1 d1 mode=3 20 | #define conf_mcasp0_ahclkr 0x99c //SP1 CS0 mode=3 21 | #define conf_mcasp0_fsr 0x9a4 //GPIO3_19 mode=7 22 | #define conf_mcasp0_ahclkx 0x9ac //GPIO3_21 mode=7 23 | 24 | 25 | #define PAD_REV (0x01<<5) 26 | #define PAD_PULL_DIS (0x01<<3) 27 | #define PAD_PULLUP (0x02<<3) 28 | #define PAD_PULLDONE (0x00<<3) 29 | 30 | #define GPIO0_BASE 0x44e07000 31 | #define GPIO0_SIZE 0x0fff //4K 32 | #define GPIO1_BASE 0x4804C000 33 | #define GPIO1_SIZE 0x0fff //4K 34 | 35 | 36 | #define GPIO2_BASE 0x481AC000 37 | #define GPIO2_SIZE 0x0fff //4K 38 | 39 | #define GPIO3_BASE 0x481AE000 40 | #define GPIO3_SIZE 0x0fff //4K 41 | #define GPIO_OE 0x134 42 | #define GPIO_DATAIN 0x138 43 | #define GPIO_DATAOUT 0x13C 44 | #define GPIO_CLEARDATAOUT 0x190 45 | #define GPIO_SETDATAOUT 0x194 46 | #define McSpi1_Base 0x481A0000 47 | #define McSpi1_Size 0x0fff //4K 48 | 49 | #define OMAP2_MCSPI_MAX_FREQ 48000000 50 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 51 | 52 | #define OMAP2_MCSPI_REVISION 0x00 53 | #define OMAP2_MCSPI_OFFSET 0x100 54 | #define OMAP2_MCSPI_SYSSCTL 0x10 55 | #define OMAP2_MCSPI_SYSSTATUS 0x14 56 | #define OMAP2_MCSPI_IRQSTATUS 0x18 57 | #define TX0_EMPTY (0x01<<0) 58 | #define RX0_FULL (0x01<<2) 59 | #define EOW (0x01<<17) 60 | #define OMAP2_MCSPI_IRQENABLE 0x1c 61 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 62 | #define OMAP2_MCSPI_SYST 0x24 63 | #define SPIEN_0 (0x01 << 0) 64 | #define OMAP2_MCSPI_MODULCTRL 0x28 65 | #define OMAP2_MCSPI_XFERLEVEL 0x7c 66 | 67 | /* per-channel banks, 0x14 bytes each, first is: */ 68 | #define OMAP2_MCSPI_CHCONF0 0x2c 69 | #define OMAP2_MCSPI_CHSTAT0 0x30 70 | #define TXFFE (0x01<<3) 71 | #define RXFFE (0x01<<5) 72 | #define OMAP2_MCSPI_CHCTRL0 0x34 73 | #define CH_ENA 0x01 74 | #define OMAP2_MCSPI_TX0 0x38 75 | #define OMAP2_MCSPI_RX0 0x3c 76 | 77 | typedef struct __mspi_struct 78 | { 79 | int irq; 80 | void *spi_vaddr; 81 | unsigned char *p_tx; 82 | unsigned char *p_rx; 83 | unsigned int length; 84 | unsigned int rev_len; 85 | struct mutex transfer_lock; 86 | bool have_wake_up; 87 | wait_queue_head_t wait_transfer_complete; 88 | 89 | }McSPI; 90 | 91 | #define SPI_USE_INTERRUPT 1 92 | 93 | extern void *gpio3_vaddr ,*gpio2_vaddr; 94 | extern void spi_init(void); 95 | void spi_close(void); 96 | extern int spi_tranfer(uint8_t cmd, uint8_t *tx_data, uint16_t tx_len, uint8_t *rx_data, uint16_t *rx_len); 97 | #endif 98 | 99 | --------------------------------------------------------------------------------