├── .gitignore
├── Binary
├── arm-elf-objcopy.exe
├── axftobin.bat
├── cygwin1.dll
├── hex2bin.exe
└── hextobin.bat
├── CORE
├── core_cm3.c
├── core_cm3.h
├── startup_stm32f10x_cl.s
├── startup_stm32f10x_hd.s
├── startup_stm32f10x_hd_vl.s
├── startup_stm32f10x_ld.s
├── startup_stm32f10x_ld_vl.s
├── startup_stm32f10x_md.s
├── startup_stm32f10x_md_vl.s
└── startup_stm32f10x_xl.s
├── IAP
├── inc
│ ├── common.h
│ ├── iap.h
│ ├── iap_config.h
│ ├── stmflash.h
│ └── ymodem.h
└── src
│ ├── common.c
│ ├── iap.c
│ ├── stmflash.c
│ └── ymodem.c
├── MDK-ARM
├── DebugConfig
│ ├── STM32-IAP_CL_STM32F107VC_1.0.0.dbgconf
│ ├── STM32-IAP_HD_VL_STM32F100ZE_1.0.0.dbgconf
│ └── STM32-IAP_MD_STM32F103C8_1.0.0.dbgconf
├── EventRecorderStub.scvd
├── IAP-UART.uvguix.Haven
├── IAP-UART.uvguix.user
├── IAP-UART.uvguix.xiebin
├── IAP-UART.uvopt
├── IAP-UART.uvoptx
├── IAP-UART.uvprojx
├── JLinkSettings.ini
├── OUTPUT
│ ├── STM32-IAP_CL
│ │ ├── STM32-IAP_CL.bin
│ │ ├── STM32-IAP_CL.hex
│ │ └── STM32-IAP_CL.sct
│ ├── STM32-IAP_HD
│ │ ├── STM32-IAP_HD.bin
│ │ └── STM32-IAP_HD.hex
│ ├── STM32-IAP_HD_VL
│ │ ├── STM32-IAP_HD_VL.bin
│ │ └── STM32-IAP_HD_VL.hex
│ ├── STM32-IAP_MD
│ │ ├── STM32-IAP_MD.bin
│ │ ├── STM32-IAP_MD.hex
│ │ └── STM32-IAP_MD.sct
│ ├── STM32-IAP_MD_VL
│ │ ├── STM32-IAP_MD_VL.bin
│ │ └── STM32-IAP_MD_VL.hex
│ └── STM32-IAP_XL
│ │ ├── STM32-IAP_XL.bin
│ │ └── STM32-IAP_XL.hex
├── RTE
│ ├── _STM32-IAP_CL
│ │ └── RTE_Components.h
│ ├── _STM32-IAP_HD_VL
│ │ └── RTE_Components.h
│ └── _STM32-IAP_MD
│ │ └── RTE_Components.h
├── main.c
├── stm32f10x.h
├── stm32f10x_conf.h
├── stm32f10x_it.c
├── stm32f10x_it.h
├── system_stm32f10x.c
└── system_stm32f10x.h
├── README.md
├── STM32F10x_FWLib
├── inc
│ ├── misc.h
│ ├── stm32f10x_adc.h
│ ├── stm32f10x_bkp.h
│ ├── stm32f10x_can.h
│ ├── stm32f10x_cec.h
│ ├── stm32f10x_crc.h
│ ├── stm32f10x_dac.h
│ ├── stm32f10x_dbgmcu.h
│ ├── stm32f10x_dma.h
│ ├── stm32f10x_exti.h
│ ├── stm32f10x_flash.h
│ ├── stm32f10x_fsmc.h
│ ├── stm32f10x_gpio.h
│ ├── stm32f10x_i2c.h
│ ├── stm32f10x_iwdg.h
│ ├── stm32f10x_pwr.h
│ ├── stm32f10x_rcc.h
│ ├── stm32f10x_rtc.h
│ ├── stm32f10x_sdio.h
│ ├── stm32f10x_spi.h
│ ├── stm32f10x_tim.h
│ ├── stm32f10x_usart.h
│ └── stm32f10x_wwdg.h
└── src
│ ├── misc.c
│ ├── stm32f10x_adc.c
│ ├── stm32f10x_bkp.c
│ ├── stm32f10x_can.c
│ ├── stm32f10x_cec.c
│ ├── stm32f10x_crc.c
│ ├── stm32f10x_dac.c
│ ├── stm32f10x_dbgmcu.c
│ ├── stm32f10x_dma.c
│ ├── stm32f10x_exti.c
│ ├── stm32f10x_flash.c
│ ├── stm32f10x_fsmc.c
│ ├── stm32f10x_gpio.c
│ ├── stm32f10x_i2c.c
│ ├── stm32f10x_iwdg.c
│ ├── stm32f10x_pwr.c
│ ├── stm32f10x_rcc.c
│ ├── stm32f10x_rtc.c
│ ├── stm32f10x_sdio.c
│ ├── stm32f10x_spi.c
│ ├── stm32f10x_tim.c
│ ├── stm32f10x_usart.c
│ └── stm32f10x_wwdg.c
└── clear.bat
/.gitignore:
--------------------------------------------------------------------------------
1 | # Prerequisites
2 | *.d
3 | *.uvgui.*
4 | JLinkSettings.ini
5 |
6 | # Object files
7 | *.o
8 | *.ko
9 | *.obj
10 | *.elf
11 | *.crf
12 | *.dep
13 | *.htm
14 | *.lnp
15 |
16 | # Linker output
17 | *.ilk
18 | *.map
19 | *.exp
20 |
21 | # Precompiled Headers
22 | *.gch
23 | *.pch
24 |
25 | # Libraries
26 | *.a
27 | *.la
28 | *.lo
29 |
30 | # Shared objects (inc. Windows DLLs)
31 | #*.dll
32 | *.so
33 | *.so.*
34 | *.dylib
35 |
36 | # Executables
37 | #*.exe
38 | *.out
39 | *.app
40 | *.i*86
41 | *.x86_64
42 |
43 | # Debug files
44 | *.dSYM/
45 | *.su
46 | *.idb
47 | *.pdb
48 |
49 | # Kernel Module Compile Results
50 | *.mod*
51 | *.cmd
52 | .tmp_versions/
53 | modules.order
54 | Module.symvers
55 | Mkfile.old
56 | dkms.conf
57 | .vscode/ipch/
58 |
59 | # Keil Project
60 |
61 |
--------------------------------------------------------------------------------
/Binary/arm-elf-objcopy.exe:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/Binary/arm-elf-objcopy.exe
--------------------------------------------------------------------------------
/Binary/axftobin.bat:
--------------------------------------------------------------------------------
1 | @echo off
2 |
3 | if exist C:\Keil\ARM\BIN40\fromelf.exe (
4 | if exist .\..\MDK-ARM\STM32100B-EVAL\STM32100B-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\MDK-ARM\STM32100B-EVAL\STM32100B-EVAL.axf" --bin --output ".\STM32100B-EVAL_SysTick.bin")
5 | if exist .\..\MDK-ARM\STM3210C-EVAL\STM3210C-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\MDK-ARM\STM3210C-EVAL\STM3210C-EVAL.axf" --bin --output ".\STM3210C-EVAL_SysTick.bin")
6 | if exist .\..\MDK-ARM\STM3210B-EVAL\STM3210B-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\MDK-ARM\STM3210B-EVAL\STM3210B-EVAL.axf" --bin --output ".\STM3210B-EVAL_SysTick.bin")
7 | if exist .\..\MDK-ARM\STM3210E-EVAL\STM3210E-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\MDK-ARM\STM3210E-EVAL\STM3210E-EVAL.axf" --bin --output ".\STM3210E-EVAL_SysTick.bin")
8 | if exist .\..\MDK-ARM\STM3210E-EVAL_XL\STM3210E-EVAL_XL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\MDK-ARM\STM3210E-EVAL_XL\STM3210E-EVAL_XL.axf" --bin --output ".\STM3210E-EVAL_XL_SysTick.bin")
9 | if exist .\..\MDK-ARM\STM32100E-EVAL\STM32100E-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\MDK-ARM\STM32100E-EVAL\STM32100E-EVAL.axf" --bin --output ".\STM32100E-EVAL_SysTick.bin")
10 |
11 | )
12 |
13 | pause
14 |
15 |
--------------------------------------------------------------------------------
/Binary/cygwin1.dll:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/Binary/cygwin1.dll
--------------------------------------------------------------------------------
/Binary/hex2bin.exe:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/Binary/hex2bin.exe
--------------------------------------------------------------------------------
/Binary/hextobin.bat:
--------------------------------------------------------------------------------
1 | if exist .\..\MDK-ARM\OUTPUT\STM32-IAP_CL\*.hex (.\..\Binary\hex2bin.exe .\..\MDK-ARM\OUTPUT\STM32-IAP_CL\*.hex)
2 | if exist .\..\MDK-ARM\OUTPUT\STM32-IAP_HD\*.hex (.\..\Binary\hex2bin.exe .\..\MDK-ARM\OUTPUT\STM32-IAP_HD\*.hex)
3 | if exist .\..\MDK-ARM\OUTPUT\STM32-IAP_HD_VL\*.hex (.\..\Binary\hex2bin.exe .\..\MDK-ARM\OUTPUT\STM32-IAP_HD_VL\*.hex)
4 | if exist .\..\MDK-ARM\OUTPUT\STM32-IAP_MD\*.hex (.\..\Binary\hex2bin.exe .\..\MDK-ARM\OUTPUT\STM32-IAP_MD\*.hex)
5 | if exist .\..\MDK-ARM\OUTPUT\STM32-IAP_MD_VL\*.hex (.\..\Binary\hex2bin.exe .\..\MDK-ARM\OUTPUT\STM32-IAP_MD_VL\*.hex)
6 | if exist .\..\MDK-ARM\OUTPUT\STM32-IAP_XL\*.hex (.\..\Binary\hex2bin.exe .\..\MDK-ARM\OUTPUT\STM32-IAP_XL\*.hex)
7 | exit
8 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_ld.s:
--------------------------------------------------------------------------------
1 | ;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
2 | ;* File Name : startup_stm32f10x_ld.s
3 | ;* Author : MCD Application Team
4 | ;* Version : V3.3.0
5 | ;* Date : 10/15/2010
6 | ;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
7 | ;* toolchain.
8 | ;* This module performs:
9 | ;* - Set the initial SP
10 | ;* - Set the initial PC == Reset_Handler
11 | ;* - Set the vector table entries with the exceptions ISR address
12 | ;* - Configure the clock system
13 | ;* - Branches to __main in the C library (which eventually
14 | ;* calls main()).
15 | ;* After Reset the CortexM3 processor is in Thread mode,
16 | ;* priority is Privileged, and the Stack is set to Main.
17 | ;* <<< Use Configuration Wizard in Context Menu >>>
18 | ;*******************************************************************************
19 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
20 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
21 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
22 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
23 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
24 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
25 | ;*******************************************************************************
26 |
27 | ; Amount of memory (in bytes) allocated for Stack
28 | ; Tailor this value to your application needs
29 | ; Stack Configuration
30 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 | ;
32 |
33 | Stack_Size EQU 0x00000800
34 |
35 | AREA STACK, NOINIT, READWRITE, ALIGN=3
36 | Stack_Mem SPACE Stack_Size
37 | __initial_sp
38 |
39 |
40 | ; Heap Configuration
41 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 | ;
43 |
44 | Heap_Size EQU 0x00000200
45 |
46 | AREA HEAP, NOINIT, READWRITE, ALIGN=3
47 | __heap_base
48 | Heap_Mem SPACE Heap_Size
49 | __heap_limit
50 |
51 | PRESERVE8
52 | THUMB
53 |
54 |
55 | ; Vector Table Mapped to Address 0 at Reset
56 | AREA RESET, DATA, READONLY
57 | EXPORT __Vectors
58 | EXPORT __Vectors_End
59 | EXPORT __Vectors_Size
60 |
61 | __Vectors DCD __initial_sp ; Top of Stack
62 | DCD Reset_Handler ; Reset Handler
63 | DCD NMI_Handler ; NMI Handler
64 | DCD HardFault_Handler ; Hard Fault Handler
65 | DCD MemManage_Handler ; MPU Fault Handler
66 | DCD BusFault_Handler ; Bus Fault Handler
67 | DCD UsageFault_Handler ; Usage Fault Handler
68 | DCD 0 ; Reserved
69 | DCD 0 ; Reserved
70 | DCD 0 ; Reserved
71 | DCD 0 ; Reserved
72 | DCD SVC_Handler ; SVCall Handler
73 | DCD DebugMon_Handler ; Debug Monitor Handler
74 | DCD 0 ; Reserved
75 | DCD PendSV_Handler ; PendSV Handler
76 | DCD SysTick_Handler ; SysTick Handler
77 |
78 | ; External Interrupts
79 | DCD WWDG_IRQHandler ; Window Watchdog
80 | DCD PVD_IRQHandler ; PVD through EXTI Line detect
81 | DCD TAMPER_IRQHandler ; Tamper
82 | DCD RTC_IRQHandler ; RTC
83 | DCD FLASH_IRQHandler ; Flash
84 | DCD RCC_IRQHandler ; RCC
85 | DCD EXTI0_IRQHandler ; EXTI Line 0
86 | DCD EXTI1_IRQHandler ; EXTI Line 1
87 | DCD EXTI2_IRQHandler ; EXTI Line 2
88 | DCD EXTI3_IRQHandler ; EXTI Line 3
89 | DCD EXTI4_IRQHandler ; EXTI Line 4
90 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
91 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
92 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
93 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
94 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
95 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
96 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
97 | DCD ADC1_2_IRQHandler ; ADC1_2
98 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
99 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
100 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1
101 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE
102 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
103 | DCD TIM1_BRK_IRQHandler ; TIM1 Break
104 | DCD TIM1_UP_IRQHandler ; TIM1 Update
105 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
107 | DCD TIM2_IRQHandler ; TIM2
108 | DCD TIM3_IRQHandler ; TIM3
109 | DCD 0 ; Reserved
110 | DCD I2C1_EV_IRQHandler ; I2C1 Event
111 | DCD I2C1_ER_IRQHandler ; I2C1 Error
112 | DCD 0 ; Reserved
113 | DCD 0 ; Reserved
114 | DCD SPI1_IRQHandler ; SPI1
115 | DCD 0 ; Reserved
116 | DCD USART1_IRQHandler ; USART1
117 | DCD USART2_IRQHandler ; USART2
118 | DCD 0 ; Reserved
119 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
120 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
121 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
122 | __Vectors_End
123 |
124 | __Vectors_Size EQU __Vectors_End - __Vectors
125 |
126 | AREA |.text|, CODE, READONLY
127 |
128 | ; Reset handler routine
129 | Reset_Handler PROC
130 | EXPORT Reset_Handler [WEAK]
131 | IMPORT __main
132 | IMPORT SystemInit
133 | LDR R0, =SystemInit
134 | BLX R0
135 | LDR R0, =__main
136 | BX R0
137 | ENDP
138 |
139 | ; Dummy Exception Handlers (infinite loops which can be modified)
140 |
141 | NMI_Handler PROC
142 | EXPORT NMI_Handler [WEAK]
143 | B .
144 | ENDP
145 | HardFault_Handler\
146 | PROC
147 | EXPORT HardFault_Handler [WEAK]
148 | B .
149 | ENDP
150 | MemManage_Handler\
151 | PROC
152 | EXPORT MemManage_Handler [WEAK]
153 | B .
154 | ENDP
155 | BusFault_Handler\
156 | PROC
157 | EXPORT BusFault_Handler [WEAK]
158 | B .
159 | ENDP
160 | UsageFault_Handler\
161 | PROC
162 | EXPORT UsageFault_Handler [WEAK]
163 | B .
164 | ENDP
165 | SVC_Handler PROC
166 | EXPORT SVC_Handler [WEAK]
167 | B .
168 | ENDP
169 | DebugMon_Handler\
170 | PROC
171 | EXPORT DebugMon_Handler [WEAK]
172 | B .
173 | ENDP
174 | PendSV_Handler PROC
175 | EXPORT PendSV_Handler [WEAK]
176 | B .
177 | ENDP
178 | SysTick_Handler PROC
179 | EXPORT SysTick_Handler [WEAK]
180 | B .
181 | ENDP
182 |
183 | Default_Handler PROC
184 |
185 | EXPORT WWDG_IRQHandler [WEAK]
186 | EXPORT PVD_IRQHandler [WEAK]
187 | EXPORT TAMPER_IRQHandler [WEAK]
188 | EXPORT RTC_IRQHandler [WEAK]
189 | EXPORT FLASH_IRQHandler [WEAK]
190 | EXPORT RCC_IRQHandler [WEAK]
191 | EXPORT EXTI0_IRQHandler [WEAK]
192 | EXPORT EXTI1_IRQHandler [WEAK]
193 | EXPORT EXTI2_IRQHandler [WEAK]
194 | EXPORT EXTI3_IRQHandler [WEAK]
195 | EXPORT EXTI4_IRQHandler [WEAK]
196 | EXPORT DMA1_Channel1_IRQHandler [WEAK]
197 | EXPORT DMA1_Channel2_IRQHandler [WEAK]
198 | EXPORT DMA1_Channel3_IRQHandler [WEAK]
199 | EXPORT DMA1_Channel4_IRQHandler [WEAK]
200 | EXPORT DMA1_Channel5_IRQHandler [WEAK]
201 | EXPORT DMA1_Channel6_IRQHandler [WEAK]
202 | EXPORT DMA1_Channel7_IRQHandler [WEAK]
203 | EXPORT ADC1_2_IRQHandler [WEAK]
204 | EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
205 | EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
206 | EXPORT CAN1_RX1_IRQHandler [WEAK]
207 | EXPORT CAN1_SCE_IRQHandler [WEAK]
208 | EXPORT EXTI9_5_IRQHandler [WEAK]
209 | EXPORT TIM1_BRK_IRQHandler [WEAK]
210 | EXPORT TIM1_UP_IRQHandler [WEAK]
211 | EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
212 | EXPORT TIM1_CC_IRQHandler [WEAK]
213 | EXPORT TIM2_IRQHandler [WEAK]
214 | EXPORT TIM3_IRQHandler [WEAK]
215 | EXPORT I2C1_EV_IRQHandler [WEAK]
216 | EXPORT I2C1_ER_IRQHandler [WEAK]
217 | EXPORT SPI1_IRQHandler [WEAK]
218 | EXPORT USART1_IRQHandler [WEAK]
219 | EXPORT USART2_IRQHandler [WEAK]
220 | EXPORT EXTI15_10_IRQHandler [WEAK]
221 | EXPORT RTCAlarm_IRQHandler [WEAK]
222 | EXPORT USBWakeUp_IRQHandler [WEAK]
223 |
224 | WWDG_IRQHandler
225 | PVD_IRQHandler
226 | TAMPER_IRQHandler
227 | RTC_IRQHandler
228 | FLASH_IRQHandler
229 | RCC_IRQHandler
230 | EXTI0_IRQHandler
231 | EXTI1_IRQHandler
232 | EXTI2_IRQHandler
233 | EXTI3_IRQHandler
234 | EXTI4_IRQHandler
235 | DMA1_Channel1_IRQHandler
236 | DMA1_Channel2_IRQHandler
237 | DMA1_Channel3_IRQHandler
238 | DMA1_Channel4_IRQHandler
239 | DMA1_Channel5_IRQHandler
240 | DMA1_Channel6_IRQHandler
241 | DMA1_Channel7_IRQHandler
242 | ADC1_2_IRQHandler
243 | USB_HP_CAN1_TX_IRQHandler
244 | USB_LP_CAN1_RX0_IRQHandler
245 | CAN1_RX1_IRQHandler
246 | CAN1_SCE_IRQHandler
247 | EXTI9_5_IRQHandler
248 | TIM1_BRK_IRQHandler
249 | TIM1_UP_IRQHandler
250 | TIM1_TRG_COM_IRQHandler
251 | TIM1_CC_IRQHandler
252 | TIM2_IRQHandler
253 | TIM3_IRQHandler
254 | I2C1_EV_IRQHandler
255 | I2C1_ER_IRQHandler
256 | SPI1_IRQHandler
257 | USART1_IRQHandler
258 | USART2_IRQHandler
259 | EXTI15_10_IRQHandler
260 | RTCAlarm_IRQHandler
261 | USBWakeUp_IRQHandler
262 |
263 | B .
264 |
265 | ENDP
266 |
267 | ALIGN
268 |
269 | ;*******************************************************************************
270 | ; User Stack and Heap initialization
271 | ;*******************************************************************************
272 | IF :DEF:__MICROLIB
273 |
274 | EXPORT __initial_sp
275 | EXPORT __heap_base
276 | EXPORT __heap_limit
277 |
278 | ELSE
279 |
280 | IMPORT __use_two_region_memory
281 | EXPORT __user_initial_stackheap
282 |
283 | __user_initial_stackheap
284 |
285 | LDR R0, = Heap_Mem
286 | LDR R1, =(Stack_Mem + Stack_Size)
287 | LDR R2, = (Heap_Mem + Heap_Size)
288 | LDR R3, = Stack_Mem
289 | BX LR
290 |
291 | ALIGN
292 |
293 | ENDIF
294 |
295 | END
296 |
297 | ;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
298 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_ld_vl.s:
--------------------------------------------------------------------------------
1 | ;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
2 | ;* File Name : startup_stm32f10x_ld_vl.s
3 | ;* Author : MCD Application Team
4 | ;* Version : V3.3.0
5 | ;* Date : 10/15/2010
6 | ;* Description : STM32F10x Low Density Value Line Devices vector table
7 | ;* for MDK-ARM toolchain.
8 | ;* This module performs:
9 | ;* - Set the initial SP
10 | ;* - Set the initial PC == Reset_Handler
11 | ;* - Set the vector table entries with the exceptions ISR address
12 | ;* - Configure the clock system
13 | ;* - Branches to __main in the C library (which eventually
14 | ;* calls main()).
15 | ;* After Reset the CortexM3 processor is in Thread mode,
16 | ;* priority is Privileged, and the Stack is set to Main.
17 | ;* <<< Use Configuration Wizard in Context Menu >>>
18 | ;*******************************************************************************
19 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
20 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
21 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
22 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
23 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
24 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
25 | ;*******************************************************************************
26 |
27 | ; Amount of memory (in bytes) allocated for Stack
28 | ; Tailor this value to your application needs
29 | ; Stack Configuration
30 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 | ;
32 |
33 | Stack_Size EQU 0x00000800
34 |
35 | AREA STACK, NOINIT, READWRITE, ALIGN=3
36 | Stack_Mem SPACE Stack_Size
37 | __initial_sp
38 |
39 |
40 | ; Heap Configuration
41 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 | ;
43 |
44 | Heap_Size EQU 0x00000200
45 |
46 | AREA HEAP, NOINIT, READWRITE, ALIGN=3
47 | __heap_base
48 | Heap_Mem SPACE Heap_Size
49 | __heap_limit
50 |
51 | PRESERVE8
52 | THUMB
53 |
54 |
55 | ; Vector Table Mapped to Address 0 at Reset
56 | AREA RESET, DATA, READONLY
57 | EXPORT __Vectors
58 | EXPORT __Vectors_End
59 | EXPORT __Vectors_Size
60 |
61 | __Vectors DCD __initial_sp ; Top of Stack
62 | DCD Reset_Handler ; Reset Handler
63 | DCD NMI_Handler ; NMI Handler
64 | DCD HardFault_Handler ; Hard Fault Handler
65 | DCD MemManage_Handler ; MPU Fault Handler
66 | DCD BusFault_Handler ; Bus Fault Handler
67 | DCD UsageFault_Handler ; Usage Fault Handler
68 | DCD 0 ; Reserved
69 | DCD 0 ; Reserved
70 | DCD 0 ; Reserved
71 | DCD 0 ; Reserved
72 | DCD SVC_Handler ; SVCall Handler
73 | DCD DebugMon_Handler ; Debug Monitor Handler
74 | DCD 0 ; Reserved
75 | DCD PendSV_Handler ; PendSV Handler
76 | DCD SysTick_Handler ; SysTick Handler
77 |
78 | ; External Interrupts
79 | DCD WWDG_IRQHandler ; Window Watchdog
80 | DCD PVD_IRQHandler ; PVD through EXTI Line detect
81 | DCD TAMPER_IRQHandler ; Tamper
82 | DCD RTC_IRQHandler ; RTC
83 | DCD FLASH_IRQHandler ; Flash
84 | DCD RCC_IRQHandler ; RCC
85 | DCD EXTI0_IRQHandler ; EXTI Line 0
86 | DCD EXTI1_IRQHandler ; EXTI Line 1
87 | DCD EXTI2_IRQHandler ; EXTI Line 2
88 | DCD EXTI3_IRQHandler ; EXTI Line 3
89 | DCD EXTI4_IRQHandler ; EXTI Line 4
90 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
91 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
92 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
93 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
94 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
95 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
96 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
97 | DCD ADC1_IRQHandler ; ADC1
98 | DCD 0 ; Reserved
99 | DCD 0 ; Reserved
100 | DCD 0 ; Reserved
101 | DCD 0 ; Reserved
102 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
103 | DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
104 | DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
105 | DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
107 | DCD TIM2_IRQHandler ; TIM2
108 | DCD TIM3_IRQHandler ; TIM3
109 | DCD 0 ; Reserved
110 | DCD I2C1_EV_IRQHandler ; I2C1 Event
111 | DCD I2C1_ER_IRQHandler ; I2C1 Error
112 | DCD 0 ; Reserved
113 | DCD 0 ; Reserved
114 | DCD SPI1_IRQHandler ; SPI1
115 | DCD 0 ; Reserved
116 | DCD USART1_IRQHandler ; USART1
117 | DCD USART2_IRQHandler ; USART2
118 | DCD 0 ; Reserved
119 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
120 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
121 | DCD CEC_IRQHandler ; HDMI-CEC
122 | DCD 0 ; Reserved
123 | DCD 0 ; Reserved
124 | DCD 0 ; Reserved
125 | DCD 0 ; Reserved
126 | DCD 0 ; Reserved
127 | DCD 0 ; Reserved
128 | DCD 0 ; Reserved
129 | DCD 0 ; Reserved
130 | DCD 0 ; Reserved
131 | DCD 0 ; Reserved
132 | DCD 0 ; Reserved
133 | DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
134 | DCD TIM7_IRQHandler ; TIM7
135 | __Vectors_End
136 |
137 | __Vectors_Size EQU __Vectors_End - __Vectors
138 |
139 | AREA |.text|, CODE, READONLY
140 |
141 | ; Reset handler
142 | Reset_Handler PROC
143 | EXPORT Reset_Handler [WEAK]
144 | IMPORT __main
145 | IMPORT SystemInit
146 | LDR R0, =SystemInit
147 | BLX R0
148 | LDR R0, =__main
149 | BX R0
150 | ENDP
151 |
152 | ; Dummy Exception Handlers (infinite loops which can be modified)
153 |
154 | NMI_Handler PROC
155 | EXPORT NMI_Handler [WEAK]
156 | B .
157 | ENDP
158 | HardFault_Handler\
159 | PROC
160 | EXPORT HardFault_Handler [WEAK]
161 | B .
162 | ENDP
163 | MemManage_Handler\
164 | PROC
165 | EXPORT MemManage_Handler [WEAK]
166 | B .
167 | ENDP
168 | BusFault_Handler\
169 | PROC
170 | EXPORT BusFault_Handler [WEAK]
171 | B .
172 | ENDP
173 | UsageFault_Handler\
174 | PROC
175 | EXPORT UsageFault_Handler [WEAK]
176 | B .
177 | ENDP
178 | SVC_Handler PROC
179 | EXPORT SVC_Handler [WEAK]
180 | B .
181 | ENDP
182 | DebugMon_Handler\
183 | PROC
184 | EXPORT DebugMon_Handler [WEAK]
185 | B .
186 | ENDP
187 | PendSV_Handler PROC
188 | EXPORT PendSV_Handler [WEAK]
189 | B .
190 | ENDP
191 | SysTick_Handler PROC
192 | EXPORT SysTick_Handler [WEAK]
193 | B .
194 | ENDP
195 |
196 | Default_Handler PROC
197 |
198 | EXPORT WWDG_IRQHandler [WEAK]
199 | EXPORT PVD_IRQHandler [WEAK]
200 | EXPORT TAMPER_IRQHandler [WEAK]
201 | EXPORT RTC_IRQHandler [WEAK]
202 | EXPORT FLASH_IRQHandler [WEAK]
203 | EXPORT RCC_IRQHandler [WEAK]
204 | EXPORT EXTI0_IRQHandler [WEAK]
205 | EXPORT EXTI1_IRQHandler [WEAK]
206 | EXPORT EXTI2_IRQHandler [WEAK]
207 | EXPORT EXTI3_IRQHandler [WEAK]
208 | EXPORT EXTI4_IRQHandler [WEAK]
209 | EXPORT DMA1_Channel1_IRQHandler [WEAK]
210 | EXPORT DMA1_Channel2_IRQHandler [WEAK]
211 | EXPORT DMA1_Channel3_IRQHandler [WEAK]
212 | EXPORT DMA1_Channel4_IRQHandler [WEAK]
213 | EXPORT DMA1_Channel5_IRQHandler [WEAK]
214 | EXPORT DMA1_Channel6_IRQHandler [WEAK]
215 | EXPORT DMA1_Channel7_IRQHandler [WEAK]
216 | EXPORT ADC1_IRQHandler [WEAK]
217 | EXPORT EXTI9_5_IRQHandler [WEAK]
218 | EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
219 | EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
220 | EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
221 | EXPORT TIM1_CC_IRQHandler [WEAK]
222 | EXPORT TIM2_IRQHandler [WEAK]
223 | EXPORT TIM3_IRQHandler [WEAK]
224 | EXPORT I2C1_EV_IRQHandler [WEAK]
225 | EXPORT I2C1_ER_IRQHandler [WEAK]
226 | EXPORT SPI1_IRQHandler [WEAK]
227 | EXPORT USART1_IRQHandler [WEAK]
228 | EXPORT USART2_IRQHandler [WEAK]
229 | EXPORT EXTI15_10_IRQHandler [WEAK]
230 | EXPORT RTCAlarm_IRQHandler [WEAK]
231 | EXPORT CEC_IRQHandler [WEAK]
232 | EXPORT TIM6_DAC_IRQHandler [WEAK]
233 | EXPORT TIM7_IRQHandler [WEAK]
234 | WWDG_IRQHandler
235 | PVD_IRQHandler
236 | TAMPER_IRQHandler
237 | RTC_IRQHandler
238 | FLASH_IRQHandler
239 | RCC_IRQHandler
240 | EXTI0_IRQHandler
241 | EXTI1_IRQHandler
242 | EXTI2_IRQHandler
243 | EXTI3_IRQHandler
244 | EXTI4_IRQHandler
245 | DMA1_Channel1_IRQHandler
246 | DMA1_Channel2_IRQHandler
247 | DMA1_Channel3_IRQHandler
248 | DMA1_Channel4_IRQHandler
249 | DMA1_Channel5_IRQHandler
250 | DMA1_Channel6_IRQHandler
251 | DMA1_Channel7_IRQHandler
252 | ADC1_IRQHandler
253 | EXTI9_5_IRQHandler
254 | TIM1_BRK_TIM15_IRQHandler
255 | TIM1_UP_TIM16_IRQHandler
256 | TIM1_TRG_COM_TIM17_IRQHandler
257 | TIM1_CC_IRQHandler
258 | TIM2_IRQHandler
259 | TIM3_IRQHandler
260 | I2C1_EV_IRQHandler
261 | I2C1_ER_IRQHandler
262 | SPI1_IRQHandler
263 | USART1_IRQHandler
264 | USART2_IRQHandler
265 | EXTI15_10_IRQHandler
266 | RTCAlarm_IRQHandler
267 | CEC_IRQHandler
268 | TIM6_DAC_IRQHandler
269 | TIM7_IRQHandler
270 | B .
271 |
272 | ENDP
273 |
274 | ALIGN
275 |
276 | ;*******************************************************************************
277 | ; User Stack and Heap initialization
278 | ;*******************************************************************************
279 | IF :DEF:__MICROLIB
280 |
281 | EXPORT __initial_sp
282 | EXPORT __heap_base
283 | EXPORT __heap_limit
284 |
285 | ELSE
286 |
287 | IMPORT __use_two_region_memory
288 | EXPORT __user_initial_stackheap
289 |
290 | __user_initial_stackheap
291 |
292 | LDR R0, = Heap_Mem
293 | LDR R1, =(Stack_Mem + Stack_Size)
294 | LDR R2, = (Heap_Mem + Heap_Size)
295 | LDR R3, = Stack_Mem
296 | BX LR
297 |
298 | ALIGN
299 |
300 | ENDIF
301 |
302 | END
303 |
304 | ;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
305 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_md.s:
--------------------------------------------------------------------------------
1 | ;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
2 | ;* File Name : startup_stm32f10x_md.s
3 | ;* Author : MCD Application Team
4 | ;* Version : V3.3.0
5 | ;* Date : 10/15/2010
6 | ;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
7 | ;* toolchain.
8 | ;* This module performs:
9 | ;* - Set the initial SP
10 | ;* - Set the initial PC == Reset_Handler
11 | ;* - Set the vector table entries with the exceptions ISR address
12 | ;* - Configure the clock system
13 | ;* - Branches to __main in the C library (which eventually
14 | ;* calls main()).
15 | ;* After Reset the CortexM3 processor is in Thread mode,
16 | ;* priority is Privileged, and the Stack is set to Main.
17 | ;* <<< Use Configuration Wizard in Context Menu >>>
18 | ;*******************************************************************************
19 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
20 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
21 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
22 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
23 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
24 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
25 | ;*******************************************************************************
26 |
27 | ; Amount of memory (in bytes) allocated for Stack
28 | ; Tailor this value to your application needs
29 | ; Stack Configuration
30 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 | ;
32 |
33 | Stack_Size EQU 0x00000800
34 |
35 | AREA STACK, NOINIT, READWRITE, ALIGN=3
36 | Stack_Mem SPACE Stack_Size
37 | __initial_sp
38 |
39 |
40 | ; Heap Configuration
41 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 | ;
43 |
44 | Heap_Size EQU 0x00000200
45 |
46 | AREA HEAP, NOINIT, READWRITE, ALIGN=3
47 | __heap_base
48 | Heap_Mem SPACE Heap_Size
49 | __heap_limit
50 |
51 | PRESERVE8
52 | THUMB
53 |
54 |
55 | ; Vector Table Mapped to Address 0 at Reset
56 | AREA RESET, DATA, READONLY
57 | EXPORT __Vectors
58 | EXPORT __Vectors_End
59 | EXPORT __Vectors_Size
60 |
61 | __Vectors DCD __initial_sp ; Top of Stack
62 | DCD Reset_Handler ; Reset Handler
63 | DCD NMI_Handler ; NMI Handler
64 | DCD HardFault_Handler ; Hard Fault Handler
65 | DCD MemManage_Handler ; MPU Fault Handler
66 | DCD BusFault_Handler ; Bus Fault Handler
67 | DCD UsageFault_Handler ; Usage Fault Handler
68 | DCD 0 ; Reserved
69 | DCD 0 ; Reserved
70 | DCD 0 ; Reserved
71 | DCD 0 ; Reserved
72 | DCD SVC_Handler ; SVCall Handler
73 | DCD DebugMon_Handler ; Debug Monitor Handler
74 | DCD 0 ; Reserved
75 | DCD PendSV_Handler ; PendSV Handler
76 | DCD SysTick_Handler ; SysTick Handler
77 |
78 | ; External Interrupts
79 | DCD WWDG_IRQHandler ; Window Watchdog
80 | DCD PVD_IRQHandler ; PVD through EXTI Line detect
81 | DCD TAMPER_IRQHandler ; Tamper
82 | DCD RTC_IRQHandler ; RTC
83 | DCD FLASH_IRQHandler ; Flash
84 | DCD RCC_IRQHandler ; RCC
85 | DCD EXTI0_IRQHandler ; EXTI Line 0
86 | DCD EXTI1_IRQHandler ; EXTI Line 1
87 | DCD EXTI2_IRQHandler ; EXTI Line 2
88 | DCD EXTI3_IRQHandler ; EXTI Line 3
89 | DCD EXTI4_IRQHandler ; EXTI Line 4
90 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
91 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
92 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
93 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
94 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
95 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
96 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
97 | DCD ADC1_2_IRQHandler ; ADC1_2
98 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
99 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
100 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1
101 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE
102 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
103 | DCD TIM1_BRK_IRQHandler ; TIM1 Break
104 | DCD TIM1_UP_IRQHandler ; TIM1 Update
105 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
107 | DCD TIM2_IRQHandler ; TIM2
108 | DCD TIM3_IRQHandler ; TIM3
109 | DCD TIM4_IRQHandler ; TIM4
110 | DCD I2C1_EV_IRQHandler ; I2C1 Event
111 | DCD I2C1_ER_IRQHandler ; I2C1 Error
112 | DCD I2C2_EV_IRQHandler ; I2C2 Event
113 | DCD I2C2_ER_IRQHandler ; I2C2 Error
114 | DCD SPI1_IRQHandler ; SPI1
115 | DCD SPI2_IRQHandler ; SPI2
116 | DCD USART1_IRQHandler ; USART1
117 | DCD USART2_IRQHandler ; USART2
118 | DCD USART3_IRQHandler ; USART3
119 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
120 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
121 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
122 | __Vectors_End
123 |
124 | __Vectors_Size EQU __Vectors_End - __Vectors
125 |
126 | AREA |.text|, CODE, READONLY
127 |
128 | ; Reset handler
129 | Reset_Handler PROC
130 | EXPORT Reset_Handler [WEAK]
131 | IMPORT __main
132 | IMPORT SystemInit
133 | LDR R0, =SystemInit
134 | BLX R0
135 | LDR R0, =__main
136 | BX R0
137 | ENDP
138 |
139 | ; Dummy Exception Handlers (infinite loops which can be modified)
140 |
141 | NMI_Handler PROC
142 | EXPORT NMI_Handler [WEAK]
143 | B .
144 | ENDP
145 | HardFault_Handler\
146 | PROC
147 | EXPORT HardFault_Handler [WEAK]
148 | B .
149 | ENDP
150 | MemManage_Handler\
151 | PROC
152 | EXPORT MemManage_Handler [WEAK]
153 | B .
154 | ENDP
155 | BusFault_Handler\
156 | PROC
157 | EXPORT BusFault_Handler [WEAK]
158 | B .
159 | ENDP
160 | UsageFault_Handler\
161 | PROC
162 | EXPORT UsageFault_Handler [WEAK]
163 | B .
164 | ENDP
165 | SVC_Handler PROC
166 | EXPORT SVC_Handler [WEAK]
167 | B .
168 | ENDP
169 | DebugMon_Handler\
170 | PROC
171 | EXPORT DebugMon_Handler [WEAK]
172 | B .
173 | ENDP
174 | PendSV_Handler PROC
175 | EXPORT PendSV_Handler [WEAK]
176 | B .
177 | ENDP
178 | SysTick_Handler PROC
179 | EXPORT SysTick_Handler [WEAK]
180 | B .
181 | ENDP
182 |
183 | Default_Handler PROC
184 |
185 | EXPORT WWDG_IRQHandler [WEAK]
186 | EXPORT PVD_IRQHandler [WEAK]
187 | EXPORT TAMPER_IRQHandler [WEAK]
188 | EXPORT RTC_IRQHandler [WEAK]
189 | EXPORT FLASH_IRQHandler [WEAK]
190 | EXPORT RCC_IRQHandler [WEAK]
191 | EXPORT EXTI0_IRQHandler [WEAK]
192 | EXPORT EXTI1_IRQHandler [WEAK]
193 | EXPORT EXTI2_IRQHandler [WEAK]
194 | EXPORT EXTI3_IRQHandler [WEAK]
195 | EXPORT EXTI4_IRQHandler [WEAK]
196 | EXPORT DMA1_Channel1_IRQHandler [WEAK]
197 | EXPORT DMA1_Channel2_IRQHandler [WEAK]
198 | EXPORT DMA1_Channel3_IRQHandler [WEAK]
199 | EXPORT DMA1_Channel4_IRQHandler [WEAK]
200 | EXPORT DMA1_Channel5_IRQHandler [WEAK]
201 | EXPORT DMA1_Channel6_IRQHandler [WEAK]
202 | EXPORT DMA1_Channel7_IRQHandler [WEAK]
203 | EXPORT ADC1_2_IRQHandler [WEAK]
204 | EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
205 | EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
206 | EXPORT CAN1_RX1_IRQHandler [WEAK]
207 | EXPORT CAN1_SCE_IRQHandler [WEAK]
208 | EXPORT EXTI9_5_IRQHandler [WEAK]
209 | EXPORT TIM1_BRK_IRQHandler [WEAK]
210 | EXPORT TIM1_UP_IRQHandler [WEAK]
211 | EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
212 | EXPORT TIM1_CC_IRQHandler [WEAK]
213 | EXPORT TIM2_IRQHandler [WEAK]
214 | EXPORT TIM3_IRQHandler [WEAK]
215 | EXPORT TIM4_IRQHandler [WEAK]
216 | EXPORT I2C1_EV_IRQHandler [WEAK]
217 | EXPORT I2C1_ER_IRQHandler [WEAK]
218 | EXPORT I2C2_EV_IRQHandler [WEAK]
219 | EXPORT I2C2_ER_IRQHandler [WEAK]
220 | EXPORT SPI1_IRQHandler [WEAK]
221 | EXPORT SPI2_IRQHandler [WEAK]
222 | EXPORT USART1_IRQHandler [WEAK]
223 | EXPORT USART2_IRQHandler [WEAK]
224 | EXPORT USART3_IRQHandler [WEAK]
225 | EXPORT EXTI15_10_IRQHandler [WEAK]
226 | EXPORT RTCAlarm_IRQHandler [WEAK]
227 | EXPORT USBWakeUp_IRQHandler [WEAK]
228 |
229 | WWDG_IRQHandler
230 | PVD_IRQHandler
231 | TAMPER_IRQHandler
232 | RTC_IRQHandler
233 | FLASH_IRQHandler
234 | RCC_IRQHandler
235 | EXTI0_IRQHandler
236 | EXTI1_IRQHandler
237 | EXTI2_IRQHandler
238 | EXTI3_IRQHandler
239 | EXTI4_IRQHandler
240 | DMA1_Channel1_IRQHandler
241 | DMA1_Channel2_IRQHandler
242 | DMA1_Channel3_IRQHandler
243 | DMA1_Channel4_IRQHandler
244 | DMA1_Channel5_IRQHandler
245 | DMA1_Channel6_IRQHandler
246 | DMA1_Channel7_IRQHandler
247 | ADC1_2_IRQHandler
248 | USB_HP_CAN1_TX_IRQHandler
249 | USB_LP_CAN1_RX0_IRQHandler
250 | CAN1_RX1_IRQHandler
251 | CAN1_SCE_IRQHandler
252 | EXTI9_5_IRQHandler
253 | TIM1_BRK_IRQHandler
254 | TIM1_UP_IRQHandler
255 | TIM1_TRG_COM_IRQHandler
256 | TIM1_CC_IRQHandler
257 | TIM2_IRQHandler
258 | TIM3_IRQHandler
259 | TIM4_IRQHandler
260 | I2C1_EV_IRQHandler
261 | I2C1_ER_IRQHandler
262 | I2C2_EV_IRQHandler
263 | I2C2_ER_IRQHandler
264 | SPI1_IRQHandler
265 | SPI2_IRQHandler
266 | USART1_IRQHandler
267 | USART2_IRQHandler
268 | USART3_IRQHandler
269 | EXTI15_10_IRQHandler
270 | RTCAlarm_IRQHandler
271 | USBWakeUp_IRQHandler
272 |
273 | B .
274 |
275 | ENDP
276 |
277 | ALIGN
278 |
279 | ;*******************************************************************************
280 | ; User Stack and Heap initialization
281 | ;*******************************************************************************
282 | IF :DEF:__MICROLIB
283 |
284 | EXPORT __initial_sp
285 | EXPORT __heap_base
286 | EXPORT __heap_limit
287 |
288 | ELSE
289 |
290 | IMPORT __use_two_region_memory
291 | EXPORT __user_initial_stackheap
292 |
293 | __user_initial_stackheap
294 |
295 | LDR R0, = Heap_Mem
296 | LDR R1, =(Stack_Mem + Stack_Size)
297 | LDR R2, = (Heap_Mem + Heap_Size)
298 | LDR R3, = Stack_Mem
299 | BX LR
300 |
301 | ALIGN
302 |
303 | ENDIF
304 |
305 | END
306 |
307 | ;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
308 |
--------------------------------------------------------------------------------
/IAP/inc/common.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file IAP/inc/common.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the headers of the common functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef _COMMON_H
23 | #define _COMMON_H
24 |
25 | /* Includes ------------------------------------------------------------------*/
26 | #include "iap_config.h"
27 | #include "stdio.h"
28 | #include "string.h"
29 | #include "stm32f10x.h"
30 |
31 |
32 | /**
33 | * @brief Definition for COM port1, connected to USART1
34 | */
35 | #define EVAL_COM1 USART1
36 | #define EVAL_COM1_CLK RCC_APB2Periph_USART1
37 | #define EVAL_COM1_TX_PIN GPIO_Pin_9
38 | #define EVAL_COM1_TX_GPIO_PORT GPIOA
39 | #define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
40 | #define EVAL_COM1_RX_PIN GPIO_Pin_10
41 | #define EVAL_COM1_RX_GPIO_PORT GPIOA
42 | #define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
43 | #define EVAL_COM1_IRQn USART1_IRQn
44 |
45 | /**
46 | * @brief Definition for COM port2, connected to USART2
47 | */
48 | #define EVAL_COM2 USART2
49 | #define EVAL_COM2_CLK RCC_APB1Periph_USART2
50 | #define EVAL_COM2_TX_PIN GPIO_Pin_2
51 | #define EVAL_COM2_TX_GPIO_PORT GPIOA
52 | #define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA
53 | #define EVAL_COM2_RX_PIN GPIO_Pin_3
54 | #define EVAL_COM2_RX_GPIO_PORT GPIOA
55 | #define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA
56 | #define EVAL_COM2_IRQn USART2_IRQn
57 |
58 |
59 |
60 | /* Exported macro ------------------------------------------------------------*/
61 | /* Common routines */
62 | #define IS_AF(c) ((c >= 'A') && (c <= 'F'))
63 | #define IS_af(c) ((c >= 'a') && (c <= 'f'))
64 | #define IS_09(c) ((c >= '0') && (c <= '9'))
65 | #define ISVALIDHEX(c) IS_AF(c) || IS_af(c) || IS_09(c)
66 | #define ISVALIDDEC(c) IS_09(c)
67 | #define CONVERTDEC(c) (c - '0')
68 |
69 | #define CONVERTHEX_alpha(c) (IS_AF(c) ? (c - 'A'+10) : (c - 'a'+10))
70 | #define CONVERTHEX(c) (IS_09(c) ? (c - '0') : CONVERTHEX_alpha(c))
71 |
72 | #define SerialPutString(x) Serial_PutString((uint8_t*)(x))
73 |
74 | /* Exported functions ------------------------------------------------------- */
75 | extern void STM_EVAL_COMInit(USART_InitTypeDef* USART_InitStruct);
76 | void Int2Str(uint8_t* str,int32_t intnum);
77 | uint32_t Str2Int(uint8_t *inputstr,int32_t *intnum);
78 | uint32_t GetIntegerInput(int32_t * num);
79 | uint32_t SerialKeyPressed(uint8_t *key);
80 | uint8_t GetKey(void);
81 | void SerialPutChar(uint8_t c);
82 | void Serial_PutString(uint8_t *s);
83 | void GetInputString(uint8_t * buffP);
84 | uint32_t FLASH_PagesMask(__IO uint32_t Size);
85 | uint8_t EraseSomePages(__IO uint32_t size, uint8_t outPutCont);
86 | extern void Delay_ms( uint16_t time_ms );
87 | extern void assert_failed(uint8_t* file, uint32_t line);
88 | #endif /* _COMMON_H */
89 |
90 | /*******************(C)COPYRIGHT 2010 STMicroelectronics *****END OF FILE******/
91 |
--------------------------------------------------------------------------------
/IAP/inc/iap.h:
--------------------------------------------------------------------------------
1 | #ifndef __IAP_H__
2 | #define __IAP_H__
3 | #include "stm32f10x.h"
4 |
5 | /* Exported types ------------------------------------------------------------*/
6 | typedef void (*pFunction)(void);
7 |
8 | extern pFunction Jump_To_Application;
9 | extern uint32_t JumpAddress;
10 |
11 |
12 | extern void IAP_Init(void);
13 | extern uint16_t IAP_ReadFlag(void);
14 | extern void IAP_WriteFlag(uint16_t flag);
15 | extern int8_t IAP_RunApp(void);
16 | extern void IAP_Main_Menu(void);
17 | extern int8_t IAP_Update(void);
18 | extern int8_t IAP_Upload(void);
19 | extern int8_t IAP_Erase(void);
20 |
21 |
22 |
23 | #endif
24 |
--------------------------------------------------------------------------------
/IAP/inc/iap_config.h:
--------------------------------------------------------------------------------
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/IAP/inc/stmflash.h:
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https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/IAP/inc/stmflash.h
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/IAP/inc/ymodem.h:
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1 | /**
2 | ******************************************************************************
3 | * @file IAP/inc/ymodem.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the software function headers of the ymodem.c
8 | * file.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef _YMODEM_H_
24 | #define _YMODEM_H_
25 | #include "stm32f10x.h"
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 |
29 | /* Exported types ------------------------------------------------------------*/
30 | /* Exported constants --------------------------------------------------------*/
31 | #define PACKET_SEQNO_INDEX (1)
32 | #define PACKET_SEQNO_COMP_INDEX (2)
33 |
34 | #define PACKET_HEADER (3)
35 | #define PACKET_TRAILER (2)
36 | #define PACKET_OVERHEAD (PACKET_HEADER + PACKET_TRAILER)
37 | #define PACKET_8B_SIZE (8)
38 | #define PACKET_16B_SIZE (16)
39 | #define PACKET_32B_SIZE (32)
40 | #define PACKET_64B_SIZE (64)
41 | #define PACKET_128B_SIZE (128)
42 | #define PACKET_256B_SIZE (256)
43 | #define PACKET_512B_SIZE (512)
44 | #define PACKET_1KB_SIZE (1024)
45 | #define PACKET_2KB_SIZE (2048)
46 |
47 | #define FILE_NAME_LENGTH (256)
48 | #define FILE_SIZE_LENGTH (16)
49 |
50 | #define SOH (0x01) /* start of 128-byte data packet */
51 | #define STX (0x02) /* start of 1024-byte data packet */
52 | #define STX_8B (0xA1)
53 | #define STX_16B (0xA2)
54 | #define STX_32B (0xA3)
55 | #define STX_64B (0xA4) /* start of 64-byte data packet */
56 | #define STX_128B (0xA5)
57 | #define STX_256B (0xA6)
58 | #define STX_512B (0xA7)
59 | #define STX_1KB (0xA8)
60 | #define STX_2KB (0XA9)
61 |
62 | #define EOT (0x04) /* end of transmission */
63 | #define ACK (0x06) /* acknowledge */
64 | #define NAK (0x15) /* negative acknowledge */
65 | #define CA (0x18) /* two of these in succession aborts transfer */
66 | #define CRC16 (0x43) /* 'C' == 0x43, request 16-bit CRC */
67 |
68 | #define ABORT1 (0x41) /* 'A' == 0x41, abort by user */
69 | #define ABORT2 (0x61) /* 'a' == 0x61, abort by user */
70 |
71 | #define NAK_TIMEOUT (0x100000)
72 | #define MAX_ERRORS (5)
73 |
74 | extern uint32_t FlashDestination;
75 | extern uint8_t file_name[FILE_NAME_LENGTH];
76 |
77 | /* Exported macro ------------------------------------------------------------*/
78 | /* Exported functions ------------------------------------------------------- */
79 | int32_t Ymodem_Receive (uint8_t *);
80 | uint8_t Ymodem_Transmit (uint8_t *,const uint8_t* , uint32_t );
81 |
82 | #endif /* _YMODEM_H_ */
83 |
84 | /*******************(C)COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
85 |
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/IAP/src/common.c:
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https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/IAP/src/common.c
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/IAP/src/iap.c:
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https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/IAP/src/iap.c
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/IAP/src/stmflash.c:
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https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/IAP/src/stmflash.c
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/IAP/src/ymodem.c:
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https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/IAP/src/ymodem.c
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/MDK-ARM/DebugConfig/STM32-IAP_CL_STM32F107VC_1.0.0.dbgconf:
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1 | // File: STM32F101_102_103_105_107.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
4 | // STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
5 |
6 | // <<< Use Configuration Wizard in Context Menu >>>
7 |
8 | // Debug MCU configuration register (DBGMCU_CR)
9 | // Reserved bits must be kept at reset value
10 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted
11 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted
12 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted
13 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
14 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
15 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
16 | // DBG_CAN2_STOP Debug CAN2 stopped when core is halted
17 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
18 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
19 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
20 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
21 | // DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
22 | // DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
23 | // DBG_CAN1_STOP Debug CAN1 stopped when Core is halted
24 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
25 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
26 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
27 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
28 | // DBG_WWDG_STOP Debug window watchdog stopped when core is halted
29 | // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted
30 | // DBG_STANDBY Debug standby mode
31 | // DBG_STOP Debug stop mode
32 | // DBG_SLEEP Debug sleep mode
33 | //
34 | DbgMCU_CR = 0x00000007;
35 |
36 | // <<< end of configuration section >>>
37 |
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/MDK-ARM/DebugConfig/STM32-IAP_HD_VL_STM32F100ZE_1.0.0.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32F100.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F100xx Reference manual (RM0041)
4 | // STM32F100xx datasheets
5 |
6 | // <<< Use Configuration Wizard in Context Menu >>>
7 |
8 | // Debug MCU configuration register (DBGMCU_CR)
9 | // Reserved bits must be kept at reset value
10 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
11 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
12 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
13 | // DBG_TIM17_STOP TIM17 counter stopped when core is halted
14 | // DBG_TIM16_STOP TIM16 counter stopped when core is halted
15 | // DBG_TIM15_STOP TIM15 counter stopped when core is halted
16 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
17 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
18 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
19 | // DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
20 | // DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
21 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
22 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
23 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
24 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
25 | // DBG_WWDG_STOP Debug window watchdog stopped when core is halted
26 | // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted
27 | // DBG_STANDBY Debug standby mode
28 | // DBG_STOP Debug stop mode
29 | // DBG_SLEEP Debug sleep mode
30 | //
31 | DbgMCU_CR = 0x00000007;
32 |
33 | // <<< end of configuration section >>>
34 |
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/MDK-ARM/DebugConfig/STM32-IAP_MD_STM32F103C8_1.0.0.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32F101_102_103_105_107.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
4 | // STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
5 |
6 | // <<< Use Configuration Wizard in Context Menu >>>
7 |
8 | // Debug MCU configuration register (DBGMCU_CR)
9 | // Reserved bits must be kept at reset value
10 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted
11 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted
12 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted
13 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
14 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
15 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
16 | // DBG_CAN2_STOP Debug CAN2 stopped when core is halted
17 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
18 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
19 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
20 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
21 | // DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
22 | // DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted
23 | // DBG_CAN1_STOP Debug CAN1 stopped when Core is halted
24 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
25 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
26 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
27 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
28 | // DBG_WWDG_STOP Debug window watchdog stopped when core is halted
29 | // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted
30 | // DBG_STANDBY Debug standby mode
31 | // DBG_STOP Debug stop mode
32 | // DBG_SLEEP Debug sleep mode
33 | //
34 | DbgMCU_CR = 0x00000007;
35 |
36 | // <<< end of configuration section >>>
37 |
--------------------------------------------------------------------------------
/MDK-ARM/EventRecorderStub.scvd:
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
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/MDK-ARM/JLinkSettings.ini:
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1 | [BREAKPOINTS]
2 | ShowInfoWin = 1
3 | EnableFlashBP = 2
4 | BPDuringExecution = 0
5 | [CFI]
6 | CFISize = 0x00
7 | CFIAddr = 0x00
8 | [CPU]
9 | OverrideMemMap = 0
10 | AllowSimulation = 1
11 | ScriptFile=""
12 | [FLASH]
13 | CacheExcludeSize = 0x00
14 | CacheExcludeAddr = 0x00
15 | MinNumBytesFlashDL = 0
16 | SkipProgOnCRCMatch = 1
17 | VerifyDownload = 1
18 | AllowCaching = 1
19 | EnableFlashDL = 2
20 | Override = 0
21 | Device="UNSPECIFIED"
22 | [GENERAL]
23 | WorkRAMSize = 0x00
24 | WorkRAMAddr = 0x00
25 | RAMUsageLimit = 0x00
26 | [SWO]
27 | SWOLogFile=""
28 | [MEM]
29 | RdOverrideOrMask = 0x00
30 | RdOverrideAndMask = 0xFFFFFFFF
31 | RdOverrideAddr = 0xFFFFFFFF
32 | WrOverrideOrMask = 0x00
33 | WrOverrideAndMask = 0xFFFFFFFF
34 | WrOverrideAddr = 0xFFFFFFFF
35 |
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/MDK-ARM/OUTPUT/STM32-IAP_CL/STM32-IAP_CL.bin:
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/MDK-ARM/OUTPUT/STM32-IAP_CL/STM32-IAP_CL.sct:
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1 | ; *************************************************************
2 | ; *** Scatter-Loading Description File generated by uVision ***
3 | ; *************************************************************
4 |
5 | LR_IROM1 0x08000000 0x00040000 { ; load region size_region
6 | ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
7 | *.o (RESET, +First)
8 | *(InRoot$$Sections)
9 | .ANY (+RO)
10 | .ANY (+XO)
11 | }
12 | RW_IRAM1 0x20000000 0x00010000 { ; RW data
13 | .ANY (+RW +ZI)
14 | }
15 | }
16 |
17 |
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/MDK-ARM/OUTPUT/STM32-IAP_HD/STM32-IAP_HD.bin:
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/MDK-ARM/OUTPUT/STM32-IAP_HD_VL/STM32-IAP_HD_VL.bin:
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/MDK-ARM/OUTPUT/STM32-IAP_MD/STM32-IAP_MD.bin:
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/MDK-ARM/OUTPUT/STM32-IAP_MD/STM32-IAP_MD.hex:
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297 | :10127000E1D1FFF7ABFB0028EFD12846FFF72EFCAA
298 | :10128000D9E7FFF78DFAD6E7FFF760FAE5E7000048
299 | :10129000B012000800000020300000000C1200080E
300 | :1012A000E012000830000020000D00001C120008B1
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303 | :1012D00000000000010203040102030406070809DC
304 | :04000005080000ED02
305 | :00000001FF
306 |
--------------------------------------------------------------------------------
/MDK-ARM/OUTPUT/STM32-IAP_MD/STM32-IAP_MD.sct:
--------------------------------------------------------------------------------
1 | ; *************************************************************
2 | ; *** Scatter-Loading Description File generated by uVision ***
3 | ; *************************************************************
4 |
5 | LR_IROM1 0x08000000 0x00010000 { ; load region size_region
6 | ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
7 | *.o (RESET, +First)
8 | *(InRoot$$Sections)
9 | .ANY (+RO)
10 | .ANY (+XO)
11 | }
12 | RW_IRAM1 0x20000000 0x00005000 { ; RW data
13 | .ANY (+RW +ZI)
14 | }
15 | }
16 |
17 |
--------------------------------------------------------------------------------
/MDK-ARM/OUTPUT/STM32-IAP_MD_VL/STM32-IAP_MD_VL.bin:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/MDK-ARM/OUTPUT/STM32-IAP_MD_VL/STM32-IAP_MD_VL.bin
--------------------------------------------------------------------------------
/MDK-ARM/OUTPUT/STM32-IAP_XL/STM32-IAP_XL.bin:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/MDK-ARM/OUTPUT/STM32-IAP_XL/STM32-IAP_XL.bin
--------------------------------------------------------------------------------
/MDK-ARM/RTE/_STM32-IAP_CL/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Component Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'IAP-UART'
7 | * Target: 'STM32-IAP_CL'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f10x.h"
18 |
19 |
20 | #endif /* RTE_COMPONENTS_H */
21 |
--------------------------------------------------------------------------------
/MDK-ARM/RTE/_STM32-IAP_HD_VL/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Component Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'IAP'
7 | * Target: 'STM32-IAP_HD_VL'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f10x.h"
18 |
19 |
20 | #endif /* RTE_COMPONENTS_H */
21 |
--------------------------------------------------------------------------------
/MDK-ARM/RTE/_STM32-IAP_MD/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Component Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'IAP-UART'
7 | * Target: 'STM32-IAP_MD'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f10x.h"
18 |
19 |
20 | #endif /* RTE_COMPONENTS_H */
21 |
--------------------------------------------------------------------------------
/MDK-ARM/main.c:
--------------------------------------------------------------------------------
1 | #include "common.h"
2 | #include "iap.h"
3 |
4 | int main(void)
5 | {
6 | IAP_Init();
7 |
8 | while(1)
9 | {
10 | switch(IAP_ReadFlag())
11 | {
12 | case APPRUN_FLAG_DATA://jump to app
13 | if( IAP_RunApp())
14 | IAP_WriteFlag(INIT_FLAG_DATA);
15 | break;
16 | case INIT_FLAG_DATA://initialze state (blank mcu)
17 | IAP_Main_Menu();
18 | break;
19 | case UPDATE_FLAG_DATA:// download app state
20 | if( !IAP_Update())
21 | IAP_WriteFlag(APPRUN_FLAG_DATA);
22 | else
23 | IAP_WriteFlag(INIT_FLAG_DATA);
24 | break;
25 | case UPLOAD_FLAG_DATA:// upload app state
26 | // if( !IAP_Upload())
27 | // IAP_WriteFlag(APPRUN_FLAG_DATA);
28 | // else
29 | // IAP_WriteFlag(INIT_FLAG_DATA);
30 | break;
31 | case ERASE_FLAG_DATA:// erase app state
32 | IAP_Erase();
33 | IAP_WriteFlag(INIT_FLAG_DATA);
34 | break;
35 | default:
36 | break;
37 | }
38 | }
39 | }
40 |
41 |
42 |
--------------------------------------------------------------------------------
/MDK-ARM/stm32f10x_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file IAP/inc/stm32f10x_conf.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 10/15/2010
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F10x_CONF_H
23 | #define __STM32F10x_CONF_H
24 |
25 | /* Includes ------------------------------------------------------------------*/
26 | /* Uncomment the line below to enable peripheral header file inclusion */
27 | /* #include "stm32f10x_adc.h" */
28 | #include "stm32f10x_bkp.h"
29 | /* #include "stm32f10x_can.h" */
30 | /* #include "stm32f10x_crc.h" */
31 | /* #include "stm32f10x_dac.h" */
32 | /* #include "stm32f10x_dbgmcu.h" */
33 | /* #include "stm32f10x_dma.h" */
34 | /* #include "stm32f10x_exti.h" */
35 | #include "stm32f10x_flash.h"
36 | /* #include "stm32f10x_fsmc.h" */
37 | #include "stm32f10x_gpio.h"
38 | /* #include "stm32f10x_i2c.h" */
39 | /* #include "stm32f10x_iwdg.h" */
40 | /* #include "stm32f10x_pwr.h" */
41 | #include "stm32f10x_rcc.h"
42 | /* #include "stm32f10x_rtc.h" */
43 | /* #include "stm32f10x_sdio.h" */
44 | /* #include "stm32f10x_spi.h" */
45 | /* #include "stm32f10x_tim.h" */
46 | #include "stm32f10x_usart.h"
47 | /* #include "stm32f10x_wwdg.h" */
48 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
49 |
50 | /* Exported types ------------------------------------------------------------*/
51 | /* Exported constants --------------------------------------------------------*/
52 | /* Uncomment the line below to expanse the "assert_param" macro in the
53 | Standard Peripheral Library drivers code */
54 | /* #define USE_FULL_ASSERT 1 */
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 | #ifdef USE_FULL_ASSERT
58 |
59 | /**
60 | * @brief The assert_param macro is used for function's parameters check.
61 | * @param expr: If expr is false, it calls assert_failed function
62 | * which reports the name of the source file and the source
63 | * line number of the call that failed.
64 | * If expr is true, it returns no value.
65 | * @retval None
66 | */
67 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
68 | /* Exported functions ------------------------------------------------------- */
69 | void assert_failed(uint8_t* file, uint32_t line);
70 | #else
71 | #define assert_param(expr) ((void)0)
72 | #endif /* USE_FULL_ASSERT */
73 |
74 | #endif /* __STM32F10x_CONF_H */
75 |
76 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
77 |
--------------------------------------------------------------------------------
/MDK-ARM/stm32f10x_it.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file IAP/src/stm32f10x_it.c
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 10/15/2010
7 | * @brief Main Interrupt Service Routines.
8 | * This file provides template for all exceptions handler and peripherals
9 | * interrupt service routine.
10 | ******************************************************************************
11 | * @copy
12 | *
13 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
15 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
16 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
17 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
18 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 | *
20 | * © COPYRIGHT 2010 STMicroelectronics
21 | */
22 |
23 | /* Includes ------------------------------------------------------------------*/
24 | #include "stm32f10x_it.h"
25 |
26 | /** @addtogroup IAP
27 | * @{
28 | */
29 |
30 | /* Private typedef -----------------------------------------------------------*/
31 | /* Private define ------------------------------------------------------------*/
32 | /* Private macro -------------------------------------------------------------*/
33 | /* Private variables ---------------------------------------------------------*/
34 | /* Private function prototypes -----------------------------------------------*/
35 | /* Private functions ---------------------------------------------------------*/
36 |
37 | /******************************************************************************/
38 | /* Cortex-M3 Processor Exceptions Handlers */
39 | /******************************************************************************/
40 |
41 | /**
42 | * @brief This function handles NMI exception.
43 | * @param None
44 | * @retval None
45 | */
46 | void NMI_Handler(void)
47 | {
48 | }
49 |
50 | /**
51 | * @brief This function handles Hard Fault exception.
52 | * @param None
53 | * @retval None
54 | */
55 | void HardFault_Handler(void)
56 | {
57 | /* Go to infinite loop when Hard Fault exception occurs */
58 | while (1)
59 | {
60 | }
61 | }
62 |
63 | /**
64 | * @brief This function handles Memory Manage exception.
65 | * @param None
66 | * @retval None
67 | */
68 | void MemManage_Handler(void)
69 | {
70 | /* Go to infinite loop when Memory Manage exception occurs */
71 | while (1)
72 | {
73 | }
74 | }
75 |
76 | /**
77 | * @brief This function handles Bus Fault exception.
78 | * @param None
79 | * @retval None
80 | */
81 | void BusFault_Handler(void)
82 | {
83 | /* Go to infinite loop when Bus Fault exception occurs */
84 | while (1)
85 | {
86 | }
87 | }
88 |
89 | /**
90 | * @brief This function handles Usage Fault exception.
91 | * @param None
92 | * @retval None
93 | */
94 | void UsageFault_Handler(void)
95 | {
96 | /* Go to infinite loop when Usage Fault exception occurs */
97 | while (1)
98 | {
99 | }
100 | }
101 |
102 | /**
103 | * @brief This function handles SVCall exception.
104 | * @param None
105 | * @retval None
106 | */
107 | void SVC_Handler(void)
108 | {
109 | }
110 |
111 | /**
112 | * @brief This function handles Debug Monitor exception.
113 | * @param None
114 | * @retval None
115 | */
116 | void DebugMon_Handler(void)
117 | {
118 | }
119 |
120 | /**
121 | * @brief This function handles PendSV_Handler exception.
122 | * @param None
123 | * @retval None
124 | */
125 | void PendSV_Handler(void)
126 | {
127 | }
128 |
129 | /**
130 | * @brief This function handles SysTick Handler.
131 | * @param None
132 | * @retval None
133 | */
134 | void SysTick_Handler(void)
135 | {
136 | }
137 |
138 | /******************************************************************************/
139 | /* STM32F10x Peripherals Interrupt Handlers */
140 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
141 | /* available peripheral interrupt handler's name please refer to the startup */
142 | /* file (startup_stm32f10x_xx.s). */
143 | /******************************************************************************/
144 |
145 | /**
146 | * @brief This function handles PPP interrupt request.
147 | * @param None
148 | * @retval None
149 | */
150 | /*void PPP_IRQHandler(void)
151 | {
152 | }*/
153 |
154 |
155 | /**
156 | * @}
157 | */
158 |
159 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
160 |
--------------------------------------------------------------------------------
/MDK-ARM/stm32f10x_it.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file IAP/inc/stm32f10x_it.h
4 | * @author MCD Application Team
5 | * @version V3.3.0
6 | * @date 10/15/2010
7 | * @brief This file contains the headers of the interrupt handlers.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F10x_IT_H
23 | #define __STM32F10x_IT_H
24 |
25 | /* Includes ------------------------------------------------------------------*/
26 | #include "stm32f10x.h"
27 |
28 | /* Exported types ------------------------------------------------------------*/
29 | /* Exported constants --------------------------------------------------------*/
30 | /* Exported macro ------------------------------------------------------------*/
31 | /* Exported functions ------------------------------------------------------- */
32 |
33 | void NMI_Handler(void);
34 | void HardFault_Handler(void);
35 | void MemManage_Handler(void);
36 | void BusFault_Handler(void);
37 | void UsageFault_Handler(void);
38 | void SVC_Handler(void);
39 | void DebugMon_Handler(void);
40 | void PendSV_Handler(void);
41 | void SysTick_Handler(void);
42 |
43 | #endif /* __STM32F10x_IT_H */
44 |
45 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
46 |
--------------------------------------------------------------------------------
/MDK-ARM/system_stm32f10x.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
8 | ******************************************************************************
9 | *
10 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
11 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
12 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
13 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
14 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
15 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
16 | *
17 | * © COPYRIGHT 2010 STMicroelectronics
18 | ******************************************************************************
19 | */
20 |
21 | /** @addtogroup CMSIS
22 | * @{
23 | */
24 |
25 | /** @addtogroup stm32f10x_system
26 | * @{
27 | */
28 |
29 | /**
30 | * @brief Define to prevent recursive inclusion
31 | */
32 | #ifndef __SYSTEM_STM32F10X_H
33 | #define __SYSTEM_STM32F10X_H
34 |
35 | #ifdef __cplusplus
36 | extern "C" {
37 | #endif
38 |
39 | /** @addtogroup STM32F10x_System_Includes
40 | * @{
41 | */
42 |
43 | /**
44 | * @}
45 | */
46 |
47 |
48 | /** @addtogroup STM32F10x_System_Exported_types
49 | * @{
50 | */
51 |
52 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @addtogroup STM32F10x_System_Exported_Constants
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @addtogroup STM32F10x_System_Exported_Macros
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @addtogroup STM32F10x_System_Exported_Functions
75 | * @{
76 | */
77 |
78 | extern void SystemInit(void);
79 | extern void SystemCoreClockUpdate(void);
80 | /**
81 | * @}
82 | */
83 |
84 | #ifdef __cplusplus
85 | }
86 | #endif
87 |
88 | #endif /*__SYSTEM_STM32F10X_H */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
98 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 |
2 | ## STM32串口IAP的boot部分使用说明
3 |
4 | 1. 该项目实现通过PC的串口对STM32系列MCU进行IAP。
5 |
6 | 2. 该项目包含三个部分（三套代码）：
7 |
8 | - 运行在STM32平台的Boot；
9 | - 运行在STM32平台的App(我做了两个，一个是支持usmart的重量版，一个是很简洁的轻量版)；
10 | - 运行在Windows平台的上位机操作工具。
11 |
12 | 3. 本篇是属于运行在STM32平台的Boot部分，另外两篇介绍请参阅：
13 |
14 | - [windows平台操作工具](https://github.com/havenxie/winapp-iap-uart)
15 | - [STM32平台的APP(支持USMART的版本)](https://github.com/havenxie/stm32-iap-uart-app)
16 | - [STM32平台的APP(轻量版)](https://github.com/havenxie/stm32-iap-uart-app_lite)
17 |
18 |
19 | 4. 该部分作为Boot可运行在多个STM32F10x系列：
20 |
21 | CL系列、XL系列、HD系列、HD_VL系列、MD系列、MD_VL系列、LD系列、LD_VL系列。
22 |
23 | 5. 这套代码几乎不用移植就可以用在你的项目上。只需要简单的根据你的项目配置工程。
24 |
25 | *****
26 |
27 | ## 准备工作：
28 |
29 | > 在开始使用之前请详细阅读下面关于STM32系列分类的介绍。
30 |
31 | ### STM32产品型号分类：
32 |
33 | - cl：互联型产品，stm32f105xx/107xx系列
34 | - vl：超值型产品，stm32f100系列
35 | - ld：低密度产品，FLASH = 16K/32K/没做
36 | - md：中等密度产品，FLASH = 64K/128k
37 | - hd：高密度产品，FLASH = 256K/384K/512K
38 | - xl：超高密度产品，FLASH = 768K/1024K(stm32f101/103)
39 |
40 | ### STM32启动文件分类：
41 |
42 | - startup_stm32f10x_cl.s：互联型的STM32F105xx，STM32F107xx
43 | - startup_stm32f10x_ld.s：小容量的STM32F101xx，STM32F102xx，STM32F103xx
44 | - startup_stm32f10x_ld_vl.s：小容量的STM32F100xx
45 | - startup_stm32f10x_md.s：中容量的STM32F101xx，STM32F102xx，STM32F103xx
46 | - startup_stm32f10x_md_vl.s：中容量的STM32F100xx
47 | - startup_stm32f10x_hd.s：大容量的STM32F101xx，STM32F102xx，STM32F103xx
48 | - startup_stm32f10x_hd_vl.s：大容量的STM32F100xx
49 | - startup_stm32f10x_xl.s：超大容量FLASH在512K到1024K字节的STM32F101xx，STM32F102xx，STM32F103xx
50 |
51 | ### STM32产品FLASH标识：
52 |
53 | - 8: 64K
54 | - B: 128K
55 | - C: 256K
56 | - D: 384K
57 | - E: 512K
58 | - F: 768K
59 | - G: 1024K
60 |
61 |
62 | *****
63 |
64 | ## 工程目录结构
65 |
66 | - "Binary": 包含将hex文件转换成bin文件的工具，你也可以不用这个工具，直接用Keil安装目录中的hex转bin工具。我在这里用了这个工具是因为每个人的安装目录不同，不可能做到一致，直接将转换工具放在项目中可以保证每个人都会有一致的效果。（这里我已经设置好了，使用者不必关心）
67 |
68 | - "CORE": STM32的启动文件和内核文件
69 |
70 | - "IAP": 实现IAP功能的主要函数都在这里
71 | ```
72 | inc/common.h 与硬件相关的配置及一些基础功能函数的头文件
73 | inc/iap.h 实现iap功能函数的头文件
74 | inc/iap_config.h IAP的配置文件（用户可以根据需求更改的文件）
75 | inc/stmflash.h 内部flash操作的函数的头文件
76 | inc/ymodem.h 实现Ymodem协议的函数的头文件
77 |
78 | ```
79 |
80 | - "IAP\src": 包含IAP固件的源文件
81 | ```
82 | src/common.c 与硬件相关的一些基础功能函数
83 | src/iap.c 实现iap各种功能的函数
84 | src/stmflash.c 内部flash操作的函数
85 | src/ymodem.c 实现Ymodem协议的函数
86 | ```
87 |
88 | - "MDK-ARM": KEIL的工程文件及user文件
89 |
90 | - "STM32F10X-FWLib": ST官方库文件
91 |
92 | - "keilkill": 用来清除中间文件的bat脚本，双击运行即可
93 |
94 | - "README": 自述文件
95 |
96 |
97 | *****
98 |
99 | ## 使用IAP工程的方法：
100 |
101 | 1. 打开MDK-ARM文件夹下的IAP.uvproj工程
102 |
103 | 2. 在工具栏(Select Target)中选择与你的硬件对应的型号:
104 |
105 | - STM32-IAP_MD_VL: 对应MD_VL设备
106 | - STM32-IAP_HD_VL: 对应HD_VL设备
107 | - STM32-IAP_CL: 对应CL设备
108 | - STM32-IAP_MD: 对应MD设备
109 | - STM32-IAP_HD: 对应HD设备
110 | - STM32-IAP_XL: 对应XL设备
111 |
112 | 3. 在iap_config.h文件中设置你的用户应用程序(app)的起始地址ApplicationAddress（我这里是0x8003000) 。设置用来存储标志信息的flash地址IAP_FLASH_FLAG_ADDR（我这里的是0x8002800，即0X8003000-2KByte）
113 |
114 | 4. 在option->target->1ROM中设置boot的起始地址是0x8000000，设置你为boot分配的flash空间大小（我这里是0x3000）。通过第三项和第四项的设置你会知道，我把flash在逻辑上分为3个部分：
115 |
116 | + 第一部分分了10KByte，用来存储boot的代码；
117 | + 第二部分分了2KByte，用来存储一些用于状态标志的数据（用户也可以把一些数据信息保留在这里，只要不放在该区域的前两个字节即可）
118 | + 剩余的部分都是用来存储用户应用程序的。也就是说你还有（flash总大小 - 12KByte）的空间可以使用。
119 |
120 | 5. 编译工程，会在MDK-ARM -> OUTPUT 文件夹下生成与你的硬件平台相对应的文件夹，在这里面就会有hex文件和bin文件。
121 |
122 | 6. 通过JLINK或者STlINK或者uart下载目标文件到你的硬件平台。
123 |
124 | 7. 使mcu运行起来。
125 |
126 | 8. 打开上位机工具，通过串口和MCU进行连接。
127 |
128 | 9. 选择需要烧入用户应用程序（[应用程序app的设置请点击此处](https://github.com/havenxie/stm32-iap-uart-app) ）。
129 |
130 | 10. 根据你的需求选择更新app、读出app、擦除app、app进入iap模式、复位运行app等操作。
131 |
132 | 注：boot部分只需要烧录一次即可，之后所有操作都通过上位机工具完成。
133 |
134 |
135 | *****
136 |
137 | ## 上位机工具配置（可修改switch-case选项以兼容超级终端）：
138 |
139 | + 数据位长度 = 8 Bits
140 | + 1位停止位
141 | + 无校验位
142 | + 波特率 = 115200 baud（根据你的项目需求选择合适的波特率）
143 | + 硬件流控: None
144 | + “包长度”指的是数据传输过程中每一包的长度。可根据你的需要选择合适的包长度。
145 |
146 | *****
147 |
148 | ## 版本说明：
149 | - level00: 官方版本首次跑通。
150 | - level01: 抽象硬件平台，
151 | + 修改输出文件
152 | + 根据MCU的类别(暂实现6种)选择工程的配置，而不是根据开发版选择硬件平台
153 | + 使boot和app识别相同的指令。
154 | - level02：处理不同情况下各功能之间跳转。
155 | - level03:
156 | + 完成update和erase部分。
157 | + first completed except upload
158 | - level04:
159 | + 裁剪工程大小
160 | + 重新构建工程结构
161 | + 添加.bat文件
162 |
163 | - 用户使用master版本即可。
164 |
165 |
166 | *****
167 |
168 | ## 更新说明：
169 |
170 | > 代码时隔一年多再次更新，增加了通过后备寄存器来存储各种状态标志，使用方法见下：
171 |
172 | 选择iap_config.h文件中的`define USE_BKP_SAVE_FLAG 1 //1:使用后备寄存器存储flag标志，0:使用flash存储flag标志（之前的版本就是这样）`
173 | 注意app部分的USE_BKP_SAVE_FLAG值要和boot保持一致
174 |
175 |
176 |
177 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/misc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file misc.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the miscellaneous
8 | * firmware library functions (add-on to CMSIS functions).
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MISC_H
24 | #define __MISC_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup MISC
38 | * @{
39 | */
40 |
41 | /** @defgroup MISC_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief NVIC Init Structure definition
47 | */
48 |
49 | typedef struct
50 | {
51 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
52 | This parameter can be a value of @ref IRQn_Type
53 | (For the complete STM32 Devices IRQ Channels list, please
54 | refer to stm32f10x.h file) */
55 |
56 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
57 | specified in NVIC_IRQChannel. This parameter can be a value
58 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */
59 |
60 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
61 | in NVIC_IRQChannel. This parameter can be a value
62 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */
63 |
64 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
65 | will be enabled or disabled.
66 | This parameter can be set either to ENABLE or DISABLE */
67 | } NVIC_InitTypeDef;
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /** @defgroup NVIC_Priority_Table
74 | * @{
75 | */
76 |
77 | /**
78 | @code
79 | The table below gives the allowed values of the pre-emption priority and subpriority according
80 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
81 | ============================================================================================================================
82 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
83 | ============================================================================================================================
84 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
85 | | | | 4 bits for subpriority
86 | ----------------------------------------------------------------------------------------------------------------------------
87 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
88 | | | | 3 bits for subpriority
89 | ----------------------------------------------------------------------------------------------------------------------------
90 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
91 | | | | 2 bits for subpriority
92 | ----------------------------------------------------------------------------------------------------------------------------
93 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
94 | | | | 1 bits for subpriority
95 | ----------------------------------------------------------------------------------------------------------------------------
96 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
97 | | | | 0 bits for subpriority
98 | ============================================================================================================================
99 | @endcode
100 | */
101 |
102 | /**
103 | * @}
104 | */
105 |
106 | /** @defgroup MISC_Exported_Constants
107 | * @{
108 | */
109 |
110 | /** @defgroup Vector_Table_Base
111 | * @{
112 | */
113 |
114 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
115 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
116 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
117 | ((VECTTAB) == NVIC_VectTab_FLASH))
118 | /**
119 | * @}
120 | */
121 |
122 | /** @defgroup System_Low_Power
123 | * @{
124 | */
125 |
126 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
127 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
128 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
129 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
130 | ((LP) == NVIC_LP_SLEEPDEEP) || \
131 | ((LP) == NVIC_LP_SLEEPONEXIT))
132 | /**
133 | * @}
134 | */
135 |
136 | /** @defgroup Preemption_Priority_Group
137 | * @{
138 | */
139 |
140 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
141 | 4 bits for subpriority */
142 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
143 | 3 bits for subpriority */
144 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
145 | 2 bits for subpriority */
146 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
147 | 1 bits for subpriority */
148 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
149 | 0 bits for subpriority */
150 |
151 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
152 | ((GROUP) == NVIC_PriorityGroup_1) || \
153 | ((GROUP) == NVIC_PriorityGroup_2) || \
154 | ((GROUP) == NVIC_PriorityGroup_3) || \
155 | ((GROUP) == NVIC_PriorityGroup_4))
156 |
157 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
158 |
159 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
160 |
161 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
162 |
163 | /**
164 | * @}
165 | */
166 |
167 | /** @defgroup SysTick_clock_source
168 | * @{
169 | */
170 |
171 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
172 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
173 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
174 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
175 | /**
176 | * @}
177 | */
178 |
179 | /**
180 | * @}
181 | */
182 |
183 | /** @defgroup MISC_Exported_Macros
184 | * @{
185 | */
186 |
187 | /**
188 | * @}
189 | */
190 |
191 | /** @defgroup MISC_Exported_Functions
192 | * @{
193 | */
194 |
195 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
196 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
197 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
198 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
200 |
201 | #ifdef __cplusplus
202 | }
203 | #endif
204 |
205 | #endif /* __MISC_H */
206 |
207 | /**
208 | * @}
209 | */
210 |
211 | /**
212 | * @}
213 | */
214 |
215 | /**
216 | * @}
217 | */
218 |
219 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
220 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_bkp.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_bkp.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the BKP firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_BKP_H
24 | #define __STM32F10x_BKP_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup BKP
38 | * @{
39 | */
40 |
41 | /** @defgroup BKP_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup BKP_Exported_Constants
50 | * @{
51 | */
52 |
53 | /** @defgroup Tamper_Pin_active_level
54 | * @{
55 | */
56 |
57 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000)
58 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
59 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
60 | ((LEVEL) == BKP_TamperPinLevel_Low))
61 | /**
62 | * @}
63 | */
64 |
65 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
66 | * @{
67 | */
68 |
69 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000)
70 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
71 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
72 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
73 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
74 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
75 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
76 | ((SOURCE) == BKP_RTCOutputSource_Second))
77 | /**
78 | * @}
79 | */
80 |
81 | /** @defgroup Data_Backup_Register
82 | * @{
83 | */
84 |
85 | #define BKP_DR1 ((uint16_t)0x0004)
86 | #define BKP_DR2 ((uint16_t)0x0008)
87 | #define BKP_DR3 ((uint16_t)0x000C)
88 | #define BKP_DR4 ((uint16_t)0x0010)
89 | #define BKP_DR5 ((uint16_t)0x0014)
90 | #define BKP_DR6 ((uint16_t)0x0018)
91 | #define BKP_DR7 ((uint16_t)0x001C)
92 | #define BKP_DR8 ((uint16_t)0x0020)
93 | #define BKP_DR9 ((uint16_t)0x0024)
94 | #define BKP_DR10 ((uint16_t)0x0028)
95 | #define BKP_DR11 ((uint16_t)0x0040)
96 | #define BKP_DR12 ((uint16_t)0x0044)
97 | #define BKP_DR13 ((uint16_t)0x0048)
98 | #define BKP_DR14 ((uint16_t)0x004C)
99 | #define BKP_DR15 ((uint16_t)0x0050)
100 | #define BKP_DR16 ((uint16_t)0x0054)
101 | #define BKP_DR17 ((uint16_t)0x0058)
102 | #define BKP_DR18 ((uint16_t)0x005C)
103 | #define BKP_DR19 ((uint16_t)0x0060)
104 | #define BKP_DR20 ((uint16_t)0x0064)
105 | #define BKP_DR21 ((uint16_t)0x0068)
106 | #define BKP_DR22 ((uint16_t)0x006C)
107 | #define BKP_DR23 ((uint16_t)0x0070)
108 | #define BKP_DR24 ((uint16_t)0x0074)
109 | #define BKP_DR25 ((uint16_t)0x0078)
110 | #define BKP_DR26 ((uint16_t)0x007C)
111 | #define BKP_DR27 ((uint16_t)0x0080)
112 | #define BKP_DR28 ((uint16_t)0x0084)
113 | #define BKP_DR29 ((uint16_t)0x0088)
114 | #define BKP_DR30 ((uint16_t)0x008C)
115 | #define BKP_DR31 ((uint16_t)0x0090)
116 | #define BKP_DR32 ((uint16_t)0x0094)
117 | #define BKP_DR33 ((uint16_t)0x0098)
118 | #define BKP_DR34 ((uint16_t)0x009C)
119 | #define BKP_DR35 ((uint16_t)0x00A0)
120 | #define BKP_DR36 ((uint16_t)0x00A4)
121 | #define BKP_DR37 ((uint16_t)0x00A8)
122 | #define BKP_DR38 ((uint16_t)0x00AC)
123 | #define BKP_DR39 ((uint16_t)0x00B0)
124 | #define BKP_DR40 ((uint16_t)0x00B4)
125 | #define BKP_DR41 ((uint16_t)0x00B8)
126 | #define BKP_DR42 ((uint16_t)0x00BC)
127 |
128 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
129 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
130 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
131 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
132 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
133 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
134 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
135 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
136 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
137 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
138 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
139 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
140 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
141 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
142 |
143 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
144 | /**
145 | * @}
146 | */
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /** @defgroup BKP_Exported_Macros
153 | * @{
154 | */
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /** @defgroup BKP_Exported_Functions
161 | * @{
162 | */
163 |
164 | void BKP_DeInit(void);
165 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
166 | void BKP_TamperPinCmd(FunctionalState NewState);
167 | void BKP_ITConfig(FunctionalState NewState);
168 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
169 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
170 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
171 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
172 | FlagStatus BKP_GetFlagStatus(void);
173 | void BKP_ClearFlag(void);
174 | ITStatus BKP_GetITStatus(void);
175 | void BKP_ClearITPendingBit(void);
176 |
177 | #ifdef __cplusplus
178 | }
179 | #endif
180 |
181 | #endif /* __STM32F10x_BKP_H */
182 | /**
183 | * @}
184 | */
185 |
186 | /**
187 | * @}
188 | */
189 |
190 | /**
191 | * @}
192 | */
193 |
194 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
195 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_cec.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_cec.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the CEC firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CEC_H
24 | #define __STM32F10x_CEC_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup CEC
38 | * @{
39 | */
40 |
41 |
42 | /** @defgroup CEC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief CEC Init structure definition
48 | */
49 | typedef struct
50 | {
51 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
52 | This parameter can be a value of @ref CEC_BitTiming_Mode */
53 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
54 | This parameter can be a value of @ref CEC_BitPeriod_Mode */
55 | }CEC_InitTypeDef;
56 |
57 | /**
58 | * @}
59 | */
60 |
61 | /** @defgroup CEC_Exported_Constants
62 | * @{
63 | */
64 |
65 | /** @defgroup CEC_BitTiming_Mode
66 | * @{
67 | */
68 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
69 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
70 |
71 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
72 | ((MODE) == CEC_BitTimingErrFreeMode))
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup CEC_BitPeriod_Mode
78 | * @{
79 | */
80 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
81 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
82 |
83 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
84 | ((MODE) == CEC_BitPeriodFlexibleMode))
85 | /**
86 | * @}
87 | */
88 |
89 |
90 | /** @defgroup CEC_interrupts_definition
91 | * @{
92 | */
93 | #define CEC_IT_TERR CEC_CSR_TERR
94 | #define CEC_IT_TBTRF CEC_CSR_TBTRF
95 | #define CEC_IT_RERR CEC_CSR_RERR
96 | #define CEC_IT_RBTF CEC_CSR_RBTF
97 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
98 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
99 | /**
100 | * @}
101 | */
102 |
103 |
104 | /** @defgroup CEC_Own_Addres
105 | * @{
106 | */
107 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
108 | /**
109 | * @}
110 | */
111 |
112 | /** @defgroup CEC_Prescaler
113 | * @{
114 | */
115 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /** @defgroup CEC_flags_definition
122 | * @{
123 | */
124 |
125 | /**
126 | * @brief ESR register flags
127 | */
128 | #define CEC_FLAG_BTE ((uint32_t)0x10010000)
129 | #define CEC_FLAG_BPE ((uint32_t)0x10020000)
130 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
131 | #define CEC_FLAG_SBE ((uint32_t)0x10080000)
132 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000)
133 | #define CEC_FLAG_LINE ((uint32_t)0x10200000)
134 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
135 |
136 | /**
137 | * @brief CSR register flags
138 | */
139 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002)
140 | #define CEC_FLAG_TERR ((uint32_t)0x00000004)
141 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
142 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010)
143 | #define CEC_FLAG_REOM ((uint32_t)0x00000020)
144 | #define CEC_FLAG_RERR ((uint32_t)0x00000040)
145 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080)
146 |
147 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
148 |
149 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
150 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
151 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
152 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
153 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
154 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
155 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | /** @defgroup CEC_Exported_Macros
166 | * @{
167 | */
168 |
169 | /**
170 | * @}
171 | */
172 |
173 | /** @defgroup CEC_Exported_Functions
174 | * @{
175 | */
176 | void CEC_DeInit(void);
177 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
178 | void CEC_Cmd(FunctionalState NewState);
179 | void CEC_ITConfig(FunctionalState NewState);
180 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
181 | void CEC_SetPrescaler(uint16_t CEC_Prescaler);
182 | void CEC_SendDataByte(uint8_t Data);
183 | uint8_t CEC_ReceiveDataByte(void);
184 | void CEC_StartOfMessage(void);
185 | void CEC_EndOfMessageCmd(FunctionalState NewState);
186 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
187 | void CEC_ClearFlag(uint32_t CEC_FLAG);
188 | ITStatus CEC_GetITStatus(uint8_t CEC_IT);
189 | void CEC_ClearITPendingBit(uint16_t CEC_IT);
190 |
191 | #ifdef __cplusplus
192 | }
193 | #endif
194 |
195 | #endif /* __STM32F10x_CEC_H */
196 |
197 | /**
198 | * @}
199 | */
200 |
201 | /**
202 | * @}
203 | */
204 |
205 | /**
206 | * @}
207 | */
208 |
209 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
210 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CRC_H
24 | #define __STM32F10x_CRC_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup CRC
38 | * @{
39 | */
40 |
41 | /** @defgroup CRC_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup CRC_Exported_Constants
50 | * @{
51 | */
52 |
53 | /**
54 | * @}
55 | */
56 |
57 | /** @defgroup CRC_Exported_Macros
58 | * @{
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /** @defgroup CRC_Exported_Functions
66 | * @{
67 | */
68 |
69 | void CRC_ResetDR(void);
70 | uint32_t CRC_CalcCRC(uint32_t Data);
71 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
72 | uint32_t CRC_GetCRC(void);
73 | void CRC_SetIDRegister(uint8_t IDValue);
74 | uint8_t CRC_GetIDRegister(void);
75 |
76 | #ifdef __cplusplus
77 | }
78 | #endif
79 |
80 | #endif /* __STM32F10x_CRC_H */
81 | /**
82 | * @}
83 | */
84 |
85 | /**
86 | * @}
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
94 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the DBGMCU
8 | * firmware library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_DBGMCU_H
24 | #define __STM32F10x_DBGMCU_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup DBGMCU
38 | * @{
39 | */
40 |
41 | /** @defgroup DBGMCU_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup DBGMCU_Exported_Constants
50 | * @{
51 | */
52 |
53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
54 | #define DBGMCU_STOP ((uint32_t)0x00000002)
55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
56 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
57 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
58 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
59 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
60 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
61 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
62 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
63 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
64 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
65 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
66 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
67 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
68 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
69 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
70 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
71 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
72 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
73 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
74 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
75 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
76 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
77 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
78 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
79 |
80 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
81 | /**
82 | * @}
83 | */
84 |
85 | /** @defgroup DBGMCU_Exported_Macros
86 | * @{
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /** @defgroup DBGMCU_Exported_Functions
94 | * @{
95 | */
96 |
97 | uint32_t DBGMCU_GetREVID(void);
98 | uint32_t DBGMCU_GetDEVID(void);
99 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
100 |
101 | #ifdef __cplusplus
102 | }
103 | #endif
104 |
105 | #endif /* __STM32F10x_DBGMCU_H */
106 | /**
107 | * @}
108 | */
109 |
110 | /**
111 | * @}
112 | */
113 |
114 | /**
115 | * @}
116 | */
117 |
118 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
119 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_exti.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the EXTI firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_EXTI_H
24 | #define __STM32F10x_EXTI_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup EXTI
38 | * @{
39 | */
40 |
41 | /** @defgroup EXTI_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief EXTI mode enumeration
47 | */
48 |
49 | typedef enum
50 | {
51 | EXTI_Mode_Interrupt = 0x00,
52 | EXTI_Mode_Event = 0x04
53 | }EXTIMode_TypeDef;
54 |
55 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
56 |
57 | /**
58 | * @brief EXTI Trigger enumeration
59 | */
60 |
61 | typedef enum
62 | {
63 | EXTI_Trigger_Rising = 0x08,
64 | EXTI_Trigger_Falling = 0x0C,
65 | EXTI_Trigger_Rising_Falling = 0x10
66 | }EXTITrigger_TypeDef;
67 |
68 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
69 | ((TRIGGER) == EXTI_Trigger_Falling) || \
70 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
71 | /**
72 | * @brief EXTI Init Structure definition
73 | */
74 |
75 | typedef struct
76 | {
77 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
78 | This parameter can be any combination of @ref EXTI_Lines */
79 |
80 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
81 | This parameter can be a value of @ref EXTIMode_TypeDef */
82 |
83 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
84 | This parameter can be a value of @ref EXTIMode_TypeDef */
85 |
86 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
87 | This parameter can be set either to ENABLE or DISABLE */
88 | }EXTI_InitTypeDef;
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup EXTI_Exported_Constants
95 | * @{
96 | */
97 |
98 | /** @defgroup EXTI_Lines
99 | * @{
100 | */
101 |
102 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
103 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
104 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
105 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
106 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
107 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
108 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
109 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
110 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
111 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
112 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
113 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
114 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
115 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
116 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
117 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
118 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
119 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
120 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
121 | Wakeup from suspend event */
122 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
123 |
124 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
125 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
126 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
127 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
128 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
129 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
130 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
131 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
132 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
133 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
134 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
135 |
136 |
137 | /**
138 | * @}
139 | */
140 |
141 | /**
142 | * @}
143 | */
144 |
145 | /** @defgroup EXTI_Exported_Macros
146 | * @{
147 | */
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /** @defgroup EXTI_Exported_Functions
154 | * @{
155 | */
156 |
157 | void EXTI_DeInit(void);
158 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
159 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
160 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
161 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
162 | void EXTI_ClearFlag(uint32_t EXTI_Line);
163 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
164 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
165 |
166 | #ifdef __cplusplus
167 | }
168 | #endif
169 |
170 | #endif /* __STM32F10x_EXTI_H */
171 | /**
172 | * @}
173 | */
174 |
175 | /**
176 | * @}
177 | */
178 |
179 | /**
180 | * @}
181 | */
182 |
183 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
184 |
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/STM32F10x_FWLib/inc/stm32f10x_fsmc.h:
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https://raw.githubusercontent.com/havenxie/stm32-iap-uart-boot/1d2c88670b2e471043e92c09f2b016d18fd30ebb/STM32F10x_FWLib/inc/stm32f10x_fsmc.h
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/STM32F10x_FWLib/inc/stm32f10x_iwdg.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_IWDG_H
24 | #define __STM32F10x_IWDG_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup IWDG
38 | * @{
39 | */
40 |
41 | /** @defgroup IWDG_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup IWDG_Exported_Constants
50 | * @{
51 | */
52 |
53 | /** @defgroup IWDG_WriteAccess
54 | * @{
55 | */
56 |
57 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
58 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
59 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
60 | ((ACCESS) == IWDG_WriteAccess_Disable))
61 | /**
62 | * @}
63 | */
64 |
65 | /** @defgroup IWDG_prescaler
66 | * @{
67 | */
68 |
69 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
70 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
71 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
72 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
73 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
74 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
75 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
76 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
77 | ((PRESCALER) == IWDG_Prescaler_8) || \
78 | ((PRESCALER) == IWDG_Prescaler_16) || \
79 | ((PRESCALER) == IWDG_Prescaler_32) || \
80 | ((PRESCALER) == IWDG_Prescaler_64) || \
81 | ((PRESCALER) == IWDG_Prescaler_128)|| \
82 | ((PRESCALER) == IWDG_Prescaler_256))
83 | /**
84 | * @}
85 | */
86 |
87 | /** @defgroup IWDG_Flag
88 | * @{
89 | */
90 |
91 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
92 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
93 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
94 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
95 | /**
96 | * @}
97 | */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup IWDG_Exported_Macros
104 | * @{
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /** @defgroup IWDG_Exported_Functions
112 | * @{
113 | */
114 |
115 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
116 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
117 | void IWDG_SetReload(uint16_t Reload);
118 | void IWDG_ReloadCounter(void);
119 | void IWDG_Enable(void);
120 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
121 |
122 | #ifdef __cplusplus
123 | }
124 | #endif
125 |
126 | #endif /* __STM32F10x_IWDG_H */
127 | /**
128 | * @}
129 | */
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | /**
136 | * @}
137 | */
138 |
139 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
140 |
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/STM32F10x_FWLib/inc/stm32f10x_pwr.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_PWR_H
24 | #define __STM32F10x_PWR_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup PWR
38 | * @{
39 | */
40 |
41 | /** @defgroup PWR_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup PWR_Exported_Constants
50 | * @{
51 | */
52 |
53 | /** @defgroup PVD_detection_level
54 | * @{
55 | */
56 |
57 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
58 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
59 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
60 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
61 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
62 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
63 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
64 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
65 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
66 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
67 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
68 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
69 | /**
70 | * @}
71 | */
72 |
73 | /** @defgroup Regulator_state_is_STOP_mode
74 | * @{
75 | */
76 |
77 | #define PWR_Regulator_ON ((uint32_t)0x00000000)
78 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001)
79 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
80 | ((REGULATOR) == PWR_Regulator_LowPower))
81 | /**
82 | * @}
83 | */
84 |
85 | /** @defgroup STOP_mode_entry
86 | * @{
87 | */
88 |
89 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
90 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
91 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | /** @defgroup PWR_Flag
98 | * @{
99 | */
100 |
101 | #define PWR_FLAG_WU ((uint32_t)0x00000001)
102 | #define PWR_FLAG_SB ((uint32_t)0x00000002)
103 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
104 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
105 | ((FLAG) == PWR_FLAG_PVDO))
106 |
107 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
108 | /**
109 | * @}
110 | */
111 |
112 | /**
113 | * @}
114 | */
115 |
116 | /** @defgroup PWR_Exported_Macros
117 | * @{
118 | */
119 |
120 | /**
121 | * @}
122 | */
123 |
124 | /** @defgroup PWR_Exported_Functions
125 | * @{
126 | */
127 |
128 | void PWR_DeInit(void);
129 | void PWR_BackupAccessCmd(FunctionalState NewState);
130 | void PWR_PVDCmd(FunctionalState NewState);
131 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
132 | void PWR_WakeUpPinCmd(FunctionalState NewState);
133 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
134 | void PWR_EnterSTANDBYMode(void);
135 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
136 | void PWR_ClearFlag(uint32_t PWR_FLAG);
137 |
138 | #ifdef __cplusplus
139 | }
140 | #endif
141 |
142 | #endif /* __STM32F10x_PWR_H */
143 | /**
144 | * @}
145 | */
146 |
147 | /**
148 | * @}
149 | */
150 |
151 | /**
152 | * @}
153 | */
154 |
155 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
156 |
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/STM32F10x_FWLib/inc/stm32f10x_rtc.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rtc.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the RTC firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_RTC_H
24 | #define __STM32F10x_RTC_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup RTC
38 | * @{
39 | */
40 |
41 | /** @defgroup RTC_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup RTC_Exported_Constants
50 | * @{
51 | */
52 |
53 | /** @defgroup RTC_interrupts_define
54 | * @{
55 | */
56 |
57 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
58 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
59 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
60 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
61 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
62 | ((IT) == RTC_IT_SEC))
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup RTC_interrupts_flags
68 | * @{
69 | */
70 |
71 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
72 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
73 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
74 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
75 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
76 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
77 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
78 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
79 | ((FLAG) == RTC_FLAG_SEC))
80 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
81 |
82 | /**
83 | * @}
84 | */
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /** @defgroup RTC_Exported_Macros
91 | * @{
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup RTC_Exported_Functions
99 | * @{
100 | */
101 |
102 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
103 | void RTC_EnterConfigMode(void);
104 | void RTC_ExitConfigMode(void);
105 | uint32_t RTC_GetCounter(void);
106 | void RTC_SetCounter(uint32_t CounterValue);
107 | void RTC_SetPrescaler(uint32_t PrescalerValue);
108 | void RTC_SetAlarm(uint32_t AlarmValue);
109 | uint32_t RTC_GetDivider(void);
110 | void RTC_WaitForLastTask(void);
111 | void RTC_WaitForSynchro(void);
112 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
113 | void RTC_ClearFlag(uint16_t RTC_FLAG);
114 | ITStatus RTC_GetITStatus(uint16_t RTC_IT);
115 | void RTC_ClearITPendingBit(uint16_t RTC_IT);
116 |
117 | #ifdef __cplusplus
118 | }
119 | #endif
120 |
121 | #endif /* __STM32F10x_RTC_H */
122 | /**
123 | * @}
124 | */
125 |
126 | /**
127 | * @}
128 | */
129 |
130 | /**
131 | * @}
132 | */
133 |
134 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
135 |
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/STM32F10x_FWLib/inc/stm32f10x_wwdg.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.h
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file contains all the functions prototypes for the WWDG firmware
8 | * library.
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_WWDG_H
24 | #define __STM32F10x_WWDG_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /** @addtogroup STM32F10x_StdPeriph_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup WWDG
38 | * @{
39 | */
40 |
41 | /** @defgroup WWDG_Exported_Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup WWDG_Exported_Constants
50 | * @{
51 | */
52 |
53 | /** @defgroup WWDG_Prescaler
54 | * @{
55 | */
56 |
57 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
58 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
59 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
60 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
61 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
62 | ((PRESCALER) == WWDG_Prescaler_2) || \
63 | ((PRESCALER) == WWDG_Prescaler_4) || \
64 | ((PRESCALER) == WWDG_Prescaler_8))
65 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
66 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
67 |
68 | /**
69 | * @}
70 | */
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup WWDG_Exported_Macros
77 | * @{
78 | */
79 | /**
80 | * @}
81 | */
82 |
83 | /** @defgroup WWDG_Exported_Functions
84 | * @{
85 | */
86 |
87 | void WWDG_DeInit(void);
88 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
89 | void WWDG_SetWindowValue(uint8_t WindowValue);
90 | void WWDG_EnableIT(void);
91 | void WWDG_SetCounter(uint8_t Counter);
92 | void WWDG_Enable(uint8_t Counter);
93 | FlagStatus WWDG_GetFlagStatus(void);
94 | void WWDG_ClearFlag(void);
95 |
96 | #ifdef __cplusplus
97 | }
98 | #endif
99 |
100 | #endif /* __STM32F10x_WWDG_H */
101 |
102 | /**
103 | * @}
104 | */
105 |
106 | /**
107 | * @}
108 | */
109 |
110 | /**
111 | * @}
112 | */
113 |
114 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
115 |
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/STM32F10x_FWLib/src/misc.c:
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1 | /**
2 | ******************************************************************************
3 | * @file misc.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the miscellaneous firmware functions (add-on
8 | * to CMSIS functions).
9 | ******************************************************************************
10 | * @copy
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2010 STMicroelectronics
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "misc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup MISC
30 | * @brief MISC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup MISC_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup MISC_Private_Defines
43 | * @{
44 | */
45 |
46 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
47 | /**
48 | * @}
49 | */
50 |
51 | /** @defgroup MISC_Private_Macros
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @defgroup MISC_Private_Variables
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup MISC_Private_FunctionPrototypes
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup MISC_Private_Functions
76 | * @{
77 | */
78 |
79 | /**
80 | * @brief Configures the priority grouping: pre-emption priority and subpriority.
81 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
82 | * This parameter can be one of the following values:
83 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
84 | * 4 bits for subpriority
85 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
86 | * 3 bits for subpriority
87 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
88 | * 2 bits for subpriority
89 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
90 | * 1 bits for subpriority
91 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
92 | * 0 bits for subpriority
93 | * @retval None
94 | */
95 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
96 | {
97 | /* Check the parameters */
98 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
99 |
100 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
101 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
102 | }
103 |
104 | /**
105 | * @brief Initializes the NVIC peripheral according to the specified
106 | * parameters in the NVIC_InitStruct.
107 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
108 | * the configuration information for the specified NVIC peripheral.
109 | * @retval None
110 | */
111 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
112 | {
113 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
114 |
115 | /* Check the parameters */
116 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
117 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
118 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
119 |
120 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
121 | {
122 | /* Compute the Corresponding IRQ Priority --------------------------------*/
123 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
124 | tmppre = (0x4 - tmppriority);
125 | tmpsub = tmpsub >> tmppriority;
126 |
127 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
128 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
129 | tmppriority = tmppriority << 0x04;
130 |
131 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
132 |
133 | /* Enable the Selected IRQ Channels --------------------------------------*/
134 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
135 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
136 | }
137 | else
138 | {
139 | /* Disable the Selected IRQ Channels -------------------------------------*/
140 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
141 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
142 | }
143 | }
144 |
145 | /**
146 | * @brief Sets the vector table location and Offset.
147 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
148 | * This parameter can be one of the following values:
149 | * @arg NVIC_VectTab_RAM
150 | * @arg NVIC_VectTab_FLASH
151 | * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.
152 | * @retval None
153 | */
154 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
155 | {
156 | /* Check the parameters */
157 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
158 | assert_param(IS_NVIC_OFFSET(Offset));
159 |
160 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
161 | }
162 |
163 | /**
164 | * @brief Selects the condition for the system to enter low power mode.
165 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
166 | * This parameter can be one of the following values:
167 | * @arg NVIC_LP_SEVONPEND
168 | * @arg NVIC_LP_SLEEPDEEP
169 | * @arg NVIC_LP_SLEEPONEXIT
170 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
171 | * @retval None
172 | */
173 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
174 | {
175 | /* Check the parameters */
176 | assert_param(IS_NVIC_LP(LowPowerMode));
177 | assert_param(IS_FUNCTIONAL_STATE(NewState));
178 |
179 | if (NewState != DISABLE)
180 | {
181 | SCB->SCR |= LowPowerMode;
182 | }
183 | else
184 | {
185 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
186 | }
187 | }
188 |
189 | /**
190 | * @brief Configures the SysTick clock source.
191 | * @param SysTick_CLKSource: specifies the SysTick clock source.
192 | * This parameter can be one of the following values:
193 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
194 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
195 | * @retval None
196 | */
197 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
198 | {
199 | /* Check the parameters */
200 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
201 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
202 | {
203 | SysTick->CTRL |= SysTick_CLKSource_HCLK;
204 | }
205 | else
206 | {
207 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
208 | }
209 | }
210 |
211 | /**
212 | * @}
213 | */
214 |
215 | /**
216 | * @}
217 | */
218 |
219 | /**
220 | * @}
221 | */
222 |
223 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
224 |
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/STM32F10x_FWLib/src/stm32f10x_adc.c:
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/STM32F10x_FWLib/src/stm32f10x_bkp.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_bkp.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the BKP firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_bkp.h"
23 | #include "stm32f10x_rcc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup BKP
30 | * @brief BKP driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup BKP_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup BKP_Private_Defines
43 | * @{
44 | */
45 |
46 | /* ------------ BKP registers bit address in the alias region --------------- */
47 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
48 |
49 | /* --- CR Register ----*/
50 |
51 | /* Alias word address of TPAL bit */
52 | #define CR_OFFSET (BKP_OFFSET + 0x30)
53 | #define TPAL_BitNumber 0x01
54 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
55 |
56 | /* Alias word address of TPE bit */
57 | #define TPE_BitNumber 0x00
58 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
59 |
60 | /* --- CSR Register ---*/
61 |
62 | /* Alias word address of TPIE bit */
63 | #define CSR_OFFSET (BKP_OFFSET + 0x34)
64 | #define TPIE_BitNumber 0x02
65 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
66 |
67 | /* Alias word address of TIF bit */
68 | #define TIF_BitNumber 0x09
69 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
70 |
71 | /* Alias word address of TEF bit */
72 | #define TEF_BitNumber 0x08
73 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
74 |
75 | /* ---------------------- BKP registers bit mask ------------------------ */
76 |
77 | /* RTCCR register bit mask */
78 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80)
79 | #define RTCCR_MASK ((uint16_t)0xFC7F)
80 |
81 | /**
82 | * @}
83 | */
84 |
85 |
86 | /** @defgroup BKP_Private_Macros
87 | * @{
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup BKP_Private_Variables
95 | * @{
96 | */
97 |
98 | /**
99 | * @}
100 | */
101 |
102 | /** @defgroup BKP_Private_FunctionPrototypes
103 | * @{
104 | */
105 |
106 | /**
107 | * @}
108 | */
109 |
110 | /** @defgroup BKP_Private_Functions
111 | * @{
112 | */
113 |
114 | /**
115 | * @brief Deinitializes the BKP peripheral registers to their default reset values.
116 | * @param None
117 | * @retval None
118 | */
119 | void BKP_DeInit(void)
120 | {
121 | RCC_BackupResetCmd(ENABLE);
122 | RCC_BackupResetCmd(DISABLE);
123 | }
124 |
125 | /**
126 | * @brief Configures the Tamper Pin active level.
127 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
128 | * This parameter can be one of the following values:
129 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
130 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
131 | * @retval None
132 | */
133 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
134 | {
135 | /* Check the parameters */
136 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
137 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
138 | }
139 |
140 | /**
141 | * @brief Enables or disables the Tamper Pin activation.
142 | * @param NewState: new state of the Tamper Pin activation.
143 | * This parameter can be: ENABLE or DISABLE.
144 | * @retval None
145 | */
146 | void BKP_TamperPinCmd(FunctionalState NewState)
147 | {
148 | /* Check the parameters */
149 | assert_param(IS_FUNCTIONAL_STATE(NewState));
150 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
151 | }
152 |
153 | /**
154 | * @brief Enables or disables the Tamper Pin Interrupt.
155 | * @param NewState: new state of the Tamper Pin Interrupt.
156 | * This parameter can be: ENABLE or DISABLE.
157 | * @retval None
158 | */
159 | void BKP_ITConfig(FunctionalState NewState)
160 | {
161 | /* Check the parameters */
162 | assert_param(IS_FUNCTIONAL_STATE(NewState));
163 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
164 | }
165 |
166 | /**
167 | * @brief Select the RTC output source to output on the Tamper pin.
168 | * @param BKP_RTCOutputSource: specifies the RTC output source.
169 | * This parameter can be one of the following values:
170 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
171 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
172 | * divided by 64 on the Tamper pin.
173 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
174 | * the Tamper pin.
175 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
176 | * the Tamper pin.
177 | * @retval None
178 | */
179 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
180 | {
181 | uint16_t tmpreg = 0;
182 | /* Check the parameters */
183 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
184 | tmpreg = BKP->RTCCR;
185 | /* Clear CCO, ASOE and ASOS bits */
186 | tmpreg &= RTCCR_MASK;
187 |
188 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
189 | tmpreg |= BKP_RTCOutputSource;
190 | /* Store the new value */
191 | BKP->RTCCR = tmpreg;
192 | }
193 |
194 | /**
195 | * @brief Sets RTC Clock Calibration value.
196 | * @param CalibrationValue: specifies the RTC Clock Calibration value.
197 | * This parameter must be a number between 0 and 0x7F.
198 | * @retval None
199 | */
200 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
201 | {
202 | uint16_t tmpreg = 0;
203 | /* Check the parameters */
204 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
205 | tmpreg = BKP->RTCCR;
206 | /* Clear CAL[6:0] bits */
207 | tmpreg &= RTCCR_CAL_MASK;
208 | /* Set CAL[6:0] bits according to CalibrationValue value */
209 | tmpreg |= CalibrationValue;
210 | /* Store the new value */
211 | BKP->RTCCR = tmpreg;
212 | }
213 |
214 | /**
215 | * @brief Writes user data to the specified Data Backup Register.
216 | * @param BKP_DR: specifies the Data Backup Register.
217 | * This parameter can be BKP_DRx where x:[1, 42]
218 | * @param Data: data to write
219 | * @retval None
220 | */
221 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
222 | {
223 | __IO uint32_t tmp = 0;
224 |
225 | /* Check the parameters */
226 | assert_param(IS_BKP_DR(BKP_DR));
227 |
228 | tmp = (uint32_t)BKP_BASE;
229 | tmp += BKP_DR;
230 |
231 | *(__IO uint32_t *) tmp = Data;
232 | }
233 |
234 | /**
235 | * @brief Reads data from the specified Data Backup Register.
236 | * @param BKP_DR: specifies the Data Backup Register.
237 | * This parameter can be BKP_DRx where x:[1, 42]
238 | * @retval The content of the specified Data Backup Register
239 | */
240 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
241 | {
242 | __IO uint32_t tmp = 0;
243 |
244 | /* Check the parameters */
245 | assert_param(IS_BKP_DR(BKP_DR));
246 |
247 | tmp = (uint32_t)BKP_BASE;
248 | tmp += BKP_DR;
249 |
250 | return (*(__IO uint16_t *) tmp);
251 | }
252 |
253 | /**
254 | * @brief Checks whether the Tamper Pin Event flag is set or not.
255 | * @param None
256 | * @retval The new state of the Tamper Pin Event flag (SET or RESET).
257 | */
258 | FlagStatus BKP_GetFlagStatus(void)
259 | {
260 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
261 | }
262 |
263 | /**
264 | * @brief Clears Tamper Pin Event pending flag.
265 | * @param None
266 | * @retval None
267 | */
268 | void BKP_ClearFlag(void)
269 | {
270 | /* Set CTE bit to clear Tamper Pin Event flag */
271 | BKP->CSR |= BKP_CSR_CTE;
272 | }
273 |
274 | /**
275 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
276 | * @param None
277 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
278 | */
279 | ITStatus BKP_GetITStatus(void)
280 | {
281 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
282 | }
283 |
284 | /**
285 | * @brief Clears Tamper Pin Interrupt pending bit.
286 | * @param None
287 | * @retval None
288 | */
289 | void BKP_ClearITPendingBit(void)
290 | {
291 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
292 | BKP->CSR |= BKP_CSR_CTI;
293 | }
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | /**
304 | * @}
305 | */
306 |
307 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
308 |
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/STM32F10x_FWLib/src/stm32f10x_can.c:
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/STM32F10x_FWLib/src/stm32f10x_cec.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_cec.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the CEC firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_cec.h"
23 | #include "stm32f10x_rcc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup CEC
30 | * @brief CEC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup CEC_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 |
43 | /** @defgroup CEC_Private_Defines
44 | * @{
45 | */
46 |
47 | /* ------------ CEC registers bit address in the alias region ----------- */
48 | #define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
49 |
50 | /* --- CFGR Register ---*/
51 |
52 | /* Alias word address of PE bit */
53 | #define CFGR_OFFSET (CEC_OFFSET + 0x00)
54 | #define PE_BitNumber 0x00
55 | #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
56 |
57 | /* Alias word address of IE bit */
58 | #define IE_BitNumber 0x01
59 | #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
60 |
61 | /* --- CSR Register ---*/
62 |
63 | /* Alias word address of TSOM bit */
64 | #define CSR_OFFSET (CEC_OFFSET + 0x10)
65 | #define TSOM_BitNumber 0x00
66 | #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
67 |
68 | /* Alias word address of TEOM bit */
69 | #define TEOM_BitNumber 0x01
70 | #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
71 |
72 | #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
73 | #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 |
80 | /** @defgroup CEC_Private_Macros
81 | * @{
82 | */
83 |
84 | /**
85 | * @}
86 | */
87 |
88 |
89 | /** @defgroup CEC_Private_Variables
90 | * @{
91 | */
92 |
93 | /**
94 | * @}
95 | */
96 |
97 |
98 | /** @defgroup CEC_Private_FunctionPrototypes
99 | * @{
100 | */
101 |
102 | /**
103 | * @}
104 | */
105 |
106 |
107 | /** @defgroup CEC_Private_Functions
108 | * @{
109 | */
110 |
111 | /**
112 | * @brief Deinitializes the CEC peripheral registers to their default reset
113 | * values.
114 | * @param None
115 | * @retval None
116 | */
117 | void CEC_DeInit(void)
118 | {
119 | /* Enable CEC reset state */
120 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
121 | /* Release CEC from reset state */
122 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
123 | }
124 |
125 |
126 | /**
127 | * @brief Initializes the CEC peripheral according to the specified
128 | * parameters in the CEC_InitStruct.
129 | * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
130 | * contains the configuration information for the specified
131 | * CEC peripheral.
132 | * @retval None
133 | */
134 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
135 | {
136 | uint16_t tmpreg = 0;
137 |
138 | /* Check the parameters */
139 | assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
140 | assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
141 |
142 | /*---------------------------- CEC CFGR Configuration -----------------*/
143 | /* Get the CEC CFGR value */
144 | tmpreg = CEC->CFGR;
145 |
146 | /* Clear BTEM and BPEM bits */
147 | tmpreg &= CFGR_CLEAR_Mask;
148 |
149 | /* Configure CEC: Bit Timing Error and Bit Period Error */
150 | tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
151 |
152 | /* Write to CEC CFGR register*/
153 | CEC->CFGR = tmpreg;
154 |
155 | }
156 |
157 | /**
158 | * @brief Enables or disables the specified CEC peripheral.
159 | * @param NewState: new state of the CEC peripheral.
160 | * This parameter can be: ENABLE or DISABLE.
161 | * @retval None
162 | */
163 | void CEC_Cmd(FunctionalState NewState)
164 | {
165 | /* Check the parameters */
166 | assert_param(IS_FUNCTIONAL_STATE(NewState));
167 |
168 | *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
169 |
170 | if(NewState == DISABLE)
171 | {
172 | /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
173 | while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
174 | {
175 | }
176 | }
177 | }
178 |
179 | /**
180 | * @brief Enables or disables the CEC interrupt.
181 | * @param NewState: new state of the CEC interrupt.
182 | * This parameter can be: ENABLE or DISABLE.
183 | * @retval None
184 | */
185 | void CEC_ITConfig(FunctionalState NewState)
186 | {
187 | /* Check the parameters */
188 | assert_param(IS_FUNCTIONAL_STATE(NewState));
189 |
190 | *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
191 | }
192 |
193 | /**
194 | * @brief Defines the Own Address of the CEC device.
195 | * @param CEC_OwnAddress: The CEC own address
196 | * @retval None
197 | */
198 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
199 | {
200 | /* Check the parameters */
201 | assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
202 |
203 | /* Set the CEC own address */
204 | CEC->OAR = CEC_OwnAddress;
205 | }
206 |
207 | /**
208 | * @brief Sets the CEC prescaler value.
209 | * @param CEC_Prescaler: CEC prescaler new value
210 | * @retval None
211 | */
212 | void CEC_SetPrescaler(uint16_t CEC_Prescaler)
213 | {
214 | /* Check the parameters */
215 | assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
216 |
217 | /* Set the Prescaler value*/
218 | CEC->PRES = CEC_Prescaler;
219 | }
220 |
221 | /**
222 | * @brief Transmits single data through the CEC peripheral.
223 | * @param Data: the data to transmit.
224 | * @retval None
225 | */
226 | void CEC_SendDataByte(uint8_t Data)
227 | {
228 | /* Transmit Data */
229 | CEC->TXD = Data ;
230 | }
231 |
232 |
233 | /**
234 | * @brief Returns the most recent received data by the CEC peripheral.
235 | * @param None
236 | * @retval The received data.
237 | */
238 | uint8_t CEC_ReceiveDataByte(void)
239 | {
240 | /* Receive Data */
241 | return (uint8_t)(CEC->RXD);
242 | }
243 |
244 | /**
245 | * @brief Starts a new message.
246 | * @param None
247 | * @retval None
248 | */
249 | void CEC_StartOfMessage(void)
250 | {
251 | /* Starts of new message */
252 | *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
253 | }
254 |
255 | /**
256 | * @brief Transmits message with or without an EOM bit.
257 | * @param NewState: new state of the CEC Tx End Of Message.
258 | * This parameter can be: ENABLE or DISABLE.
259 | * @retval None
260 | */
261 | void CEC_EndOfMessageCmd(FunctionalState NewState)
262 | {
263 | /* Check the parameters */
264 | assert_param(IS_FUNCTIONAL_STATE(NewState));
265 |
266 | /* The data byte will be transmitted with or without an EOM bit*/
267 | *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
268 | }
269 |
270 | /**
271 | * @brief Gets the CEC flag status
272 | * @param CEC_FLAG: specifies the CEC flag to check.
273 | * This parameter can be one of the following values:
274 | * @arg CEC_FLAG_BTE: Bit Timing Error
275 | * @arg CEC_FLAG_BPE: Bit Period Error
276 | * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
277 | * @arg CEC_FLAG_SBE: Start Bit Error
278 | * @arg CEC_FLAG_ACKE: Block Acknowledge Error
279 | * @arg CEC_FLAG_LINE: Line Error
280 | * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error
281 | * @arg CEC_FLAG_TEOM: Tx End Of Message
282 | * @arg CEC_FLAG_TERR: Tx Error
283 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
284 | * @arg CEC_FLAG_RSOM: Rx Start Of Message
285 | * @arg CEC_FLAG_REOM: Rx End Of Message
286 | * @arg CEC_FLAG_RERR: Rx Error
287 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
288 | * @retval The new state of CEC_FLAG (SET or RESET)
289 | */
290 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
291 | {
292 | FlagStatus bitstatus = RESET;
293 | uint32_t cecreg = 0, cecbase = 0;
294 |
295 | /* Check the parameters */
296 | assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
297 |
298 | /* Get the CEC peripheral base address */
299 | cecbase = (uint32_t)(CEC_BASE);
300 |
301 | /* Read flag register index */
302 | cecreg = CEC_FLAG >> 28;
303 |
304 | /* Get bit[23:0] of the flag */
305 | CEC_FLAG &= FLAG_Mask;
306 |
307 | if(cecreg != 0)
308 | {
309 | /* Flag in CEC ESR Register */
310 | CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
311 |
312 | /* Get the CEC ESR register address */
313 | cecbase += 0xC;
314 | }
315 | else
316 | {
317 | /* Get the CEC CSR register address */
318 | cecbase += 0x10;
319 | }
320 |
321 | if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
322 | {
323 | /* CEC_FLAG is set */
324 | bitstatus = SET;
325 | }
326 | else
327 | {
328 | /* CEC_FLAG is reset */
329 | bitstatus = RESET;
330 | }
331 |
332 | /* Return the CEC_FLAG status */
333 | return bitstatus;
334 | }
335 |
336 | /**
337 | * @brief Clears the CEC's pending flags.
338 | * @param CEC_FLAG: specifies the flag to clear.
339 | * This parameter can be any combination of the following values:
340 | * @arg CEC_FLAG_TERR: Tx Error
341 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
342 | * @arg CEC_FLAG_RSOM: Rx Start Of Message
343 | * @arg CEC_FLAG_REOM: Rx End Of Message
344 | * @arg CEC_FLAG_RERR: Rx Error
345 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
346 | * @retval None
347 | */
348 | void CEC_ClearFlag(uint32_t CEC_FLAG)
349 | {
350 | uint32_t tmp = 0x0;
351 |
352 | /* Check the parameters */
353 | assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
354 |
355 | tmp = CEC->CSR & 0x2;
356 |
357 | /* Clear the selected CEC flags */
358 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
359 | }
360 |
361 | /**
362 | * @brief Checks whether the specified CEC interrupt has occurred or not.
363 | * @param CEC_IT: specifies the CEC interrupt source to check.
364 | * This parameter can be one of the following values:
365 | * @arg CEC_IT_TERR: Tx Error
366 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished
367 | * @arg CEC_IT_RERR: Rx Error
368 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished
369 | * @retval The new state of CEC_IT (SET or RESET).
370 | */
371 | ITStatus CEC_GetITStatus(uint8_t CEC_IT)
372 | {
373 | ITStatus bitstatus = RESET;
374 | uint32_t enablestatus = 0;
375 |
376 | /* Check the parameters */
377 | assert_param(IS_CEC_GET_IT(CEC_IT));
378 |
379 | /* Get the CEC IT enable bit status */
380 | enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
381 |
382 | /* Check the status of the specified CEC interrupt */
383 | if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
384 | {
385 | /* CEC_IT is set */
386 | bitstatus = SET;
387 | }
388 | else
389 | {
390 | /* CEC_IT is reset */
391 | bitstatus = RESET;
392 | }
393 | /* Return the CEC_IT status */
394 | return bitstatus;
395 | }
396 |
397 | /**
398 | * @brief Clears the CEC's interrupt pending bits.
399 | * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
400 | * This parameter can be any combination of the following values:
401 | * @arg CEC_IT_TERR: Tx Error
402 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished
403 | * @arg CEC_IT_RERR: Rx Error
404 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished
405 | * @retval None
406 | */
407 | void CEC_ClearITPendingBit(uint16_t CEC_IT)
408 | {
409 | uint32_t tmp = 0x0;
410 |
411 | /* Check the parameters */
412 | assert_param(IS_CEC_GET_IT(CEC_IT));
413 |
414 | tmp = CEC->CSR & 0x2;
415 |
416 | /* Clear the selected CEC interrupt pending bits */
417 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
418 | }
419 |
420 | /**
421 | * @}
422 | */
423 |
424 | /**
425 | * @}
426 | */
427 |
428 | /**
429 | * @}
430 | */
431 |
432 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
433 |
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/STM32F10x_FWLib/src/stm32f10x_crc.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the CRC firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_crc.h"
23 |
24 | /** @addtogroup STM32F10x_StdPeriph_Driver
25 | * @{
26 | */
27 |
28 | /** @defgroup CRC
29 | * @brief CRC driver modules
30 | * @{
31 | */
32 |
33 | /** @defgroup CRC_Private_TypesDefinitions
34 | * @{
35 | */
36 |
37 | /**
38 | * @}
39 | */
40 |
41 | /** @defgroup CRC_Private_Defines
42 | * @{
43 | */
44 |
45 | /**
46 | * @}
47 | */
48 |
49 | /** @defgroup CRC_Private_Macros
50 | * @{
51 | */
52 |
53 | /**
54 | * @}
55 | */
56 |
57 | /** @defgroup CRC_Private_Variables
58 | * @{
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /** @defgroup CRC_Private_FunctionPrototypes
66 | * @{
67 | */
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /** @defgroup CRC_Private_Functions
74 | * @{
75 | */
76 |
77 | /**
78 | * @brief Resets the CRC Data register (DR).
79 | * @param None
80 | * @retval None
81 | */
82 | void CRC_ResetDR(void)
83 | {
84 | /* Reset CRC generator */
85 | CRC->CR = CRC_CR_RESET;
86 | }
87 |
88 | /**
89 | * @brief Computes the 32-bit CRC of a given data word(32-bit).
90 | * @param Data: data word(32-bit) to compute its CRC
91 | * @retval 32-bit CRC
92 | */
93 | uint32_t CRC_CalcCRC(uint32_t Data)
94 | {
95 | CRC->DR = Data;
96 |
97 | return (CRC->DR);
98 | }
99 |
100 | /**
101 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
102 | * @param pBuffer: pointer to the buffer containing the data to be computed
103 | * @param BufferLength: length of the buffer to be computed
104 | * @retval 32-bit CRC
105 | */
106 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
107 | {
108 | uint32_t index = 0;
109 |
110 | for(index = 0; index < BufferLength; index++)
111 | {
112 | CRC->DR = pBuffer[index];
113 | }
114 | return (CRC->DR);
115 | }
116 |
117 | /**
118 | * @brief Returns the current CRC value.
119 | * @param None
120 | * @retval 32-bit CRC
121 | */
122 | uint32_t CRC_GetCRC(void)
123 | {
124 | return (CRC->DR);
125 | }
126 |
127 | /**
128 | * @brief Stores a 8-bit data in the Independent Data(ID) register.
129 | * @param IDValue: 8-bit value to be stored in the ID register
130 | * @retval None
131 | */
132 | void CRC_SetIDRegister(uint8_t IDValue)
133 | {
134 | CRC->IDR = IDValue;
135 | }
136 |
137 | /**
138 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register
139 | * @param None
140 | * @retval 8-bit value of the ID register
141 | */
142 | uint8_t CRC_GetIDRegister(void)
143 | {
144 | return (CRC->IDR);
145 | }
146 |
147 | /**
148 | * @}
149 | */
150 |
151 | /**
152 | * @}
153 | */
154 |
155 | /**
156 | * @}
157 | */
158 |
159 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
160 |
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/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the DBGMCU firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_dbgmcu.h"
23 |
24 | /** @addtogroup STM32F10x_StdPeriph_Driver
25 | * @{
26 | */
27 |
28 | /** @defgroup DBGMCU
29 | * @brief DBGMCU driver modules
30 | * @{
31 | */
32 |
33 | /** @defgroup DBGMCU_Private_TypesDefinitions
34 | * @{
35 | */
36 |
37 | /**
38 | * @}
39 | */
40 |
41 | /** @defgroup DBGMCU_Private_Defines
42 | * @{
43 | */
44 |
45 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup DBGMCU_Private_Macros
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup DBGMCU_Private_Variables
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup DBGMCU_Private_FunctionPrototypes
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup DBGMCU_Private_Functions
75 | * @{
76 | */
77 |
78 | /**
79 | * @brief Returns the device revision identifier.
80 | * @param None
81 | * @retval Device revision identifier
82 | */
83 | uint32_t DBGMCU_GetREVID(void)
84 | {
85 | return(DBGMCU->IDCODE >> 16);
86 | }
87 |
88 | /**
89 | * @brief Returns the device identifier.
90 | * @param None
91 | * @retval Device identifier
92 | */
93 | uint32_t DBGMCU_GetDEVID(void)
94 | {
95 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
96 | }
97 |
98 | /**
99 | * @brief Configures the specified peripheral and low power mode behavior
100 | * when the MCU under Debug mode.
101 | * @param DBGMCU_Periph: specifies the peripheral and low power mode.
102 | * This parameter can be any combination of the following values:
103 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
104 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
105 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
106 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
107 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
108 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
109 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
110 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
111 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
112 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
113 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
114 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
115 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
116 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
117 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
118 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
119 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
120 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
121 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
122 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
123 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
124 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
125 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
126 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
127 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
128 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
129 | * @param NewState: new state of the specified peripheral in Debug mode.
130 | * This parameter can be: ENABLE or DISABLE.
131 | * @retval None
132 | */
133 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
134 | {
135 | /* Check the parameters */
136 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
137 | assert_param(IS_FUNCTIONAL_STATE(NewState));
138 |
139 | if (NewState != DISABLE)
140 | {
141 | DBGMCU->CR |= DBGMCU_Periph;
142 | }
143 | else
144 | {
145 | DBGMCU->CR &= ~DBGMCU_Periph;
146 | }
147 | }
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /**
154 | * @}
155 | */
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
162 |
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/STM32F10x_FWLib/src/stm32f10x_exti.c:
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/STM32F10x_FWLib/src/stm32f10x_iwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the IWDG firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_iwdg.h"
23 |
24 | /** @addtogroup STM32F10x_StdPeriph_Driver
25 | * @{
26 | */
27 |
28 | /** @defgroup IWDG
29 | * @brief IWDG driver modules
30 | * @{
31 | */
32 |
33 | /** @defgroup IWDG_Private_TypesDefinitions
34 | * @{
35 | */
36 |
37 | /**
38 | * @}
39 | */
40 |
41 | /** @defgroup IWDG_Private_Defines
42 | * @{
43 | */
44 |
45 | /* ---------------------- IWDG registers bit mask ----------------------------*/
46 |
47 | /* KR register bit mask */
48 | #define KR_KEY_Reload ((uint16_t)0xAAAA)
49 | #define KR_KEY_Enable ((uint16_t)0xCCCC)
50 |
51 | /**
52 | * @}
53 | */
54 |
55 | /** @defgroup IWDG_Private_Macros
56 | * @{
57 | */
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /** @defgroup IWDG_Private_Variables
64 | * @{
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /** @defgroup IWDG_Private_FunctionPrototypes
72 | * @{
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /** @defgroup IWDG_Private_Functions
80 | * @{
81 | */
82 |
83 | /**
84 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
85 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
86 | * This parameter can be one of the following values:
87 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
88 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
89 | * @retval None
90 | */
91 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
92 | {
93 | /* Check the parameters */
94 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
95 | IWDG->KR = IWDG_WriteAccess;
96 | }
97 |
98 | /**
99 | * @brief Sets IWDG Prescaler value.
100 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
101 | * This parameter can be one of the following values:
102 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
103 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
104 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
105 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
106 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
107 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
108 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
109 | * @retval None
110 | */
111 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
112 | {
113 | /* Check the parameters */
114 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
115 | IWDG->PR = IWDG_Prescaler;
116 | }
117 |
118 | /**
119 | * @brief Sets IWDG Reload value.
120 | * @param Reload: specifies the IWDG Reload value.
121 | * This parameter must be a number between 0 and 0x0FFF.
122 | * @retval None
123 | */
124 | void IWDG_SetReload(uint16_t Reload)
125 | {
126 | /* Check the parameters */
127 | assert_param(IS_IWDG_RELOAD(Reload));
128 | IWDG->RLR = Reload;
129 | }
130 |
131 | /**
132 | * @brief Reloads IWDG counter with value defined in the reload register
133 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
134 | * @param None
135 | * @retval None
136 | */
137 | void IWDG_ReloadCounter(void)
138 | {
139 | IWDG->KR = KR_KEY_Reload;
140 | }
141 |
142 | /**
143 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
144 | * @param None
145 | * @retval None
146 | */
147 | void IWDG_Enable(void)
148 | {
149 | IWDG->KR = KR_KEY_Enable;
150 | }
151 |
152 | /**
153 | * @brief Checks whether the specified IWDG flag is set or not.
154 | * @param IWDG_FLAG: specifies the flag to check.
155 | * This parameter can be one of the following values:
156 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
157 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
158 | * @retval The new state of IWDG_FLAG (SET or RESET).
159 | */
160 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
161 | {
162 | FlagStatus bitstatus = RESET;
163 | /* Check the parameters */
164 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
165 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
166 | {
167 | bitstatus = SET;
168 | }
169 | else
170 | {
171 | bitstatus = RESET;
172 | }
173 | /* Return the flag status */
174 | return bitstatus;
175 | }
176 |
177 | /**
178 | * @}
179 | */
180 |
181 | /**
182 | * @}
183 | */
184 |
185 | /**
186 | * @}
187 | */
188 |
189 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
190 |
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/STM32F10x_FWLib/src/stm32f10x_pwr.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the PWR firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_pwr.h"
23 | #include "stm32f10x_rcc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup PWR
30 | * @brief PWR driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup PWR_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup PWR_Private_Defines
43 | * @{
44 | */
45 |
46 | /* --------- PWR registers bit address in the alias region ---------- */
47 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
48 |
49 | /* --- CR Register ---*/
50 |
51 | /* Alias word address of DBP bit */
52 | #define CR_OFFSET (PWR_OFFSET + 0x00)
53 | #define DBP_BitNumber 0x08
54 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
55 |
56 | /* Alias word address of PVDE bit */
57 | #define PVDE_BitNumber 0x04
58 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
59 |
60 | /* --- CSR Register ---*/
61 |
62 | /* Alias word address of EWUP bit */
63 | #define CSR_OFFSET (PWR_OFFSET + 0x04)
64 | #define EWUP_BitNumber 0x08
65 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
66 |
67 | /* ------------------ PWR registers bit mask ------------------------ */
68 |
69 | /* CR register bit mask */
70 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
71 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
72 |
73 |
74 | /**
75 | * @}
76 | */
77 |
78 | /** @defgroup PWR_Private_Macros
79 | * @{
80 | */
81 |
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup PWR_Private_Variables
87 | * @{
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup PWR_Private_FunctionPrototypes
95 | * @{
96 | */
97 |
98 | /**
99 | * @}
100 | */
101 |
102 | /** @defgroup PWR_Private_Functions
103 | * @{
104 | */
105 |
106 | /**
107 | * @brief Deinitializes the PWR peripheral registers to their default reset values.
108 | * @param None
109 | * @retval None
110 | */
111 | void PWR_DeInit(void)
112 | {
113 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
115 | }
116 |
117 | /**
118 | * @brief Enables or disables access to the RTC and backup registers.
119 | * @param NewState: new state of the access to the RTC and backup registers.
120 | * This parameter can be: ENABLE or DISABLE.
121 | * @retval None
122 | */
123 | void PWR_BackupAccessCmd(FunctionalState NewState)
124 | {
125 | /* Check the parameters */
126 | assert_param(IS_FUNCTIONAL_STATE(NewState));
127 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
128 | }
129 |
130 | /**
131 | * @brief Enables or disables the Power Voltage Detector(PVD).
132 | * @param NewState: new state of the PVD.
133 | * This parameter can be: ENABLE or DISABLE.
134 | * @retval None
135 | */
136 | void PWR_PVDCmd(FunctionalState NewState)
137 | {
138 | /* Check the parameters */
139 | assert_param(IS_FUNCTIONAL_STATE(NewState));
140 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
141 | }
142 |
143 | /**
144 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
145 | * @param PWR_PVDLevel: specifies the PVD detection level
146 | * This parameter can be one of the following values:
147 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
148 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
149 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
150 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
151 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
152 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
153 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
154 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
155 | * @retval None
156 | */
157 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
158 | {
159 | uint32_t tmpreg = 0;
160 | /* Check the parameters */
161 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
162 | tmpreg = PWR->CR;
163 | /* Clear PLS[7:5] bits */
164 | tmpreg &= CR_PLS_MASK;
165 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */
166 | tmpreg |= PWR_PVDLevel;
167 | /* Store the new value */
168 | PWR->CR = tmpreg;
169 | }
170 |
171 | /**
172 | * @brief Enables or disables the WakeUp Pin functionality.
173 | * @param NewState: new state of the WakeUp Pin functionality.
174 | * This parameter can be: ENABLE or DISABLE.
175 | * @retval None
176 | */
177 | void PWR_WakeUpPinCmd(FunctionalState NewState)
178 | {
179 | /* Check the parameters */
180 | assert_param(IS_FUNCTIONAL_STATE(NewState));
181 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
182 | }
183 |
184 | /**
185 | * @brief Enters STOP mode.
186 | * @param PWR_Regulator: specifies the regulator state in STOP mode.
187 | * This parameter can be one of the following values:
188 | * @arg PWR_Regulator_ON: STOP mode with regulator ON
189 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
190 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
191 | * This parameter can be one of the following values:
192 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
193 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
194 | * @retval None
195 | */
196 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
197 | {
198 | uint32_t tmpreg = 0;
199 | /* Check the parameters */
200 | assert_param(IS_PWR_REGULATOR(PWR_Regulator));
201 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
202 |
203 | /* Select the regulator state in STOP mode ---------------------------------*/
204 | tmpreg = PWR->CR;
205 | /* Clear PDDS and LPDS bits */
206 | tmpreg &= CR_DS_MASK;
207 | /* Set LPDS bit according to PWR_Regulator value */
208 | tmpreg |= PWR_Regulator;
209 | /* Store the new value */
210 | PWR->CR = tmpreg;
211 | /* Set SLEEPDEEP bit of Cortex System Control Register */
212 | SCB->SCR |= SCB_SCR_SLEEPDEEP;
213 |
214 | /* Select STOP mode entry --------------------------------------------------*/
215 | if(PWR_STOPEntry == PWR_STOPEntry_WFI)
216 | {
217 | /* Request Wait For Interrupt */
218 | __WFI();
219 | }
220 | else
221 | {
222 | /* Request Wait For Event */
223 | __WFE();
224 | }
225 |
226 | /* Reset SLEEPDEEP bit of Cortex System Control Register */
227 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
228 | }
229 |
230 | /**
231 | * @brief Enters STANDBY mode.
232 | * @param None
233 | * @retval None
234 | */
235 | void PWR_EnterSTANDBYMode(void)
236 | {
237 | /* Clear Wake-up flag */
238 | PWR->CR |= PWR_CR_CWUF;
239 | /* Select STANDBY mode */
240 | PWR->CR |= PWR_CR_PDDS;
241 | /* Set SLEEPDEEP bit of Cortex System Control Register */
242 | SCB->SCR |= SCB_SCR_SLEEPDEEP;
243 | /* This option is used to ensure that store operations are completed */
244 | #if defined ( __CC_ARM )
245 | __force_stores();
246 | #endif
247 | /* Request Wait For Interrupt */
248 | __WFI();
249 | }
250 |
251 | /**
252 | * @brief Checks whether the specified PWR flag is set or not.
253 | * @param PWR_FLAG: specifies the flag to check.
254 | * This parameter can be one of the following values:
255 | * @arg PWR_FLAG_WU: Wake Up flag
256 | * @arg PWR_FLAG_SB: StandBy flag
257 | * @arg PWR_FLAG_PVDO: PVD Output
258 | * @retval The new state of PWR_FLAG (SET or RESET).
259 | */
260 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
261 | {
262 | FlagStatus bitstatus = RESET;
263 | /* Check the parameters */
264 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
265 |
266 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
267 | {
268 | bitstatus = SET;
269 | }
270 | else
271 | {
272 | bitstatus = RESET;
273 | }
274 | /* Return the flag status */
275 | return bitstatus;
276 | }
277 |
278 | /**
279 | * @brief Clears the PWR's pending flags.
280 | * @param PWR_FLAG: specifies the flag to clear.
281 | * This parameter can be one of the following values:
282 | * @arg PWR_FLAG_WU: Wake Up flag
283 | * @arg PWR_FLAG_SB: StandBy flag
284 | * @retval None
285 | */
286 | void PWR_ClearFlag(uint32_t PWR_FLAG)
287 | {
288 | /* Check the parameters */
289 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
290 |
291 | PWR->CR |= PWR_FLAG << 2;
292 | }
293 |
294 | /**
295 | * @}
296 | */
297 |
298 | /**
299 | * @}
300 | */
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
307 |
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/STM32F10x_FWLib/src/stm32f10x_rcc.c:
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/STM32F10x_FWLib/src/stm32f10x_rtc.c:
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/STM32F10x_FWLib/src/stm32f10x_sdio.c:
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/STM32F10x_FWLib/src/stm32f10x_tim.c:
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/STM32F10x_FWLib/src/stm32f10x_usart.c:
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/STM32F10x_FWLib/src/stm32f10x_wwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.c
4 | * @author MCD Application Team
5 | * @version V3.4.0
6 | * @date 10/15/2010
7 | * @brief This file provides all the WWDG firmware functions.
8 | ******************************************************************************
9 | * @copy
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2010 STMicroelectronics
19 | */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32f10x_wwdg.h"
23 | #include "stm32f10x_rcc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup WWDG
30 | * @brief WWDG driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup WWDG_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup WWDG_Private_Defines
43 | * @{
44 | */
45 |
46 | /* ----------- WWDG registers bit address in the alias region ----------- */
47 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
48 |
49 | /* Alias word address of EWI bit */
50 | #define CFR_OFFSET (WWDG_OFFSET + 0x04)
51 | #define EWI_BitNumber 0x09
52 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
53 |
54 | /* --------------------- WWDG registers bit mask ------------------------ */
55 |
56 | /* CR register bit mask */
57 | #define CR_WDGA_Set ((uint32_t)0x00000080)
58 |
59 | /* CFR register bit mask */
60 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
61 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80)
62 | #define BIT_Mask ((uint8_t)0x7F)
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup WWDG_Private_Macros
69 | * @{
70 | */
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup WWDG_Private_Variables
77 | * @{
78 | */
79 |
80 | /**
81 | * @}
82 | */
83 |
84 | /** @defgroup WWDG_Private_FunctionPrototypes
85 | * @{
86 | */
87 |
88 | /**
89 | * @}
90 | */
91 |
92 | /** @defgroup WWDG_Private_Functions
93 | * @{
94 | */
95 |
96 | /**
97 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
98 | * @param None
99 | * @retval None
100 | */
101 | void WWDG_DeInit(void)
102 | {
103 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
105 | }
106 |
107 | /**
108 | * @brief Sets the WWDG Prescaler.
109 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
110 | * This parameter can be one of the following values:
111 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
112 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
113 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
114 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
115 | * @retval None
116 | */
117 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
118 | {
119 | uint32_t tmpreg = 0;
120 | /* Check the parameters */
121 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
122 | /* Clear WDGTB[1:0] bits */
123 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
124 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
125 | tmpreg |= WWDG_Prescaler;
126 | /* Store the new value */
127 | WWDG->CFR = tmpreg;
128 | }
129 |
130 | /**
131 | * @brief Sets the WWDG window value.
132 | * @param WindowValue: specifies the window value to be compared to the downcounter.
133 | * This parameter value must be lower than 0x80.
134 | * @retval None
135 | */
136 | void WWDG_SetWindowValue(uint8_t WindowValue)
137 | {
138 | __IO uint32_t tmpreg = 0;
139 |
140 | /* Check the parameters */
141 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
142 | /* Clear W[6:0] bits */
143 |
144 | tmpreg = WWDG->CFR & CFR_W_Mask;
145 |
146 | /* Set W[6:0] bits according to WindowValue value */
147 | tmpreg |= WindowValue & (uint32_t) BIT_Mask;
148 |
149 | /* Store the new value */
150 | WWDG->CFR = tmpreg;
151 | }
152 |
153 | /**
154 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
155 | * @param None
156 | * @retval None
157 | */
158 | void WWDG_EnableIT(void)
159 | {
160 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
161 | }
162 |
163 | /**
164 | * @brief Sets the WWDG counter value.
165 | * @param Counter: specifies the watchdog counter value.
166 | * This parameter must be a number between 0x40 and 0x7F.
167 | * @retval None
168 | */
169 | void WWDG_SetCounter(uint8_t Counter)
170 | {
171 | /* Check the parameters */
172 | assert_param(IS_WWDG_COUNTER(Counter));
173 | /* Write to T[6:0] bits to configure the counter value, no need to do
174 | a read-modify-write; writing a 0 to WDGA bit does nothing */
175 | WWDG->CR = Counter & BIT_Mask;
176 | }
177 |
178 | /**
179 | * @brief Enables WWDG and load the counter value.
180 | * @param Counter: specifies the watchdog counter value.
181 | * This parameter must be a number between 0x40 and 0x7F.
182 | * @retval None
183 | */
184 | void WWDG_Enable(uint8_t Counter)
185 | {
186 | /* Check the parameters */
187 | assert_param(IS_WWDG_COUNTER(Counter));
188 | WWDG->CR = CR_WDGA_Set | Counter;
189 | }
190 |
191 | /**
192 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
193 | * @param None
194 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
195 | */
196 | FlagStatus WWDG_GetFlagStatus(void)
197 | {
198 | return (FlagStatus)(WWDG->SR);
199 | }
200 |
201 | /**
202 | * @brief Clears Early Wakeup interrupt flag.
203 | * @param None
204 | * @retval None
205 | */
206 | void WWDG_ClearFlag(void)
207 | {
208 | WWDG->SR = (uint32_t)RESET;
209 | }
210 |
211 | /**
212 | * @}
213 | */
214 |
215 | /**
216 | * @}
217 | */
218 |
219 | /**
220 | * @}
221 | */
222 |
223 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
224 |
--------------------------------------------------------------------------------
/clear.bat:
--------------------------------------------------------------------------------
1 | rd /s/q .\Projects\Audio_Speaker\MDK-ARM\STM32L152-EVAL
2 | rd /s/q .\Projects\Audio_Speaker\MDK-ARM\STM32L152D-EVAL
3 | rd /s/q .\Projects\Audio_Speaker\MDK-ARM\STM3210B-EVAL
4 | rd /s/q .\Projects\Audio_Speaker\MDK-ARM\STM3210E-EVAL
5 | rd /s/q .\Projects\Audio_Speaker\MDK-ARM\STM32303C-EVAL
6 | rd /s/q .\Projects\Audio_Speaker\MDK-ARM\STM32373C-EVAL
7 | rd /s/q .\Projects\Audio_Speaker\EWARM\STM32L152-EVAL
8 | rd /s/q .\Projects\Audio_Speaker\EWARM\STM32L152D-EVAL
9 | rd /s/q .\Projects\Audio_Speaker\EWARM\STM3210B-EVAL
10 | rd /s/q .\Projects\Audio_Speaker\EWARM\STM3210E-EVAL
11 | rd /s/q .\Projects\Audio_Speaker\EWARM\STM32303C-EVAL
12 | rd /s/q .\Projects\Audio_Speaker\EWARM\STM32373C-EVAL
13 |
14 | rd /s/q .\Projects\Custom_HID_MSC\MDK-ARM\STM32L152-EVAL
15 | rd /s/q .\Projects\Custom_HID_MSC\MDK-ARM\STM32L152D-EVAL
16 | rd /s/q .\Projects\Custom_HID_MSC\MDK-ARM\STM3210B-EVAL
17 | rd /s/q .\Projects\Custom_HID_MSC\MDK-ARM\STM3210E-EVAL
18 | rd /s/q .\Projects\Custom_HID_MSC\MDK-ARM\STM32303C-EVAL
19 | rd /s/q .\Projects\Custom_HID_MSC\MDK-ARM\STM32373C-EVAL
20 | rd /s/q .\Projects\Custom_HID_MSC\EWARM\STM32L152-EVAL
21 | rd /s/q .\Projects\Custom_HID_MSC\EWARM\STM32L152D-EVAL
22 | rd /s/q .\Projects\Custom_HID_MSC\EWARM\STM3210B-EVAL
23 | rd /s/q .\Projects\Custom_HID_MSC\EWARM\STM3210E-EVAL
24 | rd /s/q .\Projects\Custom_HID_MSC\EWARM\STM32303C-EVAL
25 | rd /s/q .\Projects\Custom_HID_MSC\EWARM\STM32373C-EVAL
26 |
27 | rd /s/q .\Projects\Custom_HID\MDK-ARM\STM32L152-EVAL
28 | rd /s/q .\Projects\Custom_HID\MDK-ARM\STM32L152D-EVAL
29 | rd /s/q .\Projects\Custom_HID\MDK-ARM\STM3210B-EVAL
30 | rd /s/q .\Projects\Custom_HID\MDK-ARM\STM3210E-EVAL
31 | rd /s/q .\Projects\Custom_HID\MDK-ARM\STM32303C-EVAL
32 | rd /s/q .\Projects\Custom_HID\MDK-ARM\STM32373C-EVAL
33 | rd /s/q .\Projects\Custom_HID\EWARM\STM32L152-EVAL
34 | rd /s/q .\Projects\Custom_HID\EWARM\STM32L152D-EVAL
35 | rd /s/q .\Projects\Custom_HID\EWARM\STM3210B-EVAL
36 | rd /s/q .\Projects\Custom_HID\EWARM\STM3210E-EVAL
37 | rd /s/q .\Projects\Custom_HID\EWARM\STM32303C-EVAL
38 | rd /s/q .\Projects\Custom_HID\EWARM\STM32373C-EVAL
39 |
40 | rd /s/q .\Projects\Device_Firmware_Upgrade\MDK-ARM\STM32L152-EVAL
41 | rd /s/q .\Projects\Device_Firmware_Upgrade\MDK-ARM\STM32L152D-EVAL
42 | rd /s/q .\Projects\Device_Firmware_Upgrade\MDK-ARM\STM3210B-EVAL
43 | rd /s/q .\Projects\Device_Firmware_Upgrade\MDK-ARM\STM3210E-EVAL
44 | rd /s/q .\Projects\Device_Firmware_Upgrade\MDK-ARM\STM32303C-EVAL
45 | rd /s/q .\Projects\Device_Firmware_Upgrade\MDK-ARM\STM32373C-EVAL
46 | rd /s/q .\Projects\Device_Firmware_Upgrade\EWARM\STM32L152-EVAL
47 | rd /s/q .\Projects\Device_Firmware_Upgrade\EWARM\STM32L152D-EVAL
48 | rd /s/q .\Projects\Device_Firmware_Upgrade\EWARM\STM3210B-EVAL
49 | rd /s/q .\Projects\Device_Firmware_Upgrade\EWARM\STM3210E-EVAL
50 | rd /s/q .\Projects\Device_Firmware_Upgrade\EWARM\STM32303C-EVAL
51 | rd /s/q .\Projects\Device_Firmware_Upgrade\EWARM\STM32373C-EVAL
52 |
53 | rd /s/q .\Projects\JoyStickMouse\MDK-ARM\STM32L152-EVAL
54 | rd /s/q .\Projects\JoyStickMouse\MDK-ARM\STM32L152D-EVAL
55 | rd /s/q .\Projects\JoyStickMouse\MDK-ARM\STM3210B-EVAL
56 | rd /s/q .\Projects\JoyStickMouse\MDK-ARM\STM3210E-EVAL
57 | rd /s/q .\Projects\JoyStickMouse\MDK-ARM\STM32303C-EVAL
58 | rd /s/q .\Projects\JoyStickMouse\MDK-ARM\STM32373C-EVAL
59 | rd /s/q .\Projects\JoyStickMouse\EWARM\STM32L152-EVAL
60 | rd /s/q .\Projects\JoyStickMouse\EWARM\STM32L152D-EVAL
61 | rd /s/q .\Projects\JoyStickMouse\EWARM\STM3210B-EVAL
62 | rd /s/q .\Projects\JoyStickMouse\EWARM\STM3210E-EVAL
63 | rd /s/q .\Projects\JoyStickMouse\EWARM\STM32303C-EVAL
64 | rd /s/q .\Projects\JoyStickMouse\EWARM\STM32373C-EVAL
65 |
66 | rd /s/q .\Projects\Mass_Storage\MDK-ARM\STM32L152-EVAL
67 | rd /s/q .\Projects\Mass_Storage\MDK-ARM\STM32L152D-EVAL
68 | rd /s/q .\Projects\Mass_Storage\MDK-ARM\STM3210B-EVAL
69 | rd /s/q .\Projects\Mass_Storage\MDK-ARM\STM3210E-EVAL
70 | rd /s/q .\Projects\Mass_Storage\MDK-ARM\STM32303C-EVAL
71 | rd /s/q .\Projects\Mass_Storage\MDK-ARM\STM32373C-EVAL
72 | rd /s/q .\Projects\Mass_Storage\EWARM\STM32L152-EVAL
73 | rd /s/q .\Projects\Mass_Storage\EWARM\STM32L152D-EVAL
74 | rd /s/q .\Projects\Mass_Storage\EWARM\STM3210B-EVAL
75 | rd /s/q .\Projects\Mass_Storage\EWARM\STM3210E-EVAL
76 | rd /s/q .\Projects\Mass_Storage\EWARM\STM32303C-EVAL
77 | rd /s/q .\Projects\Mass_Storage\EWARM\STM32373C-EVAL
78 |
79 | rd /s/q .\Projects\Virtual_COM_Port\MDK-ARM\STM32L152-EVAL
80 | rd /s/q .\Projects\Virtual_COM_Port\MDK-ARM\STM32L152D-EVAL
81 | rd /s/q .\Projects\Virtual_COM_Port\MDK-ARM\STM3210B-EVAL
82 | rd /s/q .\Projects\Virtual_COM_Port\MDK-ARM\STM3210E-EVAL
83 | rd /s/q .\Projects\Virtual_COM_Port\MDK-ARM\STM32303C-EVAL
84 | rd /s/q .\Projects\Virtual_COM_Port\MDK-ARM\STM32373C-EVAL
85 | rd /s/q .\Projects\Virtual_COM_Port\EWARM\STM32L152-EVAL
86 | rd /s/q .\Projects\Virtual_COM_Port\EWARM\STM32L152D-EVAL
87 | rd /s/q .\Projects\Virtual_COM_Port\EWARM\STM3210B-EVAL
88 | rd /s/q .\Projects\Virtual_COM_Port\EWARM\STM3210E-EVAL
89 | rd /s/q .\Projects\Virtual_COM_Port\EWARM\STM32303C-EVAL
90 | rd /s/q .\Projects\Virtual_COM_Port\EWARM\STM32373C-EVAL
91 |
92 | rd /s/q .\Projects\VirtualComport_Loopback\MDK-ARM\STM32L152-EVAL
93 | rd /s/q .\Projects\VirtualComport_Loopback\MDK-ARM\STM32L152D-EVAL
94 | rd /s/q .\Projects\VirtualComport_Loopback\MDK-ARM\STM3210B-EVAL
95 | rd /s/q .\Projects\VirtualComport_Loopback\MDK-ARM\STM3210E-EVAL
96 | rd /s/q .\Projects\VirtualComport_Loopback\MDK-ARM\STM32303C-EVAL
97 | rd /s/q .\Projects\VirtualComport_Loopback\MDK-ARM\STM32373C-EVAL
98 | rd /s/q .\Projects\VirtualComport_Loopback\EWARM\STM32L152-EVAL
99 | rd /s/q .\Projects\VirtualComport_Loopback\EWARM\STM32L152D-EVAL
100 | rd /s/q .\Projects\VirtualComport_Loopback\EWARM\STM3210B-EVAL
101 | rd /s/q .\Projects\VirtualComport_Loopback\EWARM\STM3210E-EVAL
102 | rd /s/q .\Projects\VirtualComport_Loopback\EWARM\STM32303C-EVAL
103 | rd /s/q .\Projects\VirtualComport_Loopback\EWARM\STM32373C-EVAL
104 |
105 | rd /s/q .\Projects\Custom_HID_VCP\MDK-ARM\STM32L152-EVAL
106 | rd /s/q .\Projects\Custom_HID_VCP\MDK-ARM\STM32L152D-EVAL
107 | rd /s/q .\Projects\Custom_HID_VCP\MDK-ARM\STM3210B-EVAL
108 | rd /s/q .\Projects\Custom_HID_VCP\MDK-ARM\STM3210E-EVAL
109 | rd /s/q .\Projects\Custom_HID_VCP\MDK-ARM\STM32303C-EVAL
110 | rd /s/q .\Projects\Custom_HID_VCP\MDK-ARM\STM32373C-EVAL
111 | rd /s/q .\Projects\Custom_HID_VCP\EWARM\STM32L152-EVAL
112 | rd /s/q .\Projects\Custom_HID_VCP\EWARM\STM32L152D-EVAL
113 | rd /s/q .\Projects\Custom_HID_VCP\EWARM\STM3210B-EVAL
114 | rd /s/q .\Projects\Custom_HID_VCP\EWARM\STM3210E-EVAL
115 | rd /s/q .\Projects\Custom_HID_VCP\EWARM\STM32303C-EVAL
116 | rd /s/q .\Projects\Custom_HID_VCP\EWARM\STM32373C-EVAL
117 | del *.bak /s
118 | del *.ddk /s
119 | del *.edk /s
120 | del *.lst /s
121 | del *.lnp /s
122 | del *.mpf /s
123 | del *.mpj /s
124 | del *.obj /s
125 | del *.omf /s
126 | ::del *.opt /s ::������ɾ��JLINK������
127 | del *.plg /s
128 | del *.rpt /s
129 | del *.tmp /s
130 | del *.__i /s
131 | del *._ip /s
132 | del *._ia /s
133 | del *.i /s
134 | del *.crf /s
135 | del *.o /s
136 | del *.d /s
137 | del *.axf /s
138 | del *.tra /s
139 | del *.dep /s
140 | del *.pbi /s
141 | del *.xcl /s
142 | del *.pbd /s
143 | del *.linf /s
144 | del *.browse /s
145 | del *.crun /s
146 | del *.dbgdt /s
147 | del *.dnx /s
148 | del *.ps1 /s
149 | del *.wsdt /s
150 | del JLinkLog.txt /s
151 |
152 | del *.iex /s
153 | del *.htm /s
154 | ::del *.sct /s
155 | del *.map /s
156 | del *.htm /s
157 | del *.txt /s
158 | del Projects/*.bat /s
159 | ::del *.uvgui.* /s
160 | exit
161 |
--------------------------------------------------------------------------------