├── .gitignore
├── .project
├── lifetab_md98486
├── .gitignore
├── datasheets
│ ├── 1908271118_Micron-Tech-MT29F64G08CBABAWP-B_C410865.pdf
│ ├── RK3066-Rockchip.pdf
│ ├── Rockchip RK3308TRM V1.1 Part1-20180810.pdf
│ ├── Rockchip RK3399 TRM V1.4 Part1.pdf
│ ├── Rockchip_RK30xx_TRM_V2.0.pdf
│ ├── schematics
│ │ ├── CM-RK3066_SCH.pdf
│ │ └── TAB 10IS(RK3066+MT5931+MT6622).pdf
│ └── tps65910.pdf
├── dts
│ ├── rk3066a-medion-e10310-u-boot.dtsi
│ └── rk3066a-medion-e10310.dts
└── u-boot
│ └── medion_e10310_defconfig
├── odys-rise10quad
├── .gitignore
├── androoid.txt
├── datasheet
│ ├── A33 user manual release 1.1.pdf
│ ├── A33_Nand_Flash_Controller_Specification.pdf
│ ├── H27UCG8T2BTR-BC.pdf
│ ├── K4B4G1646Q.pdf
│ └── axp223.pdf
├── dts
│ └── sun8i-odys-rise10quad.dts
├── fel-sdboot.sunxi
├── fex
│ ├── dumpfex.sh
│ ├── lcd.rb
│ ├── script.bin
│ ├── script.fex
│ └── u-boot.fex
├── issues
├── lin.txt
├── mountremfs.sh
└── u-boot
│ └── odys_rise10quad_defconfig
├── rock5b
├── archive
│ ├── README.md
│ ├── chromium-ffmpeg
│ │ ├── 0001-widevine-support-for-arm.patch
│ │ ├── 0002-Run-blink-bindings-generation-single-threaded.patch
│ │ ├── 0003-Fix-eu-strip-build-for-newer-GCC.patch
│ │ ├── PKGBUILD
│ │ ├── REVERT-roll-src-third_party-ffmpeg-m102.patch
│ │ ├── REVERT-roll-src-third_party-ffmpeg-m106.patch
│ │ ├── angle-wayland-include-protocol.patch
│ │ ├── chromium-icu72.patch
│ │ ├── disable-GlobalMediaControlsCastStartStop.patch
│ │ ├── use-oauth2-client-switches-as-default.patch
│ │ └── v8-enhance-Date-parser-to-take-Unicode-SPACE.patch
│ ├── librga
│ │ └── PKGBUILD
│ ├── libv4l-rkmpp-git
│ │ └── PKGBUILD
│ ├── opera
│ │ ├── PKGBUILD
│ │ ├── default
│ │ ├── eula.html
│ │ ├── opera
│ │ ├── opera.install
│ │ ├── privacy.html
│ │ ├── privacy.html:Zone.Identifier
│ │ └── terms.html
│ └── v4l-utils-mmap
│ │ ├── 0001-libv4l2-Support-mmap-to-libv4l-plugin.patch
│ │ ├── 0002-Convert-deprecated-libbpf-API.patch
│ │ └── PKGBUILD
├── linux-rk3588-midstream
│ ├── .project
│ ├── PKGBUILD
│ ├── extlinux.arch.template
│ └── linux.preset
├── mesa-pancsf-git
│ ├── LICENSE
│ └── PKGBUILD
└── unified-remote-server
│ ├── PKGBUILD
│ ├── meta.prop
│ ├── remote.lua
│ ├── unified-remote-server.install
│ └── urserver.service
└── swd
└── rk3066.cfg
/.gitignore:
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1 | backup
2 |
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/.project:
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1 |
2 |
3 | hw_necromancer
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
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/lifetab_md98486/.gitignore:
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1 | backup
2 |
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/lifetab_md98486/datasheets/1908271118_Micron-Tech-MT29F64G08CBABAWP-B_C410865.pdf:
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https://raw.githubusercontent.com/hbiyik/hw_necromancer/5a957a5bcba6f513158159984601a02037ed925c/lifetab_md98486/datasheets/1908271118_Micron-Tech-MT29F64G08CBABAWP-B_C410865.pdf
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/lifetab_md98486/datasheets/RK3066-Rockchip.pdf:
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/lifetab_md98486/datasheets/Rockchip RK3308TRM V1.1 Part1-20180810.pdf:
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https://raw.githubusercontent.com/hbiyik/hw_necromancer/5a957a5bcba6f513158159984601a02037ed925c/lifetab_md98486/datasheets/Rockchip RK3308TRM V1.1 Part1-20180810.pdf
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/lifetab_md98486/datasheets/Rockchip RK3399 TRM V1.4 Part1.pdf:
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https://raw.githubusercontent.com/hbiyik/hw_necromancer/5a957a5bcba6f513158159984601a02037ed925c/lifetab_md98486/datasheets/Rockchip RK3399 TRM V1.4 Part1.pdf
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/lifetab_md98486/datasheets/Rockchip_RK30xx_TRM_V2.0.pdf:
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https://raw.githubusercontent.com/hbiyik/hw_necromancer/5a957a5bcba6f513158159984601a02037ed925c/lifetab_md98486/datasheets/Rockchip_RK30xx_TRM_V2.0.pdf
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/lifetab_md98486/datasheets/schematics/CM-RK3066_SCH.pdf:
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/lifetab_md98486/datasheets/schematics/TAB 10IS(RK3066+MT5931+MT6622).pdf:
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https://raw.githubusercontent.com/hbiyik/hw_necromancer/5a957a5bcba6f513158159984601a02037ed925c/lifetab_md98486/datasheets/schematics/TAB 10IS(RK3066+MT5931+MT6622).pdf
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/lifetab_md98486/datasheets/tps65910.pdf:
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/lifetab_md98486/dts/rk3066a-medion-e10310-u-boot.dtsi:
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1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 |
3 | #include "rk3066a-u-boot.dtsi"
4 |
5 | /{
6 | chosen {
7 | u-boot,spl-boot-order = &mmc0, &emmc, &nfc;
8 | stdout-path = "serial2:1500000n8";
9 | };
10 | };
11 |
12 | &saradc {
13 | vdd-microvolts = <2500000>;
14 | u-boot,dm-spl;
15 | };
16 |
17 | &cru {
18 | u-boot,dm-pre-reloc;
19 | };
20 |
21 | &dmc {
22 | compatible = "rockchip,rk3066-dmc", "syscon";
23 | rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
24 | 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
25 | 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
26 | 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
27 | 0x4 0x0>;
28 | rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
29 | 0x220 0x40 0x0 0x0>;
30 | rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;
31 | };
32 |
33 | &mmc0 {
34 | fifo-mode;
35 | max-frequency = <4000000>;
36 | u-boot,dm-spl;
37 | u-boot,spl-fifo-mode;
38 | status = "okay";
39 | };
40 |
41 | &emmc {
42 | fifo-mode;
43 | max-frequency = <4000000>;
44 | u-boot,dm-spl;
45 | u-boot,spl-fifo-mode;
46 | status = "okay";
47 | cap-mmc-highspeed;
48 | non-removable;
49 | };
50 |
51 | &nfc {
52 | u-boot,dm-spl;
53 |
54 | nand@0 {
55 | u-boot,dm-spl;
56 | };
57 | };
58 |
59 | &noc {
60 | compatible = "rockchip,rk3066-noc", "syscon";
61 | };
62 |
63 | &timer2 {
64 | clock-frequency = <24000000>;
65 | u-boot,dm-pre-reloc;
66 | };
67 |
68 | &uart2 {
69 | u-boot,dm-pre-reloc;
70 | };
71 |
72 |
73 | &usb_host {
74 | u-boot,dm-spl;
75 | };
76 |
77 | &usb_otg {
78 | u-boot,dm-spl;
79 | };
80 |
81 | &usbphy {
82 | u-boot,dm-spl;
83 | };
84 |
85 | &usbphy0 {
86 | u-boot,dm-spl;
87 | };
88 |
89 | &usbphy1 {
90 | u-boot,dm-spl;
91 | };
--------------------------------------------------------------------------------
/lifetab_md98486/dts/rk3066a-medion-e10310.dts:
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1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 | /*
3 | * Copyright (c) 2014 Romain Perier
4 | */
5 |
6 | /dts-v1/;
7 | #include "rk3066a.dtsi"
8 |
9 | / {
10 | model = "Medion E10310";
11 | compatible = "Medion,E10310", "rockchip,rk3066a";
12 |
13 | aliases {
14 | mmc0 = &mmc0;
15 | emmc = &emmc;
16 | };
17 |
18 | chosen {
19 | stdout-path = "serial2:115200n8";
20 | };
21 |
22 | memory@60000000 {
23 | reg = <0x60000000 0x40000000>;
24 | device_type = "memory";
25 | };
26 |
27 | adc-keys {
28 | compatible = "adc-keys";
29 | io-channels = <&saradc 1>;
30 | io-channel-names = "buttons";
31 | keyup-threshold-microvolt = <2500000>;
32 | poll-interval = <100>;
33 |
34 | recovery {
35 | label = "recovery";
36 | press-threshold-microvolt = <0>;
37 | };
38 | };
39 |
40 | hdmi_con {
41 | compatible = "hdmi-connector";
42 | type = "c";
43 |
44 | port {
45 | hdmi_con_in: endpoint {
46 | remote-endpoint = <&hdmi_out_con>;
47 | };
48 | };
49 | };
50 |
51 | vdd_log: vdd-log {
52 | compatible = "pwm-regulator";
53 | pwms = <&pwm3 0 1000>;
54 | regulator-name = "vdd_log";
55 | regulator-min-microvolt = <1200000>;
56 | regulator-max-microvolt = <1200000>;
57 | regulator-always-on;
58 | voltage-table = <1000000 100>, <1200000 42>;
59 | status = "okay";
60 | };
61 |
62 | vsys: vsys-regulator {
63 | compatible = "regulator-fixed";
64 | regulator-name = "vsys";
65 | regulator-min-microvolt = <5000000>;
66 | regulator-max-microvolt = <5000000>;
67 | regulator-boot-on;
68 | };
69 |
70 | vcc_sd0: sdmmc-regulator {
71 | compatible = "regulator-fixed";
72 | regulator-name = "sdmmc-supply";
73 | regulator-min-microvolt = <3300000>;
74 | regulator-max-microvolt = <3300000>;
75 | gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
76 | pinctrl-0 = <&sdmmc_pwr>;
77 | startup-delay-us = <100000>;
78 | vin-supply = <&vcc_io>;
79 | };
80 |
81 | vcc_emmc: emmc-regulator {
82 | compatible = "regulator-fixed";
83 | regulator-name = "emmc_vccq";
84 | regulator-min-microvolt = <3000000>;
85 | regulator-max-microvolt = <3000000>;
86 | vin-supply = <&vsys>;
87 | };
88 |
89 | vcc_host: usb-host-regulator {
90 | compatible = "regulator-fixed";
91 | enable-active-high;
92 | gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
93 | pinctrl-0 = <&host_drv>;
94 | pinctrl-names = "default";
95 | regulator-always-on;
96 | regulator-name = "host-pwr";
97 | regulator-min-microvolt = <5000000>;
98 | regulator-max-microvolt = <5000000>;
99 | startup-delay-us = <100000>;
100 | vin-supply = <&vcc_io>;
101 | };
102 |
103 | vcc_otg: usb-otg-regulator {
104 | compatible = "regulator-fixed";
105 | enable-active-high;
106 | gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
107 | pinctrl-0 = <&otg_drv>;
108 | pinctrl-names = "default";
109 | regulator-always-on;
110 | regulator-name = "vcc_otg";
111 | regulator-min-microvolt = <5000000>;
112 | regulator-max-microvolt = <5000000>;
113 | startup-delay-us = <100000>;
114 | vin-supply = <&vcc_io>;
115 | };
116 |
117 | vcc_wifi: sdio-regulator {
118 | compatible = "regulator-fixed";
119 | enable-active-high;
120 | gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
121 | pinctrl-0 = <&wifi_pwr>;
122 | pinctrl-names = "default";
123 | regulator-name = "vcc_wifi";
124 | regulator-min-microvolt = <3300000>;
125 | regulator-max-microvolt = <3300000>;
126 | startup-delay-us = <100000>;
127 | vin-supply = <&vcc_io>;
128 | };
129 | };
130 |
131 | &hdmi {
132 | status = "okay";
133 | };
134 |
135 | &hdmi_in_vop1 {
136 | status = "disabled";
137 | };
138 |
139 | &hdmi_out {
140 | hdmi_out_con: endpoint {
141 | remote-endpoint = <&hdmi_con_in>;
142 | };
143 | };
144 |
145 | &cpu0 {
146 | cpu-supply = <&vdd_arm>;
147 | };
148 |
149 | &cpu1 {
150 | cpu-supply = <&vdd_arm>;
151 | };
152 |
153 | &i2c1 {
154 | status = "okay";
155 | clock-frequency = <400000>;
156 |
157 | tps: tps@2d {
158 | reg = <0x2d>;
159 |
160 | interrupt-parent = <&gpio6>;
161 | interrupts = ;
162 |
163 | vcc1-supply = <&vsys>;
164 | vcc2-supply = <&vsys>;
165 | vcc3-supply = <&vsys>;
166 | vcc4-supply = <&vsys>;
167 | vcc5-supply = <&vcc_io>;
168 | vcc6-supply = <&vcc_io>;
169 | vcc7-supply = <&vsys>;
170 | vccio-supply = <&vsys>;
171 |
172 | regulators {
173 | vcc_rtc: regulator@0 {
174 | regulator-name = "vcc_rtc";
175 | regulator-always-on;
176 | };
177 |
178 | vcc_io: regulator@1 {
179 | regulator-name = "vcc_io";
180 | regulator-min-microvolt = <3300000>;
181 | regulator-max-microvolt = <3300000>;
182 | regulator-always-on;
183 | };
184 |
185 | vdd_arm: regulator@2 {
186 | regulator-name = "vdd_arm";
187 | regulator-min-microvolt = <600000>;
188 | regulator-max-microvolt = <1500000>;
189 | regulator-boot-on;
190 | regulator-always-on;
191 | };
192 |
193 | vcc_ddr: regulator@3 {
194 | regulator-name = "vcc_ddr";
195 | regulator-min-microvolt = <600000>;
196 | regulator-max-microvolt = <1500000>;
197 | regulator-boot-on;
198 | regulator-always-on;
199 | };
200 |
201 | vcc18_cif: regulator@5 {
202 | regulator-name = "vcc18_cif";
203 | regulator-min-microvolt = <1800000>;
204 | regulator-max-microvolt = <1800000>;
205 | regulator-always-on;
206 | };
207 |
208 | vdd_11: regulator@6 {
209 | regulator-name = "vdd_11";
210 | regulator-min-microvolt = <1100000>;
211 | regulator-max-microvolt = <1100000>;
212 | regulator-always-on;
213 | };
214 |
215 | vcc_25: regulator@7 {
216 | regulator-name = "vcc_25";
217 | regulator-min-microvolt = <2500000>;
218 | regulator-max-microvolt = <2500000>;
219 | regulator-always-on;
220 | };
221 |
222 | vcc_18: regulator@8 {
223 | regulator-name = "vcc_18";
224 | regulator-min-microvolt = <1800000>;
225 | regulator-max-microvolt = <1800000>;
226 | regulator-always-on;
227 | };
228 |
229 | vcc25_hdmi: regulator@9 {
230 | regulator-name = "vcc25_hdmi";
231 | regulator-min-microvolt = <2500000>;
232 | regulator-max-microvolt = <2500000>;
233 | regulator-always-on;
234 | };
235 |
236 | vcca_33: regulator@10 {
237 | regulator-name = "vcca_33";
238 | regulator-min-microvolt = <3300000>;
239 | regulator-max-microvolt = <3300000>;
240 | regulator-always-on;
241 | };
242 |
243 | vcc_rmii: regulator@11 {
244 | regulator-name = "vcc_rmii";
245 | regulator-min-microvolt = <3300000>;
246 | regulator-max-microvolt = <3300000>;
247 | };
248 |
249 | vcc28_cif: regulator@12 {
250 | regulator-name = "vcc28_cif";
251 | regulator-min-microvolt = <2800000>;
252 | regulator-max-microvolt = <2800000>;
253 | regulator-always-on;
254 | };
255 | };
256 | };
257 | };
258 |
259 | /* must be included after &tps gets defined */
260 | #include "tps65910.dtsi"
261 |
262 | &mmc0 {
263 | status = "okay";
264 | bus-width = <4>;
265 | pinctrl-names = "default";
266 | pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
267 | vmmc-supply = <&vcc_sd0>;
268 | };
269 |
270 | &emmc {
271 | status = "okay";
272 | bus-width = <8>;
273 | cap-mmc-highspeed;
274 | non-removable;
275 | pinctrl-names = "default";
276 | pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
277 | vmmc-supply = <&vcc_emmc>;
278 | vqmmc-supply = <&vcc_emmc>;
279 | };
280 |
281 | &pinctrl {
282 | usb-host {
283 | host_drv: host-drv {
284 | rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>;
285 | };
286 | };
287 |
288 | usb-otg {
289 | otg_drv: otg-drv {
290 | rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>;
291 | };
292 | };
293 |
294 | sdmmc {
295 | sdmmc_pwr: sdmmc-pwr {
296 | rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>;
297 | };
298 | };
299 |
300 | sdio {
301 | wifi_pwr: wifi-pwr {
302 | rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
303 | };
304 | };
305 | };
306 |
307 | &nfc {
308 | #address-cells = <1>;
309 | #size-cells = <0>;
310 | status = "okay";
311 |
312 | nand@0 {
313 | reg = <0>;
314 | label = "rk-nand";
315 | nand-bus-width = <8>;
316 | nand-ecc-mode = "hw";
317 | nand-ecc-step-size = <1024>;
318 | nand-ecc-strength = <40>;
319 | nand-is-boot-medium;
320 | rockchip,boot-blks = <8>;
321 | rockchip,boot-ecc-strength = <24>;
322 | };
323 | };
324 |
325 | &saradc {
326 | vref-supply = <&vcc_25>;
327 | status = "okay";
328 | };
329 |
330 | &pwm3 {
331 | status = "okay";
332 | };
333 |
334 | &uart0 {
335 | status = "okay";
336 | };
337 |
338 | &uart1 {
339 | status = "okay";
340 | };
341 |
342 | &uart2 {
343 | status = "okay";
344 | };
345 |
346 | &uart3 {
347 | status = "okay";
348 | };
349 |
350 | &usbphy {
351 | status = "okay";
352 | };
353 |
354 | &usb_host {
355 | vbus-supply = <&vcc_host>;
356 | status = "okay";
357 | };
358 |
359 | &usb_otg {
360 | vbus-supply = <&vcc_otg>;
361 | status = "okay";
362 | };
363 |
364 | &vop0 {
365 | status = "okay";
366 | };
367 |
368 | &wdt {
369 | status = "okay";
370 | };
371 |
--------------------------------------------------------------------------------
/lifetab_md98486/u-boot/medion_e10310_defconfig:
--------------------------------------------------------------------------------
1 | CONFIG_ARM=y
2 | CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
3 | CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
4 | CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
5 | # CONFIG_SPL_SYS_THUMB_BUILD is not set
6 | # CONFIG_TPL_SYS_THUMB_BUILD is not set
7 | # CONFIG_SPL_USE_ARCH_MEMCPY is not set
8 | # CONFIG_SPL_USE_ARCH_MEMSET is not set
9 | CONFIG_ARCH_ROCKCHIP=y
10 |
11 | CONFIG_TPL_TEXT_BASE=0x10080C04
12 | CONFIG_TPL_STACK=0x1008FFFF
13 | CONFIG_TPL_MAX_SIZE=0x7ffc
14 |
15 | CONFIG_SPL_TEXT_BASE=0x60000000
16 | CONFIG_SPL_STACK=0x1008FFFF
17 | CONFIG_SPL_MAX_SIZE=0x32000
18 | CONFIG_SPL_STACK_R_ADDR=0x70000000
19 | CONFIG_SPL_SEPARATE_BSS=y
20 |
21 | CONFIG_TEXT_BASE=0x60408000
22 |
23 | CONFIG_SYS_LOAD_ADDR=0x70800800
24 | CONFIG_SYS_MALLOC_F_LEN=0x1000
25 | CONFIG_NR_DRAM_BANKS=1
26 | CONFIG_ENV_SIZE=0x8000
27 | CONFIG_ROCKCHIP_RK3066=y
28 | # CONFIG_ROCKCHIP_STIMER is not set
29 |
30 |
31 | CONFIG_TARGET_MK808=y
32 |
33 | CONFIG_DEBUG_UART_BASE=0x20064000
34 | CONFIG_DEBUG_UART_CLOCK=24000000
35 | CONFIG_SPL_FS_FAT=y
36 |
37 |
38 | CONFIG_SPL_PAYLOAD="u-boot.bin"
39 | CONFIG_DEBUG_UART=y
40 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
41 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000
42 | CONFIG_SD_BOOT=y
43 | CONFIG_USE_PREBOOT=y
44 | CONFIG_DEFAULT_DEVICE_TREE="rk3066a-medion-e10310"
45 | CONFIG_DEFAULT_FDT_FILE="rk3066a-medion-e10310.dtb"
46 | # CONFIG_DISPLAY_CPUINFO is not set
47 | CONFIG_DISPLAY_BOARDINFO_LATE=y
48 | CONFIG_BOARD_LATE_INIT=y
49 |
50 | CONFIG_SPL_PAD_TO=0x7f8000
51 | CONFIG_SPL_NO_BSS_LIMIT=y
52 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
53 |
54 | CONFIG_SPL_STACK_R=y
55 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x400000
56 | CONFIG_SPL_FS_EXT4=y
57 | CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
58 | CONFIG_TPL_NEEDS_SEPARATE_STACK=y
59 | CONFIG_SYS_CBSIZE=256
60 | CONFIG_SYS_PBSIZE=276
61 | # CONFIG_BOOTM_PLAN9 is not set
62 | # CONFIG_BOOTM_RTEMS is not set
63 | # CONFIG_BOOTM_VXWORKS is not set
64 | CONFIG_CMD_GPT=y
65 | CONFIG_CMD_MMC=y
66 | # CONFIG_CMD_SETEXPR is not set
67 | CONFIG_CMD_CACHE=y
68 | CONFIG_CMD_TIME=y
69 | CONFIG_CMD_REGULATOR=y
70 | CONFIG_SPL_OF_CONTROL=y
71 | CONFIG_TPL_OF_CONTROL=y
72 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
73 | CONFIG_OF_DTB_PROPS_REMOVE=y
74 | CONFIG_TPL_OF_PLATDATA=y
75 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y
76 | # CONFIG_NET is not set
77 | CONFIG_TPL_DM=y
78 | CONFIG_DM_RESET=y
79 | # CONFIG_DM_WARN is not set
80 | CONFIG_REGMAP=y
81 | CONFIG_SPL_REGMAP=y
82 | CONFIG_TPL_REGMAP=y
83 | CONFIG_SYSCON=y
84 | CONFIG_SPL_SYSCON=y
85 | CONFIG_TPL_SYSCON=y
86 | # CONFIG_SIMPLE_BUS is not set
87 | # CONFIG_SPL_SIMPLE_BUS is not set
88 | CONFIG_CLK=y
89 | CONFIG_SPL_CLK=y
90 | CONFIG_TPL_CLK=y
91 | CONFIG_ROCKCHIP_GPIO=y
92 | # CONFIG_SPL_DM_I2C is not set
93 | CONFIG_LED=y
94 | CONFIG_LED_GPIO=y
95 | CONFIG_MMC_IO_VOLTAGE=y
96 | CONFIG_SPL_MMC_IO_VOLTAGE=y
97 | CONFIG_MMC_UHS_SUPPORT=y
98 | CONFIG_SPL_MMC_UHS_SUPPORT=y
99 | CONFIG_MMC_DW=y
100 | CONFIG_MMC_DW_ROCKCHIP=y
101 | CONFIG_SF_DEFAULT_SPEED=20000000
102 | CONFIG_PINCTRL=y
103 | CONFIG_DM_PMIC=y
104 | # CONFIG_SPL_PMIC_CHILDREN is not set
105 | CONFIG_DM_REGULATOR=y
106 | CONFIG_SPL_DM_REGULATOR=y
107 | #CONFIG_SPL_POWER=y
108 | #CONFIG_SPL_PHY=y
109 | CONFIG_DM_REGULATOR_FIXED=y
110 | CONFIG_DM_REGULATOR_GPIO=y
111 | CONFIG_RAM=y
112 | CONFIG_SPL_RAM=y
113 | CONFIG_TPL_RAM=y
114 | CONFIG_DM_RESET=y
115 | # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
116 | CONFIG_DEBUG_UART_SHIFT=2
117 | CONFIG_ROCKCHIP_SERIAL=y
118 | CONFIG_SYSRESET=y
119 | CONFIG_TIMER=y
120 | CONFIG_SPL_TIMER=y
121 | CONFIG_TPL_TIMER=y
122 | CONFIG_DESIGNWARE_APB_TIMER=y
123 | CONFIG_SPL_TINY_MEMSET=y
124 | CONFIG_ERRNO_STR=y
125 | # CONFIG_TPL_OF_LIBFDT is not set
126 |
127 | CONFIG_SPL_ENV_SUPPORT=y
128 | CONFIG_SPL_MMC_WRITE=y
129 | CONFIG_SPL_USB_HOST=y
130 | CONFIG_SPL_USB_STORAGE=y
131 | CONFIG_SPL_USB_GADGET=y
132 | CONFIG_CMD_ADC=y
133 | CONFIG_CMD_USB=y
134 | CONFIG_CMD_ROCKUSB=y
135 | CONFIG_CMD_USB_MASS_STORAGE=y
136 | #CONFIG_CMD_NAND=y
137 | CONFIG_SPL_ADC=y
138 | CONFIG_SPL_SARADC_ROCKCHIP=y
139 | CONFIG_FASTBOOT_BUF_ADDR=0x80000000
140 | CONFIG_USB=y
141 | CONFIG_USB_DWC2=y
142 | CONFIG_ROCKCHIP_USB2_PHY=y
143 | CONFIG_USB_GADGET=y
144 | CONFIG_USB_GADGET_DWC2_OTG=y
145 | CONFIG_USB_FUNCTION_ROCKUSB=y
146 | CONFIG_SPL_USB_FUNCTION_ROCKUSB=y
147 | CONFIG_NAND_BOOT=y
148 | CONFIG_MTD=y
149 | CONFIG_SPL_MTD_SUPPORT=y
150 | CONFIG_SPL_NAND_SUPPORT=y
151 | CONFIG_SPL_NAND_DRIVERS=y
152 | CONFIG_ROCKCHIP_NAND=y
153 | CONFIG_MTD_RAW_NAND=y
154 | CONFIG_MTD_NAND_CORE=y
155 | CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
156 | CONFIG_SYS_NAND_ONFI_DETECTION=y
157 | CONFIG_SYS_NAND_PAGE_COUNT=0x100
158 | CONFIG_SYS_NAND_PAGE_SIZE=0x22E8
159 | CONFIG_SYS_NAND_OOBSIZE=0x2E8
160 | CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
161 | CONFIG_SYS_NAND_U_BOOT_OFFS=0x4000
162 | CONFIG_SPL_NAND_RAW_ONLY=y
163 | CONFIG_TPL_NAND_INIT=y
164 | CONFIG_SPL_NAND_LOAD=y
165 | CONFIG_SPL_NAND_BASE=y
166 | CONFIG_SPL_NAND_IDENT=y
167 | CONFIG_SPL_NAND_BBT=y
168 | CONFIG_SPL_NAND_SIMPLE=y
169 |
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/odys-rise10quad/.gitignore:
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1 | backup
2 | kernel
3 |
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/odys-rise10quad/datasheet/A33 user manual release 1.1.pdf:
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/odys-rise10quad/datasheet/A33_Nand_Flash_Controller_Specification.pdf:
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/odys-rise10quad/datasheet/H27UCG8T2BTR-BC.pdf:
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/odys-rise10quad/datasheet/K4B4G1646Q.pdf:
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/odys-rise10quad/datasheet/axp223.pdf:
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/odys-rise10quad/dts/sun8i-odys-rise10quad.dts:
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1 | /*
2 | * Copyright 2015 Hans de Goede
3 | *
4 | * This file is dual-licensed: you can use it either under the terms
5 | * of the GPL or the X11 license, at your option. Note that this dual
6 | * licensing only applies to this file, and not this project as a
7 | * whole.
8 | *
9 | * a) This file is free software; you can redistribute it and/or
10 | * modify it under the terms of the GNU General Public License as
11 | * published by the Free Software Foundation; either version 2 of the
12 | * License, or (at your option) any later version.
13 | *
14 | * This file is distributed in the hope that it will be useful,
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 | * GNU General Public License for more details.
18 | *
19 | * Or, alternatively,
20 | *
21 | * b) Permission is hereby granted, free of charge, to any person
22 | * obtaining a copy of this software and associated documentation
23 | * files (the "Software"), to deal in the Software without
24 | * restriction, including without limitation the rights to use,
25 | * copy, modify, merge, publish, distribute, sublicense, and/or
26 | * sell copies of the Software, and to permit persons to whom the
27 | * Software is furnished to do so, subject to the following
28 | * conditions:
29 | *
30 | * The above copyright notice and this permission notice shall be
31 | * included in all copies or substantial portions of the Software.
32 | *
33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 | * OTHER DEALINGS IN THE SOFTWARE.
41 | */
42 |
43 | /dts-v1/;
44 | #include "sun8i-a33.dtsi"
45 | #include "sun8i-q8-common.dtsi"
46 |
47 | / {
48 | model = "Odys Rise10Quad";
49 | compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
50 |
51 | aliases {
52 | /* serial0 = &uart0; */
53 | ethernet0 = &sdio_wifi;
54 | };
55 | };
56 |
57 | &tcon0_out {
58 | tcon0_out_lcd: endpoint@0 {
59 | reg = <0>;
60 | remote-endpoint = <&panel_input>;
61 | };
62 | };
63 |
64 | &nfc {
65 | status = "okay";
66 |
67 | pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin &nand_cs1_pin &nand_rb1_pin>;
68 |
69 | /*2*8Gb SKHynix H27UCG8T2BTR-BC*/
70 | nand0: nand@0 {
71 | reg = <0>;
72 | allwinner,rb = <0>;
73 | nand-ecc-mode = "hw";
74 | nand-ecc-strength = <40>;
75 | nand-ecc-step-size = <1024>;
76 | nand-on-flash-bbt;
77 | };
78 |
79 | nand1: nand@1 {
80 | reg = <1>;
81 | allwinner,rb = <1>;
82 | nand-ecc-mode = "hw";
83 | nand-ecc-strength = <40>;
84 | nand-ecc-step-size = <1024>;
85 | nand-on-flash-bbt;
86 | };
87 |
88 | /* Concatenated MTD dev for 2 chips
89 | flash {
90 | compatible = "mtd-concat";
91 | devices = <&nand0 &nand1>;
92 |
93 | partitions {
94 | compatible = "fixed-partitions";
95 | #address-cells = <2>;
96 | #size-cells = <2>;
97 |
98 | partition@0,0 {
99 | label = "bootloader";
100 | reg = <0x0 0x0000000 0x0400000>;
101 | };
102 | partition@0,400000 {
103 | label = "nanddisk";
104 | reg = <0x0 0x0400000 0x3f 0xfc00000>;
105 | };
106 | };
107 | };*/
108 | };
109 |
110 |
111 | &codec {
112 | status = "okay";
113 | };
114 |
115 | &dai {
116 | status = "okay";
117 | };
118 |
119 | &sound {
120 | status = "okay";
121 | };
122 |
123 | &wifi_pwrseq {
124 | reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>;
125 | /* clocks = <&rtc 1>;*/
126 | /* clock-names = "ext_clock";*/
127 | };
128 |
129 |
130 |
131 | /*
132 | *&cpu0_opp_table {
133 | * opp-1104000000 {
134 | * opp-hz = /bits/ 64 <1104000000>;
135 | * opp-microvolt = <1320000>;
136 | * clock-latency-ns = <244144>;
137 | * };
138 | *
139 | * opp-1200000000 {
140 | * opp-hz = /bits/ 64 <1200000000>;
141 | * opp-microvolt = <1320000>;
142 | * clock-latency-ns = <244144>;
143 | * };
144 | *
145 | *
146 | * opp-1300000000 {
147 | * opp-hz = /bits/ 64 <1300000000>;
148 | * opp-microvolt = <1320000>;
149 | * clock-latency-ns = <244144>;
150 | * };
151 | *
152 | * opp-1400000000 {
153 | * opp-hz = /bits/ 64 <1400000000>;
154 | * opp-microvolt = <1400000>;
155 | * clock-latency-ns = <244144>;
156 | * };
157 | *
158 | * opp-1490000000 {
159 | * opp-hz = /bits/ 64 <1480000000>;
160 | * opp-microvolt = <1520000>;
161 | * clock-latency-ns = <244144>;
162 | * };
163 | *
164 | *};
165 | */
166 |
167 | &ohci0 {
168 | status = "okay";
169 | };
170 |
171 | &usb_otg {
172 | dr_mode = "host";
173 | };
174 |
175 | /*
176 | *®_dcdc3 {
177 | * regulator-min-microvolt = <1520000>;
178 | * regulator-max-microvolt = <1520000>;
179 | *};
180 | *
181 | *®_dcdc2 {
182 | * regulator-max-microvolt = <1520000>;
183 | *};
184 | *
185 | *®_dcdc5 {
186 | * regulator-min-microvolt = <1500000>;
187 | * regulator-max-microvolt = <1500000>;
188 | *};
189 | */
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/odys-rise10quad/fel-sdboot.sunxi:
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/odys-rise10quad/fex/dumpfex.sh:
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1 | # Unlike, other allwinner devices,Script.bin is not present in the vfat partition(nanda) as file.
2 | # Instead, It is located 0x43000000, it's size is 0x00020000. script.bin can be extracted from /dev/mem using mmap() or sunxi-tools firmware_extractor.
3 | dd if=/dev/mem of=script.bin bs=1 count=131072 skip=1124073472
4 |
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/odys-rise10quad/fex/lcd.rb:
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1 | #!/usr/bin/env ruby
2 |
3 | if !ARGV[0] || !File.exists?(ARGV[0]) then
4 | abort "Usage: ruby #{__FILE__} [fex_file_name]\n"
5 | end
6 |
7 | def parse_fex_section(filename, section)
8 | results = {}
9 | current_section = ""
10 | File.open(filename).each_line {|l|
11 | current_section = $1 if l =~ /^\[(.*?)\]/
12 | next if current_section != section
13 | results[$1] = $2.strip if l =~ /^(\S+)\s*\=\s*(.*)/
14 | results[$1] = $2.to_i if l =~ /^(\S+)\s*\=\s*(\d+)\s*$/
15 | }
16 | return results
17 | end
18 |
19 | def print_video_lcd_mode(lcd0_para, vt_div)
20 | x = lcd0_para["lcd_x"]
21 | y = lcd0_para["lcd_y"]
22 | depth = { 0 => 24, 1 => 18 }[lcd0_para["lcd_frm"]]
23 | pclk_khz = lcd0_para["lcd_dclk_freq"] * 1000
24 | hs = [1, (lcd0_para["lcd_hv_hspw"] || lcd0_para["lcd_hspw"])].max
25 | vs = [1, (lcd0_para["lcd_hv_vspw"] || lcd0_para["lcd_vspw"])].max
26 | le = lcd0_para["lcd_hbp"] - hs
27 | ri = lcd0_para["lcd_ht"] - x - lcd0_para["lcd_hbp"]
28 | up = lcd0_para["lcd_vbp"] - vs
29 | lo = lcd0_para["lcd_vt"] / vt_div - y - lcd0_para["lcd_vbp"]
30 |
31 | abort "Unsupported 'lcd_frm' parameter" if !depth
32 |
33 | printf("CONFIG_VIDEO_LCD_MODE=\"" +
34 | "x:#{x},y:#{y},depth:#{depth},pclk_khz:#{pclk_khz}," +
35 | "le:#{le},ri:#{ri},up:#{up},lo:#{lo},hs:#{hs},vs:#{vs}," +
36 | "sync:3,vmode:0\"\n")
37 | end
38 |
39 | lcd0_para = parse_fex_section(ARGV[0], "lcd0_para")
40 | abort "Not a valid 'lcd0_para' section" if lcd0_para["lcd_used"] != 1
41 |
42 | printf("== for sun[457]i ==\n")
43 | print_video_lcd_mode(lcd0_para, 2)
44 |
45 | printf("\n== for sun[68]i ==\n")
46 | print_video_lcd_mode(lcd0_para, 1)
47 |
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/odys-rise10quad/fex/script.bin:
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/odys-rise10quad/fex/script.fex:
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1 | [product]
2 | version = "100"
3 | machine = "evb"
4 |
5 | [platform]
6 | eraseflag = 1
7 | next_work = 3
8 |
9 | [target]
10 | boot_clock = 1008
11 | storage_type = 0
12 | burn_key = 1
13 |
14 | [key_detect_en]
15 | keyen_flag = 1
16 |
17 | [power_sply]
18 | dcdc1_vol = 3000
19 | dcdc2_vol = 1100
20 | dcdc3_vol = 1200
21 | dcdc4_vol = 0
22 | dcdc5_vol = 1500
23 | aldo2_vol = 2500
24 | aldo3_vol = 3000
25 |
26 | [card_boot]
27 | logical_start = 40960
28 | sprite_gpio0 =
29 | next_work = 3
30 |
31 | [card0_boot_para]
32 | card_ctrl = 0
33 | card_high_speed = 1
34 | card_line = 4
35 | sdc_d1 = port:PF00<2><1><2>
36 | sdc_d0 = port:PF01<2><1><2>
37 | sdc_clk = port:PF02<2><1><2>
38 | sdc_cmd = port:PF03<2><1><2>
39 | sdc_d3 = port:PF04<2><1><2>
40 | sdc_d2 = port:PF05<2><1><2>
41 |
42 | [card2_boot_para]
43 | card_ctrl = 2
44 | card_high_speed = 1
45 | card_line = 4
46 | sdc_2xmode = 1
47 | sdc_clk = port:PC05<3><1><2>
48 | sdc_cmd = port:PC06<3><1><2>
49 | sdc_d0 = port:PC08<3><1><2>
50 | sdc_d1 = port:PC09<3><1><2>
51 | sdc_d2 = port:PC10<3><1><2>
52 | sdc_d3 = port:PC11<3><1><2>
53 |
54 | [twi_para]
55 | twi_port = 0
56 | twi_scl = port:PH02<2>
57 | twi_sda = port:PH03<2>
58 |
59 | [uart_para]
60 | uart_debug_port = 0
61 | uart_debug_tx = port:PF02<3><1>
62 | uart_debug_rx = port:PF04<3><1>
63 |
64 | [force_uart_para]
65 | force_uart_port = 0
66 | force_uart_tx = port:PF02<3><1>
67 | force_uart_rx = port:PF04<3><1>
68 |
69 | [jtag_para]
70 | jtag_enable = 1
71 | jtag_ms = port:PF00<3>
72 | jtag_ck = port:PF05<3>
73 | jtag_do = port:PF03<3>
74 | jtag_di = port:PF01<3>
75 |
76 | [clock]
77 | pll3 = 297
78 | pll4 = 300
79 | pll6 = 600
80 | pll8 = 408
81 | pll9 = 480
82 | pll10 = 297
83 | pll_cpupat = 0
84 | pll_gpupat = -1002379674
85 | pll_videopat = 0
86 | pll_vepat = 0
87 | pll_hsicpat = 0
88 | pll_depat = 0
89 | pll_mipipat = 0
90 | pll_mipitun = -1979703288
91 | pll_mipibias = -133168128
92 |
93 | [pm_para]
94 | standby_mode = 1
95 |
96 | [dram_para]
97 | dram_clk = 432
98 | dram_type = 3
99 | dram_zq = 0x3bbb
100 | dram_odt_en = 1
101 | dram_para1 = 284296192
102 | dram_para2 = 4096
103 | dram_mr0 = 7280
104 | dram_mr1 = 64
105 | dram_mr2 = 24
106 | dram_mr3 = 0
107 | dram_tpr0 = 0x45a10c
108 | dram_tpr1 = 0x1c22109
109 | dram_tpr2 = 0x4c034
110 | dram_tpr3 = 0x0
111 | dram_tpr4 = 0x0
112 | dram_tpr5 = 0x0
113 | dram_tpr6 = 0x0
114 | dram_tpr7 = 0x0
115 | dram_tpr8 = 0x0
116 | dram_tpr9 = 0x0
117 | dram_tpr10 = 0x0
118 | dram_tpr11 = 0x0
119 | dram_tpr12 = 0xa8
120 | dram_tpr13 = 0x10901
121 |
122 | [pm_para]
123 | standby_mode = 1
124 |
125 | [wakeup_src_para]
126 | cpu_en = 0
127 | cpu_freq = 48
128 | pll_ratio = 273
129 | dram_selfresh_en = 1
130 | dram_freq = 36
131 | wakeup_src_wl = port:PL07<4><0>
132 | wakeup_src_bt = port:PL09<4><0>
133 |
134 | [twi0]
135 | twi_used = 1
136 | twi_scl = port:PH02<2>
137 | twi_sda = port:PH03<2>
138 |
139 | [twi1]
140 | twi_used = 1
141 | twi_scl = port:PH04<2>
142 | twi_sda = port:PH05<2>
143 |
144 | [twi2]
145 | twi_used = 1
146 | twi_scl = port:PE12<3>
147 | twi_sda = port:PE13<3>
148 |
149 | [uart0]
150 | uart_used = 1
151 | uart_port = 0
152 | uart_type = 2
153 | uart_tx = port:PF02<3><1>
154 | uart_rx = port:PF04<3><1>
155 |
156 | [uart1]
157 | uart_used = 1
158 | uart_type = 4
159 | uart_tx = port:PG06<2><1>
160 | uart_rx = port:PG07<2><1>
161 | uart_rts = port:PG08<2><1>
162 | uart_cts = port:PG09<2><1>
163 |
164 | [uart2]
165 | uart_used = 0
166 | uart_type = 4
167 | uart_tx = port:PB00<2><1>
168 | uart_rx = port:PB01<2><1>
169 | uart_rts = port:PB02<2><1>
170 | uart_cts = port:PB03<2><1>
171 |
172 | [uart3]
173 | uart_used = 0
174 | uart_type = 4
175 | uart_tx = port:PH06<3><1>
176 | uart_rx = port:PH07<3><1>
177 | uart_rts = port:PH08<3><1>
178 | uart_cts = port:PH09<3><1>
179 |
180 | [uart4]
181 | uart_used = 0
182 | uart_port = 4
183 | uart_type = 2
184 | uart_tx = port:PA04<2><1>
185 | uart_rx = port:PA05<2><1>
186 | uart_rts = port:PA06<2><1>
187 | uart_cts = port:PA07<2><1>
188 |
189 | [spi0]
190 | spi_used = 0
191 | spi_cs_bitmap = 1
192 | spi_mosi = port:PC00<3>
193 | spi_miso = port:PC01<3>
194 | spi_sclk = port:PC02<3>
195 | spi_cs0 = port:PC03<3><1>
196 |
197 | [spi1]
198 | spi_used = 0
199 | spi_cs_bitmap = 1
200 | spi_cs0 = port:PA00<2><1>
201 | spi_sclk = port:PA01<2>
202 | spi_mosi = port:PA02<2>
203 | spi_miso = port:PA03<2>
204 |
205 | [spi_devices]
206 | spi_dev_num = 0
207 |
208 | [spi_board0]
209 | modalias = "at25df641"
210 | max_speed_hz = 50000000
211 | bus_num = 0
212 | chip_select = 0
213 | mode = 0
214 |
215 | [ctp_para]
216 | ctp_used = 1
217 | ctp_name = "gt9271_1024_600"
218 | ctp_twi_id = 0
219 | ctp_twi_addr = 0x5d
220 | ctp_screen_max_x = 1024
221 | ctp_screen_max_y = 600
222 | ctp_revert_x_flag = 0
223 | ctp_revert_y_flag = 0
224 | ctp_exchange_x_y_flag = 0
225 | gt818_update_file_path = "/system/etc/GT818-Q8-A33-QCY_Config_20141208.cfg"
226 | gt911_update_file_path = "/system/etc/gt911_A23_N02_OPDTP_800_480_20130819.cfg"
227 | gt912_update_file_path = "/system/etc/gt912_A23_N02_OPDTP_800_480_20131029.cfg"
228 | gt927_update_file_path =
229 | gt928_update_file_path =
230 | ctp_int_port = port:PB05<4>
231 | ctp_wakeup = port:PH01<1><1>
232 | ctp_power_ldo = "axp22_ldoio1"
233 | ctp_power_ldo_vol = 3000
234 | ctp_power_io =
235 |
236 | [ctp_list_para]
237 | ctp_det_used = 1
238 | ft5x_ts = 1
239 | gt82x = 1
240 | gslX680 = 1
241 | gslX680new = 0
242 | gt9xx_ts = 1
243 | gt9xxf_ts = 0
244 | tu_ts = 0
245 | gt818_ts = 1
246 | zet622x = 1
247 | aw5306_ts = 1
248 | icn83xx_ts = 0
249 |
250 | [tkey_para]
251 | tkey_used = 0
252 | tkey_twi_id =
253 | tkey_twi_addr =
254 | tkey_int =
255 |
256 | [motor_para]
257 | motor_used = 0
258 | motor_shake = port:power3<1><1>
259 | motor_ldo = ""
260 | motor_ldo_voltage = 3300
261 |
262 | [ths_para]
263 | ths_used = 1
264 | ths_trip1_count = 3
265 | ths_trip1_0 = 75
266 | ths_trip1_1 = 90
267 | ths_trip1_2 = 110
268 | ths_trip1_0_min = 0
269 | ths_trip1_0_max = 1
270 | ths_trip1_1_min = 1
271 | ths_trip1_1_max = 3
272 | ths_trip1_2_min = 0
273 | ths_trip1_2_max = 0
274 |
275 | [cooler_table]
276 | cooler_count = 4
277 | cooler0 = "1344000 4 4294967295 0"
278 | cooler1 = "1200000 4 4294967295 0"
279 | cooler2 = "1008000 4 4294967295 0"
280 | cooler3 = "648000 4 4294967295 0"
281 |
282 | [nand0_para]
283 | nand_support_2ch = 0
284 | nand0_used = 1
285 | nand0_we = port:PC00<2><2>
286 | nand0_ale = port:PC01<2><2>
287 | nand0_cle = port:PC02<2><2>
288 | nand0_ce1 = port:PC03<2><2>
289 | nand0_ce0 = port:PC04<2><2>
290 | nand0_nre = port:PC05<2><2>
291 | nand0_rb0 = port:PC06<2><2>
292 | nand0_rb1 = port:PC07<2><2>
293 | nand0_d0 = port:PC08<2><2>
294 | nand0_d1 = port:PC09<2><2>
295 | nand0_d2 = port:PC10<2><2>
296 | nand0_d3 = port:PC11<2><2>
297 | nand0_d4 = port:PC12<2><2>
298 | nand0_d5 = port:PC13<2><2>
299 | nand0_d6 = port:PC14<2><2>
300 | nand0_d7 = port:PC15<2><2>
301 | nand0_ndqs = port:PC16<2><2>
302 | nand0_ce2 = port:PC17<2><2>
303 | nand0_ce3 = port:PC18<2><2>
304 |
305 | [disp_init]
306 | disp_init_enable = 1
307 | disp_mode = 0
308 | screen0_output_type = 1
309 | screen0_output_mode = 4
310 | screen1_output_type = 1
311 | screen1_output_mode = 4
312 | fb0_format = 10
313 | fb0_pixel_sequence = 0
314 | fb0_scaler_mode_enable = 0
315 | fb0_width = 0
316 | fb0_height = 0
317 | fb1_format = 10
318 | fb1_pixel_sequence = 0
319 | fb1_scaler_mode_enable = 0
320 | fb1_width = 0
321 | fb1_height = 0
322 | lcd0_backlight = 200
323 | lcd1_backlight = 200
324 | lcd0_bright = 50
325 | lcd0_contrast = 50
326 | lcd0_saturation = 57
327 | lcd0_hue = 50
328 | lcd1_bright = 50
329 | lcd1_contrast = 50
330 | lcd1_saturation = 57
331 | lcd1_hue = 50
332 |
333 | [lcd0_para]
334 | lcd_used = 1
335 | lcd_driver_name = "default_lcd"
336 | lcd_if = 3
337 | lcd_x = 1024
338 | lcd_y = 600
339 | lcd_width = 120
340 | lcd_height = 160
341 | lcd_dclk_freq = 56
342 | lcd_pwm_used = 1
343 | lcd_pwm_ch = 0
344 | lcd_pwm_freq = 12000
345 | lcd_pwm_pol = 1
346 | lcd_hbp = 160
347 | lcd_ht = 1344
348 | lcd_hspw = 20
349 | lcd_vbp = 25
350 | lcd_vt = 635
351 | lcd_vspw = 5
352 | lcd_lvds_if = 0
353 | lcd_lvds_colordepth = 0
354 | lcd_lvds_mode = 0
355 | lcd_frm = 1
356 | lcd_io_phase = 0
357 | lcd_gamma_en = 0
358 | lcd_bright_curve_en = 0
359 | lcd_cmap_en = 0
360 | deu_mode = 0
361 | lcdgamma4iep = 22
362 | smart_color = 90
363 | lcd_bl_en = port:PH06<1><0><1>
364 | lcd_power = "axp22_dc1sw"
365 | lcd_gpio_0 = port:PH07<1><0><1>
366 | lcd_gpio_1 = port:PL05<1><0><1>
367 | lcdd18 = port:PD18<3><0>
368 | lcdd19 = port:PD19<3><0>
369 | lcdd20 = port:PD20<3><0>
370 | lcdd21 = port:PD21<3><0>
371 | lcdd22 = port:PD22<3><0>
372 | lcdd23 = port:PD23<3><0>
373 | lcdclk = port:PD24<3><0>
374 | lcdde = port:PD25<3><0>
375 | lcdhsync = port:PD26<3><0>
376 | lcdvsync = port:PD27<3><0>
377 |
378 | [pwm0_para]
379 | pwm_used = 1
380 | pwm_positive = port:PH00<2><0>
381 |
382 | [pwm1_para]
383 | pwm_used = 0
384 | pwm_positive = port:PH01<2><0>
385 |
386 | [csi0]
387 | vip_used = 1
388 | vip_mode = 0
389 | vip_dev_qty = 2
390 | vip_define_sensor_list = 0
391 | vip_csi_pck = port:PE00<2>
392 | vip_csi_mck = port:PE01<2>
393 | vip_csi_hsync = port:PE02<2>
394 | vip_csi_vsync = port:PE03<2>
395 | vip_csi_d0 = port:PE04<2>
396 | vip_csi_d1 = port:PE05<2>
397 | vip_csi_d2 = port:PE06<2>
398 | vip_csi_d3 = port:PE07<2>
399 | vip_csi_d4 = port:PE08<2>
400 | vip_csi_d5 = port:PE09<2>
401 | vip_csi_d6 = port:PE10<2>
402 | vip_csi_d7 = port:PE11<2>
403 | vip_dev0_mname = "gc2155"
404 | vip_dev0_pos = "rear"
405 | vip_dev0_lane = 1
406 | vip_dev0_twi_id = 2
407 | vip_dev0_twi_addr = 120
408 | vip_dev0_isp_used = 0
409 | vip_dev0_fmt = 0
410 | vip_dev0_stby_mode = 0
411 | vip_dev0_vflip = 0
412 | vip_dev0_hflip = 0
413 | vip_dev0_iovdd = "axp22_dldo3"
414 | vip_dev0_iovdd_vol = 2800000
415 | vip_dev0_avdd = "axp22_ldoio0"
416 | vip_dev0_avdd_vol = 2800000
417 | vip_dev0_dvdd = "axp22_eldo2"
418 | vip_dev0_dvdd_vol = 1800000
419 | vip_dev0_afvdd = "axp22_eldo1"
420 | vip_dev0_afvdd_vol = 2800000
421 | vip_dev0_power_en =
422 | vip_dev0_reset = port:PE14<1><0>
423 | vip_dev0_pwdn = port:PE15<1><1>
424 | vip_dev0_flash_en =
425 | vip_dev0_flash_mode =
426 | vip_dev0_af_pwdn =
427 | vip_dev1_mname = "gc0329"
428 | vip_dev1_pos = "front"
429 | vip_dev1_lane = 1
430 | vip_dev1_twi_id = 2
431 | vip_dev1_twi_addr = 98
432 | vip_dev1_isp_used = 0
433 | vip_dev1_fmt = 0
434 | vip_dev1_stby_mode = 0
435 | vip_dev1_vflip = 0
436 | vip_dev1_hflip = 0
437 | vip_dev1_iovdd = "axp22_dldo3"
438 | vip_dev1_iovdd_vol = 2800000
439 | vip_dev1_avdd = "axp22_ldoio0"
440 | vip_dev1_avdd_vol = 2800000
441 | vip_dev1_dvdd = "axp22_eldo2"
442 | vip_dev1_dvdd_vol = 1800000
443 | vip_dev1_afvdd = ""
444 | vip_dev1_afvdd_vol =
445 | vip_dev1_power_en =
446 | vip_dev1_reset = port:PE16<1><0>
447 | vip_dev1_pwdn = port:PE17<1><1>
448 | vip_dev1_flash_en =
449 | vip_dev1_flash_mode =
450 | vip_dev1_af_pwdn =
451 |
452 | [camera_list_para]
453 | camera_list_para_used = 1
454 | gc0328 = 1
455 | gc0329 = 1
456 | gc2155 = 1
457 | gc0308 = 1
458 | gc2035 = 1
459 | ov5647 = 1
460 |
461 | [mmc0_para]
462 | sdc_used = 1
463 | sdc_detmode = 2
464 | sdc_buswidth = 4
465 | sdc_d1 = port:PF00<2><1><2>
466 | sdc_d0 = port:PF01<2><1><2>
467 | sdc_clk = port:PF02<2><1><2>
468 | sdc_cmd = port:PF03<2><1><2>
469 | sdc_d3 = port:PF04<2><1><2>
470 | sdc_d2 = port:PF05<2><1><2>
471 | sdc_det = port:PB04<4><1><2>
472 | sdc_power_supply = "axp22_dcdc1"
473 | sdc_use_wp = 0
474 | sdc_wp =
475 | sdc_isio = 0
476 | sdc_regulator = "none"
477 |
478 | [mmc1_para]
479 | sdc_used = 1
480 | sdc_detmode = 4
481 | sdc_buswidth = 4
482 | sdc_clk = port:PG00<2><1><1>
483 | sdc_cmd = port:PG01<2><1><1>
484 | sdc_d0 = port:PG02<2><1><1>
485 | sdc_d1 = port:PG03<2><1><1>
486 | sdc_d2 = port:PG04<2><1><1>
487 | sdc_d3 = port:PG05<2><1><1>
488 | sdc_det =
489 | sdc_use_wp = 0
490 | sdc_wp =
491 | sdc_isio = 1
492 | sdc_regulator = "none"
493 |
494 | [mmc2_para]
495 | sdc_used = 0
496 | sdc_detmode = 3
497 | sdc_buswidth = 8
498 | sdc_2xmode = 1
499 | sdc_clk = port:PC05<3><1><2>
500 | sdc_cmd = port:PC06<3><1><2>
501 | sdc_d0 = port:PC08<3><1><2>
502 | sdc_d1 = port:PC09<3><1><2>