├── .gitignore ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── pll ├── Manifest.py ├── hdmi_pll.v └── hdmi_pll_xilinx.v ├── requirements.txt ├── syn ├── mkrvidor4000_quartus │ ├── Manifest.py │ └── hdmi-demo.sdc ├── sea_vivado │ └── Manifest.py ├── zybo │ └── Manifest.py └── zybo_z7_20_vivado │ └── Manifest.py └── top ├── mkrvidor4000 ├── Manifest.py ├── mkrvidor4000_top.sv ├── module.tcl └── pinout.tcl ├── sea ├── Manifest.py ├── pinout.xdc └── sea_top.sv ├── zybo ├── Manifest.py ├── pinout.xdc └── zybo_top.sv └── zybo_z7 ├── Manifest.py ├── pinout.xdc └── zybo_z7_top.sv /.gitignore: -------------------------------------------------------------------------------- 1 | .vscode 2 | .venv 3 | *.pin 4 | *.pof 5 | *.sof 6 | *.qpf 7 | *.qsf 8 | *.sid 9 | *.map.* 10 | *.sta.* 11 | *.fit.* 12 | bitstream.tcl 13 | bitstream 14 | incremental_db 15 | *.hdb 16 | *.cdb 17 | *.ddb 18 | *.idb 19 | *.rdb 20 | *.logdb 21 | *.qmsg 22 | *.hsd 23 | *.ammdb 24 | db 25 | *.rpt 26 | *.sld 27 | *.jdi 28 | *.done 29 | *.pow.* 30 | Makefile 31 | project 32 | project.tcl 33 | files.tcl 34 | *.vcd 35 | *.vvp 36 | run.command 37 | modelsim.ini 38 | transcript 39 | work/ 40 | *.wlf 41 | *.rbf 42 | *.jam 43 | *.jbc 44 | *.ttf 45 | greybox_tmp/ 46 | 47 | ip_cores/ 48 | 49 | # Vivado ignore 50 | *.jou 51 | *.log 52 | *.xpr 53 | *.str 54 | *.cache/ 55 | *.hw/ 56 | *.ip_user_files/ 57 | *.runs/ 58 | synthesize.tcl 59 | par 60 | par.tcl 61 | synthesize 62 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Copyright 2019 Sameer Puri 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Sameer Puri 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # hdmi-demo 2 | 3 | Demo of [hdl-util/hdmi](https://github.com/hdl-util/hdmi/) on several boards: 4 | 5 | |Board|FPGA|Video|Audio| 6 | |---|---|---|---| 7 | |[Arduino MKR Vidor 4000](https://store.arduino.cc/usa/mkr-vidor-4000)|Intel Cyclone 10 LP (10CL016)|1280x720 @ 59.94Hz|PCM 24-bit 48KHz| 8 | |[Seeed Spartan Edge Accelerator](https://www.seeedstudio.com/Spartan-Edge-Accelerator-Board-p-4261.html)|Xilinx Spartan 7 (XC7S15)|1280x720 @ 60Hz|PCM 24-bit 48KHz (approximately)| 9 | |[Digilent Zybo](https://digilent.com/reference/programmable-logic/zybo/start)|Xilinx Zynq-7000 (XC7Z010)|1280x720 @ 60Hz|PCM 24-bit 48KHz (approximately)| 10 | |[Digilent Zybo Z7-20](https://digilent.com/shop/zybo-z7-zynq-7000-arm-fpga-soc-development-board/)|Xilinx Zynq-7000 (XC7Z020)|1280x720 @ 60Hz|PCM 24-bit 48KHz (approximately)| 11 | -------------------------------------------------------------------------------- /pll/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "hdmi_pll.v", 3 | "hdmi_pll_xilinx.v" 4 | ] 5 | -------------------------------------------------------------------------------- /pll/hdmi_pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: hdmi_pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 19.1.0 Build 670 09/22/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module hdmi_pll ( 41 | inclk0, 42 | c0, 43 | c1, 44 | c2); 45 | 46 | input inclk0; 47 | output c0; 48 | output c1; 49 | output c2; 50 | 51 | wire [4:0] sub_wire0; 52 | wire [0:0] sub_wire6 = 1'h0; 53 | wire [2:2] sub_wire3 = sub_wire0[2:2]; 54 | wire [1:1] sub_wire2 = sub_wire0[1:1]; 55 | wire [0:0] sub_wire1 = sub_wire0[0:0]; 56 | wire c0 = sub_wire1; 57 | wire c1 = sub_wire2; 58 | wire c2 = sub_wire3; 59 | wire sub_wire4 = inclk0; 60 | wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; 61 | 62 | altpll altpll_component ( 63 | .inclk (sub_wire5), 64 | .clk (sub_wire0), 65 | .activeclock (), 66 | .areset (1'b0), 67 | .clkbad (), 68 | .clkena ({6{1'b1}}), 69 | .clkloss (), 70 | .clkswitch (1'b0), 71 | .configupdate (1'b0), 72 | .enable0 (), 73 | .enable1 (), 74 | .extclk (), 75 | .extclkena ({4{1'b1}}), 76 | .fbin (1'b1), 77 | .fbmimicbidir (), 78 | .fbout (), 79 | .fref (), 80 | .icdrclk (), 81 | .locked (), 82 | .pfdena (1'b1), 83 | .phasecounterselect ({4{1'b1}}), 84 | .phasedone (), 85 | .phasestep (1'b1), 86 | .phaseupdown (1'b1), 87 | .pllena (1'b1), 88 | .scanaclr (1'b0), 89 | .scanclk (1'b0), 90 | .scanclkena (1'b1), 91 | .scandata (1'b0), 92 | .scandataout (), 93 | .scandone (), 94 | .scanread (1'b0), 95 | .scanwrite (1'b0), 96 | .sclkout0 (), 97 | .sclkout1 (), 98 | .vcooverrange (), 99 | .vcounderrange ()); 100 | defparam 101 | altpll_component.bandwidth_type = "AUTO", 102 | altpll_component.clk0_divide_by = 750, 103 | altpll_component.clk0_duty_cycle = 50, 104 | altpll_component.clk0_multiply_by = 1159, 105 | altpll_component.clk0_phase_shift = "0", 106 | altpll_component.clk1_divide_by = 150, 107 | altpll_component.clk1_duty_cycle = 50, 108 | altpll_component.clk1_multiply_by = 1159, 109 | altpll_component.clk1_phase_shift = "0", 110 | altpll_component.clk2_divide_by = 1000, 111 | altpll_component.clk2_duty_cycle = 50, 112 | altpll_component.clk2_multiply_by = 1, 113 | altpll_component.clk2_phase_shift = "0", 114 | altpll_component.compensate_clock = "CLK0", 115 | altpll_component.inclk0_input_frequency = 20833, 116 | altpll_component.intended_device_family = "Cyclone 10 LP", 117 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=hdmi_pll", 118 | altpll_component.lpm_type = "altpll", 119 | altpll_component.operation_mode = "NORMAL", 120 | altpll_component.pll_type = "AUTO", 121 | altpll_component.port_activeclock = "PORT_UNUSED", 122 | altpll_component.port_areset = "PORT_UNUSED", 123 | altpll_component.port_clkbad0 = "PORT_UNUSED", 124 | altpll_component.port_clkbad1 = "PORT_UNUSED", 125 | altpll_component.port_clkloss = "PORT_UNUSED", 126 | altpll_component.port_clkswitch = "PORT_UNUSED", 127 | altpll_component.port_configupdate = "PORT_UNUSED", 128 | altpll_component.port_fbin = "PORT_UNUSED", 129 | altpll_component.port_inclk0 = "PORT_USED", 130 | altpll_component.port_inclk1 = "PORT_UNUSED", 131 | altpll_component.port_locked = "PORT_UNUSED", 132 | altpll_component.port_pfdena = "PORT_UNUSED", 133 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 134 | altpll_component.port_phasedone = "PORT_UNUSED", 135 | altpll_component.port_phasestep = "PORT_UNUSED", 136 | altpll_component.port_phaseupdown = "PORT_UNUSED", 137 | altpll_component.port_pllena = "PORT_UNUSED", 138 | altpll_component.port_scanaclr = "PORT_UNUSED", 139 | altpll_component.port_scanclk = "PORT_UNUSED", 140 | altpll_component.port_scanclkena = "PORT_UNUSED", 141 | altpll_component.port_scandata = "PORT_UNUSED", 142 | altpll_component.port_scandataout = "PORT_UNUSED", 143 | altpll_component.port_scandone = "PORT_UNUSED", 144 | altpll_component.port_scanread = "PORT_UNUSED", 145 | altpll_component.port_scanwrite = "PORT_UNUSED", 146 | altpll_component.port_clk0 = "PORT_USED", 147 | altpll_component.port_clk1 = "PORT_USED", 148 | altpll_component.port_clk2 = "PORT_USED", 149 | altpll_component.port_clk3 = "PORT_UNUSED", 150 | altpll_component.port_clk4 = "PORT_UNUSED", 151 | altpll_component.port_clk5 = "PORT_UNUSED", 152 | altpll_component.port_clkena0 = "PORT_UNUSED", 153 | altpll_component.port_clkena1 = "PORT_UNUSED", 154 | altpll_component.port_clkena2 = "PORT_UNUSED", 155 | altpll_component.port_clkena3 = "PORT_UNUSED", 156 | altpll_component.port_clkena4 = "PORT_UNUSED", 157 | altpll_component.port_clkena5 = "PORT_UNUSED", 158 | altpll_component.port_extclk0 = "PORT_UNUSED", 159 | altpll_component.port_extclk1 = "PORT_UNUSED", 160 | altpll_component.port_extclk2 = "PORT_UNUSED", 161 | altpll_component.port_extclk3 = "PORT_UNUSED", 162 | altpll_component.width_clock = 5; 163 | 164 | 165 | endmodule 166 | 167 | // ============================================================ 168 | // CNX file retrieval info 169 | // ============================================================ 170 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 171 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 172 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 173 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 174 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 175 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 176 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 177 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 179 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 180 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 181 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 182 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 183 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 184 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 185 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 186 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 187 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 188 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 189 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 190 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 191 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 192 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "74.176003" 193 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "370.880005" 194 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.048000" 195 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 196 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 197 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 198 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 199 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 200 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 201 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 202 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" 203 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 204 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 205 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 206 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 207 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 208 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" 209 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 210 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 212 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 213 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 214 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" 215 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 216 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" 217 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 218 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 219 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 220 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 221 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 222 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 223 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 224 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 225 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "74.17600000" 226 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "370.88000000" 227 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.04800000" 228 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 229 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 230 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 231 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 232 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 233 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 234 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 235 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 236 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 237 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 238 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" 239 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 240 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" 241 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" 242 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" 243 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 244 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 245 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 246 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 247 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 248 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 249 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 250 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 251 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 252 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 253 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "hdmi_pll.mif" 254 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 255 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 256 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 257 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 258 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 259 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 260 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 261 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 262 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 263 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 264 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 265 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 266 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 267 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 268 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 269 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 270 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 271 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 272 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 273 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 274 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 275 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 276 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 277 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 278 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 279 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 280 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "750" 281 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 282 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1159" 283 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 284 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "150" 285 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 286 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1159" 287 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 288 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1000" 289 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 290 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" 291 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" 292 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 293 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" 294 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" 295 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 296 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 297 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 298 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 299 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 300 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 301 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 302 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 303 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 304 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 305 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 306 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 307 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 308 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 309 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 310 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 311 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 312 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 313 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 314 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 315 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 316 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 317 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 318 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 319 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 320 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 321 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 322 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 323 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 324 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 325 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 326 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 327 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 328 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 329 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 330 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 331 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 332 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 333 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 334 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 335 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 336 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 337 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 338 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 339 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 340 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 341 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 342 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 343 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 344 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 345 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 346 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 347 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 348 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 349 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 350 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.v TRUE 351 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.ppf TRUE 352 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.inc FALSE 353 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.cmp FALSE 354 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.bsf FALSE 355 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll_inst.v FALSE 356 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll_bb.v FALSE 357 | // Retrieval info: LIB_FILE: altera_mf 358 | // Retrieval info: CBX_MODULE_PREFIX: ON 359 | -------------------------------------------------------------------------------- /pll/hdmi_pll_xilinx.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | 55 | // If using 125MHz clock, add synthesis argument `-verilog_define USE_125MHZ=1` 56 | //---------------------------------------------------------------------------- 57 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 58 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 59 | //---------------------------------------------------------------------------- 60 | // clk_out1____74.256______0.000______50.0______239.766____368.066 61 | // clk_out2___371.280______0.000______50.0______192.979____368.066 62 | // 63 | //---------------------------------------------------------------------------- 64 | // Input Clock Freq (MHz) Input Jitter (UI) 65 | //---------------------------------------------------------------------------- 66 | // __primary_________125.000____________0.010 67 | 68 | // Default: 100MHz clock source 69 | //---------------------------------------------------------------------------- 70 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 71 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 72 | //---------------------------------------------------------------------------- 73 | // clk_out1__74.25000______0.000______50.0______337.616____322.999 74 | // clk_out2__371.25000______0.000______50.0______258.703____322.999 75 | // 76 | //---------------------------------------------------------------------------- 77 | // Input Clock Freq (MHz) Input Jitter (UI) 78 | //---------------------------------------------------------------------------- 79 | // __primary_________100.000____________0.010 80 | 81 | `timescale 1ps/1ps 82 | 83 | module hdmi_pll_xilinx 84 | 85 | (// Clock in ports 86 | // Clock out ports 87 | output clk_out1, 88 | output clk_out2, 89 | input clk_in1 90 | ); 91 | // Input buffering 92 | //------------------------------------ 93 | wire clk_in1_clk_wiz_0; 94 | wire clk_in2_clk_wiz_0; 95 | IBUF clkin1_ibufg 96 | (.O (clk_in1_clk_wiz_0), 97 | .I (clk_in1)); 98 | 99 | 100 | 101 | 102 | // Clocking PRIMITIVE 103 | //------------------------------------ 104 | 105 | // Instantiation of the MMCM PRIMITIVE 106 | // * Unused inputs are tied off 107 | // * Unused outputs are labeled unused 108 | 109 | wire clk_out1_clk_wiz_0; 110 | wire clk_out2_clk_wiz_0; 111 | wire clk_out3_clk_wiz_0; 112 | wire clk_out4_clk_wiz_0; 113 | wire clk_out5_clk_wiz_0; 114 | wire clk_out6_clk_wiz_0; 115 | wire clk_out7_clk_wiz_0; 116 | 117 | wire [15:0] do_unused; 118 | wire drdy_unused; 119 | wire psdone_unused; 120 | wire locked_int; 121 | wire clkfbout_clk_wiz_0; 122 | wire clkfbout_buf_clk_wiz_0; 123 | wire clkfboutb_unused; 124 | wire clkout0b_unused; 125 | wire clkout1b_unused; 126 | wire clkout2_unused; 127 | wire clkout2b_unused; 128 | wire clkout3_unused; 129 | wire clkout3b_unused; 130 | wire clkout4_unused; 131 | wire clkout5_unused; 132 | wire clkout6_unused; 133 | wire clkfbstopped_unused; 134 | wire clkinstopped_unused; 135 | 136 | MMCME2_ADV 137 | #(.BANDWIDTH ("OPTIMIZED"), 138 | .CLKOUT4_CASCADE ("FALSE"), 139 | .COMPENSATION ("ZHOLD"), 140 | .STARTUP_WAIT ("FALSE"), 141 | `ifdef USE_125MHZ 142 | .DIVCLK_DIVIDE (7), 143 | .CLKFBOUT_MULT_F (62.375), 144 | .CLKOUT0_DIVIDE_F (15.000), 145 | .CLKOUT1_DIVIDE (3), 146 | .CLKIN1_PERIOD (8.000), 147 | `else // USE_100MHZ 148 | .DIVCLK_DIVIDE (5), 149 | .CLKFBOUT_MULT_F (37.125), 150 | .CLKOUT0_DIVIDE_F (10.000), 151 | .CLKOUT1_DIVIDE (2), 152 | .CLKIN1_PERIOD (10.000), 153 | `endif 154 | .CLKFBOUT_PHASE (0.000), 155 | .CLKFBOUT_USE_FINE_PS ("FALSE"), 156 | .CLKOUT0_PHASE (0.000), 157 | .CLKOUT0_DUTY_CYCLE (0.500), 158 | .CLKOUT0_USE_FINE_PS ("FALSE"), 159 | .CLKOUT1_PHASE (0.000), 160 | .CLKOUT1_DUTY_CYCLE (0.500), 161 | .CLKOUT1_USE_FINE_PS ("FALSE")) 162 | mmcm_adv_inst 163 | // Output clocks 164 | ( 165 | .CLKFBOUT (clkfbout_clk_wiz_0), 166 | .CLKFBOUTB (clkfboutb_unused), 167 | .CLKOUT0 (clk_out1_clk_wiz_0), 168 | .CLKOUT0B (clkout0b_unused), 169 | .CLKOUT1 (clk_out2_clk_wiz_0), 170 | .CLKOUT1B (clkout1b_unused), 171 | .CLKOUT2 (clkout2_unused), 172 | .CLKOUT2B (clkout2b_unused), 173 | .CLKOUT3 (clkout3_unused), 174 | .CLKOUT3B (clkout3b_unused), 175 | .CLKOUT4 (clkout4_unused), 176 | .CLKOUT5 (clkout5_unused), 177 | .CLKOUT6 (clkout6_unused), 178 | // Input clock control 179 | .CLKFBIN (clkfbout_buf_clk_wiz_0), 180 | .CLKIN1 (clk_in1_clk_wiz_0), 181 | .CLKIN2 (1'b0), 182 | // Tied to always select the primary input clock 183 | .CLKINSEL (1'b1), 184 | // Ports for dynamic reconfiguration 185 | .DADDR (7'h0), 186 | .DCLK (1'b0), 187 | .DEN (1'b0), 188 | .DI (16'h0), 189 | .DO (do_unused), 190 | .DRDY (drdy_unused), 191 | .DWE (1'b0), 192 | // Ports for dynamic phase shift 193 | .PSCLK (1'b0), 194 | .PSEN (1'b0), 195 | .PSINCDEC (1'b0), 196 | .PSDONE (psdone_unused), 197 | // Other control and status signals 198 | .LOCKED (locked_int), 199 | .CLKINSTOPPED (clkinstopped_unused), 200 | .CLKFBSTOPPED (clkfbstopped_unused), 201 | .PWRDWN (1'b0), 202 | .RST (1'b0)); 203 | 204 | // Clock Monitor clock assigning 205 | //-------------------------------------- 206 | // Output buffering 207 | //----------------------------------- 208 | 209 | BUFG clkf_buf 210 | (.O (clkfbout_buf_clk_wiz_0), 211 | .I (clkfbout_clk_wiz_0)); 212 | 213 | 214 | 215 | 216 | 217 | 218 | BUFG clkout1_buf 219 | (.O (clk_out1), 220 | .I (clk_out1_clk_wiz_0)); 221 | 222 | 223 | BUFG clkout2_buf 224 | (.O (clk_out2), 225 | .I (clk_out2_clk_wiz_0)); 226 | 227 | 228 | 229 | endmodule 230 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | hdlmake==3.3 2 | six==1.14.0 3 | -------------------------------------------------------------------------------- /syn/mkrvidor4000_quartus/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "altera" 2 | action = "synthesis" 3 | 4 | syn_family = "CYCLONE 10 LP" 5 | syn_device = "10CL016Y" 6 | syn_grade = "C6G" 7 | syn_package = "U256" 8 | syn_top = "mkrvidor4000_top" 9 | syn_project = "hdmi-demo" 10 | syn_tool = "quartus" 11 | 12 | quartus_preflow = "../../top/mkrvidor4000/pinout.tcl" 13 | quartus_postmodule = "../../top/mkrvidor4000/module.tcl" 14 | 15 | modules = { 16 | "local" : [ 17 | "../../top/mkrvidor4000", 18 | "../../pll" 19 | ], 20 | } 21 | 22 | -------------------------------------------------------------------------------- /syn/mkrvidor4000_quartus/hdmi-demo.sdc: -------------------------------------------------------------------------------- 1 | set_time_format -unit ns -decimal_places 3 2 | 3 | derive_pll_clocks 4 | derive_clock_uncertainty 5 | 6 | -------------------------------------------------------------------------------- /syn/sea_vivado/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "synthesis" 2 | syn_device = "xc7s15" 3 | syn_grade = "-1" 4 | syn_package = "ftgb196" 5 | syn_top = "sea_top" 6 | syn_project = "sea_top" 7 | syn_tool = "vivado" 8 | syn_properties = [ 9 | ["steps.synth_design.args.more options", "-effort_level quick"], 10 | ["steps.synth_design.args.directive", "RunTimeOptimized"], 11 | ["steps.opt_design.args.directive", "RuntimeOptimized"], 12 | ["steps.place_design.args.directive", "RuntimeOptimized"], 13 | ["steps.route_design.args.directive", "RuntimeOptimized"], 14 | ] 15 | 16 | modules = { 17 | "local" : [ 18 | "../../top/sea", 19 | "../../pll" 20 | ], 21 | } 22 | -------------------------------------------------------------------------------- /syn/zybo/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "synthesis" 2 | syn_device = "xc7z010" 3 | syn_grade = "-1" 4 | syn_package = "clg400" 5 | syn_top = "zybo_top" 6 | syn_project = "zybo_top" 7 | syn_tool = "vivado" 8 | syn_properties = [ 9 | ["steps.synth_design.args.more options", "-verilog_define USE_125MHZ=1 -effort_level quick"], 10 | ["steps.synth_design.args.directive", "RunTimeOptimized"], 11 | ["steps.opt_design.args.directive", "RuntimeOptimized"], 12 | ["steps.place_design.args.directive", "RuntimeOptimized"], 13 | ["steps.route_design.args.directive", "RuntimeOptimized"], 14 | ] 15 | 16 | modules = { 17 | "local" : [ 18 | "../../top/zybo", 19 | "../../pll" 20 | ], 21 | } 22 | -------------------------------------------------------------------------------- /syn/zybo_z7_20_vivado/Manifest.py: -------------------------------------------------------------------------------- 1 | action = "synthesis" 2 | syn_device = "xc7z020" 3 | syn_grade = "-1" 4 | syn_package = "clg400" 5 | syn_top = "zybo_z7_top" 6 | syn_project = "zybo_z7_top" 7 | syn_tool = "vivado" 8 | syn_properties = [ 9 | ["steps.synth_design.args.more options", "-verilog_define USE_125MHZ=1 -effort_level quick"], 10 | ["steps.synth_design.args.directive", "RunTimeOptimized"], 11 | ["steps.opt_design.args.directive", "RuntimeOptimized"], 12 | ["steps.place_design.args.directive", "RuntimeOptimized"], 13 | ["steps.route_design.args.directive", "RuntimeOptimized"], 14 | ] 15 | 16 | modules = { 17 | "local" : [ 18 | "../../top/zybo_z7", 19 | "../../pll" 20 | ], 21 | } 22 | -------------------------------------------------------------------------------- /top/mkrvidor4000/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "mkrvidor4000_top.sv", 3 | ] 4 | 5 | modules = { 6 | "git": [ 7 | "https://github.com/hdl-util/hdmi.git::master", 8 | "https://github.com/hdl-util/sound.git::master", 9 | "https://github.com/hdl-util/vga-text-mode.git::master" 10 | ] 11 | } 12 | 13 | fetchto = "../../ip_cores" 14 | 15 | -------------------------------------------------------------------------------- /top/mkrvidor4000/mkrvidor4000_top.sv: -------------------------------------------------------------------------------- 1 | module mkrvidor4000_top 2 | ( 3 | input CLK_48MHZ, 4 | 5 | // HDMI output 6 | output [2:0] HDMI_TX, 7 | output HDMI_CLK, 8 | inout HDMI_SDA, 9 | inout HDMI_SCL, 10 | input HDMI_HPD 11 | ); 12 | 13 | wire clk_pixel_x5; 14 | wire clk_pixel; 15 | wire clk_audio; 16 | hdmi_pll hdmi_pll(.inclk0(CLK_48MHZ), .c0(clk_pixel), .c1(clk_pixel_x5), .c2(clk_audio)); 17 | 18 | localparam AUDIO_BIT_WIDTH = 16; 19 | localparam AUDIO_RATE = 48000; 20 | localparam WAVE_RATE = 480; 21 | 22 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word; 23 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word_dampened; // This is to avoid giving you a heart attack -- it'll be really loud if it uses the full dynamic range. 24 | assign audio_sample_word_dampened = audio_sample_word >> 9; 25 | 26 | sawtooth #(.BIT_WIDTH(AUDIO_BIT_WIDTH), .SAMPLE_RATE(AUDIO_RATE), .WAVE_RATE(WAVE_RATE)) sawtooth (.clk_audio(clk_audio), .level(audio_sample_word)); 27 | 28 | logic [23:0] rgb; 29 | logic [9:0] cx, cy; 30 | hdmi #(.VIDEO_ID_CODE(4), .AUDIO_RATE(AUDIO_RATE), .AUDIO_BIT_WIDTH(AUDIO_BIT_WIDTH)) hdmi(.clk_pixel_x5(clk_pixel_x5), .clk_pixel(clk_pixel), .clk_audio(clk_audio), .rgb(rgb), .audio_sample_word('{audio_sample_word_dampened, audio_sample_word_dampened}), .tmds(HDMI_TX), .tmds_clock(HDMI_CLK), .cx(cx), .cy(cy)); 31 | 32 | logic [7:0] character = 8'h30; 33 | logic [5:0] prevcy = 6'd0; 34 | always @(posedge clk_pixel) 35 | begin 36 | if (cy == 10'd0) 37 | begin 38 | character <= 8'h30; 39 | prevcy <= 6'd0; 40 | end 41 | else if (prevcy != cy[9:4]) 42 | begin 43 | character <= character + 8'h01; 44 | prevcy <= cy[9:4]; 45 | end 46 | end 47 | 48 | console console(.clk_pixel(clk_pixel), .codepoint(character), .attribute({cx[9], cy[8:6], cx[8:5]}), .cx(cx), .cy(cy), .rgb(rgb)); 49 | endmodule 50 | -------------------------------------------------------------------------------- /top/mkrvidor4000/module.tcl: -------------------------------------------------------------------------------- 1 | 2 | set module [lindex $quartus(args) 0] 3 | 4 | 5 | if [string match "quartus_map" $module] { 6 | 7 | # Include commands here that are run 8 | # after analysis and synthesis 9 | post_message "Running after analysis & synthesis" 10 | } 11 | 12 | 13 | if [string match "quartus_fit" $module] { 14 | 15 | # Include commands here that are run 16 | # after fitter (Place & Route) 17 | post_message "Running after place & route" 18 | } 19 | 20 | 21 | if [string match "quartus_asm" $module] { 22 | 23 | # Include commands here that are run 24 | # after assembler (Generate programming files) 25 | post_message "Running after timing analysis" 26 | } 27 | 28 | 29 | if [string match "quartus_tan" $module] { 30 | 31 | # Include commands here that are run 32 | # after timing analysis 33 | post_message "Running after timing analysis" 34 | } 35 | 36 | 37 | -------------------------------------------------------------------------------- /top/mkrvidor4000/pinout.tcl: -------------------------------------------------------------------------------- 1 | 2 | post_message "Assigning pinout" 3 | 4 | # Load Quartus II Tcl Project package 5 | package require ::quartus::project 6 | 7 | project_open -revision hdmi-demo hdmi-demo 8 | 9 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 10 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 11 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" 12 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 13 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 14 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" 15 | set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED 16 | set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON 17 | set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON 18 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON 19 | set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON 20 | 21 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 22 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 23 | set_global_assignment -name ENABLE_OCT_DONE OFF 24 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" 25 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 26 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 27 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 28 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 29 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 30 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 31 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 32 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 33 | set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF 34 | set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF 35 | set_global_assignment -name CONFIGURATION_VCCIO_LEVEL AUTO 36 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 100% 37 | set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON 38 | set_global_assignment -name IGNORE_PARTITIONS ON 39 | # set_global_assignment -name GENERATE_RBF_FILE ON 40 | # set_global_assignment -name GENERATE_TTF_FILE ON 41 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON 42 | # set_global_assignment -name GENERATE_JAM_FILE ON 43 | # set_global_assignment -name GENERATE_JBC_FILE ON 44 | set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD 45 | set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 46 | 47 | set_global_assignment -name ENABLE_SIGNALTAP OFF 48 | 49 | 50 | # system signals 51 | set_location_assignment PIN_E2 -to CLK_48MHZ 52 | set_location_assignment PIN_E1 -to RESETn 53 | 54 | # SDRAM 55 | set_location_assignment PIN_E10 -to SDRAM_ADDR[11] 56 | set_location_assignment PIN_B13 -to SDRAM_ADDR[10] 57 | set_location_assignment PIN_C9 -to SDRAM_ADDR[9] 58 | set_location_assignment PIN_E11 -to SDRAM_ADDR[8] 59 | set_location_assignment PIN_D12 -to SDRAM_ADDR[7] 60 | set_location_assignment PIN_D11 -to SDRAM_ADDR[6] 61 | set_location_assignment PIN_C14 -to SDRAM_ADDR[5] 62 | set_location_assignment PIN_D14 -to SDRAM_ADDR[4] 63 | set_location_assignment PIN_A14 -to SDRAM_ADDR[3] 64 | set_location_assignment PIN_A15 -to SDRAM_ADDR[2] 65 | set_location_assignment PIN_B12 -to SDRAM_ADDR[1] 66 | set_location_assignment PIN_A12 -to SDRAM_ADDR[0] 67 | set_location_assignment PIN_B10 -to SDRAM_BA[1] 68 | set_location_assignment PIN_A10 -to SDRAM_BA[0] 69 | set_location_assignment PIN_B7 -to SDRAM_CASn 70 | set_location_assignment PIN_E9 -to SDRAM_CKE 71 | set_location_assignment PIN_A11 -to SDRAM_CSn 72 | set_location_assignment PIN_B6 -to SDRAM_DQ[15] 73 | set_location_assignment PIN_D6 -to SDRAM_DQ[14] 74 | set_location_assignment PIN_D8 -to SDRAM_DQ[13] 75 | set_location_assignment PIN_E6 -to SDRAM_DQ[12] 76 | set_location_assignment PIN_E8 -to SDRAM_DQ[11] 77 | set_location_assignment PIN_E7 -to SDRAM_DQ[10] 78 | set_location_assignment PIN_C8 -to SDRAM_DQ[9] 79 | set_location_assignment PIN_F8 -to SDRAM_DQ[8] 80 | set_location_assignment PIN_A6 -to SDRAM_DQ[7] 81 | set_location_assignment PIN_B5 -to SDRAM_DQ[6] 82 | set_location_assignment PIN_A5 -to SDRAM_DQ[5] 83 | set_location_assignment PIN_A4 -to SDRAM_DQ[4] 84 | set_location_assignment PIN_A3 -to SDRAM_DQ[3] 85 | set_location_assignment PIN_B3 -to SDRAM_DQ[2] 86 | set_location_assignment PIN_B4 -to SDRAM_DQ[1] 87 | set_location_assignment PIN_A2 -to SDRAM_DQ[0] 88 | set_location_assignment PIN_F9 -to SDRAM_DQM[1] 89 | set_location_assignment PIN_A7 -to SDRAM_DQM[0] 90 | set_location_assignment PIN_D9 -to SDRAM_RASn 91 | set_location_assignment PIN_B14 -to SDRAM_CLK 92 | set_location_assignment PIN_B11 -to SDRAM_WEn 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15] 94 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14] 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13] 96 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11] 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9] 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7] 114 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6] 115 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5] 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4] 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3] 118 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1] 120 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1] 122 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CASn 124 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK 126 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CSn 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1] 128 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RASn 130 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WEn 131 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM* 132 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[11] 133 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[10] 134 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[9] 135 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[8] 136 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[7] 137 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[6] 138 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[5] 139 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[4] 140 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[3] 141 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[2] 142 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[1] 143 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[0] 144 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] 145 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] 146 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM[1] 147 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM[0] 148 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RASn 149 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CASn 150 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WEn 151 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CSn 152 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CKE 153 | 154 | # SAM D21 PINS 155 | set_location_assignment PIN_B1 -to MKR_AREF 156 | set_location_assignment PIN_C2 -to MKR_A[0] 157 | set_location_assignment PIN_C3 -to MKR_A[1] 158 | set_location_assignment PIN_C6 -to MKR_A[2] 159 | set_location_assignment PIN_D1 -to MKR_A[3] 160 | set_location_assignment PIN_D3 -to MKR_A[4] 161 | set_location_assignment PIN_F3 -to MKR_A[5] 162 | set_location_assignment PIN_G2 -to MKR_A[6] 163 | 164 | set_location_assignment PIN_G1 -to MKR_D[0] 165 | set_location_assignment PIN_N3 -to MKR_D[1] 166 | set_location_assignment PIN_P3 -to MKR_D[2] 167 | set_location_assignment PIN_R3 -to MKR_D[3] 168 | set_location_assignment PIN_T3 -to MKR_D[4] 169 | set_location_assignment PIN_T2 -to MKR_D[5] 170 | set_location_assignment PIN_G16 -to MKR_D[6] 171 | set_location_assignment PIN_G15 -to MKR_D[7] 172 | set_location_assignment PIN_F16 -to MKR_D[8] 173 | set_location_assignment PIN_F15 -to MKR_D[9] 174 | set_location_assignment PIN_C16 -to MKR_D[10] 175 | set_location_assignment PIN_C15 -to MKR_D[11] 176 | set_location_assignment PIN_B16 -to MKR_D[12] 177 | set_location_assignment PIN_C11 -to MKR_D[13] 178 | set_location_assignment PIN_A13 -to MKR_D[14] 179 | 180 | # Mini PCIe 181 | set_location_assignment PIN_P8 -to PEX_PIN6 182 | set_location_assignment PIN_L7 -to PEX_PIN8 183 | set_location_assignment PIN_N8 -to PEX_PIN10 184 | set_location_assignment PIN_T8 -to PEX_PIN11 185 | set_location_assignment PIN_M8 -to PEX_PIN12 186 | set_location_assignment PIN_R8 -to PEX_PIN13 187 | set_location_assignment PIN_L8 -to PEX_PIN14 188 | set_location_assignment PIN_M10 -to PEX_PIN16 189 | set_location_assignment PIN_N12 -to PEX_PIN20 190 | set_location_assignment PIN_T9 -to PEX_PIN23 191 | set_location_assignment PIN_R9 -to PEX_PIN25 192 | set_location_assignment PIN_T13 -to PEX_PIN28 193 | set_location_assignment PIN_R12 -to PEX_PIN30 194 | set_location_assignment PIN_A9 -to PEX_PIN31 195 | set_location_assignment PIN_F13 -to PEX_PIN32 196 | set_location_assignment PIN_B9 -to PEX_PIN33 197 | set_location_assignment PIN_R13 -to PEX_PIN42 198 | set_location_assignment PIN_P14 -to PEX_PIN44 199 | set_location_assignment PIN_T15 -to PEX_PIN45 200 | set_location_assignment PIN_R14 -to PEX_PIN46 201 | set_location_assignment PIN_T14 -to PEX_PIN47 202 | set_location_assignment PIN_F14 -to PEX_PIN48 203 | set_location_assignment PIN_D16 -to PEX_PIN49 204 | set_location_assignment PIN_D15 -to PEX_PIN51 205 | set_location_assignment PIN_T12 -to PEX_RST 206 | 207 | # NINA interface 208 | set_location_assignment PIN_J13 -to WM_PIO32 209 | set_location_assignment PIN_T11 -to WM_PIO1 210 | set_location_assignment PIN_R10 -to WM_PIO2 211 | set_location_assignment PIN_P11 -to WM_PIO3 212 | set_location_assignment PIN_R11 -to WM_PIO4 213 | set_location_assignment PIN_N6 -to WM_PIO5 214 | set_location_assignment PIN_P6 -to WM_PIO7 215 | set_location_assignment PIN_N5 -to WM_PIO8 216 | # Blue LED: RMII_RXD0/DAC_16 217 | # set_location_assignment PIN_T4 -to WM_PIO16 218 | # Green LED: RMII_RXD1/DAC_17 219 | # set_location_assignment PIN_R4 -to WM_PIO17 220 | set_location_assignment PIN_T5 -to WM_PIO18 221 | set_location_assignment PIN_R6 -to WM_PIO21 222 | set_location_assignment PIN_R5 -to WM_PIO20 223 | # RMII_MDIO 224 | # set_location_assignment PIN_T7 -to WM_PIO24 225 | # RMII_MDCLK 226 | # set_location_assignment PIN_R7 -to WM_PIO25 227 | set_location_assignment PIN_N9 -to WM_PIO27 228 | set_location_assignment PIN_N11 -to WM_PIO28 229 | set_location_assignment PIN_T10 -to WM_PIO29 230 | set_location_assignment PIN_T4 -to WM_PIO31 231 | set_location_assignment PIN_M6 -to WM_PIO34 232 | set_location_assignment PIN_R4 -to WM_PIO35 233 | set_instance_assignment -name IO_STANDARD "2.5 V" -to WM_PIO36 234 | set_location_assignment PIN_N1 -to WM_PIO36 235 | set_location_assignment PIN_E15 -to WM_TX 236 | set_location_assignment PIN_T6 -to WM_RX 237 | # Aliases for WM_PIO20 WM_PIO21 respectively 238 | # set_location_assignment PIN_R5 -to WM_RTS 239 | # set_location_assignment PIN_R6 -to WM_CTS 240 | set_instance_assignment -name IO_STANDARD "2.5 V" -to WM_RESET 241 | set_location_assignment PIN_R1 -to WM_RESET 242 | 243 | # HDMI output 244 | set_instance_assignment -name IO_STANDARD LVDS -to HDMI_TX* 245 | set_instance_assignment -name IO_STANDARD LVDS -to HDMI_CLK 246 | set_location_assignment PIN_R16 -to HDMI_TX[2] 247 | set_location_assignment PIN_K15 -to HDMI_TX[1] 248 | set_location_assignment PIN_J15 -to HDMI_TX[0] 249 | set_location_assignment PIN_N15 -to HDMI_CLK 250 | set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_SCL 251 | set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_SDA 252 | set_location_assignment PIN_K5 -to HDMI_SCL 253 | set_location_assignment PIN_L4 -to HDMI_SDA 254 | set_location_assignment PIN_M16 -to HDMI_HPD 255 | 256 | # MIPI input 257 | set_instance_assignment -name FAST_INPUT_REGISTER ON -to MIPI_D* 258 | set_instance_assignment -name IO_STANDARD LVDS -to MIPI_D* 259 | set_instance_assignment -name IO_STANDARD LVDS -to MIPI_CLK* 260 | set_location_assignment PIN_L2 -to MIPI_D[0] 261 | set_location_assignment PIN_J2 -to MIPI_D[1] 262 | set_location_assignment PIN_L1 -to MIPI_D[0](n) 263 | set_location_assignment PIN_J1 -to MIPI_D[1](n) 264 | set_location_assignment PIN_M2 -to MIPI_CLK 265 | set_location_assignment PIN_M1 -to MIPI_CLK(n) 266 | set_location_assignment PIN_P2 -to MIPI_SDA 267 | set_instance_assignment -name IO_STANDARD "2.5 V" -to MIPI_SDA 268 | set_location_assignment PIN_P1 -to MIPI_SCL 269 | set_instance_assignment -name IO_STANDARD "2.5 V" -to MIPI_SCL 270 | set_location_assignment PIN_M7 -to MIPI_GP[0] 271 | set_location_assignment PIN_P9 -to MIPI_GP[1] 272 | 273 | # misc pins 274 | # TODO: the FPGA makers assigned HDMI SDA the name "panel_en" no idea why. Maybe open an issue about it? 275 | # set_instance_assignment -name IO_STANDARD "2.5 V" -to panel_en 276 | # set_location_assignment PIN_L4 -to panel_en 277 | 278 | # Flash interface 279 | set_location_assignment PIN_C1 -to FLASH_MOSI 280 | set_location_assignment PIN_H2 -to FLASH_MISO 281 | set_location_assignment PIN_H1 -to FLASH_SCK 282 | set_location_assignment PIN_D2 -to FLASH_CS 283 | set_location_assignment PIN_R7 -to FLASH_HOLD 284 | set_location_assignment PIN_T7 -to FLASH_WP 285 | 286 | # interrupt pins 287 | set_location_assignment PIN_N2 -to SAM_INT_OUT 288 | set_location_assignment PIN_L16 -to SAM_INT_IN 289 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SAM_INT_OUT 290 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SAM_INT_IN 291 | 292 | # dual purpose pins 293 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" 294 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" 295 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" 296 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" 297 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 298 | 299 | # Commit assignments 300 | export_assignments 301 | project_close 302 | -------------------------------------------------------------------------------- /top/sea/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "sea_top.sv", 3 | "pinout.xdc" 4 | ] 5 | 6 | modules = { 7 | "git": [ 8 | "https://github.com/hdl-util/hdmi.git::master", 9 | "https://github.com/hdl-util/sound.git::master", 10 | "https://github.com/hdl-util/vga-text-mode.git::master" 11 | ] 12 | } 13 | 14 | fetchto = "../../ip_cores" 15 | -------------------------------------------------------------------------------- /top/sea/pinout.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS VCCO [current_design] 2 | set_property CONFIG_VOLTAGE 3.3 [current_design] 3 | 4 | # TD0-, TD0+ 5 | set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX[0]}] 6 | set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX_N[0]}] 7 | set_property PACKAGE_PIN F1 [get_ports {HDMI_TX_N[0]}] 8 | set_property PACKAGE_PIN G1 [get_ports {HDMI_TX[0]}] 9 | 10 | # TD1-, TD1+ 11 | set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX[1]}] 12 | set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX_N[1]}] 13 | set_property PACKAGE_PIN D2 [get_ports {HDMI_TX_N[1]}] 14 | set_property PACKAGE_PIN E2 [get_ports {HDMI_TX[1]}] 15 | 16 | # TD2-, TD2+ 17 | set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX[2]}] 18 | set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX_N[2]}] 19 | set_property PACKAGE_PIN C1 [get_ports {HDMI_TX_N[2]}] 20 | set_property PACKAGE_PIN D1 [get_ports {HDMI_TX[2]}] 21 | 22 | # TCK-, TCK+ 23 | set_property IOSTANDARD TMDS_33 [get_ports HDMI_CLK_N] 24 | set_property IOSTANDARD TMDS_33 [get_ports HDMI_CLK] 25 | set_property PACKAGE_PIN F4 [get_ports HDMI_CLK_N] 26 | set_property PACKAGE_PIN G4 [get_ports HDMI_CLK] 27 | 28 | # CEC, SDA, SCL, DPD_DET 29 | set_property IOSTANDARD LVCMOS33 [get_ports HDMI_CEC] 30 | set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SDA] 31 | set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SCL] 32 | set_property IOSTANDARD LVCMOS33 [get_ports HDMI_HPD] 33 | 34 | set_property PULLTYPE PULLUP [get_ports HDMI_CEC] 35 | set_property PULLTYPE PULLUP [get_ports HDMI_SDA] 36 | set_property PULLTYPE PULLUP [get_ports HDMI_SCL] 37 | set_property PULLTYPE PULLUP [get_ports HDMI_HPD] 38 | 39 | set_property PACKAGE_PIN E4 [get_ports HDMI_CEC] 40 | set_property PACKAGE_PIN F2 [get_ports HDMI_SDA] 41 | set_property PACKAGE_PIN F3 [get_ports HDMI_SCL] 42 | set_property PACKAGE_PIN D4 [get_ports HDMI_HPD] 43 | 44 | 45 | set_property IOSTANDARD LVCMOS33 [get_ports RESET] 46 | set_property PACKAGE_PIN D14 [get_ports RESET] 47 | 48 | set_property IOSTANDARD LVCMOS33 [get_ports CLK_100MHZ] 49 | set_property PACKAGE_PIN H4 [get_ports CLK_100MHZ] 50 | create_clock -add -name CLK_100MHZ -period 10.00 -waveform {0 5} [get_ports CLK_100MHZ] 51 | 52 | set_property IOSTANDARD LVCMOS33 [get_ports LED[0]] 53 | set_property IOSTANDARD LVCMOS33 [get_ports LED[1]] 54 | set_property PACKAGE_PIN J1 [get_ports LED[0]] 55 | set_property PACKAGE_PIN A13 [get_ports LED[1]] 56 | -------------------------------------------------------------------------------- /top/sea/sea_top.sv: -------------------------------------------------------------------------------- 1 | module sea_top 2 | ( 3 | input CLK_100MHZ, 4 | 5 | output [1:0] LED, 6 | 7 | // HDMI output 8 | output [2:0] HDMI_TX, 9 | output [2:0] HDMI_TX_N, 10 | output HDMI_CLK, 11 | output HDMI_CLK_N, 12 | input HDMI_CEC, 13 | inout HDMI_SDA, 14 | inout HDMI_SCL, 15 | input HDMI_HPD 16 | ); 17 | 18 | wire clk_pixel_x5; 19 | wire clk_pixel; 20 | wire clk_audio; 21 | hdmi_pll_xilinx hdmi_pll(.clk_in1(CLK_100MHZ), .clk_out1(clk_pixel), .clk_out2(clk_pixel_x5)); 22 | 23 | logic [10:0] counter = 1'd0; 24 | always_ff @(posedge clk_pixel) 25 | begin 26 | counter <= counter == 11'd1546 ? 1'd0 : counter + 1'd1; 27 | end 28 | assign clk_audio = clk_pixel && counter == 11'd1546; 29 | 30 | localparam AUDIO_BIT_WIDTH = 16; 31 | localparam AUDIO_RATE = 48000; 32 | localparam WAVE_RATE = 480; 33 | 34 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word; 35 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word_dampened; // This is to avoid giving you a heart attack -- it'll be really loud if it uses the full dynamic range. 36 | assign audio_sample_word_dampened = audio_sample_word >> 9; 37 | 38 | sawtooth #(.BIT_WIDTH(AUDIO_BIT_WIDTH), .SAMPLE_RATE(AUDIO_RATE), .WAVE_RATE(WAVE_RATE)) sawtooth (.clk_audio(clk_audio), .level(audio_sample_word)); 39 | 40 | logic [23:0] rgb; 41 | logic [9:0] cx, cy; 42 | logic [2:0] tmds; 43 | logic tmds_clock; 44 | hdmi #(.VIDEO_ID_CODE(4), .VIDEO_REFRESH_RATE(60.0), .AUDIO_RATE(AUDIO_RATE), .AUDIO_BIT_WIDTH(AUDIO_BIT_WIDTH)) hdmi(.clk_pixel_x5(clk_pixel_x5), .clk_pixel(clk_pixel), .clk_audio(clk_audio), .rgb(rgb), .audio_sample_word('{audio_sample_word_dampened, audio_sample_word_dampened}), .tmds(tmds), .tmds_clock(tmds_clock), .cx(cx), .cy(cy)); 45 | 46 | genvar i; 47 | generate 48 | for (i = 0; i < 3; i++) 49 | begin: obufds_gen 50 | OBUFDS #(.IOSTANDARD("TMDS_33")) obufds (.I(tmds[i]), .O(HDMI_TX[i]), .OB(HDMI_TX_N[i])); 51 | end 52 | OBUFDS #(.IOSTANDARD("TMDS_33")) obufds_clock(.I(tmds_clock), .O(HDMI_CLK), .OB(HDMI_CLK_N)); 53 | endgenerate 54 | 55 | logic [7:0] character = 8'h30; 56 | logic [5:0] prevcy = 6'd0; 57 | always @(posedge clk_pixel) 58 | begin 59 | if (cy == 10'd0) 60 | begin 61 | character <= 8'h30; 62 | prevcy <= 6'd0; 63 | end 64 | else if (prevcy != cy[9:4]) 65 | begin 66 | character <= character + 8'h01; 67 | prevcy <= cy[9:4]; 68 | end 69 | end 70 | 71 | console console(.clk_pixel(clk_pixel), .codepoint(character), .attribute({cx[9], cy[8:6], cx[8:5]}), .cx(cx), .cy(cy), .rgb(rgb)); 72 | endmodule 73 | -------------------------------------------------------------------------------- /top/zybo/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "zybo_top.sv", 3 | "pinout.xdc" 4 | ] 5 | 6 | modules = { 7 | "git": [ 8 | "https://github.com/hdl-util/hdmi.git::master", 9 | "https://github.com/hdl-util/sound.git::master", 10 | "https://github.com/hdl-util/vga-text-mode.git::master" 11 | ] 12 | } 13 | 14 | fetchto = "../../ip_cores" 15 | -------------------------------------------------------------------------------- /top/zybo/pinout.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS VCCO [current_design] 2 | set_property CONFIG_VOLTAGE 3.3 [current_design] 3 | 4 | ## TD0-, TD0+ 5 | set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports HDMI_TX[0]] 6 | set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX_N[0]] 7 | 8 | ## TD1-, TD1+ 9 | set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX[1]] 10 | set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX_N[1]] 11 | 12 | ## TD2-, TD2+ 13 | set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports HDMI_TX[2]] 14 | set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX_N[2]] 15 | 16 | # TCK-, TCK+ 17 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports HDMI_CLK_N] 18 | set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports HDMI_CLK] 19 | 20 | # CEC, SDA, SCL, DPD_DET 21 | set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports HDMI_CEC] 22 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports HDMI_SDA] 23 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports HDMI_SCL] 24 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports HDMI_HPD] 25 | 26 | set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports RESET] 27 | 28 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports CLK_125MHZ] 29 | create_clock -add -name CLK_125MHZ -period 8.00 -waveform {0 4} [get_ports CLK_125MHZ] 30 | 31 | set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports LED[0]] 32 | set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports LED[1]] 33 | -------------------------------------------------------------------------------- /top/zybo/zybo_top.sv: -------------------------------------------------------------------------------- 1 | module zybo_top 2 | ( 3 | input CLK_125MHZ, 4 | 5 | output [1:0] LED, 6 | 7 | // HDMI output 8 | output [2:0] HDMI_TX, 9 | output [2:0] HDMI_TX_N, 10 | output HDMI_CLK, 11 | output HDMI_CLK_N, 12 | input HDMI_CEC, 13 | inout HDMI_SDA, 14 | inout HDMI_SCL, 15 | input HDMI_HPD 16 | ); 17 | 18 | wire clk_pixel_x5; 19 | wire clk_pixel; 20 | wire clk_audio; 21 | hdmi_pll_xilinx hdmi_pll(.clk_in1(CLK_125MHZ), .clk_out1(clk_pixel), .clk_out2(clk_pixel_x5)); 22 | 23 | logic [10:0] counter = 1'd0; 24 | always_ff @(posedge clk_pixel) 25 | begin 26 | counter <= counter == 11'd1546 ? 1'd0 : counter + 1'd1; 27 | end 28 | assign clk_audio = clk_pixel && counter == 11'd1546; 29 | 30 | localparam AUDIO_BIT_WIDTH = 16; 31 | localparam AUDIO_RATE = 48000; 32 | localparam WAVE_RATE = 480; 33 | 34 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word; 35 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word_dampened; // This is to avoid giving you a heart attack -- it'll be really loud if it uses the full dynamic range. 36 | assign audio_sample_word_dampened = audio_sample_word >> 9; 37 | 38 | sawtooth #(.BIT_WIDTH(AUDIO_BIT_WIDTH), .SAMPLE_RATE(AUDIO_RATE), .WAVE_RATE(WAVE_RATE)) sawtooth (.clk_audio(clk_audio), .level(audio_sample_word)); 39 | 40 | logic [23:0] rgb; 41 | logic [9:0] cx, cy; 42 | logic [2:0] tmds; 43 | logic tmds_clock; 44 | hdmi #(.VIDEO_ID_CODE(4), .VIDEO_REFRESH_RATE(60.0), .AUDIO_RATE(AUDIO_RATE), .AUDIO_BIT_WIDTH(AUDIO_BIT_WIDTH)) hdmi(.clk_pixel_x5(clk_pixel_x5), .clk_pixel(clk_pixel), .clk_audio(clk_audio), .rgb(rgb), .audio_sample_word('{audio_sample_word_dampened, audio_sample_word_dampened}), .tmds(tmds), .tmds_clock(tmds_clock), .cx(cx), .cy(cy)); 45 | 46 | genvar i; 47 | generate 48 | for (i = 0; i < 3; i++) 49 | begin: obufds_gen 50 | OBUFDS #(.IOSTANDARD("TMDS_33")) obufds (.I(tmds[i]), .O(HDMI_TX[i]), .OB(HDMI_TX_N[i])); 51 | end 52 | OBUFDS #(.IOSTANDARD("TMDS_33")) obufds_clock(.I(tmds_clock), .O(HDMI_CLK), .OB(HDMI_CLK_N)); 53 | endgenerate 54 | 55 | logic [7:0] character = 8'h30; 56 | logic [5:0] prevcy = 6'd0; 57 | always @(posedge clk_pixel) 58 | begin 59 | if (cy == 10'd0) 60 | begin 61 | character <= 8'h30; 62 | prevcy <= 6'd0; 63 | end 64 | else if (prevcy != cy[9:4]) 65 | begin 66 | character <= character + 8'h01; 67 | prevcy <= cy[9:4]; 68 | end 69 | end 70 | 71 | console console(.clk_pixel(clk_pixel), .codepoint(character), .attribute({cx[9], cy[8:6], cx[8:5]}), .cx(cx), .cy(cy), .rgb(rgb)); 72 | endmodule 73 | -------------------------------------------------------------------------------- /top/zybo_z7/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "zybo_z7_top.sv", 3 | "pinout.xdc" 4 | ] 5 | 6 | modules = { 7 | "git": [ 8 | "https://github.com/hdl-util/hdmi.git::master", 9 | "https://github.com/hdl-util/sound.git::master", 10 | "https://github.com/hdl-util/vga-text-mode.git::master" 11 | ] 12 | } 13 | 14 | fetchto = "../../ip_cores" 15 | -------------------------------------------------------------------------------- /top/zybo_z7/pinout.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS VCCO [current_design] 2 | set_property CONFIG_VOLTAGE 3.3 [current_design] 3 | 4 | ## TD0-, TD0+ 5 | set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports HDMI_TX[0]] 6 | set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX_N[0]] 7 | 8 | ## TD1-, TD1+ 9 | set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX[1]] 10 | set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX_N[1]] 11 | 12 | ## TD2-, TD2+ 13 | set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports HDMI_TX[2]] 14 | set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports HDMI_TX_N[2]] 15 | 16 | # TCK-, TCK+ 17 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports HDMI_CLK_N] 18 | set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports HDMI_CLK] 19 | 20 | # CEC, SDA, SCL, DPD_DET 21 | set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports HDMI_CEC] 22 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports HDMI_SDA] 23 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports HDMI_SCL] 24 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports HDMI_HPD] 25 | 26 | 27 | set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports RESET] 28 | 29 | set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports CLK_125MHZ] 30 | create_clock -add -name CLK_125MHZ -period 8.00 -waveform {0 4} [get_ports CLK_125MHZ] 31 | 32 | set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports LED[0]] 33 | set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports LED[1]] 34 | -------------------------------------------------------------------------------- /top/zybo_z7/zybo_z7_top.sv: -------------------------------------------------------------------------------- 1 | module zybo_z7_top 2 | ( 3 | input CLK_125MHZ, 4 | 5 | output [1:0] LED, 6 | 7 | // HDMI output 8 | output [2:0] HDMI_TX, 9 | output [2:0] HDMI_TX_N, 10 | output HDMI_CLK, 11 | output HDMI_CLK_N, 12 | input HDMI_CEC, 13 | inout HDMI_SDA, 14 | inout HDMI_SCL, 15 | input HDMI_HPD 16 | ); 17 | 18 | wire clk_pixel_x5; 19 | wire clk_pixel; 20 | wire clk_audio; 21 | hdmi_pll_xilinx hdmi_pll(.clk_in1(CLK_125MHZ), .clk_out1(clk_pixel), .clk_out2(clk_pixel_x5)); 22 | 23 | logic [10:0] counter = 1'd0; 24 | always_ff @(posedge clk_pixel) 25 | begin 26 | counter <= counter == 11'd1546 ? 1'd0 : counter + 1'd1; 27 | end 28 | assign clk_audio = clk_pixel && counter == 11'd1546; 29 | 30 | localparam AUDIO_BIT_WIDTH = 16; 31 | localparam AUDIO_RATE = 48000; 32 | localparam WAVE_RATE = 480; 33 | 34 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word; 35 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word_dampened; // This is to avoid giving you a heart attack -- it'll be really loud if it uses the full dynamic range. 36 | assign audio_sample_word_dampened = audio_sample_word >> 9; 37 | 38 | sawtooth #(.BIT_WIDTH(AUDIO_BIT_WIDTH), .SAMPLE_RATE(AUDIO_RATE), .WAVE_RATE(WAVE_RATE)) sawtooth (.clk_audio(clk_audio), .level(audio_sample_word)); 39 | 40 | logic [23:0] rgb; 41 | logic [9:0] cx, cy; 42 | logic [2:0] tmds; 43 | logic tmds_clock; 44 | hdmi #(.VIDEO_ID_CODE(4), .VIDEO_REFRESH_RATE(60.0), .AUDIO_RATE(AUDIO_RATE), .AUDIO_BIT_WIDTH(AUDIO_BIT_WIDTH)) hdmi(.clk_pixel_x5(clk_pixel_x5), .clk_pixel(clk_pixel), .clk_audio(clk_audio), .rgb(rgb), .audio_sample_word('{audio_sample_word_dampened, audio_sample_word_dampened}), .tmds(tmds), .tmds_clock(tmds_clock), .cx(cx), .cy(cy)); 45 | 46 | genvar i; 47 | generate 48 | for (i = 0; i < 3; i++) 49 | begin: obufds_gen 50 | OBUFDS #(.IOSTANDARD("TMDS_33")) obufds (.I(tmds[i]), .O(HDMI_TX[i]), .OB(HDMI_TX_N[i])); 51 | end 52 | OBUFDS #(.IOSTANDARD("TMDS_33")) obufds_clock(.I(tmds_clock), .O(HDMI_CLK), .OB(HDMI_CLK_N)); 53 | endgenerate 54 | 55 | logic [7:0] character = 8'h30; 56 | logic [5:0] prevcy = 6'd0; 57 | always @(posedge clk_pixel) 58 | begin 59 | if (cy == 10'd0) 60 | begin 61 | character <= 8'h30; 62 | prevcy <= 6'd0; 63 | end 64 | else if (prevcy != cy[9:4]) 65 | begin 66 | character <= character + 8'h01; 67 | prevcy <= cy[9:4]; 68 | end 69 | end 70 | 71 | console console(.clk_pixel(clk_pixel), .codepoint(character), .attribute({cx[9], cy[8:6], cx[8:5]}), .cx(cx), .cy(cy), .rgb(rgb)); 72 | endmodule 73 | --------------------------------------------------------------------------------