├── requirements.txt ├── demo.jpg ├── pll ├── Manifest.py ├── mem_pll.v └── hdmi_pll.v ├── syn └── mkrvidor4000_quartus │ ├── altera-usb-blaster.cfg │ ├── Manifest.py │ └── mipi-demo.sdc ├── .gitignore ├── LICENSE-APACHE ├── top └── mkrvidor4000 │ ├── Manifest.py │ ├── module.tcl │ ├── mkrvidor4000_top.sv │ ├── arbiter.sv │ └── pinout.tcl ├── LICENSE-MIT └── README.md /requirements.txt: -------------------------------------------------------------------------------- 1 | hdlmake==3.3 2 | six==1.14.0 3 | -------------------------------------------------------------------------------- /demo.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hdl-util/mipi-demo/HEAD/demo.jpg -------------------------------------------------------------------------------- /pll/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "hdmi_pll.v", 3 | "mem_pll.v" 4 | ] 5 | -------------------------------------------------------------------------------- /syn/mkrvidor4000_quartus/altera-usb-blaster.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # Altera USB-Blaster 3 | # 4 | # http://www.altera.com/literature/ug/ug_usb_blstr.pdf 5 | # 6 | 7 | interface usb_blaster 8 | # These are already the defaults. 9 | # usb_blaster_vid_pid 0x09FB 0x6001 10 | # usb_blaster_device_desc "USB-Blaster" 11 | init 12 | scan_chain 13 | svf hdmi-demo.svf 14 | exit 15 | -------------------------------------------------------------------------------- /syn/mkrvidor4000_quartus/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "altera" 2 | action = "synthesis" 3 | 4 | syn_family = "CYCLONE 10 LP" 5 | syn_device = "10CL016Y" 6 | syn_grade = "C8G" 7 | syn_package = "U256" 8 | syn_top = "mkrvidor4000_top" 9 | syn_project = "mipi-demo" 10 | syn_tool = "quartus" 11 | 12 | quartus_preflow = "../../top/mkrvidor4000/pinout.tcl" 13 | quartus_postmodule = "../../top/mkrvidor4000/module.tcl" 14 | 15 | modules = { 16 | "local" : [ 17 | "../../top/mkrvidor4000", 18 | "../../pll" 19 | ], 20 | } 21 | 22 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .vscode 2 | .venv 3 | *.pin 4 | *.pof 5 | *.sof 6 | *.qpf 7 | *.qsf 8 | *.sid 9 | *.map.* 10 | *.sta.* 11 | *.fit.* 12 | bitstream.tcl 13 | bitstream 14 | incremental_db 15 | *.hdb 16 | *.cdb 17 | *.ddb 18 | *.idb 19 | *.rdb 20 | *.logdb 21 | *.qmsg 22 | *.hsd 23 | *.ammdb 24 | db 25 | *.rpt 26 | *.sld 27 | *.jdi 28 | *.done 29 | *.pow.* 30 | Makefile 31 | project 32 | project.tcl 33 | files.tcl 34 | *.vcd 35 | *.vvp 36 | run.command 37 | modelsim.ini 38 | transcript 39 | work/ 40 | *.wlf 41 | ip_cores/ 42 | *.jam 43 | *.svf 44 | greybox_tmp/ 45 | *.qip 46 | *.ppf 47 | qmegawiz_errors_log.txt 48 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Copyright 2020 Sameer Puri 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | -------------------------------------------------------------------------------- /top/mkrvidor4000/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "mkrvidor4000_top.sv", 3 | "arbiter.sv" 4 | ] 5 | 6 | modules = { 7 | "git": [ 8 | "git@github.com:hdl-util/hdmi.git::master", 9 | "git@github.com:hdl-util/sound.git::master", 10 | "git@github.com:hdl-util/vga-text-mode.git::master", 11 | "git@github.com:hdl-util/mipi-ccs.git::master", 12 | "git@github.com:hdl-util/mipi-csi-2.git::master", 13 | "git@github.com:hdl-util/sdram-controller.git::master", 14 | "git@github.com:hdl-util/clock-domain-crossing.git::master", 15 | ] 16 | } 17 | 18 | fetchto = "../../ip_cores" 19 | 20 | -------------------------------------------------------------------------------- /top/mkrvidor4000/module.tcl: -------------------------------------------------------------------------------- 1 | 2 | set module [lindex $quartus(args) 0] 3 | 4 | 5 | if [string match "quartus_map" $module] { 6 | 7 | # Include commands here that are run 8 | # after analysis and synthesis 9 | post_message "Running after analysis & synthesis" 10 | } 11 | 12 | 13 | if [string match "quartus_fit" $module] { 14 | 15 | # Include commands here that are run 16 | # after fitter (Place & Route) 17 | post_message "Running after place & route" 18 | } 19 | 20 | 21 | if [string match "quartus_asm" $module] { 22 | 23 | # Include commands here that are run 24 | # after assembler (Generate programming files) 25 | post_message "Running after timing analysis" 26 | } 27 | 28 | 29 | if [string match "quartus_tan" $module] { 30 | 31 | # Include commands here that are run 32 | # after timing analysis 33 | post_message "Running after timing analysis" 34 | } 35 | 36 | 37 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Sameer Puri 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /syn/mkrvidor4000_quartus/mipi-demo.sdc: -------------------------------------------------------------------------------- 1 | set_time_format -unit ns -decimal_places 3 2 | #create_clock -name MIPI_CLK -period 15.38 [get_ports {MIPI_CLK}] 3 | create_clock -name CLK_48MHZ -period "48.0 MHz" [get_ports {CLK_48MHZ}] 4 | create_generated_clock -name SDRAM_CLK -source [get_pins mem_pll|altpll_component|auto_generated|pll1|clk[0]] [get_ports {SDRAM_CLK}] 5 | 6 | derive_pll_clocks 7 | derive_clock_uncertainty 8 | 9 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_A*] 10 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_D*] 11 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_R*] 12 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_CA*] 13 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_CK*] 14 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_CS*] 15 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_W*] 16 | set_output_delay -max 1.5 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_BA*] 17 | 18 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_A*] 19 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_D*] 20 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_R*] 21 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_CA*] 22 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_CK*] 23 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_CS*] 24 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_W*] 25 | set_output_delay -min -0.8 -clock [get_clocks SDRAM_CLK] [get_ports SDRAM_BA*] 26 | 27 | 28 | # set_false_path -from [get_clocks {MIPI_CLK}] -to [get_clocks {mem_pll|altpll_component|auto_generated|pll1|clk[2]}] 29 | # set_false_path -from [get_clocks {mem_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MIPI_CLK}] 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # mipi-demo 2 | 3 | Live stream frames from a Raspberry Pi Camera v1.1 (OV5647) over HDMI. 4 | 5 | Cumulative demonstration of a year-long journey working on the following projects: 6 | 7 | * [hdl-util/hdmi](https://github.com/hdl-util/hdmi/): video/audio transmission over [HDMI](https://en.wikipedia.org/wiki/HDMI) 8 | * [hdl-util/mipi-ccs](https://github.com/hdl-util/mipi-ccs): camera control with [MIPI CCS](https://www.mipi.org/specifications/camera-command-set) 9 | * [hdl-util/i2c](https://github.com/hdl-util/i2c): [I2C](https://en.wikipedia.org/wiki/I%C2%B2C) master 10 | * [hdl-util/mipi-csi-2](https://github.com/hdl-util/mipi-csi-2): camera video reception with [MIPI CSI 2](https://www.mipi.org/specifications/csi-2) 11 | * [hdl-util/sdram-controller](https://github.com/hdl-util/sdram-controller/): generic [SDRAM](https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory) controller 12 | * [hdl-util/clock-domain-crossing](https://github.com/hdl-util/clock-domain-crossing): utilities for [clock domain crossing](https://en.wikipedia.org/wiki/Clock_domain_crossing) on FPGAs 13 | * [hdl-util/gray-code](https://github.com/hdl-util/gray-code): arbitrary width [Gray codes](https://en.wikipedia.org/wiki/Gray_code) 14 | 15 | ## Demo 16 | 17 | Picture taken with a Pixel 3a of an OV5647 video stream on an LG 4K monitor at 640x480 resolution: 18 | 19 | ![Picture of the video stream](demo.jpg) 20 | 21 | Please forgive the horrible focus of the image, I'm using a knockoff OV5647 module with fixed-focus. 22 | The image is received in RAW8 format and hasn't been processed yet, hence the lack of color. 23 | 24 | ## What's next? 25 | 26 | * [Demosaicing](https://en.wikipedia.org/wiki/Bayer_filter#Demosaicing) 27 | * IMX219 control 28 | * This is commonly available as the [Raspberry Pi Camera Module v2](https://www.raspberrypi.org/products/camera-module-v2/) 29 | * SDRAM controller improvements 30 | * much more! 31 | 32 | ## Special thanks 33 | 34 | * Gaurav Singh for his [excellent blog post discussing a MIPI CSI 4-lane configuration](https://www.circuitvalley.com/2020/02/imx219-camera-mipi-csi-receiver-fpga-lattice-raspberry-pi-camera.html) 35 | -------------------------------------------------------------------------------- /top/mkrvidor4000/mkrvidor4000_top.sv: -------------------------------------------------------------------------------- 1 | module mkrvidor4000_top 2 | ( 3 | // system signals 4 | input CLK_48MHZ, 5 | input RESETn, 6 | input SAM_INT_IN, 7 | output SAM_INT_OUT, 8 | 9 | // SDRAM 10 | output SDRAM_CLK, 11 | output [11:0] SDRAM_ADDR, 12 | output [1:0] SDRAM_BA, 13 | output SDRAM_CASn, 14 | output SDRAM_CKE, 15 | output SDRAM_CSn, 16 | inout [15:0] SDRAM_DQ, 17 | output [1:0] SDRAM_DQM, 18 | output SDRAM_RASn, 19 | output SDRAM_WEn, 20 | 21 | // SAM D21 PINS 22 | inout MKR_AREF, 23 | inout [6:0] MKR_A, 24 | inout [14:0] MKR_D, 25 | 26 | // HDMI output 27 | output [2:0] HDMI_TX, 28 | output HDMI_CLK, 29 | inout HDMI_SDA, 30 | inout HDMI_SCL, 31 | 32 | input HDMI_HPD, 33 | 34 | // MIPI input 35 | input [1:0] MIPI_D, 36 | input MIPI_CLK, 37 | inout MIPI_SDA, 38 | inout MIPI_SCL, 39 | inout [1:0] MIPI_GP 40 | 41 | ); 42 | 43 | // internal oscillator 44 | wire OSC_CLK; 45 | cyclone10lp_oscillator osc ( 46 | .clkout(OSC_CLK), 47 | .oscena(1'b1) 48 | ); 49 | 50 | mem_pll mem_pll(.inclk0(CLK_48MHZ), .c0(SDRAM_CLK)); 51 | 52 | wire clk_pixel_x5; 53 | wire clk_pixel; 54 | wire clk_audio; 55 | hdmi_pll hdmi_pll(.inclk0(CLK_48MHZ), .c0(clk_pixel), .c1(clk_pixel_x5), .c2(clk_audio)); 56 | 57 | localparam AUDIO_BIT_WIDTH = 16; 58 | localparam AUDIO_RATE = 48000; 59 | localparam WAVE_RATE = 240; 60 | 61 | logic [AUDIO_BIT_WIDTH-1:0] audio_sample_word; 62 | sawtooth #(.BIT_WIDTH(AUDIO_BIT_WIDTH), .SAMPLE_RATE(AUDIO_RATE), .WAVE_RATE(WAVE_RATE)) sawtooth (.clk_audio(clk_audio), .level(audio_sample_word)); 63 | 64 | logic [23:0] rgb; 65 | logic [9:0] cx, cy, screen_width, screen_height; 66 | hdmi #(.VIDEO_ID_CODE(1), .AUDIO_RATE(AUDIO_RATE), .AUDIO_BIT_WIDTH(AUDIO_BIT_WIDTH)) hdmi( 67 | .clk_pixel_x5(clk_pixel_x5), 68 | .clk_pixel(clk_pixel), 69 | .clk_audio(clk_audio), 70 | .rgb(rgb), 71 | .audio_sample_word('{audio_sample_word >> 9, audio_sample_word >> 9}), 72 | .tmds(HDMI_TX), 73 | .tmds_clock(HDMI_CLK), 74 | .cx(cx), 75 | .cy(cy), 76 | .screen_width(screen_width), 77 | .screen_height(screen_height) 78 | ); 79 | 80 | logic [1:0] mode = 2'd0; 81 | logic [1:0] resolution = 2'd3; // 640x480 @ 30FPS 82 | logic format = 1'd0; // RAW8 83 | logic ready; 84 | logic model_err; 85 | logic nack_err; 86 | 87 | ov5647 #(.INPUT_CLK_RATE(48_000_000), .TARGET_SCL_RATE(100_000)) ov5647 ( 88 | .clk_in(CLK_48MHZ), 89 | .scl(MIPI_SCL), 90 | .sda(MIPI_SDA), 91 | .mode(mode), 92 | .resolution(resolution), 93 | .format(format), 94 | .ready(ready), 95 | .power_enable(MIPI_GP[0]), 96 | .model_err(model_err), 97 | .nack_err(nack_err) 98 | ); 99 | 100 | logic [7:0] image_data [3:0]; 101 | logic [5:0] image_data_type; 102 | logic image_data_enable; 103 | logic [15:0] word_count; 104 | logic frame_start, line_start, interrupt, frame_end; 105 | camera #(.NUM_LANES(2)) camera ( 106 | .clock_p(MIPI_CLK), 107 | .data_p(MIPI_D), 108 | .image_data(image_data), 109 | .image_data_type(image_data_type), 110 | .image_data_enable(image_data_enable), 111 | .word_count(word_count), 112 | .frame_start(frame_start), 113 | .frame_end(frame_end), 114 | .line_start(line_start), 115 | .interrupt(interrupt) 116 | ); 117 | 118 | // logic [7:0] raw [3:0]; 119 | // logic raw_enable; 120 | // raw8 raw8 (.image_data(image_data), .image_data_enable(image_data_enable), .raw(raw), .raw_enable(raw_enable)); 121 | 122 | logic [25:0] camera_counter = 26'd0; 123 | always @(posedge CLK_48MHZ) 124 | camera_counter <= camera_counter + 1'd1; 125 | 126 | always @(posedge CLK_48MHZ) 127 | if (ready && mode == 2'd0) 128 | mode <= 2'd1; 129 | else if (ready && mode == 2'd1 && camera_counter + 1'd1 == 26'd0) 130 | mode <= 2'd2; 131 | 132 | logic pixel_enable; 133 | assign pixel_enable = cx < screen_width && cy < screen_height; 134 | logic [7:0] pixel; 135 | 136 | arbiter arbiter ( 137 | .pixel_clk(clk_pixel), 138 | .pixel_enable(pixel_enable), 139 | .pixel(pixel), 140 | .mipi_clk(MIPI_CLK), 141 | .mipi_data_enable(image_data_enable), 142 | .mipi_data(image_data), 143 | .frame_start(frame_start), 144 | .line_start(line_start), 145 | .interrupt(interrupt), 146 | .sdram_clk(SDRAM_CLK), 147 | .clock_enable(SDRAM_CKE), 148 | .bank_activate(SDRAM_BA), 149 | .address(SDRAM_ADDR), 150 | .chip_select(SDRAM_CSn), 151 | .row_address_strobe(SDRAM_RASn), 152 | .column_address_strobe(SDRAM_CASn), 153 | .write_enable(SDRAM_WEn), 154 | .dqm(SDRAM_DQM), 155 | .dq(SDRAM_DQ) 156 | ); 157 | 158 | always @(posedge clk_pixel) 159 | rgb <= {pixel, pixel, pixel}; 160 | 161 | endmodule 162 | -------------------------------------------------------------------------------- /top/mkrvidor4000/arbiter.sv: -------------------------------------------------------------------------------- 1 | module arbiter #( 2 | parameter VIDEO_END = (640 * 480) / 2 // RAW8 --> 2 pixels per 16-bit memory address 3 | ) ( 4 | input logic pixel_clk, 5 | input logic pixel_enable, 6 | output logic [7:0] pixel, 7 | 8 | input logic mipi_clk, 9 | input logic mipi_data_enable, 10 | input logic [7:0] mipi_data [3:0], 11 | input logic frame_start, 12 | input logic line_start, 13 | input logic interrupt, 14 | 15 | input logic sdram_clk, 16 | output logic clock_enable, 17 | output logic [1:0] bank_activate, 18 | output logic [11:0] address, 19 | output logic chip_select, 20 | output logic row_address_strobe, 21 | output logic column_address_strobe, 22 | output logic write_enable, 23 | output logic [1:0] dqm, 24 | inout wire [15:0] dq 25 | ); 26 | 27 | logic [1:0] command = 2'd0; 28 | logic [21:0] data_address = 22'd0; 29 | logic [15:0] data_write = 16'd0; 30 | logic [15:0] data_read; 31 | logic data_read_valid; 32 | logic data_write_done; 33 | 34 | localparam READ_BURST_LENGTH = 8; 35 | 36 | as4c4m16sa_controller #( 37 | .CLK_RATE(140_000_000), 38 | .SPEED_GRADE(7), 39 | .READ_BURST_LENGTH(READ_BURST_LENGTH), 40 | .WRITE_BURST(1), 41 | .CAS_LATENCY(3) 42 | ) as4c4m16sa ( 43 | .clk(sdram_clk), 44 | .command(command), 45 | .data_address(data_address), 46 | .data_write(data_write), 47 | .data_read(data_read), 48 | .data_read_valid(data_read_valid), 49 | .data_write_done(data_write_done), 50 | .clock_enable(clock_enable), 51 | .bank_activate(bank_activate), 52 | .address(address), 53 | .chip_select(chip_select), 54 | .row_address_strobe(row_address_strobe), 55 | .column_address_strobe(column_address_strobe), 56 | .write_enable(write_enable), 57 | .dqm(dqm), 58 | .dq(dq) 59 | ); 60 | 61 | localparam MIPI_POINTER_WIDTH = 8; 62 | logic [MIPI_POINTER_WIDTH-1:0] mipi_data_out_used; 63 | logic mipi_data_out_acknowledge, mipi_data_in_enable; 64 | logic [15:0] mipi_data_in, mipi_data_out; 65 | 66 | fifo #(.DATA_WIDTH(16), .POINTER_WIDTH(MIPI_POINTER_WIDTH), .SENDER_DELAY_CHAIN_LENGTH(2)) mipi_write_fifo( 67 | .sender_clock(mipi_clk), 68 | .data_in_enable(mipi_data_in_enable), 69 | .data_in_used(), 70 | .data_in(mipi_data_in), 71 | .receiver_clock(sdram_clk), 72 | .data_out_used(mipi_data_out_used), 73 | .data_out_acknowledge(mipi_data_out_acknowledge), 74 | .data_out(mipi_data_out) 75 | ); 76 | 77 | logic mipi_data_in_countdown = 1'b0; 78 | assign mipi_data_in = mipi_data_in_countdown ? mipi_data_holding : {mipi_data[1], mipi_data[0]}; 79 | assign mipi_data_in_enable = mipi_data_enable || mipi_data_in_countdown; 80 | logic [15:0] mipi_data_holding = 16'd0; 81 | always_ff @(posedge mipi_clk) 82 | mipi_data_holding <= {mipi_data[3], mipi_data[2]}; 83 | always_ff @(posedge mipi_clk) 84 | if (interrupt && mipi_data_enable) 85 | mipi_data_in_countdown <= 1'b1; 86 | else 87 | mipi_data_in_countdown <= 1'b0; 88 | 89 | localparam PIXEL_POINTER_WIDTH = 8; 90 | logic [PIXEL_POINTER_WIDTH-1:0] pixel_data_in_used; 91 | logic [15:0] pixel_data_in, pixel_data_out; 92 | logic pixel_data_out_acknowledge, pixel_data_in_enable; 93 | fifo #(.DATA_WIDTH(16), .POINTER_WIDTH(PIXEL_POINTER_WIDTH), .RECEIVER_DELAY_CHAIN_LENGTH(1)) pixel_read_fifo( 94 | .sender_clock(sdram_clk), 95 | .data_in_enable(pixel_data_in_enable), 96 | .data_in_used(pixel_data_in_used), 97 | .data_in(pixel_data_in), 98 | .receiver_clock(pixel_clk), 99 | .data_out_used(), 100 | .data_out_acknowledge(pixel_data_out_acknowledge), 101 | .data_out(pixel_data_out) 102 | ); 103 | logic pixel_data_out_countdown = 1'b0; 104 | assign pixel = pixel_data_out_countdown ? pixel_data_out[15:8] : pixel_data_out[7:0]; 105 | assign pixel_data_out_acknowledge = pixel_data_out_countdown && pixel_enable; // Increment after both bytes are read 106 | always_ff @(posedge pixel_clk) 107 | pixel_data_out_countdown <= pixel_enable ? !pixel_data_out_countdown : pixel_data_out_countdown; 108 | 109 | 110 | logic [21:0] mipi_address = 22'd0; 111 | logic [21:0] pixel_address = 22'd0; 112 | logic [2:0] sdram_countup = 3'd0; 113 | 114 | assign mipi_data_out_acknowledge = (command == 2'd0 && mipi_data_out_used[3]) || (command == 2'd1 && data_write_done); 115 | assign pixel_data_in_enable = command == 2'd2 && data_read_valid; 116 | assign pixel_data_in = data_read; 117 | 118 | assign data_address = command == 2'd2 ? pixel_address : command == 2'd1 ? mipi_address : 22'dx; 119 | always_ff @(posedge sdram_clk) 120 | data_write <= mipi_data_out; 121 | 122 | always_ff @(posedge sdram_clk) 123 | begin 124 | // TODO: merge this into the fifo 125 | // all the data should've reached the SDRAM by the time it triggers, but just for clock domain crossing safety, it should be moved back 126 | if (interrupt && frame_start) 127 | mipi_address <= 22'd0; 128 | if (command == 2'd0) 129 | begin 130 | if (mipi_data_out_used[3]) // Write burst possible (prioritized over read burst) 131 | begin 132 | command <= 2'd1; 133 | sdram_countup <= 1'd1; 134 | end 135 | else if (!pixel_data_in_used[PIXEL_POINTER_WIDTH-1]) // Read burst possible 136 | begin 137 | command <= 2'd2; 138 | sdram_countup <= 3'd0; 139 | end 140 | else // Idle 141 | begin 142 | command <= 2'd0; 143 | sdram_countup <= 3'dx; 144 | end 145 | end 146 | else if (command == 2'd2) // Reading 147 | begin 148 | if (data_read_valid) 149 | begin 150 | sdram_countup <= sdram_countup + 1'd1; 151 | if (sdram_countup == 3'd7) // Last read 152 | begin 153 | command <= 2'd0; 154 | pixel_address <= pixel_address + 22'(READ_BURST_LENGTH) == 22'(VIDEO_END) ? 22'd0 : pixel_address + 22'(READ_BURST_LENGTH); 155 | end 156 | end 157 | end 158 | else if (command == 2'd1) // Writing 159 | begin 160 | if (data_write_done) 161 | begin 162 | sdram_countup <= sdram_countup + 1'd1; 163 | if (sdram_countup == 3'd7) // Last write 164 | begin 165 | command <= 2'd0; 166 | mipi_address <= mipi_address + 22'(READ_BURST_LENGTH) == 22'(VIDEO_END) ? 22'd0 : mipi_address + 22'(READ_BURST_LENGTH); 167 | end 168 | end 169 | end 170 | end 171 | 172 | endmodule 173 | -------------------------------------------------------------------------------- /pll/mem_pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: mem_pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 19.1.0 Build 670 09/22/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module mem_pll ( 41 | inclk0, 42 | c0); 43 | 44 | input inclk0; 45 | output c0; 46 | 47 | wire [4:0] sub_wire0; 48 | wire [0:0] sub_wire4 = 1'h0; 49 | wire [0:0] sub_wire1 = sub_wire0[0:0]; 50 | wire c0 = sub_wire1; 51 | wire sub_wire2 = inclk0; 52 | wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; 53 | 54 | altpll altpll_component ( 55 | .inclk (sub_wire3), 56 | .clk (sub_wire0), 57 | .activeclock (), 58 | .areset (1'b0), 59 | .clkbad (), 60 | .clkena ({6{1'b1}}), 61 | .clkloss (), 62 | .clkswitch (1'b0), 63 | .configupdate (1'b0), 64 | .enable0 (), 65 | .enable1 (), 66 | .extclk (), 67 | .extclkena ({4{1'b1}}), 68 | .fbin (1'b1), 69 | .fbmimicbidir (), 70 | .fbout (), 71 | .fref (), 72 | .icdrclk (), 73 | .locked (), 74 | .pfdena (1'b1), 75 | .phasecounterselect ({4{1'b1}}), 76 | .phasedone (), 77 | .phasestep (1'b1), 78 | .phaseupdown (1'b1), 79 | .pllena (1'b1), 80 | .scanaclr (1'b0), 81 | .scanclk (1'b0), 82 | .scanclkena (1'b1), 83 | .scandata (1'b0), 84 | .scandataout (), 85 | .scandone (), 86 | .scanread (1'b0), 87 | .scanwrite (1'b0), 88 | .sclkout0 (), 89 | .sclkout1 (), 90 | .vcooverrange (), 91 | .vcounderrange ()); 92 | defparam 93 | altpll_component.bandwidth_type = "AUTO", 94 | altpll_component.clk0_divide_by = 12, 95 | altpll_component.clk0_duty_cycle = 50, 96 | altpll_component.clk0_multiply_by = 35, 97 | altpll_component.clk0_phase_shift = "0", 98 | altpll_component.compensate_clock = "CLK0", 99 | altpll_component.inclk0_input_frequency = 20833, 100 | altpll_component.intended_device_family = "Cyclone 10 LP", 101 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=mem_pll", 102 | altpll_component.lpm_type = "altpll", 103 | altpll_component.operation_mode = "NORMAL", 104 | altpll_component.pll_type = "AUTO", 105 | altpll_component.port_activeclock = "PORT_UNUSED", 106 | altpll_component.port_areset = "PORT_UNUSED", 107 | altpll_component.port_clkbad0 = "PORT_UNUSED", 108 | altpll_component.port_clkbad1 = "PORT_UNUSED", 109 | altpll_component.port_clkloss = "PORT_UNUSED", 110 | altpll_component.port_clkswitch = "PORT_UNUSED", 111 | altpll_component.port_configupdate = "PORT_UNUSED", 112 | altpll_component.port_fbin = "PORT_UNUSED", 113 | altpll_component.port_inclk0 = "PORT_USED", 114 | altpll_component.port_inclk1 = "PORT_UNUSED", 115 | altpll_component.port_locked = "PORT_UNUSED", 116 | altpll_component.port_pfdena = "PORT_UNUSED", 117 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 118 | altpll_component.port_phasedone = "PORT_UNUSED", 119 | altpll_component.port_phasestep = "PORT_UNUSED", 120 | altpll_component.port_phaseupdown = "PORT_UNUSED", 121 | altpll_component.port_pllena = "PORT_UNUSED", 122 | altpll_component.port_scanaclr = "PORT_UNUSED", 123 | altpll_component.port_scanclk = "PORT_UNUSED", 124 | altpll_component.port_scanclkena = "PORT_UNUSED", 125 | altpll_component.port_scandata = "PORT_UNUSED", 126 | altpll_component.port_scandataout = "PORT_UNUSED", 127 | altpll_component.port_scandone = "PORT_UNUSED", 128 | altpll_component.port_scanread = "PORT_UNUSED", 129 | altpll_component.port_scanwrite = "PORT_UNUSED", 130 | altpll_component.port_clk0 = "PORT_USED", 131 | altpll_component.port_clk1 = "PORT_UNUSED", 132 | altpll_component.port_clk2 = "PORT_UNUSED", 133 | altpll_component.port_clk3 = "PORT_UNUSED", 134 | altpll_component.port_clk4 = "PORT_UNUSED", 135 | altpll_component.port_clk5 = "PORT_UNUSED", 136 | altpll_component.port_clkena0 = "PORT_UNUSED", 137 | altpll_component.port_clkena1 = "PORT_UNUSED", 138 | altpll_component.port_clkena2 = "PORT_UNUSED", 139 | altpll_component.port_clkena3 = "PORT_UNUSED", 140 | altpll_component.port_clkena4 = "PORT_UNUSED", 141 | altpll_component.port_clkena5 = "PORT_UNUSED", 142 | altpll_component.port_extclk0 = "PORT_UNUSED", 143 | altpll_component.port_extclk1 = "PORT_UNUSED", 144 | altpll_component.port_extclk2 = "PORT_UNUSED", 145 | altpll_component.port_extclk3 = "PORT_UNUSED", 146 | altpll_component.width_clock = 5; 147 | 148 | 149 | endmodule 150 | 151 | // ============================================================ 152 | // CNX file retrieval info 153 | // ============================================================ 154 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 156 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 157 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 158 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 159 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 160 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 161 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 162 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 163 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 164 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 165 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 166 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 168 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 169 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 170 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 171 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 172 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "140.000000" 173 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 174 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 175 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 176 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 177 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 179 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 180 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" 181 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 182 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 183 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 184 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 185 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 186 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" 187 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 188 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 189 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 190 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 191 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 192 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" 193 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 194 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 195 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 196 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 197 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "140.00000000" 198 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 199 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 200 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 201 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 203 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 205 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 208 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 209 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 210 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 212 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 214 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 215 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "mem_pll.mif" 216 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 218 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 219 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 220 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 221 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 222 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 223 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 224 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 225 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 226 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 227 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 228 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 229 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 230 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 231 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 232 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 233 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 234 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 235 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 236 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12" 237 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 238 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35" 239 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 240 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 241 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" 242 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" 243 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 244 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 245 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 246 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 247 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 248 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 255 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 260 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 262 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 269 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 271 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 272 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 286 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 288 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 289 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 290 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 291 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 292 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 293 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 294 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll.v TRUE 295 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll.ppf TRUE 296 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll.inc FALSE 297 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll.cmp FALSE 298 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll.bsf FALSE 299 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll_inst.v FALSE 300 | // Retrieval info: GEN_FILE: TYPE_NORMAL mem_pll_bb.v FALSE 301 | // Retrieval info: LIB_FILE: altera_mf 302 | // Retrieval info: CBX_MODULE_PREFIX: ON 303 | -------------------------------------------------------------------------------- /top/mkrvidor4000/pinout.tcl: -------------------------------------------------------------------------------- 1 | post_message "Assigning pinout" 2 | 3 | # Load Quartus II Tcl Project package 4 | package require ::quartus::project 5 | 6 | project_open -revision mipi-demo mipi-demo 7 | 8 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 9 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 10 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" 11 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 12 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 13 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" 14 | set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED 15 | set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON 16 | set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON 17 | # set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON 18 | # set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON 19 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON 20 | set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON 21 | set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON 22 | set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON 23 | set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON 24 | set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM 25 | 26 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 27 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 28 | set_global_assignment -name ENABLE_OCT_DONE OFF 29 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" 30 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 31 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 32 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 33 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 34 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 35 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 36 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 37 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 38 | set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF 39 | set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF 40 | set_global_assignment -name CONFIGURATION_VCCIO_LEVEL AUTO 41 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 100% 42 | set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON 43 | set_global_assignment -name IGNORE_PARTITIONS ON 44 | # set_global_assignment -name GENERATE_RBF_FILE ON 45 | # set_global_assignment -name GENERATE_TTF_FILE ON 46 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON 47 | set_global_assignment -name GENERATE_JAM_FILE ON 48 | set_global_assignment -name GENERATE_SVF_FILE ON 49 | # set_global_assignment -name GENERATE_JBC_FILE ON 50 | set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD 51 | set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 52 | 53 | set_global_assignment -name ENABLE_SIGNALTAP OFF 54 | 55 | 56 | # system signals 57 | set_location_assignment PIN_E2 -to CLK_48MHZ 58 | set_location_assignment PIN_E1 -to RESETn 59 | 60 | # SDRAM 61 | set_location_assignment PIN_E10 -to SDRAM_ADDR[11] 62 | set_location_assignment PIN_B13 -to SDRAM_ADDR[10] 63 | set_location_assignment PIN_C9 -to SDRAM_ADDR[9] 64 | set_location_assignment PIN_E11 -to SDRAM_ADDR[8] 65 | set_location_assignment PIN_D12 -to SDRAM_ADDR[7] 66 | set_location_assignment PIN_D11 -to SDRAM_ADDR[6] 67 | set_location_assignment PIN_C14 -to SDRAM_ADDR[5] 68 | set_location_assignment PIN_D14 -to SDRAM_ADDR[4] 69 | set_location_assignment PIN_A14 -to SDRAM_ADDR[3] 70 | set_location_assignment PIN_A15 -to SDRAM_ADDR[2] 71 | set_location_assignment PIN_B12 -to SDRAM_ADDR[1] 72 | set_location_assignment PIN_A12 -to SDRAM_ADDR[0] 73 | set_location_assignment PIN_B10 -to SDRAM_BA[1] 74 | set_location_assignment PIN_A10 -to SDRAM_BA[0] 75 | set_location_assignment PIN_B7 -to SDRAM_CASn 76 | set_location_assignment PIN_E9 -to SDRAM_CKE 77 | set_location_assignment PIN_A11 -to SDRAM_CSn 78 | set_location_assignment PIN_B6 -to SDRAM_DQ[15] 79 | set_location_assignment PIN_D6 -to SDRAM_DQ[14] 80 | set_location_assignment PIN_D8 -to SDRAM_DQ[13] 81 | set_location_assignment PIN_E6 -to SDRAM_DQ[12] 82 | set_location_assignment PIN_E8 -to SDRAM_DQ[11] 83 | set_location_assignment PIN_E7 -to SDRAM_DQ[10] 84 | set_location_assignment PIN_C8 -to SDRAM_DQ[9] 85 | set_location_assignment PIN_F8 -to SDRAM_DQ[8] 86 | set_location_assignment PIN_A6 -to SDRAM_DQ[7] 87 | set_location_assignment PIN_B5 -to SDRAM_DQ[6] 88 | set_location_assignment PIN_A5 -to SDRAM_DQ[5] 89 | set_location_assignment PIN_A4 -to SDRAM_DQ[4] 90 | set_location_assignment PIN_A3 -to SDRAM_DQ[3] 91 | set_location_assignment PIN_B3 -to SDRAM_DQ[2] 92 | set_location_assignment PIN_B4 -to SDRAM_DQ[1] 93 | set_location_assignment PIN_A2 -to SDRAM_DQ[0] 94 | set_location_assignment PIN_F9 -to SDRAM_DQM[1] 95 | set_location_assignment PIN_A7 -to SDRAM_DQM[0] 96 | set_location_assignment PIN_D9 -to SDRAM_RASn 97 | set_location_assignment PIN_B14 -to SDRAM_CLK 98 | set_location_assignment PIN_B11 -to SDRAM_WEn 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3] 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1] 114 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0] 115 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11] 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10] 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9] 118 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7] 120 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5] 122 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3] 124 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2] 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1] 126 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0] 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1] 128 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CASn 130 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE 131 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK 132 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CSn 133 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1] 134 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0] 135 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RASn 136 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WEn 137 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM* 138 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[11] 139 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[10] 140 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[9] 141 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[8] 142 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[7] 143 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[6] 144 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[5] 145 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[4] 146 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[3] 147 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[2] 148 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[1] 149 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR[0] 150 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] 151 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] 152 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM[1] 153 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM[0] 154 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RASn 155 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CASn 156 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WEn 157 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CSn 158 | # set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CKE 159 | 160 | # SAM D21 PINS 161 | set_location_assignment PIN_B1 -to MKR_AREF 162 | set_location_assignment PIN_C2 -to MKR_A[0] 163 | set_location_assignment PIN_C3 -to MKR_A[1] 164 | set_location_assignment PIN_C6 -to MKR_A[2] 165 | set_location_assignment PIN_D1 -to MKR_A[3] 166 | set_location_assignment PIN_D3 -to MKR_A[4] 167 | set_location_assignment PIN_F3 -to MKR_A[5] 168 | set_location_assignment PIN_G2 -to MKR_A[6] 169 | 170 | set_location_assignment PIN_G1 -to MKR_D[0] 171 | set_location_assignment PIN_N3 -to MKR_D[1] 172 | set_location_assignment PIN_P3 -to MKR_D[2] 173 | set_location_assignment PIN_R3 -to MKR_D[3] 174 | set_location_assignment PIN_T3 -to MKR_D[4] 175 | set_location_assignment PIN_T2 -to MKR_D[5] 176 | set_location_assignment PIN_G16 -to MKR_D[6] 177 | set_location_assignment PIN_G15 -to MKR_D[7] 178 | set_location_assignment PIN_F16 -to MKR_D[8] 179 | set_location_assignment PIN_F15 -to MKR_D[9] 180 | set_location_assignment PIN_C16 -to MKR_D[10] 181 | set_location_assignment PIN_C15 -to MKR_D[11] 182 | set_location_assignment PIN_B16 -to MKR_D[12] 183 | set_location_assignment PIN_C11 -to MKR_D[13] 184 | set_location_assignment PIN_A13 -to MKR_D[14] 185 | 186 | # Mini PCIe 187 | set_location_assignment PIN_P8 -to PEX_PIN6 188 | set_location_assignment PIN_L7 -to PEX_PIN8 189 | set_location_assignment PIN_N8 -to PEX_PIN10 190 | set_location_assignment PIN_T8 -to PEX_PIN11 191 | set_location_assignment PIN_M8 -to PEX_PIN12 192 | set_location_assignment PIN_R8 -to PEX_PIN13 193 | set_location_assignment PIN_L8 -to PEX_PIN14 194 | set_location_assignment PIN_M10 -to PEX_PIN16 195 | set_location_assignment PIN_N12 -to PEX_PIN20 196 | set_location_assignment PIN_T9 -to PEX_PIN23 197 | set_location_assignment PIN_R9 -to PEX_PIN25 198 | set_location_assignment PIN_T13 -to PEX_PIN28 199 | set_location_assignment PIN_R12 -to PEX_PIN30 200 | set_location_assignment PIN_A9 -to PEX_PIN31 201 | set_location_assignment PIN_F13 -to PEX_PIN32 202 | set_location_assignment PIN_B9 -to PEX_PIN33 203 | set_location_assignment PIN_R13 -to PEX_PIN42 204 | set_location_assignment PIN_P14 -to PEX_PIN44 205 | set_location_assignment PIN_T15 -to PEX_PIN45 206 | set_location_assignment PIN_R14 -to PEX_PIN46 207 | set_location_assignment PIN_T14 -to PEX_PIN47 208 | set_location_assignment PIN_F14 -to PEX_PIN48 209 | set_location_assignment PIN_D16 -to PEX_PIN49 210 | set_location_assignment PIN_D15 -to PEX_PIN51 211 | set_location_assignment PIN_T12 -to PEX_RST 212 | 213 | # NINA interface 214 | set_location_assignment PIN_J13 -to WM_PIO32 215 | set_location_assignment PIN_T11 -to WM_PIO1 216 | set_location_assignment PIN_R10 -to WM_PIO2 217 | set_location_assignment PIN_P11 -to WM_PIO3 218 | set_location_assignment PIN_R11 -to WM_PIO4 219 | set_location_assignment PIN_N6 -to WM_PIO5 220 | set_location_assignment PIN_P6 -to WM_PIO7 221 | set_location_assignment PIN_N5 -to WM_PIO8 222 | # Blue LED: RMII_RXD0/DAC_16 223 | # set_location_assignment PIN_T4 -to WM_PIO16 224 | # Green LED: RMII_RXD1/DAC_17 225 | # set_location_assignment PIN_R4 -to WM_PIO17 226 | set_location_assignment PIN_T5 -to WM_PIO18 227 | set_location_assignment PIN_R6 -to WM_PIO21 228 | set_location_assignment PIN_R5 -to WM_PIO20 229 | # RMII_MDIO 230 | # set_location_assignment PIN_T7 -to WM_PIO24 231 | # RMII_MDCLK 232 | # set_location_assignment PIN_R7 -to WM_PIO25 233 | set_location_assignment PIN_N9 -to WM_PIO27 234 | set_location_assignment PIN_N11 -to WM_PIO28 235 | set_location_assignment PIN_T10 -to WM_PIO29 236 | set_location_assignment PIN_T4 -to WM_PIO31 237 | set_location_assignment PIN_M6 -to WM_PIO34 238 | set_location_assignment PIN_R4 -to WM_PIO35 239 | set_instance_assignment -name IO_STANDARD "2.5 V" -to WM_PIO36 240 | set_location_assignment PIN_N1 -to WM_PIO36 241 | set_location_assignment PIN_E15 -to WM_TX 242 | set_location_assignment PIN_T6 -to WM_RX 243 | # Aliases for WM_PIO20 WM_PIO21 respectively 244 | # set_location_assignment PIN_R5 -to WM_RTS 245 | # set_location_assignment PIN_R6 -to WM_CTS 246 | set_instance_assignment -name IO_STANDARD "2.5 V" -to WM_RESET 247 | set_location_assignment PIN_R1 -to WM_RESET 248 | 249 | # HDMI output 250 | set_instance_assignment -name IO_STANDARD LVDS -to HDMI_TX* 251 | set_instance_assignment -name IO_STANDARD LVDS -to HDMI_CLK* 252 | set_location_assignment PIN_R16 -to HDMI_TX[2] 253 | set_location_assignment PIN_K15 -to HDMI_TX[1] 254 | set_location_assignment PIN_J15 -to HDMI_TX[0] 255 | set_location_assignment PIN_N15 -to HDMI_CLK 256 | set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_SCL 257 | set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_SDA 258 | set_location_assignment PIN_K5 -to HDMI_SCL 259 | set_location_assignment PIN_L4 -to HDMI_SDA 260 | set_location_assignment PIN_M16 -to HDMI_HPD 261 | 262 | # MIPI input 263 | set_instance_assignment -name FAST_INPUT_REGISTER ON -to MIPI_D* 264 | set_instance_assignment -name IO_STANDARD LVDS -to MIPI_D* 265 | set_instance_assignment -name IO_STANDARD LVDS -to MIPI_CLK* 266 | set_location_assignment PIN_J2 -to MIPI_D[1] 267 | set_location_assignment PIN_L2 -to MIPI_D[0] 268 | # set_location_assignment PIN_J1 -to MIPI_D_N[1] 269 | # set_location_assignment PIN_L1 -to MIPI_D_N[0] 270 | set_location_assignment PIN_M2 -to MIPI_CLK 271 | # set_location_assignment PIN_M1 -to MIPI_CLK_N 272 | set_instance_assignment -name IO_STANDARD "2.5 V" -to MIPI_SCL 273 | set_instance_assignment -name IO_STANDARD "2.5 V" -to MIPI_SDA 274 | set_location_assignment PIN_P1 -to MIPI_SCL 275 | set_location_assignment PIN_P2 -to MIPI_SDA 276 | set_location_assignment PIN_M7 -to MIPI_GP[0] 277 | set_location_assignment PIN_P9 -to MIPI_GP[1] 278 | 279 | # misc pins 280 | # TODO: the FPGA makers assigned HDMI SDA the name "panel_en" no idea why. Maybe open an issue about it? 281 | # set_instance_assignment -name IO_STANDARD "2.5 V" -to panel_en 282 | # set_location_assignment PIN_L4 -to panel_en 283 | 284 | # Flash interface 285 | set_location_assignment PIN_C1 -to FLASH_MOSI 286 | set_location_assignment PIN_H2 -to FLASH_MISO 287 | set_location_assignment PIN_H1 -to FLASH_SCK 288 | set_location_assignment PIN_D2 -to FLASH_CS 289 | set_location_assignment PIN_R7 -to FLASH_HOLD 290 | set_location_assignment PIN_T7 -to FLASH_WP 291 | 292 | # interrupt pins 293 | set_location_assignment PIN_N2 -to SAM_INT_OUT 294 | set_location_assignment PIN_L16 -to SAM_INT_IN 295 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SAM_INT_OUT 296 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SAM_INT_IN 297 | 298 | # dual purpose pins 299 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" 300 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" 301 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" 302 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" 303 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 304 | 305 | # Commit assignments 306 | export_assignments 307 | project_close 308 | -------------------------------------------------------------------------------- /pll/hdmi_pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: hdmi_pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 19.1.0 Build 670 09/22/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module hdmi_pll ( 41 | inclk0, 42 | c0, 43 | c1, 44 | c2); 45 | 46 | input inclk0; 47 | output c0; 48 | output c1; 49 | output c2; 50 | 51 | wire [4:0] sub_wire0; 52 | wire [0:0] sub_wire6 = 1'h0; 53 | wire [2:2] sub_wire3 = sub_wire0[2:2]; 54 | wire [1:1] sub_wire2 = sub_wire0[1:1]; 55 | wire [0:0] sub_wire1 = sub_wire0[0:0]; 56 | wire c0 = sub_wire1; 57 | wire c1 = sub_wire2; 58 | wire c2 = sub_wire3; 59 | wire sub_wire4 = inclk0; 60 | wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; 61 | 62 | altpll altpll_component ( 63 | .inclk (sub_wire5), 64 | .clk (sub_wire0), 65 | .activeclock (), 66 | .areset (1'b0), 67 | .clkbad (), 68 | .clkena ({6{1'b1}}), 69 | .clkloss (), 70 | .clkswitch (1'b0), 71 | .configupdate (1'b0), 72 | .enable0 (), 73 | .enable1 (), 74 | .extclk (), 75 | .extclkena ({4{1'b1}}), 76 | .fbin (1'b1), 77 | .fbmimicbidir (), 78 | .fbout (), 79 | .fref (), 80 | .icdrclk (), 81 | .locked (), 82 | .pfdena (1'b1), 83 | .phasecounterselect ({4{1'b1}}), 84 | .phasedone (), 85 | .phasestep (1'b1), 86 | .phaseupdown (1'b1), 87 | .pllena (1'b1), 88 | .scanaclr (1'b0), 89 | .scanclk (1'b0), 90 | .scanclkena (1'b1), 91 | .scandata (1'b0), 92 | .scandataout (), 93 | .scandone (), 94 | .scanread (1'b0), 95 | .scanwrite (1'b0), 96 | .sclkout0 (), 97 | .sclkout1 (), 98 | .vcooverrange (), 99 | .vcounderrange ()); 100 | defparam 101 | altpll_component.bandwidth_type = "AUTO", 102 | altpll_component.clk0_divide_by = 40, 103 | altpll_component.clk0_duty_cycle = 50, 104 | altpll_component.clk0_multiply_by = 21, 105 | altpll_component.clk0_phase_shift = "0", 106 | altpll_component.clk1_divide_by = 8, 107 | altpll_component.clk1_duty_cycle = 50, 108 | altpll_component.clk1_multiply_by = 21, 109 | altpll_component.clk1_phase_shift = "0", 110 | altpll_component.clk2_divide_by = 1000, 111 | altpll_component.clk2_duty_cycle = 50, 112 | altpll_component.clk2_multiply_by = 1, 113 | altpll_component.clk2_phase_shift = "0", 114 | altpll_component.compensate_clock = "CLK0", 115 | altpll_component.inclk0_input_frequency = 20833, 116 | altpll_component.intended_device_family = "Cyclone 10 LP", 117 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=hdmi_pll", 118 | altpll_component.lpm_type = "altpll", 119 | altpll_component.operation_mode = "NORMAL", 120 | altpll_component.pll_type = "AUTO", 121 | altpll_component.port_activeclock = "PORT_UNUSED", 122 | altpll_component.port_areset = "PORT_UNUSED", 123 | altpll_component.port_clkbad0 = "PORT_UNUSED", 124 | altpll_component.port_clkbad1 = "PORT_UNUSED", 125 | altpll_component.port_clkloss = "PORT_UNUSED", 126 | altpll_component.port_clkswitch = "PORT_UNUSED", 127 | altpll_component.port_configupdate = "PORT_UNUSED", 128 | altpll_component.port_fbin = "PORT_UNUSED", 129 | altpll_component.port_inclk0 = "PORT_USED", 130 | altpll_component.port_inclk1 = "PORT_UNUSED", 131 | altpll_component.port_locked = "PORT_UNUSED", 132 | altpll_component.port_pfdena = "PORT_UNUSED", 133 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 134 | altpll_component.port_phasedone = "PORT_UNUSED", 135 | altpll_component.port_phasestep = "PORT_UNUSED", 136 | altpll_component.port_phaseupdown = "PORT_UNUSED", 137 | altpll_component.port_pllena = "PORT_UNUSED", 138 | altpll_component.port_scanaclr = "PORT_UNUSED", 139 | altpll_component.port_scanclk = "PORT_UNUSED", 140 | altpll_component.port_scanclkena = "PORT_UNUSED", 141 | altpll_component.port_scandata = "PORT_UNUSED", 142 | altpll_component.port_scandataout = "PORT_UNUSED", 143 | altpll_component.port_scandone = "PORT_UNUSED", 144 | altpll_component.port_scanread = "PORT_UNUSED", 145 | altpll_component.port_scanwrite = "PORT_UNUSED", 146 | altpll_component.port_clk0 = "PORT_USED", 147 | altpll_component.port_clk1 = "PORT_USED", 148 | altpll_component.port_clk2 = "PORT_USED", 149 | altpll_component.port_clk3 = "PORT_UNUSED", 150 | altpll_component.port_clk4 = "PORT_UNUSED", 151 | altpll_component.port_clk5 = "PORT_UNUSED", 152 | altpll_component.port_clkena0 = "PORT_UNUSED", 153 | altpll_component.port_clkena1 = "PORT_UNUSED", 154 | altpll_component.port_clkena2 = "PORT_UNUSED", 155 | altpll_component.port_clkena3 = "PORT_UNUSED", 156 | altpll_component.port_clkena4 = "PORT_UNUSED", 157 | altpll_component.port_clkena5 = "PORT_UNUSED", 158 | altpll_component.port_extclk0 = "PORT_UNUSED", 159 | altpll_component.port_extclk1 = "PORT_UNUSED", 160 | altpll_component.port_extclk2 = "PORT_UNUSED", 161 | altpll_component.port_extclk3 = "PORT_UNUSED", 162 | altpll_component.width_clock = 5; 163 | 164 | 165 | endmodule 166 | 167 | // ============================================================ 168 | // CNX file retrieval info 169 | // ============================================================ 170 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 171 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 172 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 173 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 174 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 175 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 176 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 177 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 179 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 180 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 181 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 182 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 183 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 184 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 185 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 186 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 187 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" 188 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 189 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 190 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 191 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 192 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.200001" 193 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "126.000000" 194 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.048000" 195 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 196 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 197 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 198 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 199 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 200 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 201 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 202 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" 203 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 204 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 205 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 206 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 207 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 208 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" 209 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 210 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 212 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 213 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 214 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" 215 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" 216 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" 217 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 218 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 219 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 220 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 221 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 222 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" 223 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 224 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 225 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000" 226 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "126.00000000" 227 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.04800000" 228 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 229 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 230 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 231 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 232 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 233 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 234 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 235 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 236 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 237 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" 238 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" 239 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 240 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" 241 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" 242 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" 243 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 244 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 245 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 246 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 247 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 248 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 249 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 250 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 251 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 252 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 253 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "hdmi_pll.mif" 254 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 255 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 256 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 257 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 258 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 259 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 260 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 261 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 262 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 263 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 264 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 265 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 266 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 267 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 268 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 269 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 270 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 271 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 272 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 273 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 274 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 275 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 276 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 277 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 278 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 279 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 280 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "40" 281 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 282 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "21" 283 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 284 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "8" 285 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 286 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "21" 287 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" 288 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1000" 289 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 290 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" 291 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" 292 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 293 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" 294 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP" 295 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 296 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 297 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 298 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 299 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 300 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 301 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 302 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 303 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 304 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 305 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 306 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 307 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 308 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 309 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 310 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 311 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 312 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 313 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 314 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 315 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 316 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 317 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 318 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 319 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 320 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 321 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 322 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 323 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 324 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 325 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 326 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 327 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 328 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 329 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 330 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 331 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 332 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 333 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 334 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 335 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 336 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 337 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 338 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 339 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 340 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 341 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 342 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 343 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 344 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 345 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 346 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 347 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 348 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 349 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 350 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.v TRUE 351 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.ppf TRUE 352 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.inc FALSE 353 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.cmp FALSE 354 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll.bsf FALSE 355 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll_inst.v FALSE 356 | // Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_pll_bb.v FALSE 357 | // Retrieval info: LIB_FILE: altera_mf 358 | // Retrieval info: CBX_MODULE_PREFIX: ON 359 | --------------------------------------------------------------------------------