├── requirements.txt ├── board ├── DE4 │ ├── info.yml │ ├── GPIO.LED.sdc │ ├── FanControl.sdc │ ├── GPIO.Seg7.sdc │ ├── Clock.SystemClock.sdc │ ├── UART.sdc │ ├── Bus.IIC.EEPROM.sdc │ ├── GPIO.Button.sdc │ ├── GPIO.DipSwitch.sdc │ ├── GPIO.SlideSwitch.sdc │ ├── GPIO.Button.Special.sdc │ └── Bus.SMBus.sdc ├── ML505 │ ├── info.yml │ ├── Transceiver.SMA_RefClock.ucf │ ├── Clock.SMA.ucf │ ├── GPIO.Button.Special.ucf │ ├── Clock.UserClock.ucf │ ├── Bus.PS2.Mouse.ucf │ ├── Bus.PS2.Keyboard.ucf │ ├── GPIO.LED.Error.ucf │ ├── Transceiver.SMA.ucf │ ├── Bus.IIC.Monitor.ucf │ ├── Clock.SystemClock.ucf │ ├── GPIO.Rotary.ucf │ ├── GPIO.LED.Cursor.ucf │ ├── UART.ucf │ ├── Default.ucf │ ├── Bus.IIC.Main.ucf │ ├── EthernetPHY.SGMII.ucf │ ├── GPIO.Button.Cursor.ucf │ ├── Transceiver.SFP.ucf │ ├── GPIO.LED.ucf │ ├── GPIO.Switch.ucf │ ├── Bus.LCDisplay.ucf │ └── Monitor.DVI.Output.ucf ├── ML605 │ ├── info.yml │ ├── Default.ucf │ ├── Bus.PMBus.ucf │ ├── Transceiver.SMA_RefClock.ucf │ ├── GPIO.Button.Special.ucf │ └── Clock.UserClock.ucf ├── ECP5-EVN │ ├── info.yml │ └── constraints.lpf ├── Nexys4 │ └── info.yml ├── Nexys4DDR │ └── info.yml ├── S3SK │ ├── info.yml │ ├── uart.ucf │ ├── vga.ucf │ ├── buttons.ucf │ ├── default.ucf │ ├── switches.ucf │ └── leds.ucf ├── DSP_ICE │ └── info.yml ├── Pergola │ └── info.yml ├── Fomu-PVT │ ├── Clock.SystemClock.pcf │ ├── USB.pcf │ ├── GPIO.TriLED.pcf │ ├── GPIO.Buttons.pcf │ ├── info.yml │ ├── Bus.SPI.pcf │ └── constraints.pcf ├── IceStick │ ├── Clock.SystemClock.pcf │ ├── Transceiver.IrDA.pcf │ ├── info.yml │ ├── FTDI.Port0.pcf │ ├── FTDI.Port1.pcf │ ├── GPIO.LED.pcf │ ├── GPIO.Top.pcf │ ├── GPIO.Bottom.pcf │ └── PMOD.pcf ├── UPDuino-v3.0 │ ├── UART.pcf │ ├── TWI.pcf │ ├── GPIO.TriLED.pcf │ ├── SPI.user.pcf │ ├── GPIO.input.pcf │ ├── GPIO.output.pcf │ ├── SPI.onboard.pcf │ ├── info.yml │ └── constraints.pcf ├── Qomu │ └── info.yml ├── manila-iCE │ └── info.yml ├── Glasgow-revC │ └── info.yml ├── HX4K-PMOD │ └── info.yml ├── Mercury2-A7-100T │ └── info.yml ├── Mercury2-A7-35T │ └── info.yml ├── Pygmy │ └── info.yml ├── TinyFPGA-BX │ ├── Clock.SystemClock.pcf │ ├── GPIO.LED.pcf │ ├── USB.pcf │ ├── info.yml │ ├── Bus.SPI.pcf │ ├── GPIO.Bottom.pcf │ ├── GPIO.Right.pcf │ └── GPIO.Left.pcf ├── iCEBreaker │ ├── GPIO.Button.pcf │ ├── UART.pcf │ ├── TWI.pcf │ ├── GPIO.TriLED.pcf │ ├── SPI.user.pcf │ ├── GPIO.input.pcf │ ├── GPIO.output.pcf │ ├── SPI.onboard.pcf │ ├── info.yml │ └── constraints.pcf ├── PicoEVB │ └── info.yml ├── IceZumAlhambraII │ ├── Clock.SystemClock.pcf │ ├── GPIO.Buttons.pcf │ ├── Bus.I2C.ADC.pcf │ ├── info.yml │ ├── FTDI.Port0.pcf │ ├── FTDI.Port1.pcf │ ├── GPIO.LED.pcf │ ├── GPIO.Bottom.pcf │ └── GPIO.Top.pcf ├── iCE40CW312 │ ├── UART.pcf │ ├── GPIO.output.pcf │ ├── GPIO.input.pcf │ ├── info.yml │ ├── SPI.user.pcf │ └── constraints.pcf ├── BeagleWire │ └── info.yml ├── ICECREAM-1.0 │ └── info.yml ├── ICECREAM-1.2 │ └── info.yml ├── Litefury │ └── info.yml ├── QuickFeather │ └── info.yml ├── MNT-RKX7 │ └── info.yml ├── ECPIX-5-45F │ └── info.yml ├── ECPIX-5-85F │ └── info.yml ├── icoBOARD-v1.0 │ └── info.yml ├── ArcticKoala │ └── info.yml ├── Xilinx │ ├── Disable_DRC_Rules_GTHE3_Common.xdc │ ├── Disable_DRC_Rules_GTPE2_Channel.xdc │ └── Disable_DRC_Rules_GTXE2_Channel.xdc ├── doppler │ └── info.yml ├── Colorlight-i5-v7.0 │ └── info.yml ├── Colorlight-i9-v7.2 │ └── info.yml ├── ULX3S-12F │ └── info.yml ├── ULX3S-25F │ └── info.yml ├── ULX3S-45F │ └── info.yml ├── ULX3S-85F │ └── info.yml ├── CAT-Board │ └── info.yml ├── IceZero │ └── info.yml ├── KC705 │ ├── info.yml │ ├── Bus.PMBus.ucf │ ├── GPIO.SMA.ucf │ ├── Transceiver.SMA_RefClock.ucf │ ├── GPIO.SMA.xdc │ ├── GPIO.Button.Special.ucf │ ├── USB_UART.ucf │ ├── Transceiver.SMA.ucf │ ├── FMC-HPC │ │ └── FasterTechnology │ │ │ └── S14 │ │ │ ├── FMC-HPC.GPIO.LED.xdc │ │ │ ├── FMC-HPC.Clock.RefClock0.xdc │ │ │ ├── FMC-HPC.Clock.RefClock1.xdc │ │ │ ├── FMC-HPC.GPIO.Switch.xdc │ │ │ ├── FMC-HPC.SFP_Channel0.xdc │ │ │ ├── FMC-HPC.SFP_Channel1.xdc │ │ │ ├── FMC-HPC.SFP_Channel2.xdc │ │ │ └── FMC-HPC.SFP_Channel3.xdc │ ├── GPIO.Button.Special.xdc │ ├── Default.ucf │ ├── FanControl.ucf │ ├── EthernetPHY.ucf │ ├── GPIO.Rotary.ucf │ ├── Transceiver.SFP.ucf │ ├── FanControl.xdc │ ├── USB_UART.xdc │ ├── GPIO.Rotary.xdc │ ├── GPIO.Switch.ucf │ ├── GPIO.Switch.xdc │ ├── Bus.LCDisplay.ucf │ ├── FMC-LPC │ │ └── FasterTechnology │ │ │ └── S14 │ │ │ └── FMC-LPC.SFP_Channel3.xdc │ └── EthernetPHY.SGMII.ucf ├── VC707 │ ├── info.yml │ ├── Transceiver.SMA_RefClock.ucf │ ├── Bus.PMBus.ucf │ ├── USB_UART.ucf │ ├── Transceiver.SMA.ucf │ ├── Clock.ProgUserClock.ucf │ ├── FanControl.ucf │ ├── Clock.ProgUserClock.xdc │ ├── GPIO.SMA.ucf │ ├── GPIO.SMA.xdc │ ├── FanControl.xdc │ ├── GPIO.Button.Special.ucf │ ├── Default.ucf │ ├── GPIO.LED.ucf │ ├── USB_UART.xdc │ ├── GPIO.Button.Special.xdc │ ├── Clock.SystemClock.ucf │ ├── GPIO.LED.xdc │ ├── EthernetPHY.SGMII.ucf │ ├── Clock.SystemClock.xdc │ ├── Transceiver.SFP.ucf │ ├── GPIO.Rotary.ucf │ ├── EthernetPHY.ucf │ ├── GPIO.Rotary.xdc │ ├── GPIO.Button.Cursor.ucf │ └── Bus.LCDisplay.ucf ├── ZC706 │ ├── info.yml │ ├── Clock.SMAClock.xdc │ ├── Transceiver.SMA_RefClock.xdc │ ├── Transceiver.SMA_RefClock.ucf │ ├── Clock.ProgUserClock.ucf │ ├── Clock.ProgUserClock.xdc │ ├── Clock.SMAClock.ucf │ ├── Clock.SystemClock.ucf │ ├── Clock.SystemClock.xdc │ ├── GPIO.Button.Special.ucf │ ├── Transceiver.SFP.ucf │ ├── GPIO.Button.Special.xdc │ ├── Default.ucf │ ├── FanControl.ucf │ ├── GPIO.LED.ucf │ ├── FanControl.xdc │ ├── GPIO.Button.Cursor.ucf │ ├── Transceiver.SFP.xdc │ ├── PMOD.Port1.ucf │ ├── PMOD.Port1.xdc │ └── GPIO.LED.xdc ├── ML506 │ ├── info.md │ └── Default.ucf ├── TinyFPGA-B2 │ └── info.yml ├── iceFUN │ └── info.yml ├── iCESugar-pro │ └── info.yml ├── BusPirateUltra │ └── info.yml ├── DIPSY-EPT │ └── info.yml ├── iCEblink40-HX1K │ └── info.yml ├── Kefir │ └── info.yml ├── iCESugar-v1.5 │ └── info.yml ├── openFPGA │ └── info.yml ├── IceZumAlhambra │ └── info.yml ├── UPDuino-v1.0 │ └── info.yml ├── UPDuino-v2.0 │ └── info.yml ├── iCESugar-nano │ └── info.yml ├── BlackIce-MX │ └── info.yml ├── iCE40-feather-r0.2 │ └── info.yml ├── Atlys │ ├── info.yml │ ├── Bus.IIC.ucf │ ├── USB_UART.ucf │ ├── GPIO.Button.Special.ucf │ ├── Default.ucf │ ├── Clock.SystemClock.ucf │ ├── EthernetPHY.ucf │ ├── HDMI.RX.ucf │ ├── HDMI.TX.ucf │ └── GPIO.Switch.ucf ├── UPDuino-v2.1 │ └── info.yml ├── BlackIce-II │ └── info.yml ├── Nandland-Go │ └── info.yml ├── iCE40HX1K-EVB │ └── info.yml ├── iCE40HX8K-EVB │ └── info.yml ├── Alchitry-Cu │ └── info.yml ├── EDU-CIAA-FPGA │ └── info.yml ├── Arty-S7-25 │ └── info.yml ├── Arty-S7-50 │ ├── info.yml │ ├── USB_UART.xdc │ ├── GPIO.Button.Special.xdc │ ├── Bus.SPI.xdc │ ├── GPIO.LED.xdc │ └── GPIO.LED.RGB.xdc ├── Arty-A7-35T │ ├── info.yml │ ├── USB_UART.xdc │ ├── GPIO.Button.Special.xdc │ ├── Bus.SPI.xdc │ └── GPIO.LED.xdc ├── FPGA101 │ └── info.yml ├── ZedBoard │ ├── info.yml │ ├── Default.ucf │ ├── Clock.SystemClock.ucf │ ├── GPIO.LED.ucf │ ├── PMOD.PortA.ucf │ ├── PMOD.PortB.ucf │ ├── PMOD.PortC.ucf │ ├── PMOD.PortD.ucf │ ├── GPIO.Switch.ucf │ └── GPIO.Button.Cursor.ucf ├── Arty-A7-100T │ └── info.yml ├── iCE40-HX8K │ └── info.yml ├── iCEBreaker-bitsy-v0 │ └── info.yml ├── iCEBreaker-bitsy-v1 │ └── info.yml ├── iCE40-UP │ └── info.yml ├── OrangeCrab-r0.2 │ └── info.yml ├── XUPV5 │ ├── info.md │ └── Default.ucf ├── BlackIce │ └── info.yml ├── ButterStick-r1.0 │ └── info.yml └── AC701 │ ├── info.md │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.xdc │ ├── FanControl.xdc │ └── USB_UART.xdc ├── pyproject.toml ├── doc ├── _static │ ├── icon.png │ ├── usage.png │ ├── banner.png │ └── work-in-progress.png ├── Data │ ├── Boards │ │ └── index.rst │ ├── Devices.rst │ ├── SDRAM.rst │ └── Flash.rst ├── requirements.txt ├── References.rst ├── Makefile ├── Contributing.rst └── Attributes.rst ├── device └── ICE40-UP5K │ └── info.yml ├── .gitignore ├── .btd.yml ├── .github └── workflows │ └── doc.yml └── README.md /requirements.txt: -------------------------------------------------------------------------------- 1 | pyyaml 2 | -------------------------------------------------------------------------------- /board/DE4/info.yml: -------------------------------------------------------------------------------- 1 | Label: DE4 2 | -------------------------------------------------------------------------------- /board/ML505/info.yml: -------------------------------------------------------------------------------- 1 | Label: ML505 2 | -------------------------------------------------------------------------------- /board/ML605/info.yml: -------------------------------------------------------------------------------- 1 | Label: ML605 2 | -------------------------------------------------------------------------------- /board/ECP5-EVN/info.yml: -------------------------------------------------------------------------------- 1 | Label: ECP5-EVN 2 | -------------------------------------------------------------------------------- /board/Nexys4/info.yml: -------------------------------------------------------------------------------- 1 | Label: Nexys 4 2 | -------------------------------------------------------------------------------- /board/Nexys4DDR/info.yml: -------------------------------------------------------------------------------- 1 | Label: Nexys 4 DDR 2 | -------------------------------------------------------------------------------- /board/S3SK/info.yml: -------------------------------------------------------------------------------- 1 | Label: Spartan-3 Starter Kit 2 | -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [tool.black] 2 | line-length = 120 3 | -------------------------------------------------------------------------------- /doc/_static/icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hdl/constraints/HEAD/doc/_static/icon.png -------------------------------------------------------------------------------- /doc/_static/usage.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hdl/constraints/HEAD/doc/_static/usage.png -------------------------------------------------------------------------------- /doc/_static/banner.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hdl/constraints/HEAD/doc/_static/banner.png -------------------------------------------------------------------------------- /device/ICE40-UP5K/info.yml: -------------------------------------------------------------------------------- 1 | label: ICE40 UP5K 2 | device: ICE40-UP5K 3 | packages: 4 | - UWG30 5 | -------------------------------------------------------------------------------- /doc/Data/Boards/index.rst: -------------------------------------------------------------------------------- 1 | .. _Data:Boards: 2 | 3 | Boards 4 | ###### 5 | 6 | .. include:: boards.inc 7 | -------------------------------------------------------------------------------- /doc/requirements.txt: -------------------------------------------------------------------------------- 1 | -r ../requirements.txt 2 | -r ../openFPGALoader/doc/requirements.txt 3 | 4 | sphinx 5 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__ 2 | 3 | /doc/_build/ 4 | /doc/_theme/ 5 | /doc/Data/Boards/*.inc 6 | 7 | /openFPGALoader/ 8 | -------------------------------------------------------------------------------- /doc/_static/work-in-progress.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hdl/constraints/HEAD/doc/_static/work-in-progress.png -------------------------------------------------------------------------------- /board/DSP_ICE/info.yml: -------------------------------------------------------------------------------- 1 | Label: DSP_ICE 2 | Device: ICE40-HX8K 3 | Documentation: https://github.com/tvelliott/dsp_ice 4 | -------------------------------------------------------------------------------- /board/Pergola/info.yml: -------------------------------------------------------------------------------- 1 | Label: Pergola 2 | Device: ECP5-12F 3 | Documentation: https://github.com/pergola-fpga/pergola 4 | -------------------------------------------------------------------------------- /board/S3SK/uart.ucf: -------------------------------------------------------------------------------- 1 | NET "rx" LOC = "T13" | IOSTANDARD = LVCMOS33 ; 2 | NET "tx" LOC = "R13" | IOSTANDARD = LVCMOS33 ; 3 | -------------------------------------------------------------------------------- /board/Fomu-PVT/Clock.SystemClock.pcf: -------------------------------------------------------------------------------- 1 | #| Fomu-PVT 2 | 3 | 4 | #> Clock (48 MHz) 5 | set_io --warn-no-port FomuPVT_CLK F4 6 | -------------------------------------------------------------------------------- /board/IceStick/Clock.SystemClock.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> Clock (12 MHz) 5 | set_io --warn-no-port IceStick_CLK 21 6 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/UART.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> UART 5 | set_io UPDuinov30_TX 38 6 | set_io UPDuinov30_RX 28 7 | -------------------------------------------------------------------------------- /board/Qomu/info.yml: -------------------------------------------------------------------------------- 1 | Label: Qomu 2 | Device: EOS-S3 3 | Documentation: https://www.quicklogic.com/products/eos-s3/qomu-dev-kit/ 4 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/TWI.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> TWI 5 | set_io UPDuinov30_TWI_SDA 31 6 | set_io UPDuinov30_TWI_SCL 37 7 | -------------------------------------------------------------------------------- /board/manila-iCE/info.yml: -------------------------------------------------------------------------------- 1 | Label: manila iCE 2 | Device: ICE40-HX4K 3 | Documentation: https://github.com/joshtyler/manila-ice 4 | -------------------------------------------------------------------------------- /board/Glasgow-revC/info.yml: -------------------------------------------------------------------------------- 1 | Label: Glasgow revC 2 | Device: ICE40-HX8K 3 | Documentation: https://github.com/GlasgowEmbedded/glasgow 4 | -------------------------------------------------------------------------------- /board/HX4K-PMOD/info.yml: -------------------------------------------------------------------------------- 1 | Label: HX4K PMOD Breakout 2 | Device: ICE-HX4K 3 | Documentation: https://github.com/rschlaikjer/hx4k-pmod 4 | -------------------------------------------------------------------------------- /board/Mercury2-A7-100T/info.yml: -------------------------------------------------------------------------------- 1 | Label: Mercury 2 A7-100T 2 | Package: XC7A100T 3 | Documentation: https://www.micro-nova.com/mercury-2 4 | -------------------------------------------------------------------------------- /board/Mercury2-A7-35T/info.yml: -------------------------------------------------------------------------------- 1 | Label: Mercury 2 A7-35T 2 | Package: XC7A35T 3 | Documentation: https://www.micro-nova.com/mercury-2 4 | -------------------------------------------------------------------------------- /board/Pygmy/info.yml: -------------------------------------------------------------------------------- 1 | Label: Pygmy Stamp Board 2 | Device: EOS-S3 3 | Documentation: https://www.optimuslogic.in/product_pygmy.html 4 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/Clock.SystemClock.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> Clock (16 MHz) 5 | set_io --warn-no-port TinyFPGABX_CLK B2 6 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/GPIO.LED.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> LED (bottom of the board) 5 | set_io --warn-no-port TinyFPGABX_LED B3 6 | -------------------------------------------------------------------------------- /board/iCEBreaker/GPIO.Button.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> User Reset Button 5 | set_io --warn-no-port iCEBreaker_USR_RST_BTN 10 6 | -------------------------------------------------------------------------------- /board/PicoEVB/info.yml: -------------------------------------------------------------------------------- 1 | Label: PicoEVB 2 | Device: XC7A50T-2 3 | Package: CSG325C 4 | Documentation: https://github.com/RHSResearchLLC/PicoEVB 5 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/Clock.SystemClock.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> Clock (12 MHz) 5 | set_io --warn-no-port IceZumAlhambraII_CLK 49 6 | -------------------------------------------------------------------------------- /board/iCE40CW312/UART.pcf: -------------------------------------------------------------------------------- 1 | #| iCE40CW312 2 | 3 | 4 | #> UART 5 | set_io --warn-no-port iCE40CW312_TX E5 6 | set_io --warn-no-port iCE40CW312_RX D5 7 | -------------------------------------------------------------------------------- /board/iCEBreaker/UART.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> UART 5 | set_io --warn-no-port iCEBreaker_TX 9 6 | set_io --warn-no-port iCEBreaker_RX 6 7 | -------------------------------------------------------------------------------- /board/iCEBreaker/TWI.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> TWI 5 | set_io --warn-no-port iCEBreaker_TWI_SDA 2 6 | set_io --warn-no-port iCEBreaker_TWI_SCL 4 7 | -------------------------------------------------------------------------------- /board/BeagleWire/info.yml: -------------------------------------------------------------------------------- 1 | Label: BeagleWire 2 | Device: ICE40-HX4K 3 | Documentation: 4 | "elinux.org: BeagleWire": https://elinux.org/BeagleBoard/BeagleWire 5 | -------------------------------------------------------------------------------- /board/ICECREAM-1.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: ICECREAM-1.0 2 | Device: ICE40-HX1K 3 | Documentation: http://www.ele.uva.es/~jesus/ICECREAM/index.html 4 | Prog: LPC1112 5 | -------------------------------------------------------------------------------- /board/ICECREAM-1.2/info.yml: -------------------------------------------------------------------------------- 1 | Label: ICECREAM-1.2 2 | Device: ICE40-HX4K 3 | Documentation: http://www.ele.uva.es/~jesus/ICECREAM/index.html 4 | Prog: LPC1112 5 | -------------------------------------------------------------------------------- /board/Litefury/info.yml: -------------------------------------------------------------------------------- 1 | Label: Litefury 2 | Device: XC7A100T-L2 3 | Package: FGG484E 4 | Documentation: https://github.com/RHSResearchLLC/NiteFury-and-LiteFury 5 | -------------------------------------------------------------------------------- /board/QuickFeather/info.yml: -------------------------------------------------------------------------------- 1 | Label: QuickFeather 2 | Device: EOS-S3 3 | Documentation: https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/ 4 | -------------------------------------------------------------------------------- /board/MNT-RKX7/info.yml: -------------------------------------------------------------------------------- 1 | Label: MNT Reform Kintex-7 SoM 2 | Device: XC7K160T 3 | Package: FFG676 4 | Documentation: https://source.mnt.re/reform/reform-kintex-som 5 | -------------------------------------------------------------------------------- /board/ECPIX-5-45F/info.yml: -------------------------------------------------------------------------------- 1 | Label: ECPIX-5 45F 2 | Device: ECP5-45F 3 | Documentation: https://shop.lambdaconcept.com/home/46-1-ecpix-5.html#/1-ecpix_5_fpga-ecpix_5_45f 4 | -------------------------------------------------------------------------------- /board/ECPIX-5-85F/info.yml: -------------------------------------------------------------------------------- 1 | Label: ECPIX-5 85F 2 | Device: ECP5-85F 3 | Documentation: https://shop.lambdaconcept.com/home/46-2-ecpix-5.html#/2-ecpix_5_fpga-ecpix_5_85f 4 | -------------------------------------------------------------------------------- /board/S3SK/vga.ucf: -------------------------------------------------------------------------------- 1 | NET "VGA_HSync" LOC = "R9"; 2 | NET "VGA_VSync" LOC = "T10"; 3 | NET "VGA_R" LOC = "R12"; 4 | NET "VGA_G" LOC = "T12"; 5 | NET "VGA_B" LOC = "R11"; 6 | -------------------------------------------------------------------------------- /board/icoBOARD-v1.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: icoBOARD v1.0 2 | Device: ICE40-HX8K 3 | Package: CT256 4 | Documentation: http://icoboard.org/about-icoboard.html 5 | Prog: icoprog 6 | -------------------------------------------------------------------------------- /board/ArcticKoala/info.yml: -------------------------------------------------------------------------------- 1 | Label: ArcticKoala 2 | Device: CrossLinkNX-LIFCL-40 3 | Documentation: 4 | "gh:gregdavill/ArcticKoala": https://github.com/gregdavill/ArcticKoala 5 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/GPIO.TriLED.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> RGB power LED 5 | set_io UPDuinov30_LED_R 39 6 | set_io UPDuinov30_LED_G 40 7 | set_io UPDuinov30_LED_B 41 8 | -------------------------------------------------------------------------------- /board/Xilinx/Disable_DRC_Rules_GTHE3_Common.xdc: -------------------------------------------------------------------------------- 1 | #Allow to drive GTHE3_COMMON.GTGREFCLK by global clock BUFG 2 | set_property IS_ENABLED 0 [ get_drc_checks {REQP-1751} ] 3 | -------------------------------------------------------------------------------- /board/Xilinx/Disable_DRC_Rules_GTPE2_Channel.xdc: -------------------------------------------------------------------------------- 1 | #Allow to drive GTPE2_CHANNEL.GTGREFCLK by global clock BUFG 2 | set_property IS_ENABLED 0 [ get_drc_checks {REQP-49} ] 3 | -------------------------------------------------------------------------------- /board/Xilinx/Disable_DRC_Rules_GTXE2_Channel.xdc: -------------------------------------------------------------------------------- 1 | #Allow to drive GTXE2_CHANNEL.GTGREFCLK by global clock BUFG 2 | set_property IS_ENABLED 0 [ get_drc_checks {REQP-52} ] 3 | -------------------------------------------------------------------------------- /board/iCE40CW312/GPIO.output.pcf: -------------------------------------------------------------------------------- 1 | #| iCE40CW312 2 | 3 | 4 | #> GPIO [output] 5 | set_io --warn-no-port iCE40CW312_GPIO_O[0] A5 6 | set_io --warn-no-port iCE40CW312_GPIO_O[1] A1 7 | -------------------------------------------------------------------------------- /board/doppler/info.yml: -------------------------------------------------------------------------------- 1 | Label: doppler 2 | Device: ICE40-UP5K 3 | Documentation: 4 | "gh:dadamachines/doppler: hardware": https://github.com/dadamachines/doppler/tree/master/hardware 5 | -------------------------------------------------------------------------------- /board/iCE40CW312/GPIO.input.pcf: -------------------------------------------------------------------------------- 1 | #| iCE40CW312 2 | 3 | 4 | 5 | #> GPIO [input] 6 | set_io --warn-no-port iCE40CW312_GPIO_I[0] A5 7 | set_io --warn-no-port iCE40CW312_GPIO_I[1] A1 8 | -------------------------------------------------------------------------------- /doc/References.rst: -------------------------------------------------------------------------------- 1 | .. _references: 2 | 3 | References 4 | ########## 5 | 6 | * `joelw.id.au/FPGA/CheapFPGADevelopmentBoards `__ 7 | -------------------------------------------------------------------------------- /board/Colorlight-i5-v7.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: Colorlight i5-v7.0 2 | Device: ECP5-25F 3 | Package: BGA381 4 | Documentation: https://github.com/wuxx/Colorlight-FPGA-Projects 5 | Prog: DAPLink 6 | -------------------------------------------------------------------------------- /board/Colorlight-i9-v7.2/info.yml: -------------------------------------------------------------------------------- 1 | Label: Colorlight i9-v7.2 2 | Device: ECP5-45F 3 | Package: BGA381 4 | Documentation: https://github.com/wuxx/Colorlight-FPGA-Projects 5 | Prog: DAPLink 6 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/GPIO.Buttons.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> Buttons 5 | set_io --warn-no-port IceZumAlhambraII_SW1 34 6 | set_io --warn-no-port IceZumAlhambraII_SW2 33 7 | -------------------------------------------------------------------------------- /board/ULX3S-12F/info.yml: -------------------------------------------------------------------------------- 1 | Label: ULX3S 12F 2 | Device: ECP5-12F 3 | Package: CABGA381 4 | Documentation: https://github.com/emard/ulx3s 5 | Prog: 6 | ID: "0403:6015" 7 | Tools: fujprog 8 | -------------------------------------------------------------------------------- /board/ULX3S-25F/info.yml: -------------------------------------------------------------------------------- 1 | Label: ULX3S 25F 2 | Device: ECP5-25F 3 | Package: CABGA381 4 | Documentation: https://github.com/emard/ulx3s 5 | Prog: 6 | ID: "0403:6015" 7 | Tools: fujprog 8 | -------------------------------------------------------------------------------- /board/ULX3S-45F/info.yml: -------------------------------------------------------------------------------- 1 | Label: ULX3S 45F 2 | Device: ECP5-45F 3 | Package: CABGA381 4 | Documentation: https://github.com/emard/ulx3s 5 | Prog: 6 | ID: "0403:6015" 7 | Tools: fujprog 8 | -------------------------------------------------------------------------------- /board/ULX3S-85F/info.yml: -------------------------------------------------------------------------------- 1 | Label: ULX3S 85F 2 | Device: ECP5-85F 3 | Package: CABGA381 4 | Documentation: https://github.com/emard/ulx3s 5 | Prog: 6 | ID: "0403:6015" 7 | Tools: fujprog 8 | -------------------------------------------------------------------------------- /board/CAT-Board/info.yml: -------------------------------------------------------------------------------- 1 | Label: CAT Board 2 | Device: ICE40-HX8K 3 | Package: CT256 4 | Documentation: 5 | "gh:xesscorp/CAT-Board": https://github.com/xesscorp/CAT-Board 6 | Prog: litterbox 7 | -------------------------------------------------------------------------------- /board/Fomu-PVT/USB.pcf: -------------------------------------------------------------------------------- 1 | #| Fomu-PVT 2 | 3 | 4 | #> USB 5 | set_io --warn-no-port FomuPVT_USB_DN A2 6 | set_io --warn-no-port FomuPVT_USB_DP A1 7 | set_io --warn-no-port FomuPVT_USB_DP_PU A4 8 | -------------------------------------------------------------------------------- /board/IceZero/info.yml: -------------------------------------------------------------------------------- 1 | Label: IceZero 2 | Device: ICE40-HX4K 3 | Documentation: https://shop.trenz-electronic.de/en/TE0876-02-A-IceZero-with-Lattice-ICE40HX-4-MBit-external-SRAM-5.6-x-3.05-cm 4 | -------------------------------------------------------------------------------- /board/KC705/info.yml: -------------------------------------------------------------------------------- 1 | Label: KC705 2 | Device: XC7K325T-2 3 | Package: FFG900C 4 | PartNumber: EK-K7-KC705-G 5 | Documentation: https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html 6 | -------------------------------------------------------------------------------- /board/VC707/info.yml: -------------------------------------------------------------------------------- 1 | Label: VC707 2 | Device: XC7VX485T-2 3 | Package: FFG1761 4 | PartNumber: EK-V7-VC707-G 5 | Documentation: https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html 6 | -------------------------------------------------------------------------------- /board/ZC706/info.yml: -------------------------------------------------------------------------------- 1 | Label: ZC706 2 | Device: XC7Z045-2 3 | Package: FFG900 4 | PartNumber: EK-Z7-ZC706-G 5 | Documentation: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html 6 | -------------------------------------------------------------------------------- /board/ML506/info.md: -------------------------------------------------------------------------------- 1 | --- 2 | Label: ML506 3 | --- 4 | 5 | The ML506 platform corresponds to the ML505 platform for all but the FPGA 6 | device. Refer to [ML505](../ML505/) for pinout information. 7 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/USB.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> USB 5 | set_io --warn-no-port TinyFPGABX_USBP B4 6 | set_io --warn-no-port TinyFPGABX_USBN A4 7 | set_io --warn-no-port TinyFPGABX_USBPU A3 8 | -------------------------------------------------------------------------------- /board/Fomu-PVT/GPIO.TriLED.pcf: -------------------------------------------------------------------------------- 1 | #| Fomu-PVT 2 | 3 | 4 | #> Tri-colour LED 5 | set_io --warn-no-port FomuPVT_RGB0 A5 6 | set_io --warn-no-port FomuPVT_RGB1 B5 7 | set_io --warn-no-port FomuPVT_RGB2 C5 8 | -------------------------------------------------------------------------------- /board/IceStick/Transceiver.IrDA.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> IrDA 5 | set_io --warn-no-port IceStick_IR_TX 105 6 | set_io --warn-no-port IceStick_IR_RX 106 7 | set_io --warn-no-port IceStick_IR_SD 107 8 | -------------------------------------------------------------------------------- /board/TinyFPGA-B2/info.yml: -------------------------------------------------------------------------------- 1 | Label: TinyFPGA B2 2 | Device: ICE40-LP8K 3 | Package: CM81 4 | Documentation: http://tinyfpga.com/b-series-guide.html 5 | Prog: 6 | ID: "1209:2100" 7 | Tools: tinyfpgab 8 | -------------------------------------------------------------------------------- /board/iceFUN/info.yml: -------------------------------------------------------------------------------- 1 | Label: iceFUN 2 | Device: ICE40-HX8K 3 | Package: CB132 4 | Documentation: https://www.robot-electronics.co.uk/icefun.html 5 | Prog: 6 | ID: "04d8:ffee" 7 | Tools: icefunprog 8 | -------------------------------------------------------------------------------- /board/iCESugar-pro/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCESugar-pro 2 | Device: ECP5-25F 3 | Package: BGA256 4 | Documentation: https://github.com/wuxx/icesugar-pro 5 | Prog: 6 | - DAPLink 7 | - FT2232 8 | - USB-Blaster 9 | -------------------------------------------------------------------------------- /board/BusPirateUltra/info.yml: -------------------------------------------------------------------------------- 1 | Label: BusPirate Ultra 2 | Device: ICE40-HX4K 3 | Documentation: 4 | "gh:DangerousPrototypes/BusPirateUltraHardware": https://github.com/DangerousPrototypes/BusPirateUltraHardware 5 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/SPI.user.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> SPI [user port] 5 | set_io UPDuinov30_SPI_SDO 34 6 | set_io UPDuinov30_SPI_SCK 43 7 | set_io UPDuinov30_SPI_CSN 36 8 | set_io UPDuinov30_SPI_SDI 42 9 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/GPIO.input.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> GPIO [input] 5 | set_io UPDuinov30_GPIO_I[0] 44 6 | set_io UPDuinov30_GPIO_I[1] 4 7 | set_io UPDuinov30_GPIO_I[2] 3 8 | set_io UPDuinov30_GPIO_I[3] 48 9 | -------------------------------------------------------------------------------- /board/iCEBreaker/GPIO.TriLED.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> RGB power LED 5 | set_io --warn-no-port iCEBreaker_LED_R 39 6 | set_io --warn-no-port iCEBreaker_LED_G 40 7 | set_io --warn-no-port iCEBreaker_LED_B 41 8 | -------------------------------------------------------------------------------- /doc/Data/Devices.rst: -------------------------------------------------------------------------------- 1 | .. Devices: 2 | 3 | Devices 4 | ####### 5 | 6 | .. image:: ../_static/work-in-progress.png 7 | :height: 275 px 8 | :align: center 9 | :target: https://github.com/hdl/constraints 10 | -------------------------------------------------------------------------------- /doc/Data/SDRAM.rst: -------------------------------------------------------------------------------- 1 | .. _Data:SDRAM: 2 | 3 | SDRAM 4 | ##### 5 | 6 | .. image:: ../_static/work-in-progress.png 7 | :height: 275 px 8 | :align: center 9 | :target: https://github.com/hdl/constraints 10 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/GPIO.output.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> GPIO [output] 5 | set_io UPDuinov30_GPIO_O[0] 45 6 | set_io UPDuinov30_GPIO_O[1] 47 7 | set_io UPDuinov30_GPIO_O[2] 46 8 | set_io UPDuinov30_GPIO_O[3] 2 9 | -------------------------------------------------------------------------------- /board/DIPSY-EPT/info.yml: -------------------------------------------------------------------------------- 1 | Label: DIPSY EPT 2 | Device: ICE40-HX1K 3 | Documentation: 4 | "wiki.trenz-electronic.de: DIPSY EPT (Emulator Programmer Tool)": https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=20611802 5 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/SPI.onboard.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> SPI [on-board flash] 5 | set_io UPDuinov30_FLASH_SDO 14 6 | set_io UPDuinov30_FLASH_SCK 15 7 | set_io UPDuinov30_FLASH_CSN 16 8 | set_io UPDuinov30_FLASH_SDI 17 9 | -------------------------------------------------------------------------------- /board/iCEblink40-HX1K/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCEblink40-HX1K Evaluation Kit 2 | Device: ICE40-HX1K 3 | Package: VQ100 4 | Documentation: http://www.latticesemi.com/iCEblink40-HX1K 5 | Prog: 6 | ID: "1443:0007" 7 | Tools: iCEburn 8 | -------------------------------------------------------------------------------- /board/Kefir/info.yml: -------------------------------------------------------------------------------- 1 | Label: Kéfir I iCE40-HX4K 2 | Device: ICE40-HX4K 3 | Package: TQ144 4 | Documentation: http://fpgalibre.sourceforge.net/Kefir/ 5 | Prog: 6 | ID: "0403:6010" 7 | Description: Milk JTAG:u 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/info.yml: -------------------------------------------------------------------------------- 1 | Label: TinyFPGA-BX 2 | Device: ICE40-LP8K 3 | Package: CM81 4 | Documentation: https://github.com/tinyfpga/TinyFPGA-BX 5 | Prog: 6 | ID: "1d50:6130" 7 | Description: TinyFPGA BX 8 | Tools: tinyprog 9 | -------------------------------------------------------------------------------- /board/iCESugar-v1.5/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCESugar v1.5 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: https://github.com/wuxx/icesugar 5 | Prog: 6 | ID: "1d50:602b" 7 | Tools: 8 | - icesprog 9 | - DAPLink 10 | -------------------------------------------------------------------------------- /board/openFPGA/info.yml: -------------------------------------------------------------------------------- 1 | Label: openFPGA 2 | Documentation: 3 | "analogue.co/developer": https://www.analogue.co/developer 4 | "joshcampbell191/openfpga-cores-inventory": https://github.com/joshcampbell191/openfpga-cores-inventory 5 | -------------------------------------------------------------------------------- /.btd.yml: -------------------------------------------------------------------------------- 1 | input: doc 2 | output: _build 3 | requirements: requirements.txt 4 | target: gh-pages 5 | formats: [ html ] 6 | images: 7 | base: btdi/sphinx:pytooling 8 | theme: https://codeload.GitHub.com/buildthedocs/sphinx.theme/tar.gz/v1 9 | -------------------------------------------------------------------------------- /board/IceZumAlhambra/info.yml: -------------------------------------------------------------------------------- 1 | Label: IceZUM Alhambra 2 | Device: ICE40-HX1K 3 | Package: TQ144 4 | Documentation: https://github.com/FPGAwars/icezum 5 | Prog: 6 | ID: "0403:6010" 7 | Description: IceZUM Alhambra 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/UPDuino-v1.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: UPDuino v1.0 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: https://github.com/gtjennings1/UPDuino_v1_0 5 | Prog: 6 | ID: "0403:6014" 7 | Description: Single RS232-HS 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/UPDuino-v2.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: UPDuino v2.0 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: https://github.com/gtjennings1/UPDuino_v2_0 5 | Prog: 6 | ID: "0403:6014" 7 | Description: Single RS232-HS 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/iCESugar-nano/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCESugar-nano 2 | Device: ICE40-LP1K 3 | Package: CM36 4 | Documentation: https://github.com/wuxx/icesugar-nano 5 | Prog: 6 | ID: "1d50:602b" 7 | Tools: 8 | - icesprog 9 | - DAPLink 10 | -------------------------------------------------------------------------------- /board/BlackIce-MX/info.yml: -------------------------------------------------------------------------------- 1 | Label: myStorm BlackIce MX 2 | Device: ICE40-HX8K 3 | Package: TQ144 4 | Documentation: 5 | "gh:folknology/IceCore": https://github.com/folknology/IceCore 6 | Prog: 7 | ID: "0483:5740" 8 | Tools: blackiceprog 9 | -------------------------------------------------------------------------------- /board/Fomu-PVT/GPIO.Buttons.pcf: -------------------------------------------------------------------------------- 1 | #| Fomu-PVT 2 | 3 | 4 | #> Buttons 5 | set_io --warn-no-port FomuPVT_USER1 E4 6 | set_io --warn-no-port FomuPVT_USER2 D5 7 | set_io --warn-no-port FomuPVT_USER3 E5 8 | set_io --warn-no-port FomuPVT_USER4 F5 9 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: UPDuino v3.0 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: https://github.com/tinyvision-ai-inc/UPduino-v3.0 5 | Prog: 6 | ID: "0403:6014" 7 | Description: UPduino v3.0 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/iCE40-feather-r0.2/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCE40 Feather r0.2 2 | Device: ICE40-UP5K 3 | Documentation: 4 | - https://github.com/joshajohnson/iCE40-feather 5 | - https://www.pcbway.com/project/gifts_detail/iCE40_Feather.html 6 | Prog: iceprog 7 | -------------------------------------------------------------------------------- /board/Atlys/info.yml: -------------------------------------------------------------------------------- 1 | Label: Atlys 2 | Description: Spartan-6 FPGA Trainer Board 3 | Device: XC6SLX45 4 | Package: CSG324C 5 | Documentation: 6 | "digilentinc.com: Atlys": https://reference.digilentinc.com/reference/programmable-logic/atlys/start 7 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/Bus.I2C.ADC.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> I2C ADC 5 | set_io --warn-no-port IceZumAlhambraII_ADC_SCL 84 6 | set_io --warn-no-port IceZumAlhambraII_ADC_SDA 83 7 | set_io --warn-no-port IceZumAlhambraII_ADC_INT 90 8 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/info.yml: -------------------------------------------------------------------------------- 1 | Label: IceZUM Alhambra II 2 | Device: ICE40-HX4K 3 | Package: TQ144 4 | Documentation: https://github.com/FPGAwars/Alhambra-II-FPGA 5 | Prog: 6 | ID: "0403:6010" 7 | Description: Alhambra II 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/UPDuino-v2.1/info.yml: -------------------------------------------------------------------------------- 1 | Label: UPDuino v2.1 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: https://github.com/tinyvision-ai-inc/UPduino-v2.1 5 | Prog: 6 | ID: "0403:6014" 7 | Description: Single RS232-HS 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/BlackIce-II/info.yml: -------------------------------------------------------------------------------- 1 | Label: myStorm BlackIce II 2 | Device: ICE40-HX8K 3 | Package: TQ144 4 | Documentation: 5 | "gh:mystorm-org/BlackIce-II": https://github.com/mystorm-org/BlackIce-II 6 | Prog: 7 | ID: "0483:5740" 8 | Tools: blackiceprog 9 | -------------------------------------------------------------------------------- /board/IceStick/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCEstick Evaluation Kit 2 | Device: ICE40-HX1K 3 | Package: TQ144 4 | Documentation: http://www.latticesemi.com/icestick 5 | Prog: 6 | ID: "0403:6010" 7 | Description: Lattice FTUSB Interface Cable 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/Nandland-Go/info.yml: -------------------------------------------------------------------------------- 1 | Label: Nandland Go board 2 | Device: ICE40-HX1K 3 | Package: VQ100 4 | Documentation: https://www.nandland.com/goboard/introduction.html 5 | Prog: 6 | ID: "0403:6010" 7 | Description: "Dual RS232-HS" 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/iCE40CW312/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCE40CW312 2 | Device: ICE40-UP5K 3 | Package: UWG30 4 | Documentation: 5 | "gh:newaetech/chipwhisperer-target-cw308t/CW312T_ICE40UP": https://github.com/newaetech/chipwhisperer-target-cw308t/tree/main/CW312T_ICE40UP 6 | -------------------------------------------------------------------------------- /board/iCE40HX1K-EVB/info.yml: -------------------------------------------------------------------------------- 1 | Label: Olimex iCE40HX1K-EVB 2 | Device: ICE40-HX1K 3 | Package: VQ100 4 | Documentation: https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware 5 | Prog: 6 | ID: "2341:8036" 7 | Tools: iceprogduino 8 | -------------------------------------------------------------------------------- /board/iCE40HX8K-EVB/info.yml: -------------------------------------------------------------------------------- 1 | Label: Olimex iCE40HX8K-EVB 2 | Device: ICE40-HX8K 3 | Package: CT256 4 | Documentation: https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware 5 | Prog: 6 | ID: "2341:8036" 7 | Tools: iceprogduino 8 | -------------------------------------------------------------------------------- /board/Alchitry-Cu/info.yml: -------------------------------------------------------------------------------- 1 | Label: Alchitry Cu 2 | Device: ICE40-HX8K 3 | Package: CB132 4 | Documentation: 5 | "alchitry.com: Alchitry Cu": https://alchitry.com/boards/cu 6 | Prog: 7 | ID: "0403:6010" 8 | Description: Alchitry Cu 9 | Tools: iceprog 10 | -------------------------------------------------------------------------------- /board/EDU-CIAA-FPGA/info.yml: -------------------------------------------------------------------------------- 1 | Label: EDU-CIAA-FPGA 2 | Device: ICE40-HX4K 3 | Package: TQ144 4 | Documentation: http://www.proyecto-ciaa.com.ar/devwiki/doku.php?id=desarrollo:edu-fpga 5 | Prog: 6 | ID: "0403:6010" 7 | Description: Dual RS232-HS 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/iCE40CW312/SPI.user.pcf: -------------------------------------------------------------------------------- 1 | #| iCE40CW312 2 | 3 | 4 | #> SPI [user port] 5 | set_io --warn-no-port iCE40CW312_SPI_SDO F1 6 | set_io --warn-no-port iCE40CW312_SPI_SCK D1 7 | set_io --warn-no-port iCE40CW312_SPI_CSN C1 8 | set_io --warn-no-port iCE40CW312_SPI_SDI E1 9 | -------------------------------------------------------------------------------- /board/iCEBreaker/SPI.user.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> SPI [user port] 5 | set_io --warn-no-port iCEBreaker_SPI_SDO 43 6 | set_io --warn-no-port iCEBreaker_SPI_SCK 38 7 | set_io --warn-no-port iCEBreaker_SPI_CSN 34 8 | set_io --warn-no-port iCEBreaker_SPI_SDI 31 9 | -------------------------------------------------------------------------------- /board/Arty-S7-25/info.yml: -------------------------------------------------------------------------------- 1 | Label: Arty S7-25 2 | PartNumber: 410-352 3 | Device: XC7S25 4 | Package: CSGA324 5 | Documentation: 6 | "digilentinc.com: Arty S7: Spartan-7 FPGA Development Board": https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-hobbyists-and-makers/ 7 | -------------------------------------------------------------------------------- /board/Arty-S7-50/info.yml: -------------------------------------------------------------------------------- 1 | Label: Arty S7-50 2 | PartNumber: 410-352 3 | Device: XC7S50 4 | Package: CSGA324 5 | Documentation: 6 | "digilentinc.com: Arty S7: Spartan-7 FPGA Development Board": https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-hobbyists-and-makers/ 7 | -------------------------------------------------------------------------------- /board/iCEBreaker/GPIO.input.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> GPIO [input] 5 | set_io --warn-no-port iCEBreaker_GPIO_I[0] 18 6 | set_io --warn-no-port iCEBreaker_GPIO_I[1] 19 7 | set_io --warn-no-port iCEBreaker_GPIO_I[2] 20 8 | set_io --warn-no-port iCEBreaker_GPIO_I[3] 28 9 | -------------------------------------------------------------------------------- /board/iCEBreaker/GPIO.output.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> GPIO [output] 5 | set_io --warn-no-port iCEBreaker_GPIO_O[0] 25 6 | set_io --warn-no-port iCEBreaker_GPIO_O[1] 26 7 | set_io --warn-no-port iCEBreaker_GPIO_O[2] 27 8 | set_io --warn-no-port iCEBreaker_GPIO_O[3] 23 9 | -------------------------------------------------------------------------------- /board/iCEBreaker/SPI.onboard.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> SPI [on-board flash] 5 | set_io --warn-no-port iCEBreaker_FLASH_SDO 14 6 | set_io --warn-no-port iCEBreaker_FLASH_SCK 15 7 | set_io --warn-no-port iCEBreaker_FLASH_CSN 16 8 | set_io --warn-no-port iCEBreaker_FLASH_SDI 17 9 | -------------------------------------------------------------------------------- /board/iCEBreaker/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCEBreaker 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: 5 | "gh:icebreaker-fpga/icebreaker": https://github.com/icebreaker-fpga/icebreaker 6 | Prog: 7 | ID: "0403:6010" 8 | Description: Dual RS232-HS 9 | Tools: iceprog 10 | -------------------------------------------------------------------------------- /board/Arty-A7-35T/info.yml: -------------------------------------------------------------------------------- 1 | Label: Arty A7-35T 2 | PartNumber: 410-319 3 | Device: XC7A35T 4 | Package: ICSG324-1L 5 | Documentation: 6 | "digilentinc.com: Arty A7: Artix-7 FPGA Development Board": https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/ 7 | -------------------------------------------------------------------------------- /board/FPGA101/info.yml: -------------------------------------------------------------------------------- 1 | Label: FPGA 101 Workshop Badge Board 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: 5 | "gh:mmicko/workshop_badge": https://github.com/mmicko/workshop_badge 6 | Prog: 7 | ID: "0403:6014" 8 | Description: Single RS232-HS 9 | Tools: iceprog 10 | -------------------------------------------------------------------------------- /board/Fomu-PVT/info.yml: -------------------------------------------------------------------------------- 1 | Label: Fomu PVT 2 | Device: ICE40-UP5K 3 | Package: UWG30 4 | Documentation: 5 | "gh:im-tomu/fomu-hardware": https://github.com/im-tomu/fomu-hardware 6 | Prog: 7 | ID: "1209:5bf0" 8 | Description: Fomu PVT running DFU Bootloader 9 | Tools: dfu-util 10 | -------------------------------------------------------------------------------- /board/ZedBoard/info.yml: -------------------------------------------------------------------------------- 1 | Label: ZedBoard 2 | Device: XC7Z020-1 3 | Package: CLG484 4 | PartNumber: AES-Z7EV-7Z020-G 5 | Documentation: 6 | - https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html 7 | - https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ 8 | -------------------------------------------------------------------------------- /board/Arty-A7-100T/info.yml: -------------------------------------------------------------------------------- 1 | Label: Arty A7-100T 2 | PartNumber: 410-319 3 | Device: XC7A100T 4 | Package: ICSG324-1L 5 | Documentation: 6 | "digilentinc.com: Arty A7: Artix-7 FPGA Development Board": https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/ 7 | -------------------------------------------------------------------------------- /board/iCE40-HX8K/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCE40-HX8K Breakout Board 2 | Device: ICE40-HX8K 3 | Package: CT256 4 | Documentation: http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard 5 | Prog: 6 | ID: "0403:6010" 7 | Description: "Lattice FTUSB Interface Cable" 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/iCEBreaker-bitsy-v0/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCEBreaker bitsy v0 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: 5 | "gh:icebreaker-fpga/icebreaker": https://github.com/icebreaker-fpga/icebreaker 6 | Prog: 7 | ID: "1d50:6146" 8 | Description: iCEBreaker bitsy v0 9 | Tools: dfu-util 10 | -------------------------------------------------------------------------------- /board/iCEBreaker-bitsy-v1/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCEBreaker bitsy v1 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: 5 | "gh:icebreaker-fpga/icebreaker": https://github.com/icebreaker-fpga/icebreaker 6 | Prog: 7 | ID: "1d50:6146" 8 | Description: iCEBreaker bitsy v1 9 | Tools: dfu-util 10 | -------------------------------------------------------------------------------- /board/iCE40-UP/info.yml: -------------------------------------------------------------------------------- 1 | Label: iCE40 UltraPlus Breakout Board 2 | Device: ICE40-UP5K 3 | Package: SG48 4 | Documentation: http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40UltraPlusBreakoutBoard 5 | Prog: 6 | ID: "0403:6010" 7 | Description: Lattice iCE40UP5K Breakout 8 | Tools: iceprog 9 | -------------------------------------------------------------------------------- /board/OrangeCrab-r0.2/info.yml: -------------------------------------------------------------------------------- 1 | Label: OrangeCrab-r0.2-25F 2 | Device: ECP5-25F 3 | Package: csfBGA285 4 | Documentation: https://github.com/orangecrab-fpga/orangecrab-hardware 5 | Prog: 6 | ID: "1209:5af0" 7 | Description: OrangeCrab r0.2 DFU bootloader 8 | Tools: 9 | - openocd 10 | - dfu-util 11 | -------------------------------------------------------------------------------- /board/S3SK/buttons.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - user buttons (without reset): BTN2 - BTN0 7 | # 8 | NET "btn<*>" IOSTANDARD = LVCMOS33 ; 9 | NET "btn<2>" LOC = "L13" ; 10 | NET "btn<1>" LOC = "M14" ; 11 | NET "btn<0>" LOC = "M13" ; 12 | -------------------------------------------------------------------------------- /board/Fomu-PVT/Bus.SPI.pcf: -------------------------------------------------------------------------------- 1 | #| Fomu-PVT 2 | 3 | 4 | #> SPI 5 | set_io --warn-no-port FomuPVT_SPI_MOSI F1 6 | set_io --warn-no-port FomuPVT_SPI_MISO E1 7 | set_io --warn-no-port FomuPVT_SPI_CLK D1 8 | set_io --warn-no-port FomuPVT_SPI_IO2 F2 9 | set_io --warn-no-port FomuPVT_SPI_IO3 B1 10 | set_io --warn-no-port FomuPVT_SPI_cs C1 11 | -------------------------------------------------------------------------------- /board/IceStick/FTDI.Port0.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> FTDI 5 | # FTDI 0 6 | set_io --warn-no-port IceStick_RES 66 7 | set_io --warn-no-port IceStick_DONE 65 8 | set_io --warn-no-port IceStick_SS 71 9 | set_io --warn-no-port IceStick_MISO 68 10 | set_io --warn-no-port IceStick_MOSI 67 11 | set_io --warn-no-port IceStick_SCK 70 12 | -------------------------------------------------------------------------------- /board/ZC706/Clock.SMAClock.xdc: -------------------------------------------------------------------------------- 1 | ## Bank: 9 2 | ## VCCO: 2.5V (VADJ_FPGA) 3 | ## Location: J67, J68 4 | set_property PACKAGE_PIN AD18 [get_ports ZC706_SMAClock_p] 5 | set_property PACKAGE_PIN AD19 [get_ports ZC706_SMAClock_n] 6 | # set I/O standard 7 | set_property IOSTANDARD LVDS_25 [get_ports -regexp {ZC706_SMAClock_.}] 8 | -------------------------------------------------------------------------------- /board/XUPV5/info.md: -------------------------------------------------------------------------------- 1 | --- 2 | Label: XUPV5 3 | Device: XC5VLX110T-1 4 | Package: FFG1136 5 | Documentation: https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentXUPV5Board.html 6 | --- 7 | 8 | The XUPV5 platform corresponds to the ML505 platform for all but the FPGA 9 | device. Refer to [ML505](../ML505/) for pinout information. 10 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/Bus.SPI.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> SPI flash 5 | set_io --warn-no-port TinyFPGABX_SPI_SS F7 6 | set_io --warn-no-port TinyFPGABX_SPI_SCK G7 7 | set_io --warn-no-port TinyFPGABX_SPI_IO0 G6 8 | set_io --warn-no-port TinyFPGABX_SPI_IO1 H7 9 | set_io --warn-no-port TinyFPGABX_SPI_IO2 H4 10 | set_io --warn-no-port TinyFPGABX_SPI_IO3 J8 11 | -------------------------------------------------------------------------------- /board/IceStick/FTDI.Port1.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> FTDI 5 | # FTDI 1 6 | set_io --warn-no-port IceStick_DCD 1 7 | set_io --warn-no-port IceStick_DSR 2 8 | set_io --warn-no-port IceStick_DTR 3 9 | set_io --warn-no-port IceStick_CTS 4 10 | set_io --warn-no-port IceStick_RTS 7 11 | set_io --warn-no-port IceStick_TX 8 12 | set_io --warn-no-port IceStick_RX 9 13 | -------------------------------------------------------------------------------- /board/IceStick/GPIO.LED.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> LEDs 5 | # D1 6 | # D4 D5 D2 7 | # D3 8 | # 9 | # D1-D4: red 10 | # D5: green 11 | 12 | set_io --warn-no-port IceStick_LED1 99 13 | set_io --warn-no-port IceStick_LED2 98 14 | set_io --warn-no-port IceStick_LED3 97 15 | set_io --warn-no-port IceStick_LED4 96 16 | set_io --warn-no-port IceStick_LED5 95 17 | -------------------------------------------------------------------------------- /board/ML505/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 3 4 | ## ReferenceClock 5 | ## Location: J25, J26 6 | NET "ML505_SMA_RefClock_p" LOC = "H14"; ## J25 7 | NET "ML505_SMA_RefClock_n" LOC = "H15"; ## J26 8 | 9 | -------------------------------------------------------------------------------- /board/ZC706/Transceiver.SMA_RefClock.xdc: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 111 4 | ## ReferenceClock MGT_REFCLK1 5 | ## Location: J36, J31 6 | set_property PACKAGE_PIN W8 [get_ports ZC706_SMA_RefClock_p] 7 | set_property PACKAGE_PIN W7 [get_ports ZC706_SMA_RefClock_n] 8 | -------------------------------------------------------------------------------- /board/VC707/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 113 4 | ## ReferenceClock 5 | ## Location: J25, J26 6 | NET "VC707_SMA_RefClock_p" LOC = "AK8"; ## J25 7 | NET "VC707_SMA_RefClock_n" LOC = "AK7"; ## J26 8 | 9 | -------------------------------------------------------------------------------- /board/ML505/Clock.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## SMA Clock 2 | ## ============================================================================= 3 | ## Bank: 14 4 | ## VCCO: 2.5V (VCC2V5_FPGA) 5 | ## Location: J10, J11 6 | NET "ML505_SMAClock_in_p" LOC = "H14" | IOSTANDARD = LVCMOS25; ## {INOUT} J10 7 | NET "ML505_SMAClock_in_n" LOC = "H15" | IOSTANDARD = LVCMOS25; ## {INOUT} J11 8 | -------------------------------------------------------------------------------- /board/ZC706/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 111 4 | ## ReferenceClock MGT_REFCLK1 5 | ## Location: J36, J31 6 | NET "ZC706_SMA_RefClock_p" LOC = "W8"; ## J25 7 | NET "ZC706_SMA_RefClock_n" LOC = "W7"; ## J26 8 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | SPHINXOPTS = 2 | SPHINXBUILD = sphinx-build 3 | PAPER = 4 | BUILDDIR = _build 5 | 6 | PAPEROPT_a4 = -D latex_paper_size=a4 7 | PAPEROPT_letter = -D latex_paper_size=letter 8 | ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees -T -D language=en $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) . 9 | 10 | %: 11 | $(SPHINXBUILD) -b $@ $(ALLSPHINXOPTS) $(BUILDDIR)/$@ 12 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/FTDI.Port0.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> FTDI 5 | # FTDI 0 6 | set_io --warn-no-port IceZumAlhambraII_RES 66 7 | set_io --warn-no-port IceZumAlhambraII_DONE 65 8 | set_io --warn-no-port IceZumAlhambraII_SS 71 9 | set_io --warn-no-port IceZumAlhambraII_MISO 68 10 | set_io --warn-no-port IceZumAlhambraII_MOSI 67 11 | set_io --warn-no-port IceZumAlhambraII_SCK 70 12 | -------------------------------------------------------------------------------- /board/S3SK/default.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - default board clock (100 MHz) 7 | # - user reset (BTN3) 8 | # 9 | NET "clk" TNM_NET = "clk"; 10 | TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %; 11 | 12 | NET "clk" LOC = "T9" | IOSTANDARD = LVCMOS33 ; 13 | NET "rst" LOC = "L14" | IOSTANDARD = LVCMOS33 ; 14 | -------------------------------------------------------------------------------- /board/BlackIce/info.yml: -------------------------------------------------------------------------------- 1 | Label: myStorm BlackIce 2 | Device: ICE40-HX8K 3 | Package: TQ144 4 | Documentation: 5 | "gl:Folknology/mystorm: BlackIce": https://gitlab.com/Folknology/mystorm/-/tree/BlackIce 6 | "hackaday.io: BlackIce - Low Cost Open Hardware FPGA Dev Board": https://hackaday.io/project/12930-blackice-low-cost-open-hardware-fpga-dev-board 7 | Prog: 8 | ID: "0483:5740" 9 | Tools: blackiceprog 10 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/GPIO.Bottom.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> GP I/O (bottom of the board) 5 | set_io --warn-no-port TinyFPGABX_PIN_25 G1 6 | set_io --warn-no-port TinyFPGABX_PIN_26 J3 7 | set_io --warn-no-port TinyFPGABX_PIN_27 J4 8 | set_io --warn-no-port TinyFPGABX_PIN_28 G9 9 | set_io --warn-no-port TinyFPGABX_PIN_29 J9 10 | set_io --warn-no-port TinyFPGABX_PIN_30 E8 11 | set_io --warn-no-port TinyFPGABX_PIN_31 J2 12 | -------------------------------------------------------------------------------- /board/S3SK/switches.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - slide switched 7 | # 8 | NET "sw<*>" IOSTANDARD = LVCMOS33 ; 9 | NET "sw<0>" LOC = "F12" ; 10 | NET "sw<1>" LOC = "G12" ; 11 | NET "sw<2>" LOC = "H14" ; 12 | NET "sw<3>" LOC = "H13" ; 13 | NET "sw<4>" LOC = "J14" ; 14 | NET "sw<5>" LOC = "J13" ; 15 | NET "sw<6>" LOC = "K14" ; 16 | NET "sw<7>" LOC = "K13" ; 17 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/FTDI.Port1.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> FTDI 5 | # FTDI 1 6 | set_io --warn-no-port IceZumAlhambraII_DCD 47 7 | set_io --warn-no-port IceZumAlhambraII_DSR 48 8 | set_io --warn-no-port IceZumAlhambraII_DTR 52 9 | set_io --warn-no-port IceZumAlhambraII_CTS 56 10 | set_io --warn-no-port IceZumAlhambraII_RTS 60 11 | set_io --warn-no-port IceZumAlhambraII_TX 61 12 | set_io --warn-no-port IceZumAlhambraII_RX 62 13 | -------------------------------------------------------------------------------- /board/S3SK/leds.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - LEDs 7 | # 8 | NET "leds<*>" IOSTANDARD = LVCMOS33 ; 9 | NET "leds<0>" LOC = "K12" ; 10 | NET "leds<1>" LOC = "P14" ; 11 | NET "leds<2>" LOC = "L12" ; 12 | NET "leds<3>" LOC = "N14" ; 13 | NET "leds<4>" LOC = "P13" ; 14 | NET "leds<5>" LOC = "N12" ; 15 | NET "leds<6>" LOC = "P12" ; 16 | NET "leds<7>" LOC = "P11" ; 17 | -------------------------------------------------------------------------------- /board/ButterStick-r1.0/info.yml: -------------------------------------------------------------------------------- 1 | Label: ButterStick-r1.0-85F 2 | Device: ECP5-85F 3 | Package: CABGA381 4 | Documentation: 5 | "gh:butterstick-fpga/butterstick-hardware": https://github.com/butterstick-fpga/butterstick-hardware 6 | "groupgets.com: ButterStick by Good Stuff Department": https://groupgets.com/campaigns/868-butterstick 7 | Prog: 8 | ID: "1209:5af1" 9 | Description: Butterstick (dfu v1.1) 10 | Tools: 11 | - openocd 12 | - dfu-util 13 | -------------------------------------------------------------------------------- /board/DE4/GPIO.LED.sdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## ----------------------------------------------------------------------------- 8 | if {$TimingConstraints == 0} then { 9 | # is it possible to define pin and I/O standard constraints here? 10 | } else { 11 | # Ignore timings on async I/O pins 12 | set_false_path -to [get_ports DE4_GPIO_LED_n*] 13 | } 14 | -------------------------------------------------------------------------------- /board/VC707/Bus.PMBus.ucf: -------------------------------------------------------------------------------- 1 | ## PowerManagementBus (PMBus) 2 | ## ============================================================================= 3 | ## Bank: 15 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: 6 | ## Vendor: 7 | ## Device: 8 | ##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## 9 | ##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## 10 | ##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## 11 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/GPIO.LED.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> LEDs 5 | set_io --warn-no-port IceZumAlhambraII_LED0 45 6 | set_io --warn-no-port IceZumAlhambraII_LED1 44 7 | set_io --warn-no-port IceZumAlhambraII_LED2 43 8 | set_io --warn-no-port IceZumAlhambraII_LED3 42 9 | set_io --warn-no-port IceZumAlhambraII_LED4 41 10 | set_io --warn-no-port IceZumAlhambraII_LED5 39 11 | set_io --warn-no-port IceZumAlhambraII_LED6 38 12 | set_io --warn-no-port IceZumAlhambraII_LED7 37 13 | -------------------------------------------------------------------------------- /board/XUPV5/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ========================================================================== 2 | ## Xilinx User Constraint File (UCF) 3 | ## ========================================================================== 4 | ## Board: Xilinx - Virtex 5 XUPV5 5 | ## FPGA: Xilinx Virtex 5 6 | ## Device: XC5VLX110T 7 | ## Package: FF1136 8 | ## Speedgrade: -1 9 | ## ========================================================================== 10 | CONFIG PART = XC5VLX110T-FFG1136-1; 11 | -------------------------------------------------------------------------------- /board/ML506/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ========================================================================== 2 | ## Xilinx User Constraint File (UCF) 3 | ## ========================================================================== 4 | ## Board: Xilinx - Virtex 5 ML506 5 | ## FPGA: Xilinx Virtex 5 6 | ## Device: XC5VSX50T 7 | ## Package: FF1136 8 | ## Speedgrade: -1 9 | ## ========================================================================== 10 | CONFIG PART = XC5VSX50T-FF1136-1; 11 | CONFIG STEPPING = "ES"; 12 | -------------------------------------------------------------------------------- /board/IceStick/GPIO.Top.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> I/O 5 | # 7 6 5 4 3 2 1 0 6 | # TOP | 119 118 117 116 115 114 113 112 GND 3V3 | < 7 | 8 | set_io --warn-no-port IceStick_TR0 112 9 | set_io --warn-no-port IceStick_TR1 113 10 | set_io --warn-no-port IceStick_TR2 114 11 | set_io --warn-no-port IceStick_TR3 115 12 | set_io --warn-no-port IceStick_TR4 116 13 | set_io --warn-no-port IceStick_TR5 117 14 | set_io --warn-no-port IceStick_TR6 118 15 | set_io --warn-no-port IceStick_TR7 119 16 | -------------------------------------------------------------------------------- /board/DE4/FanControl.sdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Fan Control 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: J48, Q1 7 | ## ----------------------------------------------------------------------------- 8 | if {$TimingConstraints == 0} then { 9 | # is it possible to define pin and I/O standard constraints here? 10 | } else { 11 | # Ignore timings on async I/O pins 12 | set_false_path -to [get_ports DE4_FanControl] 13 | } 14 | -------------------------------------------------------------------------------- /board/IceStick/GPIO.Bottom.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> I/O 5 | # 7 6 5 4 3 2 1 0 6 | # BOT | 44 45 47 48 56 60 61 62 GND 3V3 | < 7 | 8 | set_io --warn-no-port IceStick_BR0 62 9 | set_io --warn-no-port IceStick_BR1 61 10 | set_io --warn-no-port IceStick_BR2 60 11 | set_io --warn-no-port IceStick_BR3 56 12 | set_io --warn-no-port IceStick_BR4 48 13 | set_io --warn-no-port IceStick_BR5 47 14 | set_io --warn-no-port IceStick_BR6 45 15 | set_io --warn-no-port IceStick_BR7 44 16 | -------------------------------------------------------------------------------- /board/ML505/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Special Buttons 3 | ## ============================================================================= 4 | ## Bank: 20 5 | ## VCCO: 3.3V (VCC3V3_FPGA) 6 | ## Location: SW7 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_Button_CPU_Reset_n" LOC = "E9" | IOSTANDARD = LVCMOS33; ## {IN} low-active; external 4k7 pullup resistor 9 | 10 | ## Ignore timings on async I/O pins 11 | NET "ML505_GPIO_Button_CPU_Reset_n" TIG; 12 | -------------------------------------------------------------------------------- /board/DE4/GPIO.Seg7.sdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## ----------------------------------------------------------------------------- 8 | if {$TimingConstraints == 0} then { 9 | # is it possible to define pin and I/O standard constraints here? 10 | } else { 11 | # Ignore timings on async I/O pins 12 | set_false_path -to [get_ports DE4_GPIO_Seg7_Digit0_n*] 13 | set_false_path -to [get_ports DE4_GPIO_Seg7_Digit1_n*] 14 | } 15 | -------------------------------------------------------------------------------- /board/VC707/USB_UART.ucf: -------------------------------------------------------------------------------- 1 | ## USB UART 2 | ## ============================================================================= 3 | ## Bank: 13 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: U44 6 | ## Vendor: 7 | ## Device: 8 | NET "VC707_USB_UART_RX" LOC = "AU36"; ## 9 | NET "VC707_USB_UART_RTS_n" LOC = "AT32"; ## 10 | NET "VC707_USB_UART_TX" LOC = "AU33"; ## 11 | NET "VC707_USB_UART_CTS_n" LOC = "AR34"; ## 12 | NET "VC707_USB_UART_*" IOSTANDARD = LVCMOS18; 13 | 14 | ## Ignore timings on async I/O pins 15 | NET "VC707_USB_UART_*" TIG; 16 | -------------------------------------------------------------------------------- /board/ML505/Clock.UserClock.ucf: -------------------------------------------------------------------------------- 1 | ## User Clock 2 | ## ============================================================================= 3 | ## Bank: 4 4 | ## VCCO: 3.3V (VCC3V3) 5 | ## Location: X1; single-ended clock socket 6 | ## Oscillator: 100 MHz 7 | ## Vendor: 8 | ## Device: 9 | ## Frequency: 100.0 MHz 10 | NET "ML505_UserClock" LOC = "AH15"; ## {IN} X1.Out 11 | NET "ML505_UserClock" IOSTANDARD = LVCMOS33; 12 | ## 13 | NET "ML505_UserClock" TNM_NET = "TGRP_UserClock"; 14 | TIMESPEC "TS_UserClock" = PERIOD "TGRP_UserClock" 100 MHz HIGH 40 %; 15 | -------------------------------------------------------------------------------- /board/KC705/Bus.PMBus.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## PowerManagementBus (PMBus) 3 | ## ----------------------------------------------------------------------------- 4 | #$ ## Bank: 15 5 | #$ ## VCCO: 1,8V (VCC1V8_FPGA) 6 | #$ ## Location: 7 | #$ ## Vendor: 8 | #$ ## Device: 9 | #$ ##NET "KC705_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## 10 | #$ ##NET "KC705_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## 11 | #$ ##NET "KC705_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## 12 | 13 | ## Ignore timings on async I/O pins 14 | #$ NET "KC705_LCD_*" TIG; 15 | -------------------------------------------------------------------------------- /board/Atlys/Bus.IIC.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## I²C-Bus 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 0 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: JA (PMODA) 7 | ## ----------------------------------------------------------------------------- 8 | NET "Atlys_JA_SerialClock" LOC = "C13" | IOSTANDARD = LVCMOS33; ## {INOUT} JA - Pin 17 - SerialClock 9 | NET "Atlys_JA_SerialData" LOC = "A13" | IOSTANDARD = LVCMOS33; ## {INOUT} JA - Pin 18 - SerialData 10 | 11 | ## Ignore timings on async I/O pins 12 | NET "Atlys_JA_Serial*" TIG; 13 | -------------------------------------------------------------------------------- /board/ML505/Bus.PS2.Mouse.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## PS2-Bus - Mouse 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## ----------------------------------------------------------------------------- 7 | NET "ML505_PS2_Mouse_SerialClock" LOC = "R27"; ## external 4k7 pullup resistor 8 | NET "ML505_PS2_Mouse_SerialData" LOC = "U26"; ## external 4k7 pullup resistor 9 | NET "ML505_PS2_Mouse_*" IOSTANDARD = LVCMOS18; 10 | 11 | ## Ignore timings on async I/O pins 12 | NET "ML505_PS2_Mouse_*" TIG; 13 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/GPIO.Right.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> Right side of the board 5 | set_io --warn-no-port TinyFPGABX_PIN_14 H9 6 | set_io --warn-no-port TinyFPGABX_PIN_15 D9 7 | set_io --warn-no-port TinyFPGABX_PIN_16 D8 8 | set_io --warn-no-port TinyFPGABX_PIN_17 C9 9 | set_io --warn-no-port TinyFPGABX_PIN_18 A9 10 | set_io --warn-no-port TinyFPGABX_PIN_19 B8 11 | set_io --warn-no-port TinyFPGABX_PIN_20 A8 12 | set_io --warn-no-port TinyFPGABX_PIN_21 B7 13 | set_io --warn-no-port TinyFPGABX_PIN_22 A7 14 | set_io --warn-no-port TinyFPGABX_PIN_23 B6 15 | set_io --warn-no-port TinyFPGABX_PIN_24 A6 16 | -------------------------------------------------------------------------------- /doc/Data/Flash.rst: -------------------------------------------------------------------------------- 1 | .. _Data:Flash: 2 | 3 | Flash 4 | ##### 5 | 6 | * `litex-hub/litespi `__ 7 | * `LiteSPI Roadmap `__ 8 | * `mithro/HDMI2USB-litex-firmware: Adding module for Xilinx config stuff `__ 9 | * `ohwr.org/project/conv-ttl-blo-gw/wikis/xil-multiboot `__ 10 | -------------------------------------------------------------------------------- /board/ML505/Bus.PS2.Keyboard.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## PS2-Bus - Keyboard 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## ----------------------------------------------------------------------------- 7 | NET "ML505_PS2_Keyboard_SerialClock" LOC = "T26"; ## external 4k7 pullup resistor 8 | NET "ML505_PS2_Keyboard_SerialData" LOC = "T25"; ## external 4k7 pullup resistor 9 | NET "ML505_PS2_Keyboard_*" IOSTANDARD = LVCMOS18; 10 | 11 | ## Ignore timings on async I/O pins 12 | NET "ML505_PS2_Keyboard_*" TIG; 13 | -------------------------------------------------------------------------------- /board/ZedBoard/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================= 4 | ## Board: Xilinx - Zynq 7020 ZedBoard 5 | ## FPGA: Xilinx Zynq 7000 6 | ## Device: XC7Z020 7 | ## Package: CLG484 8 | ## Speedgrade: -1 9 | ## 10 | ## ============================================================================= 11 | ## Miscellaneous 12 | ## ============================================================================= 13 | CONFIG PART = XC7Z020-CLG484-1; 14 | -------------------------------------------------------------------------------- /board/ML505/GPIO.LED.Error.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 12 5 | ## VCCO: 3.3V (VCC1V8_FPGA) 6 | ## Location: DS5, DS6 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_LED_Error<0>" LOC = "F6"; ## DS6 9 | NET "ML505_GPIO_LED_Error<1>" LOC = "T10"; ## DS5 10 | NET "ML505_GPIO_LED_Error" IOSTANDARD = LVCMOS33; 11 | NET "ML505_GPIO_LED_Error" SLEW = SLOW; 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "ML505_GPIO_LED_Error" TIG; 15 | -------------------------------------------------------------------------------- /board/VC707/Transceiver.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 113 4 | ## ReferenceClock (see Transceiver.SMA_RefClock.ucf) 5 | 6 | ## SMA LVDS signal-pairs 7 | ## -------------------------- 8 | ## Bank: 113 9 | ## Location: P27, J28, J29, J30 10 | NET "VC707_SMA_TX_p" LOC = "AP4"; ## J29 11 | NET "VC707_SMA_TX_n" LOC = "AP3"; ## J30 12 | NET "VC707_SMA_RX_p" LOC = "AN6"; ## J27 13 | NET "VC707_SMA_RX_n" LOC = "AN5"; ## J28 14 | -------------------------------------------------------------------------------- /board/ZC706/Clock.ProgUserClock.ucf: -------------------------------------------------------------------------------- 1 | ## User Clock 2 | ## ----------------------------------------------------------------------------- 3 | ## Bank: 10 4 | ## VCCO: 2.5V (VADJ_FPGA) 5 | ## Location: U37 (SI570) 6 | ## Vendor: Silicon Labs 7 | ## Device: SI570BAB0000544DG 8 | ## Frequency: 10 - 810 MHz, 50ppm 9 | ## Default Freq: 156.250 MHz 10 | ## I²C-Address: 11 | NET "ZC706_ProgUserClock_p" LOC = "AF14" | IOSTANDARD = LVDS_25; ## {IN} U37.4 12 | NET "ZC706_ProgUserClock_n" LOC = "AG14" | IOSTANDARD = LVDS_25; ## {IN} U37.5 13 | NET "ZC706_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; 14 | -------------------------------------------------------------------------------- /.github/workflows/doc.yml: -------------------------------------------------------------------------------- 1 | name: Doc 2 | 3 | on: 4 | pull_request: 5 | push: 6 | schedule: 7 | - cron: '0 0 * * 4' 8 | workflow_dispatch: 9 | 10 | jobs: 11 | 12 | Doc: 13 | runs-on: ubuntu-latest 14 | name: 📓 Doc 15 | steps: 16 | 17 | - name: 🧰 Checkout 18 | uses: actions/checkout@v3 19 | 20 | - name: 📮 Clone openFPGALoader 21 | run: git clone https://github.com/trabucayre/openFPGALoader 22 | 23 | - name: 📓 Build The Docs 24 | uses: buildthedocs/btd@v0 25 | with: 26 | token: ${{ github.token }} 27 | skip-deploy: ${{ github.event_name == 'pull_request' }} 28 | -------------------------------------------------------------------------------- /board/ZC706/Clock.ProgUserClock.xdc: -------------------------------------------------------------------------------- 1 | ## User Clock 2 | ## ----------------------------------------------------------------------------- 3 | ## Bank: 10 4 | ## VCCO: 2.5V (VADJ_FPGA) 5 | ## Location: U37 (SI570) 6 | ## Vendor: Silicon Labs 7 | ## Device: SI570BAB0000544DG 8 | ## Frequency: 10 - 810 MHz, 50ppm 9 | ## Default Freq: 156.250 MHz 10 | ## I²C-Address: 11 | set_property PACKAGE_PIN AF14 [get_ports ZC706_ProgUserClock_p] 12 | set_property PACKAGE_PIN AG14 [get_ports ZC706_ProgUserClock_n] 13 | # set I/O standard 14 | set_property IOSTANDARD LVDS_25 [get_ports -regexp {ZC706_ProgUserClock_[p|n]}] 15 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/GPIO.Bottom.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> I/O (5V) 5 | # ------------------------------- ------------------------- 6 | # | x 5V R 3v3 5vP GND GND PWR | | DD0 DD1 DD2 DD3 DD4 DD5 | 7 | # ------------------------------- ------------------------- 8 | 9 | # Bottom 10 | set_io --warn-no-port IceZumAlhambraII_DD0 114 11 | set_io --warn-no-port IceZumAlhambraII_DD1 115 12 | set_io --warn-no-port IceZumAlhambraII_DD2 116 13 | set_io --warn-no-port IceZumAlhambraII_DD3 117 14 | set_io --warn-no-port IceZumAlhambraII_DD4 118 15 | set_io --warn-no-port IceZumAlhambraII_DD5 119 16 | -------------------------------------------------------------------------------- /board/ML505/Transceiver.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 3 4 | ## ReferenceClock (see Transceiver.SMA_RefClock.ucf) 5 | 6 | ## SMA LVDS signal-pairs 7 | ## -------------------------- 8 | ## Bank: 116 9 | ## LOC X0Y4 - GTP_DUAL port 1 10 | ## Location: P27, J28, J29, J30 11 | NET "ML505_SMA_TX_p" LOC = "L2"; ## J29 12 | NET "ML505_SMA_TX_n" LOC = "K2"; ## J30 13 | NET "ML505_SMA_RX_p" LOC = "K1"; ## J27 14 | NET "ML505_SMA_RX_n" LOC = "J1"; ## J28 15 | -------------------------------------------------------------------------------- /board/VC707/Clock.ProgUserClock.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## User Clock 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14 5 | ## VCCO: 1.8V (VCC1V8_FPGA) 6 | ## Location: U34 (SI570) 7 | ## Vendor: Silicon Labs 8 | ## Device: SI570BAB0000544DG 9 | ## Frequency: 10 - 810 MHz, 50ppm 10 | ## Default Freq: 156.250 MHz 11 | ## I²C-Address: 0x5D #$ (0111 010xb) 12 | NET "VC707_ProgUserClock_p" LOC = "AK34" | IOSTANDARD = LVDS; ## {IN} U34.4 13 | NET "VC707_ProgUserClock_n" LOC = "AL34" | IOSTANDARD = LVDS; ## {IN} U34.5 14 | NET "VC707_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; 15 | -------------------------------------------------------------------------------- /board/VC707/FanControl.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Fan Control 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: J48, Q1 7 | ## ----------------------------------------------------------------------------- 8 | NET "VC707_FanControl_PWM" LOC = "BA37"; ## Q1.Gate; external 1k pullup resistor 9 | NET "VC707_FanControl_Tacho" LOC = "BB37"; ## J48 - Pin 3; voltage limited by D2 (DDZ9678 - 1.8V zener-diode) 10 | NET "VC707_FanControl_*" IOSTANDARD = LVCMOS18; 11 | 12 | ## Ignore timings on async I/O pins 13 | NET "VC707_FanControl_*" TIG; 14 | -------------------------------------------------------------------------------- /doc/Contributing.rst: -------------------------------------------------------------------------------- 1 | Contributing 2 | ============ 3 | 4 | Should you find something wrong, missing or outdated; or if you miss your favourite board/device, you are welcome to 5 | contribute! 6 | Check the `open issues and pull request `__. 7 | If no one is working on it, let us know and go ahead according to the rules explained in :ref:`Structure`. 8 | 9 | Future work 10 | ----------- 11 | 12 | * Define constraints in YAML files. 13 | * Write generators that export the content to vendor specific formats. 14 | * Write importers that read existing vendor specific constraint files and generate a YAML file. 15 | -------------------------------------------------------------------------------- /board/VC707/Clock.ProgUserClock.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## User Clock 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14 5 | ## VCCO: 1.8V (VCC1V8_FPGA) 6 | ## Location: U34 (SI570) 7 | ## Vendor: Silicon Labs 8 | ## Device: SI570BAB0000544DG 9 | ## Frequency: 10 - 810 MHz, 50ppm 10 | ## Default Freq: 156.250 MHz 11 | ## I²C-Address: 0x5D #$ (0111 010xb) 12 | set_property PACKAGE_PIN AK34 [get_ports VC707_ProgUserClock_p] 13 | set_property PACKAGE_PIN AL34 [get_ports VC707_ProgUserClock_n] 14 | # set I/O standard 15 | set_property IOSTANDARD LVDS [get_ports -regexp {VC707_ProgUserClock_[p|n]}] 16 | -------------------------------------------------------------------------------- /board/IceStick/PMOD.pcf: -------------------------------------------------------------------------------- 1 | #| iCEstick 2 | 3 | 4 | #> PMOD 5 | # ------ --------- 6 | # | 12 6 | | 3V3 3V3 | 7 | # | 11 5 | | GND GND | 8 | # | 10 4 | | 91 81 | 9 | # | 9 3 | | 90 80 | 10 | # | 8 2 | | 88 79 | 11 | # | 7 1 | < | 87 78 | < 12 | # ------ --------- 13 | 14 | set_io --warn-no-port IceStick_PMOD1 78 15 | set_io --warn-no-port IceStick_PMOD2 79 16 | set_io --warn-no-port IceStick_PMOD3 80 17 | set_io --warn-no-port IceStick_PMOD4 81 18 | set_io --warn-no-port IceStick_PMOD7 87 19 | set_io --warn-no-port IceStick_PMOD8 88 20 | set_io --warn-no-port IceStick_PMOD9 90 21 | set_io --warn-no-port IceStick_PMOD10 91 22 | -------------------------------------------------------------------------------- /board/Atlys/USB_UART.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 0 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC7 7 | ## Vendor: EXAR 8 | ## Device: XR21V1410L16 9 | ## Baud-Rate: 300 Bd - 12 MBd 10 | ## Note: FPGA is the master, USB-UART is the slave => so TX is an output and RX an input 11 | NET "Atlys_USB_UART_TX" LOC = "A16" ; ## {IN} IC7.9 {OUT} 12 | NET "Atlys_USB_UART_RX" LOC = "B16" ; ## {OUT} IC7.10 {IN} 13 | NET "Atlys_USB_UART_?X" IOSTANDARD = LVCMOS33; 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "Atlys_USB_UART_?X" TIG; 17 | -------------------------------------------------------------------------------- /board/TinyFPGA-BX/GPIO.Left.pcf: -------------------------------------------------------------------------------- 1 | #| TinyFPGA-BX 2 | 3 | 4 | #> Left side of the board 5 | set_io --warn-no-port TinyFPGABX_PIN_1 A2 6 | set_io --warn-no-port TinyFPGABX_PIN_2 A1 7 | set_io --warn-no-port TinyFPGABX_PIN_3 B1 8 | set_io --warn-no-port TinyFPGABX_PIN_4 C2 9 | set_io --warn-no-port TinyFPGABX_PIN_5 C1 10 | set_io --warn-no-port TinyFPGABX_PIN_6 D2 11 | set_io --warn-no-port TinyFPGABX_PIN_7 D1 12 | set_io --warn-no-port TinyFPGABX_PIN_8 E2 13 | set_io --warn-no-port TinyFPGABX_PIN_9 E1 14 | set_io --warn-no-port TinyFPGABX_PIN_10 G2 15 | set_io --warn-no-port TinyFPGABX_PIN_11 H1 16 | set_io --warn-no-port TinyFPGABX_PIN_12 J1 17 | set_io --warn-no-port TinyFPGABX_PIN_13 H2 18 | -------------------------------------------------------------------------------- /board/ML505/Bus.IIC.Monitor.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## I2C-MonitorBus 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## ----------------------------------------------------------------------------- 7 | ## Devices: ?? 8 | ## Location: 9 | ## Vendor: 10 | ## Device: 11 | ## I²C-Address: 12 | NET "ML505_IIC_Monitor_SerialClock" LOC = "U27"; ## 13 | NET "ML505_IIC_Monitor_SerialData" LOC = "T29"; ## 14 | NET "ML505_IIC_Monitor_*" PULLUP; 15 | NET "ML505_IIC_Monitor_*" IOSTANDARD = LVCMOS18; 16 | 17 | ## Ignore timings on async I/O pins 18 | NET "ML505_IIC_Monitor_*" TIG; 19 | -------------------------------------------------------------------------------- /board/iCE40CW312/constraints.pcf: -------------------------------------------------------------------------------- 1 | #| iCE40CW312 2 | 3 | set_io --warn-no-port iCE40CW312_CLK B3 4 | 5 | #> UART 6 | set_io --warn-no-port iCE40CW312_TX E5 7 | set_io --warn-no-port iCE40CW312_RX D5 8 | 9 | 10 | #> SPI [user port] 11 | set_io --warn-no-port iCE40CW312_SPI_SDO F1 12 | set_io --warn-no-port iCE40CW312_SPI_SCK D1 13 | set_io --warn-no-port iCE40CW312_SPI_CSN C1 14 | set_io --warn-no-port iCE40CW312_SPI_SDI E1 15 | 16 | 17 | #> GPIO [input] 18 | set_io --warn-no-port iCE40CW312_GPIO_I[0] A5 19 | set_io --warn-no-port iCE40CW312_GPIO_I[1] A1 20 | 21 | 22 | #> GPIO [output] 23 | set_io --warn-no-port iCE40CW312_GPIO_O[0] A5 24 | set_io --warn-no-port iCE40CW312_GPIO_O[1] A1 25 | 26 | 27 | -------------------------------------------------------------------------------- /board/DE4/Clock.SystemClock.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Clocks 3 | ## ============================================================================= 4 | ## 5 | ## System Clock 6 | ## ============================================================================= 7 | ## Bank: 8 | ## VCCO: 9 | ## Location: 10 | ## Vendor: 11 | ## Device: 12 | ## Frequency: 100 MHz 13 | if {$TimingConstraints == 0} then { 14 | # is it possible to define pin and I/O standard constraints here? 15 | } else { 16 | ## specify a 100 MHz clock 17 | create_clock -name PIN_SystemClock_100MHz -period 10.000 -waveform {0.000 5.000} [get_ports DE4_SystemClock_100MHz] 18 | } 19 | -------------------------------------------------------------------------------- /board/ML505/Clock.SystemClock.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## System Clock 3 | ## ============================================================================= 4 | ## Bank: 3 5 | ## VCCO: 2.5V (VCC2V5) 6 | ## Location: U8 (IDT5V9885) 7 | ## Vendor: IDT 8 | ## Device: IDT5V9885 9 | ## IIC-Address: 0x6A 10 | ## Frequency: 200 MHz 11 | NET "ML505_SystemClock_200MHz_p" LOC = "L19"; ## {IN} U8.OUT5_P_15 12 | NET "ML505_SystemClock_200MHz_n" LOC = "K19"; ## {IN} U8.OUT5_N_16 13 | NET "ML505_SystemClock_200MHz_?" IOSTANDARD = LVDS_25; 14 | ## 15 | NET "ML505_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; 16 | TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; 17 | -------------------------------------------------------------------------------- /board/ZC706/Clock.SMAClock.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Clock Sources 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## SMA Clock 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 9 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: J67, J68 10 | NET "ZC706_SMAClock_p" LOC = "AD18" | IOSTANDARD = LVDS_25; ## {INOUT} J67 11 | NET "ZC706_SMAClock_n" LOC = "AD19" | IOSTANDARD = LVDS_25; ## {INOUT} J68 12 | -------------------------------------------------------------------------------- /board/KC705/GPIO.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## GPIO SMA 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 12 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: J13, J14 10 | NET "KC705_GPIO_SMA_n" LOC = "Y24" | IOSTANDARD = LVDS_25; ## {INOUT} J14 11 | NET "KC705_GPIO_SMA_p" LOC = "Y23" | IOSTANDARD = LVDS_25; ## {INOUT} J13 12 | -------------------------------------------------------------------------------- /board/ZC706/Clock.SystemClock.ucf: -------------------------------------------------------------------------------- 1 | ## System Clock 2 | ## ----------------------------------------------------------------------------- 3 | ## Bank: 34 4 | ## VCCO: 2.5V (VCC2V5_FPGA) 5 | ## Location: U64 (SIT9102) 6 | ## Vendor: SiTime 7 | ## Device: SIT9102AI-243N25E200.0000 - 1 to 220 MHz High Performance Oscillator 8 | ## Frequency: 200 MHz, 50ppm 9 | NET "ZC706_SystemClock_200MHz_p" LOC = "H9"; ## {IN} U64.4 10 | NET "ZC706_SystemClock_200MHz_n" LOC = "G9"; ## {IN} U64.5 11 | NET "ZC706_SystemClock_200MHz_?" IOSTANDARD = LVDS; 12 | NET "ZC706_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; 13 | 14 | TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; 15 | -------------------------------------------------------------------------------- /board/KC705/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Transceiver - SMA interface 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 117 5 | ## Quad117: 6 | ## RefClock0 7 | ## RefClock1 KC705_SMA_RefClock 8 | ## Placement: 9 | ## SMA: Quad117.Channel0 (GTXE2_CHANNEL_X0Y8) 10 | ## Location: 11 | ## RefClock: J15, J16 12 | ## Lane: J17, J66, J19, J20 13 | ## 14 | ## reference clock 15 | ## -------------------------- 16 | NET "KC705_SMA_RefClock_n" LOC = "J7" | IOSTANDARD = LVDS; ## {IN} J15; external 0.01 uF decoupling capacitor 17 | NET "KC705_SMA_RefClock_p" LOC = "J8" | IOSTANDARD = LVDS; ## {IN} J16; external 0.01 uF decoupling capacitor 18 | -------------------------------------------------------------------------------- /board/VC707/GPIO.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## GPIO SMA 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 13 8 | ## VCCO: 1.8V (VCC1V8_FPGA) 9 | ## Location: J33, J34 10 | NET "VC707_GPIO_SMA_p" LOC = "AN31"; ## {INOUT} J33 11 | NET "VC707_GPIO_SMA_n" LOC = "AP31"; ## {INOUT} J34 12 | NET "VC707_GPIO_SMA_?" IOSTANDARD = LVDS; 13 | -------------------------------------------------------------------------------- /board/ZC706/Clock.SystemClock.xdc: -------------------------------------------------------------------------------- 1 | ## System Clock 2 | ## ----------------------------------------------------------------------------- 3 | ## Bank: 34 4 | ## VCCO: 2.5V (VCC2V5_FPGA) 5 | ## Location: U64 (SIT9102) 6 | ## Vendor: SiTime 7 | ## Device: SIT9102AI-243N25E200.0000 - 1 to 220 MHz High Performance Oscillator 8 | ## Frequency: 200 MHz, 50ppm 9 | set_property PACKAGE_PIN H9 [get_ports ZC706_SystemClock_200MHz_p] 10 | set_property PACKAGE_PIN G9 [get_ports ZC706_SystemClock_200MHz_n] 11 | # set I/O standard 12 | set_property IOSTANDARD LVDS [get_ports -regexp {ZC706_SystemClock_200MHz_[p|n]}] 13 | # specify a 200 MHz clock 14 | create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports ZC706_SystemClock_200MHz_p] 15 | -------------------------------------------------------------------------------- /board/ML505/GPIO.Rotary.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Rotary-Button 3 | ## ============================================================================= 4 | ## Bank: 17 5 | ## VCCO: 1,8V (VCC1V8) 6 | #$; Location: SW2 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_Rotary_Button" LOC = "AH29"; ## SW2.5; high-active; external 4k7 pulldown resistor 9 | NET "ML505_GPIO_Rotary_IncA" LOC = "AH30"; ## SW2.1; high-active; external 4k7 pulldown resistor 10 | NET "ML505_GPIO_Rotary_IncB" LOC = "AG30"; ## SW2.6; high-active; external 4k7 pulldown resistor 11 | NET "ML505_GPIO_Rotary_*" IOSTANDARD = LVCMOS18; 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "ML505_GPIO_Rotary_*" TIG; 15 | -------------------------------------------------------------------------------- /board/ECP5-EVN/constraints.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "clk" SITE "A10"; 2 | IOBUF PORT "clk" IO_TYPE=LVCMOS33; 3 | 4 | LOCATE COMP "rst" SITE "P4"; 5 | IOBUF PORT "rst" IO_TYPE=LVCMOS33; 6 | 7 | LOCATE COMP "uart0_txd" SITE "P3"; 8 | LOCATE COMP "uart0_rxd" SITE "P2"; 9 | 10 | IOBUF PORT "uart0_txd" IO_TYPE=LVCMOS33; 11 | IOBUF PORT "uart0_rxd" IO_TYPE=LVCMOS33; 12 | 13 | LOCATE COMP "debug_txd" SITE "K2"; 14 | LOCATE COMP "debug_rxd" SITE "A15"; 15 | 16 | IOBUF PORT "debug_txd" IO_TYPE=LVCMOS33; 17 | IOBUF PORT "debug_rxd" IO_TYPE=LVCMOS33; 18 | 19 | LOCATE COMP "led_a" SITE "A13"; 20 | LOCATE COMP "led_b" SITE "A12"; 21 | LOCATE COMP "led_c" SITE "B19"; 22 | 23 | IOBUF PORT "led_a" IO_TYPE=LVCMOS25; 24 | IOBUF PORT "led_b" IO_TYPE=LVCMOS25; 25 | IOBUF PORT "led_c" IO_TYPE=LVCMOS25; 26 | -------------------------------------------------------------------------------- /board/DE4/UART.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## UART (RS232) 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## Vendor: 8 | ## Device: 9 | ## ============================================================================= 10 | if {$TimingConstraints == 0} then { 11 | # is it possible to define pin and I/O standard constraints here? 12 | } else { 13 | # Ignore timings on async I/O pins 14 | set_false_path -to [get_ports DE4_UART_RS232_TX] 15 | set_false_path -from [get_ports DE4_UART_RS232_RX] 16 | set_false_path -to [get_ports DE4_UART_RS232_CTS] 17 | set_false_path -from [get_ports DE4_UART_RS232_RTS] 18 | } 19 | -------------------------------------------------------------------------------- /board/KC705/GPIO.SMA.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## GPIO SMA 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 12 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: J13, J14 10 | set_property PACKAGE_PIN Y23 [get_ports KC705_GPIO_SMA_p] 11 | set_property PACKAGE_PIN Y24 [get_ports KC705_GPIO_SMA_n] 12 | # set I/O standard 13 | set_property IOSTANDARD LVDS_25 [get_ports -regexp {KC705_GPIO_SMA_.}] 14 | -------------------------------------------------------------------------------- /board/ZedBoard/Clock.SystemClock.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Clock Sources 3 | ## ============================================================================= 4 | ## System Clock 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 13 7 | ## VCCO: 3.3V (VCC3V3) 8 | ## Location: IC17 (Fox Electronics FXO-HC53 SERIES 767-100-136) 9 | ## Vendor: Fox Electronics 10 | ## Device: 11 | ## Frequency: 100 MHz, 50ppm 12 | NET "ZED_SystemClock_100MHz" LOC = "Y9" | IOSTANDARD = LVCMOS33; ## {IN} IC17.3 13 | NET "ZED_SystemClock_100MHz" TNM_NET = "PIN_SystemClock_100MHz"; 14 | 15 | TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_100MHz" 100 MHz HIGH 50 %; 16 | -------------------------------------------------------------------------------- /board/AC701/info.md: -------------------------------------------------------------------------------- 1 | --- 2 | Label: AC701 3 | PartNumber: EK-A7-AC701-G 4 | Device: XC7A200T-2 5 | Package: FBG676C 6 | Documentation: 7 | "xilinx.com: Xilinx Artix-7 FPGA AC701 Evaluation Kit": https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html 8 | Description: Xilinx Artix-7 FPGA AC701 Evaluation Kit 9 | --- 10 | 11 | > *The Artix®-7 FPGA AC701 Evaluation Kit features the leading system performance per watt Artix-7 family to get you quickly prototyping for your cost sensitive applications. This includes all the basic components of hardware, design tools, IP, and pre-verified reference designs. This also features a targeted reference design enabling high-performance serial connectivity and advanced memory interfacing equipped with a full license for the Northwest Logic DMA engine.* 12 | -------------------------------------------------------------------------------- /board/VC707/GPIO.SMA.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## GPIO SMA 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 13 8 | ## VCCO: 1.8V (VCC1V8_FPGA) 9 | ## Location: J33, J34 10 | set_property PACKAGE_PIN AN31 [get_ports VC707_GPIO_SMA_p] 11 | set_property PACKAGE_PIN AP31 [get_ports VC707_GPIO_SMA_n] 12 | # set I/O standard 13 | set_property IOSTANDARD LVDS [get_ports -regexp {VC707_GPIO_SMA_.}] 14 | -------------------------------------------------------------------------------- /board/VC707/FanControl.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Fan Control 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: J48, Q1 7 | ## ----------------------------------------------------------------------------- 8 | ## Q1.Gate; external 1k pullup resistor 9 | set_property PACKAGE_PIN BA37 [get_ports VC707_FanControl_PWM] 10 | ## J48 - Pin 3; voltage limited by D2 (DDZ9678 - 1.8V zener-diode) 11 | set_property PACKAGE_PIN BB37 [get_ports VC707_FanControl_Tacho] 12 | # set I/O standard 13 | set_property IOSTANDARD LVCMOS18 [get_ports -regexp {VC707_FanControl_.*}] 14 | # Ignore timings on async I/O pins 15 | set_false_path -to [get_ports VC707_FanControl_PWM] 16 | set_false_path -from [get_ports VC707_FanControl_Tacho] 17 | -------------------------------------------------------------------------------- /board/DE4/Bus.IIC.EEPROM.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## I2C bus to EEPROM 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## Vendor: 8 | ## Device: 9 | ## ============================================================================= 10 | if {$TimingConstraints == 0} then { 11 | # is it possible to define pin and I/O standard constraints here? 12 | } else { 13 | # Ignore timings on async I/O pins 14 | set_false_path -from [get_ports DE4_IIC_EEPROM_SerialClock] 15 | set_false_path -to [get_ports DE4_IIC_EEPROM_SerialClock] 16 | set_false_path -from [get_ports DE4_IIC_EEPROM_SerialData] 17 | set_false_path -to [get_ports DE4_IIC_EEPROM_SerialData] 18 | } 19 | -------------------------------------------------------------------------------- /board/ML505/GPIO.LED.Cursor.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 2, 20 5 | ## VCCO: 3,3V (VCC1V8_FPGA) 6 | ## Location: DS20, DS21, DS22, DS23, DS24 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_LED_North" LOC = "AF13"; ## DS20 9 | NET "ML505_GPIO_LED_East" LOC = "AG23"; ## DS21 10 | NET "ML505_GPIO_LED_South" LOC = "AG12"; ## DS22 11 | NET "ML505_GPIO_LED_West" LOC = "AF23"; ## DS23 12 | NET "ML505_GPIO_LED_Center" LOC = "E8"; ## DS24 13 | NET "ML505_GPIO_LED_*" IOSTANDARD = LVCMOS18; 14 | NET "ML505_GPIO_LED_*" SLEW = SLOW; 15 | 16 | ## Ignore timings on async I/O pins 17 | NET "ML505_GPIO_LED_*" TIG; 18 | -------------------------------------------------------------------------------- /board/DE4/GPIO.Button.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Cursor Buttons 6 | ## ============================================================================= 7 | ## Bank: 8 | ## VCCO: 9 | ## Location: 10 | ## ----------------------------------------------------------------------------- 11 | if {$TimingConstraints == 0} then { 12 | # is it possible to define pin and I/O standard constraints here? 13 | } else { 14 | # Ignore timings on async I/O pins 15 | set_false_path -from [get_ports DE4_GPIO_Button_n*] 16 | } 17 | -------------------------------------------------------------------------------- /board/DE4/GPIO.DipSwitch.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## DIP-Switches 6 | ## ============================================================================= 7 | ## Bank: 8 | ## VCCO: 9 | ## Location: 10 | ## ----------------------------------------------------------------------------- 11 | if {$TimingConstraints == 0} then { 12 | # is it possible to define pin and I/O standard constraints here? 13 | } else { 14 | # Ignore timings on async I/O pins 15 | set_false_path -from [get_ports DE4_GPIO_DipSwitches_n*] 16 | } 17 | -------------------------------------------------------------------------------- /board/DE4/GPIO.SlideSwitch.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## DIP-Switches 6 | ## ============================================================================= 7 | ## Bank: 8 | ## VCCO: 9 | ## Location: 10 | ## ----------------------------------------------------------------------------- 11 | if {$TimingConstraints == 0} then { 12 | # is it possible to define pin and I/O standard constraints here? 13 | } else { 14 | # Ignore timings on async I/O pins 15 | set_false_path -from [get_ports DE4_GPIO_SlideSwitches*] 16 | } 17 | -------------------------------------------------------------------------------- /board/DE4/GPIO.Button.Special.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ============================================================================= 7 | ## Bank: 8 | ## VCCO: 9 | ## Location: 10 | ## ----------------------------------------------------------------------------- 11 | if {$TimingConstraints == 0} then { 12 | # is it possible to define pin and I/O standard constraints here? 13 | } else { 14 | # Ignore timings on async I/O pins 15 | set_false_path -from [get_ports DE4_GPIO_Button_Reset_n] 16 | } 17 | -------------------------------------------------------------------------------- /board/Arty-S7-50/USB_UART.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC9 7 | ## Vendor: FTDI 8 | ## Device: FT2232 9 | ## Baud-Rate: 300 Bd - 1 MBd 10 | ## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output 11 | ## {IN} {IN} 12 | set_property PACKAGE_PIN V12 [ get_ports ArtyS750_USB_UART_TX ] 13 | ## {OUT} {OUT} 14 | set_property PACKAGE_PIN R12 [ get_ports ArtyS750_USB_UART_RX ] 15 | # set I/O standard 16 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyS750_USB_UART_.*} ] 17 | # Ignore timings on async I/O pins 18 | set_false_path -from [ get_ports ArtyS750_USB_UART_TX ] 19 | set_false_path -to [ get_ports ArtyS750_USB_UART_RX ] 20 | -------------------------------------------------------------------------------- /board/Atlys/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 8 | ## VCCO: 3.3V (VCC3V3) 9 | ## Location: BTN1 10 | ## ----------------------------------------------------------------------------- 11 | NET "Atlys_GPIO_Button_Reset_n" LOC = "T15" | IOSTANDARD = LVCMOS33; ## {IN} BTN1; high-active; external 10k pullup resistor 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "Atlys_GPIO_Button_Reset_n" TIG; 15 | -------------------------------------------------------------------------------- /board/DE4/Bus.SMBus.sdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## System Management Bus (SMBus) 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## Vendor: 8 | ## Device: 9 | ## ============================================================================= 10 | if {$TimingConstraints == 0} then { 11 | # is it possible to define pin and I/O standard constraints here? 12 | } else { 13 | # Ignore timings on async I/O pins 14 | set_false_path -from [get_ports DE4_SMBus_SerialClock] 15 | set_false_path -to [get_ports DE4_SMBus_SerialClock] 16 | set_false_path -from [get_ports DE4_SMBus_SerialData] 17 | set_false_path -to [get_ports DE4_SMBus_SerialData] 18 | set_false_path -from [get_ports DE4_SMBus_Alert] 19 | } 20 | -------------------------------------------------------------------------------- /board/VC707/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ============================================================================= 7 | ## Bank: 15 8 | ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW8 10 | ## ----------------------------------------------------------------------------- 11 | NET "VC707_GPIO_Button_CPU_Reset" LOC = "AV40" | IOSTANDARD = LVCMOS18; ## high-active; external 4k7 pulldown resistor 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "VC707_GPIO_Button_CPU_Reset" TIG; 15 | -------------------------------------------------------------------------------- /doc/Attributes.rst: -------------------------------------------------------------------------------- 1 | HDL attributes/annotations 2 | ########################## 3 | 4 | Some tools/vendors support specifying implementation constraints through attributes/annotations in HDL sources. 5 | 6 | VHDL 7 | ==== 8 | 9 | * Timing 10 | 11 | * Specify SDC timing constraints inside a module 12 | * Setting cross-clock options 13 | * Disable optimizations like shiftregister extraction 14 | 15 | * Physical 16 | 17 | * Setting pin locations 18 | 19 | * Encoding 20 | 21 | * FSM encoding 22 | * Type/enum encoding 23 | 24 | * Disable renaming optimization so a wire can be used for debugging 25 | 26 | * Attach a logic analyzer 27 | 28 | * Translation hints 29 | 30 | * Setting memory styles (register, distributedRAM/LUTRAM, BlockRAM, UltraRAM, ...) 31 | 32 | Verilog 33 | ======= 34 | 35 | See :ref:`yosys-symbiflow-plugin `. 36 | -------------------------------------------------------------------------------- /board/Arty-A7-35T/USB_UART.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 16 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC8 7 | ## Vendor: FTDI 8 | ## Device: FT2232 9 | ## Baud-Rate: 300 Bd - 1 MBd 10 | ## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output 11 | ## {IN} {IN} 12 | set_property PACKAGE_PIN A9 [ get_ports ArtyA735T_USB_UART_TX ] 13 | ## {OUT} {OUT} 14 | set_property PACKAGE_PIN D10 [ get_ports ArtyA735T_USB_UART_RX ] 15 | # set I/O standard 16 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyA735T_USB_UART_.*} ] 17 | # Ignore timings on async I/O pins 18 | set_false_path -from [ get_ports ArtyA735T_USB_UART_TX ] 19 | set_false_path -to [ get_ports ArtyA735T_USB_UART_RX ] 20 | -------------------------------------------------------------------------------- /board/KC705/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 34 8 | ## VCCO: 1.5V (VCC1V5_FPGA) 9 | ## Location: SW7 10 | ## ----------------------------------------------------------------------------- 11 | NET "KC705_GPIO_Button_CPU_Reset" LOC = "AB7" | IOSTANDARD = LVCMOS15; ## {IN} SW7; high-active; external 4k7 pulldown resistor 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "KC705_GPIO_Button_CPU_Reset" TIG; 15 | -------------------------------------------------------------------------------- /board/ZC706/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 34 8 | ## VCCO: 1.5V (VCC1V5_FPGA) 9 | ## Location: SW13 10 | ## ----------------------------------------------------------------------------- 11 | NET "ZC706_GPIO_Button_CPU_Reset" LOC = "A8" | IOSTANDARD = LVCMOS15; ## {IN} SW13; high-active; external 1k pulldown resistor 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "ZC706_GPIO_Button_CPU_Reset" TIG; 15 | -------------------------------------------------------------------------------- /board/KC705/USB_UART.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 15 5 | ## VCCO: 2.5V (VCC2V5_FPGA) 6 | ## Location: U12 7 | ## Vendor: Silicon Labs 8 | ## Device: CP2103-GM 9 | ## Baud-Rate: 300 Bd - 1 MBd 10 | ## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output 11 | NET "KC705_USB_UART_TX" LOC = "M19"; ## {IN} U34.25 {OUT} 12 | NET "KC705_USB_UART_RX" LOC = "K24"; ## {OUT} U34.24 {IN} 13 | NET "KC705_USB_UART_RTS_n" LOC = "K23"; ## {IN} U34.23 {OUT} Ready to Transmit (USB-UART has new data) 14 | NET "KC705_USB_UART_CTS_n" LOC = "L27"; ## {OUT} U34.22 {IN} Clear to Send (FPGA is able to receive data) 15 | NET "KC705_USB_UART_*" IOSTANDARD = LVCMOS25; 16 | 17 | # Ignore timings on async I/O pins 18 | NET "KC705_USB_UART_*" TIG; 19 | -------------------------------------------------------------------------------- /board/KC705/Transceiver.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Transceiver - SMA interface 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 117 5 | ## Quad117: 6 | ## RefClock0 7 | ## RefClock1 KC705_SMA_RefClock (see separate file "Transceiver.SMA_RefClock.ucf) 8 | ## 9 | ## Placement: 10 | ## SMA: Quad117.Channel0 (GTXE2_CHANNEL_X0Y8) 11 | ## Location: 12 | ## RefClock: J15, J16 13 | ## Lane: J17, J66, J19, J20 14 | ## 15 | ## SMA LVDS signal-pairs 16 | ## -------------------------- 17 | NET "KC705_SMA_TX_n" LOC = "K1"; ## {OUT} J20 18 | NET "KC705_SMA_TX_p" LOC = "K2"; ## {OUT} J19 19 | NET "KC705_SMA_RX_n" LOC = "K5"; ## {IN} J66; external 0.01 uF decoupling capacitor 20 | NET "KC705_SMA_RX_p" LOC = "K6"; ## {IN} J17; external 0.01 uF decoupling capacitor 21 | -------------------------------------------------------------------------------- /board/ML505/UART.ucf: -------------------------------------------------------------------------------- 1 | ## UART - Universal Asynchronous Receiver Transmitter 2 | ## ============================================================================= 3 | ## Bank: 4, 20 4 | ## VCCO: 3.3V (VCC3V3_FPGA) 5 | ## Location: U13 (ADM3202ARUZ) 6 | ## Vendor: Analog Devices 7 | ## Device: ADM3202 - Low Power, 3.3 V, RS-232 Line Driver/Receiver 8 | ## Baud-Rate: up to 460 kBaud 9 | ## Note: FPGA is the master => so TX is an output and RX an input 10 | NET "ML505_UART1_TX" LOC = "AG20"; ## {OUT} U13.10 {IN} 11 | NET "ML505_UART1_RX" LOC = "AG15"; ## {IN} U13.9 {OUT} 12 | NET "ML505_UART2_TX" LOC = "F10"; ## {OUT} U13.11 {IN} 13 | NET "ML505_UART2_RX" LOC = "G10"; ## {IN} U13.12 {OUT} 14 | NET "ML505_UART?_?X" IOSTANDARD = LVCMOS33; 15 | NET "ML505_UART?_?X" SLEW = FAST; 16 | 17 | ## Ignore timings on async I/O pins 18 | NET "ML505_UART?_?X" TIG; 19 | -------------------------------------------------------------------------------- /board/ML605/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Virtex 6 ML605 5 | ## FPGA: Xilinx Virtex 6 6 | ## Device: XC6VLX240T 7 | ## Package: FF1156 8 | ## Speedgrade: -1 9 | ## ============================================================================================================================================================= 10 | ## Miscellaneous 11 | ## ============================================================================================================================================================= 12 | CONFIG PART = XC6VLX240TFF1156-1; 13 | -------------------------------------------------------------------------------- /board/Fomu-PVT/constraints.pcf: -------------------------------------------------------------------------------- 1 | #| Fomu-PVT 2 | 3 | 4 | #> Clock (48 MHz) 5 | set_io --warn-no-port FomuPVT_CLK F4 6 | 7 | 8 | #> Tri-colour LED 9 | set_io --warn-no-port FomuPVT_RGB0 A5 10 | set_io --warn-no-port FomuPVT_RGB1 B5 11 | set_io --warn-no-port FomuPVT_RGB2 C5 12 | 13 | 14 | #> Buttons 15 | set_io --warn-no-port FomuPVT_USER1 E4 16 | set_io --warn-no-port FomuPVT_USER2 D5 17 | set_io --warn-no-port FomuPVT_USER3 E5 18 | set_io --warn-no-port FomuPVT_USER4 F5 19 | 20 | 21 | #> SPI 22 | set_io --warn-no-port FomuPVT_SPI_MOSI F1 23 | set_io --warn-no-port FomuPVT_SPI_MISO E1 24 | set_io --warn-no-port FomuPVT_SPI_CLK D1 25 | set_io --warn-no-port FomuPVT_SPI_IO2 F2 26 | set_io --warn-no-port FomuPVT_SPI_IO3 B1 27 | set_io --warn-no-port FomuPVT_SPI_cs C1 28 | 29 | 30 | #> USB 31 | set_io --warn-no-port FomuPVT_USB_DN A2 32 | set_io --warn-no-port FomuPVT_USB_DP A1 33 | set_io --warn-no-port FomuPVT_USB_DP_PU A4 34 | -------------------------------------------------------------------------------- /board/VC707/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Virtex 7 VC707 5 | ## FPGA: Xilinx Virtex 7 6 | ## Device: XC7VX485T 7 | ## Package: FFG1761 8 | ## Speedgrade: -2 9 | 10 | ## ============================================================================================================================================================= 11 | ## Miscellaneous 12 | ## ============================================================================================================================================================= 13 | CONFIG PART = XC7VX485T-FFG1761-2; 14 | -------------------------------------------------------------------------------- /board/VC707/GPIO.LED.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9 7 | ## ----------------------------------------------------------------------------- 8 | NET "VC707_GPIO_LED<0>" LOC = "AM39"; ## DS2 9 | NET "VC707_GPIO_LED<1>" LOC = "AN39"; ## DS3 10 | NET "VC707_GPIO_LED<2>" LOC = "AR37"; ## DS4 11 | NET "VC707_GPIO_LED<3>" LOC = "AT37"; ## DS5 12 | NET "VC707_GPIO_LED<4>" LOC = "AR35"; ## DS6 13 | NET "VC707_GPIO_LED<5>" LOC = "AP41"; ## DS7 14 | NET "VC707_GPIO_LED<6>" LOC = "AP42"; ## DS8 15 | NET "VC707_GPIO_LED<7>" LOC = "AU39"; ## DS9 16 | NET "VC707_GPIO_LED" IOSTANDARD = LVCMOS18; 17 | 18 | ## Ignore timings on async I/O pins 19 | NET "VC707_GPIO_LED" TIG; 20 | -------------------------------------------------------------------------------- /board/VC707/USB_UART.xdc: -------------------------------------------------------------------------------- 1 | ## USB UART 2 | ## ============================================================================= 3 | ## Bank: 13 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: U44 6 | ## Vendor: 7 | ## Device: 8 | ## {IN} 9 | set_property PACKAGE_PIN AU33 [get_ports VC707_USB_UART_TX] 10 | ## {OUT} 11 | set_property PACKAGE_PIN AU36 [get_ports VC707_USB_UART_RX] 12 | ## {IN} 13 | set_property PACKAGE_PIN AT32 [get_ports VC707_USB_UART_RTS_n] 14 | ## {OUT} 15 | set_property PACKAGE_PIN AR34 [get_ports VC707_USB_UART_CTS_n] 16 | # set I/O standard 17 | set_property IOSTANDARD LVCMOS18 [get_ports -regexp {VC707_USB_UART_.*}] 18 | # Ignore timings on async I/O pins 19 | set_false_path -from [get_ports VC707_USB_UART_TX] 20 | set_false_path -to [get_ports VC707_USB_UART_RX] 21 | set_false_path -from [get_ports VC707_USB_UART_RTS_n] 22 | set_false_path -to [get_ports VC707_USB_UART_CTS_n] 23 | -------------------------------------------------------------------------------- /board/ML505/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Virtex 5 ML505 5 | ## FPGA: Xilinx Virtex 5 6 | ## Device: XC5VLX50T 7 | ## Package: FF1136 8 | ## Speedgrade: -1 9 | ## ============================================================================================================================================================= 10 | ## Miscellaneous 11 | ## ============================================================================================================================================================= 12 | CONFIG PART = XC5VLX50T-FFG1136-1; 13 | CONFIG STEPPING = "ES"; 14 | -------------------------------------------------------------------------------- /board/ZC706/Transceiver.SFP.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Transceiver - SFP interface 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 9, 111 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0 8 | ## RefClock1 ZC706_SMA_RefClock 9 | ## Placement: 10 | ## SFP: Quad??.Channel2 (GTXE2_CHANNEL_X??Y??) 11 | ## Location: P2 12 | ## I²C-Address: 13 | NET "ZC706_SFP_TX_Disable_n" LOC = "AA18" | IOSTANDARD = LVCMOS25; ## ; low-active; external 4k7 pullup resistor; level shifted by Q4 (NDS331N) 14 | ## 15 | ## -------------------------- 16 | ## SFP+ LVDS signal-pairs 17 | NET "ZC706_SFP_TX_p" LOC = "W4"; ## {OUT} 18 | NET "ZC706_SFP_TX_n" LOC = "W3"; ## {OUT} 19 | NET "ZC706_SFP_RX_p" LOC = "Y6"; ## {IN} 20 | NET "ZC706_SFP_RX_n" LOC = "Y5"; ## {IN} 21 | 22 | # Ignore timings on async I/O pins 23 | NET "ZC706_SFP_TX_Disable_n" TIG; 24 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.GPIO.LED.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## General Purpose I/O - LED 5 | ## ----------------------------------------------------------------------------- 6 | ## {OUT} D1; LA19_n 7 | set_property PACKAGE_PIN F18 [ get_ports KC705_FMC_HPC_GPIO_LED[0] ] 8 | ## {OUT} D2; LA19_p 9 | set_property PACKAGE_PIN G18 [ get_ports KC705_FMC_HPC_GPIO_LED[1] ] 10 | ## {OUT} D3; LA18_n 11 | set_property PACKAGE_PIN E21 [ get_ports KC705_FMC_HPC_GPIO_LED[2] ] 12 | ## {OUT} D4; LA18_p 13 | set_property PACKAGE_PIN F21 [ get_ports KC705_FMC_HPC_GPIO_LED[3] ] 14 | # set I/O standard 15 | set_property IOSTANDARD LVCMOS25 [ get_ports -regexp {KC705_FMC_HPC_GPIO_LED\[[0-3]]} ] 16 | # Ignore timings on async I/O pins 17 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_GPIO_LED\[\d\]} ] 18 | 19 | -------------------------------------------------------------------------------- /board/ML505/Bus.IIC.Main.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## I2C-MainBus 3 | ## ============================================================================= 4 | ## Bank: 20 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## ----------------------------------------------------------------------------- 7 | ## Devices: ?? 8 | ## Location: U15 9 | ## Vendor: STMicroelectronics 10 | ## Device: M24C08 11 | ## I²C-Address: 0x50 12 | ## Location: U8 13 | ## Vendor: Integrated Device Technology 14 | ## Device: IDT5V9885 15 | ## I²C-Address: 0x6A 16 | ## Location: U14 17 | ## Vendor: Analog Devices 18 | ## Device: ADT7476 19 | ## I²C-Address: 0x2C 20 | NET "ML505_IIC_Main_SerialClock" LOC = "F9"; ## 2x external 10k pullup resistors 21 | NET "ML505_IIC_Main_SerialData" LOC = "F8"; ## 2x external 10k pullup resistors 22 | NET "ML505_IIC_Main_*" IOSTANDARD = LVCMOS33; 23 | 24 | ## Ignore timings on async I/O pins 25 | NET "ML505_IIC_Main_*" TIG; 26 | -------------------------------------------------------------------------------- /board/ML505/EthernetPHY.SGMII.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## SGMII LVDS signal-pairs 3 | ## -------------------------- 4 | ## Bank: 112 5 | ## Transceiver: 6 | ## Location: X0Y3 - Port 0 7 | ## Device: Ethernet PHY 8 | ## Location: U16 (M88E1111) 9 | ## Vendor: Marvel 10 | ## Device: M88E1111 11 | ## ReferenceClock 12 | ## Location: U29 (ICS844021I_TSSOP8) 13 | ## Vendor: Integrated Device Technology 14 | ## Device: ICS844021I 15 | ## Frequency: 125 MHz 16 | NET "ML505_EthernetPHY_RefClock_125MHz_n" LOC = "P3"; ## {IN} U29.NQ0 17 | NET "ML505_EthernetPHY_RefClock_125MHz_p" LOC = "P4"; ## {IN} U29.Q0 18 | NET "ML505_EthernetPHY_SGMII_TX_p" LOC = "M2"; ## {OUT} U16.113 19 | NET "ML505_EthernetPHY_SGMII_TX_n" LOC = "N2"; ## {OUT} U16.112 20 | NET "ML505_EthernetPHY_SGMII_RX_p" LOC = "N1"; ## {IN} U16.107 21 | NET "ML505_EthernetPHY_SGMII_RX_n" LOC = "P1"; ## {IN} U16.105 22 | -------------------------------------------------------------------------------- /board/VC707/GPIO.Button.Special.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ============================================================================= 7 | ## Bank: 15 8 | ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW8 10 | ## ----------------------------------------------------------------------------- 11 | ## high-active; external 4k7 pulldown resistor 12 | set_property PACKAGE_PIN AV40 [get_ports VC707_GPIO_Button_CPU_Reset] 13 | # set I/O standard 14 | set_property IOSTANDARD LVCMOS18 [get_ports VC707_GPIO_Button_CPU_Reset] 15 | # Ignore timings on async I/O pins 16 | set_false_path -from [get_ports VC707_GPIO_Button_CPU_Reset] 17 | -------------------------------------------------------------------------------- /board/AC701/GPIO.Button.Special.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 34 8 | ## VCCO: 1.5V (FPGA_1V5) 9 | ## Location: SW8 10 | ## ----------------------------------------------------------------------------- 11 | ## {IN} SW8; high-active; external 4k7 pulldown resistor 12 | set_property PACKAGE_PIN U4 [get_ports AC701_GPIO_Button_CPU_Reset] 13 | # set I/O standard 14 | set_property IOSTANDARD LVCMOS15 [get_ports AC701_GPIO_Button_CPU_Reset] 15 | # Ignore timings on async I/O pins 16 | set_false_path -from [get_ports AC701_GPIO_Button_CPU_Reset] 17 | -------------------------------------------------------------------------------- /board/KC705/GPIO.Button.Special.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 34 8 | ## VCCO: 1.5V (VCC1V5_FPGA) 9 | ## Location: SW7 10 | ## ----------------------------------------------------------------------------- 11 | ## {IN} SW7; high-active; external 4k7 pulldown resistor 12 | set_property PACKAGE_PIN AB7 [get_ports KC705_GPIO_Button_CPU_Reset] 13 | # set I/O standard 14 | set_property IOSTANDARD LVCMOS15 [get_ports KC705_GPIO_Button_CPU_Reset] 15 | # Ignore timings on async I/O pins 16 | set_false_path -from [get_ports KC705_GPIO_Button_CPU_Reset] 17 | -------------------------------------------------------------------------------- /board/ZC706/GPIO.Button.Special.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 34 8 | ## VCCO: 1.5V (VCC1V5_FPGA) 9 | ## Location: SW13 10 | ## ----------------------------------------------------------------------------- 11 | ## {IN} SW13; high-active; external 1k pulldown resistor 12 | set_property PACKAGE_PIN A8 [get_ports ZC706_GPIO_Button_CPU_Reset] 13 | # set I/O standard 14 | set_property IOSTANDARD LVCMOS15 [get_ports ZC706_GPIO_Button_CPU_Reset] 15 | # Ignore timings on async I/O pins 16 | set_false_path -from [get_ports ZC706_GPIO_Button_CPU_Reset] 17 | -------------------------------------------------------------------------------- /board/Arty-S7-50/GPIO.Button.Special.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 35 8 | ## VCCO: 3.3V (VCC3V3) 9 | ## Location: BTNR 10 | ## ----------------------------------------------------------------------------- 11 | ## {IN} BTNR; low-active; external 10k pullup resistor 12 | set_property PACKAGE_PIN C18 [ get_ports ArtyS750_GPIO_Button_CPU_Reset ] 13 | # set I/O standard 14 | set_property IOSTANDARD LVCMOS33 [ get_ports ArtyS750_GPIO_Button_CPU_Reset ] 15 | # Ignore timings on async I/O pins 16 | set_false_path -from [ get_ports ArtyS750_GPIO_Button_CPU_Reset ] 17 | -------------------------------------------------------------------------------- /board/Arty-A7-35T/GPIO.Button.Special.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Special Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 35 8 | ## VCCO: 3.3V (VCC3V3) 9 | ## Location: BTNR 10 | ## ----------------------------------------------------------------------------- 11 | ## {IN} BTNR; low-active; external 10k pullup resistor 12 | set_property PACKAGE_PIN C2 [ get_ports ArtyA735T_GPIO_Button_CPU_Reset ] 13 | # set I/O standard 14 | set_property IOSTANDARD LVCMOS33 [ get_ports ArtyA735T_GPIO_Button_CPU_Reset ] 15 | # Ignore timings on async I/O pins 16 | set_false_path -from [ get_ports ArtyA735T_GPIO_Button_CPU_Reset ] 17 | -------------------------------------------------------------------------------- /board/IceZumAlhambraII/GPIO.Top.pcf: -------------------------------------------------------------------------------- 1 | #| IceZUM Alhambra II 2 | 3 | 4 | #> I/O (5V) 5 | # -------------------------------------- ------------------------------- 6 | # | SCL SDA AR GND D13 D12 D11 D10 D9 D8 | | D7 D6 D5 D4 D3 D2 D1 D0 | 7 | # -------------------------------------- ------------------------------- 8 | 9 | # Top 10 | set_io --warn-no-port IceZumAlhambraII_D13 64 11 | set_io --warn-no-port IceZumAlhambraII_D12 63 12 | set_io --warn-no-port IceZumAlhambraII_D11 21 13 | set_io --warn-no-port IceZumAlhambraII_D10 22 14 | set_io --warn-no-port IceZumAlhambraII_D9 19 15 | set_io --warn-no-port IceZumAlhambraII_D8 20 16 | set_io --warn-no-port IceZumAlhambraII_D7 9 17 | set_io --warn-no-port IceZumAlhambraII_D6 10 18 | set_io --warn-no-port IceZumAlhambraII_D5 7 19 | set_io --warn-no-port IceZumAlhambraII_D4 8 20 | set_io --warn-no-port IceZumAlhambraII_D3 3 21 | set_io --warn-no-port IceZumAlhambraII_D2 4 22 | set_io --warn-no-port IceZumAlhambraII_D1 1 23 | set_io --warn-no-port IceZumAlhambraII_D0 2 24 | -------------------------------------------------------------------------------- /board/ZC706/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Zynq ZC706 5 | ## FPGA: Xilinx Zynq 7000 6 | ## Device: XC7Z045 7 | ## Package: FFG900 8 | ## Speedgrade: -2 9 | ## 10 | ## Notes: 11 | ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) 12 | ## 13 | ## ============================================================================================================================================================= 14 | ## Miscellaneous 15 | ## ============================================================================================================================================================= 16 | CONFIG PART = XC7Z045-FFG900-2; 17 | -------------------------------------------------------------------------------- /board/Atlys/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Digilent - Atlys - Spartan-6 LX45 5 | ## FPGA: Xilinx Spartan-6 6 | ## Device: XC6SLX45 7 | ## Package: CSG324 8 | ## Speedgrade: -3 9 | ## 10 | ## Notes: 11 | ## VCCB2 (Bank2) is defaulted to 2.5V (choices: 2.5V, 3.3V) by jumper JP12 12 | ## 13 | ## ============================================================================================================================================================= 14 | ## Miscellaneous 15 | ## ============================================================================================================================================================= 16 | CONFIG PART = XC6SLX45-CSG324-3; 17 | -------------------------------------------------------------------------------- /board/KC705/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Kintex 7 KC705 5 | ## FPGA: Xilinx Kintex 7 6 | ## Device: XC7K325T 7 | ## Package: FFG900 8 | ## Speedgrade: -2 9 | ## 10 | ## Notes: 11 | ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) 12 | ## 13 | ## ============================================================================================================================================================= 14 | ## Miscellaneous 15 | ## ============================================================================================================================================================= 16 | CONFIG PART = XC7K325T-FFG900-2; 17 | -------------------------------------------------------------------------------- /board/UPDuino-v3.0/constraints.pcf: -------------------------------------------------------------------------------- 1 | #| UPDuino-v3.0 2 | 3 | 4 | #> UART 5 | set_io UPDuinov30_TX 38 6 | set_io UPDuinov30_RX 28 7 | 8 | 9 | #> SPI [on-board flash] 10 | set_io UPDuinov30_FLASH_SDO 14 11 | set_io UPDuinov30_FLASH_SCK 15 12 | set_io UPDuinov30_FLASH_CSN 16 13 | set_io UPDuinov30_FLASH_SDI 17 14 | 15 | 16 | #> SPI [user port] 17 | set_io UPDuinov30_SPI_SDO 34 18 | set_io UPDuinov30_SPI_SCK 43 19 | set_io UPDuinov30_SPI_CSN 36 20 | set_io UPDuinov30_SPI_SDI 42 21 | 22 | 23 | #> TWI 24 | set_io UPDuinov30_TWI_SDA 31 25 | set_io UPDuinov30_TWI_SCL 37 26 | 27 | 28 | #> GPIO [input] 29 | set_io UPDuinov30_GPIO_I[0] 44 30 | set_io UPDuinov30_GPIO_I[1] 4 31 | set_io UPDuinov30_GPIO_I[2] 3 32 | set_io UPDuinov30_GPIO_I[3] 48 33 | 34 | 35 | #> GPIO [output] 36 | set_io UPDuinov30_GPIO_O[0] 45 37 | set_io UPDuinov30_GPIO_O[1] 47 38 | set_io UPDuinov30_GPIO_O[2] 46 39 | set_io UPDuinov30_GPIO_O[3] 2 40 | 41 | 42 | #> RGB power LED 43 | set_io UPDuinov30_LED_R 39 44 | set_io UPDuinov30_LED_G 40 45 | set_io UPDuinov30_LED_B 41 46 | -------------------------------------------------------------------------------- /board/Atlys/Clock.SystemClock.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Clock Sources 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## System Clock 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 1 8 | ## VCCO: 3.3V (VCC3V3) 9 | ## Location: IC12 (SG8002JF) 10 | ## Vendor: Seiko Epson 11 | ## Device: SG8002JF - Crystal Oscillator 1 to 125 MHz 12 | ## Frequency: 100 MHz, 100ppm 13 | NET "Atlys_SystemClock_100MHz" LOC = "L15"; ## {IN} IC12.3 14 | NET "Atlys_SystemClock_100MHz" IOSTANDARD = LVCMOS33; 15 | NET "Atlys_SystemClock_100MHz" TNM_NET = "PIN_SystemClock_100MHz"; 16 | 17 | TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_100MHz" 100 MHz HIGH 50 %; # 100 MHz oscillator (50%/50% duty-cycle) 18 | -------------------------------------------------------------------------------- /board/VC707/Clock.SystemClock.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Clocks 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## System Clock 6 | ## ============================================================================= 7 | ## Bank: 38 8 | ## VCCO: 1.5V (VCC1V5_FPGA) 9 | ## Location: U51 (SIT9102) 10 | ## Vendor: SiTime 11 | ## Device: SiT9102 - 1 to 220 MHz High Performance Oscillator 12 | ## Frequency: 200 MHz, 50ppm 13 | NET "VC707_SystemClock_200MHz_p" LOC = "E19"; ## U51.4 14 | NET "VC707_SystemClock_200MHz_n" LOC = "E18"; ## U51.5 15 | NET "VC707_SystemClock_200MHz_?" IOSTANDARD = LVDS; 16 | NET "VC707_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; 17 | 18 | TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; 19 | -------------------------------------------------------------------------------- /board/ZC706/FanControl.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Fan Control 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 9 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: J61, Q1 (NDT3055L) 10 | ## ----------------------------------------------------------------------------- 11 | NET "ZC706_FanControl_PWM" LOC = "AB19"; ## {OUT} Q1.Gate; external 1k pullup resistor; Q1.Drain connects to J61.1 (GND) 12 | NET "ZC706_FanControl_Tacho" LOC = "AA19"; ## {IN} J61.3; voltage limited by D2 (MM3Z2V7B; 2.7V zener-diode) 13 | NET "ZC706_FanControl_*" IOSTANDARD = LVCMOS25; 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "ZC706_FanControl_*" TIG; 17 | -------------------------------------------------------------------------------- /board/ZedBoard/GPIO.LED.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## General Purpose IO 3 | ## ============================================================================= 4 | ## LEDs 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 33 7 | ## VCCO: 3.3V (VCC3V3) 8 | ## Location: LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_GPIO_LED<0>" LOC = "T22"; ## {OUT} LD0 11 | NET "ZED_GPIO_LED<1>" LOC = "T21"; ## {OUT} LD1 12 | NET "ZED_GPIO_LED<2>" LOC = "U22"; ## {OUT} LD2 13 | NET "ZED_GPIO_LED<3>" LOC = "U21"; ## {OUT} LD3 14 | NET "ZED_GPIO_LED<4>" LOC = "V22"; ## {OUT} LD4 15 | NET "ZED_GPIO_LED<5>" LOC = "W22"; ## {OUT} LD5 16 | NET "ZED_GPIO_LED<6>" LOC = "U19"; ## {OUT} LD6 17 | NET "ZED_GPIO_LED<7>" LOC = "U14"; ## {OUT} LD7 18 | NET "ZED_GPIO_LED" IOSTANDARD = LVCMOS33; ## {OUT} LD7 19 | -------------------------------------------------------------------------------- /board/Atlys/EthernetPHY.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Ethernet PHY - Marvell Alaska Ultra 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 1 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC8 7 | ## Vendor: Marvell 8 | ## Device: M88E1111 - RCJ1 9 | ## MDIO-Address: 0x05 (---0 0111b) 10 | ## I2C-Address: I2C management mode is not enabled 11 | ## 12 | ## common signals and management 13 | ## -------------------------- 14 | NET "KC705_EthernetPHY_Reset_n" LOC = "G13" | IOSTANDARD = LVCMOS33; ## {IN} IC8.36 15 | NET "KC705_EthernetPHY_Interrupt_n" LOC = "L16" | IOSTANDARD = LVCMOS33; ## {IN} IC8.32 16 | NET "KC705_EthernetPHY_Management_Clock" LOC = "F16" | IOSTANDARD = LVCMOS33; ## {OUT} IC8.35 17 | NET "KC705_EthernetPHY_Management_Data" LOC = "N17" | IOSTANDARD = LVCMOS33; ## {INOUT} IC8.33 18 | 19 | ## Ignore timings on async I/O pins 20 | NET "KC705_EthernetPHY_Reset_n" TIG; 21 | NET "KC705_EthernetPHY_Interrupt_n" TIG; 22 | NET "KC705_EthernetPHY_Management_*" TIG; 23 | -------------------------------------------------------------------------------- /board/VC707/GPIO.LED.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9 7 | ## ----------------------------------------------------------------------------- 8 | set_property PACKAGE_PIN AM39 [get_ports VC707_GPIO_LED[0]] 9 | set_property PACKAGE_PIN AN39 [get_ports VC707_GPIO_LED[1]] 10 | set_property PACKAGE_PIN AR37 [get_ports VC707_GPIO_LED[2]] 11 | set_property PACKAGE_PIN AT37 [get_ports VC707_GPIO_LED[3]] 12 | set_property PACKAGE_PIN AR35 [get_ports VC707_GPIO_LED[4]] 13 | set_property PACKAGE_PIN AP41 [get_ports VC707_GPIO_LED[5]] 14 | set_property PACKAGE_PIN AP42 [get_ports VC707_GPIO_LED[6]] 15 | set_property PACKAGE_PIN AU39 [get_ports VC707_GPIO_LED[7]] 16 | # set I/O standard 17 | set_property IOSTANDARD LVCMOS18 [get_ports -regexp {VC707_GPIO_LED\[\d\]}] 18 | # Ignore timings on async I/O pins 19 | set_false_path -to [get_ports -regexp {VC707_GPIO_LED\[\d\]}] 20 | -------------------------------------------------------------------------------- /board/VC707/EthernetPHY.SGMII.ucf: -------------------------------------------------------------------------------- 1 | ## Ethernet PHY - Marvell Alaska Ultra 2 | ## ============================================================================= 3 | ## Bank: 14 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: U50 6 | ## Vendor: Marvell 7 | ## Device: M88E1111 - 8 | ## MDIO-Address: 0x05 (---0 0111b) 9 | ## I²C-Address: I²C management mode is not enabled 10 | ## 11 | ## SGMII LVDS signal-pairs 12 | ## -------------------------- 13 | ## Bank: 113 14 | ## ReferenceClock 15 | ## Location: U2 (ICS844021I_TSSOP8) 16 | ## Vendor: 17 | ## Device: ICS844021I 18 | ## Frequency: 125 MHz 19 | NET "VC707_EthernetPHY_RefClock_125MHz_n" LOC = "AH7"; ## 20 | NET "VC707_EthernetPHY_RefClock_125MHz_p" LOC = "AH8"; ## 21 | NET "VC707_EthernetPHY_SGMII_TX_n" LOC = "AN1"; ## 22 | NET "VC707_EthernetPHY_SGMII_TX_p" LOC = "AN2"; ## 23 | NET "VC707_EthernetPHY_SGMII_RX_n" LOC = "AM7"; ## 24 | NET "VC707_EthernetPHY_SGMII_RX_p" LOC = "AM8"; ## 25 | -------------------------------------------------------------------------------- /board/ZedBoard/PMOD.PortA.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Peripheral Modules (Pmods) 3 | ## ============================================================================= 4 | ## Pmod Port A (2x6 pins) 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 13 7 | ## VCCO: 3.3V (VCC3V3) 8 | ## Location: JA1 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_PMOD_PortA<0>" LOC = "Y11"; ## {IN} JA1.1 11 | NET "ZED_PMOD_PortA<1>" LOC = "AA11"; ## {IN} JA1.2 12 | NET "ZED_PMOD_PortA<2>" LOC = "Y10"; ## {IN} JA1.3 13 | NET "ZED_PMOD_PortA<3>" LOC = "AA9"; ## {IN} JA1.4 14 | NET "ZED_PMOD_PortA<4>" LOC = "AB11"; ## {IN} JA1.7 15 | NET "ZED_PMOD_PortA<5>" LOC = "AB10"; ## {IN} JA1.8 16 | NET "ZED_PMOD_PortA<6>" LOC = "AB9"; ## {IN} JA1.9 17 | NET "ZED_PMOD_PortA<7>" LOC = "AA8"; ## {IN} JA1.10 18 | NET "ZED_PMOD_PortA" IOSTANDARD = LVCMOS33; ## 19 | -------------------------------------------------------------------------------- /board/ZedBoard/PMOD.PortB.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Peripheral Modules (Pmods) 3 | ## ============================================================================= 4 | ## Pmod Port B (2x6 pins) 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 13 7 | ## VCCO: 3.3V (VCC3V3) 8 | ## Location: JB1 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_PMOD_PortB<0>" LOC = "W12"; ## {IN} JB1.1 11 | NET "ZED_PMOD_PortB<1>" LOC = "W11"; ## {IN} JB1.2 12 | NET "ZED_PMOD_PortB<2>" LOC = "V10"; ## {IN} JB1.3 13 | NET "ZED_PMOD_PortB<3>" LOC = "W8"; ## {IN} JB1.4 14 | NET "ZED_PMOD_PortB<4>" LOC = "V12"; ## {IN} JB1.7 15 | NET "ZED_PMOD_PortB<5>" LOC = "W10"; ## {IN} JB1.8 16 | NET "ZED_PMOD_PortB<6>" LOC = "V9"; ## {IN} JB1.9 17 | NET "ZED_PMOD_PortB<7>" LOC = "V8"; ## {IN} JB1.10 18 | NET "ZED_PMOD_PortB" IOSTANDARD = LVCMOS33; ## 19 | -------------------------------------------------------------------------------- /board/ZedBoard/PMOD.PortC.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Peripheral Modules (Pmods) 3 | ## ============================================================================= 4 | ## Pmod Port C (2x6 pins) 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 13 7 | ## VCCO: 3.3V (VCC3V3) 8 | ## Location: JC1 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_PMOD_PortC<0>" LOC = "AB6"; ## {IN} JC1.1 11 | NET "ZED_PMOD_PortC<1>" LOC = "AB7"; ## {IN} JC1.2 12 | NET "ZED_PMOD_PortC<2>" LOC = "AA4"; ## {IN} JC1.3 13 | NET "ZED_PMOD_PortC<3>" LOC = "Y4"; ## {IN} JC1.4 14 | NET "ZED_PMOD_PortC<4>" LOC = "T6"; ## {IN} JC1.7 15 | NET "ZED_PMOD_PortC<5>" LOC = "R6"; ## {IN} JC1.8 16 | NET "ZED_PMOD_PortC<6>" LOC = "U4"; ## {IN} JC1.9 17 | NET "ZED_PMOD_PortC<7>" LOC = "T4"; ## {IN} JC1.10 18 | NET "ZED_PMOD_PortC" IOSTANDARD = LVCMOS33; ## 19 | -------------------------------------------------------------------------------- /board/ZedBoard/PMOD.PortD.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Peripheral Modules (Pmods) 3 | ## ============================================================================= 4 | ## Pmod Port D (2x6 pins) 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 13 7 | ## VCCO: 3.3V (VCC3V3) 8 | ## Location: JD1 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_PMOD_PortD<0>" LOC = "W7"; ## {IN} JD1.1 11 | NET "ZED_PMOD_PortD<1>" LOC = "V7"; ## {IN} JD1.2 12 | NET "ZED_PMOD_PortD<2>" LOC = "V4"; ## {IN} JD1.3 13 | NET "ZED_PMOD_PortD<3>" LOC = "V5"; ## {IN} JD1.4 14 | NET "ZED_PMOD_PortD<4>" LOC = "W5"; ## {IN} JD1.7 15 | NET "ZED_PMOD_PortD<5>" LOC = "W6"; ## {IN} JD1.8 16 | NET "ZED_PMOD_PortD<6>" LOC = "U5"; ## {IN} JD1.9 17 | NET "ZED_PMOD_PortD<7>" LOC = "U6"; ## {IN} JD1.10 18 | NET "ZED_PMOD_PortD" IOSTANDARD = LVCMOS33; ## 19 | -------------------------------------------------------------------------------- /board/KC705/FanControl.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Fan Control 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 14, 15 8 | ## VCCO: 2.5V, 2.5V (VCC2V5_FPGA, VCC2V5_FPGA) 9 | ## Location: J61, Q17 (NDT3055L) 10 | ## ----------------------------------------------------------------------------- 11 | NET "KC705_FanControl_PWM" LOC = "L26"; ## {OUT} Q17.Gate; external 1k pullup resistor; Q17.Drain connects to J61.1 (GND) 12 | NET "KC705_FanControl_Tacho" LOC = "U22"; ## {IN} J61.3; voltage limited by D15 (MM3Z2V7B; 2.7V zener-diode) 13 | NET "KC705_FanControl_*" IOSTANDARD = LVCMOS25; 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "KC705_FanControl_*" TIG; 17 | -------------------------------------------------------------------------------- /board/VC707/Clock.SystemClock.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Clocks 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## System Clock 6 | ## ============================================================================= 7 | ## Bank: 38 8 | ## VCCO: 1.5V (VCC1V5_FPGA) 9 | ## Location: U51 (SIT9102) 10 | ## Vendor: SiTime 11 | ## Device: SiT9102 - 1 to 220 MHz High Performance Oscillator 12 | ## Frequency: 200 MHz, 50ppm 13 | set_property PACKAGE_PIN E19 [get_ports VC707_SystemClock_200MHz_p] 14 | set_property PACKAGE_PIN E18 [get_ports VC707_SystemClock_200MHz_n] 15 | # set I/O standard 16 | set_property IOSTANDARD LVDS [get_ports -regexp {VC707_SystemClock_200MHz_[p|n]}] 17 | # specify a 200 MHz clock 18 | create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports VC707_SystemClock_200MHz_p] 19 | -------------------------------------------------------------------------------- /board/VC707/Transceiver.SFP.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SFP interface 2 | ## ============================================================================= 3 | ## Bank: 13, 15 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: P3 6 | ## I²C-Address: 0xA0 (1010 000xb) 7 | NET "VC707_SFP_TX_Disable_n" LOC = "AP33" | IOSTANDARD = LVCMOS18; ## ; low-active; external 4k7 pullup resistor; level shifted by Q4 (NDS331N) 8 | NET "VC707_SFP_LossOfSignal" LOC = "BB38" | IOSTANDARD = LVCMOS18; ## ; high-active; external 4k7 pullup resistor; level shifted by U69 (SN74AVC1T45) 9 | 10 | ## SGMII LVDS signal-pairs 11 | ## -------------------------- 12 | ## Bank: 113 13 | ## ReferenceClock 14 | ## Location: P3 15 | NET "VC707_SFP_TX_p" LOC = "AM4"; ## 16 | NET "VC707_SFP_TX_n" LOC = "AM3"; ## 17 | NET "VC707_SFP_RX_p" LOC = "AL6"; ## 18 | NET "VC707_SFP_RX_n" LOC = "AL5"; ## 19 | 20 | ## Ignore timings on async I/O pins 21 | NET "VC707_SFP_TX_Disable_n" TIG; 22 | NET "VC707_SFP_LossOfSignal" TIG; 23 | -------------------------------------------------------------------------------- /board/KC705/EthernetPHY.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Ethernet PHY - Marvell Alaska Ultra 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14, 15, 117 5 | ## VCCO: 2.5V, 2.5V (VCC2V5_FPGA, VCC2V5_FPGA) 6 | ## Location: U37 7 | ## Vendor: Marvell 8 | ## Device: M88E1111 - BAB1C000 9 | ## MDIO-Address: 0x05 (---0 0111b) 10 | ## I²C-Address: I²C management mode is not enabled 11 | ## 12 | ## common signals and management 13 | ## -------------------------- 14 | NET "KC705_EthernetPHY_Reset_n" LOC = "L20" | IOSTANDARD = LVCMOS25; ## {IN} U37.36 15 | NET "KC705_EthernetPHY_Interrupt_n" LOC = "N30" | IOSTANDARD = LVCMOS25; ## {IN} U37.32 16 | NET "KC705_EthernetPHY_Management_Clock" LOC = "R23" | IOSTANDARD = LVCMOS25; ## {OUT} U37.35 17 | NET "KC705_EthernetPHY_Management_Data" LOC = "J21" | IOSTANDARD = LVCMOS25; ## {INOUT} U37.33 18 | 19 | ## Ignore timings on async I/O pins 20 | NET "KC705_EthernetPHY_Reset_n" TIG; 21 | NET "KC705_EthernetPHY_Interrupt_n" TIG; 22 | NET "KC705_EthernetPHY_Management_*" TIG; 23 | -------------------------------------------------------------------------------- /board/ZedBoard/GPIO.Switch.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## General Purpose IO 3 | ## ============================================================================= 4 | ## DIP-Switches 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 34, 35 7 | ## VCCO: 2.5V (VADJ) 8 | ## Location: SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_GPIO_Switches<0>" LOC = "F22"; ## {IN} SW0 11 | NET "ZED_GPIO_Switches<1>" LOC = "G22"; ## {IN} SW1 12 | NET "ZED_GPIO_Switches<2>" LOC = "H22"; ## {IN} SW2 13 | NET "ZED_GPIO_Switches<3>" LOC = "F21"; ## {IN} SW3 14 | NET "ZED_GPIO_Switches<4>" LOC = "H19"; ## {IN} SW4 15 | NET "ZED_GPIO_Switches<5>" LOC = "H18"; ## {IN} SW5 16 | NET "ZED_GPIO_Switches<6>" LOC = "H17"; ## {IN} SW6 17 | NET "ZED_GPIO_Switches<7>" LOC = "M15"; ## {IN} SW7 18 | NET "ZED_GPIO_Switches" IOSTANDARD = LVCMOS25; ## 19 | -------------------------------------------------------------------------------- /board/VC707/GPIO.Rotary.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Rotary-Button 6 | ## ============================================================================= 7 | ## Bank: 13 8 | ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW10 10 | ## ----------------------------------------------------------------------------- 11 | NET "VC707_GPIO_Rotary_Button" LOC = "AW31"; ## SW10.5; high-active; external 4k7 pulldown resistor 12 | NET "VC707_GPIO_Rotary_IncA" LOC = "AR33"; ## SW10.1; high-active; external 4k7 pulldown resistor 13 | NET "VC707_GPIO_Rotary_IncB" LOC = "AT31"; ## SW10.6; high-active; external 4k7 pulldown resistor 14 | NET "VC707_GPIO_Rotary_*" IOSTANDARD = LVCMOS18; 15 | 16 | ## Ignore timings on async I/O pins 17 | NET "VC707_GPIO_Rotary_*" TIG; 18 | -------------------------------------------------------------------------------- /board/VC707/EthernetPHY.ucf: -------------------------------------------------------------------------------- 1 | ## Ethernet PHY - Marvell Alaska Ultra 2 | ## ============================================================================= 3 | ## Bank: 14 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: U50 6 | ## Vendor: Marvell 7 | ## Device: M88E1111 - 8 | ## MDIO-Address: 0x05 (---0 0111b) 9 | ## I²C-Address: I²C management mode is not enabled 10 | NET "VC707_EthernetPHY_Reset_n" LOC = "AJ33" | IOSTANDARD = LVCMOS18; ## U50 - Pin K3 ; level shifted by U70 (TXS0108E) 11 | NET "VC707_EthernetPHY_Interrupt_n" LOC = "AL31" | IOSTANDARD = LVCMOS18; ## U50 - Pin L1 ; level shifted by U70 (TXS0108E) 12 | NET "VC707_EthernetPHY_Management_Clock" LOC = "AH31" | IOSTANDARD = LVCMOS18; ## U50 - Pin L3 ; level shifted by U70 (TXS0108E) 13 | NET "VC707_EthernetPHY_Management_Data" LOC = "AK33" | IOSTANDARD = LVCMOS18; ## U50 - Pin M1 ; level shifted by U70 (TXS0108E) 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "VC707_EthernetPHY_Reset_n" TIG; 17 | NET "VC707_EthernetPHY_Interrupt_n" TIG; 18 | NET "VC707_EthernetPHY_Management_*" TIG; 19 | -------------------------------------------------------------------------------- /board/ML505/GPIO.Button.Cursor.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Cursor Buttons 3 | ## ============================================================================= 4 | ## Bank: 18 5 | ## VCCO: 3.3V (VCC1V8_FPGA) 6 | ## Location: SW10, SW11, SW12, SW13, SW14 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_Button_North" LOC = "U8" | IOSTANDARD = LVCMOS18; ## SW10; high-active; external 4k7 pulldown resistor 9 | NET "ML505_GPIO_Button_West" LOC = "AJ7" | IOSTANDARD = LVCMOS18; ## SW13; high-active; external 4k7 pulldown resistor 10 | NET "ML505_GPIO_Button_Center" LOC = "AJ6" | IOSTANDARD = LVCMOS18; ## SW14; high-active; external 4k7 pulldown resistor 11 | NET "ML505_GPIO_Button_East" LOC = "AK7" | IOSTANDARD = LVCMOS18; ## SW12; high-active; external 4k7 pulldown resistor 12 | NET "ML505_GPIO_Button_South" LOC = "V8" | IOSTANDARD = LVCMOS18; ## SW11; high-active; external 4k7 pulldown resistor 13 | NET "ML505_GPIO_Button_*" IOSTANDARD = LVCMOS33; ## 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "ML505_GPIO_Button_*" TIG; 17 | -------------------------------------------------------------------------------- /board/ML605/Bus.PMBus.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Board: Xilinx - Virtex 6 ML605 3 | ## FPGA: Xilinx Virtex 6 4 | ## Device: XC6VLX240T 5 | ## Package: FF1156 6 | ## Speedgrade: -1 7 | ## ============================================================================================================================================================= 8 | ## Low Speed Bus 9 | ## ============================================================================================================================================================= 10 | ## 11 | ## PowerManagementBus (PMBus) 12 | ## ============================================================================= 13 | ## Bank: 15 14 | ## VCCO: 1,8V (VCC1V8_FPGA) 15 | ## Location: 16 | ## Vendor: 17 | ## Device: 18 | ##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## 19 | ##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## 20 | ##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## 21 | -------------------------------------------------------------------------------- /board/KC705/GPIO.Rotary.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Rotary-Button 6 | ## ----------------------------------------------------------------------------- 7 | #$ ## Bank: 13 8 | #$ ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW8 10 | ## ----------------------------------------------------------------------------- 11 | #$ NET "KC705_GPIO_Rotary_Button" LOC = "AW31"; ## {IN} SW10.5; high-active; external 4k7 pulldown resistor 12 | #$ NET "KC705_GPIO_Rotary_IncA" LOC = "AR33"; ## {IN} SW10.1; high-active; external 4k7 pulldown resistor 13 | #$ NET "KC705_GPIO_Rotary_IncB" LOC = "AT31"; ## {IN} SW10.6; high-active; external 4k7 pulldown resistor 14 | NET "KC705_GPIO_Rotary_*" IOSTANDARD = LVCMOS18; 15 | 16 | # Ignore timings on async I/O pins 17 | NET "KC705_GPIO_Rotary_*" TIG; 18 | -------------------------------------------------------------------------------- /board/Arty-S7-50/Bus.SPI.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## SPI-Bus 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 15 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: J7 (2x3 header) 7 | ## ----------------------------------------------------------------------------- 8 | ## {OUT} SerialClock 9 | set_property PACKAGE_PIN G16 [ get_ports ArtyS750_SPI_SerialClock ] 10 | ## {OUT} SlaveSelect 11 | set_property PACKAGE_PIN H16 [ get_ports ArtyS750_SPI_SlaveSelect ] 12 | ## {OUT} MOSI (Master Out - Slave In) 13 | set_property PACKAGE_PIN H17 [ get_ports ArtyS750_SPI_MOSI ] 14 | ## {IN} MISO (Master In - Slave Out) 15 | set_property PACKAGE_PIN K14 [ get_ports ArtyS750_SPI_MISO ] 16 | # set I/O standard 17 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyS750_SPI_.*} ] 18 | 19 | # Ignore timings on async I/O pins 20 | set_false_path -to [ get_ports ArtyS750_SPI_SerialClock ] 21 | set_false_path -to [ get_ports ArtyS750_SPI_SlaveSelect ] 22 | set_false_path -to [ get_ports ArtyS750_SPI_MOSI ] 23 | set_false_path -from [ get_ports ArtyS750_SPI_MISO ] 24 | -------------------------------------------------------------------------------- /board/Arty-A7-35T/Bus.SPI.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## SPI-Bus 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 35 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: J6 (2x3 header) 7 | ## ----------------------------------------------------------------------------- 8 | ## {OUT} SerialClock 9 | set_property PACKAGE_PIN F1 [ get_ports ArtyA735T_SPI_SerialClock ] 10 | ## {OUT} SlaveSelect 11 | set_property PACKAGE_PIN C1 [ get_ports ArtyA735T_SPI_SlaveSelect ] 12 | ## {OUT} MOSI (Master Out - Slave In) 13 | set_property PACKAGE_PIN H1 [ get_ports ArtyA735T_SPI_MOSI ] 14 | ## {IN} MISO (Master In - Slave Out) 15 | set_property PACKAGE_PIN G1 [ get_ports ArtyA735T_SPI_MISO ] 16 | # set I/O standard 17 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyA735T_SPI_.*} ] 18 | 19 | # Ignore timings on async I/O pins 20 | set_false_path -to [ get_ports ArtyA735T_SPI_SerialClock ] 21 | set_false_path -to [ get_ports ArtyA735T_SPI_SlaveSelect ] 22 | set_false_path -to [ get_ports ArtyA735T_SPI_MOSI ] 23 | set_false_path -from [ get_ports ArtyA735T_SPI_MISO ] 24 | -------------------------------------------------------------------------------- /board/ML505/Transceiver.SFP.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SFP interface 2 | ## ============================================================================= 3 | ## Bank: 19 4 | ## VCCO: 1.8V (VCC1V8) 5 | ## Location: P19 6 | ## I²C-Address: 0xA0 (1010 000xb) 7 | NET "ML505_SFP_TX_Disable" LOC = "K24" | IOSTANDARD = LVCMOS18; ## ; low-active; external 4k7 pullup resistor; level shifted by Q42 (NDS331N) 8 | 9 | ## SGMII LVDS signal-pairs 10 | ## -------------------------- 11 | ## Bank: 116 12 | ## ReferenceClock 13 | ## Location: P3 14 | ## LOC X0Y4 - GTP_DUAL port 0 15 | NET "ML505_SFP_TX_p" LOC = "F2"; ## 16 | NET "ML505_SFP_TX_n" LOC = "G2"; ## 17 | NET "ML505_SFP_RX_p" LOC = "G1"; ## 18 | NET "ML505_SFP_RX_n" LOC = "H1"; ## 19 | 20 | ## Bank 15; 1.8 V 21 | NET "ML505_SFP_SerialClock" LOC = "R26"; ## level shifted by Q42 (NDS331N) 22 | NET "ML505_SFP_SerialData" LOC = "U28"; ## level shifted by Q42 (NDS331N) 23 | NET "ML505_SFP_Serial*" PULLUP; 24 | 25 | ## Ignore timings on async I/O pins 26 | NET "ML505_SFP_TX_Disable" TIG; 27 | NET "ML505_SFP_Serial*" TIG; 28 | 29 | -------------------------------------------------------------------------------- /board/ZedBoard/GPIO.Button.Cursor.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## General Purpose IO 3 | ## ============================================================================= 4 | ## Cursor Buttons 5 | ## ----------------------------------------------------------------------------- 6 | ## Bank: 34 7 | ## VCCO: 2.5V (VADJ) 8 | ## Location: BTNU, BTNL, BTNC, BTNR, BTND 9 | ## ----------------------------------------------------------------------------- 10 | NET "ZED_GPIO_Button_North" LOC = "T18" | IOSTANDARD = LVCMOS25; ## {IN} BTNU; high-active; external 10k pulldown resistor 11 | NET "ZED_GPIO_Button_West" LOC = "N15" | IOSTANDARD = LVCMOS25; ## {IN} BTNL; high-active; external 10k pulldown resistor 12 | NET "ZED_GPIO_Button_Center" LOC = "P16" | IOSTANDARD = LVCMOS25; ## {IN} BTNC; high-active; external 10k pulldown resistor 13 | NET "ZED_GPIO_Button_East" LOC = "R18" | IOSTANDARD = LVCMOS25; ## {IN} BTNR; high-active; external 10k pulldown resistor 14 | NET "ZED_GPIO_Button_South" LOC = "R16" | IOSTANDARD = LVCMOS25; ## {IN} BTND; high-active; external 10k pulldown resistor 15 | -------------------------------------------------------------------------------- /board/KC705/Transceiver.SFP.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Transceiver - SFP interface 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 15, 117 5 | ## VCCO: 2.5V, 2.5V (VADJ_FPGA, VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0 8 | ## RefClock1 KC705_SMA_RefClock 9 | ## Placement: 10 | ## SFP: Quad117.Channel2 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: P5 12 | #$ ## I²C-Address: 0xA0 (1010 000xb) 13 | NET "KC705_SFP_TX_Disable_n" LOC = "Y20" | IOSTANDARD = LVCMOS25; ## #$ ; low-active; external 4k7 pullup resistor; level shifted by Q4 (NDS331N) 14 | NET "KC705_SFP_LossOfSignal" LOC = "P19" | IOSTANDARD = LVCMOS25; ## #$ ; high-active; external 4k7 pullup resistor; level shifted by U69 (SN74AVC1T45) 15 | ## 16 | ## -------------------------- 17 | ## SFP+ LVDS signal-pairs 18 | NET "KC705_SFP_TX_n" LOC = "H1"; ## {OUT} 19 | NET "KC705_SFP_TX_p" LOC = "H2"; ## {OUT} 20 | NET "KC705_SFP_RX_n" LOC = "G3"; ## {IN} 21 | NET "KC705_SFP_RX_p" LOC = "G4"; ## {IN} 22 | 23 | # Ignore timings on async I/O pins 24 | NET "KC705_SFP_TX_Disable_n" TIG; 25 | NET "KC705_SFP_LossOfSignal" TIG; 26 | 27 | -------------------------------------------------------------------------------- /board/AC701/GPIO.LED.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## LEDs 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 14 8 | ## VCCO: 3.3V (FPGA_3V3) 9 | ## Location: DS2, DS3, DS4, DS5 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} DS2; 12 | set_property PACKAGE_PIN M26 [get_ports AC701_GPIO_LED[0]] 13 | ## {OUT} DS3; 14 | set_property PACKAGE_PIN T24 [get_ports AC701_GPIO_LED[1]] 15 | ## {OUT} DS4; 16 | set_property PACKAGE_PIN T25 [get_ports AC701_GPIO_LED[2]] 17 | ## {OUT} DS5; 18 | set_property PACKAGE_PIN R26 [get_ports AC701_GPIO_LED[3]] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS33 [get_ports -regexp {AC701_GPIO_LED\[[0-3]]}] 21 | 22 | # Ignore timings on async I/O pins 23 | set_false_path -to [get_ports -regexp {AC701_GPIO_LED\[\d\]}] 24 | -------------------------------------------------------------------------------- /board/ZC706/GPIO.LED.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## LEDs 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 11, 33, 35 8 | ## VCCO: 2.5, 1.5, 1.5V (VADJ_FPGA, VCC1V5_FPGA, VCC1V5_FPGA) 9 | ## Location: Q30, Q9, Q8, Q7 10 | ## ----------------------------------------------------------------------------- 11 | NET "ZC706_GPIO_LED<0>" LOC = "A17" | IOSTANDARD = LVCMOS15; ## {OUT} Q30; Bank 35; VCCO=VCC1V5_FPGA 12 | NET "ZC706_GPIO_LED<1>" LOC = "W21" | IOSTANDARD = LVCMOS25; ## {OUT} Q9; Bank 11; VCCO=VADJ_FPGA 13 | NET "ZC706_GPIO_LED<2>" LOC = "G2" | IOSTANDARD = LVCMOS15; ## {OUT} Q8; Bank 33; VCCO=VCC1V5_FPGA 14 | NET "ZC706_GPIO_LED<3>" LOC = "Y21" | IOSTANDARD = LVCMOS25; ## {OUT} Q7; Bank 11; VCCO=VADJ_FPGA 15 | 16 | ## Ignore timings on async I/O pins 17 | NET "ZC706_GPIO_LED" TIG; 18 | -------------------------------------------------------------------------------- /board/AC701/FanControl.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Fan Control 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 15 8 | ## VCCO: 2.5V (VCC0_VADJ) 9 | ## Location: J61, Q17 (NDT3055L) 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} Q17.Gate; external 1k pullup resistor; Q17.Drain connects to J61.1 (GND) 12 | set_property PACKAGE_PIN J26 [get_ports AC701_FanControl_PWM] 13 | ## {IN} J61.3; voltage limited by D15 (MM3Z2V7B; 2.7V zener-diode) 14 | set_property PACKAGE_PIN J25 [get_ports AC701_FanControl_Tacho] 15 | # set I/O standard 16 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {AC701_FanControl_.*}] 17 | # Ignore timings on async I/O pins 18 | set_false_path -to [get_ports AC701_FanControl_PWM] 19 | set_false_path -from [get_ports AC701_FanControl_Tacho] 20 | -------------------------------------------------------------------------------- /board/ZC706/FanControl.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Fan Control 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 9 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: J61, Q1 (NDT3055L) 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} Q1.Gate; external 1k pullup resistor; Q1.Drain connects to J61.1 (GND) 12 | set_property PACKAGE_PIN AB19 [get_ports ZC706_FanControl_PWM] 13 | ## {IN} J61.3; voltage limited by D2 (MM3Z2V7B; 2.7V zener-diode) 14 | set_property PACKAGE_PIN AA19 [get_ports ZC706_FanControl_Tacho] 15 | # set I/O standard 16 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {ZC706_FanControl_.*}] 17 | # Ignore timings on async I/O pins 18 | set_false_path -to [get_ports ZC706_FanControl_PWM] 19 | set_false_path -from [get_ports ZC706_FanControl_Tacho] 20 | -------------------------------------------------------------------------------- /board/AC701/USB_UART.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 13 5 | ## VCCO: 1.8V (FPGA_1V8) 6 | ## Location: U44 7 | ## Vendor: Silicon Labs 8 | ## Device: CP2103-GM 9 | ## Baud-Rate: 300 Bd - 1 MBd 10 | ## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output 11 | ## {IN} U44.25 {OUT} 12 | set_property PACKAGE_PIN T19 [get_ports AC701_USB_UART_TX] 13 | ## {OUT} U44.24 {IN} 14 | set_property PACKAGE_PIN U19 [get_ports AC701_USB_UART_RX] 15 | ## {IN} U44.23 {OUT} Ready to Transmit (USB-UART has new data) 16 | set_property PACKAGE_PIN V19 [get_ports AC701_USB_UART_RTS_n] 17 | ## {OUT} U44.22 {IN} Clear to Send (FPGA is able to receive data) 18 | set_property PACKAGE_PIN W19 [get_ports AC701_USB_UART_CTS_n] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {AC701_USB_UART_.*}] 21 | # Ignore timings on async I/O pins 22 | set_false_path -from [get_ports AC701_USB_UART_TX] 23 | set_false_path -to [get_ports AC701_USB_UART_RX] 24 | set_false_path -from [get_ports AC701_USB_UART_RTS_n] 25 | set_false_path -to [get_ports AC701_USB_UART_CTS_n] 26 | -------------------------------------------------------------------------------- /board/KC705/FanControl.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Fan Control 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 14, 15 8 | ## VCCO: 2.5V, 2.5V (VCC2V5_FPGA, VCC2V5_FPGA) 9 | ## Location: J61, Q17 (NDT3055L) 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} Q17.Gate; external 1k pullup resistor; Q17.Drain connects to J61.1 (GND) 12 | set_property PACKAGE_PIN L26 [get_ports KC705_FanControl_PWM] 13 | ## {IN} J61.3; voltage limited by D15 (MM3Z2V7B; 2.7V zener-diode) 14 | set_property PACKAGE_PIN U22 [get_ports KC705_FanControl_Tacho] 15 | # set I/O standard 16 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {KC705_FanControl_.*}] 17 | # Ignore timings on async I/O pins 18 | set_false_path -to [get_ports KC705_FanControl_PWM] 19 | set_false_path -from [get_ports KC705_FanControl_Tacho] 20 | -------------------------------------------------------------------------------- /board/KC705/USB_UART.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 15 5 | ## VCCO: 2.5V (VCC2V5_FPGA) 6 | ## Location: U12 7 | ## Vendor: Silicon Labs 8 | ## Device: CP2103-GM 9 | ## Baud-Rate: 300 Bd - 1 MBd 10 | ## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output 11 | ## {IN} U34.25 {OUT} 12 | set_property PACKAGE_PIN M19 [get_ports KC705_USB_UART_TX] 13 | ## {OUT} U34.24 {IN} 14 | set_property PACKAGE_PIN K24 [get_ports KC705_USB_UART_RX] 15 | ## {IN} U34.23 {OUT} Ready to Transmit (USB-UART has new data) 16 | set_property PACKAGE_PIN K23 [get_ports KC705_USB_UART_RTS_n] 17 | ## {OUT} U34.22 {IN} Clear to Send (FPGA is able to receive data) 18 | set_property PACKAGE_PIN L27 [get_ports KC705_USB_UART_CTS_n] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {KC705_USB_UART_.*}] 21 | # Ignore timings on async I/O pins 22 | set_false_path -from [get_ports KC705_USB_UART_TX] 23 | set_false_path -to [get_ports KC705_USB_UART_RX] 24 | set_false_path -from [get_ports KC705_USB_UART_RTS_n] 25 | set_false_path -to [get_ports KC705_USB_UART_CTS_n] 26 | -------------------------------------------------------------------------------- /board/VC707/GPIO.Rotary.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Rotary-Button 6 | ## ============================================================================= 7 | ## Bank: 13 8 | ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW10 10 | ## ----------------------------------------------------------------------------- 11 | ## SW10.5; high-active; external 4k7 pulldown resistor 12 | set_property PACKAGE_PIN AW31 [get_ports VC707_GPIO_Rotary_Button] 13 | ## SW10.1; high-active; external 4k7 pulldown resistor 14 | set_property PACKAGE_PIN AR33 [get_ports VC707_GPIO_Rotary_IncA] 15 | ## SW10.6; high-active; external 4k7 pulldown resistor 16 | set_property PACKAGE_PIN AT31 [get_ports VC707_GPIO_Rotary_IncB] 17 | # set I/O standard 18 | set_property IOSTANDARD LVCMOS18 [get_ports -regexp {VC707_GPIO_Rotary_.*}] 19 | # Ignore timings on async I/O pins 20 | set_false_path -from [get_ports -regexp {VC707_GPIO_Rotary_.*}] 21 | -------------------------------------------------------------------------------- /board/Arty-S7-50/GPIO.LED.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## LEDs 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 15 8 | ## VCCO: 3.3V (FPGA_3V3) 9 | ## Location: LD2, LD3, LD4, LD5 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} LD4; 12 | set_property PACKAGE_PIN E18 [ get_ports ArtyS750_GPIO_LED[2] ] 13 | ## {OUT} LD5; 14 | set_property PACKAGE_PIN F13 [ get_ports ArtyS750_GPIO_LED[3] ] 15 | ## {OUT} LD6; 16 | set_property PACKAGE_PIN E13 [ get_ports ArtyS750_GPIO_LED[4] ] 17 | ## {OUT} LD7; 18 | set_property PACKAGE_PIN H15 [ get_ports ArtyS750_GPIO_LED[5] ] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyS750_GPIO_LED\[\d\]} ] 21 | 22 | # Ignore timings on async I/O pins 23 | set_false_path -to [ get_ports -regexp {ArtyS750_GPIO_LED\[\d\]} ] 24 | -------------------------------------------------------------------------------- /board/ML605/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Virtex 6 ML605 5 | ## FPGA: Xilinx Virtex 6 6 | ## Device: XC6VLX240T 7 | ## Package: FF1156 8 | ## Speedgrade: -1 9 | ## ============================================================================================================================================================= 10 | ## High Speed I/O (Transceiver) 11 | ## ============================================================================================================================================================= 12 | ## 13 | ## Transceiver - SMA interface 14 | ## ============================================================================= 15 | ## Bank: 113 16 | ## ReferenceClock 17 | ## Location: J25, J26 18 | #$ NET "ML605_SMA_RefClock_n" LOC = "AK7"; ## J26 19 | #$ NET "ML605_SMA_RefClock_p" LOC = "AK8"; ## J25 20 | -------------------------------------------------------------------------------- /board/KC705/GPIO.Rotary.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Rotary-Button 6 | ## ----------------------------------------------------------------------------- 7 | #$ ## Bank: 13 8 | #$ ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW8 10 | ## ----------------------------------------------------------------------------- 11 | #$ SW10.5; high-active; external 4k7 pulldown resistor 12 | #$ set_property PACKAGE_PIN AW31 [get_ports KC705_GPIO_Rotary_Button] 13 | #$ SW10.1; high-active; external 4k7 pulldown resistor 14 | #$ set_property PACKAGE_PIN AR33 [get_ports KC705_GPIO_Rotary_IncA] 15 | #$ SW10.6; high-active; external 4k7 pulldown resistor 16 | #$ set_property PACKAGE_PIN AT31 [get_ports KC705_GPIO_Rotary_IncB] 17 | # set I/O standard 18 | set_property IOSTANDARD LVCMOS18 [get_ports -regexp {KC705_GPIO_Rotary_.*}] 19 | # Ignore timings on async I/O pins 20 | set_false_path -from [get_ports -regexp {KC705_GPIO_Rotary_.*}] 21 | -------------------------------------------------------------------------------- /board/ML505/GPIO.LED.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 3, 21 5 | ## VCCO: 2.5V, 1.8V (VCC2V5, VCC1V8) 6 | ## Location: DS10, DS11, DS12, DS13, DS14, DS15, DS16, DS17 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_LED<0>" LOC = "H18" | IOSTANDARD = LVCMOS25; ## DS17 9 | NET "ML505_GPIO_LED<1>" LOC = "L18" | IOSTANDARD = LVCMOS25; ## DS16 10 | NET "ML505_GPIO_LED<2>" LOC = "G15" | IOSTANDARD = LVCMOS25; ## DS15 11 | NET "ML505_GPIO_LED<3>" LOC = "AD26" | IOSTANDARD = LVCMOS18; ## DS13; level-shifted by NDS331N to 2.5V 12 | NET "ML505_GPIO_LED<4>" LOC = "G16" | IOSTANDARD = LVCMOS25; ## DS14 13 | NET "ML505_GPIO_LED<5>" LOC = "AD25" | IOSTANDARD = LVCMOS18; ## DS12; level-shifted by NDS331N to 2.5V 14 | NET "ML505_GPIO_LED<6>" LOC = "AD24" | IOSTANDARD = LVCMOS18; ## DS11; level-shifted by NDS331N to 2.5V 15 | NET "ML505_GPIO_LED<7>" LOC = "AE24" | IOSTANDARD = LVCMOS18; ## DS10; level-shifted by NDS331N to 2.5V 16 | NET "ML505_GPIO_LED" SLEW = SLOW; 17 | 18 | ## Ignore timings on async I/O pins 19 | NET "ML505_GPIO_LED" TIG; 20 | -------------------------------------------------------------------------------- /board/KC705/GPIO.Switch.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## DIP-Switches 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 13 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: SW11 10 | ## ----------------------------------------------------------------------------- 11 | NET "KC705_GPIO_Switches<0>" LOC = "Y29"; ## {IN} SW11.4; high-active; external 4k7 pulldown resistor 12 | NET "KC705_GPIO_Switches<1>" LOC = "W29"; ## {IN} SW11.3; high-active; external 4k7 pulldown resistor 13 | NET "KC705_GPIO_Switches<2>" LOC = "AA28"; ## {IN} SW11.2; high-active; external 4k7 pulldown resistor 14 | NET "KC705_GPIO_Switches<3>" LOC = "Y28"; ## {IN} SW11.1; high-active; external 4k7 pulldown resistor 15 | NET "KC705_GPIO_Switches" IOSTANDARD = LVCMOS25; ## 16 | 17 | ## Ignore timings on async I/O pins 18 | NET "KC705_GPIO_Switches" TIG; 19 | -------------------------------------------------------------------------------- /board/ZC706/GPIO.Button.Cursor.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Cursor Buttons 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 11, 35, 13 8 | ## VCCO: 2.5V, 1.5V, 2.5V (VADJ_FPGA, VCC1V5_FPGA, VADJ_FPGA) 9 | ## Location: SW7, SW9, SW8 10 | ## ----------------------------------------------------------------------------- 11 | NET "ZC706_GPIO_Button_Left" LOC = "AK25" | IOSTANDARD = LVCMOS25; ## {IN} SW7; high-active; external 4k7 pulldown resistor; Bank 11; VCCO=VADJ_FPGA 12 | NET "ZC706_GPIO_Button_Center" LOC = "K15" | IOSTANDARD = LVCMOS15; ## {IN} SW9; high-active; external 4k7 pulldown resistor; Bank 35; VCCO=VCC1V5_FPGA 13 | NET "ZC706_GPIO_Button_Right" LOC = "R27" | IOSTANDARD = LVCMOS25; ## {IN} SW8; high-active; external 4k7 pulldown resistor; Bank 13; VCCO=VADJ_FPGA 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "ZC706_GPIO_Button_*" TIG; 17 | -------------------------------------------------------------------------------- /board/Arty-A7-35T/GPIO.LED.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## LEDs 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 35, 14 8 | ## VCCO: 3.3V (FPGA_3V3) 9 | ## Location: LD4, LD5, LD6, LD7 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} LD4; 12 | set_property PACKAGE_PIN H5 [ get_ports ArtyA735T_GPIO_LED[4] ] 13 | ## {OUT} LD5; 14 | set_property PACKAGE_PIN J5 [ get_ports ArtyA735T_GPIO_LED[5] ] 15 | ## {OUT} LD6; 16 | set_property PACKAGE_PIN T9 [ get_ports ArtyA735T_GPIO_LED[6] ] 17 | ## {OUT} LD7; 18 | set_property PACKAGE_PIN T10 [ get_ports ArtyA735T_GPIO_LED[7] ] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyA735T_GPIO_LED\[\d\]} ] 21 | 22 | # Ignore timings on async I/O pins 23 | set_false_path -to [ get_ports -regexp {ArtyA735T_GPIO_LED\[\d\]} ] 24 | -------------------------------------------------------------------------------- /board/ZC706/Transceiver.SFP.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Transceiver - SFP interface 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 15, 117 5 | ## VCCO: 2.5V, 2.5V (VADJ_FPGA, VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0 8 | ## RefClock1 ZC706_SMA_RefClock 9 | ## Placement: 10 | ## SFP: Quad117.Channel2 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: P5 12 | #$ ## I²C-Address: 0xA0 (1010 000xb) 13 | ## ----------------------------------------------------------------------------- 14 | ## #$ ; low-active; external 4k7 pullup resistor; level shifted by Q4 (NDS331N) 15 | set_property PACKAGE_PIN AA18 [get_ports ZC706_SFP_TX_Disable_n] 16 | # set I/O standard 17 | set_property IOSTANDARD LVCMOS25 [get_ports ZC706_SFP_TX_Disable_n] 18 | ## 19 | ## -------------------------- 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} 22 | set_property PACKAGE_PIN W4 [get_ports ZC706_SFP_TX_p] 23 | ## {OUT} 24 | set_property PACKAGE_PIN W3 [get_ports ZC706_SFP_TX_n] 25 | ## {IN} 26 | set_property PACKAGE_PIN Y6 [get_ports ZC706_SFP_RX_p] 27 | ## {IN} 28 | set_property PACKAGE_PIN Y5 [get_ports ZC706_SFP_RX_n] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [get_ports ZC706_SFP_TX_Disable_n] 32 | 33 | 34 | -------------------------------------------------------------------------------- /board/Atlys/HDMI.RX.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## HDMI IN (RX) 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 1 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC2 (J3) 7 | ## Vendor: Texas Instruments 8 | ## Device: TMDS141RHAR 9 | ## ----------------------------------------------------------------------------- 10 | NET "Atlys_TMDS_RX_Clock_p" LOC = "H17" ## {IN} 11 | NET "Atlys_TMDS_RX_Clock_n" LOC = "H18" ## {IN} 12 | NET "Atlys_TMDS_RX_0_p" LOC = "K17" ## {IN} 13 | NET "Atlys_TMDS_RX_0_n" LOC = "K18" ## {IN} 14 | NET "Atlys_TMDS_RX_1_p" LOC = "L17" ## {IN} 15 | NET "Atlys_TMDS_RX_1_n" LOC = "L18" ## {IN} 16 | NET "Atlys_TMDS_RX_2_p" LOC = "J16" ## {IN} 17 | NET "Atlys_TMDS_RX_2_n" LOC = "J18" ## {IN} 18 | NET "Atlys_TMDS_RX_*_?" IOSTANDARD = LVCMOS33; 19 | NET "Atlys_TMDS_RX_*_?" SLEW = FAST; 20 | 21 | NET "Atlys_TMDS_RX_SerialClock" LOC = "M16" ## {INOUT} 22 | NET "Atlys_TMDS_RX_SerialData" LOC = "M18" ## {INOUT} 23 | NET "Atlys_TMDS_RX_Serial*" IOSTANDARD = LVCMOS33; 24 | NET "Atlys_TMDS_RX_Serial*" SLEW = FAST; 25 | 26 | ## Ignore timings on async I/O pins 27 | NET "Atlys_TMDS_RX_Serial*" TIG; 28 | -------------------------------------------------------------------------------- /board/Atlys/HDMI.TX.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## HDMI OUT (TX) 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 0 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC1 (J2) 7 | ## Vendor: Texas Instruments 8 | ## Device: TMDS141RHAR 9 | ## ----------------------------------------------------------------------------- 10 | NET "Atlys_TMDS_TX_Clock_p" LOC = "B6" ## {OUT} 11 | NET "Atlys_TMDS_TX_Clock_n" LOC = "A6" ## {OUT} 12 | NET "Atlys_TMDS_TX_0_p" LOC = "D8" ## {OUT} 13 | NET "Atlys_TMDS_TX_0_n" LOC = "C8" ## {OUT} 14 | NET "Atlys_TMDS_TX_1_p" LOC = "C7" ## {OUT} 15 | NET "Atlys_TMDS_TX_1_n" LOC = "A7" ## {OUT} 16 | NET "Atlys_TMDS_TX_2_p" LOC = "B8" ## {OUT} 17 | NET "Atlys_TMDS_TX_2_n" LOC = "A8" ## {OUT} 18 | NET "Atlys_TMDS_TX_*_?" IOSTANDARD = LVCMOS33; 19 | NET "Atlys_TMDS_TX_*_?" SLEW = FAST; 20 | 21 | NET "Atlys_TMDS_TX_SerialClock" LOC = "D9" ## {INOUT} 22 | NET "Atlys_TMDS_TX_SerialData" LOC = "C9" ## {INOUT} 23 | NET "Atlys_TMDS_TX_Serial*" IOSTANDARD = LVCMOS33; 24 | NET "Atlys_TMDS_TX_Serial*" SLEW = FAST; 25 | 26 | ## Ignore timings on async I/O pins 27 | NET "Atlys_TMDS_TX_Serial*" TIG; 28 | -------------------------------------------------------------------------------- /board/ML505/GPIO.Switch.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## DIP-Switches 3 | ## ============================================================================= 4 | ## Bank: 15, 21 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## Location: SW 8 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_Switches<0>" LOC = "U25"; ## SW8.1; high-active; external 4k7 pulldown resistor 9 | NET "ML505_GPIO_Switches<1>" LOC = "AG27"; ## SW8.2; high-active; external 4k7 pulldown resistor 10 | NET "ML505_GPIO_Switches<2>" LOC = "AF25"; ## SW8.3; high-active; external 4k7 pulldown resistor 11 | NET "ML505_GPIO_Switches<3>" LOC = "AF26"; ## SW8.4; high-active; external 4k7 pulldown resistor 12 | NET "ML505_GPIO_Switches<4>" LOC = "AE27"; ## SW8.5; high-active; external 4k7 pulldown resistor 13 | NET "ML505_GPIO_Switches<5>" LOC = "AE26"; ## SW8.6; high-active; external 4k7 pulldown resistor 14 | NET "ML505_GPIO_Switches<6>" LOC = "AC25"; ## SW8.7; high-active; external 4k7 pulldown resistor 15 | NET "ML505_GPIO_Switches<7>" LOC = "AC24"; ## SW8.8; high-active; external 4k7 pulldown resistor 16 | NET "ML505_GPIO_Switches<*>" IOSTANDARD = LVCMOS18; 17 | 18 | ## Ignore timings on async I/O pins 19 | NET "ML505_GPIO_Switches<*>" TIG; 20 | -------------------------------------------------------------------------------- /board/ML505/Bus.LCDisplay.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Liquid Cristal Display 3 | ## ============================================================================================================================================================= 4 | ## Bank: 3, 12 5 | ## VCCO: 2.5V, 3.3V (VCC2V5, VCC3V3) 6 | ## Connector: J (LCD header) 7 | ## Display 8 | ## Vendor: DisplayTech 9 | ## Device: S162DBABC (162D Series) 10 | ## LCD Driver 11 | ## Vendor: Sitronix 12 | ## Device: ST7066U (compatible: Samsung KS0066U) 13 | ## Size: 2 lines, 16 Characters, 40 Segments (5 x 8 Pixel) 14 | NET "ML505_LCD_DB[4]" LOC = "T9"; ## J8.4 level shifted by U3 (XC95144XL) 15 | NET "ML505_LCD_DB[5]" LOC = "G7"; ## J8.3 level shifted by U3 (XC95144XL) 16 | NET "ML505_LCD_DB[6]" LOC = "G6"; ## J8.2 level shifted by U3 (XC95144XL) 17 | NET "ML505_LCD_DB[7]" LOC = "T11"; ## J8.1 level shifted by U3 (XC95144XL) 18 | NET "ML505_LCD_E" LOC = "AC9"; ## J8.9 level shifted by U3 (XC95144XL) 19 | NET "ML505_LCD_RS" LOC = "J17"; ## J8.11 level shifted by U3 (XC95144XL) ; Bank 3 20 | NET "ML505_LCD_RW" LOC = "AC10"; ## J8.10 level shifted by U3 (XC95144XL) 21 | NET "ML505_LCD_*" IOSTANDARD = LVCMOS25; 22 | 23 | ## Ignore timings on async I/O pins 24 | NET "ML505_LCD_*" TIG; 25 | -------------------------------------------------------------------------------- /board/VC707/GPIO.Button.Cursor.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Cursor Buttons 6 | ## ============================================================================= 7 | ## Bank: 15 8 | ## VCCO: 1,8V (VCC1V8_FPGA) 9 | ## Location: SW3, SW4, SW5, SW6, SW7 10 | ## ----------------------------------------------------------------------------- 11 | NET "VC707_GPIO_Button_North" LOC = "AR40"; ## SW 3; high-active; external 4k7 pulldown resistor 12 | NET "VC707_GPIO_Button_West" LOC = "AW40"; ## SW 7; high-active; external 4k7 pulldown resistor 13 | NET "VC707_GPIO_Button_Center" LOC = "AV39"; ## SW 6; high-active; external 4k7 pulldown resistor 14 | NET "VC707_GPIO_Button_East" LOC = "AU38"; ## SW 4; high-active; external 4k7 pulldown resistor 15 | NET "VC707_GPIO_Button_South" LOC = "AP40"; ## SW 5; high-active; external 4k7 pulldown resistor 16 | NET "VC707_GPIO_Button_*" IOSTANDARD = LVCMOS18; 17 | 18 | ## Ignore timings on async I/O pins 19 | NET "VC707_GPIO_Button_*" TIG; 20 | -------------------------------------------------------------------------------- /board/ZC706/PMOD.Port1.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Peripheral Modules (Pmods) 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## Pmod Port 1 (2x6 pins) 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 10, 11 8 | ## VCCO: 2.5V (VADJ) 9 | ## Location: J58 10 | ## LevelShifted: by U40 (TXS0108E) to 3.3V VCC3V3 11 | ## ----------------------------------------------------------------------------- 12 | NET "ZC706_PMOD_Port1<0>" LOC = "AJ21"; ## {INOUT} Bank11 J58.1 13 | NET "ZC706_PMOD_Port1<1>" LOC = "AK21"; ## {INOUT} Bank11 J58.3 14 | NET "ZC706_PMOD_Port1<2>" LOC = "AB21"; ## {INOUT} Bank11 J58.5 15 | NET "ZC706_PMOD_Port1<3>" LOC = "AB16"; ## {INOUT} Bank10 J58.6 16 | NET "ZC706_PMOD_Port1<4>" LOC = "Y20"; ## {INOUT} Bank9 J58.2 17 | NET "ZC706_PMOD_Port1<5>" LOC = "AA20"; ## {INOUT} Bank9 J58.4 18 | NET "ZC706_PMOD_Port1<6>" LOC = "AC18"; ## {INOUT} Bank9 J58.6 19 | NET "ZC706_PMOD_Port1<7>" LOC = "AC19"; ## {INOUT} Bank9 J58.8 20 | NET "ZC706_PMOD_Port1" IOSTANDARD = LVCMOS25; 21 | -------------------------------------------------------------------------------- /board/ML605/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Virtex 6 ML605 5 | ## FPGA: Xilinx Virtex 6 6 | ## Device: XC6VLX240T 7 | ## Package: FF1156 8 | ## Speedgrade: -1 9 | ## ============================================================================================================================================================= 10 | ## General Purpose I/O 11 | ## ============================================================================================================================================================= 12 | ## 13 | ## Special Buttons 14 | ## ============================================================================= 15 | ## Bank: 35 16 | ## VCCO: 1.5V (VCC1V5_FPGA) 17 | ## Location: SW10 18 | ## ----------------------------------------------------------------------------- 19 | NET "ML605_GPIO_Button_CPU_Reset" LOC = "H10" | IOSTANDARD = LVCMOS15; ## {IN} high-active; breaker / normally closed 20 | 21 | ## Ignore timings on async I/O pins 22 | NET "ML605_GPIO_Button_CPU_Reset" TIG; 23 | -------------------------------------------------------------------------------- /board/VC707/Bus.LCDisplay.ucf: -------------------------------------------------------------------------------- 1 | ## Liquid Cristal Display 2 | ## ============================================================================================================================================================= 3 | ## Bank: 15 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Connector: J23 (LCD header) 6 | ## Display 7 | ## Vendor: DisplayTech 8 | ## Device: S162DBABC (162D Series) 9 | ## LCD Driver 10 | ## Vendor: Sitronix 11 | ## Device: ST7066U (compatible: Samsung KS0066U) 12 | ## Size: 2 lines, 16 Characters, 40 Segments (5 x 8 Pixel) 13 | NET "VC707_LCD_DB[4]" LOC = "AT42"; ## J23 - Pin 4 ; level shifted by U33 (TXS0108E) 14 | NET "VC707_LCD_DB[5]" LOC = "AR38"; ## J23 - Pin 3 ; level shifted by U33 (TXS0108E) 15 | NET "VC707_LCD_DB[6]" LOC = "AR39"; ## J23 - Pin 2 ; level shifted by U33 (TXS0108E) 16 | NET "VC707_LCD_DB[7]" LOC = "AN40"; ## J23 - Pin 1 ; level shifted by U33 (TXS0108E) 17 | NET "VC707_LCD_E" LOC = "AT40"; ## J23 - Pin 9 ; level shifted by U33 (TXS0108E) 18 | NET "VC707_LCD_RS" LOC = "AN41"; ## J23 - Pin 11 ; level shifted by U33 (TXS0108E) 19 | NET "VC707_LCD_RW" LOC = "AR42"; ## J23 - Pin 10 ; level shifted by U33 (TXS0108E) 20 | NET "VC707_LCD_*" IOSTANDARD = LVCMOS18; 21 | 22 | ## Ignore timings on async I/O pins 23 | NET "VC707_LCD_*" TIG; 24 | -------------------------------------------------------------------------------- /board/KC705/GPIO.Switch.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## DIP-Switches 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 13 8 | ## VCCO: 2.5V (VADJ_FPGA) 9 | ## Location: SW11 10 | ## ----------------------------------------------------------------------------- 11 | ## {IN} SW11.4; high-active; external 4k7 pulldown resistor 12 | set_property PACKAGE_PIN Y29 [get_ports KC705_GPIO_Switches[0]] 13 | ## {IN} SW11.3; high-active; external 4k7 pulldown resistor 14 | set_property PACKAGE_PIN W29 [get_ports KC705_GPIO_Switches[1]] 15 | ## {IN} SW11.2; high-active; external 4k7 pulldown resistor 16 | set_property PACKAGE_PIN AA28 [get_ports KC705_GPIO_Switches[2]] 17 | ## {IN} SW11.1; high-active; external 4k7 pulldown resistor 18 | set_property PACKAGE_PIN Y28 [get_ports KC705_GPIO_Switches[3]] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {KC705_GPIO_Switches\[\d\]}] 21 | # Ignore timings on async I/O pins 22 | set_false_path -from [get_ports -regexp {KC705_GPIO_Switches\[\d\]}] 23 | -------------------------------------------------------------------------------- /board/KC705/Bus.LCDisplay.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Liquid Cristal Display 3 | ## ============================================================================================================================================================= 4 | ## Bank: 33, 14 5 | ## VCCO: 1.5V (VCC1V5_FPGA) 6 | ## Location: J31 (LCD header) 7 | ## Display 8 | ## Vendor: DisplayTech 9 | ## Device: S162DBABC (162D Series) 10 | ## LCD Driver 11 | ## Vendor: Sitronix 12 | ## Device: ST7066U (compatible: Samsung KS0066U) 13 | ## Size: 2 lines, 16 Characters, 40 Segments (5 x 8 Pixel) 14 | NET "KC705_LCD_E" LOC = "AB10"; ## J31.9 ; level shifted by U10 (TXS0108E) 15 | NET "KC705_LCD_RS" LOC = "Y11"; ## J31.11 ; level shifted by U10 (TXS0108E) ; Bank 14 #$ error: bank 33?? 16 | NET "KC705_LCD_RW" LOC = "AB13"; ## J31.10 ; level shifted by U10 (TXS0108E) 17 | NET "KC705_LCD_DB[4]" LOC = "AA13"; ## J31.4 ; level shifted by U10 (TXS0108E) 18 | NET "KC705_LCD_DB[5]" LOC = "AA10"; ## J31.3 ; level shifted by U10 (TXS0108E) 19 | NET "KC705_LCD_DB[6]" LOC = "AA11"; ## J31.2 ; level shifted by U10 (TXS0108E) 20 | NET "KC705_LCD_DB[7]" LOC = "Y10"; ## J31.1 ; level shifted by U10 (TXS0108E) 21 | NET "KC705_LCD_*" IOSTANDARD = LVCMOS15; ## 22 | 23 | ## Ignore timings on async I/O pins 24 | NET "KC705_LCD_*" TIG; 25 | -------------------------------------------------------------------------------- /board/ZC706/PMOD.Port1.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Pmod Port 1 (2x6 pins) 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 10, 11 5 | ## VCCO: 2.5V (VADJ) 6 | ## Location: J58 7 | ## LevelShifted: by U40 (TXS0108E) to 3.3V VCC3V3 8 | ## ----------------------------------------------------------------------------- 9 | ## {INOUT} Bank11 J58.1 10 | set_property PACKAGE_PIN AJ21 [get_ports ZC706_PMOD_Port1[0]] 11 | ## {INOUT} Bank11 J58.3 12 | set_property PACKAGE_PIN AK21 [get_ports ZC706_PMOD_Port1[1]] 13 | ## {INOUT} Bank11 J58.5 14 | set_property PACKAGE_PIN AB21 [get_ports ZC706_PMOD_Port1[2]] 15 | ## {INOUT} Bank10 J58.6 16 | set_property PACKAGE_PIN AB16 [get_ports ZC706_PMOD_Port1[3]] 17 | ## {INOUT} Bank9 J58.2 18 | set_property PACKAGE_PIN Y20 [get_ports ZC706_PMOD_Port1[4]] 19 | ## {INOUT} Bank9 J58.4 20 | set_property PACKAGE_PIN AA20 [get_ports ZC706_PMOD_Port1[5]] 21 | ## {INOUT} Bank9 J58.6 22 | set_property PACKAGE_PIN AC18 [get_ports ZC706_PMOD_Port1[6]] 23 | ## {INOUT} Bank9 J58.8 24 | set_property PACKAGE_PIN AC19 [get_ports ZC706_PMOD_Port1[7]] 25 | # set I/O standard 26 | set_property IOSTANDARD LVCMOS25 [get_ports -regexp {ZC706_PMOD_Port1\[\d\]}] 27 | # Ignore timings on async I/O pins 28 | set_false_path -to [get_ports -regexp {ZC706_PMOD_Port1\[\d\]}] 29 | set_false_path -from [get_ports -regexp {ZC706_PMOD_Port1\[\d\]}] 30 | -------------------------------------------------------------------------------- /board/KC705/FMC-LPC/FasterTechnology/S14/FMC-LPC.SFP_Channel3.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-LPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 117 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad117.Channel3 (GTXE2_CHANNEL_X0Y11) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA05_n 15 | set_property PACKAGE_PIN AH22 [ get_ports KC705_FMC_LPC_SFP_SerialClock[3] ] 16 | ## {INOUT} LA06_p 17 | set_property PACKAGE_PIN AK20 [ get_ports KC705_FMC_LPC_SFP_SerialData[3] ] 18 | ## 19 | ## SFP+ LVDS signal-pairs 20 | ## {OUT} DP0_C2M_P 21 | set_property PACKAGE_PIN F2 [ get_ports KC705_FMC_LPC_SFP_TX_p[3] ] 22 | ## {OUT} DP0_C2M_N 23 | set_property PACKAGE_PIN F1 [ get_ports KC705_FMC_LPC_SFP_TX_n[3] ] 24 | ## {IN} DP0_M2C_P 25 | set_property PACKAGE_PIN F6 [ get_ports KC705_FMC_LPC_SFP_RX_p[3] ] 26 | ## {IN} DP0_M2C_N 27 | set_property PACKAGE_PIN F5 [ get_ports KC705_FMC_LPC_SFP_RX_n[3] ] 28 | 29 | # Ignore timings on async I/O pins 30 | set_false_path -to [ get_ports KC705_FMC_LPC_SFP_TX_Disable_n ] 31 | set_false_path -from [ get_ports KC705_FMC_LPC_SFP_LossOfSignal ] -------------------------------------------------------------------------------- /board/iCEBreaker/constraints.pcf: -------------------------------------------------------------------------------- 1 | #| iCEBreaker 2 | 3 | 4 | #> UART 5 | set_io --warn-no-port iCEBreaker_TX 9 6 | set_io --warn-no-port iCEBreaker_RX 6 7 | 8 | 9 | #> SPI [on-board flash] 10 | set_io --warn-no-port iCEBreaker_FLASH_SDO 14 11 | set_io --warn-no-port iCEBreaker_FLASH_SCK 15 12 | set_io --warn-no-port iCEBreaker_FLASH_CSN 16 13 | set_io --warn-no-port iCEBreaker_FLASH_SDI 17 14 | 15 | 16 | #> SPI [user port] 17 | set_io --warn-no-port iCEBreaker_SPI_SDO 43 18 | set_io --warn-no-port iCEBreaker_SPI_SCK 38 19 | set_io --warn-no-port iCEBreaker_SPI_CSN 34 20 | set_io --warn-no-port iCEBreaker_SPI_SDI 31 21 | 22 | 23 | #> TWI 24 | set_io --warn-no-port iCEBreaker_TWI_SDA 2 25 | set_io --warn-no-port iCEBreaker_TWI_SCL 4 26 | 27 | 28 | #> GPIO [input] 29 | set_io --warn-no-port iCEBreaker_GPIO_I[0] 18 30 | set_io --warn-no-port iCEBreaker_GPIO_I[1] 19 31 | set_io --warn-no-port iCEBreaker_GPIO_I[2] 20 32 | set_io --warn-no-port iCEBreaker_GPIO_I[3] 28 33 | 34 | 35 | #> GPIO [output] 36 | set_io --warn-no-port iCEBreaker_GPIO_O[0] 25 37 | set_io --warn-no-port iCEBreaker_GPIO_O[1] 26 38 | set_io --warn-no-port iCEBreaker_GPIO_O[2] 27 39 | set_io --warn-no-port iCEBreaker_GPIO_O[3] 23 40 | 41 | 42 | #> RGB power LED 43 | set_io --warn-no-port iCEBreaker_LED_R 39 44 | set_io --warn-no-port iCEBreaker_LED_G 40 45 | set_io --warn-no-port iCEBreaker_LED_B 41 46 | 47 | 48 | #> User Reset Button 49 | set_io --warn-no-port iCEBreaker_USR_RST_BTN 10 50 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |

2 | 4 | 6 | 8 | 10 |

11 | 12 | # FPGA board constraints 13 | 14 |

15 | 16 |

17 | 18 | This repository provides constraint definitions in a standardised and distributed format, for decoupling board details 19 | from design sources. 20 | -------------------------------------------------------------------------------- /board/Arty-S7-50/GPIO.LED.RGB.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## LEDs 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 15 8 | ## VCCO: 3.3V (FPGA_3V3) 9 | ## Location: LD0, LD1 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} LD0.R; 12 | set_property PACKAGE_PIN J15 [ get_ports ArtyS750_GPIO_LED[0]_R ] 13 | ## {OUT} LD0.G; 14 | set_property PACKAGE_PIN G17 [ get_ports ArtyS750_GPIO_LED[0]_G ] 15 | ## {OUT} LD0.B; 16 | set_property PACKAGE_PIN F15 [ get_ports ArtyS750_GPIO_LED[0]_B ] 17 | ## {OUT} LD1.R; 18 | set_property PACKAGE_PIN E15 [ get_ports ArtyS750_GPIO_LED[1]_R ] 19 | ## {OUT} LD1.G; 20 | set_property PACKAGE_PIN F18 [ get_ports ArtyS750_GPIO_LED[1]_G ] 21 | ## {OUT} LD1.B; 22 | set_property PACKAGE_PIN E14 [ get_ports ArtyS750_GPIO_LED[1]_B ] 23 | # set I/O standard 24 | set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {ArtyS750_GPIO_LED\[\d\]_[RGB]} ] 25 | 26 | # Ignore timings on async I/O pins 27 | set_false_path -to [ get_ports -regexp {ArtyS750_GPIO_LED\[\d\]_[RGB]} ] 28 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.Clock.RefClock0.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad117.Channel0 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA05_n 15 | set_property PACKAGE_PIN F30 [ get_ports KC705_FMC_HPC_SFP_SerialClock[3}] 16 | ## {INOUT} LA06_p 17 | set_property PACKAGE_PIN H30 [ get_ports KC705_FMC_HPC_SFP_SerialData[3] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP0_C2M_P 22 | set_property PACKAGE_PIN D2 [ get_ports KC705_FMC_HPC_SFP_TX_p[3] ] 23 | ## {OUT} DP0_C2M_N 24 | set_property PACKAGE_PIN D1 [ get_ports KC705_FMC_HPC_SFP_TX_n[3] ] 25 | ## {IN} DP0_M2C_P 26 | set_property PACKAGE_PIN E4 [ get_ports KC705_FMC_HPC_SFP_RX_p[3] ] 27 | ## {IN} DP0_M2C_N 28 | set_property PACKAGE_PIN E3 [ get_ports KC705_FMC_HPC_SFP_RX_n[3] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.Clock.RefClock1.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad117.Channel0 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA05_n 15 | set_property PACKAGE_PIN F30 [ get_ports KC705_FMC_HPC_SFP_SerialClock[3}] 16 | ## {INOUT} LA06_p 17 | set_property PACKAGE_PIN H30 [ get_ports KC705_FMC_HPC_SFP_SerialData[3] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP0_C2M_P 22 | set_property PACKAGE_PIN D2 [ get_ports KC705_FMC_HPC_SFP_TX_p[3] ] 23 | ## {OUT} DP0_C2M_N 24 | set_property PACKAGE_PIN D1 [ get_ports KC705_FMC_HPC_SFP_TX_n[3] ] 25 | ## {IN} DP0_M2C_P 26 | set_property PACKAGE_PIN E4 [ get_ports KC705_FMC_HPC_SFP_RX_p[3] ] 27 | ## {IN} DP0_M2C_N 28 | set_property PACKAGE_PIN E3 [ get_ports KC705_FMC_HPC_SFP_RX_n[3] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.GPIO.Switch.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad117.Channel0 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA05_n 15 | set_property PACKAGE_PIN F30 [ get_ports KC705_FMC_HPC_SFP_SerialClock[3}] 16 | ## {INOUT} LA06_p 17 | set_property PACKAGE_PIN H30 [ get_ports KC705_FMC_HPC_SFP_SerialData[3] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP0_C2M_P 22 | set_property PACKAGE_PIN D2 [ get_ports KC705_FMC_HPC_SFP_TX_p[3] ] 23 | ## {OUT} DP0_C2M_N 24 | set_property PACKAGE_PIN D1 [ get_ports KC705_FMC_HPC_SFP_TX_n[3] ] 25 | ## {IN} DP0_M2C_P 26 | set_property PACKAGE_PIN E4 [ get_ports KC705_FMC_HPC_SFP_RX_p[3] ] 27 | ## {IN} DP0_M2C_N 28 | set_property PACKAGE_PIN E3 [ get_ports KC705_FMC_HPC_SFP_RX_n[3] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.SFP_Channel0.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad118.Channel3 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA16_p 15 | set_property PACKAGE_PIN B27 [ get_ports KC705_FMC_HPC_SFP_SerialClock[0}] 16 | ## {INOUT} LA16_n 17 | set_property PACKAGE_PIN A27 [ get_ports KC705_FMC_HPC_SFP_SerialData[0] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP3_C2M_P 22 | set_property PACKAGE_PIN A4 [ get_ports KC705_FMC_HPC_SFP_TX_p[0] ] 23 | ## {OUT} DP3_C2M_N 24 | set_property PACKAGE_PIN A3 [ get_ports KC705_FMC_HPC_SFP_TX_n[0] ] 25 | ## {IN} DP3_M2C_P 26 | set_property PACKAGE_PIN A8 [ get_ports KC705_FMC_HPC_SFP_RX_p[0] ] 27 | ## {IN} DP3_M2C_N 28 | set_property PACKAGE_PIN A7 [ get_ports KC705_FMC_HPC_SFP_RX_n[0] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.SFP_Channel1.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad118.Channel2 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA12_n 15 | set_property PACKAGE_PIN B29 [ get_ports KC705_FMC_HPC_SFP_SerialClock[1}] 16 | ## {INOUT} LA13_p 17 | set_property PACKAGE_PIN A25 [ get_ports KC705_FMC_HPC_SFP_SerialData[1] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP2_C2M_P 22 | set_property PACKAGE_PIN B2 [ get_ports KC705_FMC_HPC_SFP_TX_p[1] ] 23 | ## {OUT} DP2_C2M_N 24 | set_property PACKAGE_PIN B1 [ get_ports KC705_FMC_HPC_SFP_TX_n[1] ] 25 | ## {IN} DP2_M2C_P 26 | set_property PACKAGE_PIN B6 [ get_ports KC705_FMC_HPC_SFP_RX_p[1] ] 27 | ## {IN} DP2_M2C_N 28 | set_property PACKAGE_PIN B5 [ get_ports KC705_FMC_HPC_SFP_RX_n[1] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.SFP_Channel2.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad118.Channel1 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA09_p 15 | set_property PACKAGE_PIN B30 [ get_ports KC705_FMC_HPC_SFP_SerialClock[2}] 16 | ## {INOUT} LA09_n 17 | set_property PACKAGE_PIN A30 [ get_ports KC705_FMC_HPC_SFP_SerialData[2] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP1_C2M_P 22 | set_property PACKAGE_PIN C4 [ get_ports KC705_FMC_HPC_SFP_TX_p[2] ] 23 | ## {OUT} DP1_C2M_N 24 | set_property PACKAGE_PIN C3 [ get_ports KC705_FMC_HPC_SFP_TX_n[2] ] 25 | ## {IN} DP1_M2C_P 26 | set_property PACKAGE_PIN D6 [ get_ports KC705_FMC_HPC_SFP_RX_p[2] ] 27 | ## {IN} DP1_M2C_N 28 | set_property PACKAGE_PIN D5 [ get_ports KC705_FMC_HPC_SFP_RX_n[2] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/KC705/FMC-HPC/FasterTechnology/S14/FMC-HPC.SFP_Channel3.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## FMC-HPC Interface for Faster Technologies S14 FMC Card 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 12, 118 5 | ## VCCO: 2.5V (VADJ_FPGA) 6 | ## Quad117: 7 | ## RefClock0: 8 | ## RefClock1 9 | ## Placement: 10 | ## SFP: Quad117.Channel0 (GTXE2_CHANNEL_X0Y10) 11 | ## Location: J2 12 | ## ----------------------------------------------------------------------------- 13 | ## I2C interface 14 | ## {INOUT} LA05_n 15 | set_property PACKAGE_PIN F30 [ get_ports KC705_FMC_HPC_SFP_SerialClock[3}] 16 | ## {INOUT} LA06_p 17 | set_property PACKAGE_PIN H30 [ get_ports KC705_FMC_HPC_SFP_SerialData[3] ] 18 | 19 | ## 20 | ## SFP+ LVDS signal-pairs 21 | ## {OUT} DP0_C2M_P 22 | set_property PACKAGE_PIN D2 [ get_ports KC705_FMC_HPC_SFP_TX_p[3] ] 23 | ## {OUT} DP0_C2M_N 24 | set_property PACKAGE_PIN D1 [ get_ports KC705_FMC_HPC_SFP_TX_n[3] ] 25 | ## {IN} DP0_M2C_P 26 | set_property PACKAGE_PIN E4 [ get_ports KC705_FMC_HPC_SFP_RX_p[3] ] 27 | ## {IN} DP0_M2C_N 28 | set_property PACKAGE_PIN E3 [ get_ports KC705_FMC_HPC_SFP_RX_n[3] ] 29 | 30 | # Ignore timings on async I/O pins 31 | set_false_path -to [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 32 | set_false_path -from [ get_ports -regexp {KC705_FMC_HPC_SFP_Serial.*} ] 33 | -------------------------------------------------------------------------------- /board/ML505/Monitor.DVI.Output.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Video - DVI Transmitter 3 | ## ============================================================================= 4 | ## Bank: 15, 18, 22 5 | ## VCCO: 1.8V, 3.3V, 3.3V (VCC1V8, VCC3V3, VCC3V3) 6 | ## Location: U17 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_Video_DVI_Reset_n" LOC = "AK6"; ## 9 | NET "ML505_Video_DVI_Clock_n" LOC = "AL10"; ## 10 | NET "ML505_Video_DVI_Clock_p" LOC = "AL11"; ## 11 | NET "ML505_Video_DVI_HSync" LOC = "AM12"; ## 12 | NET "ML505_Video_DVI_VSync" LOC = "AM11"; ## 13 | NET "ML505_Video_DVI_DataEnable" LOC = "AE8"; ## 14 | NET "ML505_Video_DVI_Data<0>" LOC = "AB8"; ## 15 | NET "ML505_Video_DVI_Data<1>" LOC = "AC8"; ## 16 | NET "ML505_Video_DVI_Data<2>" LOC = "AN12"; ## 17 | NET "ML505_Video_DVI_Data<3>" LOC = "AP12"; ## 18 | NET "ML505_Video_DVI_Data<4>" LOC = "AA9"; ## 19 | NET "ML505_Video_DVI_Data<5>" LOC = "AA8"; ## 20 | NET "ML505_Video_DVI_Data<6>" LOC = "AM13"; ## 21 | NET "ML505_Video_DVI_Data<7>" LOC = "AN13"; ## 22 | NET "ML505_Video_DVI_Data<8>" LOC = "AA10"; ## 23 | NET "ML505_Video_DVI_Data<9>" LOC = "AB10"; ## 24 | NET "ML505_Video_DVI_Data<10>" LOC = "AP14"; ## 25 | NET "ML505_Video_DVI_Data<11>" LOC = "AN14"; ## 26 | NET "ML505_Video_DVI_GPIO1" LOC = "N30"; ## 27 | NET "ML505_Video_DVI_*" SLEW = FAST; 28 | 29 | ## Ignore timings on async I/O pins 30 | NET "ML505_Video_DVI_*" TIG; 31 | -------------------------------------------------------------------------------- /board/KC705/EthernetPHY.SGMII.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Ethernet PHY - Marvell Alaska Ultra 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14, 15, 117 5 | ## VCCO: 2.5V, 2.5V (VCC2V5_FPGA, VCC2V5_FPGA) 6 | ## Location: U37 7 | ## Vendor: Marvell 8 | ## Device: M88E1111 - BAB1C000 9 | ## MDIO-Address: 0x05 (---0 0111b) 10 | ## I²C-Address: I²C management mode is not enabled 11 | ## 12 | ## SGMII LVDS signal-pairs 13 | ## -------------------------- 14 | ## Bank: 117 15 | ## Quad117: 16 | ## RefClock0 SGMII RefClock (ICS844021I) 17 | ## RefClock1 KC705_SMA_RefClock 18 | ## Placement: 19 | ## Lane: Quad117.Channel1 (GTXE2_CHANNEL_X0Y9) 20 | ## ReferenceClock: 21 | ## RefClock: Quad117.MGTRefClock0 22 | ## Location: U2 (ICS844021I) 23 | ## Vendor: Integrated Circuit Systems 24 | #$ ## Device: ICS844021AGI-01LF 25 | ## Frequency: 125 MHz 26 | ## 27 | ## reference clocks 28 | ## -------------------------- 29 | NET "KC705_EthernetPHY_RefClock_125MHz_n" LOC = "G7"; ## {IN} U2.6 30 | NET "KC705_EthernetPHY_RefClock_125MHz_p" LOC = "G8"; ## {IN} U2.7 31 | NET "KC705_EthernetPHY_SGMII_TX_n" LOC = "J3"; ## {OUT} U37.A4 32 | NET "KC705_EthernetPHY_SGMII_TX_p" LOC = "J4"; ## {OUT} U37.A3 33 | NET "KC705_EthernetPHY_SGMII_RX_n" LOC = "H5"; ## {IN} U37.A8 34 | NET "KC705_EthernetPHY_SGMII_RX_p" LOC = "H6"; ## {IN} U37.A7 35 | -------------------------------------------------------------------------------- /board/ML605/Clock.UserClock.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================================================================================================= 4 | ## Board: Xilinx - Virtex 6 ML605 5 | ## FPGA: Xilinx Virtex 6 6 | ## Device: XC6VLX240T 7 | ## Package: FF1156 8 | ## Speedgrade: -1 9 | ## ============================================================================================================================================================= 10 | ## Clock Sources 11 | ## ============================================================================================================================================================= 12 | ## 13 | ## User Clock 14 | ## ============================================================================= 15 | ## Bank: 24 16 | ## VCCO: 2.5V (VCC2V5) 17 | ## Location: X5 single-ended clock socket 18 | ## Oscillator: 66 MHz 19 | ## Vendor: MMD Components 20 | ## Device: MBH2100H-66.000 MHz 21 | ## Frequency: 66 MHz, 100ppm 22 | NET "ML605_UserClock" LOC = "U23"; ## {IN} U11.5 23 | NET "ML605_UserClock" IOSTANDARD = LVCMOS25; 24 | ## 25 | NET "ML605_UserClock" TNM_NET = "TGRP_UserClock"; 26 | TIMESPEC "TS_UserClock" = PERIOD "TGRP_UserClock" 66 MHz HIGH 40 %; 27 | -------------------------------------------------------------------------------- /board/Atlys/GPIO.Switch.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## DIP-Switches 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: MISC, 0, 2, 3 8 | ## VCCO: 3.3V, 3.3V, 3.3, V1.8V 9 | ## Location: SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7 10 | ## ----------------------------------------------------------------------------- 11 | NET "Atlys_GPIO_Switches<0>" LOC = "A10"; ## {IN} SW0; high-active 12 | NET "Atlys_GPIO_Switches<1>" LOC = "D14"; ## {IN} SW1; high-active 13 | NET "Atlys_GPIO_Switches<2>" LOC = "C14"; ## {IN} SW2; high-active 14 | NET "Atlys_GPIO_Switches<3>" LOC = "P15"; ## {IN} SW3; high-active 15 | NET "Atlys_GPIO_Switches<4>" LOC = "P12"; ## {IN} SW4; high-active 16 | NET "Atlys_GPIO_Switches<5>" LOC = "R5"; ## {IN} SW5; high-active 17 | NET "Atlys_GPIO_Switches<6>" LOC = "T5"; ## {IN} SW6; high-active 18 | NET "Atlys_GPIO_Switches<7>" LOC = "E4"; ## {IN} SW7; high-active 19 | NET "Atlys_GPIO_Switches" IOSTANDARD = LVCMOS33; ## 20 | 21 | ## Ignore timings on async I/O pins 22 | NET "Atlys_GPIO_Switches" TIG; 23 | -------------------------------------------------------------------------------- /board/ZC706/GPIO.LED.xdc: -------------------------------------------------------------------------------- 1 | ## ============================================================================================================================================================= 2 | ## General Purpose I/O 3 | ## ============================================================================================================================================================= 4 | ## 5 | ## LEDs 6 | ## ----------------------------------------------------------------------------- 7 | ## Bank: 11, 33, 35 8 | ## VCCO: 2.5, 1.5, 1.5V (VADJ_FPGA, VCC1V5_FPGA, VCC1V5_FPGA) 9 | ## Location: Q30, Q9, Q8, Q7 10 | ## ----------------------------------------------------------------------------- 11 | ## {OUT} Q30; Bank 35; VCCO=VCC1V5_FPGA 12 | set_property PACKAGE_PIN A17 [get_ports ZC706_GPIO_LED[0]] 13 | ## {OUT} Q9; Bank 11; VCCO=VADJ_FPGA 14 | set_property PACKAGE_PIN W21 [get_ports ZC706_GPIO_LED[1]] 15 | ## {OUT} Q8; Bank 33; VCCO=VCC1V5_FPGA 16 | set_property PACKAGE_PIN G2 [get_ports ZC706_GPIO_LED[2]] 17 | ## {OUT} Q7; Bank 11; VCCO=VADJ_FPGA 18 | set_property PACKAGE_PIN Y21 [get_ports ZC706_GPIO_LED[3]] 19 | # set I/O standard 20 | set_property IOSTANDARD LVCMOS15 [get_ports ZC706_GPIO_LED[0]] 21 | set_property IOSTANDARD LVCMOS25 [get_ports ZC706_GPIO_LED[1]] 22 | set_property IOSTANDARD LVCMOS15 [get_ports ZC706_GPIO_LED[2]] 23 | set_property IOSTANDARD LVCMOS25 [get_ports ZC706_GPIO_LED[3]] 24 | # Ignore timings on async I/O pins 25 | set_false_path -to [get_ports -regexp {ZC706_GPIO_LED\[\d\]}] 26 | --------------------------------------------------------------------------------