├── LICENSE ├── README.md ├── clock_divider.v ├── debouncer.v ├── file_to_stim.v ├── glitch_filter.v ├── i2c_listen.v ├── mux2x.v ├── ram.v ├── right_shiftreg.v ├── shift_register.v ├── sr_latch.v ├── ts_buf.v ├── uart_in.v ├── uart_out.v ├── uds_counter.v └── up_counter.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/README.md -------------------------------------------------------------------------------- /clock_divider.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/clock_divider.v -------------------------------------------------------------------------------- /debouncer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/debouncer.v -------------------------------------------------------------------------------- /file_to_stim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/file_to_stim.v -------------------------------------------------------------------------------- /glitch_filter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/glitch_filter.v -------------------------------------------------------------------------------- /i2c_listen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/i2c_listen.v -------------------------------------------------------------------------------- /mux2x.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/mux2x.v -------------------------------------------------------------------------------- /ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/ram.v -------------------------------------------------------------------------------- /right_shiftreg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/right_shiftreg.v -------------------------------------------------------------------------------- /shift_register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/shift_register.v -------------------------------------------------------------------------------- /sr_latch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/sr_latch.v -------------------------------------------------------------------------------- /ts_buf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/ts_buf.v -------------------------------------------------------------------------------- /uart_in.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/uart_in.v -------------------------------------------------------------------------------- /uart_out.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/uart_out.v -------------------------------------------------------------------------------- /uds_counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/uds_counter.v -------------------------------------------------------------------------------- /up_counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hedgeberg/VerilogCommon/HEAD/up_counter.v --------------------------------------------------------------------------------