├── .DS_Store ├── lab1 ├── scu_add.zip ├── scu_r.zip ├── add.v ├── im.v ├── pc.v └── gpr.v ├── lab2 ├── scu_i.zip ├── scu_j.zip ├── scu_lwsw.zip └── dm.v ├── lab4 ├── ppu_beq.zip ├── ppu_j-jr-jal.zip └── ppu_beq_hazard.zip ├── lab3 ├── ppu_wb2ex.zip ├── ppu_wb2id.zip ├── ppu_mem2ex.zip ├── ppu_start8.zip └── ppu_halt+wb2ex.zip └── README.md /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/.DS_Store -------------------------------------------------------------------------------- /lab1/scu_add.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab1/scu_add.zip -------------------------------------------------------------------------------- /lab1/scu_r.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab1/scu_r.zip -------------------------------------------------------------------------------- /lab2/scu_i.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab2/scu_i.zip -------------------------------------------------------------------------------- /lab2/scu_j.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab2/scu_j.zip -------------------------------------------------------------------------------- /lab4/ppu_beq.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab4/ppu_beq.zip -------------------------------------------------------------------------------- /lab2/scu_lwsw.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab2/scu_lwsw.zip -------------------------------------------------------------------------------- /lab3/ppu_wb2ex.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab3/ppu_wb2ex.zip -------------------------------------------------------------------------------- /lab3/ppu_wb2id.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab3/ppu_wb2id.zip -------------------------------------------------------------------------------- /lab3/ppu_mem2ex.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab3/ppu_mem2ex.zip -------------------------------------------------------------------------------- /lab3/ppu_start8.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab3/ppu_start8.zip -------------------------------------------------------------------------------- /lab4/ppu_j-jr-jal.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab4/ppu_j-jr-jal.zip -------------------------------------------------------------------------------- /lab3/ppu_halt+wb2ex.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab3/ppu_halt+wb2ex.zip -------------------------------------------------------------------------------- /lab4/ppu_beq_hazard.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/heorion/ComputerOrganizationLab_NPU/HEAD/lab4/ppu_beq_hazard.zip -------------------------------------------------------------------------------- /lab1/add.v: -------------------------------------------------------------------------------- 1 | module add(a,b,c); 2 | 3 | output reg [31:0] c; 4 | input [31:0] a,b; 5 | 6 | always @ (*) 7 | begin 8 | c=a+b; 9 | end 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /lab1/im.v: -------------------------------------------------------------------------------- 1 | module im(instruction,pc); 2 | 3 | output reg [31:0] instruction; 4 | input [31:0] pc; 5 | reg [31:0] ins_memory[1023:0]; //4k指令存储器 6 | 7 | always@(*) 8 | begin 9 | 10 | instruction = ins_memory[pc[11:2]]; 11 | 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 西北工业大学计算机组成原理实验源码 2 | 3 | 个人留档，有需要可自提 4 | 5 | 我选这个课在2024年，以后可能会改题吧 6 | 7 | 不要一发题目立马提交，燕子会认为你是抄的，然后就开始整花活（也不知道以后她还教不教这门课） 8 | 9 | 老师人挺好的，就是这实验抄的人实在有点多 10 | 11 | ---------------- 12 | 以下为实验内容 13 | 14 | lab1:实现单周期cpu各模块，支持R型指令 15 | 16 | lab2:使单周期cpu支持部分I型指令，存取数指令，跳转指令 17 | 18 | lab3:完成5级流水线CPU，处理数据冒险 19 | 20 | lab4:处理控制冒险 21 | 22 | -------------------------------------------------------------------------------- /lab1/pc.v: -------------------------------------------------------------------------------- 1 | module pc(pc,clock,reset,npc); 2 | 3 | output reg [31:0] pc; //输出 4 | input clock; //输入，时钟信号 5 | input reset; //输入，复位信号 6 | input [31:0] npc; //输入，下一条指令地址 7 | 8 | always @ (posedge clock) 9 | begin 10 | 11 | if(!reset) 12 | pc <= 32'h00003000; 13 | else 14 | pc <= npc; 15 | 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /lab2/dm.v: -------------------------------------------------------------------------------- 1 | module dm(data_out,clock,mem_write,address,data_in); 2 | 3 | output [31:0] data_out; 4 | input clock; 5 | input mem_write; 6 | input [31:0] address; 7 | input [31:0] data_in; 8 | 9 | reg [31:0] data_memory[1023:0]; //4K数据存储器 10 | 11 | assign data_out = data_memory[address[11:2]]; 12 | 13 | always @ (posedge clock) 14 | begin 15 | 16 | if(mem_write == 1) 17 | data_memory[address[11:2]] = data_in; 18 | 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /lab1/gpr.v: -------------------------------------------------------------------------------- 1 | module gpr(a,b,clock,reg_write,num_write,rs,rt,data_write); 2 | 3 | output reg [31:0] a; 4 | output reg [31:0] b; 5 | input clock; 6 | input reg_write; 7 | input [4:0] rs; //读寄存器1 8 | input [4:0] rt; //读寄存器2 9 | input [4:0] num_write; //写寄存器 10 | input [31:0] data_write; //写数据 11 | reg [31:0] gp_registers[31:0]; //32个寄存器 12 | 13 | initial 14 | begin 15 | gp_registers[0] = 32'h00000000; 16 | end 17 | 18 | always@(*) //read 19 | begin 20 | a <= gp_registers[rs]; 21 | b <= gp_registers[rt]; 22 | end 23 | 24 | always@(posedge clock) //write 25 | begin 26 | if(reg_write&& num_write!=0) 27 | gp_registers[num_write] = data_write; 28 | end 29 | 30 | endmodule 31 | --------------------------------------------------------------------------------