├── .cproject ├── .gitignore ├── .project ├── .settings ├── language.settings.xml └── org.eclipse.cdt.core.prefs ├── LICENSE ├── Makefile ├── README.md ├── bsp ├── ATSAME70 │ ├── atsame70.cfg │ ├── boot │ ├── gpio_driver.h │ ├── memory.lds │ ├── multizone.cfg │ ├── newlib │ │ ├── crt0.S │ │ ├── newlib.c │ │ └── newlib.mk │ └── platform.h ├── EKRA6M3 │ ├── boot │ ├── gpio_driver.h │ ├── jlink.cfg │ ├── memory.lds │ ├── multizone.cfg │ ├── newlib │ │ ├── crt0.S │ │ ├── newlib.c │ │ └── newlib.mk │ ├── platform.h │ └── ra6m3.cfg ├── GD32307 │ ├── boot │ ├── gdlink.cfg │ ├── gpio_driver.h │ ├── memory.lds │ ├── multizone.cfg │ ├── newlib │ │ ├── crt0.S │ │ ├── newlib.c │ │ └── newlib.mk │ └── platform.h ├── IMXRT1020 │ ├── boot │ ├── cmsis-dap.cfg │ ├── gpio_driver.h │ ├── imxrt1020.cfg │ ├── memory.lds │ ├── multizone.cfg │ ├── newlib │ │ ├── crt0.S │ │ ├── newlib.c │ │ └── newlib.mk │ └── platform.h └── STM32F767 │ ├── boot │ ├── Makefile │ ├── boot.S │ └── linker.ld │ ├── gpio_driver.h │ ├── memory.lds │ ├── multizone.cfg │ ├── newlib │ ├── crt0.S │ ├── newlib.c │ └── newlib.mk │ ├── openocd.cfg │ ├── platform.h │ └── stlink.cfg ├── manual.pdf ├── multizone-sdk-arm ATSAME70.launch ├── multizone-sdk-arm EKRA6M3.launch ├── multizone-sdk-arm GD32307.launch ├── multizone-sdk-arm IMXRT1020.launch ├── multizone-sdk-arm STM32F767.launch ├── multizone.h ├── multizone.jar ├── zone1 ├── Makefile ├── linker.ld └── main.c ├── zone2 ├── Makefile ├── linker.ld └── main.c └── zone3 ├── Makefile ├── linker.ld ├── main.c ├── owi_sequence.c └── owi_sequence.h /.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.elf 3 | *.hex 4 | *.bin 5 | *.lst 6 | *.map 7 | *.siz 8 | 9 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | multizone-sdk-arm 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | 26 | 27 | -------------------------------------------------------------------------------- /.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | -------------------------------------------------------------------------------- /.settings/org.eclipse.cdt.core.prefs: -------------------------------------------------------------------------------- 1 | eclipse.preferences.version=1 2 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/BOARD/delimiter=\: 3 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/BOARD/operation=append 4 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/BOARD/value=${ConfigName} 5 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/GNU_ARM/delimiter=\: 6 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/GNU_ARM/operation=append 7 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/GNU_ARM/value=${HOME}/gcc-arm-none-eabi-8-2019-q3-update/bin 8 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/OPENOCD/delimiter=\: 9 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/OPENOCD/operation=append 10 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/OPENOCD/value=${HOME}/riscv-openocd-20210807 11 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/PATH/delimiter=\: 12 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/PATH/operation=replace 13 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/PATH/value=/bin\:/usr/local/bin\:/usr/bin 14 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/append=true 15 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.1438407601/appendContributed=true 16 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/BOARD/delimiter=\: 17 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/BOARD/operation=append 18 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/BOARD/value=${ConfigName} 19 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/GNU_ARM/delimiter=\: 20 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/GNU_ARM/operation=append 21 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/GNU_ARM/value=${HOME}/gcc-arm-none-eabi-8-2019-q3-update/bin 22 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/OPENOCD/delimiter=\: 23 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/OPENOCD/operation=append 24 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/OPENOCD/value=${HOME}/riscv-openocd-20210807 25 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/PATH/delimiter=\: 26 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/PATH/operation=replace 27 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/PATH/value=/bin\:/usr/local/bin\:/usr/bin 28 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/append=true 29 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.163250841/appendContributed=true 30 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/BOARD/delimiter=\: 31 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/BOARD/operation=append 32 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/BOARD/value=${ConfigName} 33 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/GNU_ARM/delimiter=\: 34 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/GNU_ARM/operation=append 35 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/GNU_ARM/value=${HOME}/gcc-arm-none-eabi-8-2019-q3-update/bin 36 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/OPENOCD/delimiter=\: 37 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/OPENOCD/operation=append 38 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/OPENOCD/value=${HOME}/riscv-openocd-20210807 39 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/PATH/delimiter=\: 40 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/PATH/operation=replace 41 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/PATH/value=/bin\:/usr/local/bin\:/usr/bin 42 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/append=true 43 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.316255072/appendContributed=true 44 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/BOARD/delimiter=\: 45 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/BOARD/operation=append 46 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/BOARD/value=${ConfigName} 47 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/GNU_ARM/delimiter=\: 48 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/GNU_ARM/operation=append 49 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/GNU_ARM/value=${HOME}/gcc-arm-none-eabi-8-2019-q3-update/bin 50 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/OPENOCD/delimiter=\: 51 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/OPENOCD/operation=append 52 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/OPENOCD/value=${HOME}/riscv-openocd-20210807 53 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/PATH/delimiter=\: 54 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/PATH/operation=replace 55 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/PATH/value=/bin\:/usr/local/bin\:/usr/bin 56 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/append=true 57 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931.954568101/appendContributed=true 58 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/BOARD/delimiter=\: 59 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/BOARD/operation=append 60 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/BOARD/value=${ConfigName} 61 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/GNU_ARM/delimiter=\: 62 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/GNU_ARM/operation=append 63 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/GNU_ARM/value=${HOME}/gcc-arm-none-eabi-8-2019-q3-update/bin 64 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/OPENOCD/delimiter=\: 65 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/OPENOCD/operation=append 66 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/OPENOCD/value=${HOME}/riscv-openocd-20210807 67 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/PATH/delimiter=\: 68 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/PATH/operation=replace 69 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/PATH/value=/bin\:/usr/local/bin\:/usr/bin 70 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/append=true 71 | environment/project/cdt.managedbuild.toolchain.gnu.cross.base.745704931/appendContributed=true 72 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | HEX FIVE SECURITY, INC. 2 | SOFTWARE EVALUATION AGREEMENT 3 | 4 | THE TERMS AND CONDITIONS CONTAINED HEREIN CONSTITUTE A LEGAL AGREEMENT. 5 | THIS AGREEMENT ("AGREEMENT") CONTAINS THE ENTIRE AGREEMENT BETWEEN YOU 6 | LICENSEE ("YOU") AND HEX FIVE SECURITY, INC. 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This Agreement is the entire agreement between you 135 | and Hex Five concerning the Software and all related documentation and 136 | supersedes any other prior or contemporaneous agreements or 137 | communications with respect to the Software and related documentation, 138 | whether written or oral. 139 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | ############################################################# 4 | # Platform definitions 5 | ############################################################# 6 | 7 | BOARD ?= STM32F767 8 | ifeq ($(BOARD),STM32F767) 9 | ARM_ARCH := armv7e-m 10 | ARM_CPU := cortex-m7 11 | ARM_FLOAT := soft 12 | ARM_FPU := fpv5-sp-d16 13 | else ifeq ($(BOARD),ATSAME70) 14 | ARM_ARCH := armv7e-m 15 | ARM_CPU := cortex-m7 16 | ARM_FLOAT := softfp 17 | ARM_FPU := fpv4-sp-d16 18 | else ifeq ($(BOARD),IMXRT1020) 19 | ARM_ARCH := armv7e-m 20 | ARM_CPU := cortex-m7 21 | ARM_FLOAT := soft 22 | ARM_FPU := fpv5-d16 23 | else ifeq ($(BOARD),EKRA6M3) 24 | ARM_ARCH := armv7e-m 25 | ARM_CPU := cortex-m4 26 | ARM_FLOAT := soft 27 | ARM_FPU := fpv5-sp-d16 28 | else ifeq ($(BOARD),GD32307) 29 | ARM_ARCH := armv7e-m 30 | ARM_CPU := cortex-m4 31 | ARM_FLOAT := soft 32 | ARM_FPU := fpv5-sp-d16 33 | else 34 | $(error Unsupported board $(BOARD)) 35 | endif 36 | 37 | ############################################################# 38 | # Arguments/variables available to all submakes 39 | ############################################################# 40 | 41 | export BOARD 42 | export ARM_ARCH 43 | export ARM_CPU 44 | export ARM_FLOAT 45 | export ARM_FPU 46 | 47 | ############################################################# 48 | # Toolchain definitions 49 | ############################################################# 50 | 51 | ifndef GNU_ARM 52 | $(error GNU_ARM (GNU Arm Embedded Toolchain) not set) 53 | endif 54 | 55 | export CROSS_COMPILE := $(abspath $(GNU_ARM))/arm-none-eabi- 56 | export CC := $(CROSS_COMPILE)gcc 57 | export OBJDUMP := $(CROSS_COMPILE)objdump 58 | export OBJCOPY := $(CROSS_COMPILE)objcopy 59 | export GDB := $(CROSS_COMPILE)gdb 60 | export AR := $(CROSS_COMPILE)ar 61 | export LD := $(CROSS_COMPILE)gcc 62 | 63 | ############################################################# 64 | # Rules for building multizone 65 | ############################################################# 66 | 67 | .PHONY: all 68 | all: clean 69 | $(MAKE) -C bsp/$(BOARD)/boot 70 | $(MAKE) -C zone1 71 | $(MAKE) -C zone2 72 | $(MAKE) -C zone3 73 | java -jar multizone.jar \ 74 | --arch $(BOARD) \ 75 | --config bsp/$(BOARD)/multizone.cfg \ 76 | --boot bsp/$(BOARD)/boot/boot.hex \ 77 | zone1/zone1.elf \ 78 | zone2/zone2.elf \ 79 | zone3/zone3.elf 80 | 81 | .PHONY: clean 82 | clean: 83 | $(MAKE) -C bsp/$(BOARD)/boot clean 84 | $(MAKE) -C zone1 clean 85 | $(MAKE) -C zone2 clean 86 | $(MAKE) -C zone3 clean 87 | rm -f multizone.hex 88 | 89 | ############################################################# 90 | # Load and debug variables and rules 91 | ############################################################# 92 | 93 | ifndef OPENOCD 94 | $(error OPENOCD not set) 95 | endif 96 | 97 | OPENOCD := $(abspath $(OPENOCD))/bin/openocd 98 | 99 | ifeq ($(BOARD),STM32F767) 100 | OPENOCDCFG1 ?= bsp/$(BOARD)/stlink.cfg 101 | OPENOCDCFG2 ?= bsp/$(BOARD)/openocd.cfg 102 | OPENOCDARGS += -f $(OPENOCDCFG1) -f $(OPENOCDCFG2) 103 | else ifeq ($(BOARD),ATSAME70) 104 | OPENOCDARGS += -f bsp/$(BOARD)/atsame70.cfg 105 | else ifeq ($(BOARD),IMXRT1020) 106 | OPENOCDCFG1 ?= bsp/$(BOARD)/cmsis-dap.cfg 107 | OPENOCDCFG2 ?= bsp/$(BOARD)/imxrt1020.cfg 108 | OPENOCDARGS += -f $(OPENOCDCFG1) -f $(OPENOCDCFG2) 109 | else ifeq ($(BOARD),EKRA6M3) 110 | OPENOCDCFG1 ?= bsp/$(BOARD)/jlink.cfg 111 | OPENOCDCFG2 ?= bsp/$(BOARD)/ra6m3.cfg 112 | OPENOCDARGS += -f $(OPENOCDCFG1) -f $(OPENOCDCFG2) 113 | else ifeq ($(BOARD),GD32307) 114 | OPENOCDCFG1 ?= bsp/$(BOARD)/gdlink.cfg 115 | OPENOCDARGS += -f $(OPENOCDCFG1) 116 | endif 117 | 118 | GDB_PORT ?= 3333 119 | GDB_LOAD_ARGS ?= --batch 120 | GDB_LOAD_CMDS += -ex "set mem inaccessible-by-default off" 121 | GDB_LOAD_CMDS += -ex "set remotetimeout 240" 122 | GDB_LOAD_CMDS += -ex "set arch $(BOARD):$(ARCH)" 123 | GDB_LOAD_CMDS += -ex "target extended-remote localhost:$(GDB_PORT)" 124 | GDB_LOAD_CMDS += -ex "monitor reset halt" 125 | GDB_LOAD_CMDS += -ex "monitor flash protect 0 64 last off" 126 | GDB_LOAD_CMDS += -ex "load" 127 | GDB_LOAD_CMDS += -ex "monitor resume" 128 | GDB_LOAD_CMDS += -ex "monitor shutdown" 129 | GDB_LOAD_CMDS += -ex "quit" 130 | 131 | .PHONY: load 132 | 133 | load: 134 | $(OPENOCD) $(OPENOCDARGS) & \ 135 | $(GDB) multizone.hex $(GDB_LOAD_ARGS) $(GDB_LOAD_CMDS) 136 | 137 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # multizone-sdk-arm 2 | MultiZone® Security for Arm® Cortex®-M Processors 3 | 4 | **MultiZone® Security** is the quick and safe way to add security and separation to your Arm Cortex-M processors. MultiZone software can retrofit existing designs. If you don’t have TrustZone, or if you require finer granularity than one secure world, you can take advantage of high security separation without the need for hardware and software redesign, eliminating the complexity associated with managing a hybrid hardware/software security scheme. Cortex-M legacy designs lack the physical resources to provide the necessary separation, thus leading to larger attack surface and increased likelihood of vulnerability. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multiple equally secure worlds. Unlike traditional solutions, MultiZone is self-contained, presents an extremely small attack surface, and it is policy driven, meaning that no coding is required – or in fact even allowed. 5 | 6 | MultiZone works with any Cortex-M0+, Cortex‑M3, Cortex‑M4, and Cortex‑M7 processors. 7 | 8 | This version of the GNU-based SDK supports the following development boards: 9 | 10 | - [GigaDevice GD32307C-EVAL evaluation kit (GD32F207 Cortex-M4 @120MHz)](https://www.gigadevice.com/products/microcontrollers/gd32-development-tools/gd32-evaluation-boards/) 11 | - [Microchip SMART SAM E70 Xplained evaluation kit (ATSAME70Q21 Cortex-M7 @300MHz)](http://www.microchip.com/developmenttools/productdetails/atsame70-xpld) 12 | - [NXP MIMXRT1020-EVK (i.MX RT1020 Cortex-M7 @500MHz)](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK) 13 | - [Renesas EK-RA6M3 (R7FA6M3AH3CFC Cortex-M4 @120MHz)](https://www.renesas.com/us/en/products/software-tools/boards-and-kits/eval-kits/ek-ra6m3.html) 14 | - [ST NUCLEO-F767ZI (STM32F767ZI Cortex-M7 @216MHz)](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html) 15 | 16 | 17 | ### SDK Installation ### 18 | 19 | The MultiZone SDK works with any versions of Linux, Windows, and Mac capable of running Java 1.8 or greater. The directions in this readme are specific to a fresh installation of Ubuntu 18.04.4 LTS. Other Linux distros are similar. 20 | 21 | **Linux prerequisites** 22 | 23 | ``` 24 | sudo apt update 25 | sudo apt install make default-jre gtkterm 26 | ``` 27 | Note: GtkTerm is optional and required only to connect to the reference application via UART. It is not required to build, debug, and load the MultiZone software. Any other serial terminal application of choice would do. 28 | 29 | **GNU Arm Embedded Toolchain** 30 | 31 | Hex Five reference version: 8-2019-q3-update Linux 64-bit July 10, 2019 32 | ``` 33 | cd ~ 34 | wget http://developer.arm.com/-/media/Files/downloads/gnu-rm/8-2019q3/RC1.1/gcc-arm-none-eabi-8-2019-q3-update-linux.tar.bz2 35 | tar -xvf gcc-arm-none-eabi-8-2019-q3-update-linux.tar.bz2 36 | ``` 37 | 38 | **OpenOCD on-chip debugger** 39 | 40 | Hex Five reference build: GNU MCU Eclipse 0.10.0 41 | ``` 42 | cd ~ 43 | wget http://hex-five.com/wp-content/uploads/2020/02/gnu-mcu-openocd-20190827.tar.xz 44 | tar -xvf gnu-mcu-openocd-20190827.tar.xz 45 | ``` 46 | 47 | **Linux USB udev rules** 48 | 49 | ``` 50 | sudo vi /etc/udev/rules.d/99-openocd.rules 51 | 52 | # STMicroelectronics ST-LINK/V2.1 53 | SUBSYSTEM=="tty", ATTRS{idVendor}=="0483",ATTRS{idProduct}=="374b", MODE="664", GROUP="plugdev" 54 | SUBSYSTEM=="usb", ATTRS{idVendor}=="0483",ATTRS{idProduct}=="374b", MODE="664", GROUP="plugdev" 55 | 56 | # Atmel Corp. Xplained Pro board debugger and programmer 57 | SUBSYSTEM=="tty", ATTRS{idVendor}=="03eb",ATTRS{idProduct}=="2111", MODE="664", GROUP="plugdev" 58 | SUBSYSTEM=="usb", ATTRS{idVendor}=="03eb",ATTRS{idProduct}=="2111", MODE="664", GROUP="plugdev" 59 | 60 | # NXP MIMXRT1020-EVK 61 | SUBSYSTEM=="tty", ATTRS{idVendor}=="0d28",ATTRS{idProduct}=="0204", MODE="664", GROUP="plugdev" 62 | SUBSYSTEM=="usb", ATTRS{idVendor}=="0d28",ATTRS{idProduct}=="0204", MODE="664", GROUP="plugdev" 63 | 64 | # CMSIS-DAP compatible adapters 65 | ATTRS{product}=="*CMSIS-DAP*", MODE="664", GROUP="plugdev" 66 | ``` 67 | Reboot for these changes to take effect. 68 | 69 | **MultiZone Security SDK** 70 | 71 | ``` 72 | cd ~ 73 | wget https://github.com/hex-five/multizone-sdk-arm/archive/master.zip 74 | unzip master.zip 75 | ``` 76 | 77 | ### Build & load the MultiZone reference application ### 78 | 79 | Connect the target board to the development machine as indicated in its user manual. 80 | 81 | 'ls bsp' shows the list of supported targets: ATSAME70 EKRA6M3 GD32307 IMXRT1020 STM32F767. 82 | 83 | Assign one of these values to the BOARD variable - default is STM32F767. 84 | 85 | ``` 86 | cd ~/multizone-sdk-arm 87 | export GNU_ARM=~/gcc-arm-none-eabi-8-2019-q3-update/bin 88 | export OPENOCD=~/gnu-mcu-openocd-20190827 89 | export BOARD=ATSAME70 90 | make 91 | make load 92 | ``` 93 | 94 | 95 | ### Run the MultiZone reference application ### 96 | 97 | Connect the board UART port as indicated in its user manual. 98 | 99 | Start the serial terminal console (GtkTerm) and connect to /dev/ttyACM0 at 115200-8-N-1 100 | 101 | Hit the enter key a few times until the cursor 'Z1 >' appears on the screen 102 | 103 | Enter 'restart' to display the splash screen 104 | 105 | Hit enter again to show the list of available commands 106 | 107 | ``` 108 | ===================================================================== 109 | Hex Five MultiZone® Security 110 | Copyright© 2020 Hex Five Security, Inc. - All Rights Reserved 111 | ===================================================================== 112 | This version of MultiZone® Security is meant for evaluation purposes 113 | only. As such, use of this software is governed by the Evaluation 114 | License. There may be other functional limitations as described in 115 | the evaluation SDK documentation. The commercial version of the 116 | software does not have these restrictions. 117 | ===================================================================== 118 | Implementer : 0x41, Arm. 119 | Variant : 0x1, Revision 1. 120 | PartNo : 0xC27, Cortex-M7. 121 | Revision : 0x1, Patch 1. 122 | 123 | Z1 > 124 | Commands: yield send recv mpu load store exec stats timer restart 125 | 126 | Z1> 127 | ``` 128 | 129 | ### Optional: Eclipse CDT Project ### 130 | This repository includes an optional Eclipse CDT project for developers familiar with this IDE. No additional plugins are required to build and upload MultiZone to the target. The [OpenOCD debugging plug-in](https://eclipse-embed-cdt.github.io/debug/openocd) is optional and recommended. 131 | 132 | **Eclipse project Setup** 133 | 134 | File > Open Projects from File System > Import source: ~/multizone-sdk-arm 135 | 136 | Project > Properties > C/C++ Build > Environment: set GNU_ARM and OPENOCD variables according to your installation 137 | 138 | ![alt text](https://hex-five.com/wp-content/uploads/multizone-eclipse-proj.png) 139 | 140 | 141 | ### Technical Specs ### 142 | | | 143 | |---| 144 | | Up to 8 separated equally secure worlds – hardware-enforced, software-defined | 145 | | Up to 16 memory-mapped resources per zone – i.e. flash, ram, rom, i/o, etc. | 146 | | Scheduler: preemptive, cooperative, round robin, configurable tick | 147 | | Secure interzone communications based on messages – no shared memory | 148 | | Built-in trap & emulation for privileged instructions – SVC, MRS, MSR, CPS, WFE, WFI | 149 | | Support for secure user-mode interrupt handlers mapped to zones – up to 128 sources | 150 | | Support for Wait For Interrupt and CPU suspend mode for low power applications | 151 | | Formally verifiable runtime ~2KB, 100% written in assembly, no 3rd-party dependencies | 152 | | C library wrapper for protected mode execution – optional for high speed / low-latency | 153 | | Hardware requirements: Arm Cortex-M0+/M3/M4/M7 processor w/ Memory Protection Unit | 154 | | System requirements: 4KB for program, 2KB for data - CPU overhead < 0.01% | 155 | | Development environment: any versions of Linux, Windows, Mac running Java 1.8 | 156 | 157 | 158 | ### Additional Resources ### 159 | 160 | - [MultiZone Reference Manual](http://github.com/hex-five/multizone-sdk-arm/blob/master/manual.pdf) 161 | - [MultiZone Datasheet](http://hex-five.com/wp-content/uploads/2020/02/multizone-cortexm-datasheet-20200218.pdf) 162 | - [Frequently Asked Questions](http://hex-five.com/faq/) 163 | - Contact Hex Five http://hex-five.com/contact 164 | 165 | 166 | ### Legalities ### 167 | 168 | Please remember that export/import and/or use of strong cryptography software, providing cryptography hooks, or even just communicating technical details about cryptography software is illegal in some parts of the world. So when you import this software to your country, re-distribute it from there or even just email technical suggestions or even source patches to the authors or other people you are strongly advised to pay close attention to any laws or regulations which apply to you. Hex Five Security, Inc. and the authors of the software included in this repository are not liable for any violations you make here. So be careful, it is your responsibility. 169 | 170 | 171 | _Arm, Cortex, and TrustZone are registered trademarks of Arm Limited._ 172 | 173 | _MultiZone is a registered trademark of Hex Five Security, Inc._ 174 | 175 | _MultiZone technology is protected by patents US 11,151,262 and PCT/US2019/038774_ 176 | -------------------------------------------------------------------------------- /bsp/ATSAME70/atsame70.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # Atmel SAME70 Xplained evaluation kit. 3 | # http://www.atmel.com/tools/ATSAME70-XPLD.aspx 4 | # 5 | # Connect using the EDBG chip on the dev kit over USB 6 | source [find interface/cmsis-dap.cfg] 7 | 8 | set CHIPNAME atsame70q21 9 | 10 | source [find target/atsamv.cfg] 11 | 12 | reset_config srst_only 13 | -------------------------------------------------------------------------------- /bsp/ATSAME70/boot: -------------------------------------------------------------------------------- 1 | ../STM32F767/boot -------------------------------------------------------------------------------- /bsp/ATSAME70/gpio_driver.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef GPIO_DRIVER_H 4 | #define GPIO_DRIVER_H 5 | 6 | #define LED_INIT(_X_) \ 7 | { \ 8 | /* Enable PIO to control PIN8 of PIOC */ \ 9 | PIOC_REG(PIO_PER) |= (1<<_X_); \ 10 | /* Enable the output on PIN8 line of PIOC */ \ 11 | PIOC_REG(PIO_OER) |= (1<<_X_); \ 12 | } 13 | 14 | #define LED_SET(_X_) PIOC_REG(PIO_CODR) |= (1<<_X_) 15 | 16 | #define LED_CLR(_X_) PIOC_REG(PIO_SODR) |= (1<<_X_) 17 | 18 | #define LED_OUT(_X_) (PIOC_REG(PIO_ODSR) & (1<<_X_)) != (1<<_X_) 19 | 20 | #define BTN_INIT(_X_) \ 21 | { \ 22 | PIOA_REG(PIO_IDR) = (1<<_X_); \ 23 | /* Enable PULL-UP on PA11(SW0_PIN) of PIOA */ \ 24 | PIOA_REG(PIO_PUER) = (1<<_X_); \ 25 | /* Enable DE-GLITCH & DEBOUNCE on PA11(SW0_PIN) of PIOA */ \ 26 | PIOA_REG(PIO_IFER) = (1<<_X_); \ 27 | PIOA_REG(PIO_IFSCER) = (1<<_X_); \ 28 | /* Read interrupt status to clear pending */ \ 29 | PIOA_REG(PIO_ISR); \ 30 | PIOA_REG(PIO_IMR); \ 31 | /* Enable the input on PA11(SW0_PIN) of PIOA */ \ 32 | PIOA_REG(PIO_ODR) = (1<<_X_); \ 33 | PIOA_REG(PIO_PER) = (1<<_X_); \ 34 | /* Configure interrupt of PA11(SW0) as edge-detection event*/ \ 35 | PIOA_REG(PIO_AIMER) = (1<<_X_); \ 36 | PIOA_REG(PIO_FELLSR) = (1<<_X_); \ 37 | PIOA_REG(PIO_ESR) = (1<<_X_); \ 38 | /* Enable interrupt on input PA11(SW0_PIN) of PIOA */ \ 39 | PIOA_REG(PIO_IER) = (1<<_X_); \ 40 | } 41 | 42 | #define BTN_IRQ_CLR() \ 43 | { \ 44 | /* Read interrupt status to clear pending */ \ 45 | PIOA_REG(PIO_ISR); \ 46 | PIOA_REG(PIO_IMR); \ 47 | } 48 | 49 | #define SPI_INIT(_X_, _Y_, _Z_) \ 50 | { \ 51 | /* Enable PIO to control PD11, PD27 of PIOD */ \ 52 | PIOD_REG(PIO_PER) |= (1 << _Y_) | (1 << _X_); \ 53 | /* Enable PIO to control PA6 of PIOA */ \ 54 | PIOA_REG(PIO_PER) |= (1 << _Z_); \ 55 | /* Enable the output on PD27 and PA6 */ \ 56 | PIOD_REG(PIO_OER) |= (1 << _Y_); \ 57 | PIOA_REG(PIO_OER) |= (1 << _Z_); \ 58 | /* Enable the input on PD11 of PIOD */ \ 59 | PIOD_REG(PIO_ODR) |= (1 << _X_); \ 60 | /* Enable the pull-up input on PD11 of PIOD */ \ 61 | PIOD_REG(PIO_PUER) |= (1 << _X_); \ 62 | } 63 | 64 | #define SPI_TDO_SET(_X_) PIOA_REG(PIO_SODR) |= (0x1 << _X_) 65 | 66 | #define SPI_TDO_CLR(_X_) PIOA_REG(PIO_CODR) |= (0x1 << _X_) 67 | 68 | #define SPI_TDI_BIT(_X_) (PIOD_REG(PIO_PDSR) >> _X_) & 1U 69 | 70 | #define SPI_TCK_LOW(_X_) PIOD_REG(PIO_SODR) |= (0x1 << _X_) 71 | #define SPI_TCK_HIGH(_X_) PIOD_REG(PIO_CODR) |= (0x1 << _X_) 72 | 73 | #define UART_IRQ_CLR() \ 74 | { \ 75 | } 76 | 77 | #define UART_IRQ_RX() (USART1_REG(US_CSR) & US_CSR_RXRDY) 78 | 79 | 80 | #endif 81 | -------------------------------------------------------------------------------- /bsp/ATSAME70/memory.lds: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2019 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | flash = 0x00400000; 4 | itcm = 0x00400000; 5 | dtcm = 0x20402000; /* DTCM 0x2000_0000 64K */ 6 | 7 | -------------------------------------------------------------------------------- /bsp/ATSAME70/multizone.cfg: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | # MultiZone reserved memory: 8K @0x00400000, 8K @0x20400000 4 | 5 | Tick = 10 # ms 6 | 7 | Zone = 1 8 | irq = 30 9 | base = 0x00408000; size = 32K; rwx = rx # FLASH 10 | base = 0x20402000; size = 4K; rwx = rw # RAM 11 | base = 0x40028000; size = 0x200; rwx = rw # UART 12 | base = 0x40088100; size = 0x20; rwx = rw # MATRIX 13 | base = 0x400E0600; size = 0x80; rwx = rw # PMC 14 | base = 0x400E0C00; size = 0x20; rwx = rw # EFC 15 | base = 0x400E0E00; size = 0x80; rwx = rw # PIOA (UART RX) 16 | base = 0x400E1000; size = 0x80; rwx = rw # PIOB (UART TX) 17 | 18 | Zone = 2 19 | irq = 26 20 | base = 0x00410000; size = 32K; rwx = rx # FLASH 21 | base = 0x20403000; size = 4K; rwx = rw # RAM 22 | base = 0x400E0E00; size = 0x100; rwx = rw # PIOA (BUTTON) 23 | base = 0x400E1200; size = 0x40; rwx = rw # PIOC (LED) 24 | 25 | Zone = 3 26 | base = 0x00418000; size = 32K; rwx = rx # FLASH 27 | base = 0x20404000; size = 4K; rwx = rw # RAM 28 | base = 0x400E0E00; size = 0x40; rwx = rw # PIOA (SPI_TDO) 29 | base = 0x400E1400; size = 0x80; rwx = rw # PIOD (SPI_TDI & SPI_TCK) 30 | -------------------------------------------------------------------------------- /bsp/ATSAME70/newlib/crt0.S: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | # Make sure that the GNU assembler is using a modern syntax for Arm THUMB. 4 | .syntax unified 5 | .arch armv7e-m 6 | 7 | /** 8 | * These are the addresses for the initialized (data) and uninitialized (bss) 9 | * variables. The initialized variables will be copied from FLASH to RAM. The 10 | * uninitialized variables will be set to 0. These addresses are set in the 11 | * linker file. 12 | */ 13 | .word __data_vma_start 14 | .word __data_start 15 | .word __data_end 16 | .word __bss_start 17 | .word __bss_end 18 | 19 | # TODO - Consider to move the vector table definition to the bsp 20 | # since the vector table is specific to the CPU/BOARD 21 | # ------------------------------------------------------------- 22 | .section .text.isr_vector 23 | .align 2 24 | .globl __isr_vector 25 | # ------------------------------------------------------------- 26 | __isr_vector: 27 | .word __end_stack // MSP definition 28 | .word reset_handler // Reset_Handler 29 | .word nmi_handler // NMI_Handler 30 | .word hardfault_handler // HardFault_Handler 31 | .word memmanage_handler // MemManage_Handler 32 | .word busfault_handler // BusFault_Handler 33 | .word usagefault_handler // UsageFault_Handler 34 | .word 0 // Not Defined 35 | .word 0 // Not Defined 36 | .word 0 // Not Defined 37 | .word 0 // Not Defined 38 | .word svc_handler // SVC_Handler 39 | .word debugmon_handler // DebugMon_Handler 40 | .word 0 // Not Defined 41 | .word pendsv_handler // PendSV_Handler 42 | .word systick_handler // SysTick_Handler 43 | .rept 10 // Repeat for 44 | .word _def_handler // IRQ0_Handler to IRQ39_Handler 45 | .endr 46 | .word btn_handler 47 | .rept 20 // Repeat for 48 | .word uart_handler // IRQ0_Handler to IRQ39_Handler 49 | .endr 50 | .size __isr_vector, . - __isr_vector 51 | 52 | # ------------------------------------------------------------- 53 | .align 2 54 | .section .text.init 55 | .global reset_handler 56 | .type reset_handler, %function 57 | # ------------------------------------------------------------- 58 | reset_handler: 59 | ldr sp, =__end_stack /* set stack pointer */ 60 | 61 | // Copy the initialized global variables to RAM 62 | mov r0, #0 63 | ldr r1, = __data_start 64 | ldr r2, = __data_end 65 | ldr r3, = __data_vma_start 66 | b loopcopy_data 67 | 68 | copy_data: 69 | ldr r4, [r3, r0] 70 | str r4, [r1, r0] 71 | adds r0, r0, #4 72 | 73 | loopcopy_data: 74 | add r4, r1, r0 75 | cmp r4, r2 76 | bcc copy_data 77 | 78 | // Fill uninitialized variables with zeros 79 | mov r0, #0 80 | ldr r1, = __bss_start 81 | ldr r2, = __bss_end 82 | b loopfill_zerobss 83 | 84 | fill_zerobss: 85 | str r0, [r1] 86 | add r1, r1, #4 87 | 88 | loopfill_zerobss: 89 | cmp r1, r2 90 | bcc fill_zerobss 91 | 92 | // Call the libc init function 93 | bl __libc_init_array 94 | 95 | // Call the main function 96 | bl main 97 | 98 | 99 | .global _init 100 | .type _init, %function 101 | _init: 102 | bx lr 103 | .size _init, .-_init 104 | 105 | .global _fini 106 | .type _fini, %function 107 | _fini: 108 | bx lr 109 | .size _fini, .-_fini 110 | 111 | # ------------------------------------------------------------- 112 | .section .text.nmi_handler 113 | .type nmi_handler, %function 114 | .weak nmi_handler 115 | .thumb_set nmi_handler,_def_handler 116 | 117 | # ------------------------------------------------------------- 118 | .section .text.hardfault_handler 119 | .type hardfault_handler, %function 120 | .weak hardfault_handler 121 | .thumb_set hardfault_handler,_def_handler 122 | 123 | # ------------------------------------------------------------- 124 | .section .text.memmanage_handler 125 | .type memmanage_handler, %function 126 | .weak memmanage_handler 127 | .thumb_set memmanage_handler,_def_handler 128 | 129 | # ------------------------------------------------------------- 130 | .section .text.busfault_handler 131 | .type busfault_handler, %function 132 | .weak busfault_handler 133 | .thumb_set busfault_handler,_def_handler 134 | 135 | # ------------------------------------------------------------- 136 | .section .text.usagefault_handler 137 | .type usagefault_handler, %function 138 | .weak usagefault_handler 139 | .thumb_set usagefault_handler,_def_handler 140 | 141 | # ------------------------------------------------------------- 142 | .section .text.svc_handler 143 | .type svc_handler, %function 144 | .weak svc_handler 145 | .thumb_set svc_handler,_def_handler 146 | 147 | # ------------------------------------------------------------- 148 | .section .text.debugmon_handler 149 | .type debugmon_handler, %function 150 | .weak debugmon_handler 151 | .thumb_set debugmon_handler,_def_handler 152 | 153 | # ------------------------------------------------------------- 154 | .section .text.pendsv_handler 155 | .type pendsv_handler, %function 156 | .weak pendsv_handler 157 | .thumb_set pendsv_handler,_def_handler 158 | 159 | # ------------------------------------------------------------- 160 | .section .text.systick_handler 161 | .type systick_handler, %function 162 | .weak systick_handler 163 | .thumb_set systick_handler,_def_handler 164 | 165 | 166 | # ------------------------------------------------------------- 167 | .section .text.btn_handler 168 | .type btn_handler, %function 169 | .weak btn_handler 170 | .thumb_set btn_handler,_def_handler 171 | 172 | # ------------------------------------------------------------- 173 | .section .text.uart_handler 174 | .type uart_handler, %function 175 | .weak uart_handler 176 | .thumb_set uart_handler,_def_handler 177 | 178 | # ------------------------------------------------------------- 179 | .section .text._def_handler 180 | .type _def_handler, %function 181 | # ------------------------------------------------------------- 182 | # ------------------------------------------------------------- 183 | _def_handler: # Default Handler (Exception happen while starting) 184 | # ------------------------------------------------------------- 185 | b reset_handler // restart 186 | -------------------------------------------------------------------------------- /bsp/ATSAME70/newlib/newlib.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include 9 | 10 | // ---------------------------------------------------------------------------- 11 | int _close(int file) { 12 | // ---------------------------------------------------------------------------- 13 | 14 | return -1; 15 | } 16 | 17 | // ---------------------------------------------------------------------------- 18 | int _fstat(int file, struct stat *st) { 19 | // ---------------------------------------------------------------------------- 20 | 21 | st->st_mode = S_IFCHR; 22 | return 0; 23 | } 24 | 25 | // ---------------------------------------------------------------------------- 26 | void * _sbrk(int incr) { 27 | // ---------------------------------------------------------------------------- 28 | 29 | extern char _end[]; 30 | extern char _heap_end[]; 31 | static char *_heap_ptr = _end; 32 | 33 | if ((_heap_ptr + incr < _end) || (_heap_ptr + incr > _heap_end)) 34 | return (void *) -1; 35 | 36 | _heap_ptr += incr; 37 | return _heap_ptr - incr; 38 | } 39 | 40 | // ---------------------------------------------------------------------------- 41 | int _isatty(int file) { 42 | // ---------------------------------------------------------------------------- 43 | 44 | return (file == STDIN_FILENO || file == STDOUT_FILENO || file == STDERR_FILENO) ? 1 : 0; 45 | 46 | } 47 | 48 | // ---------------------------------------------------------------------------- 49 | int _lseek(int file, off_t ptr, int dir) { 50 | // ---------------------------------------------------------------------------- 51 | 52 | return 0; 53 | } 54 | 55 | // ---------------------------------------------------------------------------- 56 | int _open(const char* name, int flags, int mode) { 57 | // ---------------------------------------------------------------------------- 58 | 59 | if (strcmp(name, "UART")==0){ 60 | 61 | uint32_t tmp; 62 | 63 | tmp = EFC_REG(EEFC_FMR); 64 | tmp &= ~EEFC_FMR_FWS_Msk; 65 | tmp |= EEFC_FMR_FWS(CONF_EFC_WAIT_STATE); 66 | EFC_REG(EEFC_FMR) = tmp; 67 | 68 | /*_pmc_init*/ 69 | uint32_t data = 0; 70 | 71 | data = PMC_REG(CKGR_MOR) & ~CKGR_MOR_MOSCXTBY; 72 | data |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(62); 73 | PMC_REG(CKGR_MOR) = data; 74 | while (!((PMC_REG(PMC_SR) & PMC_SR_MOSCXTS) > 0)) { 75 | /* Wait until the XTAL to stabilize */ 76 | } 77 | 78 | PMC_REG(CKGR_MOR) |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL); 79 | 80 | /* Peripheral clock enable */ 81 | data = CKGR_PLLAR_MULA(CONF_PLLACK_MUL - 1) | CKGR_PLLAR_DIVA(CONF_PLLACK_DIV) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT); 82 | /* Stop PLL first */ 83 | tmp = PMC_REG(CKGR_PLLAR); 84 | tmp &= ~CKGR_PLLAR_MULA_Msk; 85 | tmp |= CKGR_PLLAR_MULA(0); 86 | PMC_REG(CKGR_PLLAR) = tmp; 87 | 88 | PMC_REG(CKGR_PLLAR) = (CKGR_PLLAR_ONE | data); 89 | while (!((PMC_REG(PMC_SR) & PMC_SR_LOCKA) > 0)) { 90 | /* Wait until PLLACK stabilize */ 91 | } 92 | 93 | tmp = PMC_REG(PMC_MCKR); 94 | tmp &= ~PMC_MCKR_PRES_Msk; 95 | tmp |= PMC_MCKR_PRES(CONF_MCKR_PRESC); 96 | PMC_REG(PMC_MCKR) = tmp; 97 | while (!(PMC_REG(PMC_SR) & PMC_SR_MCKRDY) > 0) { 98 | /* Wait until master clock is ready */ 99 | } 100 | 101 | tmp = PMC_REG(PMC_MCKR); 102 | tmp &= ~PMC_MCKR_MDIV_Msk; 103 | tmp |= PMC_MCKR_MDIV(CONF_MCK_DIV); 104 | 105 | PMC_REG(PMC_MCKR) = tmp; 106 | while (!(PMC_REG(PMC_SR) & PMC_SR_MCKRDY) > 0) { 107 | /* Wait until master clock is ready */ 108 | } 109 | 110 | tmp = PMC_REG(PMC_MCKR); 111 | tmp &= ~PMC_MCKR_CSS_Msk; 112 | tmp |= PMC_MCKR_CSS(CONF_CLK_GEN_MCKR_SRC); 113 | PMC_REG(PMC_MCKR)= tmp; 114 | while (!(PMC_REG(PMC_SR) & PMC_SR_MCKRDY) > 0) { 115 | /* Wait until master clock is ready */ 116 | } 117 | 118 | PMC_REG(PMC_PCER0) = 1 << ID_USART1; 119 | 120 | /**UART GPIO Configuration 121 | * UART_RX 122 | * UART_TX 123 | */ 124 | PIOA_REG(PIO_ABCDSR0) &= ~(1U << USART1_RX_PIN); 125 | PIOA_REG(PIO_ABCDSR1) &= ~(1U << USART1_RX_PIN); 126 | PIOA_REG(PIO_PDR) = 1U << USART1_RX_PIN; 127 | 128 | MATRIX_REG(CCFG_SYSIO) |= 1U << USART1_TX_PIN; 129 | 130 | PIOB_REG(PIO_ABCDSR0) |= 1U << USART1_TX_PIN; 131 | PIOB_REG(PIO_ABCDSR1) |= 1U << USART1_TX_PIN; 132 | PIOB_REG(PIO_PDR) = 1U << USART1_TX_PIN; 133 | 134 | /* Configure the USART driver */ 135 | /* Disable the Write Protect. */ 136 | USART1_REG(US_WPMR) = US_WPMR_WPKEY_PASSWD; 137 | /* Reset registers that could cause unpredictable behavior after reset. */ 138 | USART1_REG(US_MR) = 0x0; 139 | USART1_REG(US_RTOR) = 0x0; 140 | USART1_REG(US_TTGR) = 0x0; 141 | 142 | /* Disable and reset TX and RX. */ 143 | USART1_REG(US_CR) = (US_CR_RSTRX | US_CR_RXDIS | US_CR_RSTTX | US_CR_TXDIS); 144 | /* Reset status bits. */ 145 | USART1_REG(US_CR) = US_CR_RSTSTA; 146 | /* Turn off RTS and DTR if exist. */ 147 | USART1_REG(US_CR) = US_CR_USART_RTSDIS; 148 | 149 | USART1_REG(US_MR) = US_MR_Val; // 150 | USART1_REG(US_BRGR) = (US_BRGR_Val); 151 | 152 | USART1_REG(US_CR) = (US_CR_RXEN | US_CR_TXEN); 153 | 154 | USART1_REG(US_IER) = US_IMR_RXRDY; 155 | 156 | return 0; 157 | } 158 | 159 | return -1; 160 | } 161 | 162 | // ---------------------------------------------------------------------------- 163 | int _read(int file, char *ptr, size_t len) { 164 | // ---------------------------------------------------------------------------- 165 | if (isatty(file)) { 166 | 167 | ssize_t count = 0; 168 | int rxfifo = -1; 169 | 170 | while( count 0)) {;} 192 | 193 | USART1_REG(US_THR) = (char) buff[i]; 194 | 195 | if (buff[i] == '\n') { 196 | while(!((USART1_REG(US_CSR) & US_CSR_TXRDY) > 0)) {;} 197 | USART1_REG(US_THR) = (char) '\r'; 198 | } 199 | } 200 | 201 | return len; 202 | 203 | } 204 | 205 | return -1; 206 | } -------------------------------------------------------------------------------- /bsp/ATSAME70/newlib/newlib.mk: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | .PHONY: all 4 | all: $(TARGET) 5 | 6 | ASM_SRCS += $(NEWLIB_DIR)/crt0.S 7 | C_SRCS += $(NEWLIB_DIR)/newlib.c 8 | 9 | INCLUDES += -I$(PLATFORM_DIR) 10 | 11 | MCUFLAGS += -march=$(ARM_ARCH) 12 | MCUFLAGS += -mcpu=$(ARM_CPU) 13 | MCUFLAGS += -mfloat-abi=$(ARM_FLOAT) 14 | MCUFLAGS += -mfpu=$(ARM_FPU) 15 | 16 | LDFLAGS += -T $(PLATFORM_DIR)/memory.lds 17 | LDFLAGS += -T $(LINKER_SCRIPT) 18 | LDFLAGS += -static $(MCUFLAGS) 19 | LDFLAGS += -mthumb 20 | LDFLAGS += --specs=nano.specs 21 | LDFLAGS += -nostartfiles 22 | LDFLAGS += -Xlinker --gc-sections 23 | 24 | ASM_OBJS := $(ASM_SRCS:.S=.o) 25 | C_OBJS := $(C_SRCS:.c=.o) 26 | 27 | LINK_OBJS += $(ASM_OBJS) $(C_OBJS) 28 | LINK_DEPS += $(LINKER_SCRIPT) 29 | 30 | CLEAN_OBJS += $(TARGET) $(LINK_OBJS) 31 | 32 | CFLAGS += -g -gdwarf-4 33 | CFLAGS += -ffunction-sections -fdata-sections -fomit-frame-pointer 34 | CFLAGS += $(MCUFLAGS) 35 | CFLAGS += -O0 36 | 37 | HEX = $(subst .elf,.hex,$(TARGET)) 38 | LST = $(subst .elf,.lst,$(TARGET)) 39 | CLEAN_OBJS += $(HEX) 40 | CLEAN_OBJS += $(LST) 41 | 42 | $(TARGET): $(LINK_OBJS) $(LINK_DEPS) 43 | $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) $(LDFLAGS) -o $@ 44 | $(OBJCOPY) -O ihex $(TARGET) $(HEX) 45 | $(OBJDUMP) --all-headers --demangle --disassemble --file-headers --wide -D $(TARGET) > $(LST) 46 | 47 | $(ASM_OBJS): %.o: %.S $(HEADERS) 48 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 49 | 50 | $(C_OBJS): %.o: %.c $(HEADERS) 51 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 52 | 53 | .PHONY: clean 54 | clean: 55 | rm -f $(CLEAN_OBJS) 56 | 57 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/boot: -------------------------------------------------------------------------------- 1 | ../STM32F767/boot -------------------------------------------------------------------------------- /bsp/EKRA6M3/gpio_driver.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef GPIO_DRIVER_H 4 | #define GPIO_DRIVER_H 5 | 6 | #define LED_INIT(_X_) \ 7 | { \ 8 | /* Write to specific pin's PFS register */ \ 9 | R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos); \ 10 | } 11 | 12 | #define LED_SET(_X_) R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos) | \ 13 | (1U << R_PmnPFS_PIDR_Pos) | (1U << R_PmnPFS_PODR_Pos); 14 | 15 | #define LED_CLR(_X_) R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos); 16 | 17 | #define LED_OUT(_X_) (R_PFS_REG(_X_) & (R_PmnPFS_PIDR_Msk)) == (R_PmnPFS_PIDR_Msk) 18 | 19 | #define BTN_INIT(_X_) \ 20 | { \ 21 | /* Write to specific pin's PFS register */ \ 22 | R_PFS_REG(_X_) = (1U << R_PmnPFS_ISEL_Pos); \ 23 | /* IELSR Must be zero when modifying the IRQCR bits */ \ 24 | R_ICU_REG(R_ICU_IELSR0) = 0; \ 25 | /* Disable digital filter */ \ 26 | R_ICU_REG8(R_ICU_IRQCR+R_EVENT_PORT_IRQ13) = 0; \ 27 | /* Set IRQCR */ /* TODO - Add Masks */ \ 28 | R_ICU_REG8(R_ICU_IRQCR+R_EVENT_PORT_IRQ13) = 0xB1; \ 29 | /* Set IELSR */ \ 30 | R_ICU_REG(R_ICU_IELSR0) = R_EVENT_PORT_IRQ13; \ 31 | } 32 | 33 | #define BTN_IRQ_CLR() \ 34 | { \ 35 | R_ICU_REG(R_ICU_IELSR0) &= ~(R_ICU_IELSR_IR); \ 36 | } 37 | 38 | #define SPI_INIT(_X_, _Y_, _Z_) \ 39 | { \ 40 | /* Config PmnPFS as input (enable pull-up) */ \ 41 | R_PFS_REG(_X_) = 0; \ 42 | R_PFS_REG(_X_) = (1U << R_PmnPFS_PCR_Pos); \ 43 | /* Config PmnPFS as output */ \ 44 | R_PFS_REG(_Y_) = (1U << R_PmnPFS_PDR_Pos) | (1U << R_PmnPFS_PODR_Pos); \ 45 | R_PFS_REG(_Z_) = (1U << R_PmnPFS_PDR_Pos) | (1U << R_PmnPFS_PODR_Pos); \ 46 | } 47 | 48 | #define SPI_TDO_SET(_X_) \ 49 | { \ 50 | R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos) | (1U << R_PmnPFS_PODR_Pos); \ 51 | } 52 | 53 | #define SPI_TDO_CLR(_X_) \ 54 | { \ 55 | R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos); \ 56 | } 57 | 58 | #define SPI_TDI_BIT(_X_) ((R_PFS_REG(_X_) >> R_PmnPFS_PIDR_Pos) & 1U) \ 59 | 60 | #define SPI_TCK_HIGH(_X_) \ 61 | { \ 62 | R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos); \ 63 | } 64 | 65 | #define SPI_TCK_LOW(_X_) \ 66 | { \ 67 | R_PFS_REG(_X_) = (1U << R_PmnPFS_PDR_Pos) | (1U << R_PmnPFS_PODR_Pos); \ 68 | } 69 | 70 | #define UART_IRQ_CLR() R_ICU_REG(R_ICU_IELSR8) &= ~(R_ICU_IELSR_IR) 71 | 72 | #define UART_IRQ_RX() 1 73 | 74 | #endif 75 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/jlink.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # SEGGER J-Link 3 | # 4 | # http://www.segger.com/jlink.html 5 | # 6 | 7 | interface jlink 8 | 9 | transport select swd 10 | 11 | # The serial number can be used to select a specific device in case more than 12 | # one is connected to the host. 13 | # 14 | # Example: Select J-Link with serial number 123456789 15 | # 16 | # jlink serial 123456789 17 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/memory.lds: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2019 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | flash = 0x20010000; 4 | itcm = 0x20010000; 5 | dtcm = 0x20010000; 6 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/multizone.cfg: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | # MultiZone reserved memory: 8K @0x20000000, 8K @0x1FFE0000 4 | 5 | Tick = 10 # ms 6 | 7 | Zone = 1 8 | irq = 24 9 | base = 0x20018000; size = 32K; rwx = rx # FLASH 10 | base = 0x20010000; size = 4K; rwx = rw # RAM 11 | base = 0x40006320; size = 0x20; rwx = rw # ICU (IELSR8-15) 12 | base = 0x40047000; size = 0x20; rwx = rw # MSTP 13 | base = 0x400700E0; size = 0x20; rwx = rw # SCI7 14 | base = 0x400409A0; size = 0x20; rwx = rw # P607_PFS-P615_PFS (UART TX & RX) 15 | 16 | Zone = 2 17 | irq = 16 18 | base = 0x20020000; size = 32K; rwx = rx # FLASH 19 | base = 0x20011000; size = 4K; rwx = rw # RAM 20 | base = 0x40006000; size = 0x20; rwx = rw # ICU (IRQCR) 21 | base = 0x40006300; size = 0x20; rwx = rw # ICU (IELSR0-7) 22 | base = 0x40040820; size = 0x20; rwx = rw # P007_PFS-P015_PFS (BUTTON) 23 | base = 0x40040900; size = 0x20; rwx = rw # P400_PFS-P407_PFS (LED) 24 | 25 | Zone = 3 26 | base = 0x20028000; size = 32K; rwx = rx # FLASH 27 | base = 0x20012000; size = 4K; rwx = rw # RAM 28 | base = 0x40040940; size = 0x20; rwx = rw # P500_PFS-P507_PFS (SPI_TDO) 29 | base = 0x40040A40; size = 0x40; rwx = rw # P900_PFS-P915_PFS (SPI_TDI & SPI_TCK) 30 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/newlib/crt0.S: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | # Make sure that the GNU assembler is using a modern syntax for Arm THUMB. 4 | .syntax unified 5 | .arch armv7e-m 6 | 7 | /** 8 | * These are the addresses for the initialized (data) and uninitialized (bss) 9 | * variables. The initialized variables will be copied from FLASH to RAM. The 10 | * uninitialized variables will be set to 0. These addresses are set in the 11 | * linker file. 12 | */ 13 | .word __data_vma_start 14 | .word __data_start 15 | .word __data_end 16 | .word __bss_start 17 | .word __bss_end 18 | 19 | # TODO - Consider to move the vector table definition to the bsp 20 | # since the vector table is specific to the CPU/BOARD 21 | # ------------------------------------------------------------- 22 | .section .text.isr_vector 23 | .align 2 24 | .globl __isr_vector 25 | # ------------------------------------------------------------- 26 | __isr_vector: 27 | .word __end_stack // MSP definition 28 | .word reset_handler // Reset_Handler 29 | .word nmi_handler // NMI_Handler 30 | .word hardfault_handler // HardFault_Handler 31 | .word memmanage_handler // MemManage_Handler 32 | .word busfault_handler // BusFault_Handler 33 | .word usagefault_handler // UsageFault_Handler 34 | .word 0 // Not Defined 35 | .word 0 // Not Defined 36 | .word 0 // Not Defined 37 | .word 0 // Not Defined 38 | .word svc_handler // SVC_Handler 39 | .word debugmon_handler // DebugMon_Handler 40 | .word 0 // Not Defined 41 | .word pendsv_handler // PendSV_Handler 42 | .word systick_handler // SysTick_Handler 43 | .word btn_handler 44 | .rept 7 // Repeat for 45 | .word _def_handler // IRQ1_Handler to IRQ7_Handler 46 | .endr 47 | .word uart_handler 48 | .rept 86 // Repeat for 49 | .word _def_handler // IRQ9_Handler to IRQ95_Handler 50 | .endr 51 | .size __isr_vector, . - __isr_vector 52 | 53 | # ------------------------------------------------------------- 54 | .align 2 55 | .section .text.init 56 | .global reset_handler 57 | .type reset_handler, %function 58 | # ------------------------------------------------------------- 59 | reset_handler: 60 | ldr sp, =__end_stack /* set stack pointer */ 61 | 62 | // Copy the initialized global variables to RAM 63 | mov r0, #0 64 | ldr r1, = __data_start 65 | ldr r2, = __data_end 66 | ldr r3, = __data_vma_start 67 | b loopcopy_data 68 | 69 | copy_data: 70 | ldr r4, [r3, r0] 71 | str r4, [r1, r0] 72 | adds r0, r0, #4 73 | 74 | loopcopy_data: 75 | add r4, r1, r0 76 | cmp r4, r2 77 | bcc copy_data 78 | 79 | // Fill uninitialized variables with zeros 80 | mov r0, #0 81 | ldr r1, = __bss_start 82 | ldr r2, = __bss_end 83 | b loopfill_zerobss 84 | 85 | fill_zerobss: 86 | str r0, [r1] 87 | add r1, r1, #4 88 | 89 | loopfill_zerobss: 90 | cmp r1, r2 91 | bcc fill_zerobss 92 | 93 | // Call the libc init function 94 | bl __libc_init_array 95 | 96 | // Call the main function 97 | bl main 98 | 99 | 100 | .global _init 101 | .type _init, %function 102 | _init: 103 | bx lr 104 | .size _init, .-_init 105 | 106 | .global _fini 107 | .type _fini, %function 108 | _fini: 109 | bx lr 110 | .size _fini, .-_fini 111 | 112 | # ------------------------------------------------------------- 113 | .section .text.nmi_handler 114 | .type nmi_handler, %function 115 | .weak nmi_handler 116 | .thumb_set nmi_handler,_def_handler 117 | 118 | # ------------------------------------------------------------- 119 | .section .text.hardfault_handler 120 | .type hardfault_handler, %function 121 | .weak hardfault_handler 122 | .thumb_set hardfault_handler,_def_handler 123 | 124 | # ------------------------------------------------------------- 125 | .section .text.memmanage_handler 126 | .type memmanage_handler, %function 127 | .weak memmanage_handler 128 | .thumb_set memmanage_handler,_def_handler 129 | 130 | # ------------------------------------------------------------- 131 | .section .text.busfault_handler 132 | .type busfault_handler, %function 133 | .weak busfault_handler 134 | .thumb_set busfault_handler,_def_handler 135 | 136 | # ------------------------------------------------------------- 137 | .section .text.usagefault_handler 138 | .type usagefault_handler, %function 139 | .weak usagefault_handler 140 | .thumb_set usagefault_handler,_def_handler 141 | 142 | # ------------------------------------------------------------- 143 | .section .text.svc_handler 144 | .type svc_handler, %function 145 | .weak svc_handler 146 | .thumb_set svc_handler,_def_handler 147 | 148 | # ------------------------------------------------------------- 149 | .section .text.debugmon_handler 150 | .type debugmon_handler, %function 151 | .weak debugmon_handler 152 | .thumb_set debugmon_handler,_def_handler 153 | 154 | # ------------------------------------------------------------- 155 | .section .text.pendsv_handler 156 | .type pendsv_handler, %function 157 | .weak pendsv_handler 158 | .thumb_set pendsv_handler,_def_handler 159 | 160 | # ------------------------------------------------------------- 161 | .section .text.systick_handler 162 | .type systick_handler, %function 163 | .weak systick_handler 164 | .thumb_set systick_handler,_def_handler 165 | 166 | 167 | # ------------------------------------------------------------- 168 | .section .text.btn_handler 169 | .type btn_handler, %function 170 | .weak btn_handler 171 | .thumb_set btn_handler,_def_handler 172 | 173 | # ------------------------------------------------------------- 174 | .section .text.uart_handler 175 | .type uart_handler, %function 176 | .weak uart_handler 177 | .thumb_set uart_handler,_def_handler 178 | 179 | # ------------------------------------------------------------- 180 | .section .text._def_handler 181 | .type _def_handler, %function 182 | # ------------------------------------------------------------- 183 | # ------------------------------------------------------------- 184 | _def_handler: # Default Handler (Exception happen while starting) 185 | # ------------------------------------------------------------- 186 | b reset_handler // restart 187 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/newlib/newlib.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include 9 | 10 | // ---------------------------------------------------------------------------- 11 | int _close(int file) { 12 | // ---------------------------------------------------------------------------- 13 | 14 | return -1; 15 | } 16 | 17 | // ---------------------------------------------------------------------------- 18 | int _fstat(int file, struct stat *st) { 19 | // ---------------------------------------------------------------------------- 20 | 21 | st->st_mode = S_IFCHR; 22 | return 0; 23 | } 24 | 25 | // ---------------------------------------------------------------------------- 26 | void * _sbrk(int incr) { 27 | // ---------------------------------------------------------------------------- 28 | 29 | extern char _end[]; 30 | extern char _heap_end[]; 31 | static char *_heap_ptr = _end; 32 | 33 | if ((_heap_ptr + incr < _end) || (_heap_ptr + incr > _heap_end)) 34 | return (void *) -1; 35 | 36 | _heap_ptr += incr; 37 | return _heap_ptr - incr; 38 | } 39 | 40 | // ---------------------------------------------------------------------------- 41 | int _isatty(int file) { 42 | // ---------------------------------------------------------------------------- 43 | 44 | return (file == STDIN_FILENO || file == STDOUT_FILENO || file == STDERR_FILENO) ? 1 : 0; 45 | 46 | } 47 | 48 | // ---------------------------------------------------------------------------- 49 | int _lseek(int file, off_t ptr, int dir) { 50 | // ---------------------------------------------------------------------------- 51 | 52 | return 0; 53 | } 54 | 55 | // ---------------------------------------------------------------------------- 56 | int _open(const char* name, int flags, int mode) { 57 | // ---------------------------------------------------------------------------- 58 | 59 | if (strcmp(name, "UART")==0){ 60 | 61 | /* Write to specific pin's PFS register */ 62 | R_PFS_REG(R_PFS_P613PFS) = 0x0; 63 | R_PFS_REG(R_PFS_P613PFS) = 0x5010000; 64 | 65 | /* Write to specific pin's PFS register */ 66 | R_PFS_REG(R_PFS_P614PFS) = 0x0; 67 | R_PFS_REG(R_PFS_P614PFS) = 0x5010000; 68 | 69 | /* Enable the SCI channel and reset the registers to their initial state. */ 70 | MSTP_REG(R_SCI_SMR) = ~R_MSTP_MSTPCRB_MSTPB24_Msk; 71 | 72 | /* Initialize SCI registers as described in RA6M3 manual (34.3.7) */ 73 | R_SCI7_REG8(R_SCI_SCR) = 0U; 74 | R_SCI7_REG8(R_SCI_SSR) = 0U; 75 | R_SCI7_REG8(R_SCI_SIMR1) = 0U; 76 | R_SCI7_REG8(R_SCI_SIMR2) = 0U; 77 | R_SCI7_REG8(R_SCI_SIMR3) = 0U; 78 | R_SCI7_REG16(R_SCI_CDR) = 0U; 79 | R_SCI7_REG8(R_SCI_DCCR) = SCI_UART_DCCR_DEFAULT_VALUE; 80 | 81 | /* Set the default level of the TX pin to 1. */ 82 | R_SCI7_REG8(R_SCI_SPTR) = (uint8_t) (1U << SPTR_SPB2D_BIT) | SPTR_OUTPUT_ENABLE_MASK; 83 | 84 | /* Configure parity and stop bits. */ 85 | R_SCI7_REG8(R_SCI_SMR) = (uint8_t) 0; // parity = 0, stop_bits = 0 86 | R_SCI7_REG8(R_SCI_SCMR) = (uint8_t) SCI_UART_SCMR_DEFAULT_VALUE; 87 | R_SCI7_REG8(R_SCI_SPMR) = 0; 88 | 89 | R_SCI7_REG8(R_SCI_SNFR) = 0; 90 | R_SCI7_REG8(R_SCI_SEMR) = (SCI_UART_START_BIT_FALLING_EDGE & 1U) << 7; 91 | R_SCI7_REG8(R_SCI_BRR) = 64; 92 | R_SCI7_REG8(R_SCI_MDDR) = 0xFF; 93 | R_SCI7_REG8(R_SCI_SEMR) = (uint8_t) ((R_SCI7_REG8(R_SCI_SEMR) & ~(SCI_UART_SEMR_BAUD_SETTING_MASK)) | 94 | (0x40 & SCI_UART_SEMR_BAUD_SETTING_MASK)); 95 | 96 | /* IRQ configure - ICU */ 97 | R_ICU_REG(R_ICU_IELSR8) = R_EVENT_SCI7_RXI; 98 | 99 | R_SCI7_REG8(R_SCI_SCR) |= SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK | SCI_SCR_TE_MASK; 100 | 101 | return 0; 102 | 103 | } 104 | 105 | return -1; 106 | } 107 | 108 | // ---------------------------------------------------------------------------- 109 | int _read(int file, char *ptr, size_t len) { 110 | // ---------------------------------------------------------------------------- 111 | if (isatty(file)) { 112 | 113 | ssize_t count = 0; 114 | int rxfifo = -1; 115 | 116 | while( count $(LST) 46 | 47 | $(ASM_OBJS): %.o: %.S $(HEADERS) 48 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 49 | 50 | $(C_OBJS): %.o: %.c $(HEADERS) 51 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 52 | 53 | .PHONY: clean 54 | clean: 55 | rm -f $(CLEAN_OBJS) 56 | 57 | -------------------------------------------------------------------------------- /bsp/EKRA6M3/ra6m3.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # Renesas EKRA6M3 w/ ARM Cortex-M4 3 | # 4 | 5 | if { [info exists CHIPNAME] } { 6 | set _CHIPNAME $CHIPNAME 7 | } else { 8 | set _CHIPNAME ra6m3 9 | } 10 | 11 | if { [info exists CPU_JTAG_TAPID] } { 12 | set _CPU_JTAG_TAPID $CPU_JTAG_TAPID 13 | } else { 14 | set _CPU_JTAG_TAPID 0x5ba00477 15 | } 16 | 17 | if { [info exists CPU_SWD_TAPID] } { 18 | set _CPU_SWD_TAPID $CPU_SWD_TAPID 19 | } else { 20 | set _CPU_SWD_TAPID 0x5ba02477 21 | } 22 | 23 | source [find target/swj-dp.tcl] 24 | 25 | if { [using_jtag] } { 26 | set _CPU_TAPID $_CPU_JTAG_TAPID 27 | } else { 28 | set _CPU_TAPID $_CPU_SWD_TAPID 29 | } 30 | 31 | swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID 32 | dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu 33 | 34 | set _TARGETNAME $_CHIPNAME.cpu 35 | target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap 36 | 37 | if { [info exists WORKAREASIZE] } { 38 | set _WORKAREASIZE $WORKAREASIZE 39 | } else { 40 | # 640 KB On-Chip SRAM 41 | set _WORKAREASIZE 0x60000 42 | } 43 | 44 | $_TARGETNAME configure -work-area-phys 0x1ffe0000 \ 45 | -work-area-size $_WORKAREASIZE -work-area-backup 0 46 | 47 | if { ![using_hla] } { 48 | cortex_m reset_config sysresetreq 49 | } 50 | 51 | adapter_khz 1000 52 | -------------------------------------------------------------------------------- /bsp/GD32307/boot: -------------------------------------------------------------------------------- 1 | ../STM32F767/boot -------------------------------------------------------------------------------- /bsp/GD32307/gdlink.cfg: -------------------------------------------------------------------------------- 1 | interface cmsis-dap 2 | transport select swd 3 | # 4 | # gd32 devices support both JTAG and SWD transports. 5 | # 6 | source [find target/swj-dp.tcl] 7 | source [find mem_helper.tcl] 8 | 9 | if { [info exists CHIPNAME] } { 10 | set _CHIPNAME $CHIPNAME 11 | } else { 12 | set _CHIPNAME gd32f1x 13 | } 14 | 15 | set _ENDIAN little 16 | 17 | # Work-area is a space in RAM used for flash programming 18 | # By default use 4kB (as found on some ) 19 | if { [info exists WORKAREASIZE] } { 20 | set _WORKAREASIZE $WORKAREASIZE 21 | } else { 22 | set _WORKAREASIZE 0x1000 23 | } 24 | 25 | #jtag scan chain 26 | if { [info exists CPUTAPID] } { 27 | set _CPUTAPID $CPUTAPID 28 | } else { 29 | if { [using_jtag] } { 30 | # See Document RM0008 Section 26.6.3 31 | set _CPUTAPID 0x3ba00477 32 | } { 33 | # this is the SW-DP tap id not the jtag tap id 34 | set _CPUTAPID 0x1ba01477 35 | } 36 | } 37 | 38 | swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID 39 | 40 | if { [info exists BSTAPID] } { 41 | # FIXME this never gets used to override defaults... 42 | set _BSTAPID $BSTAPID 43 | } else { 44 | # See Document RM0008 45 | # Section 29.6.2 46 | # Low density devices, Rev A 47 | set _BSTAPID1 0x06412041 48 | # Medium density devices, Rev A 49 | set _BSTAPID2 0x06410041 50 | # Medium density devices, Rev B and Rev Z 51 | set _BSTAPID3 0x16410041 52 | set _BSTAPID4 0x06420041 53 | # High density devices, Rev A 54 | set _BSTAPID5 0x06414041 55 | # Connectivity line devices, Rev A and Rev Z 56 | set _BSTAPID6 0x06418041 57 | # XL line devices, Rev A 58 | set _BSTAPID7 0x06430041 59 | # VL line devices, Rev A and Z In medium-density and high-density value line devices 60 | set _BSTAPID8 0x06420041 61 | # VL line devices, Rev A 62 | set _BSTAPID9 0x06428041 63 | } 64 | 65 | if {[using_jtag]} { 66 | swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ 67 | -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ 68 | -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \ 69 | -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \ 70 | -expected-id $_BSTAPID8 -expected-id $_BSTAPID9 71 | } 72 | 73 | dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu 74 | 75 | set _TARGETNAME $_CHIPNAME.cpu 76 | target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap 77 | #target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME 78 | 79 | 80 | $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 81 | 82 | # flash size will be probed 83 | set _FLASHNAME $_CHIPNAME.flash 84 | flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME 85 | 86 | # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz 87 | adapter_khz 1000 88 | 89 | adapter_nsrst_delay 100 90 | if {[using_jtag]} { 91 | jtag_ntrst_delay 100 92 | } 93 | 94 | reset_config srst_nogate 95 | 96 | if {![using_hla]} { 97 | # if srst is not fitted use SYSRESETREQ to 98 | # perform a soft reset 99 | cortex_m reset_config sysresetreq 100 | } 101 | 102 | $_TARGETNAME configure -event examine-end { 103 | # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP | 104 | # DBG_STANDBY | DBG_STOP | DBG_SLEEP 105 | mmw 0xE0042004 0x00000307 0 106 | } 107 | 108 | $_TARGETNAME configure -event trace-config { 109 | # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync 110 | # change this value accordingly to configure trace pins 111 | # assignment 112 | mmw 0xE0042004 0x00000020 0 113 | } -------------------------------------------------------------------------------- /bsp/GD32307/gpio_driver.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef GPIO_DRIVER_H 4 | #define GPIO_DRIVER_H 5 | 6 | #define LED_INIT(_X_) \ 7 | { \ 8 | /* Port output control register - Output (10Mhz) & Push-Pull */ \ 9 | GPIOC_REG(GPIO_CTL0) = ( GPIO_CTL_MD_O10MHZ << (4*_X_) ); \ 10 | /* Port output control register - Set output high */ \ 11 | GPIOC_REG(GPIO_OCTL) = ( GPIO_OCTL_OH << _X_ ); \ 12 | } 13 | 14 | #define LED_SET(_X_) GPIOC_REG(GPIO_BOP) = ( GPIO_BOP_SET << _X_ ); 15 | 16 | #define LED_CLR(_X_) GPIOC_REG(GPIO_BC) = ( GPIO_BC_CLEAR << _X_ ); 17 | 18 | #define LED_OUT(_X_) (GPIOC_REG(GPIO_OCTL) & 1 ) == 1 19 | 20 | #define BTN_INIT(_X_) \ 21 | { \ 22 | /* Configure button pin as input */ \ 23 | GPIOB_REG(GPIO_CTL1) = (GPIO_CTL_CTL_IFI << ((_X_-8)*4)); \ 24 | /* Select EXTI source */ \ 25 | AFIO_REG(AFIO_EXTISS3) = AFIO_EXTI14SS_PB14; \ 26 | /* Configure EXTI line */ \ 27 | EXTI_REG(EXTI_INTEN) = (1 << _X_); \ 28 | EXTI_REG(EXTI_RTEN) = 0; \ 29 | EXTI_REG(EXTI_FTEN) = (1 << _X_); \ 30 | EXTI_REG(EXTI_PD) = (1 << _X_); \ 31 | } 32 | 33 | #define BTN_IRQ_CLR() \ 34 | { \ 35 | EXTI_REG(EXTI_PD) = (1 << BTN0_PIN); \ 36 | } 37 | 38 | /* 39 | * SPI_INIT(SPI_TDI, SPI_TCK, SPI_TDO); 40 | * SPI_TDI = PE11, SPI_TCK = PE13, SPI_TDO = PE15 41 | */ 42 | #define SPI_INIT(_X_, _Y_, _Z_) \ 43 | { \ 44 | /* SPI_TDI = PE11 as input (enable pull-up) */ \ 45 | GPIOE_REG(GPIO_CTL1) = ( GPIO_CTL_CTL_IPP << ((_X_-8)*4) ); \ 46 | /* SPI_TCK = PE13 - Output (10Mhz) & Push-Pull */ \ 47 | GPIOE_REG(GPIO_CTL1) |= ( GPIO_CTL_MD_O10MHZ << ((_Y_-8)*4) ); \ 48 | /* SPI_TCK = PE13 - Set output high */ \ 49 | GPIOE_REG(GPIO_OCTL) |= ( GPIO_OCTL_OH << _Y_ ); \ 50 | /* SPI_TDO = PE15 - Output (10Mhz) & Push-Pull */ \ 51 | GPIOE_REG(GPIO_CTL1) |= ( GPIO_CTL_MD_O10MHZ << ((_Z_-8)*4) ); \ 52 | /* SPI_TDO = PE15 - Set output high */ \ 53 | GPIOE_REG(GPIO_OCTL) |= ( GPIO_OCTL_OH << _Z_ ); \ 54 | } 55 | 56 | #define SPI_TDO_SET(_X_) GPIOE_REG(GPIO_BOP) |= ( GPIO_BOP_SET << _X_ ); 57 | 58 | #define SPI_TDO_CLR(_X_) GPIOE_REG(GPIO_BC) |= ( GPIO_BC_CLEAR << _X_ ); 59 | 60 | #define SPI_TDI_BIT(_X_) (GPIOE_REG(GPIO_ISTAT) >> _X_) & GPIO_ISTAT_IH 61 | 62 | #define SPI_TCK_LOW(_X_) GPIOE_REG(GPIO_BOP) = ( GPIO_BOP_SET << _X_ ); 63 | #define SPI_TCK_HIGH(_X_) GPIOE_REG(GPIO_BC) = ( GPIO_BC_CLEAR << _X_ ); 64 | 65 | #define UART_IRQ_CLR() \ 66 | { \ 67 | } 68 | 69 | #define UART_IRQ_RX() (USART0_REG(USART_STAT0) & USART_STAT0_RBNE) 70 | 71 | #endif 72 | -------------------------------------------------------------------------------- /bsp/GD32307/memory.lds: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2019 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | flash = 0x08000000; 4 | itcm = 0x08000000; 5 | dtcm = 0x20002000; /* DTCM 0x2000_0000 64K */ 6 | -------------------------------------------------------------------------------- /bsp/GD32307/multizone.cfg: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | # MultiZone reserved memory: 8K @0x08000000, 8K @0x20000000 4 | 5 | Tick = 10 # ms 6 | 7 | Zone = 1 8 | irq = 53 9 | base = 0x08008000; size = 32K; rwx = rx # FLASH 10 | base = 0x20002000; size = 4K; rwx = rw # RAM 11 | base = 0x40010800; size = 0x40; rwx = rw # GPIOA (TX & RX) 12 | base = 0x40013800; size = 0x40; rwx = rw # USART0 13 | 14 | Zone = 2 15 | irq = 56 16 | base = 0x08010000; size = 32K; rwx = rx # FLASH 17 | base = 0x20003000; size = 4K; rwx = rw # RAM 18 | base = 0x40011000; size = 0x40; rwx = rw # GPIOC (LED) 19 | base = 0x40010C00; size = 0x40; rwx = rw # GPIOB (BUTTON) 20 | base = 0x40010000; size = 0x40; rwx = rw # AFIO (BUTTON) 21 | base = 0x40010400; size = 0x40; rwx = rw # EXTI (BUTTON) 22 | 23 | Zone = 3 24 | base = 0x08018000; size = 32K; rwx = rx # FLASH 25 | base = 0x20004000; size = 4K; rwx = rw # RAM 26 | base = 0x40011800; size = 0x40; rwx = rw # GPIOE (ROBOT) 27 | 28 | -------------------------------------------------------------------------------- /bsp/GD32307/newlib/crt0.S: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | # Make sure that the GNU assembler is using a modern syntax for Arm THUMB. 4 | .syntax unified 5 | .arch armv7e-m 6 | 7 | /** 8 | * These are the addresses for the initialized (data) and uninitialized (bss) 9 | * variables. The initialized variables will be copied from FLASH to RAM. The 10 | * uninitialized variables will be set to 0. These addresses are set in the 11 | * linker file. 12 | */ 13 | .word __data_vma_start 14 | .word __data_start 15 | .word __data_end 16 | .word __bss_start 17 | .word __bss_end 18 | 19 | # TODO - Consider to move the vector table definition to the bsp 20 | # since the vector table is specific to the CPU/BOARD 21 | # ------------------------------------------------------------- 22 | .section .text.isr_vector 23 | .align 2 24 | .globl __isr_vector 25 | # ------------------------------------------------------------- 26 | __isr_vector: 27 | .word __end_stack // MSP definition 28 | .word reset_handler // Reset_Handler 29 | .word nmi_handler // NMI_Handler 30 | .word hardfault_handler // HardFault_Handler 31 | .word memmanage_handler // MemManage_Handler 32 | .word busfault_handler // BusFault_Handler 33 | .word usagefault_handler // UsageFault_Handler 34 | .word 0 // Not Defined 35 | .word 0 // Not Defined 36 | .word 0 // Not Defined 37 | .word 0 // Not Defined 38 | .word svc_handler // SVC_Handler 39 | .word debugmon_handler // DebugMon_Handler 40 | .word 0 // Not Defined 41 | .word pendsv_handler // PendSV_Handler 42 | .word systick_handler // SysTick_Handler 43 | .rept 37 // Repeat for 44 | .word _def_handler // IRQ0_Handler to IRQ39_Handler 45 | .endr 46 | .word uart_handler // USART Handler (USART0) 47 | .word _def_handler 48 | .word _def_handler 49 | .word btn_handler // Button Handler (EXTI10_15_IRQn) 50 | .rept 27 // Repeat for 51 | .word _def_handler // IRQ41_Handler to IRQ67_Handler 52 | .endr 53 | .size __isr_vector, . - __isr_vector 54 | 55 | # ------------------------------------------------------------- 56 | .align 2 57 | .section .text.init 58 | .global reset_handler 59 | .type reset_handler, %function 60 | # ------------------------------------------------------------- 61 | reset_handler: 62 | ldr sp, =__end_stack /* set stack pointer */ 63 | 64 | // Copy the initialized global variables to RAM 65 | mov r0, #0 66 | ldr r1, = __data_start 67 | ldr r2, = __data_end 68 | ldr r3, = __data_vma_start 69 | b loopcopy_data 70 | 71 | copy_data: 72 | ldr r4, [r3, r0] 73 | str r4, [r1, r0] 74 | adds r0, r0, #4 75 | 76 | loopcopy_data: 77 | add r4, r1, r0 78 | cmp r4, r2 79 | bcc copy_data 80 | 81 | // Fill uninitialized variables with zeros 82 | mov r0, #0 83 | ldr r1, = __bss_start 84 | ldr r2, = __bss_end 85 | b loopfill_zerobss 86 | 87 | fill_zerobss: 88 | str r0, [r1] 89 | add r1, r1, #4 90 | 91 | loopfill_zerobss: 92 | cmp r1, r2 93 | bcc fill_zerobss 94 | 95 | // Call the libc init function 96 | bl __libc_init_array 97 | 98 | // Call the main function 99 | bl main 100 | 101 | 102 | .global _init 103 | .type _init, %function 104 | _init: 105 | bx lr 106 | .size _init, .-_init 107 | 108 | .global _fini 109 | .type _fini, %function 110 | _fini: 111 | bx lr 112 | .size _fini, .-_fini 113 | 114 | # ------------------------------------------------------------- 115 | .section .text.nmi_handler 116 | .type nmi_handler, %function 117 | .weak nmi_handler 118 | .thumb_set nmi_handler,_def_handler 119 | 120 | # ------------------------------------------------------------- 121 | .section .text.hardfault_handler 122 | .type hardfault_handler, %function 123 | .weak hardfault_handler 124 | .thumb_set hardfault_handler,_def_handler 125 | 126 | # ------------------------------------------------------------- 127 | .section .text.memmanage_handler 128 | .type memmanage_handler, %function 129 | .weak memmanage_handler 130 | .thumb_set memmanage_handler,_def_handler 131 | 132 | # ------------------------------------------------------------- 133 | .section .text.busfault_handler 134 | .type busfault_handler, %function 135 | .weak busfault_handler 136 | .thumb_set busfault_handler,_def_handler 137 | 138 | # ------------------------------------------------------------- 139 | .section .text.usagefault_handler 140 | .type usagefault_handler, %function 141 | .weak usagefault_handler 142 | .thumb_set usagefault_handler,_def_handler 143 | 144 | # ------------------------------------------------------------- 145 | .section .text.svc_handler 146 | .type svc_handler, %function 147 | .weak svc_handler 148 | .thumb_set svc_handler,_def_handler 149 | 150 | # ------------------------------------------------------------- 151 | .section .text.debugmon_handler 152 | .type debugmon_handler, %function 153 | .weak debugmon_handler 154 | .thumb_set debugmon_handler,_def_handler 155 | 156 | # ------------------------------------------------------------- 157 | .section .text.pendsv_handler 158 | .type pendsv_handler, %function 159 | .weak pendsv_handler 160 | .thumb_set pendsv_handler,_def_handler 161 | 162 | # ------------------------------------------------------------- 163 | .section .text.systick_handler 164 | .type systick_handler, %function 165 | .weak systick_handler 166 | .thumb_set systick_handler,_def_handler 167 | 168 | 169 | # ------------------------------------------------------------- 170 | .section .text.btn_handler 171 | .type btn_handler, %function 172 | .weak btn_handler 173 | .thumb_set btn_handler,_def_handler 174 | 175 | # ------------------------------------------------------------- 176 | .section .text.uart_handler 177 | .type uart_handler, %function 178 | .weak uart_handler 179 | .thumb_set uart_handler,_def_handler 180 | 181 | # ------------------------------------------------------------- 182 | .section .text._def_handler 183 | .type _def_handler, %function 184 | # ------------------------------------------------------------- 185 | # ------------------------------------------------------------- 186 | _def_handler: # Default Handler (Exception happen while starting) 187 | # ------------------------------------------------------------- 188 | b reset_handler // restart 189 | 190 | -------------------------------------------------------------------------------- /bsp/GD32307/newlib/newlib.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include 9 | 10 | // ---------------------------------------------------------------------------- 11 | int _close(int file) { 12 | // ---------------------------------------------------------------------------- 13 | 14 | return -1; 15 | } 16 | 17 | // ---------------------------------------------------------------------------- 18 | int _fstat(int file, struct stat *st) { 19 | // ---------------------------------------------------------------------------- 20 | 21 | st->st_mode = S_IFCHR; 22 | return 0; 23 | } 24 | 25 | // ---------------------------------------------------------------------------- 26 | void * _sbrk(int incr) { 27 | // ---------------------------------------------------------------------------- 28 | 29 | extern char _end[]; 30 | extern char _heap_end[]; 31 | static char *_heap_ptr = _end; 32 | 33 | if ((_heap_ptr + incr < _end) || (_heap_ptr + incr > _heap_end)) 34 | return (void *) -1; 35 | 36 | _heap_ptr += incr; 37 | return _heap_ptr - incr; 38 | } 39 | 40 | // ---------------------------------------------------------------------------- 41 | int _isatty(int file) { 42 | // ---------------------------------------------------------------------------- 43 | 44 | return (file == STDIN_FILENO || file == STDOUT_FILENO || file == STDERR_FILENO) ? 1 : 0; 45 | 46 | } 47 | 48 | // ---------------------------------------------------------------------------- 49 | int _lseek(int file, off_t ptr, int dir) { 50 | // ---------------------------------------------------------------------------- 51 | 52 | return 0; 53 | } 54 | 55 | // ---------------------------------------------------------------------------- 56 | int _open(const char* name, int flags, int mode) { 57 | // ---------------------------------------------------------------------------- 58 | 59 | if (strcmp(name, "UART")==0){ 60 | 61 | /* connect port to USART0_Tx - PA.09 */ 62 | //GPIOA_REG(GPIO_CTL1) = (0xB << 4); 63 | GPIOA_REG(GPIO_CTL1) = ((GPIO_CTL_CTL_AFIOPP|GPIO_CTL_MD_O50MHZ) << 4); 64 | 65 | /* connect port to USART0_Rx - PA.10 */ 66 | GPIOA_REG(GPIO_CTL1) |= (GPIO_CTL_CTL_IFI << 8); 67 | 68 | /* 69 | * configure USART baud rate value 70 | * Assuming PCLK = SYS_CLK = 8MHz and BR=115200 71 | * USARTDIV = PLCK / (16 * BR) = 8000000 / (16*115200) = 4.340277778 72 | * INTDIV = INT(USARTDIV) = 4 73 | * FRADIV = INT(16 * REMAINING(INTDIV)) = INT(16*0.340277778) = 5 74 | * USART_BAUD = (INTDIV << 4) | (FRADIV) = 0x45 75 | */ 76 | USART0_REG(USART_BAUD) = 0x45; 77 | 78 | /* configure USART receiver */ 79 | USART0_REG(USART_CTL0) &= ~(USART_CTL0_REN); 80 | USART0_REG(USART_CTL0) |= (USART_CTL0_REN); 81 | 82 | /* configure USART transmitter */ 83 | USART0_REG(USART_CTL0) &= ~(USART_CTL0_TEN); 84 | USART0_REG(USART_CTL0) |= (USART_CTL0_TEN); 85 | 86 | /* enable USART */ 87 | USART0_REG(USART_CTL0) |= (USART_CTL0_UEN); 88 | 89 | /* enable USART interrupt */ 90 | USART0_REG(USART_CTL0) |= (USART_CTL0_RBNEIE); 91 | 92 | return 0; 93 | } 94 | 95 | return -1; 96 | } 97 | 98 | // ---------------------------------------------------------------------------- 99 | int _read(int file, char *ptr, size_t len) { 100 | // ---------------------------------------------------------------------------- 101 | if (isatty(file)) { 102 | 103 | ssize_t count = 0; 104 | int rxfifo = -1; 105 | 106 | while( count $(LST) 46 | 47 | $(ASM_OBJS): %.o: %.S $(HEADERS) 48 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 49 | 50 | $(C_OBJS): %.o: %.c $(HEADERS) 51 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 52 | 53 | .PHONY: clean 54 | clean: 55 | rm -f $(CLEAN_OBJS) 56 | 57 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/boot: -------------------------------------------------------------------------------- 1 | ../STM32F767/boot -------------------------------------------------------------------------------- /bsp/IMXRT1020/cmsis-dap.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # ARM CMSIS-DAP compliant adapter 3 | # 4 | # http://www.keil.com/support/man/docs/dapdebug/ 5 | # 6 | 7 | interface cmsis-dap 8 | 9 | # Optionally specify the serial number of CMSIS-DAP usb device. 10 | #cmsis_dap_serial 02200201E6661E601B98E3B9 11 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/gpio_driver.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef GPIO_DRIVER_H 4 | #define GPIO_DRIVER_H 5 | 6 | #define LED_INIT(_X_) \ 7 | { \ 8 | /* Enable the IOMUXC Clock */ \ 9 | CCM_REG(CCM_CCGR4) |= (0x3 << CCM_CCGR4_CG1); \ 10 | /* GPIO_AD_B0_05 is configured as GPIO1_IO05 */ \ 11 | IOMUX_REG(SW_MUX_CTL_PAD_GPIO_AD_B0_05) |= (0x5 << SW_MUX_CTL_MUX_MODE); \ 12 | IOMUX_REG(SW_MUX_CTL_PAD_GPIO_AD_B0_05) &= ~(1 << SW_MUX_CTL_SION); \ 13 | /* GPIO_AD_B0_05 PAD functional properties */ \ 14 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) &= ~(1 << SW_PAD_CTL_SRE); \ 15 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) |= (0x6 << SW_PAD_CTL_DSE); \ 16 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) |= (1 << SW_PAD_CTL_SPEED); \ 17 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) &= ~(1 << SW_PAD_CTL_ODE); \ 18 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) |= (1 << SW_PAD_CTL_PKE); \ 19 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) &= ~(1 << SW_PAD_CTL_PKU); \ 20 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) &= ~(3 << SW_PAD_CTL_PUS); \ 21 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_05) &= ~(1 << SW_PAD_CTL_HYS); \ 22 | /* Enable the GPIO_LED Clock */ \ 23 | CCM_REG(CCM_CCGR1) |= (0x3 << CCM_CCGR1_CG13); \ 24 | /* Register reset to default value */ \ 25 | GPIO1_REG(GPIO_IMR) &= ~(1 << _X_); \ 26 | /* Configure GPIO pin direction as digital output */ \ 27 | /* Set pin output to low level.*/ \ 28 | GPIO1_REG(GPIO_DR) &= ~(1 << _X_); \ 29 | GPIO1_REG(GPIO_GDIR) |= (1 << _X_); \ 30 | } 31 | 32 | #define LED_SET(_X_) GPIO1_REG(GPIO_DR) &= ~(1 << _X_) 33 | 34 | #define LED_CLR(_X_) GPIO1_REG(GPIO_DR) |= (1 << _X_) 35 | 36 | #define LED_OUT(_X_) (GPIO1_REG(GPIO_DR) & (1 << _X_)) == 0 37 | 38 | #define BTN_INIT(_X_) \ 39 | { \ 40 | /* Enable the IOMUXC Clock */ \ 41 | CCM_REG(CCM_CCGR2) |= (0x3 << CCM_CCGR2_CG2); \ 42 | /* SNVS_WAKEUP is configured as GPIO5_IO00 */ \ 43 | IOMUX_SNVS_REG(SW_MUX_CTL_PAD_WAKEUP) |= (0x5 << SW_MUX_CTL_MUX_MODE); \ 44 | IOMUX_SNVS_REG(SW_MUX_CTL_PAD_WAKEUP) &= ~(1 << SW_MUX_CTL_SION); \ 45 | /* GPIO_AD_B0_05 PAD functional properties */ \ 46 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) &= ~(1 << SW_PAD_CTL_SRE); \ 47 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) &= ~(0x7 << SW_PAD_CTL_DSE); \ 48 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) &= ~(1 << SW_PAD_CTL_ODE); \ 49 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) |= (1 << SW_PAD_CTL_PKE); \ 50 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) |= (1 << SW_PAD_CTL_PKU); \ 51 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) |= (3 << SW_PAD_CTL_PUS); \ 52 | IOMUX_SNVS_REG(SW_PAD_CTL_PAD_WAKEUP) &= ~(1 << SW_PAD_CTL_HYS); \ 53 | /* Enable the GPIO_LED Clock */ \ 54 | CCM_REG(CCM_CCGR1) |= (0x3 << CCM_CCGR1_CG15); \ 55 | /* Register reset to default value */ \ 56 | GPIO5_REG(GPIO_IMR) &= ~(1 << _X_); \ 57 | /* Configure GPIO pin direction as digital input */ \ 58 | GPIO5_REG(GPIO_GDIR) &= ~(1 << _X_); \ 59 | /* Configure GPIO pin interrupt */ \ 60 | GPIO5_REG(GPIO_ICR1) &= ~(0x3 << _X_); \ 61 | GPIO5_REG(GPIO_ICR1) |= (0x2 << _X_); \ 62 | /* Enable GPIO pin interrupt */ \ 63 | GPIO5_REG(GPIO_IMR) |= (1 << _X_); \ 64 | GPIO5_REG(GPIO_EDGE_SEL) &= ~(0x1 << _X_); \ 65 | } 66 | 67 | #define BTN_IRQ_CLR() \ 68 | { \ 69 | GPIO5_REG(GPIO_ISR) |= (1 << BTN); \ 70 | } 71 | 72 | #define SPI_INIT(_X_, _Y_, _Z_) \ 73 | { \ 74 | /* Enable the GPIO1 Clock */ \ 75 | CCM_REG(CCM_CCGR1) |= (0x3 << CCM_CCGR1_CG13); \ 76 | /* Register reset to default value */ \ 77 | GPIO1_REG(GPIO_IMR) &= ~(1 << _X_); \ 78 | GPIO1_REG(GPIO_IMR) &= ~(1 << _Y_); \ 79 | GPIO1_REG(GPIO_IMR) &= ~(1 << _Z_); \ 80 | /* Configure GPIO pin direction as digital output */ \ 81 | /* Set pin output to low level.*/ \ 82 | GPIO1_REG(GPIO_DR) &= ~(1 << _Y_); \ 83 | GPIO1_REG(GPIO_GDIR) |= (1 << _Y_); \ 84 | GPIO1_REG(GPIO_DR) &= ~(1 << _Z_); \ 85 | GPIO1_REG(GPIO_GDIR) |= (1 << _Z_); \ 86 | /* Configure GPIO pin direction as digital input */ \ 87 | GPIO1_REG(GPIO_GDIR) &= ~(1 << _X_); \ 88 | } 89 | 90 | #define SPI_TDO_SET(_X_) GPIO1_REG(GPIO_DR) |= (0x1 << _X_) 91 | 92 | #define SPI_TDO_CLR(_X_) GPIO1_REG(GPIO_DR) &= ~(0x1 << _X_) 93 | 94 | #define SPI_TDI_BIT(_X_) (GPIO1_REG(GPIO_PSR) >> _X_) & 1U 95 | 96 | #define SPI_TCK_LOW(_X_) GPIO1_REG(GPIO_DR) |= (0x1 << _X_) 97 | #define SPI_TCK_HIGH(_X_) GPIO1_REG(GPIO_DR) ^= (0x1 << _X_) 98 | 99 | #define UART_IRQ_CLR() \ 100 | { \ 101 | UART1_REG(UART_STAT); \ 102 | UART1_REG(UART_FIFO); \ 103 | } 104 | 105 | #define UART_IRQ_RX() (((UART1_REG(UART_WATER) & UART_WATER_RXCOUNT_MASK) \ 106 | >> UART_WATER_RXCOUNT_SHIFT) != 0) 107 | 108 | #endif 109 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/imxrt1020.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # NXP i.MX RT1050 family (Arm Cortex-M7 @ 600 MHz) 3 | # 4 | 5 | if { [info exists CHIPNAME] } { 6 | set _CHIPNAME $CHIPNAME 7 | } else { 8 | set _CHIPNAME imxrt1020 9 | } 10 | 11 | source [find target/swj-dp.tcl] 12 | 13 | if { [info exists CPU_SWD_TAPID] } { 14 | set _CPU_SWD_TAPID $CPU_SWD_TAPID 15 | } else { 16 | set _CPU_SWD_TAPID 0x0bd11477 17 | } 18 | 19 | if { [using_jtag] } { 20 | set _CPU_TAPID 0 21 | } else { 22 | set _CPU_TAPID $_CPU_SWD_TAPID 23 | } 24 | 25 | swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID 26 | 27 | set _TARGETNAME $_CHIPNAME.cpu 28 | dap create $_CHIPNAME.dap -chain-position $_TARGETNAME 29 | target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap 30 | 31 | 32 | if { ![using_hla] } { 33 | cortex_m reset_config sysresetreq 34 | } 35 | 36 | adapter_khz 1000 37 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/memory.lds: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2019 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | flash = 0x20200000; 4 | itcm = 0x20200000; 5 | dtcm = 0x20004000; 6 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/multizone.cfg: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | # MultiZone reserved memory: 8K @0x20000000, 8K @0x20002000 4 | 5 | Tick = 10 # ms 6 | 7 | Zone = 1 8 | irq = 36 9 | base = 0x20208000; size = 32K; rwx = rx # FLASH 10 | base = 0x20004000; size = 4K; rwx = rw # RAM 11 | base = 0x400FC000; size = 0x100; rwx = rw # CCM 12 | base = 0x40184000; size = 0x40; rwx = rw # UART 13 | base = 0x401F8000; size = 0x400; rwx = rw # IOMUXC 14 | 15 | Zone = 2 16 | irq = 104 17 | base = 0x20210000; size = 32K; rwx = rx # FLASH 18 | base = 0x20005000; size = 4K; rwx = rw # RAM 19 | base = 0x400FC000; size = 0x100; rwx = rw # CCM 20 | base = 0x400A8000; size = 0x20; rwx = rw # IOMUXC_SNVS 21 | base = 0x401F8000; size = 0x400; rwx = rw # IOMUXC 22 | base = 0x401B8000; size = 0x20; rwx = rw # GPIO1 23 | base = 0x400C0000; size = 0x20; rwx = rw # GPIO5 24 | 25 | Zone = 3 26 | base = 0x20218000; size = 32K; rwx = rx # FLASH 27 | base = 0x20006000; size = 4K; rwx = rw # RAM 28 | base = 0x400FC000; size = 0x100; rwx = rw # CCM 29 | base = 0x401B8000; size = 0x20; rwx = rw # GPIO1 30 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/newlib/crt0.S: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | # Make sure that the GNU assembler is using a modern syntax for Arm THUMB. 4 | .syntax unified 5 | .arch armv7e-m 6 | 7 | /** 8 | * These are the addresses for the initialized (data) and uninitialized (bss) 9 | * variables. The initialized variables will be copied from FLASH to RAM. The 10 | * uninitialized variables will be set to 0. These addresses are set in the 11 | * linker file. 12 | */ 13 | .word __data_vma_start 14 | .word __data_start 15 | .word __data_end 16 | .word __bss_start 17 | .word __bss_end 18 | 19 | # TODO - Consider to move the vector table definition to the bsp 20 | # since the vector table is specific to the CPU/BOARD 21 | # ------------------------------------------------------------- 22 | .section .text.isr_vector 23 | .align 2 24 | .globl __isr_vector 25 | # ------------------------------------------------------------- 26 | __isr_vector: 27 | .word __end_stack // MSP definition 28 | .word reset_handler // Reset_Handler 29 | .word nmi_handler // NMI_Handler 30 | .word hardfault_handler // HardFault_Handler 31 | .word memmanage_handler // MemManage_Handler 32 | .word busfault_handler // BusFault_Handler 33 | .word usagefault_handler // UsageFault_Handler 34 | .word 0 // Not Defined 35 | .word 0 // Not Defined 36 | .word 0 // Not Defined 37 | .word 0 // Not Defined 38 | .word svc_handler // SVC_Handler 39 | .word debugmon_handler // DebugMon_Handler 40 | .word 0 // Not Defined 41 | .word pendsv_handler // PendSV_Handler 42 | .word systick_handler // SysTick_Handler 43 | .rept 20 // Repeat for 44 | .word _def_handler // IRQ0_Handler to IRQ19_Handler 45 | .endr 46 | .word uart_handler // Uart_Handler 47 | .rept 67 // Repeat for 48 | .word _def_handler // IRQ21_Handler to IRQ87_Handler 49 | .endr 50 | .word btn_handler 51 | .size __isr_vector, . - __isr_vector 52 | 53 | # ------------------------------------------------------------- 54 | .align 2 55 | .section .text.init 56 | .global reset_handler 57 | .type reset_handler, %function 58 | # ------------------------------------------------------------- 59 | reset_handler: 60 | ldr sp, =__end_stack /* set stack pointer */ 61 | 62 | // Copy the initialized global variables to RAM 63 | mov r0, #0 64 | ldr r1, = __data_start 65 | ldr r2, = __data_end 66 | ldr r3, = __data_vma_start 67 | b loopcopy_data 68 | 69 | copy_data: 70 | ldr r4, [r3, r0] 71 | str r4, [r1, r0] 72 | adds r0, r0, #4 73 | 74 | loopcopy_data: 75 | add r4, r1, r0 76 | cmp r4, r2 77 | bcc copy_data 78 | 79 | // Fill uninitialized variables with zeros 80 | mov r0, #0 81 | ldr r1, = __bss_start 82 | ldr r2, = __bss_end 83 | b loopfill_zerobss 84 | 85 | fill_zerobss: 86 | str r0, [r1] 87 | add r1, r1, #4 88 | 89 | loopfill_zerobss: 90 | cmp r1, r2 91 | bcc fill_zerobss 92 | 93 | // Call the libc init function 94 | bl __libc_init_array 95 | 96 | // Call the main function 97 | bl main 98 | 99 | 100 | .global _init 101 | .type _init, %function 102 | _init: 103 | bx lr 104 | .size _init, .-_init 105 | 106 | .global _fini 107 | .type _fini, %function 108 | _fini: 109 | bx lr 110 | .size _fini, .-_fini 111 | 112 | # ------------------------------------------------------------- 113 | .section .text.nmi_handler 114 | .type nmi_handler, %function 115 | .weak nmi_handler 116 | .thumb_set nmi_handler,_def_handler 117 | 118 | # ------------------------------------------------------------- 119 | .section .text.hardfault_handler 120 | .type hardfault_handler, %function 121 | .weak hardfault_handler 122 | .thumb_set hardfault_handler,_def_handler 123 | 124 | # ------------------------------------------------------------- 125 | .section .text.memmanage_handler 126 | .type memmanage_handler, %function 127 | .weak memmanage_handler 128 | .thumb_set memmanage_handler,_def_handler 129 | 130 | # ------------------------------------------------------------- 131 | .section .text.busfault_handler 132 | .type busfault_handler, %function 133 | .weak busfault_handler 134 | .thumb_set busfault_handler,_def_handler 135 | 136 | # ------------------------------------------------------------- 137 | .section .text.usagefault_handler 138 | .type usagefault_handler, %function 139 | .weak usagefault_handler 140 | .thumb_set usagefault_handler,_def_handler 141 | 142 | # ------------------------------------------------------------- 143 | .section .text.svc_handler 144 | .type svc_handler, %function 145 | .weak svc_handler 146 | .thumb_set svc_handler,_def_handler 147 | 148 | # ------------------------------------------------------------- 149 | .section .text.debugmon_handler 150 | .type debugmon_handler, %function 151 | .weak debugmon_handler 152 | .thumb_set debugmon_handler,_def_handler 153 | 154 | # ------------------------------------------------------------- 155 | .section .text.pendsv_handler 156 | .type pendsv_handler, %function 157 | .weak pendsv_handler 158 | .thumb_set pendsv_handler,_def_handler 159 | 160 | # ------------------------------------------------------------- 161 | .section .text.systick_handler 162 | .type systick_handler, %function 163 | .weak systick_handler 164 | .thumb_set systick_handler,_def_handler 165 | 166 | 167 | # ------------------------------------------------------------- 168 | .section .text.btn_handler 169 | .type btn_handler, %function 170 | .weak btn_handler 171 | .thumb_set btn_handler,_def_handler 172 | 173 | # ------------------------------------------------------------- 174 | .section .text.uart_handler 175 | .type uart_handler, %function 176 | .weak uart_handler 177 | .thumb_set uart_handler,_def_handler 178 | 179 | # ------------------------------------------------------------- 180 | .section .text._def_handler 181 | .type _def_handler, %function 182 | # ------------------------------------------------------------- 183 | # ------------------------------------------------------------- 184 | _def_handler: # Default Handler (Exception happen while starting) 185 | # ------------------------------------------------------------- 186 | b reset_handler // restart 187 | 188 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/newlib/newlib.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include 9 | 10 | // ---------------------------------------------------------------------------- 11 | int _close(int file) { 12 | // ---------------------------------------------------------------------------- 13 | 14 | return -1; 15 | } 16 | 17 | // ---------------------------------------------------------------------------- 18 | int _fstat(int file, struct stat *st) { 19 | // ---------------------------------------------------------------------------- 20 | 21 | st->st_mode = S_IFCHR; 22 | return 0; 23 | } 24 | 25 | // ---------------------------------------------------------------------------- 26 | void * _sbrk(int incr) { 27 | // ---------------------------------------------------------------------------- 28 | 29 | extern char _end[]; 30 | extern char _heap_end[]; 31 | static char *_heap_ptr = _end; 32 | 33 | if ((_heap_ptr + incr < _end) || (_heap_ptr + incr > _heap_end)) 34 | return (void *) -1; 35 | 36 | _heap_ptr += incr; 37 | return _heap_ptr - incr; 38 | } 39 | 40 | // ---------------------------------------------------------------------------- 41 | int _isatty(int file) { 42 | // ---------------------------------------------------------------------------- 43 | 44 | return (file == STDIN_FILENO || file == STDOUT_FILENO || file == STDERR_FILENO) ? 1 : 0; 45 | 46 | } 47 | 48 | // ---------------------------------------------------------------------------- 49 | int _lseek(int file, off_t ptr, int dir) { 50 | // ---------------------------------------------------------------------------- 51 | 52 | return 0; 53 | } 54 | 55 | // ---------------------------------------------------------------------------- 56 | int _open(const char* name, int flags, int mode) { 57 | // ---------------------------------------------------------------------------- 58 | 59 | if (strcmp(name, "UART")==0){ 60 | /* Enable the IOMUXC Clock */ 61 | CCM_REG(CCM_CCGR4) |= (0x3 << CCM_CCGR4_CG1); //(iomuxc_clk_enable) 62 | /* GPIO_AD_B0_06 is configured as LPUART1_TX */ 63 | IOMUX_REG(SW_MUX_CTL_PAD_GPIO_AD_B0_06) = (0x2 << SW_MUX_CTL_MUX_MODE); //ALT6: LPUART1_TX of instance: gpio1 64 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_06) = 0x10B0; 65 | /* GPIO_AD_B0_07 is configured as LPUART1_RX */ 66 | IOMUX_REG(SW_MUX_CTL_PAD_GPIO_AD_B0_07) = (0x2 << SW_MUX_CTL_MUX_MODE); //ALT7: LPUART1_TX of instance: gpio1 67 | IOMUX_REG(SW_PAD_CTL_PAD_GPIO_AD_B0_07) = 0x10B0; 68 | 69 | CCM_REG(CCM_CSCDR1) &= ~CCM_CSCDR1_UART_CLK_PODF_MASK; 70 | CCM_REG(CCM_CSCDR1) &= ~CCM_CSCDR1_UART_CLK_SEL_MASK; 71 | 72 | /* Enable the UART Clock */ 73 | CCM_REG(CCM_CCGR5) |= (0x3 << CCM_CCGR5_CG12); //(uartmuxc_clk_enable) 74 | /* write the sbr value to the BAUD registers */ 75 | UART1_REG(UART_BAUD) = UART_BAUD_VAL; 76 | /* Set bit count and parity mode. */ 77 | UART1_REG(UART_BAUD) &= ~UART_BAUD_M10_MASK; 78 | UART1_REG(UART_CTRL) = 0; 79 | UART1_REG(UART_WATER) = 0; 80 | 81 | /* Enable tx/rx FIFO */ 82 | UART1_REG(UART_FIFO) |= (UART_FIFO_TXFE_MASK | UART_FIFO_RXFE_MASK); 83 | /* Flush FIFO */ 84 | UART1_REG(UART_FIFO) |= (UART_FIFO_TXFLUSH_MASK | UART_FIFO_RXFLUSH_MASK); 85 | UART1_REG(UART_MODIR) = 0; 86 | 87 | UART1_REG(UART_STAT) |= UART_STAT_VAL; 88 | UART1_REG(UART_CTRL) = UART_CTRL_VAL; 89 | return 0; 90 | } 91 | 92 | return -1; 93 | } 94 | 95 | // ---------------------------------------------------------------------------- 96 | int _read(int file, char *ptr, size_t len) { 97 | // ---------------------------------------------------------------------------- 98 | if (isatty(file)) { 99 | 100 | ssize_t count = 0; 101 | int rxfifo = -1; 102 | 103 | while( count $(LST) 46 | 47 | $(ASM_OBJS): %.o: %.S $(HEADERS) 48 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 49 | 50 | $(C_OBJS): %.o: %.c $(HEADERS) 51 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 52 | 53 | .PHONY: clean 54 | clean: 55 | rm -f $(CLEAN_OBJS) 56 | 57 | -------------------------------------------------------------------------------- /bsp/IMXRT1020/platform.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef HEXFIVE_PLATFORM_H 4 | #define HEXFIVE_PLATFORM_H 5 | 6 | 7 | /************************************************************************************ 8 | * MIMXRT1020-EVK PLATFORM GERENIC 9 | ************************************************************************************/ 10 | 11 | #define CPU_FREQ (24000000) /*!< Hz */ 12 | #define RTC_FREQ (24000000) /*!< Hz */ 13 | 14 | #define MPU_REGIONS (16) 15 | 16 | #define UART_IRQn UART1_IRQn 17 | 18 | #define LED LED0 19 | #define LED_PIN LED0_PIN 20 | 21 | #define LED0 (5) 22 | #define LED0_PIN (1< $(TARGET).lst 29 | 30 | .PHONY: clean 31 | clean: 32 | rm -f $(TARGET).o $(TARGET).hex $(TARGET).elf $(TARGET).lst $(TARGET).map 33 | 34 | 35 | 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /bsp/STM32F767/boot/boot.S: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2023 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | /** 4 | * Hardware setup / OEM low-level boot code 5 | * - pass this file to multizone.jar via --boot option 6 | * - run in privileged mode after policy integrity check 7 | * - resume execution of MultiZone boot via MZONE_WFI() 8 | */ 9 | 10 | # Make sure that the GNU assembler is using a modern syntax for Arm THUMB. 11 | .syntax unified 12 | .arch armv7e-m 13 | 14 | # ------------------------------------------------------------- 15 | .align 2 16 | .section .text.vec 17 | .type _vec_tbl, %object 18 | # ------------------------------------------------------------- 19 | _vec_tbl: 20 | .word _stack_end // MSP definition 21 | .word _boot // Reset_Handler 22 | .word _boot // NMI_Handler 23 | 24 | # ------------------------------------------------------------- 25 | .align 2 26 | .section .text.boot 27 | .global _boot 28 | .type _boot, %function 29 | # ------------------------------------------------------------- 30 | _boot: 31 | # Hardware setup code goes here 32 | nop 33 | nop 34 | 35 | # Resume MultiZone boot (MZONE_WFI) 36 | movs r4, 0x1 37 | svc 0x1 38 | -------------------------------------------------------------------------------- /bsp/STM32F767/boot/linker.ld: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2023 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | ENTRY( _boot ) 4 | 5 | MEMORY { 6 | flash (rxai!w) : ORIGIN = flash + 0x2000, LENGTH = 2K 7 | ram (wxa!ri) : ORIGIN = dtcm + 0x1800, LENGTH = 2K 8 | } 9 | 10 | SECTIONS { 11 | .boot : { KEEP(*(.text.vec)); KEEP(*(.text.boot)); . = ALIGN(4); } > flash 12 | } 13 | 14 | _stack_end = ORIGIN(ram) + LENGTH(ram); -------------------------------------------------------------------------------- /bsp/STM32F767/gpio_driver.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef GPIO_DRIVER_H 4 | #define GPIO_DRIVER_H 5 | 6 | #define LED_INIT(_X_) \ 7 | { \ 8 | /* Enable the GPIO_LED Clock */ \ 9 | RCC_REG(RCC_AHB1ENR) |= RCC_AHB1ENR_GPIOBEN; \ 10 | /* Configure the IO Output Type */ \ 11 | GPIOB_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (_X_ * 2)); \ 12 | GPIOB_REG(GPIO_MODER) |= ((GPIO_MODE_OUTPUT) << (_X_ * 2)); \ 13 | /* Configure the IO Speed */ \ 14 | GPIOB_REG(GPIO_OSPEEDR) &= ~(GPIO_OSPEEDER_OSPEEDR0 << (_X_ * 2)); \ 15 | GPIOB_REG(GPIO_OSPEEDR) |= (GPIO_SPEED_FREQ_VERY_HIGH<< (_X_ * 2)); \ 16 | /* Configure the IO Output Type */ \ 17 | GPIOB_REG(GPIO_OTYPER) &= ~(GPIO_OTYPER_OT_0 << _X_) ; \ 18 | GPIOB_REG(GPIO_OTYPER) |= (((GPIO_MODE_OUTPUT & GPIO_OUTPUT_TYPE) >> 4) << _X_); \ 19 | /* Activate the Pull-up or Pull down resistor for the current IO */ \ 20 | GPIOB_REG(GPIO_PUPDR) &= ~(GPIO_PUPDR_PUPDR0 << (_X_ * 2)); \ 21 | GPIOB_REG(GPIO_PUPDR) |= ((GPIO_NOPULL) << (_X_ * 2)); \ 22 | } 23 | 24 | #define LED_SET(_X_) GPIOB_REG(GPIO_BSRR) = (1 << _X_) 25 | 26 | #define LED_CLR(_X_) GPIOB_REG(GPIO_BSRR) = (uint32_t) (1 << _X_) << GPIO_NUMBER 27 | 28 | #define LED_OUT(_X_) (GPIOB_REG(GPIO_ODR) & (1 << _X_)) == (1 << _X_) 29 | 30 | #define BTN_INIT(_X_) \ 31 | { \ 32 | /* Enable the GPIO_LED Clock */ \ 33 | RCC_REG(RCC_AHB1ENR) |= RCC_AHB1ENR_GPIOCEN; \ 34 | /* APB2 Peripheral Clock Enable Disable */ \ 35 | RCC_REG(RCC_APB2ENR) |= RCC_APB2ENR_SYSCFGEN; \ 36 | /* Configure source input for the EXTI external interrupt. */ \ 37 | SYSCFG_REG(SYSCFG_EXTICR3) &= ~(SYSCFG_EXTI_LINE13 >> 16U); \ 38 | SYSCFG_REG(SYSCFG_EXTICR3) |= SYSCFG_EXTI_PORTC << 4U; \ 39 | /* Enable IT on provided Lines */ \ 40 | EXTI_REG(EXTI_EMR) &= ~(EXTI_IMR_MR13); \ 41 | EXTI_REG(EXTI_IMR) |= EXTI_IMR_MR13; \ 42 | /* Enable Rising Trigger on provided Lines */ \ 43 | EXTI_REG(EXTI_FTSR) &= ~(EXTI_IMR_MR13); \ 44 | EXTI_REG(EXTI_RTSR) |= EXTI_IMR_MR13; \ 45 | GPIOC_REG(GPIO_PUPDR) &= ~(GPIO_PUPDR_PUPDR0 << (_X_ * 2U)); \ 46 | GPIOC_REG(GPIO_PUPDR) |= (GPIO_NOPULL << (_X_ * 2U)); \ 47 | GPIOC_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (_X_ * 2U)); \ 48 | GPIOC_REG(GPIO_MODER) |= (GPIO_MODE_INPUT << (_X_ * 2U)); \ 49 | } 50 | 51 | #define BTN_IRQ_CLR() \ 52 | { \ 53 | EXTI_REG(EXTI_PR) |= EXTI_IMR_MR13; \ 54 | } 55 | 56 | #define SPI_INIT(_X_, _Y_, _Z_) \ 57 | { \ 58 | /* Enable the GPIOA Clock*/ \ 59 | RCC_REG(RCC_AHB1ENR) |= (RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN); \ 60 | /* Configure the IO Output Type */ \ 61 | GPIOF_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (_Y_ * 2)); \ 62 | GPIOE_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (_Z_ * 2)); \ 63 | GPIOF_REG(GPIO_MODER) |= (GPIO_MODE_OUTPUT << (_Y_ * 2)); \ 64 | GPIOE_REG(GPIO_MODER) |= (GPIO_MODE_OUTPUT << (_Z_ * 2)); \ 65 | /* Configure the IO Speed */ \ 66 | GPIOF_REG(GPIO_OSPEEDR) &= ~(GPIO_OSPEEDER_OSPEEDR0 << (_Y_ * 2)); \ 67 | GPIOE_REG(GPIO_OSPEEDR) &= ~(GPIO_OSPEEDER_OSPEEDR0 << (_Z_ * 2)); \ 68 | GPIOF_REG(GPIO_OSPEEDR) |= (GPIO_SPEED_FREQ_VERY_HIGH << (_Y_ * 2)); \ 69 | GPIOE_REG(GPIO_OSPEEDR) |= (GPIO_SPEED_FREQ_VERY_HIGH << (_Z_ * 2)); \ 70 | /* Configure the IO Output Type */ \ 71 | GPIOF_REG(GPIO_OTYPER) &= ~(GPIO_OTYPER_OT_0 << _Y_); \ 72 | GPIOE_REG(GPIO_OTYPER) &= ~(GPIO_OTYPER_OT_0 << _Z_); \ 73 | GPIOF_REG(GPIO_OTYPER) |= (((GPIO_MODE_OUTPUT & GPIO_OUTPUT_TYPE) >> 4) << _Y_); \ 74 | GPIOE_REG(GPIO_OTYPER) |= (((GPIO_MODE_OUTPUT & GPIO_OUTPUT_TYPE) >> 4) << _Z_); \ 75 | /* Activate the Pull-up or Pull down resistor for the current IO */ \ 76 | GPIOF_REG(GPIO_PUPDR) &= ~(GPIO_PUPDR_PUPDR0 << (_Y_ * 2)); \ 77 | GPIOE_REG(GPIO_PUPDR) &= ~(GPIO_PUPDR_PUPDR0 << (_Z_ * 2)); \ 78 | GPIOF_REG(GPIO_PUPDR) |= ((GPIO_NOPULL) << (_Y_ * 2)); \ 79 | GPIOE_REG(GPIO_PUPDR) |= ((GPIO_NOPULL) << (_Z_ * 2)); \ 80 | GPIOF_REG(GPIO_BSRR) |= (0x1 << _Y_); \ 81 | GPIOE_REG(GPIO_BSRR) |= (0x1 << _Z_); \ 82 | /* Configure port mode */ \ 83 | GPIOE_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (_X_ * 2)); \ 84 | /* Activate the Pull-up for the current IO */ \ 85 | GPIOE_REG(GPIO_PUPDR) &= ~(GPIO_PUPDR_PUPDR0 << (_X_ * 2)); \ 86 | GPIOE_REG(GPIO_PUPDR) |= ((GPIO_PULLUP) << (_X_ * 2)); \ 87 | } 88 | 89 | #define SPI_TDO_SET(_X_) GPIOE_REG(GPIO_ODR) |= (0x1 << _X_) 90 | 91 | #define SPI_TDO_CLR(_X_) GPIOE_REG(GPIO_ODR) &= ~(0x1 << _X_) 92 | 93 | #define SPI_TDI_BIT(_X_) (GPIOE_REG(GPIO_IDR) >> _X_) & 1U 94 | 95 | #define SPI_TCK_LOW(_X_) GPIOF_REG(GPIO_ODR) |= (0x1 << _X_) 96 | #define SPI_TCK_HIGH(_X_) GPIOF_REG(GPIO_ODR) ^= (0x1 << _X_) 97 | 98 | #define UART_IRQ_CLR() \ 99 | { \ 100 | } 101 | 102 | #define UART_IRQ_RX() ((USART3_REG(USART_ISR) & USART_ISR_RXNE) == USART_ISR_RXNE) 103 | 104 | 105 | #endif 106 | -------------------------------------------------------------------------------- /bsp/STM32F767/memory.lds: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2019 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | flash = 0x08000000; 4 | itcm = 0x08000000; 5 | dtcm = 0x20002000; /* DTCM 0x2000_0000 64K */ 6 | -------------------------------------------------------------------------------- /bsp/STM32F767/multizone.cfg: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | # MultiZone reserved memory: 8K @0x08000000, 8K @0x20000000 4 | 5 | Tick = 10 # ms 6 | 7 | Zone = 1 8 | irq = 55 9 | base = 0x08008000; size = 32K; rwx = rx # FLASH 10 | base = 0x20002000; size = 4K; rwx = rw # RAM 11 | base = 0x40023800; size = 0x80; rwx = rw # RCC (CLK USART) 12 | base = 0x40020C00; size = 0x40; rwx = rw # GPIOD (UART_RX & UART_TX) 13 | base = 0x40004800; size = 0x40; rwx = rw # USART3 14 | 15 | Zone = 2 16 | irq = 56 17 | base = 0x08010000; size = 32K; rwx = rx # FLASH 18 | base = 0x20003000; size = 4K; rwx = rw # RAM 19 | base = 0x40023800; size = 0x80; rwx = rw # RCC (CLK LED) 20 | base = 0x40020400; size = 0x40; rwx = rw # GPIOB (LED) 21 | base = 0x40020800; size = 0x40; rwx = rw # GPIOC (BTN) 22 | base = 0x40013800; size = 0x20; rwx = rw # SYSCFG 23 | base = 0x40013C00; size = 0x20; rwx = rw # EXTI 24 | 25 | Zone = 3 26 | base = 0x08018000; size = 32K; rwx = rx # FLASH 27 | base = 0x20004000; size = 4K; rwx = rw # RAM 28 | base = 0x40023800; size = 0x80; rwx = rw # RCC (CLK SPI) 29 | base = 0x40021000; size = 0x40; rwx = rw # GPIOE (SPI) 30 | base = 0x40021400; size = 0x40; rwx = rw # GPIOF (SPI) 31 | -------------------------------------------------------------------------------- /bsp/STM32F767/newlib/crt0.S: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | # Make sure that the GNU assembler is using a modern syntax for Arm THUMB. 4 | .syntax unified 5 | .arch armv7e-m 6 | 7 | /** 8 | * These are the addresses for the initialized (data) and uninitialized (bss) 9 | * variables. The initialized variables will be copied from FLASH to RAM. The 10 | * uninitialized variables will be set to 0. These addresses are set in the 11 | * linker file. 12 | */ 13 | .word __data_vma_start 14 | .word __data_start 15 | .word __data_end 16 | .word __bss_start 17 | .word __bss_end 18 | 19 | # ------------------------------------------------------------- 20 | .section .text.isr_vector 21 | .align 2 22 | .globl __isr_vector 23 | # ------------------------------------------------------------- 24 | __isr_vector: 25 | .word __end_stack // MSP definition 26 | .word reset_handler // Reset_Handler 27 | .word nmi_handler // NMI_Handler 28 | .word hardfault_handler // HardFault_Handler 29 | .word memmanage_handler // MemManage_Handler 30 | .word busfault_handler // BusFault_Handler 31 | .word usagefault_handler // UsageFault_Handler 32 | .word 0 // Not Defined 33 | .word 0 // Not Defined 34 | .word 0 // Not Defined 35 | .word 0 // Not Defined 36 | .word svc_handler // SVC_Handler 37 | .word debugmon_handler // DebugMon_Handler 38 | .word 0 // Not Defined 39 | .word pendsv_handler // PendSV_Handler 40 | .word systick_handler // SysTick_Handler 41 | .rept 39 // Repeat for 42 | .word _def_handler // IRQ0_Handler to IRQ38_Handler 43 | .endr 44 | .word uart_handler // USART3_Handler 45 | .word btn_handler // EXTI15_10_Handler 46 | .rept 69 // Repeat for 47 | .word _def_handler // IRQ41_Handler to IRQ109_Handler 48 | .endr 49 | .size __isr_vector, . - __isr_vector 50 | 51 | # ------------------------------------------------------------- 52 | .align 2 53 | .section .text.init 54 | .global reset_handler 55 | .type reset_handler, %function 56 | # ------------------------------------------------------------- 57 | reset_handler: 58 | ldr sp, =__end_stack /* set stack pointer */ 59 | 60 | // Copy the initialized global variables to RAM 61 | mov r0, #0 62 | ldr r1, = __data_start 63 | ldr r2, = __data_end 64 | ldr r3, = __data_vma_start 65 | b loopcopy_data 66 | 67 | copy_data: 68 | ldr r4, [r3, r0] 69 | str r4, [r1, r0] 70 | adds r0, r0, #4 71 | 72 | loopcopy_data: 73 | add r4, r1, r0 74 | cmp r4, r2 75 | bcc copy_data 76 | 77 | // Fill uninitialized variables with zeros 78 | mov r0, #0 79 | ldr r1, = __bss_start 80 | ldr r2, = __bss_end 81 | b loopfill_zerobss 82 | 83 | fill_zerobss: 84 | str r0, [r1] 85 | add r1, r1, #4 86 | 87 | loopfill_zerobss: 88 | cmp r1, r2 89 | bcc fill_zerobss 90 | 91 | // Call the libc init function 92 | bl __libc_init_array 93 | 94 | // Call the main function 95 | bl main 96 | 97 | 98 | .global _init 99 | .type _init, %function 100 | _init: 101 | bx lr 102 | .size _init, .-_init 103 | 104 | .global _fini 105 | .type _fini, %function 106 | _fini: 107 | bx lr 108 | .size _fini, .-_fini 109 | 110 | # ------------------------------------------------------------- 111 | .section .text.nmi_handler 112 | .type nmi_handler, %function 113 | .weak nmi_handler 114 | .thumb_set nmi_handler,_def_handler 115 | 116 | # ------------------------------------------------------------- 117 | .section .text.hardfault_handler 118 | .type hardfault_handler, %function 119 | .weak hardfault_handler 120 | .thumb_set hardfault_handler,_def_handler 121 | 122 | # ------------------------------------------------------------- 123 | .section .text.memmanage_handler 124 | .type memmanage_handler, %function 125 | .weak memmanage_handler 126 | .thumb_set memmanage_handler,_def_handler 127 | 128 | # ------------------------------------------------------------- 129 | .section .text.busfault_handler 130 | .type busfault_handler, %function 131 | .weak busfault_handler 132 | .thumb_set busfault_handler,_def_handler 133 | 134 | # ------------------------------------------------------------- 135 | .section .text.usagefault_handler 136 | .type usagefault_handler, %function 137 | .weak usagefault_handler 138 | .thumb_set usagefault_handler,_def_handler 139 | 140 | # ------------------------------------------------------------- 141 | .section .text.svc_handler 142 | .type svc_handler, %function 143 | .weak svc_handler 144 | .thumb_set svc_handler,_def_handler 145 | 146 | # ------------------------------------------------------------- 147 | .section .text.debugmon_handler 148 | .type debugmon_handler, %function 149 | .weak debugmon_handler 150 | .thumb_set debugmon_handler,_def_handler 151 | 152 | # ------------------------------------------------------------- 153 | .section .text.pendsv_handler 154 | .type pendsv_handler, %function 155 | .weak pendsv_handler 156 | .thumb_set pendsv_handler,_def_handler 157 | 158 | # ------------------------------------------------------------- 159 | .section .text.systick_handler 160 | .type systick_handler, %function 161 | .weak systick_handler 162 | .thumb_set systick_handler,_def_handler 163 | 164 | 165 | # ------------------------------------------------------------- 166 | .section .text.btn_handler 167 | .type btn_handler, %function 168 | .weak btn_handler 169 | .thumb_set btn_handler,_def_handler 170 | 171 | # ------------------------------------------------------------- 172 | .section .text.uart_handler 173 | .type uart_handler, %function 174 | .weak uart_handler 175 | .thumb_set uart_handler,_def_handler 176 | 177 | # ------------------------------------------------------------- 178 | .section .text._def_handler 179 | .type _def_handler, %function 180 | # ------------------------------------------------------------- 181 | # ------------------------------------------------------------- 182 | _def_handler: # Default Handler (Exception happen while starting) 183 | # ------------------------------------------------------------- 184 | b reset_handler // restart 185 | -------------------------------------------------------------------------------- /bsp/STM32F767/newlib/newlib.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include 9 | 10 | // ---------------------------------------------------------------------------- 11 | int _close(int file) { 12 | // ---------------------------------------------------------------------------- 13 | 14 | return -1; 15 | } 16 | 17 | // ---------------------------------------------------------------------------- 18 | int _fstat(int file, struct stat *st) { 19 | // ---------------------------------------------------------------------------- 20 | 21 | st->st_mode = S_IFCHR; 22 | return 0; 23 | } 24 | 25 | // ---------------------------------------------------------------------------- 26 | void * _sbrk(int incr) { 27 | // ---------------------------------------------------------------------------- 28 | 29 | extern char _end[]; 30 | extern char _heap_end[]; 31 | static char *_heap_ptr = _end; 32 | 33 | if ((_heap_ptr + incr < _end) || (_heap_ptr + incr > _heap_end)) 34 | return (void *) -1; 35 | 36 | _heap_ptr += incr; 37 | return _heap_ptr - incr; 38 | } 39 | 40 | // ---------------------------------------------------------------------------- 41 | int _isatty(int file) { 42 | // ---------------------------------------------------------------------------- 43 | 44 | return (file == STDIN_FILENO || file == STDOUT_FILENO || file == STDERR_FILENO) ? 1 : 0; 45 | 46 | } 47 | 48 | // ---------------------------------------------------------------------------- 49 | int _lseek(int file, off_t ptr, int dir) { 50 | // ---------------------------------------------------------------------------- 51 | 52 | return 0; 53 | } 54 | 55 | // ---------------------------------------------------------------------------- 56 | int _open(const char* name, int flags, int mode) { 57 | // ---------------------------------------------------------------------------- 58 | 59 | if (strcmp(name, "UART")==0){ 60 | /* Peripheral clock enable */ 61 | RCC_REG(RCC_APB1ENR) |= RCC_APB1ENR_USART3EN; 62 | RCC_REG(RCC_AHB1ENR) |= RCC_AHB1ENR_GPIODEN; 63 | /**UART GPIO Configuration 64 | * UART_RX 65 | * UART_TX 66 | */ 67 | 68 | /* Configure the GPIO UART_RX */ 69 | GPIOD_REG(GPIO_OSPEEDR) &= ~(GPIO_OSPEEDER_OSPEEDR0 << (UART_RX_OFFSET * 2)); 70 | GPIOD_REG(GPIO_OSPEEDR) |= (GPIO_SPEED_FREQ_VERY_HIGH << (UART_RX_OFFSET * 2)); 71 | 72 | GPIOD_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (UART_RX_OFFSET * 2)); 73 | GPIOD_REG(GPIO_MODER) |= ((GPIO_MODE_ALTERNATE) << (UART_RX_OFFSET * 2)); 74 | 75 | GPIOD_REG(GPIO_OTYPER) &= ~(GPIO_OTYPER_OT_0 << UART_RX_OFFSET); 76 | GPIOD_REG(GPIO_OTYPER) |= (((GPIO_OUTPUT_PUSHPULL & GPIO_OUTPUT_TYPE) >> 4) << UART_RX_OFFSET); 77 | 78 | GPIOD_REG(GPIO_AFR1) &= ~(GPIO_AFRH_AFRH0 << ((UART_RX_OFFSET - 8U) * 4U)), 79 | GPIOD_REG(GPIO_AFR1) |= (GPIO_AF_7 << ((UART_RX_OFFSET - 8U) * 4U)); 80 | 81 | /* Configure the GPIO UART_TX */ 82 | GPIOD_REG(GPIO_OSPEEDR) &= ~(GPIO_OSPEEDER_OSPEEDR0 << (UART_TX_OFFSET * 2)); 83 | GPIOD_REG(GPIO_OSPEEDR) |= (GPIO_SPEED_FREQ_VERY_HIGH<< (UART_TX_OFFSET * 2)); 84 | 85 | GPIOD_REG(GPIO_MODER) &= ~(GPIO_MODER_MODER0 << (UART_TX_OFFSET * 2)); 86 | GPIOD_REG(GPIO_MODER) |= ((GPIO_MODE_ALTERNATE) << (UART_TX_OFFSET * 2)); 87 | 88 | GPIOD_REG(GPIO_OTYPER) &= ~(GPIO_OTYPER_OT_0 << UART_TX_OFFSET) ; 89 | GPIOD_REG(GPIO_OTYPER) |= (((GPIO_OUTPUT_PUSHPULL & GPIO_OUTPUT_TYPE) >> 4) << UART_RX_OFFSET); 90 | 91 | GPIOD_REG(GPIO_AFR1) &= ~(GPIO_AFRH_AFRH0 << ((UART_TX_OFFSET - 8U) * 4U)), 92 | GPIOD_REG(GPIO_AFR1) |= (GPIO_AF_7 << ((UART_TX_OFFSET - 8U) * 4U)); 93 | 94 | /* Configure the USART3 */ 95 | USART3_REG(USART_CR1) = USART3_REG(USART_CR1) & ~(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8) 96 | | (USART_DATAWIDTH_8B | USART_PARITY_NONE | USART_DIRECTION_TX_RX | USART_OVERSAMPLING_16); 97 | 98 | USART3_REG(USART_CR2) &= ~(USART_CR2_STOP); 99 | USART3_REG(USART_CR2) |= USART_STOPBITS_1; 100 | 101 | USART3_REG(USART_CR3) &= ~(USART_CR3_RTSE | USART_CR3_CTSE); 102 | USART3_REG(USART_CR3) |= USART_HWCONTROL_NONE; 103 | 104 | USART3_REG(USART_BRR) = (uint16_t)(((USART3_PERIPHCLK) + ((USART_BAUDRATE)/2U))/(USART_BAUDRATE)); 105 | 106 | /* Configure AsyncMode */ 107 | USART3_REG(USART_CR2) &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); 108 | USART3_REG(USART_CR3) &= ~(USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL); 109 | 110 | /* Enable USART */ 111 | USART3_REG(USART_CR1) |= (USART_CR1_RXNEIE); 112 | USART3_REG(USART_CR1) |= (USART_CR1_UE); 113 | 114 | return 0; 115 | 116 | } 117 | 118 | return -1; 119 | } 120 | 121 | // ---------------------------------------------------------------------------- 122 | int _read(int file, char *ptr, size_t len) { 123 | // ---------------------------------------------------------------------------- 124 | if (isatty(file)) { 125 | 126 | ssize_t count = 0; 127 | int rxfifo = -1; 128 | 129 | while( count\n", 5); char c='\0'; while(1) if ( read(0, &c, 1) >0 ) write(1, &c, 1); 168 | -------------------------------------------------------------------------------- /bsp/STM32F767/newlib/newlib.mk: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | .PHONY: all 4 | all: $(TARGET) 5 | 6 | ASM_SRCS += $(NEWLIB_DIR)/crt0.S 7 | C_SRCS += $(NEWLIB_DIR)/newlib.c 8 | 9 | INCLUDES += -I$(PLATFORM_DIR) 10 | 11 | MCUFLAGS += -march=$(ARM_ARCH) 12 | MCUFLAGS += -mcpu=$(ARM_CPU) 13 | MCUFLAGS += -mfloat-abi=$(ARM_FLOAT) 14 | MCUFLAGS += -mfpu=$(ARM_FPU) 15 | 16 | LDFLAGS += -T $(PLATFORM_DIR)/memory.lds 17 | LDFLAGS += -T $(LINKER_SCRIPT) 18 | LDFLAGS += -static $(MCUFLAGS) 19 | LDFLAGS += -mthumb 20 | LDFLAGS += --specs=nano.specs 21 | LDFLAGS += -nostartfiles 22 | LDFLAGS += -Xlinker --gc-sections 23 | 24 | ASM_OBJS := $(ASM_SRCS:.S=.o) 25 | C_OBJS := $(C_SRCS:.c=.o) 26 | 27 | LINK_OBJS += $(ASM_OBJS) $(C_OBJS) 28 | LINK_DEPS += $(LINKER_SCRIPT) 29 | 30 | CLEAN_OBJS += $(TARGET) $(LINK_OBJS) 31 | 32 | CFLAGS += -g -gdwarf-4 33 | CFLAGS += -ffunction-sections -fdata-sections -fomit-frame-pointer 34 | CFLAGS += $(MCUFLAGS) 35 | CFLAGS += -O0 36 | 37 | HEX = $(subst .elf,.hex,$(TARGET)) 38 | LST = $(subst .elf,.lst,$(TARGET)) 39 | CLEAN_OBJS += $(HEX) 40 | CLEAN_OBJS += $(LST) 41 | 42 | $(TARGET): $(LINK_OBJS) $(LINK_DEPS) 43 | $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) $(LDFLAGS) -o $@ 44 | $(OBJCOPY) -O ihex $(TARGET) $(HEX) 45 | $(OBJDUMP) --all-headers --demangle --disassemble --file-headers --wide -D $(TARGET) > $(LST) 46 | 47 | $(ASM_OBJS): %.o: %.S $(HEADERS) 48 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 49 | 50 | $(C_OBJS): %.o: %.c $(HEADERS) 51 | $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< 52 | 53 | .PHONY: clean 54 | clean: 55 | rm -f $(CLEAN_OBJS) 56 | 57 | -------------------------------------------------------------------------------- /bsp/STM32F767/openocd.cfg: -------------------------------------------------------------------------------- 1 | # script for stm32f7x family 2 | 3 | # 4 | # stm32f7 devices support both JTAG and SWD transports. 5 | # 6 | source [find target/swj-dp.tcl] 7 | source [find mem_helper.tcl] 8 | 9 | if { [info exists CHIPNAME] } { 10 | set _CHIPNAME $CHIPNAME 11 | } else { 12 | set _CHIPNAME stm32f7x 13 | } 14 | 15 | set _ENDIAN little 16 | 17 | # Work-area is a space in RAM used for flash programming 18 | # By default use 128kB 19 | if { [info exists WORKAREASIZE] } { 20 | set _WORKAREASIZE $WORKAREASIZE 21 | } else { 22 | set _WORKAREASIZE 0x20000 23 | } 24 | 25 | #jtag scan chain 26 | if { [info exists CPUTAPID] } { 27 | set _CPUTAPID $CPUTAPID 28 | } else { 29 | if { [using_jtag] } { 30 | # See STM Document RM0385 31 | # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0 32 | set _CPUTAPID 0x5ba00477 33 | } { 34 | set _CPUTAPID 0x5ba02477 35 | } 36 | } 37 | 38 | swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID 39 | dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu 40 | 41 | if {[using_jtag]} { 42 | jtag newtap $_CHIPNAME bs -irlen 5 43 | } 44 | 45 | set _TARGETNAME $_CHIPNAME.cpu 46 | target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap 47 | 48 | $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 49 | 50 | set _FLASHNAME $_CHIPNAME.flash 51 | flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME 52 | 53 | # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz 54 | adapter_khz 2000 55 | 56 | adapter_nsrst_delay 100 57 | if {[using_jtag]} { 58 | jtag_ntrst_delay 100 59 | } 60 | 61 | # Use hardware reset. 62 | # 63 | # This target is compatible with connect_assert_srst, which may be set in a 64 | # board file. 65 | reset_config srst_only srst_nogate 66 | 67 | if {![using_hla]} { 68 | # if srst is not fitted use SYSRESETREQ to 69 | # perform a soft reset 70 | cortex_m reset_config sysresetreq 71 | 72 | # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal 73 | # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 74 | # makes the data access cacheable. This allows reading and writing data in the 75 | # CPU cache from the debugger, which is far more useful than going straight to 76 | # RAM when operating on typical variables, and is generally no worse when 77 | # operating on special memory locations. 78 | $_CHIPNAME.dap apcsw 0x08000000 0x08000000 79 | } 80 | 81 | $_TARGETNAME configure -event examine-end { 82 | # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP 83 | mmw 0xE0042004 0x00000007 0 84 | 85 | # Stop watchdog counters during halt 86 | # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP 87 | mmw 0xE0042008 0x00001800 0 88 | } 89 | 90 | $_TARGETNAME configure -event trace-config { 91 | # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync 92 | # change this value accordingly to configure trace pins 93 | # assignment 94 | mmw 0xE0042004 0x00000020 0 95 | } 96 | 97 | $_TARGETNAME configure -event reset-init { 98 | # If the HSE was previously enabled and the external clock source 99 | # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be 100 | # properly switched back to HSI. This situation persists even over a system 101 | # reset, including a pin reset via SRST. However, activating the clock 102 | # security system will detect the problem and clear HSERDY to 0, which in 103 | # turn allows the PLL to switch back to HSI properly. Since we just came 104 | # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must 105 | # have happened; in that case, activate the clock security system to clear 106 | # HSERDY. 107 | if {[mrw 0x40023800] & 0x00020000} { 108 | mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON 109 | sleep 10 ;# Wait for CSS to fire, if it wants to 110 | mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON 111 | mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC 112 | sleep 1 ;# Wait for CSSF to clear 113 | } 114 | 115 | # If the clock security system fired, it will pend an NMI. A pending NMI 116 | # will cause a bad time for any subsequent executing code, such as a 117 | # programming algorithm. 118 | if {[mrw 0xE000ED04] & 0x80000000} { 119 | # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be 120 | # cleared by any normal means (such as ICSR or NVIC). It can only be 121 | # cleared by entering the NMI handler or by resetting the processor. 122 | echo "[target current]: Clock security system generated NMI. Clearing." 123 | 124 | # Keep the old DEMCR value. 125 | set old [mrw 0xE000EDFC] 126 | 127 | # Enable vector catch on reset. 128 | mww 0xE000EDFC 0x01000001 129 | 130 | # Issue local reset via AIRCR. 131 | mww 0xE000ED0C 0x05FA0001 132 | 133 | # Restore old DEMCR value. 134 | mww 0xE000EDFC $old 135 | } 136 | 137 | # Configure PLL to boost clock to HSI x 10 (160 MHz) 138 | mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P) 139 | mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency) 140 | mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON 141 | sleep 10 ;# Wait for PLL to lock 142 | mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2) 143 | mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL 144 | 145 | # Boost SWD frequency 146 | # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo 147 | # suffers from DAP WAITs 148 | if {[using_jtag]} { 149 | [[target current] cget -dap] memaccess 16 150 | } { 151 | adapter_khz 8000 152 | } 153 | } 154 | 155 | $_TARGETNAME configure -event reset-start { 156 | # Reduce speed since CPU speed will slow down to 16MHz with the reset 157 | adapter_khz 2000 158 | } 159 | 160 | $_TARGETNAME configure -event gdb-attach { 161 | init 162 | } 163 | 164 | $_TARGETNAME configure -event gdb-attach { 165 | reset halt 166 | } 167 | -------------------------------------------------------------------------------- /bsp/STM32F767/stlink.cfg: -------------------------------------------------------------------------------- 1 | # 2 | # STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit 3 | # debugger/programmer 4 | # 5 | 6 | interface hla 7 | hla_layout stlink 8 | hla_device_desc "ST-LINK" 9 | hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 10 | 11 | # Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 12 | # devices seem to have serial numbers with unreadable characters. ST-LINK/V2 13 | # firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial 14 | # number reset issues. 15 | # eg. 16 | #hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" 17 | -------------------------------------------------------------------------------- /manual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hex-five/multizone-sdk-arm/16b4c4a15b2bafd60288438f8a97ff30d4a169ac/manual.pdf -------------------------------------------------------------------------------- /multizone-sdk-arm ATSAME70.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /multizone-sdk-arm EKRA6M3.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /multizone-sdk-arm GD32307.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /multizone-sdk-arm IMXRT1020.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /multizone-sdk-arm STM32F767.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | -------------------------------------------------------------------------------- /multizone.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hex-five/multizone-sdk-arm/16b4c4a15b2bafd60288438f8a97ff30d4a169ac/multizone.jar -------------------------------------------------------------------------------- /zone1/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | TARGET = zone1.elf 4 | 5 | BSP_BASE := ../bsp 6 | PLATFORM_DIR := $(BSP_BASE)/$(BOARD) 7 | NEWLIB_DIR := $(PLATFORM_DIR)/newlib 8 | 9 | LINKER_SCRIPT := linker.ld 10 | 11 | C_SRCS += main.c 12 | 13 | INCLUDES += -I../. 14 | LDFLAGS += -L../. 15 | 16 | include $(NEWLIB_DIR)/newlib.mk 17 | 18 | 19 | -------------------------------------------------------------------------------- /zone1/linker.ld: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 4 | 5 | ENTRY( reset_handler ) 6 | 7 | MEMORY { 8 | flash (rxai!w) : ORIGIN = flash + 0x08000, LENGTH = 32K 9 | itcm (rxai!w) : ORIGIN = itcm + 0x08000, LENGTH = 32K 10 | dtcm (wxa!ri) : ORIGIN = dtcm + 0x00000, LENGTH = 4K 11 | } 12 | 13 | __end_stack = _sp; 14 | SECTIONS { 15 | __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; 16 | /* Put startup code into FLASH, ALWAYS DO THIS FIRST */ 17 | 18 | 19 | /* Put program code and other data into FLASH */ 20 | .text : { 21 | . = ALIGN(4); 22 | __text_start = .; 23 | 24 | KEEP(*(.text.isr_vector)); 25 | *(.text) 26 | *(.text*) 27 | *(.glue_7) 28 | *(.glue_7t) 29 | *(.eh_frame) 30 | 31 | KEEP(*(.init)) 32 | KEEP(*(.fini)) 33 | 34 | . = ALIGN(4); 35 | __text_end = .; 36 | } > itcm AT>flash 37 | 38 | /* Put constant (read-only) data into FLASH */ 39 | .rodata : { 40 | . = ALIGN(4); 41 | __rodata_start = .; 42 | 43 | *(.rodata) 44 | *(.rodata*) 45 | 46 | . = ALIGN(4); 47 | __rodata_end = .; 48 | } > itcm AT>flash 49 | 50 | .ARM.extab : { 51 | *(.ARM.extab* .gnu.linkonce.armextab.*) 52 | } > itcm AT>flash 53 | 54 | .ARM : { 55 | __exidx_start = .; 56 | *(.ARM.exidx*) 57 | __exidx_end = .; 58 | } > itcm AT>flash 59 | 60 | .preinit_array : { 61 | PROVIDE_HIDDEN(__preinit_array_start = .); 62 | KEEP(*(.preinit_array*)) 63 | PROVIDE_HIDDEN(__preinit_array_end = .); 64 | } > itcm AT>flash 65 | .init_array : { 66 | PROVIDE_HIDDEN(__init_array_start = .); 67 | KEEP(*(.init_array*)) 68 | PROVIDE_HIDDEN(__init_array_end = .); 69 | } > itcm AT>flash 70 | .fini_array : { 71 | PROVIDE_HIDDEN(__fini_array_start = .); 72 | KEEP(*(.fini_array*)) 73 | PROVIDE_HIDDEN(__fini_array_end = .); 74 | } > itcm AT>flash 75 | 76 | .lalign : { 77 | PROVIDE( __data_vma_start = . ); 78 | } > itcm AT>flash 79 | 80 | .data : { 81 | . = ALIGN(4); 82 | __data_start = .; 83 | 84 | *(.data) 85 | *(.data*) 86 | 87 | . = ALIGN(4); 88 | __data_end = .; 89 | } > dtcm AT>flash 90 | 91 | .bss : { 92 | . = ALIGN(4); 93 | __bss_start = .; 94 | __bss_start__ = __bss_start; 95 | 96 | *(.bss) 97 | *(.bss*) 98 | *(COMMON) 99 | 100 | . = ALIGN(4); 101 | __bss_end = .; 102 | __bss_end__ = __bss_end; 103 | } > dtcm AT>dtcm 104 | 105 | . = ALIGN(4); 106 | PROVIDE( _end = . ); 107 | PROVIDE( end = . ); 108 | 109 | . = ALIGN(4); 110 | PROVIDE( _end = . ); 111 | PROVIDE( end = . ); 112 | 113 | .stack ORIGIN(dtcm) + LENGTH(dtcm) - __stack_size : { 114 | PROVIDE( _heap_end = . ); 115 | . = __stack_size; 116 | PROVIDE( _sp = . ); 117 | } >dtcm AT>dtcm 118 | 119 | /DISCARD/ : { 120 | libc.a(*) 121 | libm.a(*) 122 | libgcc.a(*) 123 | } 124 | 125 | .ARM.attributes 0 : { 126 | *(.ARM.attributes) 127 | } 128 | } 129 | -------------------------------------------------------------------------------- /zone2/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | TARGET = zone2.elf 4 | 5 | BSP_BASE := ../bsp 6 | PLATFORM_DIR := $(BSP_BASE)/$(BOARD) 7 | NEWLIB_DIR := $(PLATFORM_DIR)/newlib 8 | 9 | LINKER_SCRIPT := linker.ld 10 | 11 | C_SRCS += main.c 12 | 13 | INCLUDES += -I../. 14 | LDFLAGS += -L../. 15 | 16 | include $(NEWLIB_DIR)/newlib.mk 17 | 18 | -------------------------------------------------------------------------------- /zone2/linker.ld: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 4 | 5 | ENTRY( reset_handler ) 6 | 7 | MEMORY { 8 | flash (rxai!w) : ORIGIN = flash + 0x10000, LENGTH = 32K 9 | itcm (rxai!w) : ORIGIN = itcm + 0x10000, LENGTH = 32K 10 | dtcm (wxa!ri) : ORIGIN = dtcm + 0x01000, LENGTH = 4K 11 | } 12 | 13 | __end_stack = _sp; 14 | SECTIONS { 15 | __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; 16 | /* Put startup code into FLASH, ALWAYS DO THIS FIRST */ 17 | 18 | 19 | /* Put program code and other data into FLASH */ 20 | .text : { 21 | . = ALIGN(4); 22 | __text_start = .; 23 | 24 | KEEP(*(.text.isr_vector)); 25 | *(.text) 26 | *(.text*) 27 | *(.glue_7) 28 | *(.glue_7t) 29 | *(.eh_frame) 30 | 31 | KEEP(*(.init)) 32 | KEEP(*(.fini)) 33 | 34 | . = ALIGN(4); 35 | __text_end = .; 36 | } > itcm AT>flash 37 | 38 | /* Put constant (read-only) data into FLASH */ 39 | .rodata : { 40 | . = ALIGN(4); 41 | __rodata_start = .; 42 | 43 | *(.rodata) 44 | *(.rodata*) 45 | 46 | . = ALIGN(4); 47 | __rodata_end = .; 48 | } > itcm AT>flash 49 | 50 | .ARM.extab : { 51 | *(.ARM.extab* .gnu.linkonce.armextab.*) 52 | } > itcm AT>flash 53 | 54 | .ARM : { 55 | __exidx_start = .; 56 | *(.ARM.exidx*) 57 | __exidx_end = .; 58 | } > itcm AT>flash 59 | 60 | .preinit_array : { 61 | PROVIDE_HIDDEN(__preinit_array_start = .); 62 | KEEP(*(.preinit_array*)) 63 | PROVIDE_HIDDEN(__preinit_array_end = .); 64 | } > itcm AT>flash 65 | .init_array : { 66 | PROVIDE_HIDDEN(__init_array_start = .); 67 | KEEP(*(.init_array*)) 68 | PROVIDE_HIDDEN(__init_array_end = .); 69 | } > itcm AT>flash 70 | .fini_array : { 71 | PROVIDE_HIDDEN(__fini_array_start = .); 72 | KEEP(*(.fini_array*)) 73 | PROVIDE_HIDDEN(__fini_array_end = .); 74 | } > itcm AT>flash 75 | 76 | .lalign : { 77 | PROVIDE( __data_vma_start = . ); 78 | } > itcm AT>flash 79 | 80 | .data : { 81 | . = ALIGN(4); 82 | __data_start = .; 83 | 84 | *(.data) 85 | *(.data*) 86 | 87 | . = ALIGN(4); 88 | __data_end = .; 89 | } > dtcm AT>flash 90 | 91 | .bss : { 92 | . = ALIGN(4); 93 | __bss_start = .; 94 | __bss_start__ = __bss_start; 95 | 96 | *(.bss) 97 | *(.bss*) 98 | *(COMMON) 99 | 100 | . = ALIGN(4); 101 | __bss_end = .; 102 | __bss_end__ = __bss_end; 103 | } > dtcm AT>dtcm 104 | 105 | . = ALIGN(4); 106 | PROVIDE( _end = . ); 107 | PROVIDE( end = . ); 108 | 109 | . = ALIGN(4); 110 | PROVIDE( _end = . ); 111 | PROVIDE( end = . ); 112 | 113 | .stack ORIGIN(dtcm) + LENGTH(dtcm) - __stack_size : { 114 | PROVIDE( _heap_end = . ); 115 | . = __stack_size; 116 | PROVIDE( _sp = . ); 117 | } >dtcm AT>dtcm 118 | 119 | /DISCARD/ : { 120 | libc.a(*) 121 | libm.a(*) 122 | libgcc.a(*) 123 | } 124 | 125 | .ARM.attributes 0 : { 126 | *(.ARM.attributes) 127 | } 128 | } 129 | 130 | -------------------------------------------------------------------------------- /zone2/main.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2019 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include // strcmp() 4 | #include // uint16_t, ... 5 | 6 | #include "platform.h" 7 | #include "multizone.h" 8 | #include "gpio_driver.h" 9 | 10 | // ------------------------------------------------------------------------ 11 | void systick_handler(void) __attribute__ ((interrupt ("irq"))); 12 | void systick_handler(void){ 13 | // ------------------------------------------------------------------------ 14 | /* Set soft-timer */ 15 | const uint64_t T0 = MZONE_RDTIME(); 16 | const uint64_t T1 = T0 + (RTC_FREQ*(500/1000.0)); // 500 ms 17 | MZONE_WRTIMECMP(T1); 18 | 19 | if (LED_OUT(LED)) 20 | { 21 | LED_CLR(LED); 22 | } 23 | else 24 | { 25 | LED_SET(LED); 26 | } 27 | 28 | } 29 | 30 | // ------------------------------------------------------------------------ 31 | void btn_handler(void) __attribute__ ((interrupt ("irq"))); 32 | void btn_handler(void){ 33 | // ------------------------------------------------------------------------ 34 | BTN_IRQ_CLR(); /* Clear pending */ 35 | 36 | char msg[16] = "NVIC IRQ [BTN1]"; 37 | MZONE_SEND(1, msg); 38 | 39 | LED_SET(LED); 40 | 41 | /* Set soft-timer */ 42 | const uint64_t T0 = MZONE_RDTIME(); 43 | const uint64_t T1 = T0 + (RTC_FREQ*(3000/1000.0)); // 3000 ms 44 | MZONE_WRTIMECMP(T1); 45 | } 46 | 47 | // ------------------------------------------------------------------------ 48 | static void button_init (void) { 49 | // ------------------------------------------------------------------------ 50 | BTN_INIT(BTN_PIN); 51 | STORE_NVICISER(BTN_IRQn); /* Enable interrupt on NVIC */ 52 | } 53 | 54 | // ------------------------------------------------------------------------ 55 | static void led_init (void) { 56 | // ------------------------------------------------------------------------ 57 | LED_INIT(LED); 58 | } 59 | 60 | // ------------------------------------------------------------------------ 61 | int main (void) { 62 | // ------------------------------------------------------------------------ 63 | 64 | //volatile int w=0; while(1){w++;} 65 | //while(1) MZONE_YIELD(); 66 | //while(1) MZONE_WFI(); 67 | 68 | int i = 0; 69 | led_init(); 70 | button_init(); 71 | 72 | /* Set soft-timer */ 73 | const uint64_t T0 = MZONE_RDTIME(); 74 | const uint64_t T1 = T0 + (RTC_FREQ*(500/1000.0)); // 500 ms 75 | MZONE_WRTIMECMP(T1); 76 | 77 | 78 | 79 | while(1){ 80 | 81 | // Message handler 82 | char msg[16]; if (MZONE_RECV(1, msg)) { 83 | if (strcmp("ping", msg)==0) MZONE_SEND(1, "pong"); 84 | else if (strcmp("irq=0", msg)==0) __disable_irq(); 85 | else if (strcmp("irq=1", msg)==0) __enable_irq(); 86 | else if (strcmp("block", msg)==0) {volatile int i=0; while(1) i++; } 87 | else if (strcmp("loop", msg)==0) {while(1) MZONE_YIELD();} 88 | } 89 | 90 | // Wait For Interrupt 91 | MZONE_WFI(); 92 | 93 | } 94 | 95 | 96 | return 0; 97 | } 98 | -------------------------------------------------------------------------------- /zone3/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved 2 | 3 | TARGET = zone3.elf 4 | 5 | BSP_BASE := ../bsp 6 | PLATFORM_DIR := $(BSP_BASE)/$(BOARD) 7 | NEWLIB_DIR := $(PLATFORM_DIR)/newlib 8 | 9 | LINKER_SCRIPT := linker.ld 10 | 11 | C_SRCS += main.c owi_sequence.c 12 | 13 | INCLUDES += -I../ 14 | LDFLAGS += -L../ 15 | 16 | include $(NEWLIB_DIR)/newlib.mk 17 | 18 | -------------------------------------------------------------------------------- /zone3/linker.ld: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 4 | 5 | ENTRY( reset_handler ) 6 | 7 | MEMORY { 8 | flash (rxai!w) : ORIGIN = flash + 0x18000, LENGTH = 32K 9 | itcm (rxai!w) : ORIGIN = itcm + 0x18000, LENGTH = 32K 10 | dtcm (wxa!ri) : ORIGIN = dtcm + 0x02000, LENGTH = 4K 11 | } 12 | 13 | __end_stack = _sp; 14 | SECTIONS { 15 | __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; 16 | /* Put startup code into FLASH, ALWAYS DO THIS FIRST */ 17 | 18 | 19 | /* Put program code and other data into FLASH */ 20 | .text : { 21 | . = ALIGN(4); 22 | __text_start = .; 23 | 24 | KEEP(*(.text.isr_vector)); 25 | *(.text) 26 | *(.text*) 27 | *(.glue_7) 28 | *(.glue_7t) 29 | *(.eh_frame) 30 | 31 | KEEP(*(.init)) 32 | KEEP(*(.fini)) 33 | 34 | . = ALIGN(4); 35 | __text_end = .; 36 | } > itcm AT>flash 37 | 38 | /* Put constant (read-only) data into FLASH */ 39 | .rodata : { 40 | . = ALIGN(4); 41 | __rodata_start = .; 42 | 43 | *(.rodata) 44 | *(.rodata*) 45 | 46 | . = ALIGN(4); 47 | __rodata_end = .; 48 | } > itcm AT>flash 49 | 50 | .ARM.extab : { 51 | *(.ARM.extab* .gnu.linkonce.armextab.*) 52 | } > itcm AT>flash 53 | 54 | .ARM : { 55 | __exidx_start = .; 56 | *(.ARM.exidx*) 57 | __exidx_end = .; 58 | } > itcm AT>flash 59 | 60 | .preinit_array : { 61 | PROVIDE_HIDDEN(__preinit_array_start = .); 62 | KEEP(*(.preinit_array*)) 63 | PROVIDE_HIDDEN(__preinit_array_end = .); 64 | } > itcm AT>flash 65 | .init_array : { 66 | PROVIDE_HIDDEN(__init_array_start = .); 67 | KEEP(*(.init_array*)) 68 | PROVIDE_HIDDEN(__init_array_end = .); 69 | } > itcm AT>flash 70 | .fini_array : { 71 | PROVIDE_HIDDEN(__fini_array_start = .); 72 | KEEP(*(.fini_array*)) 73 | PROVIDE_HIDDEN(__fini_array_end = .); 74 | } > itcm AT>flash 75 | 76 | .lalign : { 77 | PROVIDE( __data_vma_start = . ); 78 | } > itcm AT>flash 79 | 80 | .data : { 81 | . = ALIGN(4); 82 | __data_start = .; 83 | 84 | *(.data) 85 | *(.data*) 86 | 87 | . = ALIGN(4); 88 | __data_end = .; 89 | } > dtcm AT>flash 90 | 91 | .bss : { 92 | . = ALIGN(4); 93 | __bss_start = .; 94 | __bss_start__ = __bss_start; 95 | 96 | *(.bss) 97 | *(.bss*) 98 | *(COMMON) 99 | 100 | . = ALIGN(4); 101 | __bss_end = .; 102 | __bss_end__ = __bss_end; 103 | } > dtcm AT>dtcm 104 | 105 | . = ALIGN(4); 106 | PROVIDE( _end = . ); 107 | PROVIDE( end = . ); 108 | 109 | . = ALIGN(4); 110 | PROVIDE( _end = . ); 111 | PROVIDE( end = . ); 112 | 113 | .stack ORIGIN(dtcm) + LENGTH(dtcm) - __stack_size : { 114 | PROVIDE( _heap_end = . ); 115 | . = __stack_size; 116 | PROVIDE( _sp = . ); 117 | } >dtcm AT>dtcm 118 | 119 | /DISCARD/ : { 120 | libc.a(*) 121 | libm.a(*) 122 | libgcc.a(*) 123 | } 124 | 125 | .ARM.attributes 0 : { 126 | *(.ARM.attributes) 127 | } 128 | } 129 | -------------------------------------------------------------------------------- /zone3/main.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include // strcmp() 4 | 5 | #include "platform.h" 6 | #include "multizone.h" 7 | #include "owi_sequence.h" 8 | #include "gpio_driver.h" 9 | 10 | #define MAN_CMD_TIME 250*(RTC_FREQ/1000) // 250ms 11 | #define KEEP_ALIVE_TIME 1*RTC_FREQ // 1 sec 12 | #define LED_TIME 20*(RTC_FREQ/1000) // 20ms 13 | 14 | void timer_handler(const uint64_t time); 15 | 16 | void systick_handler(void) __attribute__ ((interrupt ("irq"))); 17 | void systick_handler(void){ 18 | 19 | const uint64_t time = MZONE_RDTIME(); 20 | timer_handler(time); 21 | 22 | } 23 | 24 | static uint8_t CRC8(const uint8_t const bytes[]){ 25 | 26 | const uint8_t generator = 0x1D; 27 | uint8_t crc = 0; 28 | 29 | for(int b=0; b<3; b++) { 30 | 31 | crc ^= bytes[b]; /* XOR-in the next input byte */ 32 | 33 | for (int i = 0; i < 8; i++) 34 | if ((crc & 0x80) != 0) 35 | crc = (uint8_t)((crc << 1) ^ generator); 36 | else 37 | crc <<= 1; 38 | } 39 | 40 | return crc; 41 | } 42 | 43 | static uint32_t spi_rw(const uint32_t cmd){ 44 | 45 | 46 | const uint8_t const bytes[] = {(uint8_t)cmd, (uint8_t)(cmd>>8), (uint8_t)(cmd>>16)}; 47 | const uint32_t tx_data = bytes[0]<<24 | bytes[1]<<16 | bytes[2]<<8 | CRC8(bytes); 48 | 49 | uint32_t rx_data = 0; 50 | 51 | for (int i=32-1, bit; i>=0; i--){ 52 | 53 | bit = (tx_data >> i) & 1U; 54 | 55 | if(bit){ 56 | SPI_TDO_SET(SPI_TDO); 57 | } 58 | else{ 59 | SPI_TDO_CLR(SPI_TDO); 60 | } 61 | 62 | SPI_TCK_LOW(SPI_TCK); volatile int w1=0; while(w1<5) w1++; 63 | SPI_TCK_HIGH(SPI_TCK); volatile int w2=0; while(w2<5) w2++; 64 | bit = SPI_TDI_BIT(SPI_TDI); 65 | rx_data = ( bit==1 ? rx_data | (0x1 << i) : rx_data & ~(0x1 << i) ); 66 | 67 | } 68 | 69 | return rx_data; 70 | } 71 | 72 | #define CMD_DUMMY 0xFFFFFF 73 | #define CMD_STOP 0x000000 74 | 75 | static volatile uint32_t usb_state = 0; 76 | static volatile uint32_t man_cmd = CMD_STOP; 77 | 78 | uint64_t task0(); // OWI Sequence 79 | uint64_t task1(); // Manual cmd stop 80 | uint64_t task2(); // Keep alive 81 | uint64_t task3(); // LED off 82 | 83 | static struct { 84 | uint64_t (*task)(void); 85 | uint64_t timecmp; 86 | } timer[] = {{&task0, UINT64_MAX}, {&task1, UINT64_MAX}, {&task2, UINT64_MAX}, {&task3, UINT64_MAX}}; 87 | 88 | void timer_set(const int i, const uint64_t timecmp){ 89 | 90 | timer[i].timecmp = timecmp; 91 | 92 | uint64_t timecmp_min = UINT64_MAX; 93 | for (int i=0; i= timer[i].timecmp){ 104 | timer_set(i, timer[i].task()); 105 | break; 106 | } 107 | } 108 | 109 | uint64_t task0(){ // OWI sequence 110 | 111 | uint64_t timecmp = UINT64_MAX; 112 | 113 | if (usb_state==0x12670000){ 114 | 115 | if (owi_sequence_next()!=-1){ 116 | spi_rw(owi_sequence_get_cmd()); 117 | timecmp = MZONE_RDTIME() + owi_sequence_get_ms()*RTC_FREQ/1000; 118 | } 119 | 120 | } 121 | 122 | return timecmp; 123 | 124 | } 125 | 126 | uint64_t task1(){ // Manual cmd stop 127 | spi_rw(man_cmd = CMD_STOP); 128 | return UINT64_MAX; 129 | } 130 | 131 | uint64_t task2(){ // Keep alive 1sec 132 | 133 | const uint64_t time = MZONE_RDTIME(); 134 | 135 | // Send keep alive packet and check ret value 136 | const uint32_t rx_data = spi_rw(CMD_DUMMY); 137 | 138 | // Update USB state (0xFFFFFFFF no spi/usb adapter) 139 | if (rx_data != usb_state){ 140 | if (rx_data==0x12670000 && usb_state==0x0){ 141 | MZONE_SEND(1, "USB ID 0x12670000"); 142 | } else if (rx_data==0x0 && usb_state==0x12670000){ 143 | MZONE_SEND(1, "USB DISCONNECT"); 144 | owi_sequence_stop(); 145 | } 146 | usb_state=rx_data; 147 | } 148 | 149 | // Turn on LED & start LED timer 150 | //GPIO_REG(GPIO_OUTPUT_VAL) |= LED; 151 | timer_set(3, time + LED_TIME); 152 | 153 | return time + KEEP_ALIVE_TIME; 154 | } 155 | 156 | uint64_t task3(){ // LED off 157 | //GPIO_REG(GPIO_OUTPUT_VAL) &= ~LED; 158 | return UINT64_MAX; 159 | } 160 | 161 | void msg_handler(const char *msg){ 162 | 163 | if (strcmp("ping", msg)==0){ 164 | MZONE_SEND(1, "pong"); 165 | 166 | } else if (usb_state==0x12670000 && man_cmd==CMD_STOP){ 167 | 168 | if (strcmp("stop", msg)==0) owi_sequence_stop_req(); 169 | 170 | else if (!owi_sequence_is_running()){ 171 | 172 | if (strcmp("start", msg)==0) {owi_sequence_start(MAIN); timer_set(0, 0);} 173 | else if (strcmp("fold", msg)==0) {owi_sequence_start(FOLD); timer_set(0, 0);} 174 | else if (strcmp("unfold",msg)==0) {owi_sequence_start(UNFOLD); timer_set(0, 0);} 175 | 176 | // Manual single-command adjustments 177 | if (strcmp("q", msg)==0) man_cmd = 0x000001; // grip close 178 | else if (strcmp("a", msg)==0) man_cmd = 0x000002; // grip open 179 | else if (strcmp("w", msg)==0) man_cmd = 0x000004; // wrist up 180 | else if (strcmp("s", msg)==0) man_cmd = 0x000008; // wrist down 181 | else if (strcmp("e", msg)==0) man_cmd = 0x000010; // elbow up 182 | else if (strcmp("d", msg)==0) man_cmd = 0x000020; // elbow down 183 | else if (strcmp("r", msg)==0) man_cmd = 0x000040; // shoulder up 184 | else if (strcmp("f", msg)==0) man_cmd = 0x000080; // shoulder down 185 | else if (strcmp("t", msg)==0) man_cmd = 0x000100; // base clockwise 186 | else if (strcmp("g", msg)==0) man_cmd = 0x000200; // base counterclockwise 187 | else if (strcmp("y", msg)==0) man_cmd = 0x010000; // light on 188 | 189 | if (man_cmd != CMD_STOP){ 190 | spi_rw(man_cmd); 191 | timer_set(1, MZONE_RDTIME() + MAN_CMD_TIME); 192 | } 193 | 194 | } 195 | 196 | } 197 | 198 | } 199 | 200 | int main(void) 201 | { 202 | 203 | //volatile int w=0; while(1){w++;} 204 | //while(1) MZONE_YIELD(); 205 | //while(1) MZONE_WFI(); 206 | 207 | SPI_INIT(SPI_TDI, SPI_TCK, SPI_TDO); 208 | 209 | // Start task2: Hartbeat LED, USB status, Keep alive pkt 210 | timer_set(2, 0); 211 | 212 | while(1){ 213 | 214 | // Message handler 215 | char msg[16]; if (MZONE_RECV(1, msg)) msg_handler(msg); 216 | 217 | MZONE_WFI(); 218 | 219 | } 220 | } 221 | -------------------------------------------------------------------------------- /zone3/owi_sequence.c: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #include // NULL 4 | #include "owi_sequence.h" 5 | 6 | typedef enum{ 7 | STOP = 0x000000, 8 | GRIP_CLOSE = 0x000001, 9 | GRIP_OPEN = 0x000002, 10 | WRIST_UP = 0x000004, 11 | WRIST_DOWN = 0x000008, 12 | ELBOW_UP = 0x000010, 13 | ELBOW_DOWN = 0x000020, 14 | SHOULDER_UP = 0x000040, 15 | SHOULDER_DOWN = 0x000080, 16 | BASE_CLOCKWISE = 0x000100, 17 | BASE_COUNTERCLOCK = 0x000200, 18 | LIGHT_ON = 0x010000, 19 | ARM_UP = 0x000008 | 0x000010 | 0x000040, // wrist down + elbow up + shoulder up 20 | ARM_DOWN = 0x000004 | 0x000020 | 0x000080 | 0x000100, // wrist up + elbow down + shoulder down + base clockwise 21 | } cmd; 22 | 23 | struct sequence_step{ 24 | uint32_t command; 25 | int duration_ms; 26 | }; 27 | 28 | // R4 09-MAR-2019 29 | #define T_STOP 1000 30 | #define T_GRIP 1400 31 | #define T_WRIST 2600 32 | #define T_ARM 1800 33 | #define T_BASE 3000 34 | static struct sequence_step main_sequence[] = { 35 | { .command = STOP, .duration_ms = T_STOP }, 36 | { .command = GRIP_CLOSE, .duration_ms = T_GRIP }, 37 | { .command = WRIST_UP, .duration_ms = T_WRIST}, 38 | { .command = ARM_DOWN, .duration_ms = T_ARM }, 39 | { .command = BASE_CLOCKWISE, .duration_ms = T_BASE }, 40 | { .command = GRIP_OPEN, .duration_ms = T_GRIP }, 41 | { .command = STOP, .duration_ms = T_STOP }, 42 | { .command = GRIP_CLOSE, .duration_ms = T_GRIP }, 43 | { .command = BASE_COUNTERCLOCK, .duration_ms = T_BASE+T_ARM-250}, 44 | { .command = ARM_UP, .duration_ms = T_ARM }, 45 | { .command = SHOULDER_UP, .duration_ms = +175 }, 46 | { .command = ELBOW_UP, .duration_ms = +100 }, 47 | { .command = WRIST_DOWN, .duration_ms = T_WRIST-250}, 48 | { .command = GRIP_OPEN, .duration_ms = T_GRIP}, 49 | }; 50 | 51 | #define T_FOLD 4500 52 | #define T_FOLD_SHOULDER 800 53 | static struct sequence_step fold_sequence[] = { 54 | { .command = STOP, .duration_ms = 0}, 55 | { .command = GRIP_OPEN, .duration_ms = 100}, 56 | { .command = ELBOW_DOWN | SHOULDER_UP | WRIST_DOWN, .duration_ms = T_FOLD}, 57 | { .command = ELBOW_DOWN, .duration_ms = 200}, 58 | { .command = SHOULDER_UP, .duration_ms = T_FOLD_SHOULDER}, 59 | }; 60 | static struct sequence_step unfold_sequence[] = { 61 | { .command = STOP, .duration_ms = 0}, 62 | { .command = ELBOW_UP, .duration_ms = 200}, 63 | { .command = SHOULDER_DOWN, .duration_ms = T_FOLD_SHOULDER + 50}, 64 | { .command = ELBOW_UP | SHOULDER_DOWN | WRIST_UP, .duration_ms = T_FOLD}, 65 | }; 66 | 67 | static struct sequence_step *sequence = NULL; 68 | static int stepIdx = 0; 69 | static int size = 0; 70 | static int stop = 1; 71 | 72 | void owi_sequence_start(owi_sequence seq){ 73 | 74 | if (sequence==NULL){ 75 | 76 | switch(seq){ 77 | 78 | case MAIN: 79 | sequence = main_sequence; 80 | size = sizeof(main_sequence) / sizeof(main_sequence[0]); 81 | stepIdx = 0; 82 | stop = 0; 83 | break; 84 | 85 | case FOLD: 86 | sequence = fold_sequence; 87 | size = sizeof(fold_sequence) / sizeof(fold_sequence[0]); 88 | stepIdx = 0; 89 | stop = 0; 90 | break; 91 | 92 | case UNFOLD: 93 | sequence = unfold_sequence; 94 | size = sizeof(unfold_sequence) / sizeof(unfold_sequence[0]); 95 | stepIdx = 0; 96 | stop = 0; 97 | break; 98 | 99 | } 100 | 101 | } 102 | 103 | }; 104 | 105 | void owi_sequence_stop_req(){stop=1;} 106 | 107 | void owi_sequence_stop(){ 108 | sequence = NULL; 109 | stepIdx = 0; 110 | size = 0; 111 | stop = 1; 112 | } 113 | 114 | int owi_sequence_next(){ 115 | 116 | if (stop && stepIdx==0) sequence=NULL; 117 | 118 | if (sequence==NULL) return -1; 119 | 120 | stepIdx = (stepIdx+1) % size; 121 | 122 | // Auto stop FOLD/UNFOLD 123 | if (sequence[stepIdx].duration_ms==0) stop=1; 124 | 125 | return stepIdx; 126 | }; 127 | 128 | int32_t owi_sequence_get_cmd(){ 129 | 130 | if (sequence==NULL) return 0; 131 | 132 | const int32_t cmd = sequence[stepIdx].command; 133 | 134 | return stop ? cmd & ~(1UL<<16) : cmd | (1UL<<16); 135 | 136 | } 137 | int owi_sequence_get_ms(){ 138 | 139 | if (sequence==NULL) return 0; 140 | 141 | return sequence[stepIdx].duration_ms; 142 | } 143 | 144 | int owi_sequence_is_running(){ 145 | 146 | return sequence!=NULL; 147 | 148 | }; 149 | -------------------------------------------------------------------------------- /zone3/owi_sequence.h: -------------------------------------------------------------------------------- 1 | /* Copyright(C) 2018 Hex Five Security, Inc. - All Rights Reserved */ 2 | 3 | #ifndef OWI_SEQUENCE_H_ 4 | #define OWI_SEQUENCE_H_ 5 | 6 | #include 7 | 8 | typedef enum{ 9 | MAIN, 10 | FOLD, 11 | UNFOLD, 12 | } owi_sequence; 13 | 14 | void owi_sequence_start(owi_sequence); 15 | void owi_sequence_stop(); 16 | void owi_sequence_stop_req(); 17 | int owi_sequence_next(); 18 | 19 | int32_t owi_sequence_get_cmd(); 20 | int owi_sequence_get_ms(); 21 | 22 | int owi_sequence_is_running(); 23 | 24 | #endif 25 | --------------------------------------------------------------------------------