├── Lib ├── gscl45nm.db └── gscl45nm.v ├── Matlab ├── FFT64Point.m └── FFT8Point.m ├── Proposal └── Project_Proposal.pdf ├── README.md ├── Reference └── maharatna2004.pdf ├── Report ├── EE382M_VLSI_I │ └── EE382M_VLSI_I_Project_Report.pdf ├── EE382M_Verification_for_Digital_System │ └── EE382M_Verification_Project_Report.pdf ├── ET4067_VLSI_for_Digital_Communication_System │ └── ET4067_Project_Report_Bagus_Hanindhito (ID).pdf └── Sigma Expansion.xlsx ├── Synthesis ├── fft_64p_16b_top.gatelevel.v ├── fft_64p_16b_top.sdc └── fft_64p_16b_top_implementation.v ├── VHDL ├── adder_cla_16b.vhd ├── adder_cla_1b.vhd ├── adder_cla_32b.vhd ├── basic_dff_32b.vhd ├── bit_adj_32b_to_16b.vhd ├── bypass_32b.vhd ├── cb_circuit.vhd ├── complex_adder_cla_32b.vhd ├── complex_mult_twiddle_wn0_32b.vhd ├── complex_mult_twiddle_wn1_32b.vhd ├── complex_mult_twiddle_wn2_32b.vhd ├── complex_mult_twiddle_wn3_32b.vhd ├── complex_subst_cla_32b.vhd ├── const_mult_cla_16b_halfsqrtof2.vhd ├── const_mult_cla_16b_sqrtof2.vhd ├── dff_segment_for_cb.vhd ├── dff_segment_for_input.vhd ├── dff_segment_for_output.vhd ├── dff_with_hold_32b.vhd ├── dff_with_hold_input_ctrl.vhd ├── fft_64p_16b_top.vhd ├── fft_64p_16b_top_testbench.vhd ├── fft_8p_16b_top.vhd ├── generic_complex_mult_16b.vhd ├── generic_complex_mult_block.vhd ├── generic_mult_16b.vhd ├── input_circuit.vhd ├── input_counter.vhd ├── interdimensional_multiplier.vhd ├── lshift_0_16b_to_32b.vhd ├── lshift_10_16b_to_32b.vhd ├── lshift_11_16b_to_32b.vhd ├── lshift_12_16b_to_32b.vhd ├── lshift_13_16b_to_32b.vhd ├── lshift_14_16b_to_32b.vhd ├── lshift_15_16b_to_32b.vhd ├── lshift_1_16b_to_32b.vhd ├── lshift_2_16b_to_32b.vhd ├── lshift_3_16b_to_32b.vhd ├── lshift_4_16b_to_32b.vhd ├── lshift_5_16b_to_32b.vhd ├── lshift_6_16b_to_32b.vhd ├── lshift_7_16b_to_32b.vhd ├── lshift_8_16b_to_32b.vhd ├── lshift_9_16b_to_32b.vhd ├── master_control.vhd ├── mux_2to1_16b.vhd ├── mux_2to1_32b.vhd ├── mux_8to1_32b.vhd ├── notgate_16b.vhd ├── output_circuit.vhd ├── output_counter.vhd ├── real_imaginary_interchange.vhd ├── rshift_6_16b_to_16b.vhd ├── scalling_out.vhd ├── sgninv_16b.vhd ├── sgninv_1b.vhd └── subst_cla_16b.vhd ├── Verification ├── Formal │ ├── master_control.tcl │ └── v_master_control.sv ├── LEC │ ├── Mapping manager(netlist_implementation).JPG │ ├── Mapping manager(rtl_netlist).JPG │ ├── logging(netlist_implementation).txt │ ├── logging(rtl_netlist).txt │ ├── netlist_implementation.do │ ├── rtl.list │ ├── rtl_netlist.do │ ├── summary(netlist_implementation).JPG │ └── summary(rtl_netlist).JPG └── UVM │ ├── sim │ ├── Makefile │ ├── README │ ├── freqseries.hex │ ├── run.do │ └── timeseries.hex │ └── tb │ ├── coverage.sv │ ├── dummy.sv │ ├── interfaces.sv │ ├── modules.sv │ ├── scoreboard.sv │ ├── sequences.sv │ ├── tb.sv │ └── tests.sv └── Verilog ├── bit_adj_32b_to_16b.v ├── black_cell.v ├── bypass_32b.v ├── cb_circuit.v ├── complex_adder_ksa_32b.v ├── complex_mult_twiddle_wn0_32b.v ├── complex_mult_twiddle_wn1_32b.v ├── complex_mult_twiddle_wn2_32b.v ├── complex_mult_twiddle_wn3_32b.v ├── complex_subst_ksa_32b.v ├── const_mult_ksa_16b_halfsqrt2.v ├── const_mult_ksa_16b_sqrt2.v ├── dff_hold_sync_high_reset.v ├── dff_inputsel_hold_sync_high_reset.v ├── dff_segment_for_cb.v ├── dff_segment_for_input.v ├── dff_segment_for_output.v ├── dff_sync_high_reset.v ├── fft_64p_16b_top.v ├── fft_64p_16b_top_testbench.v ├── fft_8p_16b_top.v ├── freqseries.hex ├── generic_complex_mult_16b.v ├── generic_complex_mult_block.v ├── generic_mult_16b.v ├── grey_cell.v ├── input_circuit.v ├── input_counter.v ├── interdimensional_multiplier.v ├── intermediate_circuit.v ├── ks_1_16b.v ├── ks_1_32b.v ├── ks_2_16b.v ├── ks_2_32b.v ├── ks_3_16b.v ├── ks_3_32b.v ├── ks_4_16b.v ├── ks_4_32b.v ├── ks_5_16b.v ├── ks_5_32b.v ├── ks_6_16b.v ├── ks_6_32b.v ├── ks_7_16b.v ├── ks_7_32b.v ├── ksa_top_16b.v ├── ksa_top_32b.v ├── lib1 ├── lshifter.v ├── master ├── master_control.v ├── mux_2_to_1.v ├── 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