├── README.md ├── fpv.tcl ├── rtl ├── aes │ ├── addroundkey.vhd │ ├── aes_core.vhd │ ├── aes_fsm_decrypt.vhd │ ├── aes_fsm_encrypt.vhd │ ├── avs_aes.vhd │ ├── avs_aes_pkg.vhd │ ├── keyexpansionV2.vhd │ ├── memory_word.vhd │ ├── mixcol.vhd │ ├── mixcol_fwd.vhd │ ├── mixcol_inv.vhd │ ├── mux2.vhd │ ├── mux3.vhd │ ├── sbox.hex │ ├── sbox.vhd │ ├── sboxM4k.vhd │ ├── sbox_arch1.vhd │ ├── sbox_inv.hex │ ├── shiftrow.vhd │ ├── shiftrow_fwd.vhd │ └── shiftrow_inv.vhd ├── amber │ ├── README.txt │ ├── amber23 │ │ ├── a23_alu.v │ │ ├── a23_barrel_shift.v │ │ ├── a23_barrel_shift_fpga.v │ │ ├── a23_cache.v │ │ ├── a23_config_defines.vh │ │ ├── a23_coprocessor.v │ │ ├── a23_core.v │ │ ├── a23_decode.v │ │ ├── a23_decompile.v │ │ ├── a23_execute.v │ │ ├── a23_fetch.v │ │ ├── a23_functions.vh │ │ ├── a23_localparams.vh │ │ ├── a23_multiply.v │ │ ├── a23_ram_register_bank.v │ │ ├── a23_register_bank.v │ │ ├── a23_wishbone.v │ │ └── makefile.inc │ ├── amber25 │ │ ├── a25_alu.v │ │ ├── a25_barrel_shift.v │ │ ├── a25_config_defines.vh │ │ ├── a25_coprocessor.v │ │ ├── a25_core.v │ │ ├── a25_dcache.v │ │ ├── a25_decode.v │ │ ├── a25_decompile.v │ │ ├── a25_execute.v │ │ ├── a25_fetch.v │ │ ├── a25_functions.vh │ │ ├── a25_icache.v │ │ ├── a25_localparams.vh │ │ ├── a25_mem.v │ │ ├── a25_multiply.v │ │ ├── a25_register_bank.v │ │ ├── a25_shifter.v │ │ ├── a25_wishbone.v │ │ ├── a25_wishbone_buf.v │ │ ├── a25_write_back.v │ │ └── makefile.inc │ ├── ethmac │ │ ├── eth_clockgen.v │ │ ├── eth_cop.v │ │ ├── eth_crc.v │ │ ├── eth_defines.v │ │ ├── eth_fifo.v │ │ ├── eth_maccontrol.v │ │ ├── eth_macstatus.v │ │ ├── eth_miim.v │ │ ├── eth_outputcontrol.v │ │ ├── eth_random.v │ │ ├── eth_receivecontrol.v │ │ ├── eth_register.v │ │ ├── eth_registers.v │ │ ├── eth_rxaddrcheck.v │ │ ├── eth_rxcounters.v │ │ ├── eth_rxethmac.v │ │ ├── eth_rxstatem.v │ │ ├── eth_shiftreg.v │ │ ├── eth_spram_256x32.v │ │ ├── eth_top.v │ │ ├── eth_transmitcontrol.v │ │ ├── eth_txcounters.v │ │ ├── eth_txethmac.v │ │ ├── eth_txstatem.v │ │ ├── eth_wishbone.v │ │ ├── makefile.inc │ │ ├── timescale.v │ │ └── xilinx_dist_ram_16x32.v │ ├── lib │ │ ├── generic_iobuf.v │ │ ├── generic_sram_byte_en.v │ │ ├── generic_sram_line_en.v │ │ ├── xs6_addsub_n.v │ │ ├── xs6_sram_1024x128_byte_en.v │ │ ├── xs6_sram_2048x32_byte_en.v │ │ ├── xs6_sram_256x128_byte_en.v │ │ ├── xs6_sram_256x21_line_en.v │ │ ├── xs6_sram_256x32_byte_en.v │ │ ├── xs6_sram_4096x32_byte_en.v │ │ └── xs6_sram_512x128_byte_en.v │ ├── system │ │ ├── afifo.v │ │ ├── boot_mem128.v │ │ ├── boot_mem32.v │ │ ├── clocks_resets.v │ │ ├── ddr3_afifo.v │ │ ├── ethmac_wb.v │ │ ├── interrupt_controller.v │ │ ├── main_mem.v │ │ ├── makefile.inc │ │ ├── memory_configuration.vh │ │ ├── register_addresses.vh │ │ ├── system.v │ │ ├── system_config_defines.vh │ │ ├── system_functions.vh │ │ ├── test_module.v │ │ ├── timer_module.v │ │ ├── uart.v │ │ ├── wb_ddr3_bridge.v │ │ ├── wb_xs6_ddr3_bridge.v │ │ └── wishbone_arbiter.v │ ├── tb │ │ ├── debug_functions.vh │ │ ├── dumpvcd.v │ │ ├── eth_test.v │ │ ├── global_defines.vh │ │ ├── global_timescale.vh │ │ ├── tb.v │ │ └── tb_uart.v │ └── xs6_ddr3 │ │ ├── README.txt │ │ ├── coregen_sp605.cgp │ │ ├── datasheet.txt │ │ ├── ddr3.xco │ │ └── ddr3 │ │ └── user_design │ │ └── mig.prj ├── ecg │ ├── COPYING.LESSER.txt │ ├── ecg.v │ ├── f3.v │ ├── f3m.v │ ├── fun.v │ └── inc.v ├── ethernet │ ├── .DS_Store │ ├── eth_clockgen.v │ ├── eth_cop.v │ ├── eth_crc.v │ ├── eth_fifo.v │ ├── eth_maccontrol.v │ ├── eth_macstatus.v │ ├── eth_miim.v │ ├── eth_outputcontrol.v │ ├── eth_random.v │ ├── eth_receivecontrol.v │ ├── eth_register.v │ ├── eth_registers.v │ ├── eth_rxaddrcheck.v │ ├── eth_rxcounters.v │ ├── eth_rxethmac.v │ ├── eth_rxstatem.v │ ├── eth_shiftreg.v │ ├── eth_spram_256x32.v │ ├── eth_top.v │ ├── eth_transmitcontrol.v │ ├── eth_txcounters.v │ ├── eth_txethmac.v │ ├── eth_txstatem.v │ ├── eth_wishbone.v │ ├── ethmac.v │ ├── ethmac_defines.v │ ├── timescale.v │ └── xilinx_dist_ram_16x32.v ├── hpdmc │ ├── hpdmc.v │ ├── hpdmc_banktimer.v │ ├── hpdmc_busif.v │ ├── hpdmc_ctlif.v │ ├── hpdmc_datactl.v │ ├── hpdmc_mgmt.v │ └── spartan6 │ │ ├── hpdmc_ddrio.v │ │ ├── hpdmc_iddr32.v │ │ ├── hpdmc_iobuf32.v │ │ ├── hpdmc_obuft4.v │ │ ├── hpdmc_oddr32.v │ │ └── hpdmc_oddr4.v ├── i2c │ ├── i2c_master_bit_ctrl.v │ ├── i2c_master_byte_ctrl.v │ ├── i2c_master_defines.v │ ├── i2c_master_top.v │ └── timescale.v ├── lxp32 │ ├── lxp32_alu.vhd │ ├── lxp32_compl.vhd │ ├── lxp32_cpu.vhd │ ├── lxp32_dbus.vhd │ ├── lxp32_decode.vhd │ ├── lxp32_divider.vhd │ ├── lxp32_execute.vhd │ ├── lxp32_fetch.vhd │ ├── lxp32_icache.vhd │ ├── lxp32_interrupt_mux.vhd │ ├── lxp32_mul16x16.vhd │ ├── lxp32_mul_dsp.vhd │ ├── lxp32_mul_opt.vhd │ ├── lxp32_mul_seq.vhd │ ├── lxp32_ram256x32.vhd │ ├── lxp32_scratchpad.vhd │ ├── lxp32_shifter.vhd │ ├── lxp32_ubuf.vhd │ ├── lxp32c_top.vhd │ └── lxp32u_top.vhd ├── mac │ ├── .DS_Store │ ├── auto_verilog.sh │ ├── custom.el │ ├── include │ │ ├── CRC32_D64.v │ │ ├── CRC32_D8.v │ │ ├── defines.v │ │ ├── timescale.v │ │ └── utils.v │ └── verilog │ │ ├── fault_sm.v │ │ ├── generic_fifo.v │ │ ├── generic_fifo_ctrl.v │ │ ├── generic_mem_medium.v │ │ ├── generic_mem_small.v │ │ ├── meta_sync.v │ │ ├── meta_sync_single.v │ │ ├── rx_data_fifo.v │ │ ├── rx_dequeue.v │ │ ├── rx_enqueue.v │ │ ├── rx_hold_fifo.v │ │ ├── rx_stats_fifo.v │ │ ├── stats.v │ │ ├── stats_sm.v │ │ ├── sync_clk_core.v │ │ ├── sync_clk_wb.v │ │ ├── sync_clk_xgmii_tx.v │ │ ├── tx_data_fifo.v │ │ ├── tx_dequeue.v │ │ ├── tx_enqueue.v │ │ ├── tx_hold_fifo.v │ │ ├── tx_stats_fifo.v │ │ ├── wishbone_if.v │ │ └── xge_mac.v ├── minisoc │ ├── adv_debug_sys │ │ ├── Doc │ │ │ ├── or1k_debug_sys_manual.pdf │ │ │ └── src │ │ │ │ ├── block_diag_or1ksim.odg │ │ │ │ ├── block_diag_sim_rtl.odg │ │ │ │ ├── block_diag_sim_vpi.odg │ │ │ │ ├── debug_sys_blk_diag.odg │ │ │ │ ├── debug_sys_blk_diag_altera.odg │ │ │ │ └── or1k_debug_sys_manual.odt │ │ ├── Hardware │ │ │ ├── actel_ujtag │ │ │ │ ├── doc │ │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ │ ├── actel_ujtag.pdf │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ └── src │ │ │ │ │ │ └── actel_ujtag.odt │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ └── actel_ujtag.v │ │ │ ├── adv_dbg_if │ │ │ │ ├── bench │ │ │ │ │ ├── README_testbench.txt │ │ │ │ │ ├── full_system │ │ │ │ │ │ ├── adv_dbg_tb.v │ │ │ │ │ │ ├── onchip_ram_top.v │ │ │ │ │ │ ├── wave.do │ │ │ │ │ │ ├── xsv_fpga_defines.v │ │ │ │ │ │ └── xsv_fpga_top.v │ │ │ │ │ ├── jtag_serial_port │ │ │ │ │ │ ├── adv_dbg_jsp_tb.v │ │ │ │ │ │ └── wave.do │ │ │ │ │ └── simulated_system │ │ │ │ │ │ ├── adv_dbg_tb.v │ │ │ │ │ │ ├── cpu_behavioral.v │ │ │ │ │ │ ├── timescale.v │ │ │ │ │ │ ├── wave.do │ │ │ │ │ │ ├── wb_model_defines.v │ │ │ │ │ │ └── wb_slave_behavioral.v │ │ │ │ ├── doc │ │ │ │ │ ├── AdvancedDebugInterface.pdf │ │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ └── src │ │ │ │ │ │ ├── AdvancedDebugInterface.odt │ │ │ │ │ │ ├── generic_submodule.odg │ │ │ │ │ │ ├── jsp_submodule.odg │ │ │ │ │ │ ├── system_block_diagram.odg │ │ │ │ │ │ └── top_level_module.odg │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ ├── adbg_crc32.v │ │ │ │ │ ├── adbg_defines.v │ │ │ │ │ ├── adbg_jsp_biu.v │ │ │ │ │ ├── adbg_jsp_module.v │ │ │ │ │ ├── adbg_or1k_biu.v │ │ │ │ │ ├── adbg_or1k_defines.v │ │ │ │ │ ├── adbg_or1k_module.v │ │ │ │ │ ├── adbg_or1k_status_reg.v │ │ │ │ │ ├── adbg_top.v │ │ │ │ │ ├── adbg_wb_biu.v │ │ │ │ │ ├── adbg_wb_defines.v │ │ │ │ │ ├── adbg_wb_module.v │ │ │ │ │ ├── bytefifo.v │ │ │ │ │ ├── syncflop.v │ │ │ │ │ └── syncreg.v │ │ │ ├── altera_virtual_jtag │ │ │ │ ├── doc │ │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ │ ├── altera_virtual_jtag.pdf │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ └── src │ │ │ │ │ │ └── altera_virtual_jtag.odt │ │ │ │ └── rtl │ │ │ │ │ └── vhdl │ │ │ │ │ └── altera_virtual_jtag.vhd │ │ │ ├── jtag │ │ │ │ ├── BSDL │ │ │ │ │ └── opencores_tap.bsd │ │ │ │ ├── cells │ │ │ │ │ └── rtl │ │ │ │ │ │ └── verilog │ │ │ │ │ │ ├── BiDirectionalCell.v │ │ │ │ │ │ ├── ControlCell.v │ │ │ │ │ │ ├── InputCell.v │ │ │ │ │ │ └── OutputCell.v │ │ │ │ └── tap │ │ │ │ │ ├── doc │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ ├── jtag.pdf │ │ │ │ │ └── src │ │ │ │ │ │ ├── jtag.odt │ │ │ │ │ │ ├── oc_jtag_sys_diag.odg │ │ │ │ │ │ └── system_block_diagram.odg │ │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ ├── tap_defines.v │ │ │ │ │ └── tap_top.v │ │ │ └── xilinx_internal_jtag │ │ │ │ ├── doc │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ ├── gpl-2.0.txt │ │ │ │ ├── src │ │ │ │ │ ├── xilinx_bscan_waveform.odg │ │ │ │ │ └── xilinx_internal_jtag.odt │ │ │ │ └── xilinx_internal_jtag.pdf │ │ │ │ └── rtl │ │ │ │ └── verilog │ │ │ │ ├── xilinx_internal_jtag.v │ │ │ │ └── xilinx_internal_jtag_options.v │ │ ├── Patches │ │ │ ├── GDB6.8 │ │ │ │ └── gdb-6.8-bz436037-reg-no-longer-active.patch │ │ │ └── OR1200v1 │ │ │ │ └── or1200v1_hwbkpt.patch │ │ └── Software │ │ │ ├── AdvancedWatchpointControl │ │ │ ├── .classpath │ │ │ ├── .project │ │ │ ├── AdvancedWatchpointControl.jar │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── bin │ │ │ │ └── advancedWatchpointControl │ │ │ │ │ └── .keepme │ │ │ ├── doc │ │ │ │ ├── AdvancedWatchpointControl.pdf │ │ │ │ ├── EPL-v1.0.txt │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ ├── gpl-2.0.txt │ │ │ │ └── src │ │ │ │ │ ├── AdvancedWatchpointControl.odt │ │ │ │ │ ├── awc_block_diagram.odg │ │ │ │ │ ├── awc_ui_controlgroup.png │ │ │ │ │ ├── awc_ui_countersubgroup.png │ │ │ │ │ ├── awc_ui_full.png │ │ │ │ │ ├── awc_ui_serverconnection.png │ │ │ │ │ └── awc_ui_wpsubgroup.png │ │ │ ├── manifest │ │ │ ├── src │ │ │ │ └── advancedWatchpointControl │ │ │ │ │ ├── AdvancedWatchpointControl.java │ │ │ │ │ ├── LogMessageObserver.java │ │ │ │ │ ├── NetworkStatusObserver.java │ │ │ │ │ ├── ReadRegisterTransaction.java │ │ │ │ │ ├── RegisterObserver.java │ │ │ │ │ ├── TargetRunningTransaction.java │ │ │ │ │ ├── TargetTransaction.java │ │ │ │ │ ├── WriteRegisterTransaction.java │ │ │ │ │ ├── guiControlGroup.java │ │ │ │ │ ├── guiCountRegsGroup.java │ │ │ │ │ ├── guiDCRGroup.java │ │ │ │ │ ├── guiServerGroup.java │ │ │ │ │ ├── mainControl.java │ │ │ │ │ ├── networkSystem.java │ │ │ │ │ ├── registerInterpreter.java │ │ │ │ │ ├── rspCoder.java │ │ │ │ │ ├── targetDebugRegisterSet.java │ │ │ │ │ └── targetTransactor.java │ │ │ └── swt.jar │ │ │ └── adv_jtag_bridge │ │ │ ├── BUILDING │ │ │ ├── BUILDING.classic │ │ │ ├── Makefile.am │ │ │ ├── Makefile.classic │ │ │ ├── adv_dbg_commands.c │ │ │ ├── adv_dbg_commands.h │ │ │ ├── adv_jtag_bridge.c │ │ │ ├── adv_jtag_bridge.h │ │ │ ├── altera_virtual_jtag.h │ │ │ ├── autogen.sh │ │ │ ├── bsdl.c │ │ │ ├── bsdl.h │ │ │ ├── bsdl_parse.c │ │ │ ├── bsdl_parse.h │ │ │ ├── cable_common.c │ │ │ ├── cable_common.h │ │ │ ├── cable_ft2232.c │ │ │ ├── cable_ft2232.h │ │ │ ├── cable_ft245.c │ │ │ ├── cable_ft245.h │ │ │ ├── cable_parallel.c │ │ │ ├── cable_parallel.h │ │ │ ├── cable_sim.c │ │ │ ├── cable_sim.h │ │ │ ├── cable_usbblaster.c │ │ │ ├── cable_usbblaster.h │ │ │ ├── cable_usbblaster_ftdi.c │ │ │ ├── cable_xpc_dlc9.c │ │ │ ├── cable_xpc_dlc9.h │ │ │ ├── chain_commands.c │ │ │ ├── chain_commands.h │ │ │ ├── configure.ac │ │ │ ├── dbg_api.c │ │ │ ├── dbg_api.h │ │ │ ├── doc │ │ │ ├── License_FDL-1.2.txt │ │ │ ├── adv_jtag_bridge.pdf │ │ │ ├── gpl-2.0.txt │ │ │ └── src │ │ │ │ ├── adv_jtag_bridge.odt │ │ │ │ └── ajb_block_diagram.odg │ │ │ ├── errcodes.c │ │ │ ├── errcodes.h │ │ │ ├── except.h │ │ │ ├── gdb-6.8-bz436037-reg-no-longer-active.patch │ │ │ ├── hardware_monitor.c │ │ │ ├── hardware_monitor.h │ │ │ ├── hwp_server.c │ │ │ ├── hwp_server.h │ │ │ ├── jsp_server.c │ │ │ ├── jsp_server.h │ │ │ ├── legacy_dbg_commands.c │ │ │ ├── legacy_dbg_commands.h │ │ │ ├── opencores_tap.h │ │ │ ├── or32_selftest.c │ │ │ ├── or32_selftest.h │ │ │ ├── rsp-server.c │ │ │ ├── rsp-server.h │ │ │ ├── sim_lib │ │ │ ├── Makefile │ │ │ ├── icarus │ │ │ │ └── Makefile │ │ │ ├── modelsim_linux_x86 │ │ │ │ └── Makefile │ │ │ ├── modelsim_win32 │ │ │ │ ├── Makefile │ │ │ │ └── jp-io-vpi.dll │ │ │ └── src │ │ │ │ └── jp-io-vpi.c │ │ │ ├── sim_rtl │ │ │ ├── dbg_comm.v │ │ │ └── dbg_comm_vpi.v │ │ │ ├── spr-defs.h │ │ │ ├── utilities.c │ │ │ └── utilities.h │ ├── altera_pll.v │ ├── ethmac │ │ ├── README.txt │ │ ├── bench │ │ │ └── verilog │ │ │ │ ├── eth_host.v │ │ │ │ ├── eth_memory.v │ │ │ │ ├── eth_phy.v │ │ │ │ ├── eth_phy_defines.v │ │ │ │ ├── tb_cop.v │ │ │ │ ├── tb_eth_defines.v │ │ │ │ ├── tb_eth_top.v │ │ │ │ ├── tb_ethernet.v │ │ │ │ ├── tb_ethernet_with_cop.v │ │ │ │ ├── wb_bus_mon.v │ │ │ │ ├── wb_master32.v │ │ │ │ ├── wb_master_behavioral.v │ │ │ │ ├── wb_model_defines.v │ │ │ │ └── wb_slave_behavioral.v │ │ ├── doc │ │ │ ├── eth_design_document.pdf │ │ │ ├── eth_speci.pdf │ │ │ ├── ethernet_datasheet_OC_head.pdf │ │ │ ├── ethernet_product_brief_OC_head.pdf │ │ │ └── src │ │ │ │ ├── eth_design_document.doc │ │ │ │ ├── eth_speci.doc │ │ │ │ ├── ethernet_datasheet_OC_head.doc │ │ │ │ └── ethernet_product_brief_OC_head.doc │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── BUGS │ │ │ │ ├── TODO │ │ │ │ ├── eth_clockgen.v │ │ │ │ ├── eth_cop.v │ │ │ │ ├── eth_crc.v │ │ │ │ ├── eth_fifo.v │ │ │ │ ├── eth_maccontrol.v │ │ │ │ ├── eth_macstatus.v │ │ │ │ ├── eth_miim.v │ │ │ │ ├── eth_outputcontrol.v │ │ │ │ ├── eth_random.v │ │ │ │ ├── eth_receivecontrol.v │ │ │ │ ├── eth_register.v │ │ │ │ ├── eth_registers.v │ │ │ │ ├── eth_rxaddrcheck.v │ │ │ │ ├── eth_rxcounters.v │ │ │ │ ├── eth_rxethmac.v │ │ │ │ ├── eth_rxstatem.v │ │ │ │ ├── eth_shiftreg.v │ │ │ │ ├── eth_spram_256x32.v │ │ │ │ ├── eth_top.v │ │ │ │ ├── eth_transmitcontrol.v │ │ │ │ ├── eth_txcounters.v │ │ │ │ ├── eth_txethmac.v │ │ │ │ ├── eth_txstatem.v │ │ │ │ ├── eth_wishbone.v │ │ │ │ ├── ethmac.v │ │ │ │ ├── ethmac_defines.v │ │ │ │ ├── timescale.v │ │ │ │ └── xilinx_dist_ram_16x32.v │ │ ├── scripts │ │ │ ├── Makefile │ │ │ └── icarus.scr │ │ └── sim │ │ │ └── rtl_sim │ │ │ ├── bin │ │ │ ├── INCA_libs │ │ │ │ └── worklib │ │ │ │ │ └── dir_keeper │ │ │ ├── artisan_file_list.lst │ │ │ ├── cds.lib │ │ │ ├── hdl.var │ │ │ ├── ncelab.args │ │ │ ├── ncelab_xilinx.args │ │ │ ├── ncsim.rc │ │ │ ├── ncsim_waves.rc │ │ │ ├── rtl_file_list.lst │ │ │ ├── run_sim │ │ │ ├── sim_file_list.lst │ │ │ └── xilinx_file_list.lst │ │ │ ├── log │ │ │ └── dir_keeper │ │ │ ├── modelsim_sim │ │ │ ├── bin │ │ │ │ ├── do.do │ │ │ │ ├── eth_wave.do │ │ │ │ ├── ethernet.mpf │ │ │ │ ├── vlog.opt │ │ │ │ └── work │ │ │ │ │ ├── _info │ │ │ │ │ └── dir.keeper │ │ │ ├── log │ │ │ │ └── dir.keeper │ │ │ ├── out │ │ │ │ └── dir.keeper │ │ │ └── run │ │ │ │ ├── dir.keeper │ │ │ │ └── tb_eth.do │ │ │ ├── ncsim_sim │ │ │ ├── bin │ │ │ │ ├── INCA_libs │ │ │ │ │ └── worklib │ │ │ │ │ │ └── dir_keeper │ │ │ │ ├── artisan_file_list.lst │ │ │ │ ├── cds.lib │ │ │ │ ├── hdl.var │ │ │ │ ├── ncelab.args │ │ │ │ ├── ncelab_xilinx.args │ │ │ │ ├── ncsim.rc │ │ │ │ ├── ncsim_waves.rc │ │ │ │ ├── rtl_file_list.lst │ │ │ │ ├── sim_file_list.lst │ │ │ │ ├── vs_file_list.lst │ │ │ │ └── xilinx_file_list.lst │ │ │ ├── log │ │ │ │ ├── dir_keeper │ │ │ │ ├── eth_tb.log │ │ │ │ └── tb_eth_display.log │ │ │ ├── out │ │ │ │ └── dir_keeper │ │ │ └── run │ │ │ │ ├── clean │ │ │ │ ├── run_eth_sim_regr.scr │ │ │ │ └── top_groups.do │ │ │ ├── out │ │ │ └── dir_keeper │ │ │ └── run │ │ │ ├── clean │ │ │ ├── run_eth_sim_regr.scr │ │ │ └── top_groups.do │ ├── interconnect_defines.v │ ├── minsoc_clock_manager.v │ ├── minsoc_onchip_ram.v │ ├── minsoc_onchip_ram_top.v │ ├── minsoc_startup │ │ ├── OR1K_startup_generic.v │ │ ├── spi_clgen.v │ │ ├── spi_defines.v │ │ ├── spi_shift.v │ │ └── spi_top.v │ ├── minsoc_tc_top.v │ ├── minsoc_top.v │ ├── minsoc_xilinx_internal_jtag.v │ ├── or1200 │ │ ├── bench │ │ │ └── README │ │ ├── doc │ │ │ ├── Makefile │ │ │ ├── docbook-xsl.css │ │ │ ├── docbook.xsl │ │ │ ├── gen-docinfo.pl │ │ │ ├── img │ │ │ │ ├── addr_translation.gif │ │ │ │ ├── core_arch.gif │ │ │ │ ├── core_interfaces.gif │ │ │ │ ├── cpu_fpu_dsp.gif │ │ │ │ ├── data_cache_diag.gif │ │ │ │ ├── debug_unit_diag.gif │ │ │ │ ├── dev_interface_cycles.gif │ │ │ │ ├── inst_cache_diag.gif │ │ │ │ ├── inst_mmu_diag.gif │ │ │ │ ├── interrupt_controller.gif │ │ │ │ ├── or_family.gif │ │ │ │ ├── powerup_seq.gif │ │ │ │ ├── powerup_seq_gatedclk.gif │ │ │ │ ├── tlb_diag.gif │ │ │ │ ├── watchpoint_trigger.gif │ │ │ │ ├── wb_block_read.gif │ │ │ │ ├── wb_compatible.png │ │ │ │ ├── wb_read.gif │ │ │ │ ├── wb_rw.gif │ │ │ │ └── wb_write.gif │ │ │ ├── openrisc1200_spec.doc │ │ │ ├── openrisc1200_spec.odt │ │ │ ├── openrisc1200_spec.pdf │ │ │ ├── openrisc1200_spec.txt │ │ │ ├── openrisc1200_spec_0.7_jp.doc │ │ │ ├── openrisc1200_spec_0.7_jp.pdf │ │ │ ├── openrisc1200_supplementary_prm.odt │ │ │ ├── openrisc1200_supplementary_prm.pdf │ │ │ └── preprocess.pl │ │ ├── lib │ │ │ └── README │ │ ├── lint │ │ │ ├── bin │ │ │ │ ├── README │ │ │ │ └── run_lint │ │ │ ├── log │ │ │ │ └── README │ │ │ └── run │ │ │ │ └── README │ │ ├── rtl │ │ │ └── verilog │ │ │ │ ├── or1200_alu.v │ │ │ │ ├── or1200_amultp2_32x32.v │ │ │ │ ├── or1200_cfgr.v │ │ │ │ ├── or1200_cpu.v │ │ │ │ ├── or1200_ctrl.v │ │ │ │ ├── or1200_dc_fsm.v │ │ │ │ ├── or1200_dc_ram.v │ │ │ │ ├── or1200_dc_tag.v │ │ │ │ ├── or1200_dc_top.v │ │ │ │ ├── or1200_defines.v │ │ │ │ ├── or1200_dmmu_tlb.v │ │ │ │ ├── or1200_dmmu_top.v │ │ │ │ ├── or1200_dpram.v │ │ │ │ ├── or1200_dpram_256x32.v │ │ │ │ ├── or1200_dpram_32x32.v │ │ │ │ ├── or1200_du.v │ │ │ │ ├── or1200_except.v │ │ │ │ ├── or1200_fpu.v │ │ │ │ ├── or1200_fpu_addsub.v │ │ │ │ ├── or1200_fpu_arith.v │ │ │ │ ├── or1200_fpu_div.v │ │ │ │ ├── or1200_fpu_fcmp.v │ │ │ │ ├── or1200_fpu_intfloat_conv.v │ │ │ │ ├── or1200_fpu_intfloat_conv_except.v │ │ │ │ ├── or1200_fpu_mul.v │ │ │ │ ├── or1200_fpu_post_norm_addsub.v │ │ │ │ ├── or1200_fpu_post_norm_div.v │ │ │ │ ├── or1200_fpu_post_norm_intfloat_conv.v │ │ │ │ ├── or1200_fpu_post_norm_mul.v │ │ │ │ ├── or1200_fpu_pre_norm_addsub.v │ │ │ │ ├── or1200_fpu_pre_norm_div.v │ │ │ │ ├── or1200_fpu_pre_norm_mul.v │ │ │ │ ├── or1200_freeze.v │ │ │ │ ├── or1200_genpc.v │ │ │ │ ├── or1200_gmultp2_32x32.v │ │ │ │ ├── or1200_ic_fsm.v │ │ │ │ ├── or1200_ic_ram.v │ │ │ │ ├── or1200_ic_tag.v │ │ │ │ ├── or1200_ic_top.v │ │ │ │ ├── or1200_if.v │ │ │ │ ├── or1200_immu_tlb.v │ │ │ │ ├── or1200_immu_top.v │ │ │ │ ├── or1200_iwb_biu.v │ │ │ │ ├── or1200_lsu.v │ │ │ │ ├── or1200_mem2reg.v │ │ │ │ ├── or1200_mult_mac.v │ │ │ │ ├── or1200_operandmuxes.v │ │ │ │ ├── or1200_pic.v │ │ │ │ ├── or1200_pm.v │ │ │ │ ├── or1200_qmem_top.v │ │ │ │ ├── or1200_reg2mem.v │ │ │ │ ├── or1200_rf.v │ │ │ │ ├── or1200_rfram_generic.v │ │ │ │ ├── or1200_sb.v │ │ │ │ ├── or1200_sb_fifo.v │ │ │ │ ├── or1200_spram.v │ │ │ │ ├── or1200_spram_1024x32.v │ │ │ │ ├── or1200_spram_1024x32_bw.v │ │ │ │ ├── or1200_spram_1024x8.v │ │ │ │ ├── or1200_spram_128x32.v │ │ │ │ ├── or1200_spram_2048x32.v │ │ │ │ ├── or1200_spram_2048x32_bw.v │ │ │ │ ├── or1200_spram_2048x8.v │ │ │ │ ├── or1200_spram_256x21.v │ │ │ │ ├── or1200_spram_32_bw.v │ │ │ │ ├── or1200_spram_32x24.v │ │ │ │ ├── or1200_spram_512x20.v │ │ │ │ ├── or1200_spram_64x14.v │ │ │ │ ├── or1200_spram_64x22.v │ │ │ │ ├── or1200_spram_64x24.v │ │ │ │ ├── or1200_sprs.v │ │ │ │ ├── or1200_top.v │ │ │ │ ├── or1200_tpram_32x32.v │ │ │ │ ├── or1200_tt.v │ │ │ │ ├── or1200_wb_biu.v │ │ │ │ ├── or1200_wbmux.v │ │ │ │ ├── or1200_xcv_ram32x8d.v │ │ │ │ └── timescale.v │ │ ├── sim │ │ │ └── README │ │ └── syn │ │ │ └── synopsys │ │ │ ├── bin │ │ │ ├── README │ │ │ ├── read_design.inc │ │ │ ├── run_syn │ │ │ └── top.scr │ │ │ ├── log │ │ │ └── README │ │ │ ├── out │ │ │ └── README │ │ │ └── run │ │ │ └── README │ ├── timescale.v │ ├── uart16550 │ │ ├── bench │ │ │ ├── verilog │ │ │ │ ├── readme.txt │ │ │ │ ├── test_cases │ │ │ │ │ └── uart_int.v │ │ │ │ ├── uart_device.v │ │ │ │ ├── uart_device_utilities.v │ │ │ │ ├── uart_log.v │ │ │ │ ├── uart_test.v │ │ │ │ ├── uart_testbench.v │ │ │ │ ├── uart_testbench_defines.v │ │ │ │ ├── uart_testbench_utilities.v │ │ │ │ ├── uart_wb_utilities.v │ │ │ │ ├── vapi.log │ │ │ │ ├── wb_mast.v │ │ │ │ ├── wb_master_model.v │ │ │ │ └── wb_model_defines.v │ │ │ └── vhdl │ │ │ │ └── .keepme │ │ ├── doc │ │ │ ├── CHANGES.txt │ │ │ ├── UART_spec.pdf │ │ │ └── src │ │ │ │ └── UART_spec.doc │ │ ├── fv │ │ │ └── .keepme │ │ ├── lint │ │ │ ├── bin │ │ │ │ └── .keepme │ │ │ ├── log │ │ │ │ └── .keepme │ │ │ ├── out │ │ │ │ └── .keepme │ │ │ └── run │ │ │ │ └── .keepme │ │ ├── rtl │ │ │ ├── verilog-backup │ │ │ │ ├── timescale.v │ │ │ │ ├── uart_defines.v │ │ │ │ ├── uart_fifo.v │ │ │ │ ├── uart_receiver.v │ │ │ │ ├── uart_regs.v │ │ │ │ ├── uart_top.v │ │ │ │ ├── uart_transmitter.v │ │ │ │ └── uart_wb.v │ │ │ ├── verilog │ │ │ │ ├── raminfr.v │ │ │ │ ├── timescale.v │ │ │ │ ├── uart_debug_if.v │ │ │ │ ├── uart_defines.v │ │ │ │ ├── uart_receiver.v │ │ │ │ ├── uart_regs.v │ │ │ │ ├── uart_rfifo.v │ │ │ │ ├── uart_sync_flops.v │ │ │ │ ├── uart_tfifo.v │ │ │ │ ├── uart_top.v │ │ │ │ ├── uart_transmitter.v │ │ │ │ └── uart_wb.v │ │ │ └── vhdl │ │ │ │ └── .keepme │ │ ├── sim │ │ │ ├── gate_sim │ │ │ │ ├── bin │ │ │ │ │ └── .keepme │ │ │ │ ├── log │ │ │ │ │ └── .keepme │ │ │ │ ├── out │ │ │ │ │ └── .keepme │ │ │ │ ├── run │ │ │ │ │ └── .keepme │ │ │ │ └── src │ │ │ │ │ └── .keepme │ │ │ └── rtl_sim │ │ │ │ ├── bin │ │ │ │ ├── nc.scr │ │ │ │ └── sim.tcl │ │ │ │ ├── log │ │ │ │ ├── .keepme │ │ │ │ ├── uart_interrupts_report.log │ │ │ │ └── uart_interrupts_verbose.log │ │ │ │ ├── out │ │ │ │ └── .keepme │ │ │ │ ├── run │ │ │ │ ├── run_signalscan │ │ │ │ ├── run_sim │ │ │ │ └── run_sim.scr │ │ │ │ └── src │ │ │ │ └── .keepme │ │ └── syn │ │ │ ├── bin │ │ │ └── .keepme │ │ │ ├── log │ │ │ └── .keepme │ │ │ ├── out │ │ │ └── .keepme │ │ │ ├── run │ │ │ └── .keepme │ │ │ └── src │ │ │ └── .keepme │ └── xilinx_dcm.v ├── neo430 │ ├── .DS_Store │ ├── core │ │ ├── neo430_addr_gen.vhd │ │ ├── neo430_alu.vhd │ │ ├── neo430_application_image.vhd │ │ ├── neo430_boot_rom.vhd │ │ ├── neo430_bootloader_image.vhd │ │ ├── neo430_cfu.vhd │ │ ├── neo430_control.vhd │ │ ├── neo430_cpu.vhd │ │ ├── neo430_crc.vhd │ │ ├── neo430_dmem.vhd │ │ ├── neo430_gpio.vhd │ │ ├── neo430_imem.vhd │ │ ├── neo430_muldiv.vhd │ │ ├── neo430_package.vhd │ │ ├── neo430_pwm.vhd │ │ ├── neo430_reg_file.vhd │ │ ├── neo430_spi.vhd │ │ ├── neo430_sysconfig.vhd │ │ ├── neo430_timer.vhd │ │ ├── neo430_top.vhd │ │ ├── neo430_twi.vhd │ │ ├── neo430_uart.vhd │ │ ├── neo430_wb_interface.vhd │ │ └── neo430_wdt.vhd │ └── top_templates │ │ ├── README.txt │ │ ├── neo430_test.vhd │ │ ├── neo430_top_avm.vhd │ │ ├── neo430_top_axi4lite.vhd │ │ └── neo430_top_std_logic.vhd ├── openMSP430 │ ├── filelist.f │ ├── omsp_alu.v │ ├── omsp_and_gate.v │ ├── omsp_clock_gate.v │ ├── omsp_clock_module.v │ ├── omsp_clock_mux.v │ ├── omsp_dbg.v │ ├── omsp_dbg_hwbrk.v │ ├── omsp_dbg_i2c.v │ ├── omsp_dbg_uart.v │ ├── omsp_execution_unit.v │ ├── omsp_frontend.v │ ├── omsp_mem_backbone.v │ ├── omsp_multiplier.v │ ├── omsp_register_file.v │ ├── omsp_scan_mux.v │ ├── omsp_sfr.v │ ├── omsp_sync_cell.v │ ├── omsp_sync_reset.v │ ├── omsp_wakeup_cell.v │ ├── omsp_watchdog.v │ ├── openMSP430.v │ ├── openMSP430_defines.v │ ├── openMSP430_undefines.v │ └── periph │ │ ├── omsp_gpio.v │ │ ├── omsp_timerA.v │ │ ├── omsp_timerA_defines.v │ │ ├── omsp_timerA_undefines.v │ │ ├── template_periph_16b.v │ │ └── template_periph_8b.v ├── pairing │ ├── COPYING.LESSER.txt │ ├── f3.v │ ├── f32m.v │ ├── f33m.v │ ├── f36m.v │ ├── f3m.v │ ├── fun.v │ ├── inc.v │ └── tate_pairing.v ├── sdc │ ├── .DS_Store │ ├── README.txt │ ├── format │ ├── sdc_dma │ │ └── verilog │ │ │ ├── sd_bd.v │ │ │ ├── sd_clock_divider.v │ │ │ ├── sd_cmd_master.v │ │ │ ├── sd_cmd_serial_host.v │ │ │ ├── sd_controller_wb.v │ │ │ ├── sd_crc_16.v │ │ │ ├── sd_crc_7.v │ │ │ ├── sd_data_master.v │ │ │ ├── sd_data_serial_host.v │ │ │ ├── sd_defines.v │ │ │ ├── sd_fifo_rx_filler.v │ │ │ ├── sd_fifo_tx_filler.v │ │ │ ├── sd_rx_fifo.v │ │ │ ├── sd_rx_fifo_tb.v │ │ │ ├── sd_tx_fifo.v │ │ │ └── sdc_controller.v │ └── sdc_fifo │ │ └── verilog │ │ ├── Makefile │ │ ├── sd_cmd_phy.v │ │ ├── sd_controller_fifo_actel.v │ │ ├── sd_controller_fifo_wb.v │ │ ├── sd_counter.v │ │ ├── sd_crc_16.v │ │ ├── sd_crc_7.v │ │ ├── sd_data_phy.v │ │ ├── sd_defines.v │ │ ├── sd_fifo.v │ │ ├── sd_ip_comp_inst.v │ │ ├── versatile_fifo_async_cmp.v │ │ └── versatile_fifo_dptam_dw.v ├── sdr_ctrl │ ├── core │ │ ├── sdrc_bank_ctl.v │ │ ├── sdrc_bank_fsm.v │ │ ├── sdrc_bs_convert.v │ │ ├── sdrc_core.v │ │ ├── sdrc_define.v │ │ ├── sdrc_req_gen.v │ │ └── sdrc_xfr_ctl.v │ ├── filelist_rtl.f │ ├── lib │ │ ├── async_fifo.v │ │ └── sync_fifo.v │ ├── top │ │ └── sdrc_top.v │ └── wb2sdrc │ │ └── wb2sdrc.v ├── sha3 │ ├── f_permutation.v │ ├── keccak.v │ ├── padder.v │ ├── padder1.v │ ├── rconst2in1.v │ └── round2in1.v ├── sha3_2 │ ├── f_permutation.v │ ├── keccak.v │ ├── padder.v │ ├── padder1.v │ ├── rconst.v │ └── round.v ├── sockit │ ├── onewire_slave_model.v │ ├── onewire_tb.v │ ├── sockit_owm.v │ └── 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