├── .gitignore ├── LICENSE ├── README.md ├── capstone ├── CREDITS.TXT ├── ChangeLog ├── LICENSE.TXT ├── LICENSE_LLVM.TXT ├── README ├── RELEASE_NOTES ├── include │ ├── arm.h │ ├── arm64.h │ ├── capstone.h │ ├── mips.h │ ├── platform.h │ ├── ppc.h │ ├── sparc.h │ ├── systemz.h │ ├── x86.h │ └── xcore.h └── lib │ ├── capstone.debug.x86_32.lib │ ├── capstone.debug.x86_64.lib │ ├── capstone.release.x86_32.lib │ └── capstone.release.x86_64.lib ├── jitasm.Backend.h ├── jitasm.Backend.x86.cpp ├── jitasm.Backend.x86.h ├── jitasm.Backend.x86_32.h ├── jitasm.Backend.x86_64.h ├── jitasm.CodeBuffer.h ├── jitasm.Frontend.h ├── jitasm.Frontend.x86.h ├── jitasm.Frontend.x86_32.h ├── jitasm.Frontend.x86_64.h ├── jitasm.h ├── jitasm.sln ├── jitasm.vcxproj ├── jitasm.vcxproj.filters ├── jitasm.x86.encoder.h ├── jitasm.x86.h ├── jitasm.x86_32.h ├── jitasm.x86_64.h └── test ├── test.cpp ├── test.vcxproj └── test.vcxproj.filters /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Object files 2 | *.slo 3 | *.lo 4 | *.o 5 | *.obj 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Compiled Dynamic libraries 12 | *.so 13 | *.dylib 14 | *.dll 15 | 16 | # Fortran module files 17 | *.mod 18 | 19 | # Compiled Static libraries 20 | *.lai 21 | *.la 22 | *.a 23 | 24 | # Executables 25 | *.exe 26 | *.out 27 | *.app 28 | x64/Release 29 | test/x64/Release 30 | *.suo 31 | *.sdf 32 | *.opensdf 33 | Debug/ 34 | Release/ 35 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2014, hlide 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | * Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 14 | * Neither the name of jitasm nor the names of its 15 | contributors may be used to endorse or promote products derived from 16 | this software without specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | jitasm 2 | ====== 3 | 4 | JIT Assembler Library for multiple ISAs. For now, only x86. 5 | 6 | ### Goal 7 | 8 | To emit assembly code to create run-time functions dynamically with the optional ability to use virtual (symbolic or memory-mapped) registers to let jitasm compiler allocates physical registers itself using a linear scan register allocation. 9 | 10 | ### Features [*in progress*] 11 | 12 | - *Header file only* 13 | - Support for 32-bit and 64-bit x86, *mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, avx, avx2, avx3, fma, xop, fma4* 14 | - *Register allocation* 15 | - Support for Windows, *Linux, FreeBSD, Mac* 16 | 17 | ### Status 18 | 19 | -=[ WORK IN PROGRESS ]=- 20 | 21 | ### Remark 22 | 23 | Everything may undergo change 24 | 25 | ### X86 Manuals 26 | 27 | Finding out some text or xml files to describe the opcode maps of all the x86 instructions up to AVX3 is almost impossible. So far there are only two sources : 28 | - xml file : http://ref.x86asm.net/x86reference.xml 29 | - txt file : http://lxr.free-electrons.com/source/arch/x86/lib/x86-opcode-map.txt?v=3.18 30 | 31 | As for web links to manuals, I found out three interesting links : 32 | - http://www.sandpile.org/ : the most complete one since it contains AVX3 instructions. I am also attempting to put the opcode maps into one page and perhaps I will use it to extract instructions details to make a source file to describe all x86 isntructions I need. 33 | - http://www.felixcloutier.com/x86/ : this one is normally auto-generated from Intel manuals but it lacks opcode maps and AVX3 instructions. 34 | - http://ref.x86asm.net : this one is probably the most informative except that it does not contain AVX+ instructions. 35 | 36 | There are of course PDF manuals of Intel and AMD - but you know, they are not that easy to extract informations on instructions (some instructions are not extracted correctly in http://www.felixcloutier.com/x86/). 37 | -------------------------------------------------------------------------------- /capstone/CREDITS.TXT: -------------------------------------------------------------------------------- 1 | This file credits all the contributors of the Capstone engine project. 2 | 3 | Key developers 4 | ============== 5 | 1. Nguyen Anh Quynh 6 | - Core engine 7 | - Bindings: Python, Ruby, OCaml, Java, C# 8 | 9 | 2. Tan Sheng Di 10 | - Bindings: Ruby 11 | 12 | 3. Ben Nagy 13 | - Bindings: Ruby, Go 14 | 15 | 4. Dang Hoang Vu 16 | - Bindings: Java 17 | 18 | 19 | Beta testers (in random order) 20 | ============================== 21 | Pancake 22 | Van Hauser 23 | FX of Phenoelit 24 | The Grugq, The Grugq <-- our hero for submitting the first ever patch! 25 | Isaac Dawson, Veracode Inc 26 | Patroklos Argyroudis, Census Inc. (http://census-labs.com) 27 | Attila Suszter 28 | Le Dinh Long 29 | Nicolas Ruff 30 | Gunther 31 | Alex Ionescu, Winsider Seminars & Solutions Inc. 32 | Snare 33 | Daniel Godas-Lopez 34 | Joshua J. Drake 35 | Edgar Barbosa 36 | Ralf-Philipp Weinmann 37 | Hugo Fortier 38 | Joxean Koret 39 | Bruce Dang 40 | Andrew Dunham 41 | 42 | 43 | Contributors (in no particular order) 44 | ===================================== 45 | (Please let us know if you want to have your name here) 46 | 47 | Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!) 48 | Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC. 49 | Daniel Pistelli: Cmake support. 50 | Peter Hlavaty: integrate Capstone for Windows kernel drivers. 51 | Guillaume Jeanne: Ocaml binding. 52 | -------------------------------------------------------------------------------- /capstone/ChangeLog: -------------------------------------------------------------------------------- 1 | This file details the changelog of Capstone. 2 | 3 | --------------------------------- 4 | Version 2.1.2: April 3rd, 2014 5 | 6 | This is a stable release to fix some bugs deep in the core. There is no update 7 | to any architectures or bindings, so bindings version 2.1 can be used with this 8 | version 2.1.2 just fine. 9 | 10 | [ Core changes] 11 | 12 | - Support cross-compilation for all iDevices (iPhone/iPad/iPod). 13 | - X86: do not print memory offset in negative form. 14 | - Fix a bug in X86 when Capstone cannot handle short instruction. 15 | - Print negative number above -9 without prefix 0x (arm64, mips, arm). 16 | - Correct the SONAME setup for library versioning (Linux, *BSD, Solaris). 17 | - Set library versioning for dylib of OSX. 18 | 19 | --------------------------------- 20 | Version 2.1.1: March 13th, 2014 21 | 22 | This is a stable release to fix some bugs deep in the core. There is no update 23 | to any architectures or bindings, so bindings version 2.1 can be used with this 24 | version 2.1.1 just fine. 25 | 26 | [ Core changes] 27 | 28 | - Fix a buffer overflow bug in Thumb mode (ARM). Some special input can 29 | trigger this flaw. 30 | - Fix a crash issue when embedding Capstone into OSX kernel. This should 31 | also enable Capstone to be embedded into other systems with limited stack 32 | memory size such as Linux kernel or some firmwares. 33 | - Use a proper SONAME for library versioning (Linux). 34 | 35 | --------------------------------- 36 | Version 2.1: March 5th, 2014 37 | 38 | [ API changes ] 39 | 40 | - API version has been bumped to 2.1. 41 | - Change prototype of cs_close() to be able to invalidate closed handle. 42 | See http://capstone-engine.org/version_2.1_API.html for more information. 43 | - Extend cs_support() to handle more query types, not only about supported 44 | architectures. This change is backward compatible, however, so existent code 45 | do not need to be modified to support this. 46 | - New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of 47 | the engine. 48 | - New error code CS_ERR_DIET to report errors about newly added diet mode. 49 | - New error code CS_ERR_VERSION to report issue of incompatible versions between 50 | bindings & core engine. 51 | 52 | 53 | [ Core changes ] 54 | 55 | - On memory usage, Capstone uses about 40% less memory, while still faster 56 | than version 2.0. 57 | - All architectures are much smaller: binaries size reduce at least 30%. 58 | Especially, X86-only binary reduces from 1.9MB to just 720KB. 59 | - Support "diet" mode, in which engine size is further reduced (by around 40%) 60 | for embedding purpose. The price to pay is that we have to sacrifice some 61 | non-critical data fields. See http://capstone-engine.org/diet.html for more 62 | details. 63 | 64 | 65 | [ Architectures ] 66 | 67 | - Update all 5 architectures to fix bugs. 68 | - PowerPC: 69 | - New instructions: FMR & MSYNC. 70 | - Mips: 71 | - New instruction: DLSA 72 | - X86: 73 | - Properly handle AVX-512 instructions. 74 | - New instructions: PSETPM, SALC, INT1, GETSEC. 75 | - Fix some memory leaking issues in case of prefixed instructions such 76 | as LOCK, REP, REPNE. 77 | 78 | 79 | [ Python binding ] 80 | 81 | - Verify the core version at initialization time. Refuse to run if its version 82 | is different from the core's version. 83 | - New API disasm_lite() added to Cs class. This light API only returns tuples of 84 | (address, size, mnemonic, op_str), rather than list of CsInsn objects. This 85 | improves performance by around 30% in some benchmarks. 86 | - New API version_bind() returns binding's version, which might differ from 87 | the core's API version if the binding is out-of-date. 88 | - New API debug() returns information on Cython support, diet status & archs 89 | compiled in. 90 | - Fixed some memory leaking bugs for Cython binding. 91 | - Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups. 92 | - Support diet mode. 93 | 94 | 95 | [ Java binding ] 96 | 97 | - Fix some memory leaking bugs. 98 | - New API version() returns combined version. 99 | - Support diet mode. 100 | - Better support for detail option. 101 | 102 | 103 | [ Miscellaneous ] 104 | 105 | - make.sh now can uninstall the core engine. This is done with: 106 | 107 | $ sudo ./make.sh uninstall 108 | 109 | ---------------------------------- 110 | Version 2.0: January 22nd, 2014 111 | 112 | Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. 113 | 114 | [ API changes ] 115 | 116 | - API version has been bumped to 2.0 (see cs_version() API) 117 | - New API cs_strerror(errno) returns a string describing error code given 118 | in its only argument. 119 | - cs_version() now returns combined version encoding both major & minor versions. 120 | - New option CS_OPT_MODE allows to change engine’s mode at run-time with 121 | cs_option(). 122 | - New option CS_OPT_MEM allows to specify user-defined functions for dynamically 123 | memory management used internally by Capstone. This is useful to embed Capstone 124 | into special environments such as kernel or firware. 125 | - New API cs_support() can be used to check if this lib supports a particular 126 | architecture (this is necessary since we now allow to choose which architectures 127 | to compile in). 128 | - The detail option is OFF by default now. To get detail information, it should be 129 | explicitly turned ON. The details then can be accessed using cs_insn.detail 130 | pointer (to newly added structure cs_detail) 131 | 132 | 133 | [ Core changes ] 134 | 135 | - On memory usage, Capstone uses much less memory, but a lot faster now. 136 | - User now can choose which architectures to be supported by modifying config.mk 137 | before compiling/installing. 138 | 139 | 140 | [ Architectures ] 141 | 142 | - Arm 143 | - Support Big-Endian mode (besides Little-Endian mode). 144 | - Support friendly register, so instead of output sub "r12,r11,0x14", 145 | we have "sub ip,fp,0x14". 146 | - Arm64: support Big-Endian mode (besides Little-Endian mode). 147 | - PowerPC: newly added. 148 | - Mips: support friendly register, so instead of output "srl $2,$1,0x1f", 149 | we have "srl $v0,$at,0x1f". 150 | - X86: bug fixes. 151 | 152 | 153 | [ Python binding ] 154 | 155 | - Python binding is vastly improved in performance: around 3 ~ 4 times faster 156 | than in 1.0. 157 | - Cython support has been added, which can further speed up over the default 158 | pure Python binding (up to 30% in some cases) 159 | - Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) 160 | to return succesfully disassembled instructions. This improves the performance 161 | and reduces memory usage. 162 | 163 | 164 | [ Java binding ] 165 | 166 | - Better performance & bug fixes. 167 | 168 | 169 | [ Miscellaneous ] 170 | 171 | - Fixed some installation issues with Gentoo Linux. 172 | - Capstone now can easily compile/install on all *nix, including Linux, OSX, 173 | {Net, Free, Open}BSD & Solaris. 174 | 175 | ---------------------------------- 176 | [Version 1.0]: December 18th, 2013 177 | 178 | - Initial public release. 179 | 180 | -------------------------------------------------------------------------------- /capstone/LICENSE.TXT: -------------------------------------------------------------------------------- 1 | This is the software license for Capstone disassembly framework. 2 | Capstone has been designed & implemented by Nguyen Anh Quynh 3 | 4 | See http://www.capstone-engine.org for further information. 5 | 6 | Copyright (c) 2013, COSEINC. 7 | All rights reserved. 8 | 9 | Redistribution and use in source and binary forms, with or without 10 | modification, are permitted provided that the following conditions are met: 11 | 12 | * Redistributions of source code must retain the above copyright notice, 13 | this list of conditions and the following disclaimer. 14 | * Redistributions in binary form must reproduce the above copyright notice, 15 | this list of conditions and the following disclaimer in the documentation 16 | and/or other materials provided with the distribution. 17 | * Neither the name of the developer(s) nor the names of its 18 | contributors may be used to endorse or promote products derived from this 19 | software without specific prior written permission. 20 | 21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 | POSSIBILITY OF SUCH DAMAGE. 32 | -------------------------------------------------------------------------------- /capstone/LICENSE_LLVM.TXT: -------------------------------------------------------------------------------- 1 | ============================================================================== 2 | LLVM Release License 3 | ============================================================================== 4 | University of Illinois/NCSA 5 | Open Source License 6 | 7 | Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign. 8 | All rights reserved. 9 | 10 | Developed by: 11 | 12 | LLVM Team 13 | 14 | University of Illinois at Urbana-Champaign 15 | 16 | http://llvm.org 17 | 18 | Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | this software and associated documentation files (the "Software"), to deal with 20 | the Software without restriction, including without limitation the rights to 21 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | of the Software, and to permit persons to whom the Software is furnished to do 23 | so, subject to the following conditions: 24 | 25 | * Redistributions of source code must retain the above copyright notice, 26 | this list of conditions and the following disclaimers. 27 | 28 | * Redistributions in binary form must reproduce the above copyright notice, 29 | this list of conditions and the following disclaimers in the 30 | documentation and/or other materials provided with the distribution. 31 | 32 | * Neither the names of the LLVM Team, University of Illinois at 33 | Urbana-Champaign, nor the names of its contributors may be used to 34 | endorse or promote products derived from this Software without specific 35 | prior written permission. 36 | 37 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 38 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 39 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 40 | CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 41 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 42 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE 43 | SOFTWARE. 44 | 45 | ============================================================================== 46 | Copyrights and Licenses for Third Party Software Distributed with LLVM: 47 | ============================================================================== 48 | The LLVM software contains code written by third parties. Such software will 49 | have its own individual LICENSE.TXT file in the directory in which it appears. 50 | This file will describe the copyrights, license, and restrictions which apply 51 | to that code. 52 | 53 | The disclaimer of warranty in the University of Illinois Open Source License 54 | applies to all code in the LLVM Distribution, and nothing in any of the 55 | other licenses gives permission to use the names of the LLVM Team or the 56 | University of Illinois to endorse or promote products derived from this 57 | Software. 58 | 59 | The following pieces of software have additional or alternate copyrights, 60 | licenses, and/or restrictions: 61 | 62 | Program Directory 63 | ------- --------- 64 | Autoconf llvm/autoconf 65 | llvm/projects/ModuleMaker/autoconf 66 | llvm/projects/sample/autoconf 67 | Google Test llvm/utils/unittest/googletest 68 | OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} 69 | pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} 70 | ARM contributions llvm/lib/Target/ARM/LICENSE.TXT 71 | md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h 72 | -------------------------------------------------------------------------------- /capstone/README: -------------------------------------------------------------------------------- 1 | Capstone is a disassembly framework with the target of becoming the ultimate 2 | disasm engine for binary analysis and reversing in the security community. 3 | 4 | Created by Nguyen Anh Quynh, then developed and maintained by a small community, 5 | Capstone offers some unparalleled features: 6 | 7 | - Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc, 8 | SystemZ, XCore and X86. 9 | 10 | - Having clean/simple/lightweight/intuitive architecture-neutral API. 11 | 12 | - Provide details on disassembled instruction (called “decomposer” by others). 13 | 14 | - Provide semantics of the disassembled instruction, such as list of implicit 15 | registers read & written. 16 | 17 | - Implemented in pure C language, with lightweight wrappers for C++, C#, Go, 18 | Java, NodeJS, Ocaml, Python, Ruby & Vala ready (available in main code, 19 | or provided externally by the community). 20 | 21 | - Native support for all popular platforms: Windows, Mac OSX, iOS, Android, 22 | Linux, *BSD, Solaris, etc. 23 | 24 | - Thread-safe by design. 25 | 26 | - Special support for embedding into firmware or OS kernel. 27 | 28 | - Distributed under the open source BSD license. 29 | 30 | Further information is available at http://www.capstone-engine.org 31 | 32 | 33 | [Compile] 34 | 35 | See COMPILE.TXT file for how to compile and install Capstone. 36 | 37 | 38 | [Hack] 39 | 40 | See HACK.TXT file for the structuture of the source code. 41 | 42 | 43 | [License] 44 | 45 | This project is released under the BSD license. If you redistribute the binary 46 | or source code of Capstone, please attach file LICENSE.TXT with your products. 47 | -------------------------------------------------------------------------------- /capstone/RELEASE_NOTES: -------------------------------------------------------------------------------- 1 | Version 2.1.2 is a stable release that fixes some bugs deep in the core. 2 | There is no update to any architectures or bindings, so older bindings 3 | of release 2.1 can be used with this version 2.1.2 just fine. 4 | 5 | For this reason, after upgrading to 2.1.2, users do NOT need to upgrade 6 | their bindings from release 2.1. 7 | 8 | -------------------------------------------------------------------------------- /capstone/include/arm.h: -------------------------------------------------------------------------------- 1 | #ifndef CAPSTONE_ARM_H 2 | #define CAPSTONE_ARM_H 3 | 4 | /* Capstone Disassembly Engine */ 5 | /* By Nguyen Anh Quynh , 2013-2014 */ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include "platform.h" 13 | 14 | #ifdef _MSC_VER 15 | #pragma warning(disable:4201) 16 | #endif 17 | 18 | //> ARM shift type 19 | typedef enum arm_shifter { 20 | ARM_SFT_INVALID = 0, 21 | ARM_SFT_ASR, // shift with immediate const 22 | ARM_SFT_LSL, // shift with immediate const 23 | ARM_SFT_LSR, // shift with immediate const 24 | ARM_SFT_ROR, // shift with immediate const 25 | ARM_SFT_RRX, // shift with immediate const 26 | ARM_SFT_ASR_REG, // shift with register 27 | ARM_SFT_LSL_REG, // shift with register 28 | ARM_SFT_LSR_REG, // shift with register 29 | ARM_SFT_ROR_REG, // shift with register 30 | ARM_SFT_RRX_REG, // shift with register 31 | } arm_shifter; 32 | 33 | //> ARM condition code 34 | typedef enum arm_cc { 35 | ARM_CC_INVALID = 0, 36 | ARM_CC_EQ, // Equal Equal 37 | ARM_CC_NE, // Not equal Not equal, or unordered 38 | ARM_CC_HS, // Carry set >, ==, or unordered 39 | ARM_CC_LO, // Carry clear Less than 40 | ARM_CC_MI, // Minus, negative Less than 41 | ARM_CC_PL, // Plus, positive or zero >, ==, or unordered 42 | ARM_CC_VS, // Overflow Unordered 43 | ARM_CC_VC, // No overflow Not unordered 44 | ARM_CC_HI, // Unsigned higher Greater than, or unordered 45 | ARM_CC_LS, // Unsigned lower or same Less than or equal 46 | ARM_CC_GE, // Greater than or equal Greater than or equal 47 | ARM_CC_LT, // Less than Less than, or unordered 48 | ARM_CC_GT, // Greater than Greater than 49 | ARM_CC_LE, // Less than or equal <, ==, or unordered 50 | ARM_CC_AL // Always (unconditional) Always (unconditional) 51 | } arm_cc; 52 | 53 | typedef enum arm_sysreg { 54 | //> Special registers for MSR 55 | ARM_SYSREG_INVALID = 0, 56 | 57 | // SPSR* registers can be OR combined 58 | ARM_SYSREG_SPSR_C = 1, 59 | ARM_SYSREG_SPSR_X = 2, 60 | ARM_SYSREG_SPSR_S = 4, 61 | ARM_SYSREG_SPSR_F = 8, 62 | 63 | // CPSR* registers can be OR combined 64 | ARM_SYSREG_CPSR_C = 16, 65 | ARM_SYSREG_CPSR_X = 32, 66 | ARM_SYSREG_CPSR_S = 64, 67 | ARM_SYSREG_CPSR_F = 128, 68 | 69 | // independent registers 70 | ARM_SYSREG_APSR = 256, 71 | ARM_SYSREG_APSR_G, 72 | ARM_SYSREG_APSR_NZCVQ, 73 | ARM_SYSREG_APSR_NZCVQG, 74 | 75 | ARM_SYSREG_IAPSR, 76 | ARM_SYSREG_IAPSR_G, 77 | ARM_SYSREG_IAPSR_NZCVQG, 78 | 79 | ARM_SYSREG_EAPSR, 80 | ARM_SYSREG_EAPSR_G, 81 | ARM_SYSREG_EAPSR_NZCVQG, 82 | 83 | ARM_SYSREG_XPSR, 84 | ARM_SYSREG_XPSR_G, 85 | ARM_SYSREG_XPSR_NZCVQG, 86 | 87 | ARM_SYSREG_IPSR, 88 | ARM_SYSREG_EPSR, 89 | ARM_SYSREG_IEPSR, 90 | 91 | ARM_SYSREG_MSP, 92 | ARM_SYSREG_PSP, 93 | ARM_SYSREG_PRIMASK, 94 | ARM_SYSREG_BASEPRI, 95 | ARM_SYSREG_BASEPRI_MAX, 96 | ARM_SYSREG_FAULTMASK, 97 | ARM_SYSREG_CONTROL, 98 | } arm_sysreg; 99 | 100 | //> Operand type for instruction's operands 101 | typedef enum arm_op_type { 102 | ARM_OP_INVALID = 0, // Uninitialized. 103 | ARM_OP_REG, // Register operand. 104 | ARM_OP_CIMM, // C-Immediate (coprocessor registers) 105 | ARM_OP_PIMM, // P-Immediate (coprocessor registers) 106 | ARM_OP_IMM, // Immediate operand. 107 | ARM_OP_FP, // Floating-Point immediate operand. 108 | ARM_OP_MEM, // Memory operand 109 | ARM_OP_SETEND, // operand for SETEND instruction 110 | ARM_OP_SYSREG, // MSR/MSR special register operand 111 | } arm_op_type; 112 | 113 | //> Operand type for SETEND instruction 114 | typedef enum arm_setend_type { 115 | ARM_SETEND_INVALID = 0, // Uninitialized. 116 | ARM_SETEND_BE, // BE operand. 117 | ARM_SETEND_LE, // LE operand 118 | } arm_setend_type; 119 | 120 | typedef enum arm_cpsmode_type { 121 | ARM_CPSMODE_INVALID = 0, 122 | ARM_CPSMODE_IE = 2, 123 | ARM_CPSMODE_ID = 3 124 | } arm_cpsmode_type; 125 | 126 | //> Operand type for SETEND instruction 127 | typedef enum arm_cpsflag_type { 128 | ARM_CPSFLAG_INVALID = 0, 129 | ARM_CPSFLAG_F = 1, 130 | ARM_CPSFLAG_I = 2, 131 | ARM_CPSFLAG_A = 4, 132 | ARM_CPSFLAG_NONE = 16, // no flag 133 | } arm_cpsflag_type; 134 | 135 | //> Data type for elements of vector instructions. 136 | typedef enum arm_vectordata_type { 137 | ARM_VECTORDATA_INVALID = 0, 138 | 139 | // Integer type 140 | ARM_VECTORDATA_I8, 141 | ARM_VECTORDATA_I16, 142 | ARM_VECTORDATA_I32, 143 | ARM_VECTORDATA_I64, 144 | 145 | // Signed integer type 146 | ARM_VECTORDATA_S8, 147 | ARM_VECTORDATA_S16, 148 | ARM_VECTORDATA_S32, 149 | ARM_VECTORDATA_S64, 150 | 151 | // Unsigned integer type 152 | ARM_VECTORDATA_U8, 153 | ARM_VECTORDATA_U16, 154 | ARM_VECTORDATA_U32, 155 | ARM_VECTORDATA_U64, 156 | 157 | // Data type for VMUL/VMULL 158 | ARM_VECTORDATA_P8, 159 | 160 | // Floating type 161 | ARM_VECTORDATA_F32, 162 | ARM_VECTORDATA_F64, 163 | 164 | // Convert float <-> float 165 | ARM_VECTORDATA_F16F64, // f16.f64 166 | ARM_VECTORDATA_F64F16, // f64.f16 167 | ARM_VECTORDATA_F32F16, // f32.f16 168 | ARM_VECTORDATA_F16F32, // f32.f16 169 | ARM_VECTORDATA_F64F32, // f64.f32 170 | ARM_VECTORDATA_F32F64, // f32.f64 171 | 172 | // Convert integer <-> float 173 | ARM_VECTORDATA_S32F32, // s32.f32 174 | ARM_VECTORDATA_U32F32, // u32.f32 175 | ARM_VECTORDATA_F32S32, // f32.s32 176 | ARM_VECTORDATA_F32U32, // f32.u32 177 | ARM_VECTORDATA_F64S16, // f64.s16 178 | ARM_VECTORDATA_F32S16, // f32.s16 179 | ARM_VECTORDATA_F64S32, // f64.s32 180 | ARM_VECTORDATA_S16F64, // s16.f64 181 | ARM_VECTORDATA_S16F32, // s16.f64 182 | ARM_VECTORDATA_S32F64, // s32.f64 183 | ARM_VECTORDATA_U16F64, // u16.f64 184 | ARM_VECTORDATA_U16F32, // u16.f32 185 | ARM_VECTORDATA_U32F64, // u32.f64 186 | ARM_VECTORDATA_F64U16, // f64.u16 187 | ARM_VECTORDATA_F32U16, // f32.u16 188 | ARM_VECTORDATA_F64U32, // f64.u32 189 | } arm_vectordata_type; 190 | 191 | // Instruction's operand referring to memory 192 | // This is associated with ARM_OP_MEM operand type above 193 | typedef struct arm_op_mem { 194 | unsigned int base; // base register 195 | unsigned int index; // index register 196 | int scale; // scale for index register (can be 1, or -1) 197 | int disp; // displacement/offset value 198 | } arm_op_mem; 199 | 200 | // Instruction operand 201 | typedef struct cs_arm_op { 202 | int vector_index; // Vector Index for some vector operands (or -1 if irrelevant) 203 | struct { 204 | arm_shifter type; 205 | unsigned int value; 206 | } shift; 207 | arm_op_type type; // operand type 208 | union { 209 | unsigned int reg; // register value for REG/SYSREG operand 210 | int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand 211 | double fp; // floating point value for FP operand 212 | arm_op_mem mem; // base/index/scale/disp value for MEM operand 213 | arm_setend_type setend; // SETEND instruction's operand type 214 | }; 215 | } cs_arm_op; 216 | 217 | // Instruction structure 218 | typedef struct cs_arm { 219 | bool usermode; // User-mode registers to be loaded (for LDM/STM instructions) 220 | int vector_size; // Scalar size for vector instructions 221 | arm_vectordata_type vector_data; // Data type for elements of vector instructions 222 | arm_cpsmode_type cps_mode; // CPS mode for CPS instruction 223 | arm_cpsflag_type cps_flag; // CPS mode for CPS instruction 224 | arm_cc cc; // conditional code for this insn 225 | bool update_flags; // does this insn update flags? 226 | bool writeback; // does this insn write-back? 227 | 228 | // Number of operands of this instruction, 229 | // or 0 when instruction has no operand. 230 | uint8_t op_count; 231 | 232 | cs_arm_op operands[36]; // operands for this instruction. 233 | } cs_arm; 234 | 235 | //> ARM registers 236 | typedef enum arm_reg { 237 | ARM_REG_INVALID = 0, 238 | ARM_REG_APSR, 239 | ARM_REG_APSR_NZCV, 240 | ARM_REG_CPSR, 241 | ARM_REG_FPEXC, 242 | ARM_REG_FPINST, 243 | ARM_REG_FPSCR, 244 | ARM_REG_FPSCR_NZCV, 245 | ARM_REG_FPSID, 246 | ARM_REG_ITSTATE, 247 | ARM_REG_LR, 248 | ARM_REG_PC, 249 | ARM_REG_SP, 250 | ARM_REG_SPSR, 251 | ARM_REG_D0, 252 | ARM_REG_D1, 253 | ARM_REG_D2, 254 | ARM_REG_D3, 255 | ARM_REG_D4, 256 | ARM_REG_D5, 257 | ARM_REG_D6, 258 | ARM_REG_D7, 259 | ARM_REG_D8, 260 | ARM_REG_D9, 261 | ARM_REG_D10, 262 | ARM_REG_D11, 263 | ARM_REG_D12, 264 | ARM_REG_D13, 265 | ARM_REG_D14, 266 | ARM_REG_D15, 267 | ARM_REG_D16, 268 | ARM_REG_D17, 269 | ARM_REG_D18, 270 | ARM_REG_D19, 271 | ARM_REG_D20, 272 | ARM_REG_D21, 273 | ARM_REG_D22, 274 | ARM_REG_D23, 275 | ARM_REG_D24, 276 | ARM_REG_D25, 277 | ARM_REG_D26, 278 | ARM_REG_D27, 279 | ARM_REG_D28, 280 | ARM_REG_D29, 281 | ARM_REG_D30, 282 | ARM_REG_D31, 283 | ARM_REG_FPINST2, 284 | ARM_REG_MVFR0, 285 | ARM_REG_MVFR1, 286 | ARM_REG_MVFR2, 287 | ARM_REG_Q0, 288 | ARM_REG_Q1, 289 | ARM_REG_Q2, 290 | ARM_REG_Q3, 291 | ARM_REG_Q4, 292 | ARM_REG_Q5, 293 | ARM_REG_Q6, 294 | ARM_REG_Q7, 295 | ARM_REG_Q8, 296 | ARM_REG_Q9, 297 | ARM_REG_Q10, 298 | ARM_REG_Q11, 299 | ARM_REG_Q12, 300 | ARM_REG_Q13, 301 | ARM_REG_Q14, 302 | ARM_REG_Q15, 303 | ARM_REG_R0, 304 | ARM_REG_R1, 305 | ARM_REG_R2, 306 | ARM_REG_R3, 307 | ARM_REG_R4, 308 | ARM_REG_R5, 309 | ARM_REG_R6, 310 | ARM_REG_R7, 311 | ARM_REG_R8, 312 | ARM_REG_R9, 313 | ARM_REG_R10, 314 | ARM_REG_R11, 315 | ARM_REG_R12, 316 | ARM_REG_S0, 317 | ARM_REG_S1, 318 | ARM_REG_S2, 319 | ARM_REG_S3, 320 | ARM_REG_S4, 321 | ARM_REG_S5, 322 | ARM_REG_S6, 323 | ARM_REG_S7, 324 | ARM_REG_S8, 325 | ARM_REG_S9, 326 | ARM_REG_S10, 327 | ARM_REG_S11, 328 | ARM_REG_S12, 329 | ARM_REG_S13, 330 | ARM_REG_S14, 331 | ARM_REG_S15, 332 | ARM_REG_S16, 333 | ARM_REG_S17, 334 | ARM_REG_S18, 335 | ARM_REG_S19, 336 | ARM_REG_S20, 337 | ARM_REG_S21, 338 | ARM_REG_S22, 339 | ARM_REG_S23, 340 | ARM_REG_S24, 341 | ARM_REG_S25, 342 | ARM_REG_S26, 343 | ARM_REG_S27, 344 | ARM_REG_S28, 345 | ARM_REG_S29, 346 | ARM_REG_S30, 347 | ARM_REG_S31, 348 | 349 | ARM_REG_MAX, // <-- mark the end of the list or registers 350 | 351 | //> alias registers 352 | ARM_REG_R13 = ARM_REG_SP, 353 | ARM_REG_R14 = ARM_REG_LR, 354 | ARM_REG_R15 = ARM_REG_PC, 355 | 356 | ARM_REG_SB = ARM_REG_R9, 357 | ARM_REG_SL = ARM_REG_R10, 358 | ARM_REG_FP = ARM_REG_R11, 359 | ARM_REG_IP = ARM_REG_R12, 360 | } arm_reg; 361 | 362 | //> ARM instruction 363 | typedef enum arm_insn { 364 | ARM_INS_INVALID = 0, 365 | 366 | ARM_INS_ADC, 367 | ARM_INS_ADD, 368 | ARM_INS_ADR, 369 | ARM_INS_AESD, 370 | ARM_INS_AESE, 371 | ARM_INS_AESIMC, 372 | ARM_INS_AESMC, 373 | ARM_INS_AND, 374 | ARM_INS_BFC, 375 | ARM_INS_BFI, 376 | ARM_INS_BIC, 377 | ARM_INS_BKPT, 378 | ARM_INS_BL, 379 | ARM_INS_BLX, 380 | ARM_INS_BX, 381 | ARM_INS_BXJ, 382 | ARM_INS_B, 383 | ARM_INS_CDP, 384 | ARM_INS_CDP2, 385 | ARM_INS_CLREX, 386 | ARM_INS_CLZ, 387 | ARM_INS_CMN, 388 | ARM_INS_CMP, 389 | ARM_INS_CPS, 390 | ARM_INS_CRC32B, 391 | ARM_INS_CRC32CB, 392 | ARM_INS_CRC32CH, 393 | ARM_INS_CRC32CW, 394 | ARM_INS_CRC32H, 395 | ARM_INS_CRC32W, 396 | ARM_INS_DBG, 397 | ARM_INS_DMB, 398 | ARM_INS_DSB, 399 | ARM_INS_EOR, 400 | ARM_INS_VMOV, 401 | ARM_INS_FLDMDBX, 402 | ARM_INS_FLDMIAX, 403 | ARM_INS_VMRS, 404 | ARM_INS_FSTMDBX, 405 | ARM_INS_FSTMIAX, 406 | ARM_INS_HINT, 407 | ARM_INS_HLT, 408 | ARM_INS_ISB, 409 | ARM_INS_LDA, 410 | ARM_INS_LDAB, 411 | ARM_INS_LDAEX, 412 | ARM_INS_LDAEXB, 413 | ARM_INS_LDAEXD, 414 | ARM_INS_LDAEXH, 415 | ARM_INS_LDAH, 416 | ARM_INS_LDC2L, 417 | ARM_INS_LDC2, 418 | ARM_INS_LDCL, 419 | ARM_INS_LDC, 420 | ARM_INS_LDMDA, 421 | ARM_INS_LDMDB, 422 | ARM_INS_LDM, 423 | ARM_INS_LDMIB, 424 | ARM_INS_LDRBT, 425 | ARM_INS_LDRB, 426 | ARM_INS_LDRD, 427 | ARM_INS_LDREX, 428 | ARM_INS_LDREXB, 429 | ARM_INS_LDREXD, 430 | ARM_INS_LDREXH, 431 | ARM_INS_LDRH, 432 | ARM_INS_LDRHT, 433 | ARM_INS_LDRSB, 434 | ARM_INS_LDRSBT, 435 | ARM_INS_LDRSH, 436 | ARM_INS_LDRSHT, 437 | ARM_INS_LDRT, 438 | ARM_INS_LDR, 439 | ARM_INS_MCR, 440 | ARM_INS_MCR2, 441 | ARM_INS_MCRR, 442 | ARM_INS_MCRR2, 443 | ARM_INS_MLA, 444 | ARM_INS_MLS, 445 | ARM_INS_MOV, 446 | ARM_INS_MOVT, 447 | ARM_INS_MOVW, 448 | ARM_INS_MRC, 449 | ARM_INS_MRC2, 450 | ARM_INS_MRRC, 451 | ARM_INS_MRRC2, 452 | ARM_INS_MRS, 453 | ARM_INS_MSR, 454 | ARM_INS_MUL, 455 | ARM_INS_MVN, 456 | ARM_INS_ORR, 457 | ARM_INS_PKHBT, 458 | ARM_INS_PKHTB, 459 | ARM_INS_PLDW, 460 | ARM_INS_PLD, 461 | ARM_INS_PLI, 462 | ARM_INS_QADD, 463 | ARM_INS_QADD16, 464 | ARM_INS_QADD8, 465 | ARM_INS_QASX, 466 | ARM_INS_QDADD, 467 | ARM_INS_QDSUB, 468 | ARM_INS_QSAX, 469 | ARM_INS_QSUB, 470 | ARM_INS_QSUB16, 471 | ARM_INS_QSUB8, 472 | ARM_INS_RBIT, 473 | ARM_INS_REV, 474 | ARM_INS_REV16, 475 | ARM_INS_REVSH, 476 | ARM_INS_RFEDA, 477 | ARM_INS_RFEDB, 478 | ARM_INS_RFEIA, 479 | ARM_INS_RFEIB, 480 | ARM_INS_RSB, 481 | ARM_INS_RSC, 482 | ARM_INS_SADD16, 483 | ARM_INS_SADD8, 484 | ARM_INS_SASX, 485 | ARM_INS_SBC, 486 | ARM_INS_SBFX, 487 | ARM_INS_SDIV, 488 | ARM_INS_SEL, 489 | ARM_INS_SETEND, 490 | ARM_INS_SHA1C, 491 | ARM_INS_SHA1H, 492 | ARM_INS_SHA1M, 493 | ARM_INS_SHA1P, 494 | ARM_INS_SHA1SU0, 495 | ARM_INS_SHA1SU1, 496 | ARM_INS_SHA256H, 497 | ARM_INS_SHA256H2, 498 | ARM_INS_SHA256SU0, 499 | ARM_INS_SHA256SU1, 500 | ARM_INS_SHADD16, 501 | ARM_INS_SHADD8, 502 | ARM_INS_SHASX, 503 | ARM_INS_SHSAX, 504 | ARM_INS_SHSUB16, 505 | ARM_INS_SHSUB8, 506 | ARM_INS_SMC, 507 | ARM_INS_SMLABB, 508 | ARM_INS_SMLABT, 509 | ARM_INS_SMLAD, 510 | ARM_INS_SMLADX, 511 | ARM_INS_SMLAL, 512 | ARM_INS_SMLALBB, 513 | ARM_INS_SMLALBT, 514 | ARM_INS_SMLALD, 515 | ARM_INS_SMLALDX, 516 | ARM_INS_SMLALTB, 517 | ARM_INS_SMLALTT, 518 | ARM_INS_SMLATB, 519 | ARM_INS_SMLATT, 520 | ARM_INS_SMLAWB, 521 | ARM_INS_SMLAWT, 522 | ARM_INS_SMLSD, 523 | ARM_INS_SMLSDX, 524 | ARM_INS_SMLSLD, 525 | ARM_INS_SMLSLDX, 526 | ARM_INS_SMMLA, 527 | ARM_INS_SMMLAR, 528 | ARM_INS_SMMLS, 529 | ARM_INS_SMMLSR, 530 | ARM_INS_SMMUL, 531 | ARM_INS_SMMULR, 532 | ARM_INS_SMUAD, 533 | ARM_INS_SMUADX, 534 | ARM_INS_SMULBB, 535 | ARM_INS_SMULBT, 536 | ARM_INS_SMULL, 537 | ARM_INS_SMULTB, 538 | ARM_INS_SMULTT, 539 | ARM_INS_SMULWB, 540 | ARM_INS_SMULWT, 541 | ARM_INS_SMUSD, 542 | ARM_INS_SMUSDX, 543 | ARM_INS_SRSDA, 544 | ARM_INS_SRSDB, 545 | ARM_INS_SRSIA, 546 | ARM_INS_SRSIB, 547 | ARM_INS_SSAT, 548 | ARM_INS_SSAT16, 549 | ARM_INS_SSAX, 550 | ARM_INS_SSUB16, 551 | ARM_INS_SSUB8, 552 | ARM_INS_STC2L, 553 | ARM_INS_STC2, 554 | ARM_INS_STCL, 555 | ARM_INS_STC, 556 | ARM_INS_STL, 557 | ARM_INS_STLB, 558 | ARM_INS_STLEX, 559 | ARM_INS_STLEXB, 560 | ARM_INS_STLEXD, 561 | ARM_INS_STLEXH, 562 | ARM_INS_STLH, 563 | ARM_INS_STMDA, 564 | ARM_INS_STMDB, 565 | ARM_INS_STM, 566 | ARM_INS_STMIB, 567 | ARM_INS_STRBT, 568 | ARM_INS_STRB, 569 | ARM_INS_STRD, 570 | ARM_INS_STREX, 571 | ARM_INS_STREXB, 572 | ARM_INS_STREXD, 573 | ARM_INS_STREXH, 574 | ARM_INS_STRH, 575 | ARM_INS_STRHT, 576 | ARM_INS_STRT, 577 | ARM_INS_STR, 578 | ARM_INS_SUB, 579 | ARM_INS_SVC, 580 | ARM_INS_SWP, 581 | ARM_INS_SWPB, 582 | ARM_INS_SXTAB, 583 | ARM_INS_SXTAB16, 584 | ARM_INS_SXTAH, 585 | ARM_INS_SXTB, 586 | ARM_INS_SXTB16, 587 | ARM_INS_SXTH, 588 | ARM_INS_TEQ, 589 | ARM_INS_TRAP, 590 | ARM_INS_TST, 591 | ARM_INS_UADD16, 592 | ARM_INS_UADD8, 593 | ARM_INS_UASX, 594 | ARM_INS_UBFX, 595 | ARM_INS_UDF, 596 | ARM_INS_UDIV, 597 | ARM_INS_UHADD16, 598 | ARM_INS_UHADD8, 599 | ARM_INS_UHASX, 600 | ARM_INS_UHSAX, 601 | ARM_INS_UHSUB16, 602 | ARM_INS_UHSUB8, 603 | ARM_INS_UMAAL, 604 | ARM_INS_UMLAL, 605 | ARM_INS_UMULL, 606 | ARM_INS_UQADD16, 607 | ARM_INS_UQADD8, 608 | ARM_INS_UQASX, 609 | ARM_INS_UQSAX, 610 | ARM_INS_UQSUB16, 611 | ARM_INS_UQSUB8, 612 | ARM_INS_USAD8, 613 | ARM_INS_USADA8, 614 | ARM_INS_USAT, 615 | ARM_INS_USAT16, 616 | ARM_INS_USAX, 617 | ARM_INS_USUB16, 618 | ARM_INS_USUB8, 619 | ARM_INS_UXTAB, 620 | ARM_INS_UXTAB16, 621 | ARM_INS_UXTAH, 622 | ARM_INS_UXTB, 623 | ARM_INS_UXTB16, 624 | ARM_INS_UXTH, 625 | ARM_INS_VABAL, 626 | ARM_INS_VABA, 627 | ARM_INS_VABDL, 628 | ARM_INS_VABD, 629 | ARM_INS_VABS, 630 | ARM_INS_VACGE, 631 | ARM_INS_VACGT, 632 | ARM_INS_VADD, 633 | ARM_INS_VADDHN, 634 | ARM_INS_VADDL, 635 | ARM_INS_VADDW, 636 | ARM_INS_VAND, 637 | ARM_INS_VBIC, 638 | ARM_INS_VBIF, 639 | ARM_INS_VBIT, 640 | ARM_INS_VBSL, 641 | ARM_INS_VCEQ, 642 | ARM_INS_VCGE, 643 | ARM_INS_VCGT, 644 | ARM_INS_VCLE, 645 | ARM_INS_VCLS, 646 | ARM_INS_VCLT, 647 | ARM_INS_VCLZ, 648 | ARM_INS_VCMP, 649 | ARM_INS_VCMPE, 650 | ARM_INS_VCNT, 651 | ARM_INS_VCVTA, 652 | ARM_INS_VCVTB, 653 | ARM_INS_VCVT, 654 | ARM_INS_VCVTM, 655 | ARM_INS_VCVTN, 656 | ARM_INS_VCVTP, 657 | ARM_INS_VCVTT, 658 | ARM_INS_VDIV, 659 | ARM_INS_VDUP, 660 | ARM_INS_VEOR, 661 | ARM_INS_VEXT, 662 | ARM_INS_VFMA, 663 | ARM_INS_VFMS, 664 | ARM_INS_VFNMA, 665 | ARM_INS_VFNMS, 666 | ARM_INS_VHADD, 667 | ARM_INS_VHSUB, 668 | ARM_INS_VLD1, 669 | ARM_INS_VLD2, 670 | ARM_INS_VLD3, 671 | ARM_INS_VLD4, 672 | ARM_INS_VLDMDB, 673 | ARM_INS_VLDMIA, 674 | ARM_INS_VLDR, 675 | ARM_INS_VMAXNM, 676 | ARM_INS_VMAX, 677 | ARM_INS_VMINNM, 678 | ARM_INS_VMIN, 679 | ARM_INS_VMLA, 680 | ARM_INS_VMLAL, 681 | ARM_INS_VMLS, 682 | ARM_INS_VMLSL, 683 | ARM_INS_VMOVL, 684 | ARM_INS_VMOVN, 685 | ARM_INS_VMSR, 686 | ARM_INS_VMUL, 687 | ARM_INS_VMULL, 688 | ARM_INS_VMVN, 689 | ARM_INS_VNEG, 690 | ARM_INS_VNMLA, 691 | ARM_INS_VNMLS, 692 | ARM_INS_VNMUL, 693 | ARM_INS_VORN, 694 | ARM_INS_VORR, 695 | ARM_INS_VPADAL, 696 | ARM_INS_VPADDL, 697 | ARM_INS_VPADD, 698 | ARM_INS_VPMAX, 699 | ARM_INS_VPMIN, 700 | ARM_INS_VQABS, 701 | ARM_INS_VQADD, 702 | ARM_INS_VQDMLAL, 703 | ARM_INS_VQDMLSL, 704 | ARM_INS_VQDMULH, 705 | ARM_INS_VQDMULL, 706 | ARM_INS_VQMOVUN, 707 | ARM_INS_VQMOVN, 708 | ARM_INS_VQNEG, 709 | ARM_INS_VQRDMULH, 710 | ARM_INS_VQRSHL, 711 | ARM_INS_VQRSHRN, 712 | ARM_INS_VQRSHRUN, 713 | ARM_INS_VQSHL, 714 | ARM_INS_VQSHLU, 715 | ARM_INS_VQSHRN, 716 | ARM_INS_VQSHRUN, 717 | ARM_INS_VQSUB, 718 | ARM_INS_VRADDHN, 719 | ARM_INS_VRECPE, 720 | ARM_INS_VRECPS, 721 | ARM_INS_VREV16, 722 | ARM_INS_VREV32, 723 | ARM_INS_VREV64, 724 | ARM_INS_VRHADD, 725 | ARM_INS_VRINTA, 726 | ARM_INS_VRINTM, 727 | ARM_INS_VRINTN, 728 | ARM_INS_VRINTP, 729 | ARM_INS_VRINTR, 730 | ARM_INS_VRINTX, 731 | ARM_INS_VRINTZ, 732 | ARM_INS_VRSHL, 733 | ARM_INS_VRSHRN, 734 | ARM_INS_VRSHR, 735 | ARM_INS_VRSQRTE, 736 | ARM_INS_VRSQRTS, 737 | ARM_INS_VRSRA, 738 | ARM_INS_VRSUBHN, 739 | ARM_INS_VSELEQ, 740 | ARM_INS_VSELGE, 741 | ARM_INS_VSELGT, 742 | ARM_INS_VSELVS, 743 | ARM_INS_VSHLL, 744 | ARM_INS_VSHL, 745 | ARM_INS_VSHRN, 746 | ARM_INS_VSHR, 747 | ARM_INS_VSLI, 748 | ARM_INS_VSQRT, 749 | ARM_INS_VSRA, 750 | ARM_INS_VSRI, 751 | ARM_INS_VST1, 752 | ARM_INS_VST2, 753 | ARM_INS_VST3, 754 | ARM_INS_VST4, 755 | ARM_INS_VSTMDB, 756 | ARM_INS_VSTMIA, 757 | ARM_INS_VSTR, 758 | ARM_INS_VSUB, 759 | ARM_INS_VSUBHN, 760 | ARM_INS_VSUBL, 761 | ARM_INS_VSUBW, 762 | ARM_INS_VSWP, 763 | ARM_INS_VTBL, 764 | ARM_INS_VTBX, 765 | ARM_INS_VCVTR, 766 | ARM_INS_VTRN, 767 | ARM_INS_VTST, 768 | ARM_INS_VUZP, 769 | ARM_INS_VZIP, 770 | ARM_INS_ADDW, 771 | ARM_INS_ASR, 772 | ARM_INS_DCPS1, 773 | ARM_INS_DCPS2, 774 | ARM_INS_DCPS3, 775 | ARM_INS_IT, 776 | ARM_INS_LSL, 777 | ARM_INS_LSR, 778 | ARM_INS_ASRS, 779 | ARM_INS_LSRS, 780 | ARM_INS_ORN, 781 | ARM_INS_ROR, 782 | ARM_INS_RRX, 783 | ARM_INS_SUBS, 784 | ARM_INS_SUBW, 785 | ARM_INS_TBB, 786 | ARM_INS_TBH, 787 | ARM_INS_CBNZ, 788 | ARM_INS_CBZ, 789 | ARM_INS_MOVS, 790 | ARM_INS_POP, 791 | ARM_INS_PUSH, 792 | 793 | // special instructions 794 | ARM_INS_NOP, 795 | ARM_INS_YIELD, 796 | ARM_INS_WFE, 797 | ARM_INS_WFI, 798 | ARM_INS_SEV, 799 | ARM_INS_SEVL, 800 | ARM_INS_VPUSH, 801 | ARM_INS_VPOP, 802 | 803 | ARM_INS_MAX, // <-- mark the end of the list of instructions 804 | } arm_insn; 805 | 806 | //> Group of ARM instructions 807 | typedef enum arm_insn_group { 808 | ARM_GRP_INVALID = 0, 809 | ARM_GRP_CRYPTO, 810 | ARM_GRP_DATABARRIER, 811 | ARM_GRP_DIVIDE, 812 | ARM_GRP_FPARMV8, 813 | ARM_GRP_MULTPRO, 814 | ARM_GRP_NEON, 815 | ARM_GRP_T2EXTRACTPACK, 816 | ARM_GRP_THUMB2DSP, 817 | ARM_GRP_TRUSTZONE, 818 | ARM_GRP_V4T, 819 | ARM_GRP_V5T, 820 | ARM_GRP_V5TE, 821 | ARM_GRP_V6, 822 | ARM_GRP_V6T2, 823 | ARM_GRP_V7, 824 | ARM_GRP_V8, 825 | ARM_GRP_VFP2, 826 | ARM_GRP_VFP3, 827 | ARM_GRP_VFP4, 828 | ARM_GRP_ARM, 829 | ARM_GRP_MCLASS, 830 | ARM_GRP_NOTMCLASS, 831 | ARM_GRP_THUMB, 832 | ARM_GRP_THUMB1ONLY, 833 | ARM_GRP_THUMB2, 834 | ARM_GRP_PREV8, 835 | ARM_GRP_FPVMLX, 836 | ARM_GRP_MULOPS, 837 | ARM_GRP_CRC, 838 | ARM_GRP_DPVFP, 839 | ARM_GRP_V6M, 840 | 841 | ARM_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) 842 | 843 | ARM_GRP_MAX, 844 | } arm_insn_group; 845 | 846 | #ifdef __cplusplus 847 | } 848 | #endif 849 | 850 | #endif 851 | -------------------------------------------------------------------------------- /capstone/include/capstone.h: -------------------------------------------------------------------------------- 1 | #ifndef CAPSTONE_ENGINE_H 2 | #define CAPSTONE_ENGINE_H 3 | 4 | /* Capstone Disassembly Engine */ 5 | /* By Nguyen Anh Quynh , 2013-2014 */ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include 13 | #include 14 | #include 15 | 16 | #include "platform.h" 17 | 18 | #ifdef _MSC_VER 19 | #pragma warning(disable:4201) 20 | #pragma warning(disable:4100) 21 | #ifdef CAPSTONE_SHARED 22 | #define CAPSTONE_EXPORT __declspec(dllexport) 23 | #else // defined(CAPSTONE_STATIC) 24 | #define CAPSTONE_EXPORT 25 | #endif 26 | #else 27 | #define CAPSTONE_EXPORT 28 | #endif 29 | 30 | #ifdef __GNUC__ 31 | #define CAPSTONE_DEPRECATED __attribute__((deprecated)) 32 | #elif defined(_MSC_VER) 33 | #define CAPSTONE_DEPRECATED __declspec(deprecated) 34 | #else 35 | #pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler") 36 | #define CAPSTONE_DEPRECATED 37 | #endif 38 | 39 | // Capstone API version 40 | #define CS_API_MAJOR 3 41 | #define CS_API_MINOR 0 42 | 43 | // Macro to create combined version which can be compared to 44 | // result of cs_version() API. 45 | #define CS_MAKE_VERSION(major, minor) ((major << 8) + minor) 46 | 47 | // Handle using with all API 48 | typedef size_t csh; 49 | 50 | // Architecture type 51 | typedef enum cs_arch { 52 | CS_ARCH_ARM = 0, // ARM architecture (including Thumb, Thumb-2) 53 | CS_ARCH_ARM64, // ARM-64, also called AArch64 54 | CS_ARCH_MIPS, // Mips architecture 55 | CS_ARCH_X86, // X86 architecture (including x86 & x86-64) 56 | CS_ARCH_PPC, // PowerPC architecture 57 | CS_ARCH_SPARC, // Sparc architecture 58 | CS_ARCH_SYSZ, // SystemZ architecture 59 | CS_ARCH_XCORE, // XCore architecture 60 | CS_ARCH_MAX, 61 | CS_ARCH_ALL = 0xFFFF, 62 | } cs_arch; 63 | 64 | // Support value to verify diet mode of the engine. 65 | // If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled 66 | // in diet mode. 67 | #define CS_SUPPORT_DIET (CS_ARCH_ALL + 1) 68 | 69 | // Support value to verify X86 reduce mode of the engine. 70 | // If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled 71 | // in X86 reduce mode. 72 | #define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2) 73 | 74 | // Mode type 75 | typedef enum cs_mode { 76 | CS_MODE_LITTLE_ENDIAN = 0, // little endian mode (default mode) 77 | CS_MODE_ARM = 0, // 32-bit ARM 78 | CS_MODE_16 = 1 << 1, // 16-bit mode 79 | CS_MODE_32 = 1 << 2, // 32-bit mode 80 | CS_MODE_64 = 1 << 3, // 64-bit mode 81 | CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2 82 | CS_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series 83 | CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture) 84 | CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture) 85 | CS_MODE_MIPS3 = 1 << 6, // Mips III ISA 86 | CS_MODE_MIPS32R6 = 1 << 7, // Mips32r6 ISA 87 | CS_MODE_MIPSGP64 = 1 << 8, // General Purpose Registers are 64-bit wide (MIPS arch) 88 | CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture) 89 | CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode 90 | } cs_mode; 91 | 92 | typedef void* (*cs_malloc_t)(size_t size); 93 | typedef void* (*cs_calloc_t)(size_t nmemb, size_t size); 94 | typedef void* (*cs_realloc_t)(void *ptr, size_t size); 95 | typedef void (*cs_free_t)(void *ptr); 96 | typedef int (*cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap); 97 | 98 | 99 | // User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf() 100 | // By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf(). 101 | typedef struct cs_opt_mem { 102 | cs_malloc_t malloc; 103 | cs_calloc_t calloc; 104 | cs_realloc_t realloc; 105 | cs_free_t free; 106 | cs_vsnprintf_t vsnprintf; 107 | } cs_opt_mem; 108 | 109 | // Runtime option for the disassembled engine 110 | typedef enum cs_opt_type { 111 | CS_OPT_SYNTAX = 1, // Asssembly output syntax 112 | CS_OPT_DETAIL, // Break down instruction structure into details 113 | CS_OPT_MODE, // Change engine's mode at run-time 114 | CS_OPT_MEM, // User-defined dynamic memory related functions 115 | CS_OPT_SKIPDATA, // Skip data when disassembling. Then engine is in SKIPDATA mode. 116 | CS_OPT_SKIPDATA_SETUP, // Setup user-defined function for SKIPDATA option 117 | CS_OPT_INSN_CACHE_SIZE, // Set INSN_CACHE_SIZE 118 | CS_OPT_CHECKINSN, // Check instruction when disassembling. 119 | CS_OPT_CHECKINSN_SETUP, // Setup user-defined function for CHECKINSN option 120 | } cs_opt_type; 121 | 122 | // Runtime option value (associated with option type above) 123 | typedef enum cs_opt_value { 124 | CS_OPT_OFF = 0, // Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. 125 | CS_OPT_ON = 3, // Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). 126 | CS_OPT_SYNTAX_DEFAULT = 0, // Default asm syntax (CS_OPT_SYNTAX). 127 | CS_OPT_SYNTAX_INTEL, // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). 128 | CS_OPT_SYNTAX_ATT, // X86 ATT asm syntax (CS_OPT_SYNTAX). 129 | CS_OPT_SYNTAX_NOREGNAME, // Prints register name with only number (CS_OPT_SYNTAX) 130 | } cs_opt_value; 131 | 132 | // User-defined callback function for SKIPDATA option 133 | // @code: the input buffer containing code to be disassembled. This is the 134 | // same buffer passed to cs_disasm(). 135 | // @code_size: size (in bytes) of the above @code buffer. 136 | // @offset: the position of the currently-examining byte in the input 137 | // buffer @code mentioned above. 138 | // @user_data: user-data passed to cs_option() via @user_data field in 139 | // cs_opt_skipdata struct below. 140 | // @return: return number of bytes to skip, or 0 to immediately stop disassembling. 141 | typedef size_t (*cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void* user_data); 142 | 143 | // User-customized setup for SKIPDATA option 144 | typedef struct cs_opt_skipdata { 145 | // Capstone considers data to skip as special "instructions". 146 | // User can specify the string for this instruction's "mnemonic" here. 147 | // By default (if @mnemonic is NULL), Capstone use ".byte". 148 | const char *mnemonic; 149 | 150 | // User-defined callback function to be called when Capstone hits data. 151 | // If the returned value from this callback is positive (>0), Capstone 152 | // will skip exactly that number of bytes & continue. Otherwise, if 153 | // the callback returns 0, Capstone stops disassembling and returns 154 | // immediately from cs_disasm() 155 | // NOTE: if this callback pointer is NULL, Capstone would skip a number 156 | // of bytes depending on architectures, as following: 157 | // Arm: 2 bytes (Thumb mode) or 4 bytes. 158 | // Arm64: 4 bytes. 159 | // Mips: 4 bytes. 160 | // PowerPC: 4 bytes. 161 | // Sparc: 4 bytes. 162 | // SystemZ: 2 bytes. 163 | // X86: 1 bytes. 164 | // XCore: 2 bytes. 165 | cs_skipdata_cb_t callback; // default value is NULL 166 | 167 | // User-defined data to be passed to @callback function pointer. 168 | void *user_data; 169 | } cs_opt_skipdata; 170 | 171 | // User-defined callback function for CHECKINSN option 172 | // @insn: the instruction to check. 173 | // @user_data: user-data passed to cs_option() via @user_data field in 174 | // cs_opt_checkinsn struct below. 175 | // @return: return true to continue, or false to immediately stop disassembling. 176 | typedef bool(*cs_checkinsn_cb_t)(const uint8_t *code, size_t code_size, size_t offset, struct cs_insn *insn, void* user_data); 177 | 178 | // User-customized setup for CHECKINSN option 179 | typedef struct cs_opt_checkinsn 180 | { 181 | cs_checkinsn_cb_t callback; // default value is NULL 182 | 183 | // User-defined data to be passed to @callback function pointer. 184 | void *user_data; 185 | } cs_opt_checkinsn; 186 | 187 | 188 | #include "arm.h" 189 | #include "arm64.h" 190 | #include "mips.h" 191 | #include "ppc.h" 192 | #include "sparc.h" 193 | #include "systemz.h" 194 | #include "x86.h" 195 | #include "xcore.h" 196 | 197 | // NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON 198 | typedef struct cs_detail { 199 | uint8_t regs_read[12]; // list of implicit registers read by this insn 200 | uint8_t regs_read_count; // number of implicit registers read by this insn 201 | 202 | uint8_t regs_write[20]; // list of implicit registers modified by this insn 203 | uint8_t regs_write_count; // number of implicit registers modified by this insn 204 | 205 | uint8_t groups[8]; // list of group this instruction belong to 206 | uint8_t groups_count; // number of groups this insn belongs to 207 | 208 | // Architecture-specific instruction info 209 | union { 210 | cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode 211 | cs_arm64 arm64; // ARM64 architecture (aka AArch64) 212 | cs_arm arm; // ARM architecture (including Thumb/Thumb2) 213 | cs_mips mips; // MIPS architecture 214 | cs_ppc ppc; // PowerPC architecture 215 | cs_sparc sparc; // Sparc architecture 216 | cs_sysz sysz; // SystemZ architecture 217 | cs_xcore xcore; // XCore architecture 218 | }; 219 | } cs_detail; 220 | 221 | // Detail information of disassembled instruction 222 | typedef struct cs_insn { 223 | // Instruction ID 224 | // Find the instruction id from header file of corresponding architecture, 225 | // such as arm.h for ARM, x86.h for X86, etc... 226 | // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF 227 | unsigned int id; 228 | 229 | // Address (EIP) of this instruction 230 | // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF 231 | uint64_t address; 232 | 233 | // Size of this instruction 234 | // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF 235 | uint16_t size; 236 | // Machine bytes of this instruction, with number of bytes indicated by @size above 237 | // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF 238 | uint8_t bytes[16]; 239 | 240 | // Ascii text of instruction mnemonic 241 | // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF 242 | char mnemonic[32]; 243 | 244 | // Ascii text of instruction operands 245 | // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF 246 | char op_str[160]; 247 | 248 | // Pointer to cs_detail. 249 | // NOTE: detail pointer is only valid (not NULL) when both requirements below are met: 250 | // (1) CS_OP_DETAIL = CS_OPT_ON 251 | // (2) If engine is in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON), then 252 | // the current instruction is not the "data" instruction (which clearly has no detail). 253 | cs_detail *detail; 254 | } cs_insn; 255 | 256 | 257 | // Calculate the offset of a disassembled instruction in its buffer, given its position 258 | // in its array of disassembled insn 259 | // NOTE: this macro works with position (>=1), not index 260 | #define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address) 261 | 262 | 263 | // All type of errors encountered by Capstone API. 264 | // These are values returned by cs_errno() 265 | typedef enum cs_err { 266 | CS_ERR_OK = 0, // No error: everything was fine 267 | CS_ERR_MEM, // Out-Of-Memory error: cs_open(), cs_disasm() 268 | CS_ERR_ARCH, // Unsupported architecture: cs_open() 269 | CS_ERR_HANDLE, // Invalid handle: cs_op_count(), cs_op_index() 270 | CS_ERR_CSH, // Invalid csh argument: cs_close(), cs_errno(), cs_option() 271 | CS_ERR_MODE, // Invalid/unsupported mode: cs_open() 272 | CS_ERR_OPTION, // Invalid/unsupported option: cs_option() 273 | CS_ERR_DETAIL, // Information is unavailable because detail option is OFF 274 | CS_ERR_MEMSETUP, // Dynamic memory management uninitialized (see CS_OPT_MEM) 275 | CS_ERR_VERSION, // Unsupported version (bindings) 276 | CS_ERR_DIET, // Access irrelevant data in "diet" engine 277 | CS_ERR_SKIPDATA, // Access irrelevant data for "data" instruction in SKIPDATA mode 278 | CS_ERR_X86_ATT, // X86 AT&T syntax is unsupported (opt-out at compile time) 279 | CS_ERR_X86_INTEL, // X86 Intel syntax is unsupported (opt-out at compile time) 280 | } cs_err; 281 | 282 | /* 283 | Return combined API version & major and minor version numbers. 284 | 285 | @major: major number of API version 286 | @minor: minor number of API version 287 | 288 | @return hexical number as (major << 8 | minor), which encodes both 289 | major & minor versions. 290 | NOTE: This returned value can be compared with version number made 291 | with macro CS_MAKE_VERSION 292 | 293 | For example, second API version would return 1 in @major, and 1 in @minor 294 | The return value would be 0x0101 295 | 296 | NOTE: if you only care about returned value, but not major and minor values, 297 | set both @major & @minor arguments to NULL. 298 | */ 299 | CAPSTONE_EXPORT 300 | unsigned int cs_version(int *major, int *minor); 301 | 302 | 303 | /* 304 | This API can be used to either ask for archs supported by this library, 305 | or check to see if the library was compile with 'diet' option (or called 306 | in 'diet' mode). 307 | 308 | To check if a particular arch is supported by this library, set @query to 309 | arch mode (CS_ARCH_* value). 310 | To verify if this library supports all the archs, use CS_ARCH_ALL. 311 | 312 | To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET. 313 | 314 | @return True if this library supports the given arch, or in 'diet' mode. 315 | */ 316 | CAPSTONE_EXPORT 317 | bool cs_support(int query); 318 | 319 | /* 320 | Initialize CS handle: this must be done before any usage of CS. 321 | 322 | @arch: architecture type (CS_ARCH_*) 323 | @mode: hardware mode. This is combined of CS_MODE_* 324 | @handle: pointer to handle, which will be updated at return time 325 | 326 | @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum 327 | for detailed error). 328 | */ 329 | CAPSTONE_EXPORT 330 | cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle); 331 | 332 | /* 333 | Close CS handle: MUST do to release the handle when it is not used anymore. 334 | NOTE: this must be only called when there is no longer usage of Capstone, 335 | not even access to cs_insn array. The reason is the this API releases some 336 | cached memory, thus access to any Capstone API after cs_close() might crash 337 | your application. 338 | 339 | In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0). 340 | 341 | @handle: pointer to a handle returned by cs_open() 342 | 343 | @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum 344 | for detailed error). 345 | */ 346 | CAPSTONE_EXPORT 347 | cs_err cs_close(csh *handle); 348 | 349 | /* 350 | Set option for disassembling engine at runtime 351 | 352 | @handle: handle returned by cs_open() 353 | @type: type of option to be set 354 | @value: option value corresponding with @type 355 | 356 | @return CS_ERR_OK on success, or other value on failure. 357 | Refer to cs_err enum for detailed error. 358 | 359 | NOTE: in the case of CS_OPT_MEM, handle's value can be anything, 360 | so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called 361 | even before cs_open() 362 | */ 363 | CAPSTONE_EXPORT 364 | cs_err cs_option(csh handle, cs_opt_type type, size_t value); 365 | 366 | /* 367 | Report the last error number when some API function fail. 368 | Like glibc's errno, cs_errno might not retain its old value once accessed. 369 | 370 | @handle: handle returned by cs_open() 371 | 372 | @return: error code of cs_err enum type (CS_ERR_*, see above) 373 | */ 374 | CAPSTONE_EXPORT 375 | cs_err cs_errno(csh handle); 376 | 377 | 378 | /* 379 | Return a string describing given error code. 380 | 381 | @code: error code (see CS_ERR_* above) 382 | 383 | @return: returns a pointer to a string that describes the error code 384 | passed in the argument @code 385 | */ 386 | CAPSTONE_EXPORT 387 | const char *cs_strerror(cs_err code); 388 | 389 | /* 390 | Dynamicly allocate memory to contain disasm insn 391 | Disassembled instructions will be put into @*insn 392 | 393 | NOTE 1: this API will automatically determine memory needed to contain 394 | output disassembled instructions in @insn. 395 | NOTE 2: caller must free() the allocated memory itself to avoid memory leaking 396 | 397 | @handle: handle returned by cs_open() 398 | @code: buffer containing raw binary code to be disassembled 399 | @code_size: size of above code 400 | @address: address of the first insn in given raw code buffer 401 | @insn: array of insn filled in by this function 402 | NOTE: @insn will be allocated by this function, and should be freed 403 | with cs_free() API. 404 | @count: number of instrutions to be disassembled, or 0 to get all of them 405 | @return: the number of succesfully disassembled instructions, 406 | or 0 if this function failed to disassemble the given code 407 | 408 | On failure, call cs_errno() for error code. 409 | */ 410 | CAPSTONE_EXPORT 411 | size_t cs_disasm(csh handle, 412 | const uint8_t *code, size_t code_size, 413 | uint64_t address, 414 | size_t count, 415 | cs_insn **insn); 416 | 417 | /* Deprecated function - to be retired in the next version! 418 | Use cs_disasm() instead of cs_disasm_ex() 419 | */ 420 | CAPSTONE_EXPORT 421 | CAPSTONE_DEPRECATED 422 | size_t cs_disasm_ex(csh handle, 423 | const uint8_t *code, size_t code_size, 424 | uint64_t address, 425 | size_t count, 426 | cs_insn **insn); 427 | /* 428 | Free memory allocated in @insn by cs_disasm() 429 | 430 | @insn: pointer returned by @insn argument in cs_disasm() 431 | @count: number of cs_insn structures returned by cs_disasm() 432 | */ 433 | CAPSTONE_EXPORT 434 | void cs_free(cs_insn *insn, size_t count); 435 | 436 | /* 437 | Return friendly name of regiser in a string. 438 | Find the instruction id from header file of corresponding architecture (arm.h for ARM, 439 | x86.h for X86, ...) 440 | 441 | WARN: when in 'diet' mode, this API is irrelevant because engine does not 442 | store register name. 443 | 444 | @handle: handle returned by cs_open() 445 | @reg_id: register id 446 | @return: string name of the register, or NULL if @reg_id is invalid. 447 | */ 448 | CAPSTONE_EXPORT 449 | const char *cs_reg_name(csh handle, unsigned int reg_id); 450 | 451 | /* 452 | Return friendly name of an instruction in a string. 453 | Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 454 | 455 | WARN: when in 'diet' mode, this API is irrelevant because the engine does not 456 | store instruction name. 457 | 458 | @handle: handle returned by cs_open() 459 | @insn_id: instruction id 460 | 461 | @return: string name of the instruction, or NULL if @insn_id is invalid. 462 | */ 463 | CAPSTONE_EXPORT 464 | const char *cs_insn_name(csh handle, unsigned int insn_id); 465 | 466 | /* 467 | Return friendly name of a group id (that an instruction can belong to) 468 | Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 469 | 470 | WARN: when in 'diet' mode, this API is irrelevant because the engine does not 471 | store group name. 472 | 473 | @handle: handle returned by cs_open() 474 | @group_id: group id 475 | 476 | @return: string name of the group, or NULL if @group_id is invalid. 477 | */ 478 | CAPSTONE_EXPORT 479 | const char *cs_group_name(csh handle, unsigned int insn_id); 480 | 481 | /* 482 | Check if a disassembled instruction belong to a particular group. 483 | Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 484 | Internally, this simply verifies if @group_id matches any member of insn->groups array. 485 | 486 | NOTE: this API is only valid when detail option is ON (which is OFF by default). 487 | 488 | WARN: when in 'diet' mode, this API is irrelevant because the engine does not 489 | update @groups array. 490 | 491 | @handle: handle returned by cs_open() 492 | @insn: disassembled instruction structure received from cs_disasm() or cs_disasm() 493 | @group_id: group that you want to check if this instruction belong to. 494 | 495 | @return: true if this instruction indeed belongs to aboved group, or false otherwise. 496 | */ 497 | CAPSTONE_EXPORT 498 | bool cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id); 499 | 500 | /* 501 | Check if a disassembled instruction IMPLICITLY used a particular register. 502 | Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 503 | Internally, this simply verifies if @reg_id matches any member of insn->regs_read array. 504 | 505 | NOTE: this API is only valid when detail option is ON (which is OFF by default) 506 | 507 | WARN: when in 'diet' mode, this API is irrelevant because the engine does not 508 | update @regs_read array. 509 | 510 | @insn: disassembled instruction structure received from cs_disasm() or cs_disasm() 511 | @reg_id: register that you want to check if this instruction used it. 512 | 513 | @return: true if this instruction indeed implicitly used aboved register, or false otherwise. 514 | */ 515 | CAPSTONE_EXPORT 516 | bool cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id); 517 | 518 | /* 519 | Check if a disassembled instruction IMPLICITLY modified a particular register. 520 | Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 521 | Internally, this simply verifies if @reg_id matches any member of insn->regs_write array. 522 | 523 | NOTE: this API is only valid when detail option is ON (which is OFF by default) 524 | 525 | WARN: when in 'diet' mode, this API is irrelevant because the engine does not 526 | update @regs_write array. 527 | 528 | @insn: disassembled instruction structure received from cs_disasm() or cs_disasm() 529 | @reg_id: register that you want to check if this instruction modified it. 530 | 531 | @return: true if this instruction indeed implicitly modified aboved register, or false otherwise. 532 | */ 533 | CAPSTONE_EXPORT 534 | bool cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id); 535 | 536 | /* 537 | Count the number of operands of a given type. 538 | Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 539 | 540 | NOTE: this API is only valid when detail option is ON (which is OFF by default) 541 | 542 | @handle: handle returned by cs_open() 543 | @insn: disassembled instruction structure received from cs_disasm() or cs_disasm() 544 | @op_type: Operand type to be found. 545 | 546 | @return: number of operands of given type @op_type in instruction @insn, 547 | or -1 on failure. 548 | */ 549 | CAPSTONE_EXPORT 550 | int cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type); 551 | 552 | /* 553 | Retrieve the position of operand of given type in .operands[] array. 554 | Later, the operand can be accessed using the returned position. 555 | Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) 556 | 557 | NOTE: this API is only valid when detail option is ON (which is OFF by default) 558 | 559 | @handle: handle returned by cs_open() 560 | @insn: disassembled instruction structure received from cs_disasm() or cs_disasm() 561 | @op_type: Operand type to be found. 562 | @position: position of the operand to be found. This must be in the range 563 | [1, cs_op_count(handle, insn, op_type)] 564 | 565 | @return: index of operand of given type @op_type in .operands[] array 566 | in instruction @insn, or -1 on failure. 567 | */ 568 | CAPSTONE_EXPORT 569 | int cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, 570 | unsigned int position); 571 | 572 | #ifdef __cplusplus 573 | } 574 | #endif 575 | 576 | #endif 577 | -------------------------------------------------------------------------------- /capstone/include/mips.h: -------------------------------------------------------------------------------- 1 | #ifndef CAPSTONE_MIPS_H 2 | #define CAPSTONE_MIPS_H 3 | 4 | /* Capstone Disassembly Engine */ 5 | /* By Nguyen Anh Quynh , 2013-2014 */ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include "platform.h" 13 | 14 | // GCC MIPS toolchain has a default macro called "mips" which breaks 15 | // compilation 16 | #undef mips 17 | 18 | #ifdef _MSC_VER 19 | #pragma warning(disable:4201) 20 | #endif 21 | 22 | //> Operand type for instruction's operands 23 | typedef enum mips_op_type { 24 | MIPS_OP_INVALID = 0, // Uninitialized. 25 | MIPS_OP_REG, // Register operand. 26 | MIPS_OP_IMM, // Immediate operand. 27 | MIPS_OP_MEM, // Memory operand 28 | } mips_op_type; 29 | 30 | // Instruction's operand referring to memory 31 | // This is associated with MIPS_OP_MEM operand type above 32 | typedef struct mips_op_mem { 33 | unsigned int base; // base register 34 | int64_t disp; // displacement/offset value 35 | } mips_op_mem; 36 | 37 | // Instruction operand 38 | typedef struct cs_mips_op { 39 | mips_op_type type; // operand type 40 | union { 41 | unsigned int reg; // register value for REG operand 42 | int64_t imm; // immediate value for IMM operand 43 | mips_op_mem mem; // base/index/scale/disp value for MEM operand 44 | }; 45 | } cs_mips_op; 46 | 47 | // Instruction structure 48 | typedef struct cs_mips { 49 | // Number of operands of this instruction, 50 | // or 0 when instruction has no operand. 51 | uint8_t op_count; 52 | cs_mips_op operands[8]; // operands for this instruction. 53 | } cs_mips; 54 | 55 | //> MIPS registers 56 | typedef enum mips_reg { 57 | MIPS_REG_INVALID = 0, 58 | // General purpose registers 59 | MIPS_REG_0, 60 | MIPS_REG_1, 61 | MIPS_REG_2, 62 | MIPS_REG_3, 63 | MIPS_REG_4, 64 | MIPS_REG_5, 65 | MIPS_REG_6, 66 | MIPS_REG_7, 67 | MIPS_REG_8, 68 | MIPS_REG_9, 69 | MIPS_REG_10, 70 | MIPS_REG_11, 71 | MIPS_REG_12, 72 | MIPS_REG_13, 73 | MIPS_REG_14, 74 | MIPS_REG_15, 75 | MIPS_REG_16, 76 | MIPS_REG_17, 77 | MIPS_REG_18, 78 | MIPS_REG_19, 79 | MIPS_REG_20, 80 | MIPS_REG_21, 81 | MIPS_REG_22, 82 | MIPS_REG_23, 83 | MIPS_REG_24, 84 | MIPS_REG_25, 85 | MIPS_REG_26, 86 | MIPS_REG_27, 87 | MIPS_REG_28, 88 | MIPS_REG_29, 89 | MIPS_REG_30, 90 | MIPS_REG_31, 91 | 92 | // DSP registers 93 | MIPS_REG_DSPCCOND, 94 | MIPS_REG_DSPCARRY, 95 | MIPS_REG_DSPEFI, 96 | MIPS_REG_DSPOUTFLAG, 97 | MIPS_REG_DSPOUTFLAG16_19, 98 | MIPS_REG_DSPOUTFLAG20, 99 | MIPS_REG_DSPOUTFLAG21, 100 | MIPS_REG_DSPOUTFLAG22, 101 | MIPS_REG_DSPOUTFLAG23, 102 | MIPS_REG_DSPPOS, 103 | MIPS_REG_DSPSCOUNT, 104 | 105 | // ACC registers 106 | MIPS_REG_AC0, 107 | MIPS_REG_AC1, 108 | MIPS_REG_AC2, 109 | MIPS_REG_AC3, 110 | 111 | // FPU registers 112 | MIPS_REG_F0, 113 | MIPS_REG_F1, 114 | MIPS_REG_F2, 115 | MIPS_REG_F3, 116 | MIPS_REG_F4, 117 | MIPS_REG_F5, 118 | MIPS_REG_F6, 119 | MIPS_REG_F7, 120 | MIPS_REG_F8, 121 | MIPS_REG_F9, 122 | MIPS_REG_F10, 123 | MIPS_REG_F11, 124 | MIPS_REG_F12, 125 | MIPS_REG_F13, 126 | MIPS_REG_F14, 127 | MIPS_REG_F15, 128 | MIPS_REG_F16, 129 | MIPS_REG_F17, 130 | MIPS_REG_F18, 131 | MIPS_REG_F19, 132 | MIPS_REG_F20, 133 | MIPS_REG_F21, 134 | MIPS_REG_F22, 135 | MIPS_REG_F23, 136 | MIPS_REG_F24, 137 | MIPS_REG_F25, 138 | MIPS_REG_F26, 139 | MIPS_REG_F27, 140 | MIPS_REG_F28, 141 | MIPS_REG_F29, 142 | MIPS_REG_F30, 143 | MIPS_REG_F31, 144 | 145 | MIPS_REG_FCC0, 146 | MIPS_REG_FCC1, 147 | MIPS_REG_FCC2, 148 | MIPS_REG_FCC3, 149 | MIPS_REG_FCC4, 150 | MIPS_REG_FCC5, 151 | MIPS_REG_FCC6, 152 | MIPS_REG_FCC7, 153 | 154 | // AFPR128 155 | MIPS_REG_W0, 156 | MIPS_REG_W1, 157 | MIPS_REG_W2, 158 | MIPS_REG_W3, 159 | MIPS_REG_W4, 160 | MIPS_REG_W5, 161 | MIPS_REG_W6, 162 | MIPS_REG_W7, 163 | MIPS_REG_W8, 164 | MIPS_REG_W9, 165 | MIPS_REG_W10, 166 | MIPS_REG_W11, 167 | MIPS_REG_W12, 168 | MIPS_REG_W13, 169 | MIPS_REG_W14, 170 | MIPS_REG_W15, 171 | MIPS_REG_W16, 172 | MIPS_REG_W17, 173 | MIPS_REG_W18, 174 | MIPS_REG_W19, 175 | MIPS_REG_W20, 176 | MIPS_REG_W21, 177 | MIPS_REG_W22, 178 | MIPS_REG_W23, 179 | MIPS_REG_W24, 180 | MIPS_REG_W25, 181 | MIPS_REG_W26, 182 | MIPS_REG_W27, 183 | MIPS_REG_W28, 184 | MIPS_REG_W29, 185 | MIPS_REG_W30, 186 | MIPS_REG_W31, 187 | 188 | MIPS_REG_HI, 189 | MIPS_REG_LO, 190 | MIPS_REG_PC, 191 | 192 | MIPS_REG_P0, 193 | MIPS_REG_P1, 194 | MIPS_REG_P2, 195 | 196 | MIPS_REG_MPL0, 197 | MIPS_REG_MPL1, 198 | MIPS_REG_MPL2, 199 | 200 | MIPS_REG_MAX, // <-- mark the end of the list or registers 201 | 202 | // alias registers 203 | MIPS_REG_ZERO = MIPS_REG_0, 204 | MIPS_REG_AT = MIPS_REG_1, 205 | MIPS_REG_V0 = MIPS_REG_2, 206 | MIPS_REG_V1 = MIPS_REG_3, 207 | MIPS_REG_A0 = MIPS_REG_4, 208 | MIPS_REG_A1 = MIPS_REG_5, 209 | MIPS_REG_A2 = MIPS_REG_6, 210 | MIPS_REG_A3 = MIPS_REG_7, 211 | MIPS_REG_T0 = MIPS_REG_8, 212 | MIPS_REG_T1 = MIPS_REG_9, 213 | MIPS_REG_T2 = MIPS_REG_10, 214 | MIPS_REG_T3 = MIPS_REG_11, 215 | MIPS_REG_T4 = MIPS_REG_12, 216 | MIPS_REG_T5 = MIPS_REG_13, 217 | MIPS_REG_T6 = MIPS_REG_14, 218 | MIPS_REG_T7 = MIPS_REG_15, 219 | MIPS_REG_S0 = MIPS_REG_16, 220 | MIPS_REG_S1 = MIPS_REG_17, 221 | MIPS_REG_S2 = MIPS_REG_18, 222 | MIPS_REG_S3 = MIPS_REG_19, 223 | MIPS_REG_S4 = MIPS_REG_20, 224 | MIPS_REG_S5 = MIPS_REG_21, 225 | MIPS_REG_S6 = MIPS_REG_22, 226 | MIPS_REG_S7 = MIPS_REG_23, 227 | MIPS_REG_T8 = MIPS_REG_24, 228 | MIPS_REG_T9 = MIPS_REG_25, 229 | MIPS_REG_K0 = MIPS_REG_26, 230 | MIPS_REG_K1 = MIPS_REG_27, 231 | MIPS_REG_GP = MIPS_REG_28, 232 | MIPS_REG_SP = MIPS_REG_29, 233 | MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, 234 | MIPS_REG_RA = MIPS_REG_31, 235 | 236 | MIPS_REG_HI0 = MIPS_REG_AC0, 237 | MIPS_REG_HI1 = MIPS_REG_AC1, 238 | MIPS_REG_HI2 = MIPS_REG_AC2, 239 | MIPS_REG_HI3 = MIPS_REG_AC3, 240 | 241 | MIPS_REG_LO0 = MIPS_REG_HI0, 242 | MIPS_REG_LO1 = MIPS_REG_HI1, 243 | MIPS_REG_LO2 = MIPS_REG_HI2, 244 | MIPS_REG_LO3 = MIPS_REG_HI3, 245 | } mips_reg; 246 | 247 | //> MIPS instruction 248 | typedef enum mips_insn { 249 | MIPS_INS_INVALID = 0, 250 | 251 | MIPS_INS_ABSQ_S, 252 | MIPS_INS_ADD, 253 | MIPS_INS_ADDIUPC, 254 | MIPS_INS_ADDQH, 255 | MIPS_INS_ADDQH_R, 256 | MIPS_INS_ADDQ, 257 | MIPS_INS_ADDQ_S, 258 | MIPS_INS_ADDSC, 259 | MIPS_INS_ADDS_A, 260 | MIPS_INS_ADDS_S, 261 | MIPS_INS_ADDS_U, 262 | MIPS_INS_ADDUH, 263 | MIPS_INS_ADDUH_R, 264 | MIPS_INS_ADDU, 265 | MIPS_INS_ADDU_S, 266 | MIPS_INS_ADDVI, 267 | MIPS_INS_ADDV, 268 | MIPS_INS_ADDWC, 269 | MIPS_INS_ADD_A, 270 | MIPS_INS_ADDI, 271 | MIPS_INS_ADDIU, 272 | MIPS_INS_ALIGN, 273 | MIPS_INS_ALUIPC, 274 | MIPS_INS_AND, 275 | MIPS_INS_ANDI, 276 | MIPS_INS_APPEND, 277 | MIPS_INS_ASUB_S, 278 | MIPS_INS_ASUB_U, 279 | MIPS_INS_AUI, 280 | MIPS_INS_AUIPC, 281 | MIPS_INS_AVER_S, 282 | MIPS_INS_AVER_U, 283 | MIPS_INS_AVE_S, 284 | MIPS_INS_AVE_U, 285 | MIPS_INS_BADDU, 286 | MIPS_INS_BAL, 287 | MIPS_INS_BALC, 288 | MIPS_INS_BALIGN, 289 | MIPS_INS_BC, 290 | MIPS_INS_BC1EQZ, 291 | MIPS_INS_BC1F, 292 | MIPS_INS_BC1NEZ, 293 | MIPS_INS_BC1T, 294 | MIPS_INS_BC2EQZ, 295 | MIPS_INS_BC2NEZ, 296 | MIPS_INS_BCLRI, 297 | MIPS_INS_BCLR, 298 | MIPS_INS_BEQ, 299 | MIPS_INS_BEQC, 300 | MIPS_INS_BEQZALC, 301 | MIPS_INS_BEQZC, 302 | MIPS_INS_BGEC, 303 | MIPS_INS_BGEUC, 304 | MIPS_INS_BGEZ, 305 | MIPS_INS_BGEZAL, 306 | MIPS_INS_BGEZALC, 307 | MIPS_INS_BGEZC, 308 | MIPS_INS_BGTZ, 309 | MIPS_INS_BGTZALC, 310 | MIPS_INS_BGTZC, 311 | MIPS_INS_BINSLI, 312 | MIPS_INS_BINSL, 313 | MIPS_INS_BINSRI, 314 | MIPS_INS_BINSR, 315 | MIPS_INS_BITREV, 316 | MIPS_INS_BITSWAP, 317 | MIPS_INS_BLEZ, 318 | MIPS_INS_BLEZALC, 319 | MIPS_INS_BLEZC, 320 | MIPS_INS_BLTC, 321 | MIPS_INS_BLTUC, 322 | MIPS_INS_BLTZ, 323 | MIPS_INS_BLTZAL, 324 | MIPS_INS_BLTZALC, 325 | MIPS_INS_BLTZC, 326 | MIPS_INS_BMNZI, 327 | MIPS_INS_BMNZ, 328 | MIPS_INS_BMZI, 329 | MIPS_INS_BMZ, 330 | MIPS_INS_BNE, 331 | MIPS_INS_BNEC, 332 | MIPS_INS_BNEGI, 333 | MIPS_INS_BNEG, 334 | MIPS_INS_BNEZALC, 335 | MIPS_INS_BNEZC, 336 | MIPS_INS_BNVC, 337 | MIPS_INS_BNZ, 338 | MIPS_INS_BOVC, 339 | MIPS_INS_BPOSGE32, 340 | MIPS_INS_BREAK, 341 | MIPS_INS_BSELI, 342 | MIPS_INS_BSEL, 343 | MIPS_INS_BSETI, 344 | MIPS_INS_BSET, 345 | MIPS_INS_BZ, 346 | MIPS_INS_BEQZ, 347 | MIPS_INS_B, 348 | MIPS_INS_BNEZ, 349 | MIPS_INS_BTEQZ, 350 | MIPS_INS_BTNEZ, 351 | MIPS_INS_CACHE, 352 | MIPS_INS_CEIL, 353 | MIPS_INS_CEQI, 354 | MIPS_INS_CEQ, 355 | MIPS_INS_CFC1, 356 | MIPS_INS_CFCMSA, 357 | MIPS_INS_CINS, 358 | MIPS_INS_CINS32, 359 | MIPS_INS_CLASS, 360 | MIPS_INS_CLEI_S, 361 | MIPS_INS_CLEI_U, 362 | MIPS_INS_CLE_S, 363 | MIPS_INS_CLE_U, 364 | MIPS_INS_CLO, 365 | MIPS_INS_CLTI_S, 366 | MIPS_INS_CLTI_U, 367 | MIPS_INS_CLT_S, 368 | MIPS_INS_CLT_U, 369 | MIPS_INS_CLZ, 370 | MIPS_INS_CMPGDU, 371 | MIPS_INS_CMPGU, 372 | MIPS_INS_CMPU, 373 | MIPS_INS_CMP, 374 | MIPS_INS_COPY_S, 375 | MIPS_INS_COPY_U, 376 | MIPS_INS_CTC1, 377 | MIPS_INS_CTCMSA, 378 | MIPS_INS_CVT, 379 | MIPS_INS_C, 380 | MIPS_INS_CMPI, 381 | MIPS_INS_DADD, 382 | MIPS_INS_DADDI, 383 | MIPS_INS_DADDIU, 384 | MIPS_INS_DADDU, 385 | MIPS_INS_DAHI, 386 | MIPS_INS_DALIGN, 387 | MIPS_INS_DATI, 388 | MIPS_INS_DAUI, 389 | MIPS_INS_DBITSWAP, 390 | MIPS_INS_DCLO, 391 | MIPS_INS_DCLZ, 392 | MIPS_INS_DDIV, 393 | MIPS_INS_DDIVU, 394 | MIPS_INS_DERET, 395 | MIPS_INS_DEXT, 396 | MIPS_INS_DEXTM, 397 | MIPS_INS_DEXTU, 398 | MIPS_INS_DI, 399 | MIPS_INS_DINS, 400 | MIPS_INS_DINSM, 401 | MIPS_INS_DINSU, 402 | MIPS_INS_DIV, 403 | MIPS_INS_DIVU, 404 | MIPS_INS_DIV_S, 405 | MIPS_INS_DIV_U, 406 | MIPS_INS_DLSA, 407 | MIPS_INS_DMFC0, 408 | MIPS_INS_DMFC1, 409 | MIPS_INS_DMFC2, 410 | MIPS_INS_DMOD, 411 | MIPS_INS_DMODU, 412 | MIPS_INS_DMTC0, 413 | MIPS_INS_DMTC1, 414 | MIPS_INS_DMTC2, 415 | MIPS_INS_DMUH, 416 | MIPS_INS_DMUHU, 417 | MIPS_INS_DMUL, 418 | MIPS_INS_DMULT, 419 | MIPS_INS_DMULTU, 420 | MIPS_INS_DMULU, 421 | MIPS_INS_DOTP_S, 422 | MIPS_INS_DOTP_U, 423 | MIPS_INS_DPADD_S, 424 | MIPS_INS_DPADD_U, 425 | MIPS_INS_DPAQX_SA, 426 | MIPS_INS_DPAQX_S, 427 | MIPS_INS_DPAQ_SA, 428 | MIPS_INS_DPAQ_S, 429 | MIPS_INS_DPAU, 430 | MIPS_INS_DPAX, 431 | MIPS_INS_DPA, 432 | MIPS_INS_DPOP, 433 | MIPS_INS_DPSQX_SA, 434 | MIPS_INS_DPSQX_S, 435 | MIPS_INS_DPSQ_SA, 436 | MIPS_INS_DPSQ_S, 437 | MIPS_INS_DPSUB_S, 438 | MIPS_INS_DPSUB_U, 439 | MIPS_INS_DPSU, 440 | MIPS_INS_DPSX, 441 | MIPS_INS_DPS, 442 | MIPS_INS_DROTR, 443 | MIPS_INS_DROTR32, 444 | MIPS_INS_DROTRV, 445 | MIPS_INS_DSBH, 446 | MIPS_INS_DSHD, 447 | MIPS_INS_DSLL, 448 | MIPS_INS_DSLL32, 449 | MIPS_INS_DSLLV, 450 | MIPS_INS_DSRA, 451 | MIPS_INS_DSRA32, 452 | MIPS_INS_DSRAV, 453 | MIPS_INS_DSRL, 454 | MIPS_INS_DSRL32, 455 | MIPS_INS_DSRLV, 456 | MIPS_INS_DSUB, 457 | MIPS_INS_DSUBU, 458 | MIPS_INS_EHB, 459 | MIPS_INS_EI, 460 | MIPS_INS_ERET, 461 | MIPS_INS_EXT, 462 | MIPS_INS_EXTP, 463 | MIPS_INS_EXTPDP, 464 | MIPS_INS_EXTPDPV, 465 | MIPS_INS_EXTPV, 466 | MIPS_INS_EXTRV_RS, 467 | MIPS_INS_EXTRV_R, 468 | MIPS_INS_EXTRV_S, 469 | MIPS_INS_EXTRV, 470 | MIPS_INS_EXTR_RS, 471 | MIPS_INS_EXTR_R, 472 | MIPS_INS_EXTR_S, 473 | MIPS_INS_EXTR, 474 | MIPS_INS_EXTS, 475 | MIPS_INS_EXTS32, 476 | MIPS_INS_ABS, 477 | MIPS_INS_FADD, 478 | MIPS_INS_FCAF, 479 | MIPS_INS_FCEQ, 480 | MIPS_INS_FCLASS, 481 | MIPS_INS_FCLE, 482 | MIPS_INS_FCLT, 483 | MIPS_INS_FCNE, 484 | MIPS_INS_FCOR, 485 | MIPS_INS_FCUEQ, 486 | MIPS_INS_FCULE, 487 | MIPS_INS_FCULT, 488 | MIPS_INS_FCUNE, 489 | MIPS_INS_FCUN, 490 | MIPS_INS_FDIV, 491 | MIPS_INS_FEXDO, 492 | MIPS_INS_FEXP2, 493 | MIPS_INS_FEXUPL, 494 | MIPS_INS_FEXUPR, 495 | MIPS_INS_FFINT_S, 496 | MIPS_INS_FFINT_U, 497 | MIPS_INS_FFQL, 498 | MIPS_INS_FFQR, 499 | MIPS_INS_FILL, 500 | MIPS_INS_FLOG2, 501 | MIPS_INS_FLOOR, 502 | MIPS_INS_FMADD, 503 | MIPS_INS_FMAX_A, 504 | MIPS_INS_FMAX, 505 | MIPS_INS_FMIN_A, 506 | MIPS_INS_FMIN, 507 | MIPS_INS_MOV, 508 | MIPS_INS_FMSUB, 509 | MIPS_INS_FMUL, 510 | MIPS_INS_MUL, 511 | MIPS_INS_NEG, 512 | MIPS_INS_FRCP, 513 | MIPS_INS_FRINT, 514 | MIPS_INS_FRSQRT, 515 | MIPS_INS_FSAF, 516 | MIPS_INS_FSEQ, 517 | MIPS_INS_FSLE, 518 | MIPS_INS_FSLT, 519 | MIPS_INS_FSNE, 520 | MIPS_INS_FSOR, 521 | MIPS_INS_FSQRT, 522 | MIPS_INS_SQRT, 523 | MIPS_INS_FSUB, 524 | MIPS_INS_SUB, 525 | MIPS_INS_FSUEQ, 526 | MIPS_INS_FSULE, 527 | MIPS_INS_FSULT, 528 | MIPS_INS_FSUNE, 529 | MIPS_INS_FSUN, 530 | MIPS_INS_FTINT_S, 531 | MIPS_INS_FTINT_U, 532 | MIPS_INS_FTQ, 533 | MIPS_INS_FTRUNC_S, 534 | MIPS_INS_FTRUNC_U, 535 | MIPS_INS_HADD_S, 536 | MIPS_INS_HADD_U, 537 | MIPS_INS_HSUB_S, 538 | MIPS_INS_HSUB_U, 539 | MIPS_INS_ILVEV, 540 | MIPS_INS_ILVL, 541 | MIPS_INS_ILVOD, 542 | MIPS_INS_ILVR, 543 | MIPS_INS_INS, 544 | MIPS_INS_INSERT, 545 | MIPS_INS_INSV, 546 | MIPS_INS_INSVE, 547 | MIPS_INS_J, 548 | MIPS_INS_JAL, 549 | MIPS_INS_JALR, 550 | MIPS_INS_JALX, 551 | MIPS_INS_JIALC, 552 | MIPS_INS_JIC, 553 | MIPS_INS_JR, 554 | MIPS_INS_JRC, 555 | MIPS_INS_JALRC, 556 | MIPS_INS_LB, 557 | MIPS_INS_LBUX, 558 | MIPS_INS_LBU, 559 | MIPS_INS_LD, 560 | MIPS_INS_LDC1, 561 | MIPS_INS_LDC2, 562 | MIPS_INS_LDC3, 563 | MIPS_INS_LDI, 564 | MIPS_INS_LDL, 565 | MIPS_INS_LDPC, 566 | MIPS_INS_LDR, 567 | MIPS_INS_LDXC1, 568 | MIPS_INS_LH, 569 | MIPS_INS_LHX, 570 | MIPS_INS_LHU, 571 | MIPS_INS_LL, 572 | MIPS_INS_LLD, 573 | MIPS_INS_LSA, 574 | MIPS_INS_LUXC1, 575 | MIPS_INS_LUI, 576 | MIPS_INS_LW, 577 | MIPS_INS_LWC1, 578 | MIPS_INS_LWC2, 579 | MIPS_INS_LWC3, 580 | MIPS_INS_LWL, 581 | MIPS_INS_LWPC, 582 | MIPS_INS_LWR, 583 | MIPS_INS_LWUPC, 584 | MIPS_INS_LWU, 585 | MIPS_INS_LWX, 586 | MIPS_INS_LWXC1, 587 | MIPS_INS_LI, 588 | MIPS_INS_MADD, 589 | MIPS_INS_MADDF, 590 | MIPS_INS_MADDR_Q, 591 | MIPS_INS_MADDU, 592 | MIPS_INS_MADDV, 593 | MIPS_INS_MADD_Q, 594 | MIPS_INS_MAQ_SA, 595 | MIPS_INS_MAQ_S, 596 | MIPS_INS_MAXA, 597 | MIPS_INS_MAXI_S, 598 | MIPS_INS_MAXI_U, 599 | MIPS_INS_MAX_A, 600 | MIPS_INS_MAX, 601 | MIPS_INS_MAX_S, 602 | MIPS_INS_MAX_U, 603 | MIPS_INS_MFC0, 604 | MIPS_INS_MFC1, 605 | MIPS_INS_MFC2, 606 | MIPS_INS_MFHC1, 607 | MIPS_INS_MFHI, 608 | MIPS_INS_MFLO, 609 | MIPS_INS_MINA, 610 | MIPS_INS_MINI_S, 611 | MIPS_INS_MINI_U, 612 | MIPS_INS_MIN_A, 613 | MIPS_INS_MIN, 614 | MIPS_INS_MIN_S, 615 | MIPS_INS_MIN_U, 616 | MIPS_INS_MOD, 617 | MIPS_INS_MODSUB, 618 | MIPS_INS_MODU, 619 | MIPS_INS_MOD_S, 620 | MIPS_INS_MOD_U, 621 | MIPS_INS_MOVE, 622 | MIPS_INS_MOVF, 623 | MIPS_INS_MOVN, 624 | MIPS_INS_MOVT, 625 | MIPS_INS_MOVZ, 626 | MIPS_INS_MSUB, 627 | MIPS_INS_MSUBF, 628 | MIPS_INS_MSUBR_Q, 629 | MIPS_INS_MSUBU, 630 | MIPS_INS_MSUBV, 631 | MIPS_INS_MSUB_Q, 632 | MIPS_INS_MTC0, 633 | MIPS_INS_MTC1, 634 | MIPS_INS_MTC2, 635 | MIPS_INS_MTHC1, 636 | MIPS_INS_MTHI, 637 | MIPS_INS_MTHLIP, 638 | MIPS_INS_MTLO, 639 | MIPS_INS_MTM0, 640 | MIPS_INS_MTM1, 641 | MIPS_INS_MTM2, 642 | MIPS_INS_MTP0, 643 | MIPS_INS_MTP1, 644 | MIPS_INS_MTP2, 645 | MIPS_INS_MUH, 646 | MIPS_INS_MUHU, 647 | MIPS_INS_MULEQ_S, 648 | MIPS_INS_MULEU_S, 649 | MIPS_INS_MULQ_RS, 650 | MIPS_INS_MULQ_S, 651 | MIPS_INS_MULR_Q, 652 | MIPS_INS_MULSAQ_S, 653 | MIPS_INS_MULSA, 654 | MIPS_INS_MULT, 655 | MIPS_INS_MULTU, 656 | MIPS_INS_MULU, 657 | MIPS_INS_MULV, 658 | MIPS_INS_MUL_Q, 659 | MIPS_INS_MUL_S, 660 | MIPS_INS_NLOC, 661 | MIPS_INS_NLZC, 662 | MIPS_INS_NMADD, 663 | MIPS_INS_NMSUB, 664 | MIPS_INS_NOR, 665 | MIPS_INS_NORI, 666 | MIPS_INS_NOT, 667 | MIPS_INS_OR, 668 | MIPS_INS_ORI, 669 | MIPS_INS_PACKRL, 670 | MIPS_INS_PAUSE, 671 | MIPS_INS_PCKEV, 672 | MIPS_INS_PCKOD, 673 | MIPS_INS_PCNT, 674 | MIPS_INS_PICK, 675 | MIPS_INS_POP, 676 | MIPS_INS_PRECEQU, 677 | MIPS_INS_PRECEQ, 678 | MIPS_INS_PRECEU, 679 | MIPS_INS_PRECRQU_S, 680 | MIPS_INS_PRECRQ, 681 | MIPS_INS_PRECRQ_RS, 682 | MIPS_INS_PRECR, 683 | MIPS_INS_PRECR_SRA, 684 | MIPS_INS_PRECR_SRA_R, 685 | MIPS_INS_PREF, 686 | MIPS_INS_PREPEND, 687 | MIPS_INS_RADDU, 688 | MIPS_INS_RDDSP, 689 | MIPS_INS_RDHWR, 690 | MIPS_INS_REPLV, 691 | MIPS_INS_REPL, 692 | MIPS_INS_RINT, 693 | MIPS_INS_ROTR, 694 | MIPS_INS_ROTRV, 695 | MIPS_INS_ROUND, 696 | MIPS_INS_SAT_S, 697 | MIPS_INS_SAT_U, 698 | MIPS_INS_SB, 699 | MIPS_INS_SC, 700 | MIPS_INS_SCD, 701 | MIPS_INS_SD, 702 | MIPS_INS_SDBBP, 703 | MIPS_INS_SDC1, 704 | MIPS_INS_SDC2, 705 | MIPS_INS_SDC3, 706 | MIPS_INS_SDL, 707 | MIPS_INS_SDR, 708 | MIPS_INS_SDXC1, 709 | MIPS_INS_SEB, 710 | MIPS_INS_SEH, 711 | MIPS_INS_SELEQZ, 712 | MIPS_INS_SELNEZ, 713 | MIPS_INS_SEL, 714 | MIPS_INS_SEQ, 715 | MIPS_INS_SEQI, 716 | MIPS_INS_SH, 717 | MIPS_INS_SHF, 718 | MIPS_INS_SHILO, 719 | MIPS_INS_SHILOV, 720 | MIPS_INS_SHLLV, 721 | MIPS_INS_SHLLV_S, 722 | MIPS_INS_SHLL, 723 | MIPS_INS_SHLL_S, 724 | MIPS_INS_SHRAV, 725 | MIPS_INS_SHRAV_R, 726 | MIPS_INS_SHRA, 727 | MIPS_INS_SHRA_R, 728 | MIPS_INS_SHRLV, 729 | MIPS_INS_SHRL, 730 | MIPS_INS_SLDI, 731 | MIPS_INS_SLD, 732 | MIPS_INS_SLL, 733 | MIPS_INS_SLLI, 734 | MIPS_INS_SLLV, 735 | MIPS_INS_SLT, 736 | MIPS_INS_SLTI, 737 | MIPS_INS_SLTIU, 738 | MIPS_INS_SLTU, 739 | MIPS_INS_SNE, 740 | MIPS_INS_SNEI, 741 | MIPS_INS_SPLATI, 742 | MIPS_INS_SPLAT, 743 | MIPS_INS_SRA, 744 | MIPS_INS_SRAI, 745 | MIPS_INS_SRARI, 746 | MIPS_INS_SRAR, 747 | MIPS_INS_SRAV, 748 | MIPS_INS_SRL, 749 | MIPS_INS_SRLI, 750 | MIPS_INS_SRLRI, 751 | MIPS_INS_SRLR, 752 | MIPS_INS_SRLV, 753 | MIPS_INS_SSNOP, 754 | MIPS_INS_ST, 755 | MIPS_INS_SUBQH, 756 | MIPS_INS_SUBQH_R, 757 | MIPS_INS_SUBQ, 758 | MIPS_INS_SUBQ_S, 759 | MIPS_INS_SUBSUS_U, 760 | MIPS_INS_SUBSUU_S, 761 | MIPS_INS_SUBS_S, 762 | MIPS_INS_SUBS_U, 763 | MIPS_INS_SUBUH, 764 | MIPS_INS_SUBUH_R, 765 | MIPS_INS_SUBU, 766 | MIPS_INS_SUBU_S, 767 | MIPS_INS_SUBVI, 768 | MIPS_INS_SUBV, 769 | MIPS_INS_SUXC1, 770 | MIPS_INS_SW, 771 | MIPS_INS_SWC1, 772 | MIPS_INS_SWC2, 773 | MIPS_INS_SWC3, 774 | MIPS_INS_SWL, 775 | MIPS_INS_SWR, 776 | MIPS_INS_SWXC1, 777 | MIPS_INS_SYNC, 778 | MIPS_INS_SYSCALL, 779 | MIPS_INS_TEQ, 780 | MIPS_INS_TEQI, 781 | MIPS_INS_TGE, 782 | MIPS_INS_TGEI, 783 | MIPS_INS_TGEIU, 784 | MIPS_INS_TGEU, 785 | MIPS_INS_TLBP, 786 | MIPS_INS_TLBR, 787 | MIPS_INS_TLBWI, 788 | MIPS_INS_TLBWR, 789 | MIPS_INS_TLT, 790 | MIPS_INS_TLTI, 791 | MIPS_INS_TLTIU, 792 | MIPS_INS_TLTU, 793 | MIPS_INS_TNE, 794 | MIPS_INS_TNEI, 795 | MIPS_INS_TRUNC, 796 | MIPS_INS_V3MULU, 797 | MIPS_INS_VMM0, 798 | MIPS_INS_VMULU, 799 | MIPS_INS_VSHF, 800 | MIPS_INS_WAIT, 801 | MIPS_INS_WRDSP, 802 | MIPS_INS_WSBH, 803 | MIPS_INS_XOR, 804 | MIPS_INS_XORI, 805 | 806 | //> some alias instructions 807 | MIPS_INS_NOP, 808 | MIPS_INS_NEGU, 809 | 810 | MIPS_INS_MAXIMUM, 811 | } mips_insn; 812 | 813 | //> Group of MIPS instructions 814 | typedef enum mips_insn_group { 815 | MIPS_GRP_INVALID = 0, 816 | 817 | MIPS_GRP_BITCOUNT, 818 | MIPS_GRP_DSP, 819 | MIPS_GRP_DSPR2, 820 | MIPS_GRP_FPIDX, 821 | MIPS_GRP_MSA, 822 | MIPS_GRP_MIPS32R2, 823 | MIPS_GRP_MIPS64, 824 | MIPS_GRP_MIPS64R2, 825 | MIPS_GRP_SEINREG, 826 | MIPS_GRP_STDENC, 827 | MIPS_GRP_SWAP, 828 | MIPS_GRP_MICROMIPS, 829 | MIPS_GRP_MIPS16MODE, 830 | MIPS_GRP_FP64BIT, 831 | MIPS_GRP_NONANSFPMATH, 832 | MIPS_GRP_NOTFP64BIT, 833 | MIPS_GRP_NOTINMICROMIPS, 834 | MIPS_GRP_NOTNACL, 835 | MIPS_GRP_NOTMIPS32R6, 836 | MIPS_GRP_NOTMIPS64R6, 837 | MIPS_GRP_CNMIPS, 838 | MIPS_GRP_MIPS32, 839 | MIPS_GRP_MIPS32R6, 840 | MIPS_GRP_MIPS64R6, 841 | MIPS_GRP_MIPS2, 842 | MIPS_GRP_MIPS3, 843 | MIPS_GRP_MIPS3_32, 844 | MIPS_GRP_MIPS3_32R2, 845 | MIPS_GRP_MIPS4_32, 846 | MIPS_GRP_MIPS4_32R2, 847 | MIPS_GRP_MIPS5_32R2, 848 | MIPS_GRP_GP32BIT, 849 | MIPS_GRP_GP64BIT, 850 | 851 | MIPS_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) 852 | 853 | MIPS_GRP_MAX, 854 | } mips_insn_group; 855 | 856 | #ifdef __cplusplus 857 | } 858 | #endif 859 | 860 | #endif 861 | -------------------------------------------------------------------------------- /capstone/include/platform.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Axel Souchet & Nguyen Anh Quynh, 2014 */ 3 | 4 | // handle C99 issue (for pre-2013 VisualStudio) 5 | #ifndef CAPSTONE_PLATFORM_H 6 | #define CAPSTONE_PLATFORM_H 7 | 8 | #if !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) 9 | // MSVC 10 | 11 | // stdbool.h 12 | #if (_MSC_VER < 1800) 13 | #ifndef __cplusplus 14 | typedef unsigned char bool; 15 | #define false 0 16 | #define true 1 17 | #endif 18 | 19 | #else 20 | // VisualStudio 2013+ -> C99 is supported 21 | #include 22 | #endif 23 | 24 | #else // not MSVC -> C99 is supported 25 | #include 26 | #endif 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /capstone/include/sparc.h: -------------------------------------------------------------------------------- 1 | #ifndef CAPSTONE_SPARC_H 2 | #define CAPSTONE_SPARC_H 3 | 4 | /* Capstone Disassembly Engine */ 5 | /* By Nguyen Anh Quynh , 2014 */ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include "platform.h" 13 | 14 | // GCC SPARC toolchain has a default macro called "sparc" which breaks 15 | // compilation 16 | #undef sparc 17 | 18 | #ifdef _MSC_VER 19 | #pragma warning(disable:4201) 20 | #endif 21 | 22 | //> Enums corresponding to Sparc condition codes, both icc's and fcc's. 23 | typedef enum sparc_cc { 24 | SPARC_CC_INVALID = 0, // invalid CC (default) 25 | //> Integer condition codes 26 | SPARC_CC_ICC_A = 8+256, // Always 27 | SPARC_CC_ICC_N = 0+256, // Never 28 | SPARC_CC_ICC_NE = 9+256, // Not Equal 29 | SPARC_CC_ICC_E = 1+256, // Equal 30 | SPARC_CC_ICC_G = 10+256, // Greater 31 | SPARC_CC_ICC_LE = 2+256, // Less or Equal 32 | SPARC_CC_ICC_GE = 11+256, // Greater or Equal 33 | SPARC_CC_ICC_L = 3+256, // Less 34 | SPARC_CC_ICC_GU = 12+256, // Greater Unsigned 35 | SPARC_CC_ICC_LEU = 4+256, // Less or Equal Unsigned 36 | SPARC_CC_ICC_CC = 13+256, // Carry Clear/Great or Equal Unsigned 37 | SPARC_CC_ICC_CS = 5+256, // Carry Set/Less Unsigned 38 | SPARC_CC_ICC_POS = 14+256, // Positive 39 | SPARC_CC_ICC_NEG = 6+256, // Negative 40 | SPARC_CC_ICC_VC = 15+256, // Overflow Clear 41 | SPARC_CC_ICC_VS = 7+256, // Overflow Set 42 | 43 | //> Floating condition codes 44 | SPARC_CC_FCC_A = 8+16+256, // Always 45 | SPARC_CC_FCC_N = 0+16+256, // Never 46 | SPARC_CC_FCC_U = 7+16+256, // Unordered 47 | SPARC_CC_FCC_G = 6+16+256, // Greater 48 | SPARC_CC_FCC_UG = 5+16+256, // Unordered or Greater 49 | SPARC_CC_FCC_L = 4+16+256, // Less 50 | SPARC_CC_FCC_UL = 3+16+256, // Unordered or Less 51 | SPARC_CC_FCC_LG = 2+16+256, // Less or Greater 52 | SPARC_CC_FCC_NE = 1+16+256, // Not Equal 53 | SPARC_CC_FCC_E = 9+16+256, // Equal 54 | SPARC_CC_FCC_UE = 10+16+256, // Unordered or Equal 55 | SPARC_CC_FCC_GE = 11+16+256, // Greater or Equal 56 | SPARC_CC_FCC_UGE = 12+16+256, // Unordered or Greater or Equal 57 | SPARC_CC_FCC_LE = 13+16+256, // Less or Equal 58 | SPARC_CC_FCC_ULE = 14+16+256, // Unordered or Less or Equal 59 | SPARC_CC_FCC_O = 15+16+256, // Ordered 60 | } sparc_cc; 61 | 62 | //> Branch hint 63 | typedef enum sparc_hint { 64 | SPARC_HINT_INVALID = 0, // no hint 65 | SPARC_HINT_A = 1 << 0, // annul delay slot instruction 66 | SPARC_HINT_PT = 1 << 1, // branch taken 67 | SPARC_HINT_PN = 1 << 2, // branch NOT taken 68 | } sparc_hint; 69 | 70 | //> Operand type for instruction's operands 71 | typedef enum sparc_op_type { 72 | SPARC_OP_INVALID = 0, // Uninitialized. 73 | SPARC_OP_REG, // Register operand. 74 | SPARC_OP_IMM, // Immediate operand. 75 | SPARC_OP_MEM, // Memory operand 76 | } sparc_op_type; 77 | 78 | // Instruction's operand referring to memory 79 | // This is associated with SPARC_OP_MEM operand type above 80 | typedef struct sparc_op_mem { 81 | uint8_t base; // base register 82 | uint8_t index; // index register 83 | int32_t disp; // displacement/offset value 84 | } sparc_op_mem; 85 | 86 | // Instruction operand 87 | typedef struct cs_sparc_op { 88 | sparc_op_type type; // operand type 89 | union { 90 | unsigned int reg; // register value for REG operand 91 | int32_t imm; // immediate value for IMM operand 92 | sparc_op_mem mem; // base/disp value for MEM operand 93 | }; 94 | } cs_sparc_op; 95 | 96 | // Instruction structure 97 | typedef struct cs_sparc { 98 | sparc_cc cc; // code condition for this insn 99 | sparc_hint hint; // branch hint: encoding as bitwise OR of SPARC_HINT_*. 100 | // Number of operands of this instruction, 101 | // or 0 when instruction has no operand. 102 | uint8_t op_count; 103 | cs_sparc_op operands[4]; // operands for this instruction. 104 | } cs_sparc; 105 | 106 | //> SPARC registers 107 | typedef enum sparc_reg { 108 | SPARC_REG_INVALID = 0, 109 | 110 | SPARC_REG_F0, 111 | SPARC_REG_F1, 112 | SPARC_REG_F2, 113 | SPARC_REG_F3, 114 | SPARC_REG_F4, 115 | SPARC_REG_F5, 116 | SPARC_REG_F6, 117 | SPARC_REG_F7, 118 | SPARC_REG_F8, 119 | SPARC_REG_F9, 120 | SPARC_REG_F10, 121 | SPARC_REG_F11, 122 | SPARC_REG_F12, 123 | SPARC_REG_F13, 124 | SPARC_REG_F14, 125 | SPARC_REG_F15, 126 | SPARC_REG_F16, 127 | SPARC_REG_F17, 128 | SPARC_REG_F18, 129 | SPARC_REG_F19, 130 | SPARC_REG_F20, 131 | SPARC_REG_F21, 132 | SPARC_REG_F22, 133 | SPARC_REG_F23, 134 | SPARC_REG_F24, 135 | SPARC_REG_F25, 136 | SPARC_REG_F26, 137 | SPARC_REG_F27, 138 | SPARC_REG_F28, 139 | SPARC_REG_F29, 140 | SPARC_REG_F30, 141 | SPARC_REG_F31, 142 | SPARC_REG_F32, 143 | SPARC_REG_F34, 144 | SPARC_REG_F36, 145 | SPARC_REG_F38, 146 | SPARC_REG_F40, 147 | SPARC_REG_F42, 148 | SPARC_REG_F44, 149 | SPARC_REG_F46, 150 | SPARC_REG_F48, 151 | SPARC_REG_F50, 152 | SPARC_REG_F52, 153 | SPARC_REG_F54, 154 | SPARC_REG_F56, 155 | SPARC_REG_F58, 156 | SPARC_REG_F60, 157 | SPARC_REG_F62, 158 | SPARC_REG_FCC0, // Floating condition codes 159 | SPARC_REG_FCC1, 160 | SPARC_REG_FCC2, 161 | SPARC_REG_FCC3, 162 | SPARC_REG_FP, 163 | SPARC_REG_G0, 164 | SPARC_REG_G1, 165 | SPARC_REG_G2, 166 | SPARC_REG_G3, 167 | SPARC_REG_G4, 168 | SPARC_REG_G5, 169 | SPARC_REG_G6, 170 | SPARC_REG_G7, 171 | SPARC_REG_I0, 172 | SPARC_REG_I1, 173 | SPARC_REG_I2, 174 | SPARC_REG_I3, 175 | SPARC_REG_I4, 176 | SPARC_REG_I5, 177 | SPARC_REG_I7, 178 | SPARC_REG_ICC, // Integer condition codes 179 | SPARC_REG_L0, 180 | SPARC_REG_L1, 181 | SPARC_REG_L2, 182 | SPARC_REG_L3, 183 | SPARC_REG_L4, 184 | SPARC_REG_L5, 185 | SPARC_REG_L6, 186 | SPARC_REG_L7, 187 | SPARC_REG_O0, 188 | SPARC_REG_O1, 189 | SPARC_REG_O2, 190 | SPARC_REG_O3, 191 | SPARC_REG_O4, 192 | SPARC_REG_O5, 193 | SPARC_REG_O7, 194 | SPARC_REG_SP, 195 | SPARC_REG_Y, 196 | 197 | SPARC_REG_MAX, // <-- mark the end of the list of registers 198 | 199 | // extras 200 | SPARC_REG_O6 = SPARC_REG_SP, 201 | SPARC_REG_I6 = SPARC_REG_FP, 202 | } sparc_reg; 203 | 204 | //> SPARC instruction 205 | typedef enum sparc_insn { 206 | SPARC_INS_INVALID = 0, 207 | 208 | SPARC_INS_ADDCC, 209 | SPARC_INS_ADDX, 210 | SPARC_INS_ADDXCC, 211 | SPARC_INS_ADDXC, 212 | SPARC_INS_ADDXCCC, 213 | SPARC_INS_ADD, 214 | SPARC_INS_ALIGNADDR, 215 | SPARC_INS_ALIGNADDRL, 216 | SPARC_INS_ANDCC, 217 | SPARC_INS_ANDNCC, 218 | SPARC_INS_ANDN, 219 | SPARC_INS_AND, 220 | SPARC_INS_ARRAY16, 221 | SPARC_INS_ARRAY32, 222 | SPARC_INS_ARRAY8, 223 | SPARC_INS_B, 224 | SPARC_INS_JMP, 225 | SPARC_INS_BMASK, 226 | SPARC_INS_FB, 227 | SPARC_INS_BRGEZ, 228 | SPARC_INS_BRGZ, 229 | SPARC_INS_BRLEZ, 230 | SPARC_INS_BRLZ, 231 | SPARC_INS_BRNZ, 232 | SPARC_INS_BRZ, 233 | SPARC_INS_BSHUFFLE, 234 | SPARC_INS_CALL, 235 | SPARC_INS_CASX, 236 | SPARC_INS_CAS, 237 | SPARC_INS_CMASK16, 238 | SPARC_INS_CMASK32, 239 | SPARC_INS_CMASK8, 240 | SPARC_INS_CMP, 241 | SPARC_INS_EDGE16, 242 | SPARC_INS_EDGE16L, 243 | SPARC_INS_EDGE16LN, 244 | SPARC_INS_EDGE16N, 245 | SPARC_INS_EDGE32, 246 | SPARC_INS_EDGE32L, 247 | SPARC_INS_EDGE32LN, 248 | SPARC_INS_EDGE32N, 249 | SPARC_INS_EDGE8, 250 | SPARC_INS_EDGE8L, 251 | SPARC_INS_EDGE8LN, 252 | SPARC_INS_EDGE8N, 253 | SPARC_INS_FABSD, 254 | SPARC_INS_FABSQ, 255 | SPARC_INS_FABSS, 256 | SPARC_INS_FADDD, 257 | SPARC_INS_FADDQ, 258 | SPARC_INS_FADDS, 259 | SPARC_INS_FALIGNDATA, 260 | SPARC_INS_FAND, 261 | SPARC_INS_FANDNOT1, 262 | SPARC_INS_FANDNOT1S, 263 | SPARC_INS_FANDNOT2, 264 | SPARC_INS_FANDNOT2S, 265 | SPARC_INS_FANDS, 266 | SPARC_INS_FCHKSM16, 267 | SPARC_INS_FCMPD, 268 | SPARC_INS_FCMPEQ16, 269 | SPARC_INS_FCMPEQ32, 270 | SPARC_INS_FCMPGT16, 271 | SPARC_INS_FCMPGT32, 272 | SPARC_INS_FCMPLE16, 273 | SPARC_INS_FCMPLE32, 274 | SPARC_INS_FCMPNE16, 275 | SPARC_INS_FCMPNE32, 276 | SPARC_INS_FCMPQ, 277 | SPARC_INS_FCMPS, 278 | SPARC_INS_FDIVD, 279 | SPARC_INS_FDIVQ, 280 | SPARC_INS_FDIVS, 281 | SPARC_INS_FDMULQ, 282 | SPARC_INS_FDTOI, 283 | SPARC_INS_FDTOQ, 284 | SPARC_INS_FDTOS, 285 | SPARC_INS_FDTOX, 286 | SPARC_INS_FEXPAND, 287 | SPARC_INS_FHADDD, 288 | SPARC_INS_FHADDS, 289 | SPARC_INS_FHSUBD, 290 | SPARC_INS_FHSUBS, 291 | SPARC_INS_FITOD, 292 | SPARC_INS_FITOQ, 293 | SPARC_INS_FITOS, 294 | SPARC_INS_FLCMPD, 295 | SPARC_INS_FLCMPS, 296 | SPARC_INS_FLUSHW, 297 | SPARC_INS_FMEAN16, 298 | SPARC_INS_FMOVD, 299 | SPARC_INS_FMOVQ, 300 | SPARC_INS_FMOVRDGEZ, 301 | SPARC_INS_FMOVRQGEZ, 302 | SPARC_INS_FMOVRSGEZ, 303 | SPARC_INS_FMOVRDGZ, 304 | SPARC_INS_FMOVRQGZ, 305 | SPARC_INS_FMOVRSGZ, 306 | SPARC_INS_FMOVRDLEZ, 307 | SPARC_INS_FMOVRQLEZ, 308 | SPARC_INS_FMOVRSLEZ, 309 | SPARC_INS_FMOVRDLZ, 310 | SPARC_INS_FMOVRQLZ, 311 | SPARC_INS_FMOVRSLZ, 312 | SPARC_INS_FMOVRDNZ, 313 | SPARC_INS_FMOVRQNZ, 314 | SPARC_INS_FMOVRSNZ, 315 | SPARC_INS_FMOVRDZ, 316 | SPARC_INS_FMOVRQZ, 317 | SPARC_INS_FMOVRSZ, 318 | SPARC_INS_FMOVS, 319 | SPARC_INS_FMUL8SUX16, 320 | SPARC_INS_FMUL8ULX16, 321 | SPARC_INS_FMUL8X16, 322 | SPARC_INS_FMUL8X16AL, 323 | SPARC_INS_FMUL8X16AU, 324 | SPARC_INS_FMULD, 325 | SPARC_INS_FMULD8SUX16, 326 | SPARC_INS_FMULD8ULX16, 327 | SPARC_INS_FMULQ, 328 | SPARC_INS_FMULS, 329 | SPARC_INS_FNADDD, 330 | SPARC_INS_FNADDS, 331 | SPARC_INS_FNAND, 332 | SPARC_INS_FNANDS, 333 | SPARC_INS_FNEGD, 334 | SPARC_INS_FNEGQ, 335 | SPARC_INS_FNEGS, 336 | SPARC_INS_FNHADDD, 337 | SPARC_INS_FNHADDS, 338 | SPARC_INS_FNOR, 339 | SPARC_INS_FNORS, 340 | SPARC_INS_FNOT1, 341 | SPARC_INS_FNOT1S, 342 | SPARC_INS_FNOT2, 343 | SPARC_INS_FNOT2S, 344 | SPARC_INS_FONE, 345 | SPARC_INS_FONES, 346 | SPARC_INS_FOR, 347 | SPARC_INS_FORNOT1, 348 | SPARC_INS_FORNOT1S, 349 | SPARC_INS_FORNOT2, 350 | SPARC_INS_FORNOT2S, 351 | SPARC_INS_FORS, 352 | SPARC_INS_FPACK16, 353 | SPARC_INS_FPACK32, 354 | SPARC_INS_FPACKFIX, 355 | SPARC_INS_FPADD16, 356 | SPARC_INS_FPADD16S, 357 | SPARC_INS_FPADD32, 358 | SPARC_INS_FPADD32S, 359 | SPARC_INS_FPADD64, 360 | SPARC_INS_FPMERGE, 361 | SPARC_INS_FPSUB16, 362 | SPARC_INS_FPSUB16S, 363 | SPARC_INS_FPSUB32, 364 | SPARC_INS_FPSUB32S, 365 | SPARC_INS_FQTOD, 366 | SPARC_INS_FQTOI, 367 | SPARC_INS_FQTOS, 368 | SPARC_INS_FQTOX, 369 | SPARC_INS_FSLAS16, 370 | SPARC_INS_FSLAS32, 371 | SPARC_INS_FSLL16, 372 | SPARC_INS_FSLL32, 373 | SPARC_INS_FSMULD, 374 | SPARC_INS_FSQRTD, 375 | SPARC_INS_FSQRTQ, 376 | SPARC_INS_FSQRTS, 377 | SPARC_INS_FSRA16, 378 | SPARC_INS_FSRA32, 379 | SPARC_INS_FSRC1, 380 | SPARC_INS_FSRC1S, 381 | SPARC_INS_FSRC2, 382 | SPARC_INS_FSRC2S, 383 | SPARC_INS_FSRL16, 384 | SPARC_INS_FSRL32, 385 | SPARC_INS_FSTOD, 386 | SPARC_INS_FSTOI, 387 | SPARC_INS_FSTOQ, 388 | SPARC_INS_FSTOX, 389 | SPARC_INS_FSUBD, 390 | SPARC_INS_FSUBQ, 391 | SPARC_INS_FSUBS, 392 | SPARC_INS_FXNOR, 393 | SPARC_INS_FXNORS, 394 | SPARC_INS_FXOR, 395 | SPARC_INS_FXORS, 396 | SPARC_INS_FXTOD, 397 | SPARC_INS_FXTOQ, 398 | SPARC_INS_FXTOS, 399 | SPARC_INS_FZERO, 400 | SPARC_INS_FZEROS, 401 | SPARC_INS_JMPL, 402 | SPARC_INS_LDD, 403 | SPARC_INS_LD, 404 | SPARC_INS_LDQ, 405 | SPARC_INS_LDSB, 406 | SPARC_INS_LDSH, 407 | SPARC_INS_LDSW, 408 | SPARC_INS_LDUB, 409 | SPARC_INS_LDUH, 410 | SPARC_INS_LDX, 411 | SPARC_INS_LZCNT, 412 | SPARC_INS_MEMBAR, 413 | SPARC_INS_MOVDTOX, 414 | SPARC_INS_MOV, 415 | SPARC_INS_MOVRGEZ, 416 | SPARC_INS_MOVRGZ, 417 | SPARC_INS_MOVRLEZ, 418 | SPARC_INS_MOVRLZ, 419 | SPARC_INS_MOVRNZ, 420 | SPARC_INS_MOVRZ, 421 | SPARC_INS_MOVSTOSW, 422 | SPARC_INS_MOVSTOUW, 423 | SPARC_INS_MULX, 424 | SPARC_INS_NOP, 425 | SPARC_INS_ORCC, 426 | SPARC_INS_ORNCC, 427 | SPARC_INS_ORN, 428 | SPARC_INS_OR, 429 | SPARC_INS_PDIST, 430 | SPARC_INS_PDISTN, 431 | SPARC_INS_POPC, 432 | SPARC_INS_RD, 433 | SPARC_INS_RESTORE, 434 | SPARC_INS_RETT, 435 | SPARC_INS_SAVE, 436 | SPARC_INS_SDIVCC, 437 | SPARC_INS_SDIVX, 438 | SPARC_INS_SDIV, 439 | SPARC_INS_SETHI, 440 | SPARC_INS_SHUTDOWN, 441 | SPARC_INS_SIAM, 442 | SPARC_INS_SLLX, 443 | SPARC_INS_SLL, 444 | SPARC_INS_SMULCC, 445 | SPARC_INS_SMUL, 446 | SPARC_INS_SRAX, 447 | SPARC_INS_SRA, 448 | SPARC_INS_SRLX, 449 | SPARC_INS_SRL, 450 | SPARC_INS_STBAR, 451 | SPARC_INS_STB, 452 | SPARC_INS_STD, 453 | SPARC_INS_ST, 454 | SPARC_INS_STH, 455 | SPARC_INS_STQ, 456 | SPARC_INS_STX, 457 | SPARC_INS_SUBCC, 458 | SPARC_INS_SUBX, 459 | SPARC_INS_SUBXCC, 460 | SPARC_INS_SUB, 461 | SPARC_INS_SWAP, 462 | SPARC_INS_TADDCCTV, 463 | SPARC_INS_TADDCC, 464 | SPARC_INS_T, 465 | SPARC_INS_TSUBCCTV, 466 | SPARC_INS_TSUBCC, 467 | SPARC_INS_UDIVCC, 468 | SPARC_INS_UDIVX, 469 | SPARC_INS_UDIV, 470 | SPARC_INS_UMULCC, 471 | SPARC_INS_UMULXHI, 472 | SPARC_INS_UMUL, 473 | SPARC_INS_UNIMP, 474 | SPARC_INS_FCMPED, 475 | SPARC_INS_FCMPEQ, 476 | SPARC_INS_FCMPES, 477 | SPARC_INS_WR, 478 | SPARC_INS_XMULX, 479 | SPARC_INS_XMULXHI, 480 | SPARC_INS_XNORCC, 481 | SPARC_INS_XNOR, 482 | SPARC_INS_XORCC, 483 | SPARC_INS_XOR, 484 | 485 | SPARC_INS_MAX, // <-- mark the end of the list of instructions 486 | } sparc_insn; 487 | 488 | //> Group of SPARC instructions 489 | typedef enum sparc_insn_group { 490 | SPARC_GRP_INVALID = 0, 491 | 492 | SPARC_GRP_HARDQUAD, 493 | SPARC_GRP_V9, 494 | SPARC_GRP_VIS, 495 | SPARC_GRP_VIS2, 496 | SPARC_GRP_VIS3, 497 | SPARC_GRP_32BIT, 498 | SPARC_GRP_64BIT, 499 | 500 | SPARC_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) 501 | 502 | SPARC_GRP_MAX, // <-- mark the end of the list of groups 503 | } sparc_insn_group; 504 | 505 | #ifdef __cplusplus 506 | } 507 | #endif 508 | 509 | #endif 510 | -------------------------------------------------------------------------------- /capstone/include/systemz.h: -------------------------------------------------------------------------------- 1 | #ifndef CAPSTONE_SYSTEMZ_H 2 | #define CAPSTONE_SYSTEMZ_H 3 | 4 | /* Capstone Disassembly Engine */ 5 | /* By Nguyen Anh Quynh , 2014 */ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include "platform.h" 13 | 14 | #ifdef _MSC_VER 15 | #pragma warning(disable:4201) 16 | #endif 17 | 18 | //> Enums corresponding to SystemZ condition codes 19 | typedef enum sysz_cc { 20 | SYSZ_CC_INVALID = 0, // invalid CC (default) 21 | 22 | SYSZ_CC_O, 23 | SYSZ_CC_H, 24 | SYSZ_CC_NLE, 25 | SYSZ_CC_L, 26 | SYSZ_CC_NHE, 27 | SYSZ_CC_LH, 28 | SYSZ_CC_NE, 29 | SYSZ_CC_E, 30 | SYSZ_CC_NLH, 31 | SYSZ_CC_HE, 32 | SYSZ_CC_NL, 33 | SYSZ_CC_LE, 34 | SYSZ_CC_NH, 35 | SYSZ_CC_NO, 36 | } sysz_cc; 37 | 38 | //> Operand type for instruction's operands 39 | typedef enum sysz_op_type { 40 | SYSZ_OP_INVALID = 0, // Uninitialized. 41 | SYSZ_OP_REG, // Register operand. 42 | SYSZ_OP_ACREG, // Access register operand. 43 | SYSZ_OP_IMM, // Immediate operand. 44 | SYSZ_OP_MEM, // Memory operand 45 | } sysz_op_type; 46 | 47 | // Instruction's operand referring to memory 48 | // This is associated with SYSZ_OP_MEM operand type above 49 | typedef struct sysz_op_mem { 50 | uint8_t base; // base register 51 | uint8_t index; // index register 52 | uint64_t length; // BDLAddr operand 53 | int64_t disp; // displacement/offset value 54 | } sysz_op_mem; 55 | 56 | // Instruction operand 57 | typedef struct cs_sysz_op { 58 | sysz_op_type type; // operand type 59 | union { 60 | unsigned int reg; // register value for REG operand 61 | int64_t imm; // immediate value for IMM operand 62 | sysz_op_mem mem; // base/disp value for MEM operand 63 | }; 64 | } cs_sysz_op; 65 | 66 | // Instruction structure 67 | typedef struct cs_sysz { 68 | sysz_cc cc; // Code condition 69 | // Number of operands of this instruction, 70 | // or 0 when instruction has no operand. 71 | uint8_t op_count; 72 | cs_sysz_op operands[6]; // operands for this instruction. 73 | } cs_sysz; 74 | 75 | //> SystemZ registers 76 | typedef enum sysz_reg { 77 | SYSZ_REG_INVALID = 0, 78 | 79 | SYSZ_REG_0, 80 | SYSZ_REG_1, 81 | SYSZ_REG_2, 82 | SYSZ_REG_3, 83 | SYSZ_REG_4, 84 | SYSZ_REG_5, 85 | SYSZ_REG_6, 86 | SYSZ_REG_7, 87 | SYSZ_REG_8, 88 | SYSZ_REG_9, 89 | SYSZ_REG_10, 90 | SYSZ_REG_11, 91 | SYSZ_REG_12, 92 | SYSZ_REG_13, 93 | SYSZ_REG_14, 94 | SYSZ_REG_15, 95 | SYSZ_REG_CC, 96 | SYSZ_REG_F0, 97 | SYSZ_REG_F1, 98 | SYSZ_REG_F2, 99 | SYSZ_REG_F3, 100 | SYSZ_REG_F4, 101 | SYSZ_REG_F5, 102 | SYSZ_REG_F6, 103 | SYSZ_REG_F7, 104 | SYSZ_REG_F8, 105 | SYSZ_REG_F9, 106 | SYSZ_REG_F10, 107 | SYSZ_REG_F11, 108 | SYSZ_REG_F12, 109 | SYSZ_REG_F13, 110 | SYSZ_REG_F14, 111 | SYSZ_REG_F15, 112 | 113 | SYSZ_REG_R0L, 114 | 115 | SYSZ_REG_MAX, 116 | } sysz_reg; 117 | 118 | //> SystemZ instruction 119 | typedef enum sysz_insn { 120 | SYSZ_INS_INVALID = 0, 121 | 122 | SYSZ_INS_A, 123 | SYSZ_INS_ADB, 124 | SYSZ_INS_ADBR, 125 | SYSZ_INS_AEB, 126 | SYSZ_INS_AEBR, 127 | SYSZ_INS_AFI, 128 | SYSZ_INS_AG, 129 | SYSZ_INS_AGF, 130 | SYSZ_INS_AGFI, 131 | SYSZ_INS_AGFR, 132 | SYSZ_INS_AGHI, 133 | SYSZ_INS_AGHIK, 134 | SYSZ_INS_AGR, 135 | SYSZ_INS_AGRK, 136 | SYSZ_INS_AGSI, 137 | SYSZ_INS_AH, 138 | SYSZ_INS_AHI, 139 | SYSZ_INS_AHIK, 140 | SYSZ_INS_AHY, 141 | SYSZ_INS_AIH, 142 | SYSZ_INS_AL, 143 | SYSZ_INS_ALC, 144 | SYSZ_INS_ALCG, 145 | SYSZ_INS_ALCGR, 146 | SYSZ_INS_ALCR, 147 | SYSZ_INS_ALFI, 148 | SYSZ_INS_ALG, 149 | SYSZ_INS_ALGF, 150 | SYSZ_INS_ALGFI, 151 | SYSZ_INS_ALGFR, 152 | SYSZ_INS_ALGHSIK, 153 | SYSZ_INS_ALGR, 154 | SYSZ_INS_ALGRK, 155 | SYSZ_INS_ALHSIK, 156 | SYSZ_INS_ALR, 157 | SYSZ_INS_ALRK, 158 | SYSZ_INS_ALY, 159 | SYSZ_INS_AR, 160 | SYSZ_INS_ARK, 161 | SYSZ_INS_ASI, 162 | SYSZ_INS_AXBR, 163 | SYSZ_INS_AY, 164 | SYSZ_INS_BCR, 165 | SYSZ_INS_BRC, 166 | SYSZ_INS_BRCL, 167 | SYSZ_INS_CGIJ, 168 | SYSZ_INS_CGRJ, 169 | SYSZ_INS_CIJ, 170 | SYSZ_INS_CLGIJ, 171 | SYSZ_INS_CLGRJ, 172 | SYSZ_INS_CLIJ, 173 | SYSZ_INS_CLRJ, 174 | SYSZ_INS_CRJ, 175 | SYSZ_INS_BER, 176 | SYSZ_INS_JE, 177 | SYSZ_INS_JGE, 178 | SYSZ_INS_LOCE, 179 | SYSZ_INS_LOCGE, 180 | SYSZ_INS_LOCGRE, 181 | SYSZ_INS_LOCRE, 182 | SYSZ_INS_STOCE, 183 | SYSZ_INS_STOCGE, 184 | SYSZ_INS_BHR, 185 | SYSZ_INS_BHER, 186 | SYSZ_INS_JHE, 187 | SYSZ_INS_JGHE, 188 | SYSZ_INS_LOCHE, 189 | SYSZ_INS_LOCGHE, 190 | SYSZ_INS_LOCGRHE, 191 | SYSZ_INS_LOCRHE, 192 | SYSZ_INS_STOCHE, 193 | SYSZ_INS_STOCGHE, 194 | SYSZ_INS_JH, 195 | SYSZ_INS_JGH, 196 | SYSZ_INS_LOCH, 197 | SYSZ_INS_LOCGH, 198 | SYSZ_INS_LOCGRH, 199 | SYSZ_INS_LOCRH, 200 | SYSZ_INS_STOCH, 201 | SYSZ_INS_STOCGH, 202 | SYSZ_INS_CGIJNLH, 203 | SYSZ_INS_CGRJNLH, 204 | SYSZ_INS_CIJNLH, 205 | SYSZ_INS_CLGIJNLH, 206 | SYSZ_INS_CLGRJNLH, 207 | SYSZ_INS_CLIJNLH, 208 | SYSZ_INS_CLRJNLH, 209 | SYSZ_INS_CRJNLH, 210 | SYSZ_INS_CGIJE, 211 | SYSZ_INS_CGRJE, 212 | SYSZ_INS_CIJE, 213 | SYSZ_INS_CLGIJE, 214 | SYSZ_INS_CLGRJE, 215 | SYSZ_INS_CLIJE, 216 | SYSZ_INS_CLRJE, 217 | SYSZ_INS_CRJE, 218 | SYSZ_INS_CGIJNLE, 219 | SYSZ_INS_CGRJNLE, 220 | SYSZ_INS_CIJNLE, 221 | SYSZ_INS_CLGIJNLE, 222 | SYSZ_INS_CLGRJNLE, 223 | SYSZ_INS_CLIJNLE, 224 | SYSZ_INS_CLRJNLE, 225 | SYSZ_INS_CRJNLE, 226 | SYSZ_INS_CGIJH, 227 | SYSZ_INS_CGRJH, 228 | SYSZ_INS_CIJH, 229 | SYSZ_INS_CLGIJH, 230 | SYSZ_INS_CLGRJH, 231 | SYSZ_INS_CLIJH, 232 | SYSZ_INS_CLRJH, 233 | SYSZ_INS_CRJH, 234 | SYSZ_INS_CGIJNL, 235 | SYSZ_INS_CGRJNL, 236 | SYSZ_INS_CIJNL, 237 | SYSZ_INS_CLGIJNL, 238 | SYSZ_INS_CLGRJNL, 239 | SYSZ_INS_CLIJNL, 240 | SYSZ_INS_CLRJNL, 241 | SYSZ_INS_CRJNL, 242 | SYSZ_INS_CGIJHE, 243 | SYSZ_INS_CGRJHE, 244 | SYSZ_INS_CIJHE, 245 | SYSZ_INS_CLGIJHE, 246 | SYSZ_INS_CLGRJHE, 247 | SYSZ_INS_CLIJHE, 248 | SYSZ_INS_CLRJHE, 249 | SYSZ_INS_CRJHE, 250 | SYSZ_INS_CGIJNHE, 251 | SYSZ_INS_CGRJNHE, 252 | SYSZ_INS_CIJNHE, 253 | SYSZ_INS_CLGIJNHE, 254 | SYSZ_INS_CLGRJNHE, 255 | SYSZ_INS_CLIJNHE, 256 | SYSZ_INS_CLRJNHE, 257 | SYSZ_INS_CRJNHE, 258 | SYSZ_INS_CGIJL, 259 | SYSZ_INS_CGRJL, 260 | SYSZ_INS_CIJL, 261 | SYSZ_INS_CLGIJL, 262 | SYSZ_INS_CLGRJL, 263 | SYSZ_INS_CLIJL, 264 | SYSZ_INS_CLRJL, 265 | SYSZ_INS_CRJL, 266 | SYSZ_INS_CGIJNH, 267 | SYSZ_INS_CGRJNH, 268 | SYSZ_INS_CIJNH, 269 | SYSZ_INS_CLGIJNH, 270 | SYSZ_INS_CLGRJNH, 271 | SYSZ_INS_CLIJNH, 272 | SYSZ_INS_CLRJNH, 273 | SYSZ_INS_CRJNH, 274 | SYSZ_INS_CGIJLE, 275 | SYSZ_INS_CGRJLE, 276 | SYSZ_INS_CIJLE, 277 | SYSZ_INS_CLGIJLE, 278 | SYSZ_INS_CLGRJLE, 279 | SYSZ_INS_CLIJLE, 280 | SYSZ_INS_CLRJLE, 281 | SYSZ_INS_CRJLE, 282 | SYSZ_INS_CGIJNE, 283 | SYSZ_INS_CGRJNE, 284 | SYSZ_INS_CIJNE, 285 | SYSZ_INS_CLGIJNE, 286 | SYSZ_INS_CLGRJNE, 287 | SYSZ_INS_CLIJNE, 288 | SYSZ_INS_CLRJNE, 289 | SYSZ_INS_CRJNE, 290 | SYSZ_INS_CGIJLH, 291 | SYSZ_INS_CGRJLH, 292 | SYSZ_INS_CIJLH, 293 | SYSZ_INS_CLGIJLH, 294 | SYSZ_INS_CLGRJLH, 295 | SYSZ_INS_CLIJLH, 296 | SYSZ_INS_CLRJLH, 297 | SYSZ_INS_CRJLH, 298 | SYSZ_INS_BLR, 299 | SYSZ_INS_BLER, 300 | SYSZ_INS_JLE, 301 | SYSZ_INS_JGLE, 302 | SYSZ_INS_LOCLE, 303 | SYSZ_INS_LOCGLE, 304 | SYSZ_INS_LOCGRLE, 305 | SYSZ_INS_LOCRLE, 306 | SYSZ_INS_STOCLE, 307 | SYSZ_INS_STOCGLE, 308 | SYSZ_INS_BLHR, 309 | SYSZ_INS_JLH, 310 | SYSZ_INS_JGLH, 311 | SYSZ_INS_LOCLH, 312 | SYSZ_INS_LOCGLH, 313 | SYSZ_INS_LOCGRLH, 314 | SYSZ_INS_LOCRLH, 315 | SYSZ_INS_STOCLH, 316 | SYSZ_INS_STOCGLH, 317 | SYSZ_INS_JL, 318 | SYSZ_INS_JGL, 319 | SYSZ_INS_LOCL, 320 | SYSZ_INS_LOCGL, 321 | SYSZ_INS_LOCGRL, 322 | SYSZ_INS_LOCRL, 323 | SYSZ_INS_LOC, 324 | SYSZ_INS_LOCG, 325 | SYSZ_INS_LOCGR, 326 | SYSZ_INS_LOCR, 327 | SYSZ_INS_STOCL, 328 | SYSZ_INS_STOCGL, 329 | SYSZ_INS_BNER, 330 | SYSZ_INS_JNE, 331 | SYSZ_INS_JGNE, 332 | SYSZ_INS_LOCNE, 333 | SYSZ_INS_LOCGNE, 334 | SYSZ_INS_LOCGRNE, 335 | SYSZ_INS_LOCRNE, 336 | SYSZ_INS_STOCNE, 337 | SYSZ_INS_STOCGNE, 338 | SYSZ_INS_BNHR, 339 | SYSZ_INS_BNHER, 340 | SYSZ_INS_JNHE, 341 | SYSZ_INS_JGNHE, 342 | SYSZ_INS_LOCNHE, 343 | SYSZ_INS_LOCGNHE, 344 | SYSZ_INS_LOCGRNHE, 345 | SYSZ_INS_LOCRNHE, 346 | SYSZ_INS_STOCNHE, 347 | SYSZ_INS_STOCGNHE, 348 | SYSZ_INS_JNH, 349 | SYSZ_INS_JGNH, 350 | SYSZ_INS_LOCNH, 351 | SYSZ_INS_LOCGNH, 352 | SYSZ_INS_LOCGRNH, 353 | SYSZ_INS_LOCRNH, 354 | SYSZ_INS_STOCNH, 355 | SYSZ_INS_STOCGNH, 356 | SYSZ_INS_BNLR, 357 | SYSZ_INS_BNLER, 358 | SYSZ_INS_JNLE, 359 | SYSZ_INS_JGNLE, 360 | SYSZ_INS_LOCNLE, 361 | SYSZ_INS_LOCGNLE, 362 | SYSZ_INS_LOCGRNLE, 363 | SYSZ_INS_LOCRNLE, 364 | SYSZ_INS_STOCNLE, 365 | SYSZ_INS_STOCGNLE, 366 | SYSZ_INS_BNLHR, 367 | SYSZ_INS_JNLH, 368 | SYSZ_INS_JGNLH, 369 | SYSZ_INS_LOCNLH, 370 | SYSZ_INS_LOCGNLH, 371 | SYSZ_INS_LOCGRNLH, 372 | SYSZ_INS_LOCRNLH, 373 | SYSZ_INS_STOCNLH, 374 | SYSZ_INS_STOCGNLH, 375 | SYSZ_INS_JNL, 376 | SYSZ_INS_JGNL, 377 | SYSZ_INS_LOCNL, 378 | SYSZ_INS_LOCGNL, 379 | SYSZ_INS_LOCGRNL, 380 | SYSZ_INS_LOCRNL, 381 | SYSZ_INS_STOCNL, 382 | SYSZ_INS_STOCGNL, 383 | SYSZ_INS_BNOR, 384 | SYSZ_INS_JNO, 385 | SYSZ_INS_JGNO, 386 | SYSZ_INS_LOCNO, 387 | SYSZ_INS_LOCGNO, 388 | SYSZ_INS_LOCGRNO, 389 | SYSZ_INS_LOCRNO, 390 | SYSZ_INS_STOCNO, 391 | SYSZ_INS_STOCGNO, 392 | SYSZ_INS_BOR, 393 | SYSZ_INS_JO, 394 | SYSZ_INS_JGO, 395 | SYSZ_INS_LOCO, 396 | SYSZ_INS_LOCGO, 397 | SYSZ_INS_LOCGRO, 398 | SYSZ_INS_LOCRO, 399 | SYSZ_INS_STOCO, 400 | SYSZ_INS_STOCGO, 401 | SYSZ_INS_STOC, 402 | SYSZ_INS_STOCG, 403 | SYSZ_INS_BASR, 404 | SYSZ_INS_BR, 405 | SYSZ_INS_BRAS, 406 | SYSZ_INS_BRASL, 407 | SYSZ_INS_J, 408 | SYSZ_INS_JG, 409 | SYSZ_INS_BRCT, 410 | SYSZ_INS_BRCTG, 411 | SYSZ_INS_C, 412 | SYSZ_INS_CDB, 413 | SYSZ_INS_CDBR, 414 | SYSZ_INS_CDFBR, 415 | SYSZ_INS_CDGBR, 416 | SYSZ_INS_CDLFBR, 417 | SYSZ_INS_CDLGBR, 418 | SYSZ_INS_CEB, 419 | SYSZ_INS_CEBR, 420 | SYSZ_INS_CEFBR, 421 | SYSZ_INS_CEGBR, 422 | SYSZ_INS_CELFBR, 423 | SYSZ_INS_CELGBR, 424 | SYSZ_INS_CFDBR, 425 | SYSZ_INS_CFEBR, 426 | SYSZ_INS_CFI, 427 | SYSZ_INS_CFXBR, 428 | SYSZ_INS_CG, 429 | SYSZ_INS_CGDBR, 430 | SYSZ_INS_CGEBR, 431 | SYSZ_INS_CGF, 432 | SYSZ_INS_CGFI, 433 | SYSZ_INS_CGFR, 434 | SYSZ_INS_CGFRL, 435 | SYSZ_INS_CGH, 436 | SYSZ_INS_CGHI, 437 | SYSZ_INS_CGHRL, 438 | SYSZ_INS_CGHSI, 439 | SYSZ_INS_CGR, 440 | SYSZ_INS_CGRL, 441 | SYSZ_INS_CGXBR, 442 | SYSZ_INS_CH, 443 | SYSZ_INS_CHF, 444 | SYSZ_INS_CHHSI, 445 | SYSZ_INS_CHI, 446 | SYSZ_INS_CHRL, 447 | SYSZ_INS_CHSI, 448 | SYSZ_INS_CHY, 449 | SYSZ_INS_CIH, 450 | SYSZ_INS_CL, 451 | SYSZ_INS_CLC, 452 | SYSZ_INS_CLFDBR, 453 | SYSZ_INS_CLFEBR, 454 | SYSZ_INS_CLFHSI, 455 | SYSZ_INS_CLFI, 456 | SYSZ_INS_CLFXBR, 457 | SYSZ_INS_CLG, 458 | SYSZ_INS_CLGDBR, 459 | SYSZ_INS_CLGEBR, 460 | SYSZ_INS_CLGF, 461 | SYSZ_INS_CLGFI, 462 | SYSZ_INS_CLGFR, 463 | SYSZ_INS_CLGFRL, 464 | SYSZ_INS_CLGHRL, 465 | SYSZ_INS_CLGHSI, 466 | SYSZ_INS_CLGR, 467 | SYSZ_INS_CLGRL, 468 | SYSZ_INS_CLGXBR, 469 | SYSZ_INS_CLHF, 470 | SYSZ_INS_CLHHSI, 471 | SYSZ_INS_CLHRL, 472 | SYSZ_INS_CLI, 473 | SYSZ_INS_CLIH, 474 | SYSZ_INS_CLIY, 475 | SYSZ_INS_CLR, 476 | SYSZ_INS_CLRL, 477 | SYSZ_INS_CLST, 478 | SYSZ_INS_CLY, 479 | SYSZ_INS_CPSDR, 480 | SYSZ_INS_CR, 481 | SYSZ_INS_CRL, 482 | SYSZ_INS_CS, 483 | SYSZ_INS_CSG, 484 | SYSZ_INS_CSY, 485 | SYSZ_INS_CXBR, 486 | SYSZ_INS_CXFBR, 487 | SYSZ_INS_CXGBR, 488 | SYSZ_INS_CXLFBR, 489 | SYSZ_INS_CXLGBR, 490 | SYSZ_INS_CY, 491 | SYSZ_INS_DDB, 492 | SYSZ_INS_DDBR, 493 | SYSZ_INS_DEB, 494 | SYSZ_INS_DEBR, 495 | SYSZ_INS_DL, 496 | SYSZ_INS_DLG, 497 | SYSZ_INS_DLGR, 498 | SYSZ_INS_DLR, 499 | SYSZ_INS_DSG, 500 | SYSZ_INS_DSGF, 501 | SYSZ_INS_DSGFR, 502 | SYSZ_INS_DSGR, 503 | SYSZ_INS_DXBR, 504 | SYSZ_INS_EAR, 505 | SYSZ_INS_FIDBR, 506 | SYSZ_INS_FIDBRA, 507 | SYSZ_INS_FIEBR, 508 | SYSZ_INS_FIEBRA, 509 | SYSZ_INS_FIXBR, 510 | SYSZ_INS_FIXBRA, 511 | SYSZ_INS_FLOGR, 512 | SYSZ_INS_IC, 513 | SYSZ_INS_ICY, 514 | SYSZ_INS_IIHF, 515 | SYSZ_INS_IIHH, 516 | SYSZ_INS_IIHL, 517 | SYSZ_INS_IILF, 518 | SYSZ_INS_IILH, 519 | SYSZ_INS_IILL, 520 | SYSZ_INS_IPM, 521 | SYSZ_INS_L, 522 | SYSZ_INS_LA, 523 | SYSZ_INS_LAA, 524 | SYSZ_INS_LAAG, 525 | SYSZ_INS_LAAL, 526 | SYSZ_INS_LAALG, 527 | SYSZ_INS_LAN, 528 | SYSZ_INS_LANG, 529 | SYSZ_INS_LAO, 530 | SYSZ_INS_LAOG, 531 | SYSZ_INS_LARL, 532 | SYSZ_INS_LAX, 533 | SYSZ_INS_LAXG, 534 | SYSZ_INS_LAY, 535 | SYSZ_INS_LB, 536 | SYSZ_INS_LBH, 537 | SYSZ_INS_LBR, 538 | SYSZ_INS_LCDBR, 539 | SYSZ_INS_LCEBR, 540 | SYSZ_INS_LCGFR, 541 | SYSZ_INS_LCGR, 542 | SYSZ_INS_LCR, 543 | SYSZ_INS_LCXBR, 544 | SYSZ_INS_LD, 545 | SYSZ_INS_LDEB, 546 | SYSZ_INS_LDEBR, 547 | SYSZ_INS_LDGR, 548 | SYSZ_INS_LDR, 549 | SYSZ_INS_LDXBR, 550 | SYSZ_INS_LDXBRA, 551 | SYSZ_INS_LDY, 552 | SYSZ_INS_LE, 553 | SYSZ_INS_LEDBR, 554 | SYSZ_INS_LEDBRA, 555 | SYSZ_INS_LER, 556 | SYSZ_INS_LEXBR, 557 | SYSZ_INS_LEXBRA, 558 | SYSZ_INS_LEY, 559 | SYSZ_INS_LFH, 560 | SYSZ_INS_LG, 561 | SYSZ_INS_LGB, 562 | SYSZ_INS_LGBR, 563 | SYSZ_INS_LGDR, 564 | SYSZ_INS_LGF, 565 | SYSZ_INS_LGFI, 566 | SYSZ_INS_LGFR, 567 | SYSZ_INS_LGFRL, 568 | SYSZ_INS_LGH, 569 | SYSZ_INS_LGHI, 570 | SYSZ_INS_LGHR, 571 | SYSZ_INS_LGHRL, 572 | SYSZ_INS_LGR, 573 | SYSZ_INS_LGRL, 574 | SYSZ_INS_LH, 575 | SYSZ_INS_LHH, 576 | SYSZ_INS_LHI, 577 | SYSZ_INS_LHR, 578 | SYSZ_INS_LHRL, 579 | SYSZ_INS_LHY, 580 | SYSZ_INS_LLC, 581 | SYSZ_INS_LLCH, 582 | SYSZ_INS_LLCR, 583 | SYSZ_INS_LLGC, 584 | SYSZ_INS_LLGCR, 585 | SYSZ_INS_LLGF, 586 | SYSZ_INS_LLGFR, 587 | SYSZ_INS_LLGFRL, 588 | SYSZ_INS_LLGH, 589 | SYSZ_INS_LLGHR, 590 | SYSZ_INS_LLGHRL, 591 | SYSZ_INS_LLH, 592 | SYSZ_INS_LLHH, 593 | SYSZ_INS_LLHR, 594 | SYSZ_INS_LLHRL, 595 | SYSZ_INS_LLIHF, 596 | SYSZ_INS_LLIHH, 597 | SYSZ_INS_LLIHL, 598 | SYSZ_INS_LLILF, 599 | SYSZ_INS_LLILH, 600 | SYSZ_INS_LLILL, 601 | SYSZ_INS_LMG, 602 | SYSZ_INS_LNDBR, 603 | SYSZ_INS_LNEBR, 604 | SYSZ_INS_LNGFR, 605 | SYSZ_INS_LNGR, 606 | SYSZ_INS_LNR, 607 | SYSZ_INS_LNXBR, 608 | SYSZ_INS_LPDBR, 609 | SYSZ_INS_LPEBR, 610 | SYSZ_INS_LPGFR, 611 | SYSZ_INS_LPGR, 612 | SYSZ_INS_LPR, 613 | SYSZ_INS_LPXBR, 614 | SYSZ_INS_LR, 615 | SYSZ_INS_LRL, 616 | SYSZ_INS_LRV, 617 | SYSZ_INS_LRVG, 618 | SYSZ_INS_LRVGR, 619 | SYSZ_INS_LRVR, 620 | SYSZ_INS_LT, 621 | SYSZ_INS_LTDBR, 622 | SYSZ_INS_LTEBR, 623 | SYSZ_INS_LTG, 624 | SYSZ_INS_LTGF, 625 | SYSZ_INS_LTGFR, 626 | SYSZ_INS_LTGR, 627 | SYSZ_INS_LTR, 628 | SYSZ_INS_LTXBR, 629 | SYSZ_INS_LXDB, 630 | SYSZ_INS_LXDBR, 631 | SYSZ_INS_LXEB, 632 | SYSZ_INS_LXEBR, 633 | SYSZ_INS_LXR, 634 | SYSZ_INS_LY, 635 | SYSZ_INS_LZDR, 636 | SYSZ_INS_LZER, 637 | SYSZ_INS_LZXR, 638 | SYSZ_INS_MADB, 639 | SYSZ_INS_MADBR, 640 | SYSZ_INS_MAEB, 641 | SYSZ_INS_MAEBR, 642 | SYSZ_INS_MDB, 643 | SYSZ_INS_MDBR, 644 | SYSZ_INS_MDEB, 645 | SYSZ_INS_MDEBR, 646 | SYSZ_INS_MEEB, 647 | SYSZ_INS_MEEBR, 648 | SYSZ_INS_MGHI, 649 | SYSZ_INS_MH, 650 | SYSZ_INS_MHI, 651 | SYSZ_INS_MHY, 652 | SYSZ_INS_MLG, 653 | SYSZ_INS_MLGR, 654 | SYSZ_INS_MS, 655 | SYSZ_INS_MSDB, 656 | SYSZ_INS_MSDBR, 657 | SYSZ_INS_MSEB, 658 | SYSZ_INS_MSEBR, 659 | SYSZ_INS_MSFI, 660 | SYSZ_INS_MSG, 661 | SYSZ_INS_MSGF, 662 | SYSZ_INS_MSGFI, 663 | SYSZ_INS_MSGFR, 664 | SYSZ_INS_MSGR, 665 | SYSZ_INS_MSR, 666 | SYSZ_INS_MSY, 667 | SYSZ_INS_MVC, 668 | SYSZ_INS_MVGHI, 669 | SYSZ_INS_MVHHI, 670 | SYSZ_INS_MVHI, 671 | SYSZ_INS_MVI, 672 | SYSZ_INS_MVIY, 673 | SYSZ_INS_MVST, 674 | SYSZ_INS_MXBR, 675 | SYSZ_INS_MXDB, 676 | SYSZ_INS_MXDBR, 677 | SYSZ_INS_N, 678 | SYSZ_INS_NC, 679 | SYSZ_INS_NG, 680 | SYSZ_INS_NGR, 681 | SYSZ_INS_NGRK, 682 | SYSZ_INS_NI, 683 | SYSZ_INS_NIHF, 684 | SYSZ_INS_NIHH, 685 | SYSZ_INS_NIHL, 686 | SYSZ_INS_NILF, 687 | SYSZ_INS_NILH, 688 | SYSZ_INS_NILL, 689 | SYSZ_INS_NIY, 690 | SYSZ_INS_NR, 691 | SYSZ_INS_NRK, 692 | SYSZ_INS_NY, 693 | SYSZ_INS_O, 694 | SYSZ_INS_OC, 695 | SYSZ_INS_OG, 696 | SYSZ_INS_OGR, 697 | SYSZ_INS_OGRK, 698 | SYSZ_INS_OI, 699 | SYSZ_INS_OIHF, 700 | SYSZ_INS_OIHH, 701 | SYSZ_INS_OIHL, 702 | SYSZ_INS_OILF, 703 | SYSZ_INS_OILH, 704 | SYSZ_INS_OILL, 705 | SYSZ_INS_OIY, 706 | SYSZ_INS_OR, 707 | SYSZ_INS_ORK, 708 | SYSZ_INS_OY, 709 | SYSZ_INS_PFD, 710 | SYSZ_INS_PFDRL, 711 | SYSZ_INS_RISBG, 712 | SYSZ_INS_RISBHG, 713 | SYSZ_INS_RISBLG, 714 | SYSZ_INS_RLL, 715 | SYSZ_INS_RLLG, 716 | SYSZ_INS_RNSBG, 717 | SYSZ_INS_ROSBG, 718 | SYSZ_INS_RXSBG, 719 | SYSZ_INS_S, 720 | SYSZ_INS_SDB, 721 | SYSZ_INS_SDBR, 722 | SYSZ_INS_SEB, 723 | SYSZ_INS_SEBR, 724 | SYSZ_INS_SG, 725 | SYSZ_INS_SGF, 726 | SYSZ_INS_SGFR, 727 | SYSZ_INS_SGR, 728 | SYSZ_INS_SGRK, 729 | SYSZ_INS_SH, 730 | SYSZ_INS_SHY, 731 | SYSZ_INS_SL, 732 | SYSZ_INS_SLB, 733 | SYSZ_INS_SLBG, 734 | SYSZ_INS_SLBR, 735 | SYSZ_INS_SLFI, 736 | SYSZ_INS_SLG, 737 | SYSZ_INS_SLBGR, 738 | SYSZ_INS_SLGF, 739 | SYSZ_INS_SLGFI, 740 | SYSZ_INS_SLGFR, 741 | SYSZ_INS_SLGR, 742 | SYSZ_INS_SLGRK, 743 | SYSZ_INS_SLL, 744 | SYSZ_INS_SLLG, 745 | SYSZ_INS_SLLK, 746 | SYSZ_INS_SLR, 747 | SYSZ_INS_SLRK, 748 | SYSZ_INS_SLY, 749 | SYSZ_INS_SQDB, 750 | SYSZ_INS_SQDBR, 751 | SYSZ_INS_SQEB, 752 | SYSZ_INS_SQEBR, 753 | SYSZ_INS_SQXBR, 754 | SYSZ_INS_SR, 755 | SYSZ_INS_SRA, 756 | SYSZ_INS_SRAG, 757 | SYSZ_INS_SRAK, 758 | SYSZ_INS_SRK, 759 | SYSZ_INS_SRL, 760 | SYSZ_INS_SRLG, 761 | SYSZ_INS_SRLK, 762 | SYSZ_INS_SRST, 763 | SYSZ_INS_ST, 764 | SYSZ_INS_STC, 765 | SYSZ_INS_STCH, 766 | SYSZ_INS_STCY, 767 | SYSZ_INS_STD, 768 | SYSZ_INS_STDY, 769 | SYSZ_INS_STE, 770 | SYSZ_INS_STEY, 771 | SYSZ_INS_STFH, 772 | SYSZ_INS_STG, 773 | SYSZ_INS_STGRL, 774 | SYSZ_INS_STH, 775 | SYSZ_INS_STHH, 776 | SYSZ_INS_STHRL, 777 | SYSZ_INS_STHY, 778 | SYSZ_INS_STMG, 779 | SYSZ_INS_STRL, 780 | SYSZ_INS_STRV, 781 | SYSZ_INS_STRVG, 782 | SYSZ_INS_STY, 783 | SYSZ_INS_SXBR, 784 | SYSZ_INS_SY, 785 | SYSZ_INS_TM, 786 | SYSZ_INS_TMHH, 787 | SYSZ_INS_TMHL, 788 | SYSZ_INS_TMLH, 789 | SYSZ_INS_TMLL, 790 | SYSZ_INS_TMY, 791 | SYSZ_INS_X, 792 | SYSZ_INS_XC, 793 | SYSZ_INS_XG, 794 | SYSZ_INS_XGR, 795 | SYSZ_INS_XGRK, 796 | SYSZ_INS_XI, 797 | SYSZ_INS_XIHF, 798 | SYSZ_INS_XILF, 799 | SYSZ_INS_XIY, 800 | SYSZ_INS_XR, 801 | SYSZ_INS_XRK, 802 | SYSZ_INS_XY, 803 | 804 | SYSZ_INS_MAX, // <-- mark the end of the list of instructions 805 | } sysz_insn; 806 | 807 | //> Group of SystemZ instructions 808 | typedef enum sysz_insn_group { 809 | SYSZ_GRP_INVALID = 0, 810 | SYSZ_GRP_DISTINCTOPS, 811 | SYSZ_GRP_FPEXTENSION, 812 | SYSZ_GRP_HIGHWORD, 813 | SYSZ_GRP_INTERLOCKEDACCESS1, 814 | SYSZ_GRP_LOADSTOREONCOND, 815 | 816 | SYSZ_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) 817 | 818 | SYSZ_GRP_MAX, // <-- mark the end of the list of groups 819 | } sysz_insn_group; 820 | 821 | #ifdef __cplusplus 822 | } 823 | #endif 824 | 825 | #endif 826 | -------------------------------------------------------------------------------- /capstone/include/xcore.h: -------------------------------------------------------------------------------- 1 | #ifndef CAPSTONE_XCORE_H 2 | #define CAPSTONE_XCORE_H 3 | 4 | /* Capstone Disassembly Engine */ 5 | /* By Nguyen Anh Quynh , 2014 */ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include "platform.h" 13 | 14 | #ifdef _MSC_VER 15 | #pragma warning(disable:4201) 16 | #endif 17 | 18 | //> Operand type for instruction's operands 19 | typedef enum xcore_op_type { 20 | XCORE_OP_INVALID = 0, // Uninitialized. 21 | XCORE_OP_REG, // Register operand. 22 | XCORE_OP_IMM, // Immediate operand. 23 | XCORE_OP_MEM, // Memory operand 24 | } xcore_op_type; 25 | 26 | // Instruction's operand referring to memory 27 | // This is associated with XCORE_OP_MEM operand type above 28 | typedef struct xcore_op_mem { 29 | uint8_t base; // base register 30 | uint8_t index; // index register 31 | int32_t disp; // displacement/offset value 32 | int direct; // +1: forward, -1: backward 33 | } xcore_op_mem; 34 | 35 | // Instruction operand 36 | typedef struct cs_xcore_op { 37 | xcore_op_type type; // operand type 38 | union { 39 | unsigned int reg; // register value for REG operand 40 | int32_t imm; // immediate value for IMM operand 41 | xcore_op_mem mem; // base/disp value for MEM operand 42 | }; 43 | } cs_xcore_op; 44 | 45 | // Instruction structure 46 | typedef struct cs_xcore { 47 | // Number of operands of this instruction, 48 | // or 0 when instruction has no operand. 49 | uint8_t op_count; 50 | cs_xcore_op operands[8]; // operands for this instruction. 51 | } cs_xcore; 52 | 53 | //> XCore registers 54 | typedef enum xcore_reg { 55 | XCORE_REG_INVALID = 0, 56 | 57 | XCORE_REG_CP, 58 | XCORE_REG_DP, 59 | XCORE_REG_LR, 60 | XCORE_REG_SP, 61 | XCORE_REG_R0, 62 | XCORE_REG_R1, 63 | XCORE_REG_R2, 64 | XCORE_REG_R3, 65 | XCORE_REG_R4, 66 | XCORE_REG_R5, 67 | XCORE_REG_R6, 68 | XCORE_REG_R7, 69 | XCORE_REG_R8, 70 | XCORE_REG_R9, 71 | XCORE_REG_R10, 72 | XCORE_REG_R11, 73 | 74 | //> pseudo registers 75 | XCORE_REG_PC, // pc 76 | 77 | // internal thread registers 78 | // see The-XMOS-XS1-Architecture(X7879A).pdf 79 | XCORE_REG_SCP, // save pc 80 | XCORE_REG_SSR, // save status 81 | XCORE_REG_ET, // exception type 82 | XCORE_REG_ED, // exception data 83 | XCORE_REG_SED, // save exception data 84 | XCORE_REG_KEP, // kernel entry pointer 85 | XCORE_REG_KSP, // kernel stack pointer 86 | XCORE_REG_ID, // thread ID 87 | 88 | XCORE_REG_MAX, // <-- mark the end of the list of registers 89 | } xcore_reg; 90 | 91 | //> XCore instruction 92 | typedef enum xcore_insn { 93 | XCORE_INS_INVALID = 0, 94 | 95 | XCORE_INS_ADD, 96 | XCORE_INS_ANDNOT, 97 | XCORE_INS_AND, 98 | XCORE_INS_ASHR, 99 | XCORE_INS_BAU, 100 | XCORE_INS_BITREV, 101 | XCORE_INS_BLA, 102 | XCORE_INS_BLAT, 103 | XCORE_INS_BL, 104 | XCORE_INS_BF, 105 | XCORE_INS_BT, 106 | XCORE_INS_BU, 107 | XCORE_INS_BRU, 108 | XCORE_INS_BYTEREV, 109 | XCORE_INS_CHKCT, 110 | XCORE_INS_CLRE, 111 | XCORE_INS_CLRPT, 112 | XCORE_INS_CLRSR, 113 | XCORE_INS_CLZ, 114 | XCORE_INS_CRC8, 115 | XCORE_INS_CRC32, 116 | XCORE_INS_DCALL, 117 | XCORE_INS_DENTSP, 118 | XCORE_INS_DGETREG, 119 | XCORE_INS_DIVS, 120 | XCORE_INS_DIVU, 121 | XCORE_INS_DRESTSP, 122 | XCORE_INS_DRET, 123 | XCORE_INS_ECALLF, 124 | XCORE_INS_ECALLT, 125 | XCORE_INS_EDU, 126 | XCORE_INS_EEF, 127 | XCORE_INS_EET, 128 | XCORE_INS_EEU, 129 | XCORE_INS_ENDIN, 130 | XCORE_INS_ENTSP, 131 | XCORE_INS_EQ, 132 | XCORE_INS_EXTDP, 133 | XCORE_INS_EXTSP, 134 | XCORE_INS_FREER, 135 | XCORE_INS_FREET, 136 | XCORE_INS_GETD, 137 | XCORE_INS_GET, 138 | XCORE_INS_GETN, 139 | XCORE_INS_GETR, 140 | XCORE_INS_GETSR, 141 | XCORE_INS_GETST, 142 | XCORE_INS_GETTS, 143 | XCORE_INS_INCT, 144 | XCORE_INS_INIT, 145 | XCORE_INS_INPW, 146 | XCORE_INS_INSHR, 147 | XCORE_INS_INT, 148 | XCORE_INS_IN, 149 | XCORE_INS_KCALL, 150 | XCORE_INS_KENTSP, 151 | XCORE_INS_KRESTSP, 152 | XCORE_INS_KRET, 153 | XCORE_INS_LADD, 154 | XCORE_INS_LD16S, 155 | XCORE_INS_LD8U, 156 | XCORE_INS_LDA16, 157 | XCORE_INS_LDAP, 158 | XCORE_INS_LDAW, 159 | XCORE_INS_LDC, 160 | XCORE_INS_LDW, 161 | XCORE_INS_LDIVU, 162 | XCORE_INS_LMUL, 163 | XCORE_INS_LSS, 164 | XCORE_INS_LSUB, 165 | XCORE_INS_LSU, 166 | XCORE_INS_MACCS, 167 | XCORE_INS_MACCU, 168 | XCORE_INS_MJOIN, 169 | XCORE_INS_MKMSK, 170 | XCORE_INS_MSYNC, 171 | XCORE_INS_MUL, 172 | XCORE_INS_NEG, 173 | XCORE_INS_NOT, 174 | XCORE_INS_OR, 175 | XCORE_INS_OUTCT, 176 | XCORE_INS_OUTPW, 177 | XCORE_INS_OUTSHR, 178 | XCORE_INS_OUTT, 179 | XCORE_INS_OUT, 180 | XCORE_INS_PEEK, 181 | XCORE_INS_REMS, 182 | XCORE_INS_REMU, 183 | XCORE_INS_RETSP, 184 | XCORE_INS_SETCLK, 185 | XCORE_INS_SET, 186 | XCORE_INS_SETC, 187 | XCORE_INS_SETD, 188 | XCORE_INS_SETEV, 189 | XCORE_INS_SETN, 190 | XCORE_INS_SETPSC, 191 | XCORE_INS_SETPT, 192 | XCORE_INS_SETRDY, 193 | XCORE_INS_SETSR, 194 | XCORE_INS_SETTW, 195 | XCORE_INS_SETV, 196 | XCORE_INS_SEXT, 197 | XCORE_INS_SHL, 198 | XCORE_INS_SHR, 199 | XCORE_INS_SSYNC, 200 | XCORE_INS_ST16, 201 | XCORE_INS_ST8, 202 | XCORE_INS_STW, 203 | XCORE_INS_SUB, 204 | XCORE_INS_SYNCR, 205 | XCORE_INS_TESTCT, 206 | XCORE_INS_TESTLCL, 207 | XCORE_INS_TESTWCT, 208 | XCORE_INS_TSETMR, 209 | XCORE_INS_START, 210 | XCORE_INS_WAITEF, 211 | XCORE_INS_WAITET, 212 | XCORE_INS_WAITEU, 213 | XCORE_INS_XOR, 214 | XCORE_INS_ZEXT, 215 | 216 | XCORE_INS_MAX, // <-- mark the end of the list of instructions 217 | } xcore_insn; 218 | 219 | //> Group of XCore instructions 220 | typedef enum xcore_insn_group { 221 | XCORE_GRP_INVALID = 0, 222 | 223 | XCORE_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) 224 | 225 | XCORE_GRP_MAX, // <-- mark the end of the list of groups 226 | } xcore_insn_group; 227 | 228 | #ifdef __cplusplus 229 | } 230 | #endif 231 | 232 | #endif 233 | -------------------------------------------------------------------------------- /capstone/lib/capstone.debug.x86_32.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hlide/jitasm/dacbf6db9cfc50ac9b902284fc501f7f39f465b4/capstone/lib/capstone.debug.x86_32.lib -------------------------------------------------------------------------------- /capstone/lib/capstone.debug.x86_64.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hlide/jitasm/dacbf6db9cfc50ac9b902284fc501f7f39f465b4/capstone/lib/capstone.debug.x86_64.lib -------------------------------------------------------------------------------- /capstone/lib/capstone.release.x86_32.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hlide/jitasm/dacbf6db9cfc50ac9b902284fc501f7f39f465b4/capstone/lib/capstone.release.x86_32.lib -------------------------------------------------------------------------------- /capstone/lib/capstone.release.x86_64.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hlide/jitasm/dacbf6db9cfc50ac9b902284fc501f7f39f465b4/capstone/lib/capstone.release.x86_64.lib -------------------------------------------------------------------------------- /jitasm.Backend.h: -------------------------------------------------------------------------------- 1 | #include "jitasm.h" 2 | 3 | namespace jitasm 4 | { 5 | template < typename Derived > struct Backend$CRTP 6 | { 7 | uint8 * buffaddr_; 8 | size_t buffsize_; 9 | size_t size_; 10 | std::multimap< size_t, uint64 > bookmarks_; 11 | 12 | Backend$CRTP(void * buffaddr = nullptr, size_t buffsize = 0) 13 | : buffaddr_((uint8 *)buffaddr), buffsize_(buffsize), size_(0) 14 | { 15 | } 16 | 17 | std::vector< uint64 > GetBookmarks(size_t offset) 18 | { 19 | std::vector< uint64 > sources; 20 | auto r = bookmarks_.equal_range(offset); 21 | for (auto i = r.first; i != r.second; ++i) 22 | { 23 | sources.push_back(i->second); 24 | } 25 | return sources; 26 | } 27 | 28 | void AddBookmark(size_t offset, uint64 bookmark) 29 | { 30 | bookmarks_.insert(std::make_pair(offset, bookmark)); 31 | } 32 | 33 | size_t GetSize() const 34 | { 35 | return size_; 36 | } 37 | 38 | void PutBytes(void * p, size_t n) 39 | { 40 | uint8 * pb = (uint8 *)p; 41 | if (buffaddr_) 42 | { 43 | while (n--) buffaddr_[size_++] = *pb++; 44 | } 45 | else 46 | { 47 | size_ += n; 48 | } 49 | } 50 | 51 | void db(uint64 b) 52 | { 53 | PutBytes(&b, 1); 54 | } 55 | 56 | void dw(uint64 w) 57 | { 58 | PutBytes(&w, 2); 59 | } 60 | 61 | void dd(uint64 d) 62 | { 63 | PutBytes(&d, 4); 64 | } 65 | 66 | void dq(uint64 q) 67 | { 68 | PutBytes(&q, 8); 69 | } 70 | }; 71 | } -------------------------------------------------------------------------------- /jitasm.Backend.x86.h: -------------------------------------------------------------------------------- 1 | #ifndef jitasm_Backend_x86_h__ 2 | #define jitasm_Backend_x86_h__ 3 | #include "jitasm.x86.h" 4 | #include "jitasm.Backend.h" 5 | namespace jitasm 6 | { 7 | namespace x86 8 | { 9 | struct Backend : jitasm::Backend$CRTP < Backend > 10 | { 11 | bool is64_; 12 | 13 | Backend(bool is64, void * buffaddr = nullptr, size_t buffsize = 0) 14 | : jitasm::Backend$CRTP< Backend >(buffaddr, buffsize), is64_(is64) 15 | { 16 | memset(buffaddr, 0xCC, buffsize); 17 | } 18 | 19 | size_t SizeOf(Instr & instr) 20 | { 21 | Backend backend(is64_); 22 | backend.Assemble(instr); 23 | return backend.GetSize(); 24 | } 25 | 26 | static bool HasRIP(detail::Opd const & opd) 27 | { 28 | return opd.IsMem() && (opd.GetBase().type == R_TYPE_IP); 29 | } 30 | 31 | uint8 GetWRXB(int w, detail::Opd const & reg, detail::Opd const & r_m) 32 | { 33 | uint8 wrxb = w ? 8 : 0; 34 | if (reg.IsReg()) 35 | { 36 | if (!reg.GetReg().IsInvalid() && reg.GetReg().id >= R8) wrxb |= 4; 37 | } 38 | if (r_m.IsReg()) 39 | { 40 | if (r_m.GetReg().id >= R8) wrxb |= 1; 41 | } 42 | if (r_m.IsMem()) 43 | { 44 | if (!r_m.GetIndex().IsInvalid() && r_m.GetIndex().id >= R8) wrxb |= 2; 45 | if (!r_m.GetBase().IsInvalid() && r_m.GetBase().id >= R8) wrxb |= 1; 46 | } 47 | return wrxb; 48 | } 49 | 50 | void EncodePrefixes(uint32 flag, detail::Opd const & reg, detail::Opd const & r_m, detail::Opd const & vex) 51 | { 52 | if (flag & (E_VEX | E_XOP)) 53 | { 54 | // Encode VEX prefix 55 | if (is64_ && r_m.IsMem() && r_m.GetAddressBaseSize() != O_SIZE_64) db(0x67); 56 | uint8 vvvv = vex.IsReg() ? 0xF - (uint8)vex.GetReg().id : 0xF; 57 | uint8 mmmmm = (flag & E_VEX_MMMMM_MASK) >> E_VEX_MMMMM_SHIFT; 58 | uint8 pp = static_cast((flag & E_VEX_PP_MASK) >> E_VEX_PP_SHIFT); 59 | uint8 wrxb = GetWRXB(flag & E_VEX_W, reg, r_m); 60 | if (flag & E_XOP) 61 | { 62 | db(0x8F); 63 | db((~wrxb & 7) << 5 | mmmmm); 64 | db((wrxb & 8) << 4 | vvvv << 3 | (flag & E_VEX_L ? 4 : 0) | pp); 65 | } 66 | else if (wrxb & 0xB || (flag & E_VEX_MMMMM_MASK) == E_VEX_0F38 || (flag & E_VEX_MMMMM_MASK) == E_VEX_0F3A) 67 | { 68 | db(0xC4); 69 | db((~wrxb & 7) << 5 | mmmmm); 70 | db((wrxb & 8) << 4 | vvvv << 3 | (flag & E_VEX_L ? 4 : 0) | pp); 71 | } 72 | else 73 | { 74 | db(0xC5); 75 | db((~wrxb & 4) << 5 | vvvv << 3 | (flag & E_VEX_L ? 4 : 0) | pp); 76 | } 77 | } 78 | else 79 | { 80 | uint8 wrxb = GetWRXB(flag & E_REXW_PREFIX, reg, r_m); 81 | if (wrxb) 82 | { 83 | // Encode REX prefix 84 | if (flag & E_REP_PREFIX) db(0xF3); 85 | if (is64_ && r_m.IsMem() && r_m.GetAddressBaseSize() != O_SIZE_64) db(0x67); 86 | if (flag & E_OPERAND_SIZE_PREFIX) db(0x66); 87 | 88 | /**/ if (flag & E_MANDATORY_PREFIX_66) db(0x66); 89 | else if (flag & E_MANDATORY_PREFIX_F2) db(0xF2); 90 | else if (flag & E_MANDATORY_PREFIX_F3) db(0xF3); 91 | 92 | db(0x40 | wrxb); 93 | } 94 | else 95 | { 96 | /**/ if (flag & E_MANDATORY_PREFIX_66) db(0x66); 97 | else if (flag & E_MANDATORY_PREFIX_F2) db(0xF2); 98 | else if (flag & E_MANDATORY_PREFIX_F3) db(0xF3); 99 | 100 | if (flag & E_REP_PREFIX) db(0xF3); 101 | if (is64_ && r_m.IsMem() && r_m.GetAddressBaseSize() != O_SIZE_64) db(0x67); 102 | if (flag & E_OPERAND_SIZE_PREFIX) db(0x66); 103 | } 104 | } 105 | } 106 | 107 | void EncodeModRM(uint8 reg, detail::Opd const & r_m) 108 | { 109 | reg &= 0x7; 110 | 111 | /**/ if (r_m.IsReg()) 112 | { 113 | db(0xC0 | (reg << 3) | (r_m.GetReg().id & 0x7)); 114 | } 115 | else if (r_m.IsMem()) 116 | { 117 | int base = r_m.GetBase().id; if (base != INVALID) base &= 0x7; 118 | int index = r_m.GetIndex().id; if (index != INVALID) index &= 0x7; 119 | 120 | if (base == INVALID && index == INVALID) 121 | { 122 | if (is64_) 123 | { 124 | db(reg << 3 | 4); 125 | db(0x25); 126 | } 127 | else 128 | { 129 | db(reg << 3 | 5); 130 | } 131 | dd(r_m.GetDisp()); 132 | } 133 | else if (r_m.GetBase().type == R_TYPE_IP) 134 | { 135 | db(0 << 6 | reg << 3 | 5); 136 | dd(r_m.GetDisp()); 137 | } 138 | else 139 | { 140 | if (index == ESP) 141 | { 142 | index = base; 143 | base = ESP; 144 | } 145 | bool sib = index != INVALID || r_m.GetScale() || base == ESP; 146 | 147 | // ModR/M 148 | uint8 mod = 0; 149 | /**/ if (r_m.GetDisp() == 0 || (sib && base == INVALID)) mod = base != EBP ? 0 : 1; 150 | else if (detail::IsInt8(r_m.GetDisp())) mod = 1; 151 | else if (detail::IsInt32(r_m.GetDisp())) mod = 2; 152 | db(mod << 6 | reg << 3 | (sib ? 4 : base)); 153 | 154 | // SIB 155 | if (sib) 156 | { 157 | uint8 ss = 0; 158 | if (r_m.GetScale() == 0) ss = 0; 159 | else if (r_m.GetScale() == 2) ss = 1; 160 | else if (r_m.GetScale() == 4) ss = 2; 161 | else if (r_m.GetScale() == 8) ss = 3; 162 | else JITASM_ASSERT(0); 163 | if (index != INVALID && base != INVALID) 164 | { 165 | db(ss << 6 | index << 3 | base); 166 | } 167 | else if (base != INVALID) 168 | { 169 | db(ss << 6 | 4 << 3 | base); 170 | } 171 | else if (index != INVALID) 172 | { 173 | db(ss << 6 | index << 3 | 5); 174 | } 175 | } 176 | 177 | // Displacement 178 | if (mod == 0 && sib && base == INVALID) dd(r_m.GetDisp()); 179 | if (mod == 1) db(r_m.GetDisp()); 180 | if (mod == 2) dd(r_m.GetDisp()); 181 | } 182 | } 183 | } 184 | 185 | void EncodeOpcode(uint32 opcode) 186 | { 187 | if (opcode & 0xFF000000) db((opcode >> 24) & 0xFF); 188 | if (opcode & 0xFFFF0000) db((opcode >> 16) & 0xFF); 189 | if (opcode & 0xFFFFFF00) db((opcode >> 8) & 0xFF); 190 | /**********************/ db((opcode >> 0) & 0xFF); 191 | } 192 | 193 | void EncodeImm(detail::Opd const & imm) 194 | { 195 | auto const size = imm.GetSize(); 196 | /**/ if (size == O_SIZE_8) db(imm.GetImm()); 197 | else if (size == O_SIZE_16) dw(imm.GetImm()); 198 | else if (size == O_SIZE_32) dd(imm.GetImm()); 199 | else if (size == O_SIZE_64) dq(imm.GetImm()); 200 | } 201 | 202 | void EncodeSource(detail::Opd const & imm) 203 | { 204 | AddBookmark(size_, uint64(imm.GetImm())); 205 | } 206 | 207 | void EncodeMultiNop(detail::Opd const & imm) 208 | { 209 | size_t align = 1ULL << size_t(imm.GetImm()); 210 | size_t bytes = ((size_ + align - 1) & size_t(-intptr_t(align))) - size_; 211 | while (bytes > 0) 212 | { 213 | size_t size = bytes < 16 ? bytes : 16; 214 | bytes -= size; 215 | switch (size) 216 | { 217 | case 0: break; 218 | case 1: PutBytes("\x90", 1); break; 219 | case 2: PutBytes("\x66\x90", 2); break; 220 | case 3: PutBytes("\x0f\x1f\x00", 3); break; 221 | case 4: PutBytes("\x0f\x1f\x40\x00", 4); break; 222 | case 5: PutBytes("\x0f\x1f\x44\x00\x00", 5); break; 223 | case 6: PutBytes("\x66\x0f\x1f\x44\x00\x00", 6); break; 224 | case 7: PutBytes("\x0f\x1f\x80\x00\x00\x00\x00", 7); break; 225 | case 8: PutBytes("\x0f\x1f\x84\x00\x00\x00\x00\x00", 8); break; 226 | case 9: PutBytes("\x66\x0f\x1f\x84\x00\x00\x00\x00\x00", 9); break; 227 | case 10: 228 | more_10: PutBytes("\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00", 10); break; 229 | case 11: 230 | case 12: 231 | case 13: 232 | case 14: 233 | case 15: 234 | default: PutBytes("\x66\x66\x66\x66\x66\x66", size - 10); goto more_10; 235 | } 236 | } 237 | } 238 | 239 | void Encode(Instr const & instr) 240 | { 241 | uint32 opcode = instr.opcode_; 242 | 243 | auto const & opd0 = instr.GetOpd(0).IsDummy() ? detail::Opd() : instr.GetOpd(0); 244 | auto const & opd1 = instr.GetOpd(1).IsDummy() ? detail::Opd() : instr.GetOpd(1); 245 | auto const & opd2 = instr.GetOpd(2).IsDummy() ? detail::Opd() : instr.GetOpd(2); 246 | auto const & opd3 = instr.GetOpd(3).IsDummy() ? detail::Opd() : instr.GetOpd(3); 247 | 248 | // +rb, +rw, +rd, +ro 249 | if (opd0.IsReg() && (opd1.IsNone() || opd1.IsImm())) 250 | { 251 | opcode += opd0.GetReg().id & 0x7; 252 | } 253 | 254 | if ((opd0.IsImm() || opd0.IsReg()) && (opd1.IsReg() || opd1.IsMem())) 255 | { // ModR/M 256 | auto const & reg = opd0; 257 | auto const & r_m = opd1; 258 | auto const & vex = opd2; 259 | EncodePrefixes(instr.encoding_flags_, reg, r_m, vex); 260 | EncodeOpcode(opcode); 261 | EncodeModRM((uint8)(reg.IsImm() ? reg.GetImm() : reg.GetReg().id), r_m); 262 | 263 | // /is4 264 | if (opd3.IsReg()) 265 | { 266 | EncodeImm(Imm8(static_cast(opd3.GetReg().id << 4))); 267 | } 268 | } 269 | else 270 | { 271 | auto const & reg = detail::Opd(); 272 | auto const & r_m = opd0.IsReg() ? opd0 : detail::Opd(); 273 | auto const & vex = detail::Opd(); 274 | EncodePrefixes(instr.encoding_flags_, reg, r_m, vex); 275 | EncodeOpcode(opcode); 276 | } 277 | 278 | if (opd0.IsImm() && !opd1.IsReg() && !opd1.IsMem()) EncodeImm(opd0); 279 | if (opd1.IsImm()) EncodeImm(opd1); 280 | if (opd2.IsImm()) EncodeImm(opd2); 281 | if (opd3.IsImm()) EncodeImm(opd3); 282 | } 283 | 284 | void EncodeInstr(Instr & instr); 285 | 286 | #ifdef JITASM_TEST 287 | void TestInstr(InstrID id, std::vector< Instr > & list, bool is64); 288 | #endif 289 | 290 | void Assemble(Instr & instr) 291 | { 292 | if (0 == (instr.encoding_flags_ & E_ENCODED)) 293 | { 294 | EncodeInstr(instr); 295 | } 296 | 297 | switch (instr.GetID()) 298 | { 299 | case I_ALIGN: EncodeMultiNop(instr.GetOpd(0)); break; 300 | case I_NULL: break; 301 | case I_SOURCE: EncodeSource(instr.GetOpd(0)); break; 302 | case I_DB: db(instr.GetOpd(0).GetImm()); break; 303 | case I_DW: dw(instr.GetOpd(0).GetImm()); break; 304 | case I_DD: dd(instr.GetOpd(0).GetImm()); break; 305 | case I_DQ: dq(instr.GetOpd(0).GetImm()); break; 306 | default: Encode(instr); break; 307 | } 308 | } 309 | }; 310 | } 311 | } 312 | #endif // jitasm_Backend_x86_h__ -------------------------------------------------------------------------------- /jitasm.Backend.x86_32.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_Backend_x86_32_h__ 3 | #define jitasm_Backend_x86_32_h__ 4 | #include "jitasm.x86_32.h" 5 | #include "jitasm.Backend.x86.h" 6 | namespace jitasm 7 | { 8 | namespace x86_32 9 | { 10 | struct Backend : jitasm::x86::Backend 11 | { 12 | Backend(void * buffaddr = nullptr, size_t buffsize = 0) : jitasm::x86::Backend(false, buffaddr, buffsize) 13 | { 14 | } 15 | }; 16 | } 17 | } 18 | #endif // jitasm_Backend_x86_32_h__ -------------------------------------------------------------------------------- /jitasm.Backend.x86_64.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_Backend_x86_64_h__ 3 | #define jitasm_Backend_x86_64_h__ 4 | #include "jitasm.x86_64.h" 5 | #include "jitasm.Backend.x86.h" 6 | namespace jitasm 7 | { 8 | namespace x86_64 9 | { 10 | struct Backend : jitasm::x86::Backend 11 | { 12 | Backend(void * buffaddr = nullptr, size_t buffsize = 0) : jitasm::x86::Backend(true, buffaddr, buffsize) 13 | { 14 | } 15 | }; 16 | } 17 | } 18 | #endif // jitasm_Backend_x86_64_h__ -------------------------------------------------------------------------------- /jitasm.CodeBuffer.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_CodeBuffer_h__ 3 | #define jitasm_CodeBuffer_h__ 4 | #include "jitasm.h" 5 | namespace jitasm 6 | { 7 | template < typename Derived > class CodeBuffer$CRTP /* using Curiously Recurring Template Pattern */ 8 | { 9 | protected: 10 | void * buffaddr_; 11 | size_t codesize_; 12 | size_t buffsize_; 13 | 14 | Derived & derived() 15 | { 16 | return *static_cast(this); 17 | } 18 | 19 | Derived const & derived() const 20 | { 21 | return *static_cast(this); 22 | } 23 | 24 | public: 25 | CodeBuffer$CRTP() : buffaddr_(nullptr), codesize_(0), buffsize_(0) 26 | { 27 | } 28 | ~CodeBuffer$CRTP() 29 | { 30 | ResetBuffer(0); 31 | } 32 | 33 | void * GetBufferPointer() const 34 | { 35 | return buffaddr_; 36 | } 37 | size_t GetBufferCapacity() const 38 | { 39 | return buffsize_; 40 | } 41 | size_t GetBufferSize() const 42 | { 43 | return codesize_; 44 | } 45 | 46 | bool ResetBuffer(size_t codesize) 47 | { 48 | bool result = true; 49 | if (buffaddr_) 50 | { 51 | result = derived().FreeBuffer(); 52 | if (result) 53 | { 54 | buffaddr_ = nullptr; 55 | codesize_ = 0; 56 | buffsize_ = 0; 57 | } 58 | } 59 | if (result && codesize) 60 | { 61 | result = derived().AllocateBuffer(codesize); 62 | if (result) 63 | { 64 | codesize_ = codesize; 65 | } 66 | } 67 | return result; 68 | } 69 | }; 70 | } 71 | #endif // jitasm_CodeBuffer_h__ 72 | -------------------------------------------------------------------------------- /jitasm.Frontend.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_Frontend_h__ 3 | #define jitasm_Frontend_h__ 4 | #include "jitasm.h" 5 | #include "jitasm.CodeBuffer.h" 6 | namespace jitasm 7 | { 8 | class Frontend 9 | { 10 | protected: 11 | virtual ~Frontend() 12 | { 13 | } 14 | 15 | virtual void Assemble() = 0; 16 | }; 17 | 18 | template < typename Derived > struct Frontend$CRTP : Frontend /* using Curiously Recurring Template Pattern */ 19 | { 20 | Derived & derived() 21 | { 22 | return *static_cast(this); 23 | } 24 | 25 | Derived const & derived() const 26 | { 27 | return *static_cast(this); 28 | } 29 | 30 | struct Label 31 | { 32 | sint32 key; 33 | size_t instr; 34 | explicit Label(sint32 key) : key(key), instr(0) {} 35 | }; 36 | typedef std::deque< Label > LabelList; 37 | 38 | bool assembled_; 39 | LabelList labels_; 40 | 41 | Frontend$CRTP() : assembled_(false) 42 | { 43 | } 44 | 45 | void * GetCodePointer() 46 | { 47 | if (!assembled_) 48 | { 49 | Assemble(); 50 | } 51 | return derived().GetBufferPointer(); 52 | } 53 | 54 | size_t GetCodeSize() 55 | { 56 | return derived().GetBufferSize(); 57 | } 58 | 59 | size_t NewLabelID(sint32 label_key) 60 | { 61 | labels_.push_back(Label(label_key)); 62 | return labels_.size() - 1; 63 | } 64 | 65 | size_t CheckLabelID(sint32 label_key) 66 | { 67 | for (size_t i = 0; i < labels_.size(); i++) 68 | { 69 | if (labels_[i].key == label_key) 70 | { 71 | return i; 72 | } 73 | } 74 | return (size_t)-1; 75 | } 76 | 77 | size_t GetLabelID(sint32 label_key) 78 | { 79 | for (auto const & label : labels) 80 | { 81 | if (label.key == label_key) 82 | { 83 | return i; 84 | } 85 | } 86 | return NewLabelID(label_key); 87 | } 88 | 89 | void SetLabelID(size_t label_id) 90 | { 91 | labels_[label_id].instr = instrs_.size(); 92 | } 93 | 94 | void L(sint32 label_key) 95 | { 96 | SetLabelID(GetLabelID(label_key)); 97 | } 98 | }; 99 | } 100 | #endif // jitasm_Frontend_h__ 101 | -------------------------------------------------------------------------------- /jitasm.Frontend.x86_32.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_Frontend_x86_32_h__ 3 | #define jitasm_Frontend_x86_32_h__ 4 | #include "jitasm.x86.h" 5 | #include "jitasm.x86_32.h" 6 | #include "jitasm.Frontend.x86.h" 7 | namespace jitasm 8 | { 9 | namespace x86_32 10 | { 11 | using namespace jitasm::x86; 12 | 13 | namespace detail 14 | { 15 | using namespace jitasm::detail; 16 | 17 | /** 18 | * Stack layout 19 | * \verbatim 20 | * +-----------------------+ 21 | * | Caller return address | 22 | * +=======================+======== 23 | * | ebp (rbp) | 24 | * +-----------------------+ <-- ebp (rbp) 25 | * | Saved gp registers | 26 | * +-----------------------+ 27 | * | Padding for alignment | 28 | * +-----------------------+ <-- Stack base 29 | * | Spill slots and | 30 | * | local variable | 31 | * +-----------------------+ <-- esp (rsp) 32 | * \endverbatim 33 | */ 34 | class StackManager 35 | { 36 | private: 37 | Addr stack_base_; 38 | uint32 stack_size_; 39 | 40 | public: 41 | StackManager() : stack_base_(RegID::CreatePhysicalRegID(R_TYPE_GP, EBX), 0), stack_size_(0) {} 42 | 43 | /// Get allocated stack size 44 | uint32 GetSize() const { return (stack_size_ + 15) / 16 * 16; /* 16 bytes aligned*/ } 45 | 46 | /// Get stack base 47 | Addr GetStackBase() const { return stack_base_; } 48 | 49 | /// Set stack base 50 | void SetStackBase(const Addr& stack_base) { stack_base_ = stack_base; } 51 | 52 | /// Allocate stack 53 | Addr Alloc(uint32 size, uint32 alignment) 54 | { 55 | stack_size_ = (stack_size_ + alignment - 1) / alignment * alignment; 56 | stack_size_ += size; 57 | return stack_base_ - stack_size_; 58 | } 59 | }; 60 | } 61 | 62 | template < typename Derived > struct Frontend$CRTP : jitasm::x86::Frontend$CRTP< Derived > /* using Curiously Recurring Template Pattern */ 63 | { 64 | typedef jitasm::x86::Addr32 Addr; 65 | typedef jitasm::x86::Reg32 Reg; 66 | 67 | AddressingPtr byte_ptr; 68 | AddressingPtr word_ptr; 69 | AddressingPtr dword_ptr; 70 | AddressingPtr qword_ptr; 71 | AddressingPtr mmword_ptr; 72 | AddressingPtr xmmword_ptr; 73 | AddressingPtr ymmword_ptr; 74 | AddressingPtr real4_ptr; 75 | AddressingPtr real8_ptr; 76 | AddressingPtr real10_ptr; 77 | AddressingPtr m2byte_ptr; 78 | AddressingPtr m28byte_ptr; 79 | AddressingPtr m108byte_ptr; 80 | AddressingPtr m512byte_ptr; 81 | 82 | Reg zax, zcx, zdx, zbx, zsp, zbp, zsi, zdi; 83 | AddressingPtr ptr; 84 | 85 | detail::StackManager stack_manager_; 86 | 87 | Frontend$CRTP() 88 | : jitasm::x86::Frontend$CRTP< Derived >(false), 89 | 90 | zax(EAX), 91 | zcx(ECX), 92 | zdx(EDX), 93 | zbx(EBX), 94 | zsp(ESP), 95 | zbp(EBP), 96 | zsi(ESI), 97 | zdi(EDI) 98 | { 99 | } 100 | virtual ~Frontend$CRTP() 101 | { 102 | } 103 | 104 | ///////////// 105 | 106 | void aaa(Reg16 const & a1 = ax) { AppendInstr(I_AAA, a1); } 107 | 108 | void aad(Reg16 const & a1 = ax, Imm8 const & a2 = Imm8(5)) { AppendInstr(I_AAD, a1, a2); } 109 | 110 | void aam(Reg16 const & a1 = ax, Imm8 const & a2 = Imm8(5)) { AppendInstr(I_AAM, a1, a2); } 111 | 112 | void aas(Reg16 const & a1 = ax) { AppendInstr(I_AAS, a1); } 113 | 114 | void arpl(Mem16 const & a1, Reg16 const & a2) { AppendInstr(I_ARPL, a1, a2); } 115 | 116 | void bound(Reg16 const & a1, Mem32 const & a2) { AppendInstr(I_BOUND, a1, a2); } 117 | void bound(Reg32 const & a1, Mem64 const & a2) { AppendInstr(I_BOUND, a1, a2); } 118 | 119 | 120 | }; 121 | } 122 | } 123 | #endif // jitasm_Frontend_x86_32_h__ -------------------------------------------------------------------------------- /jitasm.Frontend.x86_64.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_Frontend_x86_64_h__ 3 | #define jitasm_Frontend_x86_x64_h__ 4 | #include "jitasm.x86.h" 5 | #include "jitasm.x86_64.h" 6 | #include "jitasm.Frontend.x86.h" 7 | namespace jitasm 8 | { 9 | namespace x86_64 10 | { 11 | namespace detail 12 | { 13 | using namespace jitasm::detail; 14 | 15 | /** 16 | * Stack layout 17 | * \verbatim 18 | * +-----------------------+ 19 | * | Caller return address | 20 | * +=======================+======== 21 | * | ebp (rbp) | 22 | * +-----------------------+ <-- ebp (rbp) 23 | * | Saved gp registers | 24 | * +-----------------------+ 25 | * | Padding for alignment | 26 | * +-----------------------+ <-- Stack base 27 | * | Spill slots and | 28 | * | local variable | 29 | * +-----------------------+ <-- esp (rsp) 30 | * \endverbatim 31 | */ 32 | class StackManager 33 | { 34 | private: 35 | Addr stack_base_; 36 | uint32 stack_size_; 37 | 38 | public: 39 | StackManager() : stack_base_(RegID::CreatePhysicalRegID(R_TYPE_GP, EBX), 0), stack_size_(0) {} 40 | 41 | /// Get allocated stack size 42 | uint32 GetSize() const { return (stack_size_ + 15) / 16 * 16; /* 16 bytes aligned*/ } 43 | 44 | /// Get stack base 45 | Addr GetStackBase() const { return stack_base_; } 46 | 47 | /// Set stack base 48 | void SetStackBase(const Addr& stack_base) { stack_base_ = stack_base; } 49 | 50 | /// Allocate stack 51 | Addr Alloc(uint32 size, uint32 alignment) 52 | { 53 | stack_size_ = (stack_size_ + alignment - 1) / alignment * alignment; 54 | stack_size_ += size; 55 | return stack_base_ - stack_size_; 56 | } 57 | }; 58 | } 59 | 60 | template < typename Derived > struct Frontend$CRTP : jitasm::x86::Frontend$CRTP< Derived > /* using Curiously Recurring Template Pattern */ 61 | { 62 | typedef jitasm::x86::Addr64 Addr; 63 | typedef jitasm::x86::Reg64 Reg; 64 | 65 | Reg8 r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b; 66 | Reg16 r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w; 67 | Reg32 r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d; 68 | Reg64 rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15; 69 | XmmReg xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15; 70 | YmmReg ymm8, ymm9, ymm10, ymm11, ymm12, ymm13, ymm14, ymm15; 71 | Reg zax, zcx, zdx, zbx, zsp, zbp, zsi, zdi; 72 | 73 | AddressingPtr byte_ptr; 74 | AddressingPtr word_ptr; 75 | AddressingPtr dword_ptr; 76 | AddressingPtr qword_ptr; 77 | AddressingPtr mmword_ptr; 78 | AddressingPtr xmmword_ptr; 79 | AddressingPtr ymmword_ptr; 80 | AddressingPtr real4_ptr; 81 | AddressingPtr real8_ptr; 82 | AddressingPtr real10_ptr; 83 | AddressingPtr m2byte_ptr; 84 | AddressingPtr m28byte_ptr; 85 | AddressingPtr m108byte_ptr; 86 | AddressingPtr m512byte_ptr; 87 | 88 | AddressingPtr ptr; 89 | 90 | detail::StackManager stack_manager_; 91 | 92 | template < typename OpdN > struct RipPtr : AddressingPtr < OpdN > 93 | { 94 | Mem$< OpdN > operator[](uint32_t label_name) 95 | { 96 | Mem$< OpdN > result(O_SIZE_64, O_SIZE_64, RegID::CreatePhysicalRegID(R_TYPE_IP, RIP), RegID::Invalid(), 0, 0); 97 | switch (result.GetSize()) 98 | { 99 | case O_SIZE_8: return result[((Frontend*)((char*)this - offsetof(Frontend, byte_rip_ptr)))->GetLabelID(label_name)]; 100 | case O_SIZE_16: return result[((Frontend*)((char*)this - offsetof(Frontend, word_rip_ptr)))->GetLabelID(label_name)]; 101 | case O_SIZE_32: return result[((Frontend*)((char*)this - offsetof(Frontend, dword_rip_ptr)))->GetLabelID(label_name)]; 102 | case O_SIZE_64: return result[((Frontend*)((char*)this - offsetof(Frontend, qword_rip_ptr)))->GetLabelID(label_name)]; 103 | case O_SIZE_128: return result[((Frontend*)((char*)this - offsetof(Frontend, xmmword_rip_ptr)))->GetLabelID(label_name)]; 104 | case O_SIZE_256: return result[((Frontend*)((char*)this - offsetof(Frontend, ymmword_rip_ptr)))->GetLabelID(label_name)]; 105 | } 106 | return result; 107 | } 108 | }; 109 | 110 | RipPtr< Opd8 > byte_rip_ptr; 111 | RipPtr< Opd16 > word_rip_ptr; 112 | RipPtr< Opd32 > dword_rip_ptr; 113 | RipPtr< Opd64 > qword_rip_ptr, rip_ptr; 114 | RipPtr< Opd128 > xmmword_rip_ptr; 115 | RipPtr< Opd256 > ymmword_rip_ptr; 116 | 117 | Frontend$CRTP() 118 | : jitasm::x86::Frontend$CRTP< Derived >(true), 119 | 120 | r8b(R8B), 121 | r9b(R9B), 122 | r10b(R10B), 123 | r11b(R11B), 124 | r12b(R12B), 125 | r13b(R13B), 126 | r14b(R14B), 127 | r15b(R15B), 128 | r8w(R8W), 129 | r9w(R9W), 130 | r10w(R10W), 131 | r11w(R11W), 132 | r12w(R12W), 133 | r13w(R13W), 134 | r14w(R14W), 135 | r15w(R15W), 136 | r8d(R8D), 137 | r9d(R9D), 138 | r10d(R10D), 139 | r11d(R11D), 140 | r12d(R12D), 141 | r13d(R13D), 142 | r14d(R14D), 143 | r15d(R15D), 144 | rax(RAX), 145 | rcx(RCX), 146 | rdx(RDX), 147 | rbx(RBX), 148 | rsp(RSP), 149 | rbp(RBP), 150 | rsi(RSI), 151 | rdi(RDI), 152 | r8(R8), 153 | r9(R9), 154 | r10(R10), 155 | r11(R11), 156 | r12(R12), 157 | r13(R13), 158 | r14(R14), 159 | r15(R15), 160 | xmm8(XMM8), 161 | xmm9(XMM9), 162 | xmm10(XMM10), 163 | xmm11(XMM11), 164 | xmm12(XMM12), 165 | xmm13(XMM13), 166 | xmm14(XMM14), 167 | xmm15(XMM15), 168 | ymm8(YMM8), 169 | ymm9(YMM9), 170 | ymm10(YMM10), 171 | ymm11(YMM11), 172 | ymm12(YMM12), 173 | ymm13(YMM13), 174 | ymm14(YMM14), 175 | ymm15(YMM15), 176 | zax(RAX), 177 | zcx(RCX), 178 | zdx(RDX), 179 | zbx(RBX), 180 | zsp(RSP), 181 | zbp(RBP), 182 | zsi(RSI), 183 | zdi(RDI) 184 | { 185 | } 186 | virtual ~Frontend$CRTP() 187 | { 188 | } 189 | 190 | ///////////// 191 | 192 | void adc(Reg64 const & a1, Imm32 const & a2) { AppendInstr(I_ADC, a1, a2); } 193 | void adc(Mem64 const & a1, Imm32 const & a2) { AppendInstr(I_ADC, a1, a2); } 194 | void adc(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_ADC, a1, a2); } 195 | void adc(Reg64 const & a1, Mem64 const & a2) { AppendInstr(I_ADC, a1, a2); } 196 | void adc(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_ADC, a1, a2); } 197 | 198 | void add(Reg64 const & a1, Imm32 const & a2) { AppendInstr(I_ADD, a1, a2); } 199 | void add(Mem64 const & a1, Imm32 const & a2) { AppendInstr(I_ADD, a1, a2); } 200 | void add(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_ADD, a1, a2); } 201 | void add(Reg64 const & a1, Mem64 const & a2) { AppendInstr(I_ADD, a1, a2); } 202 | void add(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_ADD, a1, a2); } 203 | 204 | void and(Reg64 const & a1, Imm32 const & a2) { AppendInstr(I_AND, a1, a2); } 205 | void and(Mem64 const & a1, Imm32 const & a2) { AppendInstr(I_AND, a1, a2); } 206 | void and(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_AND, a1, a2); } 207 | void and(Reg64 const & a1, Mem64 const & a2) { AppendInstr(I_AND, a1, a2); } 208 | void and(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_AND, a1, a2); } 209 | 210 | void bsf(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_BSF, a1, a2); } 211 | void bsf(Reg64 const & a1, Mem64 const & a2) { AppendInstr(I_BSF, a1, a2); } 212 | 213 | void bsr(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_BSR, a1, a2); } 214 | void bsr(Reg64 const & a1, Mem64 const & a2) { AppendInstr(I_BSR, a1, a2); } 215 | 216 | void bswap(Reg64 const & a1) { AppendInstr(I_BSWAP, a1); } 217 | 218 | void bt(Reg64 const & a1, Imm8 const & a2) { AppendInstr(I_BT, a1, a2); } 219 | void bt(Mem64 const & a1, Imm8 const & a2) { AppendInstr(I_BT, a1, a2); } 220 | void bt(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_BT, a1, a2); } 221 | void bt(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_BT, a1, a2); } 222 | 223 | void btc(Reg64 const & a1, Imm8 const & a2) { AppendInstr(I_BTC, a1, a2); } 224 | void btc(Mem64 const & a1, Imm8 const & a2) { AppendInstr(I_BTC, a1, a2); } 225 | void btc(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_BTC, a1, a2); } 226 | void btc(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_BTC, a1, a2); } 227 | 228 | void btr(Reg64 const & a1, Imm8 const & a2) { AppendInstr(I_BTR, a1, a2); } 229 | void btr(Mem64 const & a1, Imm8 const & a2) { AppendInstr(I_BTR, a1, a2); } 230 | void btr(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_BTR, a1, a2); } 231 | void btr(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_BTR, a1, a2); } 232 | 233 | void bts(Reg64 const & a1, Imm8 const & a2) { AppendInstr(I_BTS, a1, a2); } 234 | void bts(Mem64 const & a1, Imm8 const & a2) { AppendInstr(I_BTS, a1, a2); } 235 | void bts(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_BTS, a1, a2); } 236 | void bts(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_BTS, a1, a2); } 237 | 238 | void cdqe() { AppendInstr(I_CDQE); } 239 | 240 | void cmovcc(ConditionCode cc, Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, cc, a1, a2); } 241 | void cmovcc(ConditionCode cc, Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, cc, a1, a2); } 242 | void cmovo(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_O, a1, a2); } 243 | void cmovo(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_O, a1, a2); } 244 | void cmovno(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NO, a1, a2); } 245 | void cmovno(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NO, a1, a2); } 246 | void cmovb(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_B, a1, a2); } 247 | void cmovb(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_B, a1, a2); } 248 | void cmovc(Reg64 const & a1, Reg64 const & a2) { cmovb(a1, a2); } 249 | void cmovc(Reg64 const & a1, Mem64 const & a2) { cmovb(a1, a2); } 250 | void cmovnae(Reg64 const & a1, Reg64 const & a2) { cmovb(a1, a2); } 251 | void cmovnae(Reg64 const & a1, Mem64 const & a2) { cmovb(a1, a2); } 252 | void cmovae(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_AE, a1, a2); } 253 | void cmovae(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_AE, a1, a2); } 254 | void cmovnb(Reg64 const & a1, Reg64 const & a2) { cmovae(a1, a2); } 255 | void cmovnb(Reg64 const & a1, Mem64 const & a2) { cmovae(a1, a2); } 256 | void cmovnc(Reg64 const & a1, Reg64 const & a2) { cmovae(a1, a2); } 257 | void cmovnc(Reg64 const & a1, Mem64 const & a2) { cmovae(a1, a2); } 258 | void cmove(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_E, a1, a2); } 259 | void cmove(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_E, a1, a2); } 260 | void cmovz(Reg64 const & a1, Reg64 const & a2) { cmove(a1, a2); } 261 | void cmovz(Reg64 const & a1, Mem64 const & a2) { cmove(a1, a2); } 262 | void cmovne(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NE, a1, a2); } 263 | void cmovne(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NE, a1, a2); } 264 | void cmovnz(Reg64 const & a1, Reg64 const & a2) { cmovne(a1, a2); } 265 | void cmovnz(Reg64 const & a1, Mem64 const & a2) { cmovne(a1, a2); } 266 | void cmovbe(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_BE, a1, a2); } 267 | void cmovbe(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_BE, a1, a2); } 268 | void cmovna(Reg64 const & a1, Reg64 const & a2) { cmovbe(a1, a2); } 269 | void cmovna(Reg64 const & a1, Mem64 const & a2) { cmovbe(a1, a2); } 270 | void cmova(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_A, a1, a2); } 271 | void cmova(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_A, a1, a2); } 272 | void cmovnbe(Reg64 const & a1, Reg64 const & a2) { cmova(a1, a2); } 273 | void cmovnbe(Reg64 const & a1, Mem64 const & a2) { cmova(a1, a2); } 274 | void cmovs(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_S, a1, a2); } 275 | void cmovs(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_S, a1, a2); } 276 | void cmovns(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NS, a1, a2); } 277 | void cmovns(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NS, a1, a2); } 278 | void cmovp(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_P, a1, a2); } 279 | void cmovp(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_P, a1, a2); } 280 | void cmovnpe(Reg64 const & a1, Reg64 const & a2) { cmovp(a1, a2); } 281 | void cmovnpe(Reg64 const & a1, Mem64 const & a2) { cmovp(a1, a2); } 282 | void cmovnp(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NP, a1, a2); } 283 | void cmovnp(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_NP, a1, a2); } 284 | void cmovnpo(Reg64 const & a1, Reg64 const & a2) { cmovnp(a1, a2); } 285 | void cmovnpo(Reg64 const & a1, Mem64 const & a2) { cmovnp(a1, a2); } 286 | void cmovge(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_GE, a1, a2); } 287 | void cmovge(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_GE, a1, a2); } 288 | void cmovnl(Reg64 const & a1, Reg64 const & a2) { cmovge(a1, a2); } 289 | void cmovnl(Reg64 const & a1, Mem64 const & a2) { cmovge(a1, a2); } 290 | void cmovle(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_LE, a1, a2); } 291 | void cmovle(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_LE, a1, a2); } 292 | void cmovng(Reg64 const & a1, Reg64 const & a2) { cmovle(a1, a2); } 293 | void cmovng(Reg64 const & a1, Mem64 const & a2) { cmovle(a1, a2); } 294 | void cmovg(Reg64 const & a1, Reg64 const & a2) { AppendCondInstr(I_CMOVCC, CC_G, a1, a2); } 295 | void cmovg(Reg64 const & a1, Mem64 const & a2) { AppendCondInstr(I_CMOVCC, CC_G, a1, a2); } 296 | void cmovnle(Reg64 const & a1, Reg64 const & a2) { cmovg(a1, a2); } 297 | void cmovnle(Reg64 const & a1, Mem64 const & a2) { cmovg(a1, a2); } 298 | 299 | void cmp(Reg64 const & a1, Imm32 const & a2) { AppendInstr(I_CMP, a1, a2); } 300 | void cmp(Mem64 const & a1, Imm32 const & a2) { AppendInstr(I_CMP, a1, a2); } 301 | void cmp(Reg64 const & a1, Reg64 const & a2) { AppendInstr(I_CMP, a1, a2); } 302 | void cmp(Reg64 const & a1, Mem64 const & a2) { AppendInstr(I_CMP, a1, a2); } 303 | void cmp(Mem64 const & a1, Reg64 const & a2) { AppendInstr(I_CMP, a1, a2); } 304 | 305 | void cqo() { AppendInstr(I_CQO); } 306 | 307 | }; 308 | } 309 | } 310 | #endif // jitasm_Frontend_xx86_64_h__ 311 | -------------------------------------------------------------------------------- /jitasm.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_h__ 3 | #define jitasm_h__ 4 | 5 | #define JITASM_TEST 6 | 7 | #if defined(_WIN32) 8 | #define JITASM_WIN // Windows 9 | #endif 10 | 11 | #if (defined(_WIN64) && (defined(_M_AMD64) || defined(_M_X64))) || defined(__x86_64__) 12 | #define JITASM_X64 13 | #endif 14 | 15 | #if defined(__GNUC__) 16 | #define JITASM_GCC 17 | #endif 18 | 19 | #if !defined(JITASM_MMINTRIN) 20 | #if !defined(__GNUC__) || defined(__MMX__) 21 | #define JITASM_MMINTRIN 1 22 | #else 23 | #define JITASM_MMINTRIN 0 24 | #endif 25 | #endif 26 | #if !defined(JITASM_XMMINTRIN) 27 | #if !defined(__GNUC__) || defined(__SSE__) 28 | #define JITASM_XMMINTRIN 1 29 | #else 30 | #define JITASM_XMMINTRIN 0 31 | #endif 32 | #endif 33 | #if !defined(JITASM_EMMINTRIN) 34 | #if !defined(__GNUC__) || defined(__SSE2__) 35 | #define JITASM_EMMINTRIN 1 36 | #else 37 | #define JITASM_EMMINTRIN 0 38 | #endif 39 | #endif 40 | 41 | 42 | #include 43 | #include 44 | #include 45 | #include 46 | #include 47 | #include 48 | #include 49 | #include 50 | 51 | #if defined(JITASM_WIN) 52 | #include 53 | #else 54 | #include 55 | #include 56 | #include 57 | #endif 58 | 59 | #if JITASM_MMINTRIN 60 | #include 61 | #endif 62 | #if JITASM_XMMINTRIN 63 | #include 64 | #endif 65 | #if JITASM_EMMINTRIN 66 | #include 67 | #endif 68 | 69 | #if _MSC_VER >= 1400 // VC8 or later 70 | #include 71 | #endif 72 | 73 | #if defined(JITASM_GCC) 74 | #define JITASM_ATTRIBUTE_WEAK __attribute__((weak)) 75 | #elif defined(_MSC_VER) 76 | #define JITASM_ATTRIBUTE_WEAK __declspec(selectany) 77 | #else 78 | #define JITASM_ATTRIBUTE_WEAK 79 | #endif 80 | 81 | #if defined(_MSC_VER) 82 | #pragma warning( push ) 83 | #pragma warning( disable : 4127 ) // conditional expression is constant. 84 | #pragma warning( disable : 4201 ) // nonstandard extension used : nameless struct/union 85 | #endif 86 | 87 | #ifdef ASSERT 88 | #define JITASM_ASSERT ASSERT 89 | #else 90 | #include 91 | //#define JITASM_ASSERT assert 92 | #define JITASM_ASSERT(x) x 93 | #endif 94 | 95 | //#define JITASM_DEBUG_DUMP 96 | #ifdef JITASM_DEBUG_DUMP 97 | #include 98 | #if defined(JITASM_GCC) 99 | #define JITASM_TRACE printf 100 | #else 101 | #define JITASM_TRACE jitasm::detail::Trace 102 | #endif 103 | #elif defined(JITASM_GCC) 104 | #define JITASM_TRACE(...) ((void)0) 105 | #else 106 | #define JITASM_TRACE __noop 107 | #endif 108 | 109 | #include 110 | #include 111 | 112 | namespace jitasm 113 | { 114 | typedef int8_t sint8; 115 | typedef int16_t sint16; 116 | typedef int32_t sint32; 117 | typedef int64_t sint64; 118 | typedef uint8_t uint8; 119 | typedef uint16_t uint16; 120 | typedef uint32_t uint32; 121 | typedef uint64_t uint64; 122 | 123 | template< typename T > inline void avoid_unused_warn(T const &) {} 124 | 125 | namespace detail 126 | { 127 | inline void * aligned_malloc(size_t size, size_t alignment) 128 | { 129 | #ifdef __MINGW32__ 130 | return __mingw_aligned_malloc(size, alignment); 131 | #elif defined(_MSC_VER) 132 | return _aligned_malloc(size, alignment); 133 | #else 134 | void * p; 135 | int ret = posix_memalign(&p, alignment, size); 136 | return (ret == 0) ? p : 0; 137 | #endif 138 | } 139 | 140 | inline void aligned_free(void * p) 141 | { 142 | #ifdef __MINGW32__ 143 | __mingw_aligned_free(p); 144 | #elif defined(_MSC_VER) 145 | _aligned_free(p); 146 | #else 147 | free(p); 148 | #endif 149 | } 150 | 151 | /// Counting 1-Bits 152 | inline uint32 count_1_bits(uint32 x) 153 | { 154 | x = x - ((x >> 1) & 0x55555555); 155 | x = (x & 0x33333333) + ((x >> 2) & 0x33333333); 156 | x = (x + (x >> 4)) & 0x0F0F0F0F; 157 | x = x + (x >> 8); 158 | x = x + (x >> 16); 159 | return x & 0x0000003F; 160 | } 161 | 162 | /// The bit position of the first bit 1. 163 | inline uint32 bit_scan_forward(uint32 x) 164 | { 165 | #if defined(JITASM_GCC) 166 | return __builtin_ctz(x); 167 | #else 168 | unsigned long index; 169 | _BitScanForward(&index, x); 170 | return index; 171 | #endif 172 | } 173 | 174 | /// The bit position of the last bit 1. 175 | inline uint32 bit_scan_reverse(uint32 x) 176 | { 177 | #if defined(JITASM_GCC) 178 | return 31 - __builtin_clz(x); 179 | #else 180 | unsigned long index; 181 | _BitScanReverse(&index, x); 182 | return index; 183 | #endif 184 | } 185 | 186 | /// Prior iterator 187 | template< class It > It prior(It const & it) 188 | { 189 | It i = it; 190 | return --i; 191 | } 192 | 193 | /// Next iterator 194 | template< class It > It next(It const & it) 195 | { 196 | It i = it; 197 | return ++i; 198 | } 199 | 200 | /// Iterator range 201 | template< class T, class It = typename T::iterator > struct Range : std::pair < It, It > 202 | { 203 | typedef It Iterator; 204 | Range() : std::pair< It, It >() {} 205 | Range(It const & f, It const & s) : std::pair< It, It >(f, s) {} 206 | Range(T & container) : std::pair< It, It >(container.begin(), container.end()) {} 207 | bool empty() const { return this->first == this->second; } 208 | size_t size() const { return std::distance(this->first, this->second); } 209 | }; 210 | 211 | /// Const iterator range 212 | template< class T > struct ConstRange : Range < T, typename T::const_iterator > 213 | { 214 | ConstRange() : Range< T, typename T::const_iterator >() {} 215 | ConstRange(typename T::const_iterator const & f, typename T::const_iterator const & s) : Range< T, typename T::const_iterator >(f, s) {} 216 | ConstRange(T const & container) : Range< T, typename T::const_iterator >(container.begin(), container.end()) {} 217 | }; 218 | 219 | inline void append_num(std::string & str, size_t num) 220 | { 221 | if (num >= 10) 222 | { 223 | append_num(str, num / 10); 224 | } 225 | str.append(1, static_cast('0' + num % 10)); 226 | } 227 | 228 | #if defined(JITASM_DEBUG_DUMP) && defined(JITASM_WIN) 229 | /// Debug trace 230 | inline void Trace(const char *format, ...) 231 | { 232 | char szBuf[256]; 233 | va_list args; 234 | va_start(args, format); 235 | #if _MSC_VER >= 1400 // VC8 or later 236 | _vsnprintf_s(szBuf, sizeof(szBuf) / sizeof(char), format, args); 237 | #else 238 | vsnprintf(szBuf, sizeof(szBuf) / sizeof(char), format, args); 239 | #endif 240 | va_end(args); 241 | ::OutputDebugStringA(szBuf); 242 | } 243 | #endif 244 | } 245 | } 246 | 247 | #if defined(_MSC_VER) 248 | #pragma warning( pop ) 249 | #endif 250 | 251 | #endif // jitasm_h__ 252 | 253 | -------------------------------------------------------------------------------- /jitasm.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio 2013 4 | VisualStudioVersion = 12.0.31101.0 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "jitasm", "jitasm.vcxproj", "{A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}" 7 | EndProject 8 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test", "test\test.vcxproj", "{4EC7B156-8FE1-42D7-9598-236DC01BE727}" 9 | ProjectSection(ProjectDependencies) = postProject 10 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3} = {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3} 11 | EndProjectSection 12 | EndProject 13 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "yard", "yard\yard_vs2013_project\yard.vcxproj", "{86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}" 14 | EndProject 15 | Global 16 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 17 | Debug|Mixed Platforms = Debug|Mixed Platforms 18 | Debug|Win32 = Debug|Win32 19 | Debug|x64 = Debug|x64 20 | Release|Mixed Platforms = Release|Mixed Platforms 21 | Release|Win32 = Release|Win32 22 | Release|x64 = Release|x64 23 | EndGlobalSection 24 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 25 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Debug|Mixed Platforms.ActiveCfg = Debug|Win32 26 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Debug|Mixed Platforms.Build.0 = Debug|Win32 27 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Debug|Win32.ActiveCfg = Debug|Win32 28 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Debug|Win32.Build.0 = Debug|Win32 29 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Debug|x64.ActiveCfg = Debug|x64 30 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Debug|x64.Build.0 = Debug|x64 31 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Release|Mixed Platforms.ActiveCfg = Release|Win32 32 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Release|Mixed Platforms.Build.0 = Release|Win32 33 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Release|Win32.ActiveCfg = Release|Win32 34 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Release|Win32.Build.0 = Release|Win32 35 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Release|x64.ActiveCfg = Release|x64 36 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3}.Release|x64.Build.0 = Release|x64 37 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Debug|Mixed Platforms.ActiveCfg = Debug|Win32 38 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Debug|Mixed Platforms.Build.0 = Debug|Win32 39 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Debug|Win32.ActiveCfg = Debug|Win32 40 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Debug|Win32.Build.0 = Debug|Win32 41 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Debug|x64.ActiveCfg = Debug|x64 42 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Debug|x64.Build.0 = Debug|x64 43 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Release|Mixed Platforms.ActiveCfg = Release|Win32 44 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Release|Mixed Platforms.Build.0 = Release|Win32 45 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Release|Win32.ActiveCfg = Release|Win32 46 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Release|Win32.Build.0 = Release|Win32 47 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Release|x64.ActiveCfg = Release|x64 48 | {4EC7B156-8FE1-42D7-9598-236DC01BE727}.Release|x64.Build.0 = Release|x64 49 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Debug|Mixed Platforms.ActiveCfg = Debug|Win32 50 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Debug|Mixed Platforms.Build.0 = Debug|Win32 51 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Debug|Win32.ActiveCfg = Debug|Win32 52 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Debug|Win32.Build.0 = Debug|Win32 53 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Debug|x64.ActiveCfg = Debug|Win32 54 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Release|Mixed Platforms.ActiveCfg = Release|Win32 55 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Release|Mixed Platforms.Build.0 = Release|Win32 56 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Release|Win32.ActiveCfg = Release|Win32 57 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Release|Win32.Build.0 = Release|Win32 58 | {86D41A41-F407-4042-B1F7-FA2D7DB1E7D5}.Release|x64.ActiveCfg = Release|Win32 59 | EndGlobalSection 60 | GlobalSection(SolutionProperties) = preSolution 61 | HideSolutionNode = FALSE 62 | EndGlobalSection 63 | EndGlobal 64 | -------------------------------------------------------------------------------- /jitasm.vcxproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Debug 10 | x64 11 | 12 | 13 | Release 14 | Win32 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {A8B1E13C-9EC9-482A-A4BB-A1F3F9796AF3} 23 | Win32Proj 24 | jitasm 25 | 26 | 27 | 28 | StaticLibrary 29 | true 30 | v120 31 | Unicode 32 | 33 | 34 | StaticLibrary 35 | true 36 | v120 37 | Unicode 38 | 39 | 40 | StaticLibrary 41 | false 42 | v120 43 | true 44 | Unicode 45 | 46 | 47 | StaticLibrary 48 | false 49 | v120 50 | true 51 | Unicode 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | Level3 75 | Disabled 76 | _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) 77 | 78 | 79 | 80 | 81 | Windows 82 | true 83 | 84 | 85 | 86 | 87 | 88 | 89 | Level3 90 | Disabled 91 | _CRT_SECURE_NO_WARNINGS;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) 92 | 93 | 94 | 95 | 96 | Windows 97 | true 98 | 99 | 100 | 101 | 102 | Level3 103 | 104 | 105 | Full 106 | true 107 | true 108 | _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) 109 | true 110 | true 111 | 112 | 113 | 114 | 115 | Windows 116 | true 117 | true 118 | true 119 | 120 | 121 | 122 | 123 | Level3 124 | 125 | 126 | Full 127 | true 128 | true 129 | _CRT_SECURE_NO_WARNINGS;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) 130 | true 131 | true 132 | 133 | 134 | 135 | 136 | Windows 137 | true 138 | true 139 | true 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | -------------------------------------------------------------------------------- /jitasm.vcxproj.filters: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | {4FC737F1-C7A5-4376-A066-2A32D752A2FF} 6 | cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx 7 | 8 | 9 | {93995380-89BD-4b04-88EB-625FBE52EBFB} 10 | h;hh;hpp;hxx;hm;inl;inc;xsd 11 | 12 | 13 | {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} 14 | rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms 15 | 16 | 17 | 18 | 19 | Header Files 20 | 21 | 22 | Header Files 23 | 24 | 25 | Header Files 26 | 27 | 28 | Header Files 29 | 30 | 31 | Header Files 32 | 33 | 34 | Header Files 35 | 36 | 37 | Header Files 38 | 39 | 40 | Header Files 41 | 42 | 43 | Header Files 44 | 45 | 46 | Header Files 47 | 48 | 49 | Header Files 50 | 51 | 52 | Header Files 53 | 54 | 55 | Header Files 56 | 57 | 58 | Header Files 59 | 60 | 61 | Header Files 62 | 63 | 64 | 65 | 66 | Source Files 67 | 68 | 69 | -------------------------------------------------------------------------------- /jitasm.x86_32.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_x86_32_h__ 3 | #define jitasm_x86_32_h__ 4 | #include "jitasm.x86.h" 5 | namespace jitasm 6 | { 7 | namespace x86_32 8 | { 9 | using namespace x86; 10 | 11 | namespace detail 12 | { 13 | using namespace jitasm::detail; 14 | } 15 | 16 | enum 17 | { 18 | NUM_OF_PHYSICAL_REG = 16, 19 | SIZE_OF_GP_REG = 8 20 | }; 21 | 22 | typedef Reg32 Reg; 23 | typedef Addr32 Addr; 24 | typedef Addr32BI AddrBI; 25 | typedef Addr32SI AddrSI; 26 | typedef Addr32SIB AddrSIB; 27 | 28 | template 29 | struct AddressingPtr 30 | { 31 | // 32bit-Addressing 32 | Mem$ operator[](const Addr32& obj) { return Mem$(O_SIZE_32, O_SIZE_32, obj.reg_, RegID::Invalid(), 0, obj.disp_); } 33 | Mem$ operator[](const Addr32BI& obj) { return Mem$(O_SIZE_32, O_SIZE_32, obj.base_, obj.index_, 0, obj.disp_); } 34 | Mem$ operator[](const Addr32SI& obj) { return Mem$(O_SIZE_32, O_SIZE_32, RegID::Invalid(), obj.index_, obj.scale_, obj.disp_); } 35 | Mem$ operator[](const Addr32SIB& obj) { return Mem$(O_SIZE_32, O_SIZE_32, obj.base_, obj.index_, obj.scale_, obj.disp_); } 36 | VecMem$ operator[](const Addr32XmmSIB& obj) { return VecMem$(O_SIZE_32, obj.base_, obj.index_, obj.scale_, obj.disp_); } 37 | VecMem$ operator[](const Addr32YmmSIB& obj) { return VecMem$(O_SIZE_32, obj.base_, obj.index_, obj.scale_, obj.disp_); } 38 | 39 | Mem$ operator[](sint32 disp) { return Mem$(O_SIZE_32, O_SIZE_32, RegID::Invalid(), RegID::Invalid(), 0, disp); } 40 | Mem$ operator[](uint32 disp) { return Mem$(O_SIZE_32, O_SIZE_32, RegID::Invalid(), RegID::Invalid(), 0, (sint32)disp); } 41 | }; 42 | } 43 | } 44 | #endif // jitasm_x64_h__ -------------------------------------------------------------------------------- /jitasm.x86_64.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #ifndef jitasm_x86_64_h__ 3 | #define jitasm_x86_x64_h__ 4 | #include "jitasm.x86.h" 5 | namespace jitasm 6 | { 7 | namespace x86_64 8 | { 9 | using namespace x86; 10 | 11 | namespace detail 12 | { 13 | using namespace jitasm::x86::detail; 14 | } 15 | 16 | enum 17 | { 18 | NUM_OF_PHYSICAL_REG = 16, 19 | SIZE_OF_GP_REG = 8 20 | }; 21 | 22 | typedef Reg64 Reg; 23 | typedef Addr64 Addr; 24 | typedef Addr64BI AddrBI; 25 | typedef Addr64SI AddrSI; 26 | typedef Addr64SIB AddrSIB; 27 | 28 | 29 | template 30 | struct AddressingPtr 31 | { 32 | // 32bit-Addressing 33 | Mem$ operator[](const Addr32& obj) { return Mem$(O_SIZE_32, O_SIZE_32, obj.reg_, RegID::Invalid(), 0, obj.disp_); } 34 | Mem$ operator[](const Addr32BI& obj) { return Mem$(O_SIZE_32, O_SIZE_32, obj.base_, obj.index_, 0, obj.disp_); } 35 | Mem$ operator[](const Addr32SI& obj) { return Mem$(O_SIZE_32, O_SIZE_32, RegID::Invalid(), obj.index_, obj.scale_, obj.disp_); } 36 | Mem$ operator[](const Addr32SIB& obj) { return Mem$(O_SIZE_32, O_SIZE_32, obj.base_, obj.index_, obj.scale_, obj.disp_); } 37 | VecMem$ operator[](const Addr32XmmSIB& obj) { return VecMem$(O_SIZE_32, obj.base_, obj.index_, obj.scale_, obj.disp_); } 38 | VecMem$ operator[](const Addr32YmmSIB& obj) { return VecMem$(O_SIZE_32, obj.base_, obj.index_, obj.scale_, obj.disp_); } 39 | 40 | // 64bit-Addressing 41 | Mem$ operator[](const Addr64& obj) { return Mem$(O_SIZE_64, O_SIZE_64, obj.reg_, RegID::Invalid(), 0, obj.disp_); } 42 | Mem$ operator[](const Addr64BI& obj) { return Mem$(O_SIZE_64, O_SIZE_64, obj.base_, obj.index_, 0, obj.disp_); } 43 | Mem$ operator[](const Addr64SI& obj) { return Mem$(O_SIZE_64, O_SIZE_64, RegID::Invalid(), obj.index_, obj.scale_, obj.disp_); } 44 | Mem$ operator[](const Addr64SIB& obj) { return Mem$(O_SIZE_64, O_SIZE_64, obj.base_, obj.index_, obj.scale_, obj.disp_); } 45 | //MemOffset64 operator[](sint64 offset) { return MemOffset64(offset); } 46 | //MemOffset64 operator[](uint64 offset) { return MemOffset64((sint64)offset); } 47 | VecMem$ operator[](const Addr64XmmSIB& obj) { return VecMem$(O_SIZE_64, obj.base_, obj.index_, obj.scale_, obj.disp_); } 48 | VecMem$ operator[](const Addr64YmmSIB& obj) { return VecMem$(O_SIZE_64, obj.base_, obj.index_, obj.scale_, obj.disp_); } 49 | 50 | Mem$ operator[](sint32 disp) { return Mem$(O_SIZE_64, O_SIZE_64, RegID::Invalid(), RegID::Invalid(), 0, (sint32)disp); } 51 | Mem$ operator[](uint32 disp) { return Mem$(O_SIZE_64, O_SIZE_64, RegID::Invalid(), RegID::Invalid(), 0, (sint32)disp); } 52 | Mem$ operator[](sint64 disp) { return Mem$(O_SIZE_64, O_SIZE_64, RegID::Invalid(), RegID::Invalid(), 0, (sint64)disp); } 53 | Mem$ operator[](uint64 disp) { return Mem$(O_SIZE_64, O_SIZE_64, RegID::Invalid(), RegID::Invalid(), 0, (sint64)disp); } 54 | }; 55 | } 56 | } 57 | #endif // jitasm_x86_64_h__ -------------------------------------------------------------------------------- /test/test.cpp: -------------------------------------------------------------------------------- 1 | #if 1 2 | #include 3 | 4 | #include "jitasm.Frontend.x86_32.h" 5 | #include "jitasm.Frontend.x86_64.h" 6 | 7 | #include "capstone/include/capstone.h" 8 | #if defined(NDEBUG) 9 | # if defined(_WIN64) 10 | # pragma comment(lib, "x64/release/jitasm.lib") 11 | # pragma comment(lib, "capstone/lib/capstone.release.x86_64.lib") 12 | # else 13 | # pragma comment(lib, "release/jitasm.lib") 14 | # pragma comment(lib, "capstone/lib/capstone.release.x86_32.lib") 15 | # endif 16 | #else 17 | # if defined(_WIN64) 18 | # pragma comment(lib, "x64/debug/jitasm.lib") 19 | # pragma comment(lib, "capstone/lib/capstone.debug.x86_64.lib") 20 | # else 21 | # pragma comment(lib, "debug/jitasm.lib") 22 | # pragma comment(lib, "capstone/lib/capstone.debug.x86_32.lib") 23 | # endif 24 | #endif 25 | 26 | static void capstone_Disassemble(FILE * out, cs_insn & insn) 27 | { 28 | char address[32]; 29 | 30 | sprintf(address, "0x%08llX(%2d):", insn.address, insn.size); 31 | 32 | char bytes[64], *p = bytes; 33 | 34 | for (size_t i = 0; i < insn.size; ++i) 35 | { 36 | p += sprintf(p, "%02X", size_t(insn.bytes[insn.size - i - 1])); 37 | } 38 | 39 | fprintf(out, "%s %32s %-16s %s\r\n", address, bytes, insn.mnemonic, insn.op_str); 40 | } 41 | 42 | static void capstone_Dump(FILE * out, cs_mode mode, void * code, size_t size) 43 | { 44 | cs_insn * insn; 45 | csh handle; 46 | cs_err err = ::cs_open(CS_ARCH_X86, mode, &handle); 47 | 48 | if (CS_ERR_OK == err) 49 | { 50 | size_t count = ::cs_disasm(handle, (uint8_t const *)code, size, (uint64_t)0x10000000, 0, &insn); 51 | if (count > 0) 52 | { 53 | for (size_t j = 0; j < count; ++j) 54 | { 55 | capstone_Disassemble(out, insn[j]); 56 | size = size - insn[j].size; 57 | code = (void *)((uint8_t *)code + insn[j].size); 58 | } 59 | ::cs_free(insn, count); 60 | } 61 | 62 | if (size) 63 | { 64 | char address[32]; 65 | 66 | size = min(size, 16); 67 | 68 | sprintf(address, "(%2d):", size); 69 | 70 | char bytes[64], *p = bytes; 71 | 72 | for (size_t i = 0; i < size; ++i) 73 | { 74 | p += sprintf(p, "%02X", size_t(((uint8_t const *)code)[i])); 75 | } 76 | 77 | fprintf(out, "%s %16s unknown instruction(s)\r\n", address, bytes); 78 | } 79 | 80 | ::cs_close(&handle); 81 | } 82 | } 83 | 84 | class CriticalSection : CRITICAL_SECTION 85 | { 86 | public: 87 | CriticalSection() 88 | { 89 | ::InitializeCriticalSection(this); 90 | } 91 | 92 | ~CriticalSection() 93 | { 94 | ::DeleteCriticalSection(this); 95 | } 96 | 97 | void Enter() 98 | { 99 | ::EnterCriticalSection(this); 100 | } 101 | 102 | void Leave() 103 | { 104 | ::LeaveCriticalSection(this); 105 | } 106 | }; 107 | 108 | /** @brief The RTL create heap. */ 109 | static auto RtlCreateHeap = 110 | (PVOID (NTAPI *)( 111 | _In_ ULONG Flags, 112 | _In_opt_ PVOID HeapBase, 113 | _In_opt_ SIZE_T ReserveSize, 114 | _In_opt_ SIZE_T CommitSize, 115 | _In_opt_ PVOID Lock, 116 | _In_opt_ PVOID Parameters 117 | ))::GetProcAddress(::GetModuleHandleA("ntdll.dll"), "RtlCreateHeap"); 118 | 119 | static auto RtlAllocateHeap = 120 | (PVOID (NTAPI *)( 121 | _In_ PVOID HeapHandle, 122 | _In_opt_ ULONG Flags, 123 | _In_ SIZE_T Size 124 | ))::GetProcAddress(::GetModuleHandleA("ntdll.dll"), "RtlAllocateHeap"); 125 | 126 | static auto RtlFreeHeap = 127 | (BOOLEAN (NTAPI *)( 128 | _In_ PVOID HeapHandle, 129 | _In_opt_ ULONG Flags, 130 | _In_ PVOID HeapBase 131 | ))::GetProcAddress(::GetModuleHandleA("ntdll.dll"), "RtlFreeHeap"); 132 | 133 | static auto RtlDestroyHeap = 134 | (PVOID (NTAPI *)( 135 | _In_ PVOID HeapHandle 136 | ))::GetProcAddress(::GetModuleHandleA("ntdll.dll"), "RtlDestroyHeap"); 137 | 138 | struct CodeBuffer : jitasm::CodeBuffer$CRTP< CodeBuffer > 139 | { 140 | bool AllocateBuffer(size_t codesize) 141 | { 142 | void * p = ::RtlAllocateHeap(heap_, 0, codesize); 143 | if (p) 144 | { 145 | buffaddr_ = p; 146 | buffsize_ = codesize; 147 | } 148 | return !!p; 149 | } 150 | 151 | bool FreeBuffer() 152 | { 153 | return TRUE == ::RtlFreeHeap(heap_, 0, buffaddr_); 154 | } 155 | 156 | CodeBuffer() 157 | { 158 | if (0 == _InterlockedExchangeAdd(&refs_, 1)) 159 | { 160 | cs_.Enter(); 161 | if (!filemapping_) 162 | { 163 | size_t size = 64 * 1024 * 1024; // 64 Mbyte 164 | bool ok = 0 != (filemapping_ = ::CreateFileMappingA(INVALID_HANDLE_VALUE, NULL, SEC_COMMIT | PAGE_EXECUTE_READWRITE, 0, (DWORD)size, NULL)); 165 | if (ok) 166 | { 167 | ok = 0 != (base_ = ::MapViewOfFileEx(filemapping_, FILE_MAP_READ | FILE_MAP_WRITE | FILE_MAP_EXECUTE, 0, 0, size, (LPVOID)0)); 168 | if (ok) 169 | { 170 | ok = 0 != (heap_ = ::RtlCreateHeap(HEAP_CREATE_ENABLE_EXECUTE | HEAP_CREATE_ALIGN_16 | HEAP_GENERATE_EXCEPTIONS, base_, size, 0, NULL, NULL)); 171 | 172 | if (!ok) 173 | { 174 | ::UnmapViewOfFile(base_); 175 | base_ = 0; 176 | } 177 | } 178 | if (!ok) 179 | { 180 | ::CloseHandle(filemapping_); 181 | filemapping_ = 0; 182 | } 183 | } 184 | } 185 | cs_.Leave(); 186 | } 187 | } 188 | 189 | ~CodeBuffer() 190 | { 191 | if (1 == _InterlockedExchangeAdd(&refs_, -1)) 192 | { 193 | cs_.Enter(); 194 | if (filemapping_) 195 | { 196 | if (heap_) 197 | { 198 | ::RtlDestroyHeap(heap_); 199 | heap_ = 0; 200 | } 201 | 202 | if (base_) 203 | { 204 | ::UnmapViewOfFile(base_); 205 | base_ = 0; 206 | } 207 | 208 | ::CloseHandle(filemapping_); 209 | filemapping_ = 0; 210 | } 211 | cs_.Leave(); 212 | } 213 | } 214 | 215 | static HANDLE heap_; 216 | static HANDLE filemapping_; 217 | static void * base_; 218 | static CriticalSection cs_; 219 | static long refs_; 220 | static CodeBuffer singleton_; 221 | }; 222 | 223 | HANDLE CodeBuffer::heap_ = 0; 224 | HANDLE CodeBuffer::filemapping_ = 0; 225 | void * CodeBuffer::base_ = 0; 226 | CriticalSection CodeBuffer::cs_; 227 | long CodeBuffer::refs_ = 0; 228 | CodeBuffer CodeBuffer::singleton_; 229 | 230 | struct Frontend_x86_32 : jitasm::x86_32::Frontend$CRTP< Frontend_x86_32 >, CodeBuffer 231 | { 232 | void InternalMain() 233 | { 234 | using namespace jitasm::x86_32; 235 | 236 | Imm8 i8(0x55); 237 | Imm16 i16(0x5555); 238 | Imm32 i32(0x55555555); 239 | 240 | AppendInstr(I_ADD, dl, i8); 241 | AppendInstr(I_OR, dl, i8); 242 | AppendInstr(I_ADC, dl, i8); 243 | AppendInstr(I_SBB, dl, i8); 244 | AppendInstr(I_AND, dl, i8); 245 | AppendInstr(I_SUB, dl, i8); 246 | AppendInstr(I_XOR, dl, i8); 247 | AppendInstr(I_CMP, dl, i8); 248 | 249 | AppendInstr(I_ADD, byte_ptr[0x55555555], i8); 250 | AppendInstr(I_OR, byte_ptr[0x55555555], i8); 251 | AppendInstr(I_ADC, byte_ptr[0x55555555], i8); 252 | AppendInstr(I_SBB, byte_ptr[0x55555555], i8); 253 | AppendInstr(I_AND, byte_ptr[0x55555555], i8); 254 | AppendInstr(I_SUB, byte_ptr[0x55555555], i8); 255 | AppendInstr(I_XOR, byte_ptr[0x55555555], i8); 256 | AppendInstr(I_CMP, byte_ptr[0x55555555], i8); 257 | } 258 | }; 259 | 260 | struct Frontend_x86_64 : jitasm::x86_64::Frontend$CRTP< Frontend_x86_64 >, CodeBuffer 261 | { 262 | void InternalMain() 263 | { 264 | using namespace jitasm::x86_64; 265 | 266 | Imm8 i8(0x55); 267 | Imm16 i16(0x5555); 268 | Imm32 i32(0x55555555); 269 | } 270 | }; 271 | 272 | void test_x86_32() 273 | { 274 | Frontend_x86_32 x86_32; 275 | 276 | fprintf(stdout, "test_x86 - 32-bit mode:\r\n=========\r\n"); 277 | 278 | #if 1 279 | for (jitasm::x86::InstrID id = jitasm::x86::I_AAA; id <= jitasm::x86::I_XTEST; id = jitasm::x86::InstrID(size_t(id) + 1)) 280 | { 281 | x86_32.Test(id); 282 | 283 | void * code = x86_32.GetCodePointer(); 284 | size_t size = x86_32.GetCodeSize(); 285 | 286 | if (size) 287 | { 288 | capstone_Dump(stdout, CS_MODE_32, code, size); 289 | fprintf(stdout, "\r\n"); 290 | } 291 | } 292 | #else 293 | void * code = x86_32.GetCodePointer(); 294 | size_t size = x86_32.GetCodeSize(); 295 | 296 | capstone_Dump(stdout, CS_MODE_32, code, size); 297 | #endif 298 | 299 | fprintf(stdout, "\r\n"); 300 | } 301 | 302 | void test_x86_64() 303 | { 304 | Frontend_x86_64 x86_64; 305 | 306 | fprintf(stdout, "test_x86 - 64-bit mode:\r\n=========\r\n"); 307 | #if 1 308 | for (jitasm::x86::InstrID id = jitasm::x86::I_AAA; id <= jitasm::x86::I_XTEST; id = jitasm::x86::InstrID(size_t(id) + 1)) 309 | { 310 | x86_64.Test(id); 311 | 312 | void * code = x86_64.GetCodePointer(); 313 | size_t size = x86_64.GetCodeSize(); 314 | 315 | if (size) 316 | { 317 | capstone_Dump(stdout, CS_MODE_64, code, size); 318 | fprintf(stdout, "\r\n"); 319 | } 320 | } 321 | #else 322 | void * code = x86_64.GetCodePointer(); 323 | size_t size = x86_64.GetCodeSize(); 324 | capstone_Dump(stdout, CS_MODE_64, code, size); 325 | #endif 326 | fprintf(stdout, "\r\n"); 327 | } 328 | 329 | int main(int argc, char * argv[]) 330 | { 331 | test_x86_32(); 332 | 333 | //test_x86_64(); 334 | 335 | system("pause"); 336 | 337 | return 0; 338 | } 339 | #else 340 | #include 341 | #include 342 | 343 | using namespace std; 344 | 345 | typedef size_t Instr; // dummy one for simplified code 346 | 347 | enum 348 | { 349 | I_INVALID = 0, 350 | 351 | I_LAST_INSTRUCTION = 1223 352 | }; 353 | 354 | template< size_t id > 355 | static void Test_T(std::vector< Instr > &, bool) 356 | { 357 | cout << "testing instruction #" << id << endl; 358 | } 359 | 360 | struct Tester; 361 | 362 | template< size_t start_id, size_t end_id > 363 | struct TestArrayInitializer_T 364 | { 365 | static void Set(Tester & tester) 366 | { 367 | tester.array[start_id] = Test_T < start_id > ; 368 | TestArrayInitializer_T< start_id + 1, end_id >::Set(tester); 369 | } 370 | }; 371 | 372 | template< size_t start_id > 373 | struct TestArrayInitializer_T < start_id, start_id > 374 | { 375 | static void Set(Tester & tester) 376 | { 377 | tester.array[start_id] = Test_T < start_id > ; 378 | } 379 | }; 380 | 381 | template< typename Derived, 382 | size_t start_id, 383 | size_t end_id, 384 | size_t bits, 385 | size_t N = (1 << bits), 386 | size_t i = (end_id - start_id) & (N - 1) > 387 | struct Tester_T : Tester_T < Derived, start_id, end_id - N + i, bits > 388 | { 389 | Tester_T() 390 | { 391 | TestArrayInitializer_T< end_id - N + i, end_id - 1 >::Set(*static_cast(this)); 392 | } 393 | }; 394 | 395 | template< typename Derived, size_t bits, size_t N, size_t i > 396 | struct Tester_T < Derived, 0, 0, bits, N, i > 397 | { 398 | }; 399 | 400 | struct Tester : Tester_T < Tester, I_INVALID, I_LAST_INSTRUCTION, 8 > 401 | { 402 | void(*array[size_t(I_LAST_INSTRUCTION)])(std::vector< Instr > & list, bool is64); 403 | 404 | void operator()(size_t id, std::vector< Instr > & list, bool is64) const 405 | { 406 | if (id < I_LAST_INSTRUCTION) 407 | { 408 | (array[size_t(id)])(list, is64); 409 | } 410 | else 411 | { 412 | // to do nothing 413 | } 414 | } 415 | }; 416 | 417 | static Tester const tester; 418 | 419 | int main() 420 | { 421 | std::vector< Instr > list; 422 | 423 | tester(0, list, true); // display testing instruction #0 424 | tester(1, list, true); // display testing instruction #1 425 | tester(2, list, true); // display testing instruction #2 426 | tester(3, list, true); // display testing instruction #3 427 | tester(4, list, true); // display testing instruction #4 428 | tester(8, list, true); // display testing instruction #8 429 | tester(15, list, true); // display testing instruction #15 430 | tester(16, list, true); // display testing instruction #16 431 | tester(1024, list, true); // display testing instruction #1024 432 | tester(1222, list, true); // display testing instruction #1222 433 | tester(1223, list, true); // invalid instruction number - do nothing 434 | tester(2048, list, true); // invalid instruction number - do nothing 435 | } 436 | #endif -------------------------------------------------------------------------------- /test/test.vcxproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Debug 10 | x64 11 | 12 | 13 | Release 14 | Win32 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {4EC7B156-8FE1-42D7-9598-236DC01BE727} 23 | Win32Proj 24 | test 25 | 26 | 27 | 28 | Application 29 | true 30 | v120 31 | Unicode 32 | 33 | 34 | Application 35 | true 36 | v120 37 | Unicode 38 | 39 | 40 | Application 41 | false 42 | v120 43 | true 44 | Unicode 45 | 46 | 47 | Application 48 | false 49 | v120 50 | true 51 | Unicode 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | true 71 | 72 | 73 | true 74 | 75 | 76 | false 77 | 78 | 79 | false 80 | 81 | 82 | 83 | 84 | 85 | Level3 86 | Disabled 87 | WIN32;_DEBUG;_CONSOLE;_LIB;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) 88 | ..;%(AdditionalIncludeDirectories) 89 | 90 | 91 | Console 92 | true 93 | ..;%(AdditionalLibraryDirectories) 94 | 95 | 96 | 97 | 98 | 99 | 100 | Level3 101 | Disabled 102 | WIN32;_DEBUG;_CONSOLE;_LIB;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) 103 | ..;%(AdditionalIncludeDirectories) 104 | 105 | 106 | Console 107 | true 108 | ..;%(AdditionalLibraryDirectories) 109 | 110 | 111 | 112 | 113 | Level3 114 | 115 | 116 | Full 117 | true 118 | true 119 | WIN32;NDEBUG;_CONSOLE;_LIB;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) 120 | ..;%(AdditionalIncludeDirectories) 121 | true 122 | true 123 | 124 | 125 | Console 126 | true 127 | true 128 | true 129 | ..;%(AdditionalLibraryDirectories) 130 | 131 | 132 | 133 | 134 | Level3 135 | 136 | 137 | Full 138 | true 139 | true 140 | WIN32;NDEBUG;_CONSOLE;_LIB;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) 141 | ..;%(AdditionalIncludeDirectories) 142 | true 143 | true 144 | 145 | 146 | Console 147 | true 148 | true 149 | true 150 | ..;%(AdditionalLibraryDirectories) 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | -------------------------------------------------------------------------------- /test/test.vcxproj.filters: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | {4FC737F1-C7A5-4376-A066-2A32D752A2FF} 6 | cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx 7 | 8 | 9 | {93995380-89BD-4b04-88EB-625FBE52EBFB} 10 | h;hh;hpp;hxx;hm;inl;inc;xsd 11 | 12 | 13 | {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} 14 | rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms 15 | 16 | 17 | 18 | 19 | Header Files 20 | 21 | 22 | Header Files 23 | 24 | 25 | 26 | 27 | Source Files 28 | 29 | 30 | --------------------------------------------------------------------------------