├── Counter ├── test_output.PNG ├── up_down_counter.sv ├── testbench_7.sv └── README.md ├── Decoder-Encoder-3to8 ├── test_output.png ├── DecoderEncoder.sv └── README.md ├── Ripple-Carry-Adder ├── test_output.png ├── rc_adder_slice.sv ├── rc_adder4.sv ├── testbench_3.sv └── README.md ├── Verilog-Logic-Modules ├── test_output.png ├── module_s.sv ├── module_d.sv ├── module_b.sv ├── testbench_2.sv └── README.md ├── .idea ├── vcs.xml ├── .gitignore ├── misc.xml ├── modules.xml ├── aws.xml ├── Digital-Design-Labs.iml └── workspace.xml ├── Guessing-Game-Assembly ├── output_images │ ├── When a correct guess is made.JPG │ ├── When an incorrect guess is made.JPG │ ├── At State S1 (no input is selected).JPG │ ├── At State S2 (no input is selected).JPG │ ├── At State S3 (no input is selected).JPG │ ├── At State S4 (no input is selected).JPG │ ├── When two guesses are made at the same time.JPG │ └── Back to State S1 when at S4 and no guess is made.JPG ├── README.md ├── P16F84A.inc └── GuessingGame.ASM ├── Arithmetic-Logic-Unit ├── alu_slice.sv ├── gen_alu.sv ├── testbench_4.sv └── README.md ├── Carry-Lookahead-Adder ├── cla_adder.sv ├── testbench_5.sv └── README.md ├── LICENSE ├── Finite-State-Machine ├── testbench_8.sv ├── tbird_fsm.sv └── README.md ├── PIC16F84A-Microcontrollers ├── README.md ├── partc.ASM ├── partb.ASM ├── P16F84A.inc ├── partd.ASM └── parta.ASM └── README.md /Counter/test_output.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Counter/test_output.PNG -------------------------------------------------------------------------------- /Decoder-Encoder-3to8/test_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Decoder-Encoder-3to8/test_output.png -------------------------------------------------------------------------------- /Ripple-Carry-Adder/test_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Ripple-Carry-Adder/test_output.png -------------------------------------------------------------------------------- /Verilog-Logic-Modules/test_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Verilog-Logic-Modules/test_output.png -------------------------------------------------------------------------------- /.idea/vcs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /.idea/.gitignore: -------------------------------------------------------------------------------- 1 | # Default ignored files 2 | /shelf/ 3 | # Editor-based HTTP Client requests 4 | /httpRequests/ 5 | # Datasource local storage ignored files 6 | /dataSources/ 7 | /dataSources.local.xml 8 | -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/When a correct guess is made.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/When a correct guess is made.JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/When an incorrect guess is made.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/When an incorrect guess is made.JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/At State S1 (no input is selected).JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/At State S1 (no input is selected).JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/At State S2 (no input is selected).JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/At State S2 (no input is selected).JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/At State S3 (no input is selected).JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/At State S3 (no input is selected).JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/At State S4 (no input is selected).JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/At State S4 (no input is selected).JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/When two guesses are made at the same time.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/When two guesses are made at the same time.JPG -------------------------------------------------------------------------------- /Guessing-Game-Assembly/output_images/Back to State S1 when at S4 and no guess is made.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hoangsonww/Digital-Design-Labs/HEAD/Guessing-Game-Assembly/output_images/Back to State S1 when at S4 and no guess is made.JPG -------------------------------------------------------------------------------- /Verilog-Logic-Modules/module_s.sv: -------------------------------------------------------------------------------- 1 | module module_s( 2 | input logic a, 3 | input logic b, 4 | output logic y1, 5 | output logic y2, 6 | output logic y3 7 | ); 8 | 9 | and U1 (y1,a,b); 10 | 11 | or U2 (y2,a,b); 12 | 13 | xor U3 (y3,a,b); 14 | 15 | endmodule -------------------------------------------------------------------------------- /Verilog-Logic-Modules/module_d.sv: -------------------------------------------------------------------------------- 1 | module module_d ( 2 | input logic a, 3 | input logic b, 4 | output logic y1, 5 | output logic y2, 6 | output logic y3 7 | ); 8 | 9 | assign y1 = a & b; 10 | 11 | assign y2 = a | b; 12 | 13 | assign y3 = a ^ b; 14 | 15 | endmodule -------------------------------------------------------------------------------- /Verilog-Logic-Modules/module_b.sv: -------------------------------------------------------------------------------- 1 | module module_b( 2 | input logic a, 3 | input logic b, 4 | output logic y1, 5 | output logic y2, 6 | output logic y3 7 | ); 8 | 9 | always_comb 10 | begin 11 | 12 | y1 = a & b; 13 | y2 = a | b; 14 | y3 = a ^ b; 15 | 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /.idea/misc.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Ripple-Carry-Adder/rc_adder_slice.sv: -------------------------------------------------------------------------------- 1 | module rc_adder_slice ( 2 | input logic a, b, c_in, 3 | output logic s, c_out 4 | ); 5 | 6 | logic p, g; 7 | 8 | assign p = a ^ b; 9 | assign g = a & b; 10 | 11 | assign s = p ^ c_in; 12 | assign c_out = g | (p & c_in); 13 | 14 | endmodule -------------------------------------------------------------------------------- /.idea/modules.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /.idea/aws.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 10 | 11 | -------------------------------------------------------------------------------- /Ripple-Carry-Adder/rc_adder4.sv: -------------------------------------------------------------------------------- 1 | module rc_adder4 ( 2 | input logic [2:0] a, b, 3 | output logic [2:0] s, 4 | output logic co 5 | ); 6 | 7 | logic [3:0] c; 8 | 9 | rc_adder_slice adders[2:0]( 10 | .a(a), 11 | .b(b), 12 | .c_in(c[2:0]), 13 | .s(s), 14 | .c_out(c[3:1]) 15 | ); 16 | 17 | assign c[0] = 0; 18 | assign co = c[3]; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /.idea/Digital-Design-Labs.iml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /Arithmetic-Logic-Unit/alu_slice.sv: -------------------------------------------------------------------------------- 1 | module alu_slice ( 2 | input logic a, b, c_in, 3 | input logic [1:0] f, 4 | output logic s, c_out 5 | ); 6 | 7 | logic b_inv, c; 8 | 9 | assign b_inv = b ^ f[0]; 10 | assign c = f[1] & c_in ; 11 | 12 | rc_adder_slice U1 ( 13 | .a(a), 14 | .b(b_inv), 15 | .c_in(c), 16 | .s(s), 17 | .c_out(c_out) 18 | ); 19 | 20 | endmodule -------------------------------------------------------------------------------- /Arithmetic-Logic-Unit/gen_alu.sv: -------------------------------------------------------------------------------- 1 | module gen_alu #( 2 | parameter N = 8 3 | ) ( 4 | input logic [N-1:0] a, b, 5 | input logic [1:0] f, 6 | output logic [N-1:0] s, 7 | output logic co 8 | ); 9 | 10 | logic [N:0] c; 11 | 12 | alu_slice slice[N-1:0] ( 13 | .a(a), 14 | .b(b), 15 | .c_in(c[N-1:0]), 16 | .f(f), 17 | .s(s), 18 | .c_out(c[N:1]) 19 | ); 20 | 21 | assign c[0] = 0; 22 | assign co = c[N]; 23 | 24 | endmodule -------------------------------------------------------------------------------- /Counter/up_down_counter.sv: -------------------------------------------------------------------------------- 1 | module up_down_counter #( 2 | parameter N = 4 3 | ) ( 4 | input logic clk, 5 | input logic en_b, 6 | input logic load_b, 7 | input logic up, 8 | input logic [N-1:0] load_in, 9 | output logic [N-1:0] q, 10 | output logic rco_b 11 | ); 12 | 13 | always_ff @(posedge clk) begin 14 | if (~en_b) begin 15 | if (load_b) begin 16 | q <= up ? q + 1 : q - 1; 17 | end 18 | else begin 19 | q <= load_in; 20 | end 21 | end 22 | end 23 | 24 | assign rco_b = ~(up & (&q)) | (up | (&q)); 25 | 26 | endmodule -------------------------------------------------------------------------------- /Carry-Lookahead-Adder/cla_adder.sv: -------------------------------------------------------------------------------- 1 | module cla_adder #( 2 | parameter N 3 | ) ( 4 | input logic [N-1:0] a, 5 | input logic [N-1:0] b, 6 | input logic c_in, 7 | output logic [N-1:0] s, 8 | output logic c_out 9 | ); 10 | 11 | logic [N-1:0] p, g; 12 | logic [N:0] c; 13 | 14 | assign p = a ^ b; 15 | assign g = a & b; 16 | 17 | for (genvar i = 0; i <= N; i++) begin 18 | if (i == 0) 19 | assign c[i] = c_in; 20 | else 21 | assign c[i] = (c[i-1] & p[i-1]) | g[i-1]; 22 | end 23 | 24 | assign s = c[N-1:0] + a + b; 25 | assign c_out = c[N]; 26 | 27 | endmodule -------------------------------------------------------------------------------- /Ripple-Carry-Adder/testbench_3.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | 3 | module testbench_lab3 (); 4 | 5 | logic [2:0] a, b, s; 6 | logic co; 7 | 8 | rc_adder4 UUT ( 9 | .a(a), 10 | .b(b), 11 | .s(s), 12 | .co(co) 13 | ); 14 | 15 | initial begin 16 | a = 0; 17 | forever begin 18 | #10 a++; 19 | end 20 | end 21 | 22 | initial begin 23 | b = 0; 24 | forever begin 25 | #20 b++; 26 | end 27 | end 28 | 29 | initial begin 30 | $display("TIME | A B | S CO"); 31 | $display("-----------------"); 32 | $monitor(" %2d | %d %d | %d %b", 33 | $time, a, b, s, co); 34 | #160 35 | $finish(); 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /Carry-Lookahead-Adder/testbench_5.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | 3 | module testbench (); 4 | 5 | logic [1:0] a2, b2, s2; 6 | logic [7:0] a8, b8, s8; 7 | logic co2, co8; 8 | 9 | cla_adder #( 10 | .N(2) 11 | ) UUT2 ( 12 | .a(a2), 13 | .b(b2), 14 | .c_in(0), 15 | .s(s2), 16 | .c_out(co2) 17 | ); 18 | 19 | cla_adder #( 20 | .N(8) 21 | ) UUT8 ( 22 | .a(a8), 23 | .b(b8), 24 | .c_in(0), 25 | .s(s8), 26 | .c_out(co8) 27 | ); 28 | 29 | initial begin 30 | a2 = 0; 31 | forever 32 | #10 33 | a2 = a2 + 1; 34 | end 35 | 36 | initial begin 37 | b2 = 0; 38 | forever 39 | #40 40 | b2 = b2 + 1; 41 | end 42 | 43 | initial begin 44 | a8 = 0; 45 | forever 46 | #10 47 | a8 = a8 + 3; 48 | end 49 | 50 | initial begin 51 | b8 = 0; 52 | forever 53 | #10 54 | b8 = b8 + 5; 55 | end 56 | 57 | initial begin 58 | #320 59 | $finish(); 60 | end 61 | 62 | endmodule -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 Son Nguyen Hoang 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Arithmetic-Logic-Unit/testbench_4.sv: -------------------------------------------------------------------------------- 1 | module testbench_lab4 (); 2 | 3 | logic [3:0] a4, b4, s4; 4 | logic [7:0] a8, b8, s8; 5 | logic [1:0] f; 6 | logic co4, co8; 7 | logic clk; 8 | logic [25:0] tvs [15:0]; 9 | int i = 0; 10 | 11 | gen_alu #( 12 | .N(4) 13 | ) UUT4 ( 14 | .a(a4), 15 | .b(b4), 16 | .f(f), 17 | .s(s4), 18 | .co(co4) 19 | ); 20 | 21 | gen_alu #( 22 | .N(8) 23 | ) UUT8 ( 24 | .a(a8), 25 | .b(b8), 26 | .f(f), 27 | .s(s8), 28 | .co(co8) 29 | ); 30 | 31 | initial begin 32 | clk = 1'b0; 33 | forever #10 34 | clk = ~clk; 35 | end 36 | 37 | always @(posedge clk) begin 38 | f = tvs[i][25:24]; 39 | a4 = tvs[i][23:20]; 40 | b4 = tvs[i][19:16]; 41 | a8 = tvs[i][15:8]; 42 | b8 = tvs[i][7:0]; 43 | i++; 44 | end 45 | 46 | initial begin 47 | $readmemb("test_vectors.txt", tvs); 48 | $display("TIME | A4 B4 | S4 CO4| A8 B8 | S8 CO8| "); 49 | $monitor(" %3d | %4b %4b | %4b %b | %8b %8b | %8b %b |", $time, a4, b4, s4, co4, a8, b8, s8, co8); 50 | #320 51 | $finish(); 52 | end 53 | 54 | endmodule -------------------------------------------------------------------------------- /Verilog-Logic-Modules/testbench_2.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | 3 | module testbench_lab2 (); 4 | 5 | logic a, b; 6 | logic y1s, y2s, y3s; 7 | logic y1d, y2d, y3d; 8 | logic y1b, y2b, y3b; 9 | 10 | module_s UUT1 ( 11 | .a (a), 12 | .b (b), 13 | .y1(y1s), 14 | .y2(y2s), 15 | .y3(y3s) 16 | ); 17 | 18 | module_d UUT2 ( 19 | .a (a), 20 | .b (b), 21 | .y1(y1d), 22 | .y2(y2d), 23 | .y3(y3d) 24 | ); 25 | 26 | module_b UUT3 ( 27 | .a (a), 28 | .b (b), 29 | .y1(y1b), 30 | .y2(y2b), 31 | .y3(y3b) 32 | ); 33 | 34 | 35 | initial begin 36 | a = 0; 37 | b = 0; 38 | #10; 39 | a = 1; 40 | b = 0; 41 | #10; 42 | a = 0; 43 | b = 1; 44 | #10; 45 | a = 1; 46 | b = 1; 47 | #10; 48 | $finish(); 49 | end 50 | 51 | initial begin 52 | $display("TIME | AB | y1s y2s y3s | y1d y2d y3d | y1b y2b y3b"); 53 | $display("---------------------------------------------------"); 54 | $monitor(" %2d | %b %b | %b %b %b | %b %b %b | %b %b %b", 55 | $time, a, b, y1s, y2s, y3s, y1d, y2d, y3d, y1b, y2b, y3b); 56 | 57 | $dumpfile("lab2.vcd"); 58 | $dumpvars(1, a, b, y1s, y2s, y3s, y1d, y2d, y3d, y1b, y2b, y3b); 59 | $dumpflush; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /Finite-State-Machine/testbench_8.sv: -------------------------------------------------------------------------------- 1 | module testbench_hw8 (); 2 | 3 | logic clk, rst_b, left, right, haz; 4 | logic [2:0] l_lights, r_lights; 5 | 6 | tbird_fsm UUT ( 7 | .clk(clk), 8 | .rst_b(rst_b), 9 | .left(left), 10 | .right(right), 11 | .haz(haz), 12 | .l_lights(l_lights), 13 | .r_lights(r_lights) 14 | ); 15 | 16 | initial begin 17 | clk = 1'b0; 18 | rst_b = 1'b1; 19 | left = 1'b0; 20 | right = 1'b0; 21 | haz = 1'b0; 22 | 23 | forever #5 clk = ~clk; 24 | end 25 | 26 | initial begin 27 | #10; 28 | rst_b = 1'b0; 29 | #20; 30 | rst_b = 1'b1; 31 | #20; 32 | right = 1'b1; 33 | #40; 34 | right = 1'b0; 35 | left = 1'b1; 36 | #40; 37 | left = 1'b0; 38 | right = 1'b1; 39 | #10; 40 | right = 1'b0; 41 | haz = 1'b1; 42 | #10; 43 | haz = 1'b0; 44 | #10; 45 | right = 1'b1; 46 | #20; 47 | right = 1'b0; 48 | haz = 1'b1; 49 | #10; 50 | haz = 1'b0; 51 | #10; 52 | left = 1'b1; 53 | #10; 54 | left = 1'b0; 55 | haz = 1'b1; 56 | #10; 57 | haz = 1'b0; 58 | #10; 59 | left = 1'b1; 60 | #20; 61 | left = 1'b0; 62 | haz = 1'b1; 63 | #10; 64 | haz = 1'b0; 65 | #10; 66 | $finish(); 67 | end 68 | endmodule -------------------------------------------------------------------------------- /Decoder-Encoder-3to8/DecoderEncoder.sv: -------------------------------------------------------------------------------- 1 | module lab6 (); 2 | 3 | function logic [7:0] decoder3to8 (logic en_b, logic [2:0] in); 4 | casex({en_b, in}) 5 | 4'b1_xxx: return 8'b1111_1111; 6 | 4'b0_000: return 8'b1111_1110; 7 | 4'b0_001: return 8'b1111_1101; 8 | 4'b0_010: return 8'b1111_1011; 9 | 4'b0_011: return 8'b1111_0111; 10 | 4'b0_100: return 8'b1110_1111; 11 | 4'b0_101: return 8'b1101_1111; 12 | 4'b0_110: return 8'b1011_1111; 13 | 4'b0_111: return 8'b0111_1111; 14 | endcase 15 | endfunction 16 | 17 | function logic [2:0] encoder8to3 (logic en_b, logic [7:0] in_b); 18 | casex({en_b, in_b}) 19 | 9'b1_xxxxxxxx: return 3'b111; 20 | 9'b0_1xxxxxxx: return 3'b000; 21 | 9'b0_x1xxxxxx: return 3'b001; 22 | 9'b0_xx1xxxxx: return 3'b010; 23 | 9'b0_xxx1xxxx: return 3'b011; 24 | 9'b0_xxxx1xxx: return 3'b100; 25 | 9'b0_xxxxx1xx: return 3'b101; 26 | 9'b0_xxxxxx1x: return 3'b110; 27 | 9'b0_xxxxxxx1: return 3'b111; 28 | endcase 29 | endfunction 30 | 31 | logic [2:0] in, out; 32 | logic clk; 33 | logic [7:0] output_from_decoder; 34 | 35 | assign output_from_decoder = decoder3to8(clk, in); 36 | assign out = encoder8to3(clk, output_from_decoder); 37 | 38 | initial begin 39 | clk = 1'b1; 40 | in = 3'b111; 41 | forever #5 clk = ~clk; 42 | end 43 | 44 | always @ (posedge clk) 45 | in <= in + 1'b1; 46 | 47 | initial begin 48 | $monitor("Time: %0t, Input: %b, Decoder Output: %b, Encoder Output: %b", $time, in, output_from_decoder, out); 49 | #80 50 | $finish(); 51 | end 52 | 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /Counter/testbench_7.sv: -------------------------------------------------------------------------------- 1 | module testbench_hw7 (); 2 | 3 | logic clk, en_b; 4 | logic load4_b, load5_b, up; 5 | logic [3:0] load_in4; 6 | logic [4:0] load_in5; 7 | logic [3:0] q4; 8 | logic [4:0] q5; 9 | logic rco4_b, rco5_b; 10 | 11 | up_down_counter #( 12 | .N(4) 13 | ) counter4 ( 14 | .clk (clk), 15 | .en_b (en_b), 16 | .load_b (load4_b), 17 | .up (up), 18 | .load_in(load_in4), 19 | .q (q4), 20 | .rco_b (rco4_b) 21 | ); 22 | 23 | up_down_counter #( 24 | .N(5) 25 | ) counter5 ( 26 | .clk (clk), 27 | .en_b (en_b), 28 | .load_b (load5_b), 29 | .up (up), 30 | .load_in(load_in5), 31 | .q (q5), 32 | .rco_b (rco5_b) 33 | ); 34 | 35 | initial begin 36 | clk = 1'b0; 37 | en_b = 1'b1; 38 | load4_b = 1'b0; 39 | load5_b = 1'b0; 40 | up = 1'b1; 41 | load_in4 = 4'b0000; 42 | load_in5 = 5'b00000; 43 | 44 | forever #5 clk = ~clk; 45 | 46 | end 47 | 48 | initial begin 49 | #10; 50 | load4_b = 1'b0; 51 | load5_b = 1'b0; 52 | #10; 53 | en_b = 1'b0; 54 | #10; 55 | load4_b = 1'b1; 56 | load5_b = 1'b1; 57 | #320; 58 | en_b = 1'b1; 59 | up = 1'b0; 60 | load4_b = 1'b0; 61 | load5_b = 1'b0; 62 | load_in4 = 4'b1111; 63 | load_in5 = 5'b11111; 64 | #10; 65 | en_b = 1'b0; 66 | #10; 67 | load4_b = 1'b1; 68 | load5_b = 1'b1; 69 | en_b = 1'b1; 70 | #10; 71 | en_b = 1'b0; 72 | #320; 73 | load4_b = 1'b0; 74 | load5_b = 1'b0; 75 | load_in4 = 4'b1010; 76 | load_in5 = 5'b01010; 77 | #10; 78 | load4_b = 1'b1; 79 | load5_b = 1'b1; 80 | #10; 81 | up = 1'b1; 82 | load4_b = 1'b0; 83 | load5_b = 1'b0; 84 | load_in4 = 4'b0101; 85 | load_in5 = 5'b10101; 86 | #10; 87 | load4_b = 1'b1; 88 | load5_b = 1'b1; 89 | #10; 90 | $finish(); 91 | end 92 | 93 | always @(posedge clk) begin 94 | $display("Time: %0dns | en_b: %b | load4_b: %b | load5_b: %b | up: %b | load_in4: %4b | load_in5: %5b | q4: %4b | q5: %5b | rco4_b: %b | rco5_b: %b", 95 | $time, en_b, load4_b, load5_b, up, load_in4, load_in5, q4, q5, rco4_b, rco5_b); 96 | end 97 | 98 | endmodule -------------------------------------------------------------------------------- /Finite-State-Machine/tbird_fsm.sv: -------------------------------------------------------------------------------- 1 | typedef enum logic [2:0] { 2 | IDLE = 3'b000, 3 | L1 = 3'b001, 4 | L2 = 3'b011, 5 | L3 = 3'b010, 6 | R1 = 3'b101, 7 | R2 = 3'b111, 8 | R3 = 3'b110, 9 | LR3 = 3'b100 10 | } t_tbird_lights_state; 11 | 12 | module tbird_fsm ( 13 | input logic clk, 14 | input logic rst_b, 15 | input logic left, 16 | input logic right, 17 | input logic haz, 18 | output logic [2:0] l_lights, 19 | output logic [2:0] r_lights 20 | ); 21 | t_tbird_lights_state state; 22 | 23 | always_ff @(posedge clk or negedge rst_b) begin 24 | if (~rst_b) 25 | state <= IDLE; 26 | else 27 | case (state) 28 | IDLE: begin 29 | if ( (left & right) | haz) 30 | state <= LR3; 31 | else if (left) 32 | state <= L1; 33 | else if (right) 34 | state <= R1; 35 | else 36 | state <= IDLE; 37 | end 38 | L1: state <= haz ? LR3 : L2; 39 | L2: state <= haz ? LR3 : L3; 40 | L3: state <= haz ? LR3 : L1; 41 | R1: state <= haz ? LR3 : R2; 42 | R2: state <= haz ? LR3 : R3; 43 | R3: state <= haz ? LR3 : R1; 44 | LR3: state <= IDLE; 45 | endcase 46 | end 47 | 48 | always_comb begin 49 | case (state) 50 | IDLE: begin 51 | l_lights = 3'b000; 52 | r_lights = 3'b000; 53 | end 54 | L1: begin 55 | l_lights = 3'b001; 56 | r_lights = 3'b000; 57 | end 58 | L2: begin 59 | l_lights = 3'b010; 60 | r_lights = 3'b000; 61 | end 62 | L3: begin 63 | l_lights = 3'b011; 64 | r_lights = 3'b000; 65 | end 66 | R1: begin 67 | l_lights = 3'b000; 68 | r_lights = 3'b001; 69 | end 70 | R2: begin 71 | l_lights = 3'b000; 72 | r_lights = 3'b010; 73 | end 74 | R3: begin 75 | l_lights = 3'b000; 76 | r_lights = 3'b011; 77 | end 78 | LR3: begin 79 | l_lights = 3'b111; 80 | r_lights = 3'b111; 81 | end 82 | endcase 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /Decoder-Encoder-3to8/README.md: -------------------------------------------------------------------------------- 1 | # 3-to-8 Decoder and 8-to-3 Encoder Simulation 2 | 3 | ## Overview 4 | 5 | This directory houses a SystemVerilog module for simulating a 3-to-8 decoder followed by an 8-to-3 encoder. The module showcases the basic principles of digital decoding and encoding, transforming a 3-bit input into an 8-bit output, which is then re-encoded back into a 3-bit representation. This simulation is valuable for understanding digital logic conversion and the operation of decoders and encoders in digital circuits. 6 | 7 | ## File Description 8 | 9 | - **`DecoderEncoder.sv`**: The main simulation module that includes both the decoder and encoder functions. It provides an illustrative example of decoding and encoding processes by converting a 3-bit input to an 8-bit output and then back to a 3-bit output, with the initial and final 3-bit values being identical under ideal conditions. 10 | 11 | ## Simulation Setup 12 | 13 | ### Prerequisites 14 | 15 | - A SystemVerilog-compatible simulator (e.g., ModelSim, VCS, Vivado Simulator). 16 | - Basic understanding of digital circuits and SystemVerilog. 17 | 18 | ### Running the Simulation 19 | 20 | 1. **Compile** the `DecoderEncoder.sv` file in your simulation environment to prepare for simulation. 21 | 22 | 2. **Execute** the simulation by running the compiled module. Ensure that the simulation time is sufficient to observe multiple decoding and encoding cycles. 23 | 24 | 3. **Monitor** the simulation output. The module includes `$monitor` commands to display the input to the decoder, the output from the decoder, and the final output from the encoder in real-time. 25 | 26 | ## Understanding the Module 27 | 28 | The simulation module operates in the following manner: 29 | 30 | - **Decoding**: Converts a 3-bit input into an 8-bit output based on the predefined logic, where each 3-bit input value selects one of the eight outputs to be active (low in this context). 31 | 32 | - **Encoding**: Reverses the process by converting the 8-bit output back into a 3-bit value corresponding to the active output bit's original input value. 33 | 34 | The module uses a clock signal to periodically change the input value, demonstrating the dynamic operation of the decoder and encoder. 35 | 36 | ## Example Verilog Output 37 | 38 | ![Test Output](test_output.png) 39 | 40 | ## Contributing 41 | 42 | Contributions to enhance or expand the functionality of the decoder-encoder simulation are welcome. Whether it's optimizing the existing logic, adding new features, or creating additional testbenches for more complex scenarios, your input can significantly improve this educational resource. 43 | 44 | ## License 45 | 46 | This project is made available under a license that permits use, modification, and distribution for educational purposes. Redistribution and use for commercial purposes are not allowed without explicit permission. 47 | 48 | --- 49 | -------------------------------------------------------------------------------- /Guessing-Game-Assembly/README.md: -------------------------------------------------------------------------------- 1 | # PIC16F84A Guessing Game 2 | 3 | ## Overview 4 | 5 | This directory houses the assembly source code for a guessing game designed for the PIC16F84A microcontroller. The game uses a simple interface with 4 LEDs and input buttons to allow users to guess the correct LED. Success or failure is indicated through dedicated WIN and ERR LEDs, providing immediate feedback on each guess. 6 | 7 | ## File Description 8 | 9 | - **`GuessingGame.asm`**: The main assembly file for the guessing game. It contains the complete program logic, including initialization of the microcontroller, the main game loop, input handling, and LED control logic. 10 | 11 | ## Getting Started 12 | 13 | ### Prerequisites 14 | 15 | To compile and run this game, you will need: 16 | 17 | - MPLAB X IDE or any compatible assembly development environment. 18 | - A PIC16F84A microcontroller. 19 | - A programming device to upload the compiled hex file to the PIC16F84A. 20 | - An electronic setup with 4 input buttons and 6 LEDs (4 for guessing, 1 for WIN indication, and 1 for ERR indication) connected to the appropriate pins on the PIC16F84A. 21 | 22 | ### Configuration 23 | 24 | - The processor frequency is set to 100 kHz. 25 | - The instruction cycle frequency must be set to 25 kHz for proper timing and delays. 26 | - Make sure to configure your project to include the `P16F84A.INC` file for register and bit definitions specific to the PIC16F84A. 27 | 28 | ### Hardware Setup 29 | 30 | - Connect four buttons to PORTA pins (RA0-RA3) for user input. 31 | - Connect six LEDs to PORTB pins (RB0-RB5), where RB0-RB3 are guessing LEDs, RB4 is the ERR LED, and RB5 is the WIN LED. 32 | 33 | ### Compilation and Upload 34 | 35 | 1. Open the `GuessingGame.asm` file in your assembly development environment. 36 | 2. Compile the assembly code to generate a hex file. 37 | 3. Use a PIC programmer to upload the hex file to your PIC16F84A microcontroller. 38 | 4. Power up the microcontroller and start playing the guessing game! 39 | 40 | ## Gameplay 41 | 42 | 1. The game starts with one of the four guessing LEDs (RB0-RB3) lit up. 43 | 2. The player presses one of the four buttons connected to RA0-RA3 to guess which LED is active. 44 | 3. If the guess is correct, the WIN LED (RB5) lights up; if incorrect, the ERR LED (RB4) lights up. 45 | 4. The game progresses through the LEDs in a predetermined order, waiting for the player's input at each step. 46 | 5. The game resets to the initial state once all inputs are cleared after a WIN or ERR condition. 47 | 48 | ## Contributing 49 | 50 | Feel free to fork this project and contribute to making the guessing game more interesting or challenging. Suggestions for new features, bug fixes, or improvements in code efficiency are always welcome. 51 | 52 | ## License 53 | 54 | This project is open-source and available for educational purposes. It is provided "as is", without warranty of any kind. 55 | 56 | --- 57 | -------------------------------------------------------------------------------- /Arithmetic-Logic-Unit/README.md: -------------------------------------------------------------------------------- 1 | # Arithmetic Logic Unit (ALU) Simulation 2 | 3 | ## Overview 4 | 5 | The `Arithmetic-Logic-Unit` directory contains a set of SystemVerilog files designed to model and simulate the operations of an Arithmetic Logic Unit (ALU). This ALU is capable of performing various arithmetic and logic operations, depending on the selected function code. The design is modular, with a focus on scalability and ease of testing. 6 | 7 | ## Contents 8 | 9 | This directory includes the following SystemVerilog files: 10 | 11 | - **`alu_slice.sv`**: Defines a single slice of the ALU, capable of performing one bit of arithmetic or logic operation based on the input function code. It uses a ripple-carry adder slice as a fundamental building block. 12 | 13 | - **`gen_alu.sv`**: A parametrizable ALU module that generates a complete ALU of `N` bits by instantiating `N` `alu_slice` modules. It supports scalable arithmetic and logic operations across the specified bit width. 14 | 15 | - **`testbench_4.sv`**: Provides a comprehensive testbench for verifying the functionality of the ALU with 4-bit and 8-bit wide operations. It automates the testing process by cycling through test vectors defined in an external file, `test_vectors.txt`, not included in the directory but required for the testbench to function. 16 | 17 | ## Getting Started 18 | 19 | ### Prerequisites 20 | 21 | - SystemVerilog-compatible simulation environment (e.g., ModelSim, VCS, or Vivado Simulator). 22 | - Basic understanding of digital logic and SystemVerilog. 23 | 24 | ### Running Simulations 25 | 26 | 1. **Setup**: Ensure that your simulation tool is installed and configured correctly. 27 | 28 | 2. **Compile**: Compile the ALU and testbench SystemVerilog files. Include all files in the compilation process since they are interdependent. 29 | 30 | 3. **Run**: Execute the testbench. This process will automatically load the test vectors from `test_vectors.txt` and cycle through them to validate the ALU's functionality. 31 | 32 | 4. **Observe**: Monitor the simulation's output. The testbench is designed to display the input and output values for each operation, making it easy to verify correct behavior. 33 | 34 | ### Understanding the Testbench Output 35 | 36 | The testbench output is structured to provide a clear and concise view of each test case. It shows the current simulation time, the inputs to the ALU (`A`, `B`, and function code `f`), and the resulting outputs (`S` for sum/result and `CO` for carry-out), for both 4-bit and 8-bit operations. 37 | 38 | ## Contributing 39 | 40 | Contributions to improve or extend the ALU's functionality and test coverage are welcome. Please feel free to fork the repository, make your changes, and submit a pull request with a clear explanation of your modifications or additions. 41 | 42 | ## License 43 | 44 | This project is released under the MIT License. See the LICENSE file in the repository for more details. 45 | 46 | --- 47 | -------------------------------------------------------------------------------- /Carry-Lookahead-Adder/README.md: -------------------------------------------------------------------------------- 1 | # Carry-Lookahead Adder (CLA) Simulation 2 | 3 | ## Overview 4 | 5 | This directory contains SystemVerilog implementation and testbench for a Carry-Lookahead Adder (CLA), a fast digital circuit to perform addition. CLAs are known for their ability to calculate carry bits quickly, reducing the addition time compared to simple ripple-carry adders, especially for wider bit-widths. 6 | 7 | ## Files Description 8 | 9 | - **`cla-adder.sv`**: The main module defines a parametrizable CLA capable of adding two N-bit numbers along with an input carry bit. The module calculates the sum and the output carry bit, showcasing the CLA's efficiency in handling carry propagation. 10 | 11 | - **`testbench_5.sv`**: Provides a testbench to simulate and verify the functionality of the CLA module with different bit widths (e.g., 2-bit and 8-bit). It dynamically changes input values to test various addition scenarios and monitor the correctness of the sum and carry-out outputs. 12 | 13 | ## Simulation Setup 14 | 15 | ### Prerequisites 16 | 17 | - A SystemVerilog-compatible simulator (e.g., ModelSim, VCS, Vivado Simulator). 18 | - Basic understanding of digital circuits and SystemVerilog syntax. 19 | 20 | ### Running the Simulation 21 | 22 | 1. **Compile** the `cla-adder.sv` and `testbench_5.sv` files using your simulator's compilation command or IDE. 23 | 24 | 2. **Execute** the simulation by running the compiled testbench. Make sure both the CLA module and the testbench are correctly loaded and compiled. 25 | 26 | 3. **Observe** the outputs (sum and carry-out) for correctness. The testbench will automatically cycle through a range of input values for both `a` and `b` inputs, along with a fixed `c_in` value, to ensure comprehensive testing of the CLA module. 27 | 28 | ## Understanding the CLA Module 29 | 30 | The CLA module utilizes the concept of generate and propagate to quickly determine carry bits for each bit position. This approach significantly speeds up addition by reducing the dependency on the calculation of previous carry bits: 31 | 32 | - **Generate (g)**: Indicates if a carry will be generated by the two adding bits regardless of the carry-in. 33 | - **Propagate (p)**: Indicates if a carry-in will be propagated as carry-out by the two adding bits. 34 | 35 | The module calculates these terms for each bit position and uses them to efficiently compute the carry for the entire adder. 36 | 37 | ## Contributing 38 | 39 | Contributions to this CLA simulation are welcomed, including optimizations, additional features, or improved test coverage. Please feel free to fork this repository, commit your changes, and submit a pull request with a clear description of your modifications or enhancements. 40 | 41 | ## License 42 | 43 | This project is provided for educational and non-commercial use. Redistribution and use, with or without modification, are permitted provided that the original author is credited. 44 | 45 | --- 46 | -------------------------------------------------------------------------------- /Finite-State-Machine/README.md: -------------------------------------------------------------------------------- 1 | # Thunderbird Tail Lights Finite State Machine (FSM) Simulation 2 | 3 | ## Overview 4 | 5 | The `finite-state-machine` directory contains SystemVerilog modules for simulating the behavior of tail lights in a hypothetical Thunderbird car model, utilizing a finite state machine (FSM). This simulation includes modes for left turn, right turn, hazard lights, and idle states. It demonstrates the use of enumerations for state definitions and sequential logic to transition between states based on input signals. 6 | 7 | ## Files Description 8 | 9 | - **`tbird-fsm.sv`**: Defines the FSM logic for the Thunderbird tail lights. The module transitions between different states (IDLE, L1-L3 for left signals, R1-R3 for right signals, and LR3 for hazards) based on inputs for left, right, and hazard commands. 10 | 11 | - **`testbench_8.sv`**: Provides a testbench for the tbird_fsm module. It systematically applies different combinations of the left, right, and hazard inputs to verify the FSM's response under various conditions. 12 | 13 | ## Simulation Setup 14 | 15 | ### Prerequisites 16 | 17 | To simulate these modules, you'll need: 18 | 19 | - A SystemVerilog-compatible simulator (e.g., ModelSim, VCS, or Vivado Simulator). 20 | - Basic knowledge of digital logic design and SystemVerilog. 21 | 22 | ### Simulation Steps 23 | 24 | 1. **Compile** both `tbird-fsm.sv` and `testbench_8.sv` files in your SystemVerilog simulation environment. 25 | 2. **Run** the simulation by executing the `testbench_8` module. 26 | 3. **Observe** the changes in the `l_lights` and `r_lights` output vectors as different input scenarios are applied. These outputs represent the state of the left and right tail lights, respectively. 27 | 28 | ## Understanding the FSM Behavior 29 | 30 | The FSM transitions through states based on the combination of inputs: 31 | 32 | - **IDLE**: All lights are off unless a left, right, or hazard signal is activated. 33 | - **L1-L3**: Sequences through left tail lights to simulate a left turn signal. 34 | - **R1-R3**: Sequences through right tail lights to simulate a right turn signal. 35 | - **LR3**: Activates all tail lights to indicate hazard lights are on. 36 | 37 | The testbench applies various combinations of inputs over time to ensure the FSM correctly transitions between these states. 38 | 39 | ## Contributing 40 | 41 | Contributions to this FSM simulation project are welcome. Whether it's adding new features, refining the existing logic, or improving the testbench for more comprehensive coverage, your input is valuable. Please feel free to fork the repository, make your modifications, and submit a pull request with a clear explanation of your changes. 42 | 43 | ## License 44 | 45 | This project is provided for educational purposes and is not associated with any commercial product. It is available under an open-source license, allowing for modification and distribution with appropriate attribution. 46 | 47 | --- 48 | -------------------------------------------------------------------------------- /Verilog-Logic-Modules/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Logic Modules 2 | 3 | ## Overview 4 | 5 | This repository contains a collection of Verilog module files that implement basic logic operations: AND, OR, and XOR. Each file represents a unique approach to achieving the same functionality, demonstrating various Verilog coding styles and methodologies for educational purposes. These modules are designed to be simple yet illustrative, making them ideal for learners and professionals looking to deepen their understanding of Verilog and digital logic design. 6 | 7 | ## Contents 8 | 9 | The directory includes the following Verilog files: 10 | 11 | - `module_b.sv` - Implements basic logic operations using behavioral modeling with an `always_comb` block. 12 | - `module_d.sv` - Utilizes continuous assignment statements (`assign`) to achieve the logic operations. 13 | - `module_s.sv` - Employs structural modeling with gate-level primitives (`and`, `or`, `xor`) to construct the logic functions. 14 | - `testbench_2.sv` - A comprehensive testbench designed to validate the functionality of the modules by simulating various input combinations and observing the output. 15 | 16 | ## Getting Started 17 | 18 | To use these modules in your project, follow these steps: 19 | 20 | 1. Clone or download this repository to your local machine. 21 | 2. Include the desired Verilog file(s) in your project's Verilog source directory. 22 | 3. Instantiate the module(s) in your Verilog design as required. Make sure to connect the input and output ports according to your design's needs. 23 | 24 | ## Module Interfaces 25 | 26 | Each module in this collection has the following interface: 27 | 28 | - **Inputs:** 29 | - `a` : logic signal input 30 | - `b` : logic signal input 31 | - **Outputs:** 32 | - `y1` : logic output representing the AND operation between inputs `a` and `b`. 33 | - `y2` : logic output representing the OR operation between inputs `a` and `b`. 34 | - `y3` : logic output representing the XOR operation between inputs `a` and `b`. 35 | 36 | ## Usage Example 37 | 38 | Here is a simple instantiation example of `module_b`: 39 | 40 | ```verilog 41 | module top_module ( 42 | input logic top_a, 43 | input logic top_b, 44 | output logic top_y1, 45 | output logic top_y2, 46 | output logic top_y3 47 | ); 48 | 49 | module_b instance_b ( 50 | .a(top_a), 51 | .b(top_b), 52 | .y1(top_y1), 53 | .y2(top_y2), 54 | .y3(top_y3) 55 | ); 56 | 57 | endmodule 58 | ``` 59 | 60 | Replace `module_b` with `module_d` or `module_s` as needed for your application. 61 | 62 | ## Example Test Output 63 | 64 | ![Test Output](test_output.png) 65 | 66 | ## Contributing 67 | 68 | We welcome contributions and suggestions to improve these modules or add new ones. Please feel free to submit issues or pull requests through the repository's issue tracker. 69 | 70 | ## License 71 | 72 | This project is licensed under the MIT License - see the LICENSE file in the repository for details. 73 | 74 | --- 75 | -------------------------------------------------------------------------------- /PIC16F84A-Microcontrollers/README.md: -------------------------------------------------------------------------------- 1 | # PIC16F84A Assembly Programs 2 | 3 | ## Overview 4 | 5 | This repository contains a series of assembly programs designed specifically for the PIC16F84A microcontroller. These programs showcase various techniques and functionalities, from basic operations to more complex procedures, providing valuable insights into assembly programming and microcontroller manipulation. 6 | 7 | ## Contents 8 | 9 | The directory is structured with the following assembly files, each serving a unique purpose: 10 | 11 | - **`parta.ASM`**: Introduces basic setup and configuration for the PIC16F84A, along with simple arithmetic operations. It demonstrates context saving in interrupt service routines (ISR) and manipulation of the W register. 12 | 13 | - **`partb.ASM`**: Builds upon `parta.ASM`, introducing variable manipulation and arithmetic operations using a different strategy. It emphasizes on the usage of the file register for calculations. 14 | 15 | - **`partc.ASM`**: Similar to `partb.ASM`, this file further explores arithmetic operations and introduces the XOR operation as a method to achieve specific computational goals. 16 | 17 | - **`partd.ASM`**: Extends the concepts introduced in previous parts with more complex operations, including loops and conditional execution based on the manipulation of port and control registers. 18 | 19 | ## Getting Started 20 | 21 | To work with these programs, you will need an assembler like MPASM and a device programmer compatible with the PIC16F84A. Follow these steps to get started: 22 | 23 | 1. Install the necessary software for compiling and uploading assembly code to the PIC16F84A. The MPLAB X IDE from Microchip is a good starting point, as it includes MPASM. 24 | 2. Clone or download this repository to your local machine. 25 | 3. Open the desired `.ASM` file with your assembler or IDE. 26 | 4. Compile the program to generate a hex file. 27 | 5. Upload the hex file to your PIC16F84A using your device programmer. 28 | 29 | ## Prerequisites 30 | 31 | Before working with these files, ensure you have a basic understanding of assembly language and familiarity with the PIC16F84A microcontroller. It's also recommended to have the PIC16F84A datasheet handy for reference. 32 | 33 | ## Usage and Modification 34 | 35 | Feel free to use these programs as a starting point for your own projects or as educational tools to learn more about assembly programming and microcontroller operations. You are encouraged to modify and experiment with the code to better understand the workings of the PIC16F84A. 36 | 37 | ## Contributing 38 | 39 | Contributions to this collection are welcome. Whether it's adding new examples, improving existing ones, or fixing bugs, your input is valuable. Please submit pull requests or open issues as needed. 40 | 41 | ## License 42 | 43 | This project is open-source and freely available for educational and non-commercial use. Please credit the original author(s) when using or modifying these files in your projects. 44 | 45 | --- 46 | -------------------------------------------------------------------------------- /Ripple-Carry-Adder/README.md: -------------------------------------------------------------------------------- 1 | # Ripple-Carry Adder Simulation 2 | 3 | ## Overview 4 | 5 | This directory contains SystemVerilog modules for simulating a ripple-carry adder (RCA), a fundamental digital circuit used for binary addition. This set of modules demonstrates how a ripple-carry adder operates at a bit level by cascading basic adder slices. The simulation includes a 3-bit ripple-carry adder and its constituent adder slice, along with a testbench for verification. 6 | 7 | ## Contents 8 | 9 | The `Ripple-Carry-Adder` directory comprises the following SystemVerilog files: 10 | 11 | - **`rc_adder4.sv`**: Implements a 3-bit ripple-carry adder using cascaded adder slices. It takes two 3-bit inputs and produces a 3-bit sum output along with a carry-out bit. 12 | 13 | - **`rc_adder_slice.sv`**: Defines a single-bit adder slice, which is the basic building block of the ripple-carry adder. It performs single-bit binary addition with a carry-in and produces a sum bit and a carry-out bit. 14 | 15 | - **`testbench_3.sv`**: A testbench for the 3-bit ripple-carry adder, automatically cycling through all possible combinations of inputs to verify the adder's functionality. 16 | 17 | ## Getting Started 18 | 19 | ### Prerequisites 20 | 21 | - A SystemVerilog-compatible simulation environment, such as ModelSim, Vivado Simulator, or VCS. 22 | - Basic knowledge of digital logic design and SystemVerilog. 23 | 24 | ### Running Simulations 25 | 26 | 1. **Setup**: Ensure your simulation toolchain is correctly installed and set up on your system. 27 | 28 | 2. **Compile**: Compile the ripple-carry adder (`rc_adder4.sv`), the adder slice (`rc_adder_slice.sv`), and the testbench (`testbench_3.sv`). Make sure all files are included in the compilation process. 29 | 30 | 3. **Run**: Execute the testbench module. The testbench is designed to systematically test every possible input combination for the 3-bit inputs `a` and `b`. 31 | 32 | 4. **Observe**: Watch the simulation output. The testbench prints the current simulation time, input values `a` and `b`, and the resulting sum `s` along with the carry-out `co` for each test case. 33 | 34 | ## Understanding the Testbench Output 35 | 36 | The testbench output format is designed to be intuitive, displaying the simulation time alongside the input and output values: 37 | 38 | ``` 39 | TIME | A B | S CO 40 | ----------------- 41 | ...example outputs... 42 | ``` 43 | 44 | This format helps users quickly verify the functionality of the ripple-carry adder against expected results. 45 | 46 | ## Example Test Output 47 | 48 | ![Test Output](test_output.png) 49 | 50 | ## Contributing 51 | 52 | We welcome contributions to enhance the ripple-carry adder simulation, whether it's refining the existing modules, expanding the testbench, or adding new features. Please fork the repository, commit your changes, and open a pull request detailing your modifications. 53 | 54 | ## License 55 | 56 | The project is available under the MIT License. Please see the LICENSE file in the repository for full details. 57 | 58 | --- 59 | -------------------------------------------------------------------------------- /Counter/README.md: -------------------------------------------------------------------------------- 1 | # Up/Down Counter Simulation 2 | 3 | ## Overview 4 | 5 | The `Counter` directory includes SystemVerilog modules for simulating a parameterizable up/down counter. This counter supports loading initial values, counting up or down based on the input signal, and indicating when a roll-over or roll-under condition occurs. 6 | 7 | ## Files Description 8 | 9 | - **`up_down_counter.sv`**: The main module defines the logic for a parameterizable N-bit up/down counter. It features enable, load, and up/down controls along with an N-bit load input and output. The module also provides a roll-over/under output indication (`rco_b`). 10 | 11 | - **`testbench_7.sv`**: A testbench module that instantiates the up/down counter with different parameter sizes (4-bit and 5-bit) and applies various test scenarios to verify its functionality. It systematically changes the counter's mode of operation and initial load values to test all functionalities. 12 | 13 | ## Simulation Setup 14 | 15 | ### Prerequisites 16 | 17 | - A SystemVerilog-compatible simulator (e.g., ModelSim, VCS, or Vivado Simulator). 18 | - Familiarity with digital logic and SystemVerilog simulation environments. 19 | 20 | ### Running the Simulation 21 | 22 | 1. **Compile** both `up_down_counter.sv` and `testbench_7.sv` in your simulation environment. 23 | 2. **Execute** the `testbench_7` to initiate the simulation. 24 | 3. **Monitor** the simulation output for changes in the counter values (`q4`, `q5`), and the roll-over/under indicators (`rco4_b`, `rco5_b`) as the testbench applies different inputs. 25 | 26 | ## Key Features 27 | 28 | - **Parameterizable Width**: The counter's bit-width is customizable through a module parameter, allowing for flexibility in design and application. 29 | - **Up/Down Counting**: Controlled by a single input signal, the counter can either increment or decrement, demonstrating versatility in counting operations. 30 | - **Load Capability**: Enables the counter to be initialized with a specific value at any point during operation, useful for dynamic counting applications. 31 | - **Roll-over/Under Indication**: Provides an output signal to indicate when the counter has rolled over (in up mode) or rolled under (in down mode), essential for detecting boundary conditions. 32 | 33 | ## Example Usage 34 | 35 | The testbench demonstrates several operational scenarios including: 36 | - Initializing the counter with specific values and enabling up/down counting. 37 | - Dynamically switching between up and down modes to observe counting behavior. 38 | - Utilizing the roll-over/under indication to detect when the counter has completed a full cycle. 39 | 40 | ## Example Test Output 41 | 42 | ![Test Output](test_output.PNG) 43 | 44 | ## Contributing 45 | 46 | Contributions to enhance or extend the functionality of the up/down counter are welcome. This could include adding features, improving efficiency, or expanding the testbench to cover more scenarios. Please fork the repository, commit your changes, and submit a pull request with a detailed description of your contributions. 47 | 48 | ## License 49 | 50 | This project is provided for educational and non-commercial use. It is freely available for modification and distribution with proper attribution to the original author(s). 51 | 52 | --- 53 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Digital Design in `System Verilog` and `Assembly` 2 | 3 | ## Overview 4 | 5 | This repository contains a suite of digital design modules written in SystemVerilog and assembly language programs. The collection covers a range of topics from basic logic components to complex sequential designs and a microprocessor-interfacing game, suitable for educational purposes and as a reference for designing similar systems. 6 | 7 | ## Contents 8 | 9 | ### SystemVerilog Modules 10 | 11 | - **DecoderEncoder.sv**: Implements a 3-to-8 line decoder and a 8-to-3 encoder with enable functionality, translating 3-bit binary inputs into an 8-bit one-hot encoded output and vice versa. 12 | - **alu_slice.sv**: Represents a slice of an Arithmetic Logic Unit (ALU) capable of performing a variety of arithmetic and logical operations. 13 | - **cla_adder.sv**: A carry-lookahead adder module that provides fast binary addition by pre-computing carry signals. 14 | - **gen_alu.sv**: A general ALU module that combines multiple `alu_slice` modules to perform operations on wider data. 15 | - **module_b.sv**, **module_d.sv**, **module_s.sv**: Various SystemVerilog modules demonstrating different digital design constructs and methodologies. 16 | - **rc_adder4.sv**: A 4-bit ripple-carry adder built using cascaded full-adder stages. 17 | - **rc_adder_slice.sv**: A single slice/stage of a ripple-carry adder used within larger bit-width adders. 18 | - **tbird_fsm.sv**: A finite state machine (FSM) implementation for a traffic light controller (often used as an example in state machine design). 19 | - **testbench_*.sv**: A series of testbenches corresponding to various SystemVerilog modules for simulation and validation of the modules' functionalities. 20 | - **up_down_counter.sv**: A counter module that can count up or down based on control signals. 21 | 22 | ### Assembly Programs 23 | 24 | - **GuessingGame.ASM**: An interactive guessing game written in assembly language, demonstrating branching and memory interfacing on a microprocessor. 25 | - **guessing_game_simuli_Spring2023.sbs**: A stimulus file for testing the Assembly scripts of the Guessing Game (not provided here - you can easily create your own or contact me to request one.) 26 | - **parta.ASM**, **partb.ASM**, **partc.ASM**, **partd.ASM**: Assembly programs covering different aspects of assembly language programming and microprocessor operations. 27 | 28 | ## Getting Started 29 | 30 | To run the SystemVerilog files, you'll need to have an HDL simulator like ModelSim or Vivado installed. You can compile and simulate each module and its corresponding testbench to observe the behavior and validate the design. For your information, I used [ModelSim](https://www.intel.com/content/www/us/en/software-kit/750666/modelsim-intel-fpgas-standard-edition-software-version-20-1-1.html) to develop with Verilog. 31 | 32 | For the Assembly language files, an assembler and simulator for the specific microprocessor architecture they are written for **(PIC16F84A)** are required. These files can be assembled into machine code, loaded, and run on the simulator to watch the program's execution. Additionally, I use [WinAsm](https://winasm.org/) to write Assembly code. 33 | 34 | **IMPORTANT**: You are also encouraged to visit the specific directories and files to read the code and understand the design and implementation details. There will also be README files in these directories providing additional information about the modules and programs. 35 | 36 | ## How to Use 37 | 38 | 1. Clone the repository to your local machine. 39 | 2. Navigate to the specific project or file you wish to examine or simulate. 40 | 3. Open the file with an appropriate editor or IDE for SystemVerilog/assembly language. 41 | 4. To simulate SystemVerilog modules, compile them along with the testbenches using your HDL simulator and run the simulation. 42 | 5. To run assembly programs, assemble them with your chosen assembler and run them using a simulator or an actual microprocessor, if available. 43 | 44 | ## Contributing 45 | 46 | Your contributions are welcome! If you have suggestions for additional modules, improvements to existing ones, or have found any issues, please open a pull request or issue. 47 | 48 | ## License 49 | 50 | This project is licensed under the MIT License - see the [LICENSE](LICENSE) file for details. 51 | 52 | ## Acknowledgements 53 | 54 | I'd like to thank all the contributors and users of this repository for their interest in digital design and assembly programming! 55 | 56 | --- 57 | 58 | Created with ❤️ by [Son Nguyen](https://github.com/hoangsonww) in 2024. 59 | -------------------------------------------------------------------------------- /PIC16F84A-Microcontrollers/partc.ASM: -------------------------------------------------------------------------------- 1 | ;********************************************************************** 2 | ; * 3 | ; This file is a basic code template for assembly code generation * 4 | ; on the PIC16F84A. This file contains the basic code * 5 | ; building blocks to build upon. * 6 | ; * 7 | ; Refer to the MPASM User's Guide for additional information on * 8 | ; features of the assembler (Document DS33014). * 9 | ; * 10 | ; Refer to the respective PIC data sheet for additional * 11 | ; information on the instruction set. * 12 | ; * 13 | ;********************************************************************** 14 | ; * 15 | ; Filename: partc.asm * 16 | ; Date: * 17 | ; File Version: * 18 | ; * 19 | ; Author: * 20 | ; Company: * 21 | ; * 22 | ; * 23 | ;********************************************************************** 24 | ; * 25 | ; Files required: P16F84A.INC * 26 | ; * 27 | ; * 28 | ; * 29 | ;********************************************************************** 30 | ; * 31 | ; Notes: * 32 | ; * 33 | ; * 34 | ; * 35 | ; * 36 | ;********************************************************************** 37 | 38 | 39 | list p=16F84A ; list directive to define processor 40 | #include ; processor specific variable definitions 41 | 42 | __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _RC_OSC 43 | 44 | ; '__CONFIG' directive is used to embed configuration data within .asm file. 45 | ; The lables following the directive are located in the respective .inc file. 46 | ; See respective data sheet for additional information on configuration word. 47 | 48 | ;***** VARIABLE DEFINITIONS 49 | w_temp EQU 0x0C ; variable used for context saving 50 | status_temp EQU 0x0D ; variable used for context saving 51 | my_result EQU 0x0E 52 | ctr EQU 0x0F 53 | ;********************************************************************** 54 | RESET_VECTOR CODE 0x0000 ; processor reset vector 55 | goto start ; go to beginning of program 56 | 57 | ISR CODE 0x0004 ; interrupt vector location 58 | 59 | Interrupt: 60 | 61 | movwf w_temp ; save off current W register contents 62 | movf STATUS,w ; move status register into W register 63 | movwf status_temp ; save off contents of STATUS register 64 | 65 | ; Place ISR Here 66 | 67 | movf status_temp,w ; retrieve copy of STATUS register 68 | movwf STATUS ; restore pre-isr STATUS register contents 69 | swapf w_temp,f 70 | swapf w_temp,w ; restore pre-isr W register contents 71 | retfie ; return from interrupt 72 | 73 | MAIN_PROGRAM CODE 74 | 75 | ; David Nguyen 76 | 77 | start: 78 | 79 | ; remaining code goes here 80 | clrf my_result 81 | movlw 0x0A 82 | movwf ctr ; makes the counter value equal to 10 83 | 84 | loop1: 85 | incf my_result,f 86 | decfsz ctr,f 87 | goto loop1 88 | movlw 0x04 89 | movwf ctr 90 | 91 | ; Complete for the subtraction loop 92 | loop2: 93 | movlw 3 94 | subwf my_result,f 95 | decfsz ctr,f 96 | goto loop2 97 | 98 | ; Complete the comparison with -2 part 99 | ; remember this is xor with 1 code from part b 100 | movlw 1 101 | xorwf my_result,1 102 | 103 | fin: 104 | goto fin 105 | 106 | END ; directive 'end of program' 107 | 108 | -------------------------------------------------------------------------------- /PIC16F84A-Microcontrollers/partb.ASM: -------------------------------------------------------------------------------- 1 | ;********************************************************************** 2 | ; * 3 | ; This file is a basic code template for assembly code generation * 4 | ; on the PIC16F84A. This file contains the basic code * 5 | ; building blocks to build upon. * 6 | ; * 7 | ; Refer to the MPASM User's Guide for additional information on * 8 | ; features of the assembler (Document DS33014). * 9 | ; * 10 | ; Refer to the respective PIC data sheet for additional * 11 | ; information on the instruction set. * 12 | ; * 13 | ;********************************************************************** 14 | ; * 15 | ; Filename: partb.asm * 16 | ; Date: * 17 | ; File Version: * 18 | ; * 19 | ; Author: * 20 | ; Company: * 21 | ; * 22 | ; * 23 | ;********************************************************************** 24 | ; * 25 | ; Files required: P16F84A.INC * 26 | ; * 27 | ; * 28 | ; * 29 | ;********************************************************************** 30 | ; * 31 | ; Notes: * 32 | ; * 33 | ; * 34 | ; * 35 | ; * 36 | ;********************************************************************** 37 | 38 | 39 | list p=16F84A ; list directive to define processor 40 | #include ; processor specific variable definitions 41 | 42 | __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _RC_OSC 43 | 44 | ; '__CONFIG' directive is used to embed configuration data within .asm file. 45 | ; The lables following the directive are located in the respective .inc file. 46 | ; See respective data sheet for additional information on configuration word. 47 | 48 | ;***** VARIABLE DEFINITIONS 49 | w_temp EQU 0x0C ; variable used for context saving 50 | status_temp EQU 0x0D ; variable used for context saving 51 | my_result EQU 0x0E 52 | ;********************************************************************** 53 | RESET_VECTOR CODE 0x0000 ; processor reset vector 54 | goto start ; go to beginning of program 55 | 56 | ISR CODE 0x0004 ; interrupt vector location 57 | 58 | Interrupt: 59 | 60 | movwf w_temp ; save off current W register contents 61 | movf STATUS,w ; move status register into W register 62 | movwf status_temp ; save off contents of STATUS register 63 | 64 | ; Place ISR Here 65 | 66 | movf status_temp,w ; retrieve copy of STATUS register 67 | movwf STATUS ; restore pre-isr STATUS register contents 68 | swapf w_temp,f 69 | swapf w_temp,w ; restore pre-isr W register contents 70 | retfie ; return from interrupt 71 | 72 | MAIN_PROGRAM CODE 73 | 74 | ; David Nguyen 75 | 76 | start: 77 | 78 | ; remaining code goes here 79 | clrf my_result 80 | ; Add 1 to my_result ten times 81 | incf my_result,f ; make sure you increment my_result nine more times 82 | incf my_result,f 83 | incf my_result,f 84 | incf my_result,f 85 | incf my_result,f 86 | incf my_result,f 87 | incf my_result,f 88 | incf my_result,f 89 | incf my_result,f 90 | incf my_result,f 91 | 92 | movlw 3 ; this line writes 3 to w-reg 93 | subwf my_result,f ; this line will subtract 3 from my_result 94 | ; repeat the subtraction line three more times 95 | subwf my_result,f 96 | subwf my_result,f 97 | subwf my_result,f 98 | 99 | movlw 1 100 | xorwf my_result,1 101 | 102 | 103 | fin: 104 | goto fin 105 | 106 | 107 | 108 | END ; directive 'end of program' 109 | 110 | -------------------------------------------------------------------------------- /Guessing-Game-Assembly/P16F84A.inc: -------------------------------------------------------------------------------- 1 | LIST 2 | ; P16F84A.INC Standard Header File, Version 2.00 Microchip Technology, Inc. 3 | NOLIST 4 | 5 | ; This header file defines configurations, registers, and other useful bits of 6 | ; information for the PIC16F84 microcontroller. These names are taken to match 7 | ; the data sheets as closely as possible. 8 | 9 | ; Note that the processor must be selected before this file is 10 | ; included. The processor may be selected the following ways: 11 | 12 | ; 1. Command line switch: 13 | ; C:\ MPASM MYFILE.ASM /PIC16F84A 14 | ; 2. LIST directive in the source file 15 | ; LIST P=PIC16F84A 16 | ; 3. Processor Type entry in the MPASM full-screen interface 17 | 18 | ;========================================================================== 19 | ; 20 | ; Revision History 21 | ; 22 | ;========================================================================== 23 | 24 | ;Rev: Date: Reason: 25 | 26 | ;1.00 2/15/99 Initial Release 27 | 28 | ;========================================================================== 29 | ; 30 | ; Verify Processor 31 | ; 32 | ;========================================================================== 33 | 34 | IFNDEF __16F84A 35 | MESSG "Processor-header file mismatch. Verify selected processor." 36 | ENDIF 37 | 38 | ;========================================================================== 39 | ; 40 | ; Register Definitions 41 | ; 42 | ;========================================================================== 43 | 44 | W EQU H'0000' 45 | F EQU H'0001' 46 | 47 | ;----- Register Files------------------------------------------------------ 48 | 49 | INDF EQU H'0000' 50 | TMR0 EQU H'0001' 51 | PCL EQU H'0002' 52 | STATUS EQU H'0003' 53 | FSR EQU H'0004' 54 | PORTA EQU H'0005' 55 | PORTB EQU H'0006' 56 | EEDATA EQU H'0008' 57 | EEADR EQU H'0009' 58 | PCLATH EQU H'000A' 59 | INTCON EQU H'000B' 60 | 61 | OPTION_REG EQU H'0081' 62 | TRISA EQU H'0085' 63 | TRISB EQU H'0086' 64 | EECON1 EQU H'0088' 65 | EECON2 EQU H'0089' 66 | 67 | ;----- STATUS Bits -------------------------------------------------------- 68 | 69 | IRP EQU H'0007' 70 | RP1 EQU H'0006' 71 | RP0 EQU H'0005' 72 | NOT_TO EQU H'0004' 73 | NOT_PD EQU H'0003' 74 | Z EQU H'0002' 75 | DC EQU H'0001' 76 | C EQU H'0000' 77 | 78 | ;----- INTCON Bits -------------------------------------------------------- 79 | 80 | GIE EQU H'0007' 81 | EEIE EQU H'0006' 82 | T0IE EQU H'0005' 83 | INTE EQU H'0004' 84 | RBIE EQU H'0003' 85 | T0IF EQU H'0002' 86 | INTF EQU H'0001' 87 | RBIF EQU H'0000' 88 | 89 | ;----- OPTION_REG Bits ---------------------------------------------------- 90 | 91 | NOT_RBPU EQU H'0007' 92 | INTEDG EQU H'0006' 93 | T0CS EQU H'0005' 94 | T0SE EQU H'0004' 95 | PSA EQU H'0003' 96 | PS2 EQU H'0002' 97 | PS1 EQU H'0001' 98 | PS0 EQU H'0000' 99 | 100 | ;----- EECON1 Bits -------------------------------------------------------- 101 | 102 | EEIF EQU H'0004' 103 | WRERR EQU H'0003' 104 | WREN EQU H'0002' 105 | WR EQU H'0001' 106 | RD EQU H'0000' 107 | 108 | ;========================================================================== 109 | ; 110 | ; RAM Definition 111 | ; 112 | ;========================================================================== 113 | 114 | __MAXRAM H'CF' 115 | __BADRAM H'07', H'50'-H'7F', H'87' 116 | 117 | ;========================================================================== 118 | ; 119 | ; Configuration Bits 120 | ; 121 | ;========================================================================== 122 | 123 | _CP_ON EQU H'000F' 124 | _CP_OFF EQU H'3FFF' 125 | _PWRTE_ON EQU H'3FF7' 126 | _PWRTE_OFF EQU H'3FFF' 127 | _WDT_ON EQU H'3FFF' 128 | _WDT_OFF EQU H'3FFB' 129 | _LP_OSC EQU H'3FFC' 130 | _XT_OSC EQU H'3FFD' 131 | _HS_OSC EQU H'3FFE' 132 | _RC_OSC EQU H'3FFF' 133 | 134 | LIST -------------------------------------------------------------------------------- /PIC16F84A-Microcontrollers/P16F84A.inc: -------------------------------------------------------------------------------- 1 | LIST 2 | ; P16F84A.INC Standard Header File, Version 2.00 Microchip Technology, Inc. 3 | NOLIST 4 | 5 | ; This header file defines configurations, registers, and other useful bits of 6 | ; information for the PIC16F84 microcontroller. These names are taken to match 7 | ; the data sheets as closely as possible. 8 | 9 | ; Note that the processor must be selected before this file is 10 | ; included. The processor may be selected the following ways: 11 | 12 | ; 1. Command line switch: 13 | ; C:\ MPASM MYFILE.ASM /PIC16F84A 14 | ; 2. LIST directive in the source file 15 | ; LIST P=PIC16F84A 16 | ; 3. Processor Type entry in the MPASM full-screen interface 17 | 18 | ;========================================================================== 19 | ; 20 | ; Revision History 21 | ; 22 | ;========================================================================== 23 | 24 | ;Rev: Date: Reason: 25 | 26 | ;1.00 2/15/99 Initial Release 27 | 28 | ;========================================================================== 29 | ; 30 | ; Verify Processor 31 | ; 32 | ;========================================================================== 33 | 34 | IFNDEF __16F84A 35 | MESSG "Processor-header file mismatch. Verify selected processor." 36 | ENDIF 37 | 38 | ;========================================================================== 39 | ; 40 | ; Register Definitions 41 | ; 42 | ;========================================================================== 43 | 44 | W EQU H'0000' 45 | F EQU H'0001' 46 | 47 | ;----- Register Files------------------------------------------------------ 48 | 49 | INDF EQU H'0000' 50 | TMR0 EQU H'0001' 51 | PCL EQU H'0002' 52 | STATUS EQU H'0003' 53 | FSR EQU H'0004' 54 | PORTA EQU H'0005' 55 | PORTB EQU H'0006' 56 | EEDATA EQU H'0008' 57 | EEADR EQU H'0009' 58 | PCLATH EQU H'000A' 59 | INTCON EQU H'000B' 60 | 61 | OPTION_REG EQU H'0081' 62 | TRISA EQU H'0085' 63 | TRISB EQU H'0086' 64 | EECON1 EQU H'0088' 65 | EECON2 EQU H'0089' 66 | 67 | ;----- STATUS Bits -------------------------------------------------------- 68 | 69 | IRP EQU H'0007' 70 | RP1 EQU H'0006' 71 | RP0 EQU H'0005' 72 | NOT_TO EQU H'0004' 73 | NOT_PD EQU H'0003' 74 | Z EQU H'0002' 75 | DC EQU H'0001' 76 | C EQU H'0000' 77 | 78 | ;----- INTCON Bits -------------------------------------------------------- 79 | 80 | GIE EQU H'0007' 81 | EEIE EQU H'0006' 82 | T0IE EQU H'0005' 83 | INTE EQU H'0004' 84 | RBIE EQU H'0003' 85 | T0IF EQU H'0002' 86 | INTF EQU H'0001' 87 | RBIF EQU H'0000' 88 | 89 | ;----- OPTION_REG Bits ---------------------------------------------------- 90 | 91 | NOT_RBPU EQU H'0007' 92 | INTEDG EQU H'0006' 93 | T0CS EQU H'0005' 94 | T0SE EQU H'0004' 95 | PSA EQU H'0003' 96 | PS2 EQU H'0002' 97 | PS1 EQU H'0001' 98 | PS0 EQU H'0000' 99 | 100 | ;----- EECON1 Bits -------------------------------------------------------- 101 | 102 | EEIF EQU H'0004' 103 | WRERR EQU H'0003' 104 | WREN EQU H'0002' 105 | WR EQU H'0001' 106 | RD EQU H'0000' 107 | 108 | ;========================================================================== 109 | ; 110 | ; RAM Definition 111 | ; 112 | ;========================================================================== 113 | 114 | __MAXRAM H'CF' 115 | __BADRAM H'07', H'50'-H'7F', H'87' 116 | 117 | ;========================================================================== 118 | ; 119 | ; Configuration Bits 120 | ; 121 | ;========================================================================== 122 | 123 | _CP_ON EQU H'000F' 124 | _CP_OFF EQU H'3FFF' 125 | _PWRTE_ON EQU H'3FF7' 126 | _PWRTE_OFF EQU H'3FFF' 127 | _WDT_ON EQU H'3FFF' 128 | _WDT_OFF EQU H'3FFB' 129 | _LP_OSC EQU H'3FFC' 130 | _XT_OSC EQU H'3FFD' 131 | _HS_OSC EQU H'3FFE' 132 | _RC_OSC EQU H'3FFF' 133 | 134 | LIST -------------------------------------------------------------------------------- /PIC16F84A-Microcontrollers/partd.ASM: -------------------------------------------------------------------------------- 1 | ;********************************************************************** 2 | ; * 3 | ; This file is a basic code template for assembly code generation * 4 | ; on the PIC16F84A. This file contains the basic code * 5 | ; building blocks to build upon. * 6 | ; * 7 | ; Refer to the MPASM User's Guide for additional information on * 8 | ; features of the assembler (Document DS33014). * 9 | ; * 10 | ; Refer to the respective PIC data sheet for additional * 11 | ; information on the instruction set. * 12 | ; * 13 | ;********************************************************************** 14 | ; * 15 | ; Filename: partd.asm * 16 | ; Date: * 17 | ; File Version: * 18 | ; * 19 | ; Author: * 20 | ; Company: * 21 | ; * 22 | ; * 23 | ;********************************************************************** 24 | ; * 25 | ; Files required: P16F84A.INC * 26 | ; * 27 | ; * 28 | ; * 29 | ;********************************************************************** 30 | ; * 31 | ; Notes: * 32 | ; * 33 | ; * 34 | ; * 35 | ; * 36 | ;********************************************************************** 37 | 38 | 39 | list p=16F84A ; list directive to define processor 40 | #include ; processor specific variable definitions 41 | 42 | __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _RC_OSC 43 | 44 | ; '__CONFIG' directive is used to embed configuration data within .asm file. 45 | ; The lables following the directive are located in the respective .inc file. 46 | ; See respective data sheet for additional information on configuration word. 47 | 48 | ;***** VARIABLE DEFINITIONS 49 | w_temp EQU 0x0C ; variable used for context saving 50 | status_temp EQU 0x0D ; variable used for context saving 51 | my_result EQU 0x0E 52 | ctr EQU 0x0F 53 | ;********************************************************************** 54 | RESET_VECTOR CODE 0x0000 ; processor reset vector 55 | goto start ; go to beginning of program 56 | 57 | ISR CODE 0x0004 ; interrupt vector location 58 | 59 | Interrupt: 60 | 61 | movwf w_temp ; save off current W register contents 62 | movf STATUS,w ; move status register into W register 63 | movwf status_temp ; save off contents of STATUS register 64 | 65 | ; Place ISR Here 66 | 67 | movf status_temp,w ; retrieve copy of STATUS register 68 | movwf STATUS ; restore pre-isr STATUS register contents 69 | swapf w_temp,f 70 | swapf w_temp,w ; restore pre-isr W register contents 71 | retfie ; return from interrupt 72 | 73 | MAIN_PROGRAM CODE 74 | 75 | ; David Nguyen 76 | 77 | start: 78 | 79 | ; remaining code goes here 80 | clrf my_result 81 | movlw 0x0A 82 | movwf ctr ; makes the counter value equal to 10 83 | 84 | movf PORTB,w 85 | andlw 0x0F ; this will retain the least significant four bits (bits 3-0) 86 | ; and it will remove the value in the bits 7-4 87 | 88 | 89 | loop1: 90 | addwf my_result,f 91 | decfsz ctr,f 92 | goto loop1 93 | 94 | ; first set the ctr to 4 for the subtraction loop 95 | movlw 0x04 96 | movwf ctr 97 | 98 | swapf PORTB,w ; get the decrement amount from PORTB 99 | andlw 0x0F 100 | 101 | ; Complete for the subtraction loop 102 | loop2: 103 | subwf my_result,f 104 | decfsz ctr,f 105 | goto loop2 106 | 107 | 108 | ; Complete the comparison with -2 part 109 | ; remember this is xor with 1 code from part b 110 | movlw 1 111 | xorwf my_result,1 112 | 113 | fin: 114 | goto fin 115 | 116 | END ; directive 'end of program' 117 | 118 | -------------------------------------------------------------------------------- /PIC16F84A-Microcontrollers/parta.ASM: -------------------------------------------------------------------------------- 1 | ;********************************************************************** 2 | ; * 3 | ; This file is a basic code template for assembly code generation * 4 | ; on the PIC16F84A. This file contains the basic code * 5 | ; building blocks to build upon. * 6 | ; * 7 | ; Refer to the MPASM User's Guide for additional information on * 8 | ; features of the assembler (Document DS33014). * 9 | ; * 10 | ; Refer to the respective PIC data sheet for additional * 11 | ; information on the instruction set. * 12 | ; * 13 | ;********************************************************************** 14 | ; * 15 | ; Filename: parta.asm * 16 | ; Date: * 17 | ; File Version: * 18 | ; * 19 | ; Author: * 20 | ; Company: * 21 | ; * 22 | ; * 23 | ;********************************************************************** 24 | ; * 25 | ; Files required: P16F84A.INC * 26 | ; * 27 | ; * 28 | ; * 29 | ;********************************************************************** 30 | ; * 31 | ; Notes: * 32 | ; * 33 | ; * 34 | ; * 35 | ; * 36 | ;********************************************************************** 37 | 38 | 39 | list p=16F84A ; list directive to define processor 40 | #include ; processor specific variable definitions 41 | 42 | __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _RC_OSC 43 | 44 | ; '__CONFIG' directive is used to embed configuration data within .asm file. 45 | ; The lables following the directive are located in the respective .inc file. 46 | ; See respective data sheet for additional information on configuration word. 47 | 48 | ;***** VARIABLE DEFINITIONS 49 | w_temp EQU 0x0C ; variable used for context saving 50 | status_temp EQU 0x0D ; variable used for context saving 51 | 52 | ;********************************************************************** 53 | RESET_VECTOR CODE 0x0000 ; processor reset vector 54 | goto start ; go to beginning of program 55 | 56 | ISR CODE 0x0004 ; interrupt vector location 57 | 58 | Interrupt: 59 | 60 | movwf w_temp ; save off current W register contents 61 | movf STATUS,w ; move status register into W register 62 | movwf status_temp ; save off contents of STATUS register 63 | 64 | ; Place ISR Here 65 | 66 | movf status_temp,w ; retrieve copy of STATUS register 67 | movwf STATUS ; restore pre-isr STATUS register contents 68 | swapf w_temp,f 69 | swapf w_temp,w ; restore pre-isr W register contents 70 | retfie ; return from interrupt 71 | 72 | MAIN_PROGRAM CODE 73 | 74 | ; David Nguyen 75 | 76 | start: 77 | 78 | ; remaining code goes here 79 | 80 | clrw ; clears the w-register 81 | ; need to add 1 ten times to w-reg 82 | addlw 1 ; adds the value 1 to the w-reg 83 | addlw 1 ; adds the value 1 to the w-reg 84 | addlw 1 ; adds the value 1 to the w-reg 85 | addlw 1 ; adds the value 1 to the w-reg 86 | addlw 1 ; adds the value 1 to the w-reg 87 | addlw 1 ; adds the value 1 to the w-reg 88 | addlw 1 ; adds the value 1 to the w-reg 89 | addlw 1 ; adds the value 1 to the w-reg 90 | addlw 1 ; adds the value 1 to the w-reg 91 | addlw 1 ; adds the value 1 to the w-reg 92 | 93 | ; Next step is to subtract 3 four times 94 | addlw -3 ; this instruction will subtract 3 from w-reg 95 | addlw -3 ; this instruction will subtract 3 from w-reg 96 | addlw -3 ; this instruction will subtract 3 from w-reg 97 | addlw -3 ; this instruction will subtract 3 from w-reg 98 | 99 | ;Need to compare if the result is -2 100 | ;-2 in two's complement representation is 0xFE ('B 111111110) 101 | ;We do not have xnor as instruction so we need to use xor with 'B00000001 102 | xorlw 1 103 | 104 | fin: 105 | goto fin 106 | 107 | 108 | END ; directive 'end of program' 109 | 110 | -------------------------------------------------------------------------------- /.idea/workspace.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | 7 | 8 | 9 | 10 | 15 | 16 | 18 | 24 | 30 | 31 | 33 | { 34 | "associatedIndex": 2 35 | } 36 | 37 | 38 | 39 | 40 | 41 | 44 | { 45 | "keyToString": { 46 | "ASKED_SHARE_PROJECT_CONFIGURATION_FILES": "true", 47 | "RunOnceActivity.OpenProjectViewOnStart": "true", 48 | "RunOnceActivity.ShowReadmeOnStart": "true", 49 | "SHARE_PROJECT_CONFIGURATION_FILES": "true", 50 | "git-widget-placeholder": "master", 51 | "ignore.virus.scanning.warn.message": "true", 52 | "kotlin-language-version-configured": "true", 53 | "last_opened_file_path": "C:/Users/hoang/IdeaProjects/Digital-Design-Labs/Guessing-Game-Assembly", 54 | "node.js.detected.package.eslint": "true", 55 | "node.js.detected.package.tslint": "true", 56 | "node.js.selected.package.eslint": "(autodetect)", 57 | "node.js.selected.package.tslint": "(autodetect)", 58 | "nodejs_package_manager_path": "npm", 59 | "settings.editor.selected.configurable": "preferences.general", 60 | "vue.rearranger.settings.migration": "true" 61 | } 62 | } 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 1710281231539 88 | 95 | 96 | 103 | 104 | 111 | 112 | 119 | 122 | 123 | 125 | 126 | 127 | 128 | 130 | -------------------------------------------------------------------------------- /Guessing-Game-Assembly/GuessingGame.ASM: -------------------------------------------------------------------------------- 1 | ;********************************************************************** 2 | ; * 3 | ; An Assembly file for the Guessing Game in PIC16F84A. * 4 | ; The goal of this program is to implement a simple guessing game * 5 | ; with 4 LEDs, where the user inputs a combination via the PORTA * 6 | ; pins and the program checks the input against the active LED. If * 7 | ; the input is correct, the WIN LED will light up, otherwise, the * 8 | ; ERR LED will light up. * 9 | ; * 10 | ;********************************************************************** 11 | ; * 12 | ; Filename: GuessingGame.asm * 13 | ; Date: 04/30/2023 * 14 | ; File Version: 1.0 * 15 | ; * 16 | ; Author: David Nguyen * 17 | ; Company: Case Western Reserve University * 18 | ; * 19 | ; * 20 | ;********************************************************************** 21 | ; * 22 | ; Files required: P16F84A.INC * 23 | ; * 24 | ; * 25 | ;********************************************************************** 26 | ; * 27 | ; Note: The processor frequency must be set to 100 kHz and the * 28 | ; instruction frequency must be set to 25 kHz in order to * 29 | ; monitor the outputs and for the delay to achieve a ~1 second * * 30 | ; delay! * 31 | ; * 32 | ;********************************************************************** 33 | 34 | list p=16F84A ; Directive to define the PIC16F84A 35 | #include ; INC file for the PIC16F84A 36 | 37 | ; CPU configuration 38 | ; (16F84 with RC osc, watchdog timer off, power-up timer on) 39 | __CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _RC_OSC 40 | 41 | ; '__CONFIG' directive is used to embed configuration data within .asm file. 42 | ; The lables following the directive are located in the respective .inc file. 43 | ; See respective data sheet for additional information on configuration word. 44 | 45 | ; ******************** VARIABLE & STATE DEFINITIONS ********************** ; 46 | delay_outer_counter EQU 0x0D ; Variable used for outer delay loop 47 | delay_inner_counter EQU 0x0E ; Variable used for inner delay loop 48 | current_state EQU 0x0C ; Variable used for current state saving 49 | state_S1 EQU B'00000001' ; State S1 (RB0 = 1) 50 | state_S2 EQU B'00000010' ; State S2 (RB1 = 1) 51 | state_S3 EQU B'00000100' ; State S3 (RB2 = 1) 52 | state_S4 EQU B'00001000' ; State S4 (RB3 = 1) 53 | state_SERR EQU B'00010000' ; State SERR (RB4 = 1) 54 | state_SOK EQU B'00100000' ; State SOK (win, so RB5 = 1) 55 | 56 | ; Some handy MACRO definitions: 57 | ; (inspired by author: Steven L. Garverick in his "tbird.asm" file): 58 | 59 | If_Bit_Is_Set macro fr, bit, label 60 | btfss fr, bit ; if (fr.bit) then execute code following macro 61 | goto label ; else goto label 62 | endm 63 | 64 | If_Bit_Is_Clear macro fr, bit, label 65 | btfsc fr, bit ; if (! fr.bit) then execute code following macro 66 | goto label ; else goto label 67 | endm 68 | 69 | If_Bit_Equals_Literal macro fr, lit, label 70 | movlw lit 71 | xorwf fr, W 72 | btfss STATUS, Z ; (fr == lit) then execute code following macro 73 | goto label ; else goto label 74 | endm 75 | 76 | If_Bit_Not_Equals_Literal macro fr, lit, label 77 | movlw lit 78 | xorwf fr, W 79 | btfsc STATUS, Z ; (fr != lit) then execute code following macro 80 | goto label ; else goto label 81 | endm 82 | 83 | Move_Literal_To_F macro lit, fr 84 | movlw lit 85 | movwf fr 86 | endm 87 | 88 | Move_F_To_F macro from, to 89 | movf from, W 90 | movwf to 91 | endm 92 | 93 | ;***************************** RESER VECTORS ******************************; 94 | ; (This portion is inspired by Steven M. Garverick in his tbird.asm program) 95 | 96 | org 0x00 ; reset at address 0 97 | reset: goto start ; skip reserved program addresses 98 | 99 | org 0x08 ; beginning of user code 100 | 101 | ; ************************ START OF MAIN PROGRAM ************************ ; 102 | 103 | MAIN_PROGRAM CODE 104 | 105 | start: 106 | 107 | ; David Nguyen 108 | 109 | ; Initializing the inputs and outputs for the PIC16F84A: 110 | bsf STATUS, RP0 ; Switch to Bank 1 111 | movlw 0x0F ; Sets RA0-3 as inputs 112 | movwf TRISA ; Sets RA0-3 as inputs 113 | movlw B'11000000' ; Sets RB0-5 as outputs (no info provided for unused 114 | ; RB6-7, so set them as inputs.) 115 | movwf TRISB ; Sets RB0-5 as outputs, RB6-7 as unused inputs 116 | bcf STATUS, RP0 ; Switch back to Bank 0 117 | 118 | ; Initialize the state machine to state S1 (binary: 00000001): 119 | initialize_state_machine: 120 | ; Initialize current_State variable to S1 (binary: 00000001) 121 | movlw state_S1 122 | movwf current_state 123 | 124 | ; The state machine's main, indefinite loop: 125 | state_machine_loop: 126 | ; Load the current state into PORTB outputs 127 | movf current_state, W 128 | movwf PORTB 129 | ; Calls the subroutine to delay for 1 second before each state change 130 | goto delay_one_second 131 | 132 | ;************************************************************************** 133 | ; SUBROUTINES * 134 | ;************************************************************************** 135 | 136 | ; Calls the subroutine to handle SOK and SERR states 137 | ; If at state SOK or SERR, the program will only continue when the inputs are 138 | ; CLEARED - so the player must clear the inputs before continue playing: 139 | handle_SOK_SERR_states: 140 | ; If the curent state is SOK, clear (reset) the inputs before continuing 141 | movlw state_SOK 142 | xorwf current_state, W 143 | btfsc STATUS, Z 144 | goto clear_the_inputs_and_lights 145 | ; If the curent state is SERR, clear (reset) the inputs before continuing 146 | movlw state_SERR 147 | xorwf current_state, W 148 | btfsc STATUS, Z 149 | goto clear_the_inputs_and_lights 150 | ; Otherwise, handle the cases where the current state is not SOK or SERR 151 | goto handle_not_SOK_or_SERR_states 152 | 153 | ; The subroutine to clear the inputs when they are not needed 154 | clear_the_inputs_and_lights: 155 | movf PORTA, W 156 | andlw 0x0F 157 | xorlw 0x00 158 | btfsc STATUS, Z 159 | ; Go back to intial state of the machine 160 | goto initialize_state_machine 161 | ; Also attempts to clear the inputs as well as the lights 162 | goto clear_the_inputs_and_lights 163 | 164 | ; If the current state is not SOK or SERR then rotate the lights normally 165 | handle_not_SOK_or_SERR_states: 166 | ; Move the current inputs to the working register 167 | movf PORTA, W 168 | ; Mask the upper 4 bits to check for the rest of PORTA bits (RA0-3) 169 | andlw B'00001111' 170 | ; Check if there is any inputs 171 | xorlw B'00000000' 172 | ; If bit is clear, then go to the next state (S1, S2, S3, or S4) 173 | btfsc STATUS, Z 174 | goto compute_next_state 175 | ; Otherwise, if there is at least one input, check every single state 176 | ; from S1 to S3 177 | ; First, check G1 guesses: 178 | movlw state_S1 179 | xorwf current_state, W 180 | btfsc STATUS, Z 181 | goto handle_G1_guesses 182 | ; Then, check G2 guesses: 183 | movlw state_S2 184 | xorwf current_state, W 185 | btfsc STATUS, Z 186 | goto handle_G2_guesses 187 | ; Then, check G3 guesses: 188 | movlw state_S3 189 | xorwf current_state, W 190 | btfsc STATUS, Z 191 | goto handle_G3_guesses 192 | ; If input is not from G1 to G3, it must be G4: 193 | goto handle_G4_guesses 194 | 195 | ; Handle the case where G1 (RA0) is pressed 196 | handle_G1_guesses: 197 | movf PORTA, W 198 | andlw 0x0F 199 | xorlw state_S1 200 | btfsc STATUS, Z 201 | ; If G1 is pressed and the current state is S1, the guess is correct 202 | goto handle_correct_guesses 203 | ; If G1 is pressed but the current state is not S1, the guess is incorrect 204 | goto handle_incorrect_guesses 205 | 206 | ; Handle the case where G2 (RA1) is pressed 207 | handle_G2_guesses: 208 | movf PORTA, W 209 | andlw 0x0F 210 | xorlw state_S2 211 | btfsc STATUS, Z 212 | ; If G2 is pressed and the current state is S2, the guess is correct 213 | goto handle_correct_guesses 214 | ; If G2 is pressed but the current state is not S2, the guess is incorrect 215 | goto handle_incorrect_guesses 216 | 217 | ; Handle the case where G3 (RA2) is pressed 218 | handle_G3_guesses: 219 | movf PORTA, W 220 | andlw 0x0F 221 | xorlw state_S3 222 | btfsc STATUS, Z 223 | ; If G3 is pressed and the current state is S3, the guess is correct 224 | goto handle_correct_guesses 225 | ; If G3 is pressed but the current state is not S3, the guess is incorrect 226 | goto handle_incorrect_guesses 227 | 228 | ; Handle the case where G4 (RA3) is pressed 229 | handle_G4_guesses: 230 | movf PORTA, W 231 | andlw 0x0F 232 | xorlw state_S4 233 | btfsc STATUS, Z 234 | ; If G4 is pressed and the current state is S4, the guess is correct 235 | goto handle_correct_guesses 236 | ; If G4 is pressed but the current state is not S4, the guess is incorrect 237 | goto handle_incorrect_guesses 238 | 239 | ; Handle the case where an incorrect guess is made 240 | handle_incorrect_guesses: 241 | ; Sets the current state to the SERR state 242 | movlw state_SERR 243 | movwf current_state 244 | goto state_machine_loop 245 | 246 | ; Handle the case where a correct guess is made 247 | handle_correct_guesses: 248 | ; Sets the current state to the SOK state 249 | movlw state_SOK 250 | movwf current_state 251 | goto state_machine_loop 252 | 253 | ; Determine the next state of the state machine (when no inputs is selected): 254 | compute_next_state: 255 | ; If the current state is S1, move to S2 256 | movlw state_S1 257 | xorwf current_state, W 258 | btfsc STATUS, Z 259 | goto move_to_state_S2 260 | ; If the current state is S2, move to S3 261 | movlw state_S2 262 | xorwf current_state, W 263 | btfsc STATUS, Z 264 | goto move_to_state_S3 265 | ; If the current state is S3, move to S4 266 | movlw state_S3 267 | xorwf current_state, W 268 | btfsc STATUS, Z 269 | goto move_to_state_S4 270 | ; If the current state is S4, move to S1 271 | goto move_to_state_S1 272 | 273 | ; Sets the current state to state S1 274 | move_to_state_S1: 275 | movlw state_S1 276 | movwf current_state 277 | goto state_machine_loop 278 | 279 | ; Sets the current state to state S2 280 | move_to_state_S2: 281 | movlw state_S2 282 | movwf current_state 283 | goto state_machine_loop 284 | 285 | ; Sets the current state to state S3 286 | move_to_state_S3: 287 | movlw state_S3 288 | movwf current_state 289 | goto state_machine_loop 290 | 291 | ; Sets the current state to state S4 292 | move_to_state_S4: 293 | movlw state_S4 294 | movwf current_state 295 | goto state_machine_loop 296 | 297 | ; Calls delay loops for 1 second between every state 298 | ; Creating a delay of about 1 second: 299 | ; (Inspired by: Steven M. Garverick in his tbird.asm file) 300 | delay_one_second: 301 | ; Initialize outer loop counter to 32 302 | movlw d'32' 303 | movwf delay_outer_counter 304 | outer_delay_loop: 305 | ; Initialize inner loop counter to 256 306 | clrf delay_inner_counter 307 | inner_delay_loop: 308 | ; If (--delay_inner_counter != 0) loop to inner_delay_loop 309 | decfsz delay_inner_counter,F 310 | goto inner_delay_loop 311 | ; If (--delay_outer_counter != 0) loop to outer_delay_loop 312 | decfsz delay_outer_counter,F 313 | goto outer_delay_loop 314 | ; Go back to the subroutine that handles SOK and SERR states 315 | goto handle_SOK_SERR_states 316 | 317 | ; Directive 'end of program' 318 | END --------------------------------------------------------------------------------