├── tests ├── bram │ ├── .gitignore │ └── run-single.sh ├── fsm │ └── .gitignore ├── lut │ ├── .gitignore │ ├── map_not.v │ ├── map_and.v │ ├── map_or.v │ ├── map_xor.v │ ├── map_mux.v │ ├── run-test.sh │ └── check_map.ys ├── opt │ ├── .gitignore │ ├── opt_ff.ys │ ├── opt_lut_elim.ys │ ├── opt_lut_port.ys │ ├── run-test.sh │ ├── opt_lut.ys │ ├── opt_expr_cmp.ys │ ├── opt_lut.v │ ├── opt_lut_elim.il │ ├── opt_ff.v │ └── opt_lut_port.il ├── sat │ ├── .gitignore │ ├── sizebits.ys │ ├── initval.ys │ ├── asserts.ys │ ├── run-test.sh │ ├── counters.ys │ ├── splice.ys │ ├── splice.v │ ├── initval.v │ ├── expose_dff.ys │ ├── asserts.v │ ├── share.ys │ ├── share.v │ ├── asserts_seq.ys │ ├── counters.v │ └── expose_dff.v ├── share │ └── .gitignore ├── smv │ ├── .gitignore │ ├── run-test.sh │ └── run-single.sh ├── realmath │ └── .gitignore ├── techmap │ ├── .gitignore │ ├── run-test.sh │ ├── mem_simple_4x1_cells.v │ ├── mem_simple_4x1_uut.v │ ├── mem_simple_4x1_tb.v │ └── mem_simple_4x1_runtest.sh ├── tools │ ├── .gitignore │ └── autotest.mk ├── various │ ├── .gitignore │ ├── reg_wire_error.ys │ ├── constmsk_test.v │ ├── constmsk_test.ys │ ├── run-test.sh │ └── submod_extract.ys ├── hana │ ├── .gitignore │ ├── README │ ├── test_simulation_seq.v │ ├── run-test.sh │ ├── test_simulation_buffer.v │ ├── test_simulation_nor.v │ ├── test_simulation_xor.v │ ├── test_simulation_xnor.v │ ├── test_simulation_nand.v │ ├── test_simulation_inc.v │ └── test_simulation_or.v ├── simple │ ├── .gitignore │ ├── always01.v │ ├── always02.v │ ├── arraycells.v │ ├── undef_eqx_nex.v │ ├── arrays01.v │ ├── wreduce.v │ ├── forgen01.v │ ├── constpower.v │ ├── signedexpr.v │ ├── always03.v │ ├── specify.v │ ├── run-test.sh │ ├── carryadd.v │ ├── constmuldivmod.v │ ├── aes_kexp128.v │ ├── realexpr.v │ ├── forgen02.v │ ├── hierarchy.v │ ├── hierdefparam.v │ ├── repwhile.v │ └── usb_phy_tests.v ├── asicworld │ ├── .gitignore │ ├── README │ ├── code_tidbits_wire_example.v │ ├── code_hdl_models_encoder_4to2_gates.v │ ├── code_verilog_tutorial_bus_con.v │ ├── code_verilog_tutorial_tri_buf.v │ ├── code_verilog_tutorial_simple_if.v │ ├── code_verilog_tutorial_simple_function.v │ ├── code_verilog_tutorial_multiply.v │ ├── code_verilog_tutorial_mux_21.v │ ├── code_tidbits_reg_combo_example.v │ ├── code_verilog_tutorial_task_global.v │ ├── code_verilog_tutorial_if_else.v │ ├── code_verilog_tutorial_which_clock.v │ ├── code_tidbits_blocking.v │ ├── code_verilog_tutorial_always_example.v │ ├── code_tidbits_nonblocking.v │ ├── code_verilog_tutorial_d_ff.v │ ├── code_hdl_models_d_latch_gates.v │ ├── code_hdl_models_decoder_2to4_gates.v │ ├── code_verilog_tutorial_flip_flop.v │ ├── code_tidbits_reg_seq_example.v │ ├── code_verilog_tutorial_escape_id.v │ ├── code_tidbits_syn_reset.v │ ├── code_verilog_tutorial_n_out_primitive.v │ ├── run-test.sh │ ├── code_tidbits_asyn_reset.v │ ├── code_verilog_tutorial_good_code.v │ ├── code_hdl_models_half_adder_gates.v │ ├── code_verilog_tutorial_decoder.v │ ├── code_verilog_tutorial_comment.v │ ├── code_hdl_models_d_ff_gates.v │ ├── code_verilog_tutorial_decoder_always.v │ ├── code_verilog_tutorial_addbit.v │ ├── code_hdl_models_parity_using_bitwise.v │ ├── code_hdl_models_mux_2to1_gates.v │ ├── code_verilog_tutorial_parallel_if.v │ ├── code_hdl_models_full_adder_gates.v │ ├── code_verilog_tutorial_counter.v │ ├── code_verilog_tutorial_v2k_reg.v │ ├── code_verilog_tutorial_explicit.v │ ├── code_hdl_models_full_subtracter_gates.v │ ├── code_hdl_models_decoder_using_assign.v │ ├── code_hdl_models_parity_using_assign.v │ ├── code_hdl_models_mux_using_assign.v │ ├── code_hdl_models_tff_sync_reset.v │ ├── code_hdl_models_up_counter.v │ ├── code_hdl_models_dff_sync_reset.v │ └── code_hdl_models_tff_async_reset.v ├── memories │ ├── .gitignore │ ├── shared_ports.v │ ├── implicit_en.v │ ├── no_implicit_en.v │ └── simple_sram_byte_en.v ├── errors │ ├── syntax_err04.v │ ├── syntax_err05.v │ ├── syntax_err13.v │ ├── syntax_err01.v │ ├── syntax_err09.v │ ├── syntax_err10.v │ ├── syntax_err11.v │ ├── syntax_err06.v │ ├── syntax_err03.v │ ├── syntax_err07.v │ ├── syntax_err08.v │ ├── syntax_err02.v │ └── syntax_err12.v ├── svinterfaces │ ├── run-test.sh │ └── .gitignore ├── sva │ ├── .gitignore │ ├── sva_range.sv │ ├── sva_throughout.sv │ ├── basic04.sv │ ├── Makefile │ ├── basic03.sv │ ├── basic01.sv │ ├── basic05.sv │ ├── basic00.sv │ ├── basic04.vhd │ ├── basic02.sv │ ├── basic05.vhd │ └── sva_not.sv ├── vloghtb │ ├── .gitignore │ ├── test_share.sh │ ├── test_makefile │ ├── test_mapopt.sh │ ├── run-test.sh │ └── test_febe.sh └── unit │ └── kernel │ ├── logTest.cc │ └── rtlilTest.cc ├── techlibs ├── .gitignore ├── common │ ├── .gitignore │ ├── dff2ff.v │ ├── pmux2mux.v │ └── adff2dff.v ├── xilinx │ ├── .gitignore │ ├── tests │ │ ├── .gitignore │ │ ├── bram2.sh │ │ └── bram2.v │ └── drams.txt ├── easic │ └── Makefile.inc ├── ice40 │ ├── .gitignore │ ├── tests │ │ ├── test_arith.v │ │ ├── .gitignore │ │ ├── test_arith.ys │ │ ├── test_dsp_model.sh │ │ └── test_bram.v │ ├── latches_map.v │ ├── brams.txt │ └── brams_init.py ├── greenpak4 │ ├── cells_sim.v │ ├── cells_latch.v │ ├── cells_blackbox.v │ └── Makefile.inc ├── ecp5 │ ├── .gitignore │ ├── dram.txt │ ├── latches_map.v │ ├── bram.txt │ └── drams_map.v ├── achronix │ └── Makefile.inc ├── anlogic │ ├── drams.txt │ ├── drams_map.v │ └── Makefile.inc ├── gowin │ └── Makefile.inc ├── sf2 │ └── Makefile.inc ├── coolrunner2 │ ├── Makefile.inc │ ├── cells_latch.v │ └── tff_extract.v └── intel │ └── common │ └── brams.txt ├── backends ├── smt2 │ ├── .gitignore │ ├── example.ys │ └── example.v ├── firrtl │ ├── .gitignore │ ├── Makefile.inc │ └── test.sh ├── simplec │ ├── .gitignore │ ├── Makefile.inc │ ├── test00.sh │ └── test00_uut.v ├── protobuf │ ├── .gitignore │ └── Makefile.inc ├── smv │ ├── Makefile.inc │ └── test_cells.sh ├── aiger │ └── Makefile.inc ├── blif │ └── Makefile.inc ├── btor │ ├── Makefile.inc │ └── test_cells.sh ├── edif │ └── Makefile.inc ├── json │ └── Makefile.inc ├── spice │ └── Makefile.inc ├── table │ └── Makefile.inc ├── ilang │ └── Makefile.inc ├── intersynth │ └── Makefile.inc └── verilog │ └── Makefile.inc ├── passes ├── pmgen │ ├── .gitignore │ └── Makefile.inc ├── techmap │ ├── .gitignore │ └── filterlib.cc ├── tests │ ├── Makefile.inc │ └── flowmap │ │ ├── pack1p.v │ │ ├── pack1.v │ │ ├── pack3p.v │ │ ├── flowp.v │ │ ├── pack3.v │ │ ├── pack2p.v │ │ ├── pack2.v │ │ └── flow.v ├── hierarchy │ └── Makefile.inc ├── proc │ └── Makefile.inc ├── fsm │ └── Makefile.inc ├── sat │ ├── Makefile.inc │ └── example.ys ├── memory │ └── Makefile.inc ├── equiv │ └── Makefile.inc └── opt │ └── Makefile.inc ├── libs ├── subcircuit │ └── .gitignore ├── ezsat │ ├── .gitignore │ └── Makefile ├── bigint │ ├── .gitignore │ └── BigIntegerLibrary.hh └── minisat │ ├── 00_PATCH_typofixes.patch │ └── 00_UPDATE.sh ├── manual ├── PRESENTATION_ExAdv │ ├── .gitignore │ ├── mymul_test.v │ ├── red_or3x1_test.v │ ├── red_or3x1_cells.v │ ├── addshift_test.v │ ├── mulshift_test.v │ ├── macc_simple_test.v │ ├── macc_simple_xmap.v │ ├── sym_mul_test.v │ ├── addshift_test.ys │ ├── macc_simple_test_01.v │ ├── macc_simple_test_02.v │ ├── sym_mul_cells.v │ ├── sym_mul_test.ys │ ├── macc_xilinx_xmap.v │ ├── red_or3x1_test.ys │ ├── mulshift_test.ys │ ├── select.ys │ ├── macc_xilinx_test.v │ ├── select.v │ ├── mymul_map.v │ ├── mymul_test.ys │ ├── sym_mul_map.v │ ├── addshift_map.v │ ├── macc_xilinx_swap_map.v │ ├── Makefile │ └── mulshift_map.v ├── PRESENTATION_ExOth │ ├── .gitignore │ ├── axis_test.ys │ ├── scrambler.v │ ├── Makefile │ ├── scrambler.ys │ ├── equiv.ys │ └── axis_master.v ├── PRESENTATION_ExSyn │ ├── .gitignore │ ├── opt_01.ys │ ├── opt_02.ys │ ├── opt_03.ys │ ├── opt_04.ys │ ├── proc_01.ys │ ├── proc_02.ys │ ├── proc_03.ys │ ├── memory_01.ys │ ├── opt_02.v │ ├── opt_01.v │ ├── techmap_01.ys │ ├── techmap_01.v │ ├── memory_02.ys │ ├── opt_03.v │ ├── abc_01.ys │ ├── proc_01.v │ ├── proc_02.v │ ├── proc_03.v │ ├── abc_01.v │ ├── memory_01.v │ ├── opt_04.v │ ├── Makefile │ ├── techmap_01_map.v │ ├── abc_01_cells.v │ └── memory_02.v ├── PRESENTATION_Prog │ ├── .gitignore │ ├── sigmap_test.v │ ├── absval_ref.v │ └── Makefile ├── CHAPTER_Eval │ ├── or1200_ys.prj │ ├── openmsp430_ys.prj │ └── settings.xst ├── CHAPTER_Prog │ ├── .gitignore │ ├── test.v │ └── Makefile ├── PRESENTATION_Intro │ ├── .gitignore │ ├── counter.v │ ├── Makefile │ ├── mycells.v │ └── counter.ys ├── APPNOTE_011_Design_Investigation │ ├── cmos.v │ ├── primetest.v │ ├── sumprod_02.dot │ ├── example.v │ ├── sumprod.v │ ├── example.ys │ ├── splice.v │ ├── foobaraddsub.v │ ├── example_03.dot │ ├── memdemo.v │ ├── sumprod_03.dot │ ├── sumprod_04.dot │ ├── submod.ys │ ├── sumprod_05.dot │ ├── sumprod_00.dot │ └── sumprod_01.dot ├── .gitignore ├── clean.sh ├── CHAPTER_StateOfTheArt │ ├── always01_pub.v │ ├── always02_pub.v │ ├── always01.v │ ├── always02.v │ ├── arrays01.v │ ├── forgen01.v │ ├── always03.v │ ├── forgen02.v │ └── iverilog-0.8.7-buildfixes.patch └── appnotes.sh ├── examples ├── osu035 │ ├── example.constr │ ├── .gitignore │ ├── example.v │ ├── example.ys │ └── Makefile ├── cmos │ ├── .gitignore │ ├── testbench.sh │ ├── counter_tb.gtkw │ ├── counter.v │ ├── testbench_digital.sh │ ├── counter.ys │ ├── counter_digital.ys │ ├── README │ ├── cmos_cells_digital.sp │ ├── testbench_digital.sp │ ├── counter_tb.v │ ├── testbench.sp │ ├── cmos_cells.v │ └── cmos_cells.sp ├── igloo2 │ ├── .gitignore │ ├── example.sdc │ └── runme.sh ├── aiger │ ├── .gitignore │ ├── demo.sh │ └── demo.v ├── gowin │ ├── demo.sdc │ ├── .gitignore │ ├── demo.v │ ├── run.sh │ ├── README │ └── testbench.v ├── anlogic │ ├── build.sh │ ├── demo.ys │ ├── .gitignore │ ├── demo.adc │ ├── build.tcl │ ├── README │ └── demo.v ├── basys3 │ ├── run_yosys.ys │ ├── run.sh │ ├── run_prog.tcl │ ├── run_vivado.tcl │ ├── README │ └── example.v ├── smtbmc │ ├── demo3.smtc │ ├── demo4.smtc │ ├── demo6.v │ ├── demo8.v │ ├── demo4.v │ ├── .gitignore │ ├── demo5.v │ ├── demo7.v │ ├── demo1.v │ ├── demo3.v │ └── demo2.v ├── intel │ ├── MAX10 │ │ ├── run_max10 │ │ ├── runme_postsynth │ │ ├── top.v │ │ └── sevenseg.v │ ├── DE2i-150 │ │ ├── quartus_compile │ │ │ ├── de2i.qpf │ │ │ └── runme_quartus │ │ ├── run_cycloneiv │ │ ├── top.v │ │ └── sevenseg.v │ └── asicworld_lfsr │ │ ├── run_max10 │ │ ├── runme_presynth │ │ ├── run_cycloneiv │ │ ├── runme_postsynth │ │ ├── README │ │ └── lfsr_updown_tb.v └── cxx-api │ └── demomain.cc ├── frontends ├── blif │ └── Makefile.inc ├── json │ └── Makefile.inc ├── liberty │ └── Makefile.inc ├── ilang │ ├── .gitignore │ └── Makefile.inc ├── verilog │ └── .gitignore ├── ast │ └── Makefile.inc └── verific │ ├── example.sby │ ├── example.sv │ └── Makefile.inc ├── .travis ├── deploy-after-success.sh └── common.sh ├── Brewfile ├── .editorconfig ├── .github └── issue_template.md ├── .gitignore └── COPYING /tests/bram/.gitignore: -------------------------------------------------------------------------------- 1 | temp 2 | -------------------------------------------------------------------------------- /tests/fsm/.gitignore: -------------------------------------------------------------------------------- 1 | temp 2 | -------------------------------------------------------------------------------- /tests/lut/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | -------------------------------------------------------------------------------- /tests/opt/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | -------------------------------------------------------------------------------- /tests/sat/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | -------------------------------------------------------------------------------- /tests/share/.gitignore: -------------------------------------------------------------------------------- 1 | temp 2 | -------------------------------------------------------------------------------- /tests/smv/.gitignore: -------------------------------------------------------------------------------- 1 | temp 2 | -------------------------------------------------------------------------------- /techlibs/.gitignore: -------------------------------------------------------------------------------- 1 | blackbox.v 2 | -------------------------------------------------------------------------------- /tests/realmath/.gitignore: -------------------------------------------------------------------------------- 1 | temp 2 | -------------------------------------------------------------------------------- /tests/techmap/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | -------------------------------------------------------------------------------- /tests/tools/.gitignore: -------------------------------------------------------------------------------- 1 | cmp_tbdata 2 | -------------------------------------------------------------------------------- /tests/various/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | -------------------------------------------------------------------------------- /backends/smt2/.gitignore: -------------------------------------------------------------------------------- 1 | test_cells 2 | -------------------------------------------------------------------------------- /passes/pmgen/.gitignore: -------------------------------------------------------------------------------- 1 | /ice40_dsp_pm.h 2 | -------------------------------------------------------------------------------- /passes/techmap/.gitignore: -------------------------------------------------------------------------------- 1 | techmap.inc 2 | -------------------------------------------------------------------------------- /tests/hana/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.out 3 | -------------------------------------------------------------------------------- /tests/simple/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.out 3 | -------------------------------------------------------------------------------- /libs/subcircuit/.gitignore: -------------------------------------------------------------------------------- 1 | demo 2 | scshell 3 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/.gitignore: -------------------------------------------------------------------------------- 1 | *.dot 2 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/.gitignore: -------------------------------------------------------------------------------- 1 | *.dot 2 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/.gitignore: -------------------------------------------------------------------------------- 1 | *.dot 2 | -------------------------------------------------------------------------------- /tests/asicworld/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.out 3 | -------------------------------------------------------------------------------- /backends/firrtl/.gitignore: -------------------------------------------------------------------------------- 1 | test.fir 2 | test_out.v 3 | -------------------------------------------------------------------------------- /backends/simplec/.gitignore: -------------------------------------------------------------------------------- 1 | test00_tb 2 | test00_uut.c 3 | -------------------------------------------------------------------------------- /tests/memories/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.out 3 | *.dmp 4 | -------------------------------------------------------------------------------- /backends/protobuf/.gitignore: -------------------------------------------------------------------------------- 1 | yosys.pb.cc 2 | yosys.pb.h 3 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Prog/.gitignore: -------------------------------------------------------------------------------- 1 | my_cmd.so 2 | my_cmd.d 3 | -------------------------------------------------------------------------------- /backends/smv/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/smv/smv.o 3 | 4 | -------------------------------------------------------------------------------- /manual/CHAPTER_Eval/or1200_ys.prj: -------------------------------------------------------------------------------- 1 | verilog work "or1200_ys.v" 2 | -------------------------------------------------------------------------------- /techlibs/common/.gitignore: -------------------------------------------------------------------------------- 1 | simlib_help.inc 2 | simcells_help.inc 3 | -------------------------------------------------------------------------------- /techlibs/xilinx/.gitignore: -------------------------------------------------------------------------------- 1 | brams_init.mk 2 | brams_init_*.vh 3 | -------------------------------------------------------------------------------- /backends/aiger/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/aiger/aiger.o 3 | 4 | -------------------------------------------------------------------------------- /backends/blif/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/blif/blif.o 3 | 4 | -------------------------------------------------------------------------------- /backends/btor/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/btor/btor.o 3 | 4 | -------------------------------------------------------------------------------- /backends/edif/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/edif/edif.o 3 | 4 | -------------------------------------------------------------------------------- /backends/json/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/json/json.o 3 | 4 | -------------------------------------------------------------------------------- /backends/spice/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/spice/spice.o 3 | 4 | -------------------------------------------------------------------------------- /backends/table/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/table/table.o 3 | 4 | -------------------------------------------------------------------------------- /manual/CHAPTER_Eval/openmsp430_ys.prj: -------------------------------------------------------------------------------- 1 | verilog work "openmsp430_ys.v" 2 | -------------------------------------------------------------------------------- /manual/CHAPTER_Prog/.gitignore: -------------------------------------------------------------------------------- 1 | stubnets.so 2 | stubnets.d 3 | *.log 4 | -------------------------------------------------------------------------------- /tests/various/reg_wire_error.ys: -------------------------------------------------------------------------------- 1 | read_verilog -sv reg_wire_error.sv 2 | -------------------------------------------------------------------------------- /backends/firrtl/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/firrtl/firrtl.o 3 | 4 | -------------------------------------------------------------------------------- /backends/simplec/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/simplec/simplec.o 3 | 4 | -------------------------------------------------------------------------------- /examples/osu035/example.constr: -------------------------------------------------------------------------------- 1 | set_driving_cell INVX1 2 | set_load 0.015 3 | -------------------------------------------------------------------------------- /frontends/blif/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += frontends/blif/blifparse.o 3 | 4 | -------------------------------------------------------------------------------- /frontends/json/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += frontends/json/jsonparse.o 3 | 4 | -------------------------------------------------------------------------------- /techlibs/easic/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/easic/synth_easic.o 3 | 4 | -------------------------------------------------------------------------------- /tests/errors/syntax_err04.v: -------------------------------------------------------------------------------- 1 | module a; 2 | wire [3]x; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /tests/errors/syntax_err05.v: -------------------------------------------------------------------------------- 1 | module a; 2 | input x[2:0]; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /tests/errors/syntax_err13.v: -------------------------------------------------------------------------------- 1 | module a #(p = 0) 2 | (); 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /tests/opt/opt_ff.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_ff.v 2 | synth_ice40 3 | ice40_unlut 4 | -------------------------------------------------------------------------------- /backends/ilang/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/ilang/ilang_backend.o 3 | 4 | -------------------------------------------------------------------------------- /examples/cmos/.gitignore: -------------------------------------------------------------------------------- 1 | counter_tb 2 | counter_tb.vcd 3 | synth.sp 4 | synth.v 5 | -------------------------------------------------------------------------------- /frontends/liberty/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += frontends/liberty/liberty.o 3 | 4 | -------------------------------------------------------------------------------- /tests/errors/syntax_err01.v: -------------------------------------------------------------------------------- 1 | module a; 2 | integer [31:0]w; 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /tests/errors/syntax_err09.v: -------------------------------------------------------------------------------- 1 | module a(input wire x = 1'b0); 2 | endmodule 3 | 4 | -------------------------------------------------------------------------------- /backends/intersynth/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/intersynth/intersynth.o 3 | 4 | -------------------------------------------------------------------------------- /backends/verilog/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += backends/verilog/verilog_backend.o 3 | 4 | -------------------------------------------------------------------------------- /examples/igloo2/.gitignore: -------------------------------------------------------------------------------- 1 | /netlist.edn 2 | /netlist.vm 3 | /example.stp 4 | /proj 5 | -------------------------------------------------------------------------------- /examples/osu035/.gitignore: -------------------------------------------------------------------------------- 1 | osu035_stdcells.lib 2 | example.yslog 3 | example.edif 4 | -------------------------------------------------------------------------------- /libs/ezsat/.gitignore: -------------------------------------------------------------------------------- 1 | demo_bit 2 | demo_cmp 3 | demo_vec 4 | puzzle3d 5 | testbench 6 | -------------------------------------------------------------------------------- /passes/techmap/filterlib.cc: -------------------------------------------------------------------------------- 1 | 2 | #define FILTERLIB 3 | #include "libparse.cc" 4 | 5 | -------------------------------------------------------------------------------- /tests/asicworld/README: -------------------------------------------------------------------------------- 1 | Borrowed Verilog examples from http://www.asic-world.com/. 2 | -------------------------------------------------------------------------------- /tests/errors/syntax_err10.v: -------------------------------------------------------------------------------- 1 | module a; 2 | parameter integer [2:0]x=0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/errors/syntax_err11.v: -------------------------------------------------------------------------------- 1 | module a; 2 | parameter integer real x=0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /examples/aiger/.gitignore: -------------------------------------------------------------------------------- 1 | demo.aig 2 | demo.aim 3 | demo.aiw 4 | demo.smt2 5 | demo.vcd 6 | -------------------------------------------------------------------------------- /tests/sat/sizebits.ys: -------------------------------------------------------------------------------- 1 | read_verilog -sv sizebits.sv 2 | prep; sat -verify -prove-asserts 3 | -------------------------------------------------------------------------------- /examples/gowin/demo.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] 2 | -------------------------------------------------------------------------------- /tests/sat/initval.ys: -------------------------------------------------------------------------------- 1 | read_verilog -sv initval.v 2 | proc;; 3 | 4 | sat -seq 10 -prove-asserts 5 | -------------------------------------------------------------------------------- /examples/anlogic/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | yosys demo.ys 4 | $TD_HOME/bin/td build.tcl 5 | -------------------------------------------------------------------------------- /examples/anlogic/demo.ys: -------------------------------------------------------------------------------- 1 | read_verilog demo.v 2 | synth_anlogic -top demo 3 | write_verilog full.v 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_01.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_01.v 2 | hierarchy -check -top test 3 | opt 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_02.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_02.v 2 | hierarchy -check -top test 3 | opt 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_03.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_03.v 2 | hierarchy -check -top test 3 | opt 4 | -------------------------------------------------------------------------------- /techlibs/ice40/.gitignore: -------------------------------------------------------------------------------- 1 | brams_init.mk 2 | brams_init1.vh 3 | brams_init2.vh 4 | brams_init3.vh 5 | -------------------------------------------------------------------------------- /tests/opt/opt_lut_elim.ys: -------------------------------------------------------------------------------- 1 | read_ilang opt_lut_elim.il 2 | opt_lut 3 | select -assert-count 0 t:$lut 4 | -------------------------------------------------------------------------------- /tests/opt/opt_lut_port.ys: -------------------------------------------------------------------------------- 1 | read_ilang opt_lut_port.il 2 | opt_lut 3 | select -assert-count 2 t:$lut 4 | -------------------------------------------------------------------------------- /examples/anlogic/.gitignore: -------------------------------------------------------------------------------- 1 | demo.bit 2 | demo_phy.area 3 | full.v 4 | *.log 5 | *.h 6 | *.tde 7 | *.svf 8 | -------------------------------------------------------------------------------- /examples/basys3/run_yosys.ys: -------------------------------------------------------------------------------- 1 | read_verilog example.v 2 | synth_xilinx -edif example.edif -top example 3 | -------------------------------------------------------------------------------- /examples/smtbmc/demo3.smtc: -------------------------------------------------------------------------------- 1 | initial 2 | assume [rst] 3 | 4 | always -1 5 | assert (= [-1:mem] [mem]) 6 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_04.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_04.v 2 | hierarchy -check -top test 3 | proc; opt 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/proc_01.ys: -------------------------------------------------------------------------------- 1 | read_verilog proc_01.v 2 | hierarchy -check -top test 3 | proc;; 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/proc_02.ys: -------------------------------------------------------------------------------- 1 | read_verilog proc_02.v 2 | hierarchy -check -top test 3 | proc;; 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/proc_03.ys: -------------------------------------------------------------------------------- 1 | read_verilog proc_03.v 2 | hierarchy -check -top test 3 | proc;; 4 | -------------------------------------------------------------------------------- /tests/errors/syntax_err06.v: -------------------------------------------------------------------------------- 1 | module a; 2 | initial 3 | begin : label1 4 | end: label2 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /examples/intel/MAX10/run_max10: -------------------------------------------------------------------------------- 1 | yosys -p "synth_intel -family max10 -top top -vqm top.vqm" top.v sevenseg.v 2 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Intro/.gitignore: -------------------------------------------------------------------------------- 1 | counter_00.dot 2 | counter_01.dot 3 | counter_02.dot 4 | counter_03.dot 5 | -------------------------------------------------------------------------------- /tests/errors/syntax_err03.v: -------------------------------------------------------------------------------- 1 | module a; 2 | task to ( 3 | input [3]x 4 | ); 5 | endtask 6 | endmodule 7 | 8 | -------------------------------------------------------------------------------- /tests/lut/map_not.v: -------------------------------------------------------------------------------- 1 | module top(...); 2 | input a; 3 | output y; 4 | assign y = ~a; 5 | endmodule 6 | -------------------------------------------------------------------------------- /frontends/ilang/.gitignore: -------------------------------------------------------------------------------- 1 | ilang_lexer.cc 2 | ilang_parser.output 3 | ilang_parser.tab.cc 4 | ilang_parser.tab.hh 5 | -------------------------------------------------------------------------------- /libs/bigint/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | sample 3 | testsuite 4 | testsuite.expected 5 | testsuite.out 6 | testsuite.err 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Prog/sigmap_test.v: -------------------------------------------------------------------------------- 1 | module test(input a, output x, y); 2 | assign x = a, y = a; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/errors/syntax_err07.v: -------------------------------------------------------------------------------- 1 | module a; 2 | wire [5:0]x; 3 | wire [3:0]y; 4 | assign y = (4)55; 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /tests/errors/syntax_err08.v: -------------------------------------------------------------------------------- 1 | module a; 2 | wire [5:0]x; 3 | wire [3:0]y; 4 | assign y = x 55; 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /tests/lut/map_and.v: -------------------------------------------------------------------------------- 1 | module top(...); 2 | input a, b; 3 | output y; 4 | assign y = a&b; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/lut/map_or.v: -------------------------------------------------------------------------------- 1 | module top(...); 2 | input a, b; 3 | output y; 4 | assign y = a|b; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/lut/map_xor.v: -------------------------------------------------------------------------------- 1 | module top(...); 2 | input a, b; 3 | output y; 4 | assign y = a^b; 5 | endmodule 6 | -------------------------------------------------------------------------------- /examples/cmos/testbench.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | ../../yosys counter.ys 6 | ngspice testbench.sp 7 | 8 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/memory_01.ys: -------------------------------------------------------------------------------- 1 | read_verilog memory_01.v 2 | hierarchy -check -top test 3 | proc;; memory; opt 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_02.v: -------------------------------------------------------------------------------- 1 | module test(input A, output Y, Z); 2 | assign Y = A == A, Z = A != A; 3 | endmodule 4 | -------------------------------------------------------------------------------- /techlibs/xilinx/tests/.gitignore: -------------------------------------------------------------------------------- 1 | bram1_cmp 2 | bram1.mk 3 | bram1_[0-9]*/ 4 | bram2.log 5 | bram2_syn.v 6 | bram2_tb 7 | -------------------------------------------------------------------------------- /tests/errors/syntax_err02.v: -------------------------------------------------------------------------------- 1 | module a; 2 | task to ( 3 | input integer [3:0]x 4 | ); 5 | endtask 6 | endmodule 7 | 8 | -------------------------------------------------------------------------------- /tests/lut/map_mux.v: -------------------------------------------------------------------------------- 1 | module top(...); 2 | input a, b, s; 3 | output y; 4 | assign y = s?a:b; 5 | endmodule 6 | -------------------------------------------------------------------------------- /examples/intel/DE2i-150/quartus_compile/de2i.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "16.1" 2 | # Revisions 3 | 4 | PROJECT_REVISION = "de2i" 5 | -------------------------------------------------------------------------------- /frontends/verilog/.gitignore: -------------------------------------------------------------------------------- 1 | verilog_lexer.cc 2 | verilog_parser.output 3 | verilog_parser.tab.cc 4 | verilog_parser.tab.hh 5 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_01.v: -------------------------------------------------------------------------------- 1 | module test(input A, B, output Y); 2 | assign Y = A ? A ? B : 1'b1 : B; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/errors/syntax_err12.v: -------------------------------------------------------------------------------- 1 | interface iface; 2 | endinterface 3 | 4 | module a ( 5 | iface x = 1'b0 6 | ); 7 | endmodule 8 | -------------------------------------------------------------------------------- /tests/hana/README: -------------------------------------------------------------------------------- 1 | 2 | These test cases are copied from the hana project: 3 | https://sourceforge.net/projects/sim-sim/ 4 | 5 | -------------------------------------------------------------------------------- /.travis/deploy-after-success.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | set -x 4 | set -e 5 | 6 | # FIXME: Upload the build results somewhere... 7 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/cmos.v: -------------------------------------------------------------------------------- 1 | module cmos_demo(input a, b, output [1:0] y); 2 | assign y = a + b; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/svinterfaces/run-test.sh: -------------------------------------------------------------------------------- 1 | #/bin/bash -e 2 | 3 | 4 | 5 | ./runone.sh svinterface1 6 | ./runone.sh svinterface_at_top 7 | -------------------------------------------------------------------------------- /examples/igloo2/example.sdc: -------------------------------------------------------------------------------- 1 | # Add timing constraints here 2 | create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] 3 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/mymul_test.v: -------------------------------------------------------------------------------- 1 | module test(A, B, Y); 2 | input [1:0] A, B; 3 | output [1:0] Y = A * B; 4 | endmodule 5 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/techmap_01.ys: -------------------------------------------------------------------------------- 1 | read_verilog techmap_01.v 2 | hierarchy -check -top test 3 | techmap -map techmap_01_map.v;; 4 | -------------------------------------------------------------------------------- /tests/sva/.gitignore: -------------------------------------------------------------------------------- 1 | /*_pass.sby 2 | /*_fail.sby 3 | /*_pass 4 | /*_fail 5 | /*.ok 6 | /vhdlpsl[0-9][0-9] 7 | /vhdlpsl[0-9][0-9].sby 8 | -------------------------------------------------------------------------------- /examples/gowin/.gitignore: -------------------------------------------------------------------------------- 1 | demo.bit 2 | demo.out 3 | demo.rpt 4 | demo_syn.v 5 | demo_out.v 6 | demo_tr.html 7 | testbench 8 | testbench.vcd 9 | -------------------------------------------------------------------------------- /examples/intel/DE2i-150/run_cycloneiv: -------------------------------------------------------------------------------- 1 | #/bin/env bash 2 | yosys -p "synth_intel -family cycloneiv -top top -vqm top.vqm" top.v sevenseg.v 3 | -------------------------------------------------------------------------------- /tests/opt/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | for x in *.ys; do 4 | echo "Running $x.." 5 | ../../yosys -ql ${x%.ys}.log $x 6 | done 7 | -------------------------------------------------------------------------------- /tests/sat/asserts.ys: -------------------------------------------------------------------------------- 1 | read_verilog -sv asserts.v 2 | hierarchy; proc; opt 3 | sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts 4 | -------------------------------------------------------------------------------- /tests/sat/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | for x in *.ys; do 4 | echo "Running $x.." 5 | ../../yosys -ql ${x%.ys}.log $x 6 | done 7 | -------------------------------------------------------------------------------- /examples/anlogic/demo.adc: -------------------------------------------------------------------------------- 1 | set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ 2 | set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED 3 | -------------------------------------------------------------------------------- /examples/cmos/counter_tb.gtkw: -------------------------------------------------------------------------------- 1 | [dumpfile] "counter_tb.vcd" 2 | counter_tb.clk 3 | counter_tb.count[2:0] 4 | counter_tb.en 5 | counter_tb.reset 6 | -------------------------------------------------------------------------------- /examples/intel/asicworld_lfsr/run_max10: -------------------------------------------------------------------------------- 1 | #!/bin/env bash 2 | yosys -p "synth_intel -family max10 -top lfsr_updown -vqm top.vqm" lfsr_updown.v 3 | -------------------------------------------------------------------------------- /examples/intel/asicworld_lfsr/runme_presynth: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\ 4 | 5 | vvp -N presynth -------------------------------------------------------------------------------- /examples/osu035/example.v: -------------------------------------------------------------------------------- 1 | module top (input clk, input [7:0] a, b, output reg [15:0] c); 2 | always @(posedge clk) c <= a * b; 3 | endmodule 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/red_or3x1_test.v: -------------------------------------------------------------------------------- 1 | module test (A, Y); 2 | input [6:0] A; 3 | output Y; 4 | assign Y = |A; 5 | endmodule 6 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/techmap_01.v: -------------------------------------------------------------------------------- 1 | module test(input [31:0] a, b, 2 | output [31:0] y); 3 | assign y = a + b; 4 | endmodule 5 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Prog/absval_ref.v: -------------------------------------------------------------------------------- 1 | module absval_ref(input signed [3:0] a, output [3:0] y); 2 | assign y = a[3] ? -a : a; 3 | endmodule 4 | -------------------------------------------------------------------------------- /Brewfile: -------------------------------------------------------------------------------- 1 | brew "bison" 2 | brew "flex" 3 | brew "gawk" 4 | brew "libffi" 5 | brew "git" 6 | brew "graphviz" 7 | brew "pkg-config" 8 | brew "python3" 9 | -------------------------------------------------------------------------------- /examples/intel/asicworld_lfsr/run_cycloneiv: -------------------------------------------------------------------------------- 1 | #!/bin/env bash 2 | yosys -p "synth_intel -family cycloneiv -top lfsr_updown -vqm top.vqm" lfsr_updown.v 3 | -------------------------------------------------------------------------------- /manual/.gitignore: -------------------------------------------------------------------------------- 1 | *.aux 2 | *.bbl 3 | *.blg 4 | *.idx 5 | *.log 6 | *.out 7 | *.pdf 8 | *.toc 9 | *.snm 10 | *.nav 11 | *.vrb 12 | *.ok 13 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/memory_02.ys: -------------------------------------------------------------------------------- 1 | read_verilog memory_02.v 2 | hierarchy -check -top test 3 | proc;; memory -nomap 4 | opt -mux_undef -mux_bool 5 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_03.v: -------------------------------------------------------------------------------- 1 | module test(input [3:0] A, B, 2 | output [3:0] Y, Z); 3 | assign Y = A + B, Z = B + A; 4 | endmodule 5 | -------------------------------------------------------------------------------- /passes/tests/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/tests/test_autotb.o 3 | OBJS += passes/tests/test_cell.o 4 | OBJS += passes/tests/test_abcloop.o 5 | 6 | -------------------------------------------------------------------------------- /tests/vloghtb/.gitignore: -------------------------------------------------------------------------------- 1 | Makefile 2 | refdat 3 | rtl 4 | scripts 5 | spec 6 | check_yosys 7 | vloghammer_tb.tar.bz2 8 | temp 9 | log_test_* 10 | -------------------------------------------------------------------------------- /.editorconfig: -------------------------------------------------------------------------------- 1 | root = true 2 | 3 | [*] 4 | indent_style = tab 5 | indent_size = tab 6 | trim_trailing_whitespace = true 7 | insert_final_newline = true 8 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/red_or3x1_cells.v: -------------------------------------------------------------------------------- 1 | module OR3X1(A, B, C, Y); 2 | input A, B, C; 3 | output Y; 4 | assign Y = A | B | C; 5 | endmodule 6 | -------------------------------------------------------------------------------- /passes/hierarchy/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/hierarchy/hierarchy.o 3 | OBJS += passes/hierarchy/uniquify.o 4 | OBJS += passes/hierarchy/submod.o 5 | 6 | -------------------------------------------------------------------------------- /techlibs/greenpak4/cells_sim.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | `include "cells_sim_ams.v" 4 | `include "cells_sim_digital.v" 5 | `include "cells_sim_wip.v" 6 | -------------------------------------------------------------------------------- /backends/smt2/example.ys: -------------------------------------------------------------------------------- 1 | read_verilog -formal example.v 2 | hierarchy; proc; opt; memory -nordff -nomap; opt -fast 3 | write_smt2 -bv -mem -wires example.smt2 4 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/addshift_test.v: -------------------------------------------------------------------------------- 1 | module test (A, B, X, Y); 2 | input [7:0] A, B; 3 | output [7:0] X = A + B; 4 | output [7:0] Y = A + A; 5 | endmodule 6 | -------------------------------------------------------------------------------- /manual/clean.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | for f in $( find . -name .gitignore ); do sed -Ee "s,^,find ${f%.gitignore} -name ',; s,$,' | xargs rm -f,;" $f; done | bash -v 3 | -------------------------------------------------------------------------------- /techlibs/ice40/tests/test_arith.v: -------------------------------------------------------------------------------- 1 | module test(input [4:0] a, b, c, output [4:0] y); 2 | assign y = ((a+b) ^ (a-c)) - ((a*b) + (a*c) - (b*c)); 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/lut/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | for x in *.v; do 4 | echo "Running $x.." 5 | ../../yosys -q -s check_map.ys -l ${x%.v}.log $x 6 | done 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/mulshift_test.v: -------------------------------------------------------------------------------- 1 | module test (A, X, Y); 2 | input [7:0] A; 3 | output [7:0] X = A * 8'd 6; 4 | output [7:0] Y = A * 8'd 8; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/opt/opt_lut.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_lut.v 2 | synth_ice40 3 | ice40_unlut 4 | equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 5 | -------------------------------------------------------------------------------- /tests/svinterfaces/.gitignore: -------------------------------------------------------------------------------- 1 | /a.out 2 | /dut_result.txt 3 | /reference_result.txt 4 | /*.diff 5 | /*.log_stderr 6 | /*.log_stdout 7 | /*_ref_syn.v 8 | /*_syn.v 9 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/primetest.v: -------------------------------------------------------------------------------- 1 | module primetest(p, a, b, ok); 2 | input [15:0] p, a, b; 3 | output ok = p != a*b || a == 1 || b == 1; 4 | endmodule 5 | -------------------------------------------------------------------------------- /tests/opt/opt_expr_cmp.ys: -------------------------------------------------------------------------------- 1 | read_verilog opt_expr_cmp.v 2 | equiv_opt -assert opt_expr -fine 3 | design -load postopt 4 | select -assert-count 0 t:$gt t:$ge t:$lt t:$le 5 | -------------------------------------------------------------------------------- /frontends/ast/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += frontends/ast/ast.o 3 | OBJS += frontends/ast/simplify.o 4 | OBJS += frontends/ast/genrtlil.o 5 | OBJS += frontends/ast/dpicall.o 6 | 7 | -------------------------------------------------------------------------------- /tests/various/constmsk_test.v: -------------------------------------------------------------------------------- 1 | module test(input [3:0] A, output [3:0] Y1, Y2); 2 | assign Y1 = |{A[3], 1'b0, A[1]}; 3 | assign Y2 = |{A[2], 1'b1, A[0]}; 4 | endmodule 5 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/axis_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog -sv axis_master.v axis_test.v 2 | hierarchy -top axis_test 3 | 4 | proc; flatten;; 5 | sat -falsify -seq 50 -prove-asserts 6 | -------------------------------------------------------------------------------- /examples/basys3/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | yosys run_yosys.ys 3 | vivado -nolog -nojournal -mode batch -source run_vivado.tcl 4 | vivado -nolog -nojournal -mode batch -source run_prog.tcl 5 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_simple_test.v: -------------------------------------------------------------------------------- 1 | module test(a, b, c, d, y); 2 | input [15:0] a, b; 3 | input [31:0] c, d; 4 | output [31:0] y; 5 | assign y = a * b + c + d; 6 | endmodule 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_simple_xmap.v: -------------------------------------------------------------------------------- 1 | module macc_16_16_32(a, b, c, y); 2 | input [15:0] a, b; 3 | input [31:0] c; 4 | output [31:0] y; 5 | assign y = a*b + c; 6 | endmodule 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/sym_mul_test.v: -------------------------------------------------------------------------------- 1 | module test(A, B, C, Y1, Y2); 2 | input [7:0] A, B, C; 3 | output [7:0] Y1 = A * B; 4 | output [15:0] Y2 = A * C; 5 | endmodule 6 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/abc_01.ys: -------------------------------------------------------------------------------- 1 | read_verilog abc_01.v 2 | read_verilog -lib abc_01_cells.v 3 | hierarchy -check -top test 4 | proc; opt; techmap 5 | abc -dff -liberty abc_01_cells.lib;; 6 | -------------------------------------------------------------------------------- /backends/simplec/test00.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | ../../yosys -p 'synth -top test; write_simplec -verbose -i8 test00_uut.c' test00_uut.v 4 | clang -o test00_tb test00_tb.c 5 | ./test00_tb 6 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/sumprod_02.dot: -------------------------------------------------------------------------------- 1 | digraph "sumprod" { 2 | rankdir="LR"; 3 | remincross=true; 4 | n1 [ shape=octagon, label="prod", color="black", fontcolor="black" ]; 5 | } 6 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/addshift_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog addshift_test.v 2 | hierarchy -check -top test 3 | 4 | techmap -map addshift_map.v;; 5 | 6 | show -prefix addshift -format pdf -notitle 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_simple_test_01.v: -------------------------------------------------------------------------------- 1 | module test(a, b, c, d, x, y); 2 | input [15:0] a, b, c, d; 3 | input [31:0] x; 4 | output [31:0] y; 5 | assign y = a*b + c*d + x; 6 | endmodule 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_simple_test_02.v: -------------------------------------------------------------------------------- 1 | module test(a, b, c, d, x, y); 2 | input [15:0] a, b, c, d; 3 | input [31:0] x; 4 | output [31:0] y; 5 | assign y = a*b + (c*d + x); 6 | endmodule 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/proc_01.v: -------------------------------------------------------------------------------- 1 | module test(input D, C, R, output reg Q); 2 | always @(posedge C, posedge R) 3 | if (R) 4 | Q <= 0; 5 | else 6 | Q <= D; 7 | endmodule 8 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_wire_example.v: -------------------------------------------------------------------------------- 1 | module wire_example( a, b, y); 2 | input a, b; 3 | output y; 4 | 5 | wire a, b, y; 6 | 7 | assign y = a & b; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /manual/CHAPTER_Prog/test.v: -------------------------------------------------------------------------------- 1 | module uut(in1, in2, in3, out1, out2); 2 | 3 | input [8:0] in1, in2, in3; 4 | output [8:0] out1, out2; 5 | 6 | assign out1 = in1 + in2 + (in3 >> 4); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/sym_mul_cells.v: -------------------------------------------------------------------------------- 1 | module MYMUL(A, B, Y); 2 | parameter WIDTH = 1; 3 | input [WIDTH-1:0] A, B; 4 | output [WIDTH-1:0] Y; 5 | assign Y = A * B; 6 | endmodule 7 | -------------------------------------------------------------------------------- /examples/intel/DE2i-150/quartus_compile/runme_quartus: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export REV="de2i" 4 | 5 | quartus_map -c $REV top && \ 6 | quartus_fit -c $REV top && \ 7 | quartus_asm -c $REV top 8 | -------------------------------------------------------------------------------- /manual/CHAPTER_Eval/settings.xst: -------------------------------------------------------------------------------- 1 | run -ifn @prj_file@ -ofn @out_file@ -ofmt NGC -top @top_module@ -p artix7 2 | -use_dsp48 NO -iobuf NO -ram_extract NO -rom_extract NO -fsm_extract YES -fsm_encoding Auto 3 | -------------------------------------------------------------------------------- /examples/intel/MAX10/runme_postsynth: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) 4 | vvp -N verif_post 5 | 6 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/sym_mul_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog sym_mul_test.v 2 | hierarchy -check -top test 3 | 4 | techmap -map sym_mul_map.v;; 5 | 6 | show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/proc_02.v: -------------------------------------------------------------------------------- 1 | module test(input D, C, R, RV, 2 | output reg Q); 3 | always @(posedge C, posedge R) 4 | if (R) 5 | Q <= RV; 6 | else 7 | Q <= D; 8 | endmodule 9 | -------------------------------------------------------------------------------- /techlibs/ecp5/.gitignore: -------------------------------------------------------------------------------- 1 | bram_init_1_2_4.vh 2 | bram_init_9_18_36.vh 3 | brams_init.mk 4 | bram_conn_1.vh 5 | bram_conn_2.vh 6 | bram_conn_4.vh 7 | bram_conn_9.vh 8 | bram_conn_18.vh 9 | brams_connect.mk 10 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_encoder_4to2_gates.v: -------------------------------------------------------------------------------- 1 | module encoder_4to2_gates (i0,i1,i2,i3,y); 2 | input i0,i1,i2,i3; 3 | output [1:0] y; 4 | 5 | or o1 (y[0],i1,i3); 6 | or o2 (y[1],i2,i3); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_bus_con.v: -------------------------------------------------------------------------------- 1 | module bus_con (a,b, y); 2 | input [3:0] a, b; 3 | output [7:0] y; 4 | wire [7:0] y; 5 | 6 | assign y = {a,b}; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_tri_buf.v: -------------------------------------------------------------------------------- 1 | module tri_buf (a,b,enable); 2 | input a; 3 | output b; 4 | input enable; 5 | wire b; 6 | 7 | assign b = (enable) ? a : 1'bz; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /examples/intel/asicworld_lfsr/runme_postsynth: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) 4 | vvp -N verif_post 5 | 6 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v: -------------------------------------------------------------------------------- 1 | module DSP48_MACC (a, b, c, y); 2 | 3 | input [17:0] a; 4 | input [24:0] b; 5 | input [47:0] c; 6 | output [47:0] y; 7 | 8 | assign y = a*b + c; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /examples/basys3/run_prog.tcl: -------------------------------------------------------------------------------- 1 | open_hw 2 | connect_hw_server 3 | open_hw_target [lindex [get_hw_targets] 0] 4 | set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0] 5 | program_hw_devices [lindex [get_hw_devices] 0] 6 | -------------------------------------------------------------------------------- /examples/smtbmc/demo4.smtc: -------------------------------------------------------------------------------- 1 | initial 2 | assume [rst] 3 | 4 | always -1 5 | assume (not [rst]) 6 | assume (=> [-1:inv2] [inv2]) 7 | 8 | final -2 9 | assume [-1:inv2] 10 | assume (not [-2:inv2]) 11 | assert (= [r1] [r2]) 12 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/example.v: -------------------------------------------------------------------------------- 1 | module example(input clk, a, b, c, 2 | output reg [1:0] y); 3 | always @(posedge clk) 4 | if (c) 5 | y <= c ? a + b : 2'd0; 6 | endmodule 7 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_simple_if.v: -------------------------------------------------------------------------------- 1 | module simple_if(); 2 | 3 | reg latch; 4 | wire enable,din; 5 | 6 | always @ (enable or din) 7 | if (enable) begin 8 | latch <= din; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/techmap/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | for x in *_runtest.sh; do 4 | echo "Running $x.." 5 | if ! bash $x &> ${x%.sh}.log; then 6 | tail ${x%.sh}.log 7 | echo ERROR 8 | exit 1 9 | fi 10 | done 11 | -------------------------------------------------------------------------------- /tests/vloghtb/test_share.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | source common.sh 5 | 6 | f=$1 7 | n=$(basename ${f%.v}) 8 | 9 | test_equiv share "wreduce; share -aggressive" "-ignore_div_by_zero" $n $f 10 | 11 | exit 0 12 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/proc_03.v: -------------------------------------------------------------------------------- 1 | module test(input A, B, C, D, E, 2 | output reg Y); 3 | always @* begin 4 | Y <= A; 5 | if (B) 6 | Y <= C; 7 | if (D) 8 | Y <= E; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_simple_function.v: -------------------------------------------------------------------------------- 1 | module simple_function(); 2 | 3 | function myfunction; 4 | input a, b, c, d; 5 | begin 6 | myfunction = ((a+b) + (c-d)); 7 | end 8 | endfunction 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_multiply.v: -------------------------------------------------------------------------------- 1 | module muliply (a,product); 2 | input [3:0] a; 3 | output [4:0] product; 4 | wire [4:0] product; 5 | 6 | assign product = a << 1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_mux_21.v: -------------------------------------------------------------------------------- 1 | module mux_21 (a,b,sel,y); 2 | input a, b; 3 | output y; 4 | input sel; 5 | wire y; 6 | 7 | assign y = (sel) ? b : a; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/red_or3x1_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog red_or3x1_test.v 2 | hierarchy -check -top test 3 | 4 | techmap -map red_or3x1_map.v;; 5 | 6 | splitnets -ports 7 | show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v 8 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_reg_combo_example.v: -------------------------------------------------------------------------------- 1 | module reg_combo_example( a, b, y); 2 | input a, b; 3 | output y; 4 | 5 | reg y; 6 | wire a, b; 7 | 8 | always @ ( a or b) 9 | begin 10 | y = a & b; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/simple/always01.v: -------------------------------------------------------------------------------- 1 | module uut_always01(clock, reset, count); 2 | 3 | input clock, reset; 4 | output [3:0] count; 5 | reg [3:0] count; 6 | 7 | always @(posedge clock) 8 | count <= reset ? 0 : count + 1; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /examples/intel/asicworld_lfsr/README: -------------------------------------------------------------------------------- 1 | Source of the files: 2 | http://www.asic-world.com/examples/verilog/lfsr.html 3 | 4 | Run first: runme_presynth 5 | Generate output netlist with run_max10 or run_cycloneiv 6 | Then, check with: runme_postsynth 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/mulshift_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog mulshift_test.v 2 | hierarchy -check -top test 3 | 4 | techmap -map sym_mul_map.v \ 5 | -map mulshift_map.v;; 6 | 7 | show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v 8 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/abc_01.v: -------------------------------------------------------------------------------- 1 | module test(input clk, a, b, c, 2 | output reg y); 3 | 4 | reg [2:0] q1, q2; 5 | always @(posedge clk) begin 6 | q1 <= { a, b, c }; 7 | q2 <= q1; 8 | y <= ^q2; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/lut/check_map.ys: -------------------------------------------------------------------------------- 1 | simplemap 2 | equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v 3 | design -load postopt 4 | equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v 5 | design -load postopt 6 | select -assert-count 0 t:* t:$lut %d 7 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_task_global.v: -------------------------------------------------------------------------------- 1 | module task_global(); 2 | 3 | reg [7:0] temp_out; 4 | reg [7:0] temp_in; 5 | 6 | task convert; 7 | begin 8 | temp_out = (9/5) *( temp_in + 32); 9 | end 10 | endtask 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/vloghtb/test_makefile: -------------------------------------------------------------------------------- 1 | 2 | MODE := share 3 | TESTS := $(shell ls rtl/ | sed 's,\.v$$,,' ) 4 | 5 | run: $(addprefix log_test_$(MODE)/,$(addsuffix .txt,$(TESTS))) 6 | 7 | log_test_$(MODE)/%.txt: rtl/%.v 8 | @bash test_$(MODE).sh $< 9 | 10 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_if_else.v: -------------------------------------------------------------------------------- 1 | module if_else(); 2 | 3 | reg dff; 4 | wire clk,din,reset; 5 | 6 | always @ (posedge clk) 7 | if (reset) begin 8 | dff <= 0; 9 | end else begin 10 | dff <= din; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_which_clock.v: -------------------------------------------------------------------------------- 1 | module which_clock (x,y,q,d); 2 | input x,y,d; 3 | output q; 4 | reg q; 5 | 6 | always @ (posedge x or posedge y) 7 | if (x) 8 | q <= 1'b0; 9 | else 10 | q <= d; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /examples/basys3/run_vivado.tcl: -------------------------------------------------------------------------------- 1 | read_xdc example.xdc 2 | read_edif example.edif 3 | link_design -part xc7a35tcpg236-1 -top example 4 | opt_design 5 | place_design 6 | route_design 7 | report_utilization 8 | report_timing 9 | write_bitstream -force example.bit 10 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_blocking.v: -------------------------------------------------------------------------------- 1 | module blocking (clk,a,c); 2 | input clk; 3 | input a; 4 | output c; 5 | 6 | wire clk; 7 | wire a; 8 | reg c; 9 | reg b; 10 | 11 | always @ (posedge clk ) 12 | begin 13 | b = a; 14 | c = b; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests/simple/always02.v: -------------------------------------------------------------------------------- 1 | module uut_always02(clock, reset, count); 2 | 3 | input clock, reset; 4 | output [3:0] count; 5 | reg [3:0] count; 6 | 7 | always @(posedge clock) begin 8 | count <= count + 1; 9 | if (reset) 10 | count <= 0; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/sumprod.v: -------------------------------------------------------------------------------- 1 | module sumprod(a, b, c, sum, prod); 2 | 3 | input [7:0] a, b, c; 4 | output [7:0] sum, prod; 5 | 6 | {* sumstuff *} 7 | assign sum = a + b + c; 8 | {* *} 9 | 10 | assign prod = a * b * c; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Intro/counter.v: -------------------------------------------------------------------------------- 1 | module counter (clk, rst, en, count); 2 | 3 | input clk, rst, en; 4 | output reg [1:0] count; 5 | 6 | always @(posedge clk) 7 | if (rst) 8 | count <= 2'd0; 9 | else if (en) 10 | count <= count + 2'd1; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_always_example.v: -------------------------------------------------------------------------------- 1 | module always_example(); 2 | reg clk,reset,enable,q_in,data; 3 | 4 | always @ (posedge clk) 5 | if (reset) begin 6 | data <= 0; 7 | end else if (enable) begin 8 | data <= q_in; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/always01_pub.v: -------------------------------------------------------------------------------- 1 | module uut_always01(clock, 2 | reset, count); 3 | 4 | input clock, reset; 5 | output [3:0] count; 6 | reg [3:0] count; 7 | 8 | always @(posedge clock) 9 | count <= reset ? 10 | 0 : count + 1; 11 | 12 | 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_nonblocking.v: -------------------------------------------------------------------------------- 1 | module nonblocking (clk,a,c); 2 | input clk; 3 | input a; 4 | output c; 5 | 6 | wire clk; 7 | wire a; 8 | reg c; 9 | reg b; 10 | 11 | always @ (posedge clk ) 12 | begin 13 | b <= a; 14 | c <= b; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /passes/tests/flowmap/pack1p.v: -------------------------------------------------------------------------------- 1 | // Like pack1.v, but results in a simpler network. 2 | module top(...); 3 | input a,b,c,d,e,f,g,h; 4 | wire x = c|d; 5 | wire y = e&f; 6 | wire u = a&b; 7 | wire v = x|y; 8 | wire w = g&h; 9 | output s = u|v; 10 | output t = v|w; 11 | endmodule 12 | -------------------------------------------------------------------------------- /examples/cmos/counter.v: -------------------------------------------------------------------------------- 1 | module counter (clk, rst, en, count); 2 | 3 | input clk, rst, en; 4 | output reg [2:0] count; 5 | 6 | always @(posedge clk) 7 | if (rst) 8 | count <= 3'd0; 9 | else if (en) 10 | count <= count + 3'd1; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /frontends/verific/example.sby: -------------------------------------------------------------------------------- 1 | # Simple SymbiYosys example job utilizing Verific 2 | 3 | [options] 4 | mode prove 5 | depth 10 6 | 7 | [engines] 8 | smtbmc yices 9 | 10 | [script] 11 | verific -sv example.sv 12 | verific -import top 13 | prep -top top 14 | 15 | [files] 16 | example.sv 17 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/memory_01.v: -------------------------------------------------------------------------------- 1 | module test(input CLK, ADDR, 2 | input [7:0] DIN, 3 | output reg [7:0] DOUT); 4 | reg [7:0] mem [0:1]; 5 | always @(posedge CLK) begin 6 | mem[ADDR] <= DIN; 7 | DOUT <= mem[ADDR]; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_d_ff.v: -------------------------------------------------------------------------------- 1 | // D flip-flop Code 2 | module d_ff ( d, clk, q, q_bar); 3 | input d ,clk; 4 | output q, q_bar; 5 | wire d ,clk; 6 | reg q, q_bar; 7 | 8 | always @ (posedge clk) 9 | begin 10 | q <= d; 11 | q_bar <= !d; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /libs/bigint/BigIntegerLibrary.hh: -------------------------------------------------------------------------------- 1 | // This header file includes all of the library header files. 2 | 3 | #include "NumberlikeArray.hh" 4 | #include "BigUnsigned.hh" 5 | #include "BigInteger.hh" 6 | #include "BigIntegerAlgorithms.hh" 7 | #include "BigUnsignedInABase.hh" 8 | #include "BigIntegerUtils.hh" 9 | -------------------------------------------------------------------------------- /techlibs/achronix/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/achronix/synth_achronix.o 3 | 4 | $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v)) 5 | $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v)) 6 | 7 | -------------------------------------------------------------------------------- /techlibs/anlogic/drams.txt: -------------------------------------------------------------------------------- 1 | bram $__ANLOGIC_DRAM16X4 2 | init 1 3 | abits 4 4 | dbits 4 5 | groups 2 6 | ports 1 1 7 | wrmode 0 1 8 | enable 0 1 9 | transp 0 0 10 | clocks 0 1 11 | clkpol 0 1 12 | endbram 13 | 14 | match $__ANLOGIC_DRAM16X4 15 | make_outreg 16 | endmatch 17 | -------------------------------------------------------------------------------- /techlibs/gowin/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/gowin/synth_gowin.o 3 | 4 | $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) 5 | $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) 6 | $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) 7 | 8 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_d_latch_gates.v: -------------------------------------------------------------------------------- 1 | module d_latch_gates(d,clk,q,q_bar); 2 | input d,clk; 3 | output q, q_bar; 4 | 5 | wire n1,n2,n3; 6 | 7 | not (n1,d); 8 | 9 | nand (n2,d,clk); 10 | nand (n3,n1,clk); 11 | 12 | nand (q,q_bar,n2); 13 | nand (q_bar,q,n3); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/unit/kernel/logTest.cc: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "kernel/yosys.h" 4 | #include "kernel/log.h" 5 | 6 | YOSYS_NAMESPACE_BEGIN 7 | 8 | TEST(KernelLogTest, logvValidValues) 9 | { 10 | //TODO: Implement log test 11 | EXPECT_EQ(7, 7); 12 | } 13 | 14 | YOSYS_NAMESPACE_END 15 | -------------------------------------------------------------------------------- /backends/protobuf/Makefile.inc: -------------------------------------------------------------------------------- 1 | ifeq ($(ENABLE_PROTOBUF),1) 2 | 3 | backends/protobuf/yosys.pb.cc backends/protobuf/yosys.pb.h: misc/yosys.proto 4 | $(Q) cd misc && protoc --cpp_out "../backends/protobuf" yosys.proto 5 | 6 | OBJS += backends/protobuf/protobuf.o backends/protobuf/yosys.pb.o 7 | 8 | endif 9 | -------------------------------------------------------------------------------- /examples/smtbmc/demo6.v: -------------------------------------------------------------------------------- 1 | // Demo for assertpmux 2 | 3 | module demo6 (input A, B, C, D, E, output reg Y); 4 | always @* begin 5 | Y = 0; 6 | if (A != B) begin 7 | (* parallel_case *) 8 | case (C) 9 | A: Y = D; 10 | B: Y = E; 11 | endcase 12 | end 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/example.ys: -------------------------------------------------------------------------------- 1 | read_verilog example.v 2 | show -format dot -prefix example_00 3 | proc 4 | show -format dot -prefix example_01 5 | opt 6 | show -format dot -prefix example_02 7 | 8 | cd example 9 | select t:$add 10 | show -format dot -prefix example_03 11 | 12 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/splice.v: -------------------------------------------------------------------------------- 1 | module splice_demo(a, b, c, d, e, f, x, y); 2 | 3 | input [1:0] a, b, c, d, e, f; 4 | output [1:0] x = {a[0], a[1]}; 5 | 6 | output [11:0] y; 7 | assign {y[11:4], y[1:0], y[3:2]} = 8 | {a, b, -{c, d}, ~{e, f}}; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/always02_pub.v: -------------------------------------------------------------------------------- 1 | module uut_always02(clock, 2 | reset, count); 3 | 4 | input clock, reset; 5 | output [3:0] count; 6 | reg [3:0] count; 7 | 8 | always @(posedge clock) begin 9 | count <= count + 1; 10 | if (reset) 11 | count <= 0; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /techlibs/ice40/tests/.gitignore: -------------------------------------------------------------------------------- 1 | /test_ffs_[01][01][01][01][01]_* 2 | /test_bram_[0-9]* 3 | /test_dsp_model 4 | /test_dsp_model.vcd 5 | /test_dsp_model_ref.v 6 | /test_dsp_model_uut.v 7 | /test_dsp_map 8 | /test_dsp_map.vcd 9 | /test_dsp_map_tb.v 10 | /test_dsp_map_top.v 11 | /test_dsp_map_syn.v 12 | -------------------------------------------------------------------------------- /techlibs/ice40/tests/test_arith.ys: -------------------------------------------------------------------------------- 1 | read_verilog test_arith.v 2 | synth_ice40 3 | techmap -map ../cells_sim.v 4 | rename test gate 5 | 6 | read_verilog test_arith.v 7 | rename test gold 8 | 9 | miter -equiv -flatten -make_outputs gold gate miter 10 | sat -verify -prove trigger 0 -show-ports miter 11 | -------------------------------------------------------------------------------- /techlibs/xilinx/tests/bram2.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims 5 | ../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v 6 | iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v 7 | vvp -N bram2_tb 8 | 9 | -------------------------------------------------------------------------------- /backends/smt2/example.v: -------------------------------------------------------------------------------- 1 | module main(input clk); 2 | reg [3:0] counter = 0; 3 | always @(posedge clk) begin 4 | if (counter == 10) 5 | counter <= 0; 6 | else 7 | counter <= counter + 1; 8 | end 9 | assert property (counter != 15); 10 | // assert property (counter <= 10); 11 | endmodule 12 | -------------------------------------------------------------------------------- /examples/smtbmc/demo8.v: -------------------------------------------------------------------------------- 1 | // Simple exists-forall demo 2 | 3 | module demo8; 4 | wire [7:0] prime = $anyconst; 5 | wire [3:0] factor = $allconst; 6 | 7 | always @* begin 8 | if (1 < factor && factor < prime) 9 | assume((prime % factor) != 0); 10 | assume(prime > 1); 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/always01.v: -------------------------------------------------------------------------------- 1 | module uut_always01(clock, reset, c3, c2, c1, c0); 2 | 3 | input clock, reset; 4 | output c3, c2, c1, c0; 5 | reg [3:0] count; 6 | 7 | assign {c3, c2, c1, c0} = count; 8 | 9 | always @(posedge clock) 10 | count <= reset ? 0 : count + 1; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/simple/arraycells.v: -------------------------------------------------------------------------------- 1 | 2 | module array_test001(a, b, c, y); 3 | input a; 4 | input [31:0] b, c; 5 | output [31:0] y; 6 | 7 | aoi12 p [31:0] (a, b, c, y); 8 | endmodule 9 | 10 | module aoi12(a, b, c, y); 11 | input a, b, c; 12 | output y; 13 | assign y = ~((a & b) | c); 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /examples/igloo2/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v 4 | export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} 5 | /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl 6 | cp proj/designer/example/export/example.stp . 7 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Intro/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: counter_00.pdf counter_01.pdf counter_02.pdf counter_03.pdf 3 | 4 | counter_00.pdf: counter.v counter.ys mycells.lib 5 | ../../yosys counter.ys 6 | 7 | counter_01.pdf: counter_00.pdf 8 | counter_02.pdf: counter_00.pdf 9 | counter_03.pdf: counter_00.pdf 10 | 11 | -------------------------------------------------------------------------------- /techlibs/ecp5/dram.txt: -------------------------------------------------------------------------------- 1 | bram $__TRELLIS_DPR16X4 2 | init 1 3 | abits 4 4 | dbits 4 5 | groups 2 6 | ports 1 1 7 | wrmode 0 1 8 | enable 0 1 9 | transp 0 0 10 | clocks 0 1 11 | clkpol 0 2 12 | endbram 13 | 14 | match $__TRELLIS_DPR16X4 15 | make_outreg 16 | min wports 1 17 | endmatch 18 | -------------------------------------------------------------------------------- /techlibs/sf2/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/sf2/synth_sf2.o 3 | OBJS += techlibs/sf2/sf2_iobs.o 4 | 5 | $(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v)) 6 | $(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v)) 7 | $(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_sim.v)) 8 | 9 | -------------------------------------------------------------------------------- /tests/sat/counters.ys: -------------------------------------------------------------------------------- 1 | 2 | read_verilog counters.v 3 | proc; opt 4 | 5 | expose -shared counter1 counter2 6 | miter -equiv -make_assert -make_outputs counter1 counter2 miter 7 | 8 | cd miter; flatten; opt 9 | sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs 10 | 11 | -------------------------------------------------------------------------------- /tests/unit/kernel/rtlilTest.cc: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "kernel/yosys.h" 4 | #include "kernel/rtlil.h" 5 | 6 | YOSYS_NAMESPACE_BEGIN 7 | 8 | TEST(KernelRtlilTest, getReferenceValid) 9 | { 10 | //TODO: Implement rtlil test 11 | EXPECT_EQ(33, 33); 12 | } 13 | 14 | YOSYS_NAMESPACE_END 15 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/foobaraddsub.v: -------------------------------------------------------------------------------- 1 | module foobaraddsub(a, b, c, d, fa, fs, ba, bs); 2 | input [7:0] a, b, c, d; 3 | output [7:0] fa, fs, ba, bs; 4 | assign fa = a + (* foo *) b; 5 | assign fs = a - (* foo *) b; 6 | assign ba = c + (* bar *) d; 7 | assign bs = c - (* bar *) d; 8 | endmodule 9 | -------------------------------------------------------------------------------- /passes/tests/flowmap/pack1.v: -------------------------------------------------------------------------------- 1 | // Exact reproduction of Figure 3(a) from 10.1109/92.285741. 2 | module top(...); 3 | input a,b,c,d,e,f,g,h; 4 | wire x = !(c|d); 5 | wire y = !(e&f); 6 | wire u = !(a&b); 7 | wire v = !(x|y); 8 | wire w = !(g&h); 9 | output s = !(u|v); 10 | output t = !(v|w); 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_decoder_2to4_gates.v: -------------------------------------------------------------------------------- 1 | module decoder_2to4_gates (x,y,f0,f1,f2,f3); 2 | input x,y; 3 | output f0,f1,f2,f3; 4 | 5 | wire n1,n2; 6 | 7 | not i1 (n1,x); 8 | not i2 (n2,y); 9 | and a1 (f0,n1,n2); 10 | and a2 (f1,n1,y); 11 | and a3 (f2,x,n2); 12 | and a4 (f3,x,y); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/sat/splice.ys: -------------------------------------------------------------------------------- 1 | read_verilog splice.v 2 | hierarchy -check; opt 3 | copy test gold 4 | 5 | cd test 6 | splice 7 | # show 8 | 9 | cd .. 10 | rename test gate 11 | miter -equiv -make_assert -make_outputs gold gate miter 12 | 13 | flatten miter 14 | sat -verify -prove-asserts -show-inputs -show-outputs miter 15 | -------------------------------------------------------------------------------- /examples/osu035/example.ys: -------------------------------------------------------------------------------- 1 | read_verilog example.v 2 | read_liberty -lib osu035_stdcells.lib 3 | 4 | synth -top top 5 | 6 | dfflibmap -liberty osu035_stdcells.lib 7 | abc -D 10000 -constr example.constr -liberty osu035_stdcells.lib 8 | opt_clean 9 | 10 | stat -liberty osu035_stdcells.lib 11 | write_edif example.edif 12 | -------------------------------------------------------------------------------- /passes/proc/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/proc/proc.o 3 | OBJS += passes/proc/proc_clean.o 4 | OBJS += passes/proc/proc_rmdead.o 5 | OBJS += passes/proc/proc_init.o 6 | OBJS += passes/proc/proc_arst.o 7 | OBJS += passes/proc/proc_mux.o 8 | OBJS += passes/proc/proc_dlatch.o 9 | OBJS += passes/proc/proc_dff.o 10 | 11 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_flip_flop.v: -------------------------------------------------------------------------------- 1 | module flif_flop (clk,reset, q, d); 2 | input clk, reset, d; 3 | output q; 4 | reg q; 5 | 6 | always @ (posedge clk ) 7 | begin 8 | if (reset == 1) begin 9 | q <= 0; 10 | end else begin 11 | q <= d; 12 | end 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /techlibs/ecp5/latches_map.v: -------------------------------------------------------------------------------- 1 | module \$_DLATCH_N_ (E, D, Q); 2 | wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; 3 | input E, D; 4 | output Q = !E ? D : Q; 5 | endmodule 6 | 7 | module \$_DLATCH_P_ (E, D, Q); 8 | wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; 9 | input E, D; 10 | output Q = E ? D : Q; 11 | endmodule 12 | -------------------------------------------------------------------------------- /techlibs/ice40/latches_map.v: -------------------------------------------------------------------------------- 1 | module \$_DLATCH_N_ (E, D, Q); 2 | wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; 3 | input E, D; 4 | output Q = !E ? D : Q; 5 | endmodule 6 | 7 | module \$_DLATCH_P_ (E, D, Q); 8 | wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; 9 | input E, D; 10 | output Q = E ? D : Q; 11 | endmodule 12 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_reg_seq_example.v: -------------------------------------------------------------------------------- 1 | module reg_seq_example( clk, reset, d, q); 2 | input clk, reset, d; 3 | output q; 4 | 5 | reg q; 6 | wire clk, reset, d; 7 | 8 | always @ (posedge clk or posedge reset) 9 | if (reset) begin 10 | q <= 1'b0; 11 | end else begin 12 | q <= d; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/simple/undef_eqx_nex.v: -------------------------------------------------------------------------------- 1 | module undef_eqx_nex(y); 2 | output [7:0] y; 3 | assign y[0] = 0/0; 4 | assign y[1] = 0/1; 5 | assign y[2] = 0/0 == 32'bx; 6 | assign y[3] = 0/0 != 32'bx; 7 | assign y[4] = 0/0 === 32'bx; 8 | assign y[5] = 0/0 !== 32'bx; 9 | assign y[6] = 0/1 === 32'bx; 10 | assign y[7] = 0/1 !== 32'bx; 11 | endmodule 12 | -------------------------------------------------------------------------------- /passes/pmgen/Makefile.inc: -------------------------------------------------------------------------------- 1 | OBJS += passes/pmgen/ice40_dsp.o 2 | 3 | passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h 4 | EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h 5 | .SECONDARY: passes/pmgen/ice40_dsp_pm.h 6 | 7 | passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg 8 | $(P) mkdir -p passes/pmgen && python3 $^ $@ 9 | -------------------------------------------------------------------------------- /tests/sat/splice.v: -------------------------------------------------------------------------------- 1 | module test(a, b, y); 2 | 3 | input [15:0] a, b; 4 | output [15:0] y; 5 | 6 | wire [7:0] ah = a[15:8], al = a[7:0]; 7 | wire [7:0] bh = b[15:8], bl = b[7:0]; 8 | 9 | wire [7:0] th = ah + bh, tl = al + bl; 10 | wire [15:0] t = {th, tl}, k = t ^ 16'hcd; 11 | 12 | assign y = { k[7:0], k[15:8] }; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /examples/gowin/demo.v: -------------------------------------------------------------------------------- 1 | module demo ( 2 | input clk, 3 | input [3:0] sw, 4 | output [15:0] leds, 5 | output [7:0] seg7dig, 6 | output [3:0] seg7sel 7 | ); 8 | localparam PRESCALE = 20; 9 | reg [PRESCALE+3:0] counter = 0; 10 | always @(posedge clk) counter <= counter + 1; 11 | assign leds = 1 << counter[PRESCALE +: 4]; 12 | endmodule 13 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/always02.v: -------------------------------------------------------------------------------- 1 | module uut_always02(clock, reset, c3, c2, c1, c0); 2 | 3 | input clock, reset; 4 | output c3, c2, c1, c0; 5 | reg [3:0] count; 6 | 7 | assign {c3, c2, c1, c0} = count; 8 | 9 | always @(posedge clock) begin 10 | count <= count + 1; 11 | if (reset) 12 | count <= 0; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /passes/fsm/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/fsm/fsm.o 3 | OBJS += passes/fsm/fsm_detect.o 4 | OBJS += passes/fsm/fsm_extract.o 5 | OBJS += passes/fsm/fsm_opt.o 6 | OBJS += passes/fsm/fsm_expand.o 7 | OBJS += passes/fsm/fsm_recode.o 8 | OBJS += passes/fsm/fsm_info.o 9 | OBJS += passes/fsm/fsm_export.o 10 | OBJS += passes/fsm/fsm_map.o 11 | 12 | -------------------------------------------------------------------------------- /techlibs/common/dff2ff.v: -------------------------------------------------------------------------------- 1 | (* techmap_celltype = "$dff" *) 2 | module dff2ff (CLK, D, Q); 3 | parameter WIDTH = 1; 4 | parameter CLK_POLARITY = 1; 5 | 6 | input CLK; 7 | input [WIDTH-1:0] D; 8 | output reg [WIDTH-1:0] Q; 9 | 10 | wire [1023:0] _TECHMAP_DO_ = "proc;;"; 11 | 12 | always @($global_clock) 13 | Q <= D; 14 | endmodule 15 | -------------------------------------------------------------------------------- /techlibs/greenpak4/cells_latch.v: -------------------------------------------------------------------------------- 1 | module $_DLATCH_P_(input E, input D, output Q); 2 | GP_DLATCH _TECHMAP_REPLACE_ ( 3 | .D(D), 4 | .nCLK(!E), 5 | .Q(Q) 6 | ); 7 | endmodule 8 | 9 | module $_DLATCH_N_(input E, input D, output Q); 10 | GP_DLATCH _TECHMAP_REPLACE_ ( 11 | .D(D), 12 | .nCLK(E), 13 | .Q(Q) 14 | ); 15 | endmodule 16 | -------------------------------------------------------------------------------- /examples/anlogic/build.tcl: -------------------------------------------------------------------------------- 1 | import_device eagle_s20.db -package BG256 2 | read_verilog full.v -top demo 3 | read_adc demo.adc 4 | optimize_rtl 5 | map_macro 6 | map 7 | pack 8 | place 9 | route 10 | report_area -io_info -file demo_phy.area 11 | bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000 12 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_seq.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_seq_ff_1_test.v 3 | module f1_test(input in, input clk, output reg out); 4 | always @(posedge clk) 5 | out <= in; 6 | endmodule 7 | 8 | // test_simulation_seq_ff_2_test.v 9 | module f2_test(input in, input clk, output reg out); 10 | always @(negedge clk) 11 | out <= in; 12 | endmodule 13 | -------------------------------------------------------------------------------- /examples/smtbmc/demo4.v: -------------------------------------------------------------------------------- 1 | // Demo for "final" smtc constraints 2 | 3 | module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2); 4 | always @(posedge clk) begin 5 | if (rst) begin 6 | r1 <= in; 7 | r2 <= -in; 8 | end else begin 9 | r1 <= r1 + in; 10 | r2 <= inv2 ? -(r2 - in) : (r2 - in); 11 | end 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/sva/sva_range.sv: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, 3 | input a, b, c, d 4 | ); 5 | default clocking @(posedge clk); endclocking 6 | 7 | assert property ( 8 | a ##[*] b |=> c until d 9 | ); 10 | 11 | `ifndef FAIL 12 | assume property ( 13 | b |=> ##5 d 14 | ); 15 | assume property ( 16 | b || (c && !d) |=> c 17 | ); 18 | `endif 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_escape_id.v: -------------------------------------------------------------------------------- 1 | // There must be white space after the 2 | // string which uses escape character 3 | module \1dff ( 4 | q, // Q output 5 | \q~ , // Q_out output 6 | d, // D input 7 | cl$k, // CLOCK input 8 | \reset* // Reset input 9 | ); 10 | 11 | input d, cl$k, \reset* ; 12 | output q, \q~ ; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /tests/simple/arrays01.v: -------------------------------------------------------------------------------- 1 | module uut_arrays01(clock, we, addr, wr_data, rd_data); 2 | 3 | input clock, we; 4 | input [3:0] addr, wr_data; 5 | output [3:0] rd_data; 6 | reg [3:0] rd_data; 7 | 8 | reg [3:0] memory [15:0]; 9 | 10 | always @(posedge clock) begin 11 | if (we) 12 | memory[addr] <= wr_data; 13 | rd_data <= memory[addr]; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/simple/wreduce.v: -------------------------------------------------------------------------------- 1 | module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z); 2 | assign x = -$signed({1'b0, a}); 3 | assign y = $signed({1'b0, a}) + $signed({1'b0, b}); 4 | assign z = x ^ y; 5 | endmodule 6 | 7 | module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w); 8 | assign x = a - b, y = a * b, z = a >> b, w = a << b; 9 | endmodule 10 | -------------------------------------------------------------------------------- /tests/sva/sva_throughout.sv: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, 3 | input a, b, c, d 4 | ); 5 | default clocking @(posedge clk); endclocking 6 | 7 | assert property ( 8 | a |=> b throughout (c ##1 d) 9 | ); 10 | 11 | `ifndef FAIL 12 | assume property ( 13 | a |=> b && c 14 | ); 15 | assume property ( 16 | b && c |=> b && d 17 | ); 18 | `endif 19 | endmodule 20 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/select.ys: -------------------------------------------------------------------------------- 1 | read_verilog select.v 2 | hierarchy -check -top test 3 | proc; opt 4 | cd test 5 | select -set cone_a state_a %ci*:-$dff 6 | select -set cone_b state_b %ci*:-$dff 7 | select -set cone_ab @cone_a @cone_b %i 8 | show -prefix select -format pdf -notitle \ 9 | -color red @cone_ab -color magenta @cone_a \ 10 | -color blue @cone_b 11 | -------------------------------------------------------------------------------- /tests/techmap/mem_simple_4x1_cells.v: -------------------------------------------------------------------------------- 1 | module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); 2 | input CLK, WR_DATA, WR_EN; 3 | input [3:0] RD_ADDR, WR_ADDR; 4 | output reg RD_DATA; 5 | 6 | reg [15:0] memory; 7 | 8 | always @(posedge CLK) begin 9 | if (WR_EN) 10 | memory[WR_ADDR] <= WR_DATA; 11 | RD_DATA <= memory[RD_ADDR]; 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/techmap/mem_simple_4x1_uut.v: -------------------------------------------------------------------------------- 1 | module uut (clk, rst, out, counter); 2 | 3 | input clk, rst; 4 | output reg [7:0] out; 5 | output reg [4:0] counter; 6 | 7 | reg [7:0] memory [0:19]; 8 | 9 | always @(posedge clk) begin 10 | counter <= rst || counter == 19 ? 0 : counter+1; 11 | memory[counter] <= counter; 12 | out <= memory[counter]; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /frontends/verific/example.sv: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, rst, 3 | output reg [3:0] cnt 4 | ); 5 | initial cnt = 0; 6 | 7 | always @(posedge clk) begin 8 | if (rst) 9 | cnt <= 0; 10 | else 11 | cnt <= cnt + 4'd 1; 12 | end 13 | 14 | always @(posedge clk) begin 15 | assume (cnt != 10); 16 | assert (cnt != 15); 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /passes/tests/flowmap/pack3p.v: -------------------------------------------------------------------------------- 1 | // Like pack2.v, but results in a simpler network. 2 | module top(...); 3 | input a,b,c,d,e,f,g,h,i,j; 4 | wire x = a&b; 5 | wire y = c|d; 6 | wire z = e|f; 7 | wire n0 = g&h; 8 | wire n1 = i|j; 9 | wire w = x&y; 10 | wire n2 = z&n0; 11 | wire n3 = n0|n1; 12 | wire n4 = n2|n3; 13 | wire v = w|n5; 14 | output u = w&v; 15 | endmodule 16 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/arrays01.v: -------------------------------------------------------------------------------- 1 | module uut_arrays01(clock, we, addr, wr_data, rd_data); 2 | 3 | input clock, we; 4 | input [3:0] addr, wr_data; 5 | output [3:0] rd_data; 6 | reg [3:0] rd_data; 7 | 8 | reg [3:0] memory [15:0]; 9 | 10 | always @(posedge clock) begin 11 | if (we) 12 | memory[addr] <= wr_data; 13 | rd_data <= memory[addr]; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_syn_reset.v: -------------------------------------------------------------------------------- 1 | module syn_reset (clk,reset,a,c); 2 | input clk; 3 | input reset; 4 | input a; 5 | output c; 6 | 7 | wire clk; 8 | wire reset; 9 | wire a; 10 | reg c; 11 | 12 | always @ (posedge clk ) 13 | if ( reset == 1'b1) begin 14 | c <= 0; 15 | end else begin 16 | c <= a; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/forgen01.v: -------------------------------------------------------------------------------- 1 | module uut_forgen01(a, y); 2 | 3 | input [4:0] a; 4 | output y; 5 | 6 | integer i, j; 7 | reg [31:0] lut; 8 | 9 | initial begin 10 | for (i = 0; i < 32; i = i+1) begin 11 | lut[i] = i > 1; 12 | for (j = 2; j*j <= i; j = j+1) 13 | if (i % j == 0) 14 | lut[i] = 0; 15 | end 16 | end 17 | 18 | assign y = lut[a]; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/opt_04.v: -------------------------------------------------------------------------------- 1 | module test(input CLK, ARST, 2 | output [7:0] Q1, Q2, Q3); 3 | 4 | wire NO_CLK = 0; 5 | 6 | always @(posedge CLK, posedge ARST) 7 | if (ARST) 8 | Q1 <= 42; 9 | 10 | always @(posedge NO_CLK, posedge ARST) 11 | if (ARST) 12 | Q2 <= 42; 13 | else 14 | Q2 <= 23; 15 | 16 | always @(posedge CLK) 17 | Q3 <= 42; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests/sat/initval.v: -------------------------------------------------------------------------------- 1 | module test(input clk, input [3:0] bar, output [3:0] foo); 2 | reg [3:0] foo = 0; 3 | reg [3:0] last_bar = 0; 4 | 5 | always @* 6 | foo[1:0] <= bar[1:0]; 7 | 8 | always @(posedge clk) 9 | foo[3:2] <= bar[3:2]; 10 | 11 | always @(posedge clk) 12 | last_bar <= bar; 13 | 14 | assert property (foo == {last_bar[3:2], bar[1:0]}); 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/sva/basic04.sv: -------------------------------------------------------------------------------- 1 | module top_properties (input logic clock, read, write, ready); 2 | a_rw: assert property ( @(posedge clock) !(read && write) ); 3 | `ifdef FAIL 4 | a_wr: assert property ( @(posedge clock) write |-> ready ); 5 | `else 6 | a_wr: assert property ( @(posedge clock) write |=> ready ); 7 | `endif 8 | endmodule 9 | 10 | bind top top_properties properties_inst (.*); 11 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/scrambler.v: -------------------------------------------------------------------------------- 1 | module scrambler( 2 | input clk, rst, in_bit, 3 | output reg out_bit 4 | ); 5 | reg [31:0] xs; 6 | always @(posedge clk) begin 7 | if (rst) 8 | xs = 1; 9 | xs = xs ^ (xs << 13); 10 | xs = xs ^ (xs >> 17); 11 | xs = xs ^ (xs << 5); 12 | out_bit <= in_bit ^ xs[0]; 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /passes/sat/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/sat/sat.o 3 | OBJS += passes/sat/freduce.o 4 | OBJS += passes/sat/eval.o 5 | OBJS += passes/sat/sim.o 6 | OBJS += passes/sat/miter.o 7 | OBJS += passes/sat/expose.o 8 | OBJS += passes/sat/assertpmux.o 9 | OBJS += passes/sat/clk2fflogic.o 10 | OBJS += passes/sat/async2sync.o 11 | OBJS += passes/sat/supercover.o 12 | OBJS += passes/sat/mutate.o 13 | 14 | -------------------------------------------------------------------------------- /passes/tests/flowmap/flowp.v: -------------------------------------------------------------------------------- 1 | // Like flow.v, but results in a network identical to Figure 2(b). 2 | module top(...); 3 | input a,b,c,d,e,f; 4 | wire A = b&c; 5 | wire B = c|d; 6 | wire C = e&f; 7 | wire D = A|B; 8 | wire E = a&D; 9 | wire F = D&C; 10 | wire G = F|B; 11 | wire H = a&F; 12 | wire I = E|G; 13 | wire J = G&C; 14 | output p = H&I; 15 | output q = A|J; 16 | endmodule 17 | -------------------------------------------------------------------------------- /tests/various/constmsk_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog constmsk_test.v 2 | 3 | copy test gold 4 | rename test gate 5 | 6 | cd gate 7 | techmap -map constmsk_testmap.v;; 8 | cd .. 9 | 10 | select -assert-count 2 gold/r:A_WIDTH=3 11 | select -assert-count 1 gate/r:A_WIDTH=2 12 | select -assert-count 1 gate/c:* 13 | 14 | miter -equiv -flatten gold gate miter 15 | sat -verify -prove trigger 0 miter 16 | -------------------------------------------------------------------------------- /.travis/common.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | # Setup the CC / CXX from the matrix config 4 | eval "${MATRIX_EVAL}" 5 | 6 | # Look for location binaries first 7 | export PATH="$HOME/.local-bin/bin:$PATH" 8 | 9 | # OS X specific common setup 10 | if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then 11 | export PATH="/usr/local/opt/ccache/libexec:$PATH" 12 | fi 13 | 14 | # Parallel builds! 15 | MAKEFLAGS="-j 2" 16 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_xilinx_test.v: -------------------------------------------------------------------------------- 1 | module test1(a, b, c, d, e, f, y); 2 | input [19:0] a, b, c; 3 | input [15:0] d, e, f; 4 | output [41:0] y; 5 | assign y = a*b + c*d + e*f; 6 | endmodule 7 | 8 | module test2(a, b, c, d, e, f, y); 9 | input [19:0] a, b, c; 10 | input [15:0] d, e, f; 11 | output [41:0] y; 12 | assign y = a*b + (c*d + e*f); 13 | endmodule 14 | -------------------------------------------------------------------------------- /passes/memory/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/memory/memory.o 3 | OBJS += passes/memory/memory_dff.o 4 | OBJS += passes/memory/memory_share.o 5 | OBJS += passes/memory/memory_collect.o 6 | OBJS += passes/memory/memory_unpack.o 7 | OBJS += passes/memory/memory_bram.o 8 | OBJS += passes/memory/memory_map.o 9 | OBJS += passes/memory/memory_memx.o 10 | OBJS += passes/memory/memory_nordff.o 11 | 12 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_n_out_primitive.v: -------------------------------------------------------------------------------- 1 | module n_out_primitive(); 2 | 3 | wire out,out_0,out_1,out_2,out_3,out_a,out_b,out_c; 4 | wire in; 5 | 6 | // one output Buffer gate 7 | buf u_buf0 (out,in); 8 | // four output Buffer gate 9 | buf u_buf1 (out_0, out_1, out_2, out_3, in); 10 | // three output Invertor gate 11 | not u_not0 (out_a, out_b, out_c, in); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/asicworld/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | OPTIND=1 4 | seed="" # default to no seed specified 5 | while getopts "S:" opt 6 | do 7 | case "$opt" in 8 | S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space 9 | seed="SEED=$arg" ;; 10 | esac 11 | done 12 | shift "$((OPTIND-1))" 13 | 14 | exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS+="-e" *.v 15 | -------------------------------------------------------------------------------- /examples/cmos/testbench_digital.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | # iverlog simulation 6 | echo "Doing Verilog simulation with iverilog" 7 | iverilog -o counter_tb counter.v counter_tb.v 8 | ./counter_tb; gtkwave counter_tb.gtkw & 9 | 10 | # yosys synthesis 11 | ../../yosys counter_digital.ys 12 | 13 | # requires ngspice with xspice support enabled: 14 | ngspice testbench_digital.sp 15 | 16 | -------------------------------------------------------------------------------- /examples/smtbmc/.gitignore: -------------------------------------------------------------------------------- 1 | demo1.smt2 2 | demo1.yslog 3 | demo2.smt2 4 | demo2.smtc 5 | demo2.vcd 6 | demo2.yslog 7 | demo2_tb 8 | demo2_tb.v 9 | demo2_tb.vcd 10 | demo3.smt2 11 | demo3.vcd 12 | demo3.yslog 13 | demo4.smt2 14 | demo4.vcd 15 | demo4.yslog 16 | demo5.smt2 17 | demo5.vcd 18 | demo5.yslog 19 | demo6.smt2 20 | demo6.yslog 21 | demo7.smt2 22 | demo7.yslog 23 | demo8.smt2 24 | demo8.yslog 25 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/select.v: -------------------------------------------------------------------------------- 1 | module test(clk, s, a, y); 2 | input clk, s; 3 | input [15:0] a; 4 | output [15:0] y; 5 | reg [15:0] b, c; 6 | 7 | always @(posedge clk) begin 8 | b <= a; 9 | c <= b; 10 | end 11 | 12 | wire [15:0] state_a = (a ^ b) + c; 13 | wire [15:0] state_b = (a ^ b) - c; 14 | assign y = !s ? state_a : state_b; 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/asicworld/code_tidbits_asyn_reset.v: -------------------------------------------------------------------------------- 1 | module asyn_reset(clk,reset,a,c); 2 | input clk; 3 | input reset; 4 | input a; 5 | output c; 6 | 7 | wire clk; 8 | wire reset; 9 | wire a; 10 | reg c; 11 | 12 | always @ (posedge clk or posedge reset) 13 | if ( reset == 1'b1) begin 14 | c <= 0; 15 | end else begin 16 | c <= a; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/simple/forgen01.v: -------------------------------------------------------------------------------- 1 | 2 | // VERIFIC-SKIP 3 | 4 | module uut_forgen01(a, y); 5 | 6 | input [4:0] a; 7 | output y; 8 | 9 | integer i, j; 10 | reg [31:0] lut; 11 | 12 | initial begin 13 | for (i = 0; i < 32; i = i+1) begin 14 | lut[i] = i > 1; 15 | for (j = 2; j*j <= i; j = j+1) 16 | if (i % j == 0) 17 | lut[i] = 0; 18 | end 19 | end 20 | 21 | assign y = lut[a]; 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Intro/mycells.v: -------------------------------------------------------------------------------- 1 | 2 | module NOT(A, Y); 3 | input A; 4 | output Y = ~A; 5 | endmodule 6 | 7 | module NAND(A, B, Y); 8 | input A, B; 9 | output Y = ~(A & B); 10 | endmodule 11 | 12 | module NOR(A, B, Y); 13 | input A, B; 14 | output Y = ~(A | B); 15 | endmodule 16 | 17 | module DFF(C, D, Q); 18 | input C, D; 19 | output reg Q; 20 | always @(posedge C) 21 | Q <= D; 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /tests/sat/expose_dff.ys: -------------------------------------------------------------------------------- 1 | 2 | read_verilog expose_dff.v 3 | hierarchy; proc;; 4 | 5 | expose -shared -evert-dff test1 test2 6 | miter -equiv test1 test2 miter12 7 | flatten miter12; opt miter12 8 | 9 | expose -shared -evert-dff test3 test4 10 | miter -equiv test3 test4 miter34 11 | flatten miter34; opt miter34 12 | 13 | sat -verify -prove trigger 0 miter12 14 | sat -verify -prove trigger 0 miter34 15 | 16 | -------------------------------------------------------------------------------- /tests/simple/constpower.v: -------------------------------------------------------------------------------- 1 | module constpower(ys, yu); 2 | 3 | output [8*8*8-1:0] ys, yu; 4 | 5 | genvar i, j; 6 | 7 | generate 8 | for (i = 0; i < 8; i = i+1) 9 | for (j = 0; j < 8; j = j+1) begin:V 10 | assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4); 11 | assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j); 12 | end 13 | endgenerate 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/tools/autotest.mk: -------------------------------------------------------------------------------- 1 | 2 | # Don't bother defining default values for SEED and EXTRA_FLAGS. 3 | # Their "natural" default values should be sufficient, 4 | # and they may be overridden in the environment. 5 | ifneq ($(strip $(SEED)),) 6 | SEEDOPT=-S$(SEED) 7 | endif 8 | 9 | $(MAKECMDGOALS): 10 | @$(basename $(MAKEFILE_LIST)).sh -G -j $(SEEDOPT) $(EXTRA_FLAGS) $@ 11 | 12 | .PHONY: $(MAKECMDGOALS) 13 | 14 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/mymul_map.v: -------------------------------------------------------------------------------- 1 | module MYMUL(A, B, Y); 2 | parameter WIDTH = 1; 3 | input [WIDTH-1:0] A, B; 4 | output reg [WIDTH-1:0] Y; 5 | 6 | wire [1023:0] _TECHMAP_DO_ = "proc; clean"; 7 | 8 | integer i; 9 | always @* begin 10 | Y = 0; 11 | for (i = 0; i < WIDTH; i=i+1) 12 | if (A[i]) 13 | Y = Y + (B << i); 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/hana/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | OPTIND=1 4 | seed="" # default to no seed specified 5 | while getopts "S:" opt 6 | do 7 | case "$opt" in 8 | S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space 9 | seed="SEED=$arg" ;; 10 | esac 11 | done 12 | shift "$((OPTIND-1))" 13 | 14 | exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS="-l hana_vlib.v -n 300 -e" test_*.v 15 | -------------------------------------------------------------------------------- /tests/opt/opt_lut.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input [8:0] a, 3 | input [8:0] b, 4 | output [8:0] o1, 5 | output [2:0] o2, 6 | input [2:0] c, 7 | input [2:0] d, 8 | output [2:0] o3, 9 | output [2:0] o4, 10 | input s 11 | ); 12 | 13 | assign o1 = (s ? 0 : a + b); 14 | assign o2 = (s ? a : a - b); 15 | assign o3 = (s ? 4'b1111 : d + c); 16 | assign o4 = (s ? d : c - d); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/sva/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TESTS = $(sort $(basename $(wildcard *.sv)) $(basename $(wildcard *.vhd))) 3 | 4 | all: $(addsuffix .ok,$(TESTS)) 5 | 6 | %.ok: 7 | bash runtest.sh $@ 8 | 9 | clean: 10 | rm -rf $(addsuffix .ok,$(TESTS)) $(addsuffix .sby,$(TESTS)) $(TESTS) 11 | rm -rf $(addsuffix _pass.sby,$(TESTS)) $(addsuffix _pass,$(TESTS)) 12 | rm -rf $(addsuffix _fail.sby,$(TESTS)) $(addsuffix _fail,$(TESTS)) 13 | 14 | -------------------------------------------------------------------------------- /examples/aiger/demo.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | yosys -p ' 4 | read_verilog -formal demo.v 5 | prep -flatten -nordff -top demo 6 | write_smt2 -wires demo.smt2 7 | flatten demo; delete -output 8 | memory_map; opt -full 9 | techmap; opt -fast 10 | abc -fast -g AND; opt_clean 11 | write_aiger -map demo.aim demo.aig 12 | ' 13 | super_prove demo.aig > demo.aiw 14 | yosys-smtbmc --dump-vcd demo.vcd --aig demo demo.smt2 15 | -------------------------------------------------------------------------------- /examples/aiger/demo.v: -------------------------------------------------------------------------------- 1 | module demo(input clk, reset, ctrl); 2 | localparam NBITS = 10; 3 | reg [NBITS-1:0] counter; 4 | initial counter[NBITS-2] = 0; 5 | initial counter[0] = 1; 6 | always @(posedge clk) begin 7 | counter <= reset ? 1 : ctrl ? counter + 1 : counter - 1; 8 | assume(counter != 0); 9 | assume(counter != 1 << (NBITS-1)); 10 | assert(counter != (1 << NBITS)-1); 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/example_03.dot: -------------------------------------------------------------------------------- 1 | digraph "example" { 2 | rankdir="LR"; 3 | remincross=true; 4 | v0 [ label="a" ]; 5 | v1 [ label="b" ]; 6 | v2 [ label="$2_Y" ]; 7 | c4 [ shape=record, label="{{ A| B}|$2\n$add|{ Y}}" ]; 8 | v0:e -> c4:p1:w [color="black", label=""]; 9 | v1:e -> c4:p2:w [color="black", label=""]; 10 | c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""]; 11 | } 12 | -------------------------------------------------------------------------------- /passes/tests/flowmap/pack3.v: -------------------------------------------------------------------------------- 1 | // Exact reproduction of Figure 5(a) (bottom) from 10.1109/92.285741. 2 | module top(...); 3 | input a,b,c,d,e,f,g,h,i,j; 4 | wire x = !(a&b); 5 | wire y = !(c|d); 6 | wire z = !(e|f); 7 | wire n0 = !(g&h); 8 | wire n1 = !(i|j); 9 | wire w = !(x&y); 10 | wire n2 = !(z&n0); 11 | wire n3 = !(n0|n1); 12 | wire n4 = !(n2|n3); 13 | wire v = !(w|n5); 14 | output u = !(w&v); 15 | endmodule 16 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/mymul_test.ys: -------------------------------------------------------------------------------- 1 | read_verilog mymul_test.v 2 | hierarchy -check -top test 3 | 4 | techmap -map sym_mul_map.v \ 5 | -map mymul_map.v;; 6 | 7 | rename test test_mapped 8 | read_verilog mymul_test.v 9 | miter -equiv test test_mapped miter 10 | flatten miter 11 | 12 | sat -verify -prove trigger 0 miter 13 | 14 | splitnets -ports test_mapped/A 15 | show -prefix mymul -format pdf -notitle test_mapped 16 | -------------------------------------------------------------------------------- /tests/simple/signedexpr.v: -------------------------------------------------------------------------------- 1 | module signed_test01(a, b, xu, xs, yu, ys, zu, zs); 2 | 3 | input signed [1:0] a; 4 | input signed [2:0] b; 5 | output [3:0] xu, xs; 6 | output [3:0] yu, ys; 7 | output zu, zs; 8 | 9 | assign xu = (a + b) + 3'd0; 10 | assign xs = (a + b) + 3'sd0; 11 | 12 | assign yu = {a + b} + 3'd0; 13 | assign ys = {a + b} + 3'sd0; 14 | 15 | assign zu = a + b != 3'd0; 16 | assign zs = a + b != 3'sd0; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/smv/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | rm -rf temp 6 | mkdir -p temp 7 | 8 | ../../yosys -p 'test_cell -muxdiv -w temp/test all' 9 | rm -f temp/test_{alu,fa,lcu,lut,macc,shiftx}_* 10 | 11 | cat > temp/makefile << "EOT" 12 | all: $(addsuffix .ok,$(basename $(wildcard temp/test_*.il))) 13 | %.ok: %.il 14 | bash run-single.sh $(basename $<) 15 | touch $@ 16 | EOT 17 | 18 | ${MAKE:-make} -f temp/makefile 19 | 20 | -------------------------------------------------------------------------------- /tests/various/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | set -e 3 | for x in *.ys; do 4 | echo "Running $x.." 5 | ../../yosys -ql ${x%.ys}.log $x 6 | done 7 | # Run any .sh files in this directory (with the exception of the file - run-test.sh 8 | shell_tests=$(echo *.sh | sed -e 's/run-test.sh//') 9 | if [ "$shell_tests" ]; then 10 | for s in $shell_tests; do 11 | echo "Running $s.." 12 | bash $s 13 | done 14 | fi 15 | -------------------------------------------------------------------------------- /tests/vloghtb/test_mapopt.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | source common.sh 5 | 6 | f=$1 7 | n=$(basename ${f%.v}) 8 | 9 | mkdir -p log_test_mapopt 10 | rm -f log_test_mapopt/$n.* 11 | 12 | test_equiv mapopt_1 "opt -fine; techmap; opt" "-set-def-inputs" $n $f 13 | test_autotest mapopt_2 "proc; opt; techmap; opt" $n $f 14 | 15 | tail -n20 log_test_mapopt_1/$n.txt log_test_mapopt_2/$n.txt > log_test_mapopt/$n.txt 16 | 17 | exit 0 18 | -------------------------------------------------------------------------------- /examples/anlogic/README: -------------------------------------------------------------------------------- 1 | LED Blink project for Anlogic Lichee Tang board. 2 | 3 | Follow the install instructions for the Tang Dynasty IDE from given link below. 4 | 5 | https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/ 6 | 7 | 8 | set TD_HOME env variable to the full path to the TD as follow. 9 | 10 | export TD_HOME= 11 | 12 | then run "bash build.sh" in this directory. 13 | -------------------------------------------------------------------------------- /tests/opt/opt_lut_elim.il: -------------------------------------------------------------------------------- 1 | module \test 2 | wire input 1 \i 3 | 4 | wire output 2 \o1 5 | cell $lut $1 6 | parameter \LUT 16'0110100110010110 7 | parameter \WIDTH 4 8 | connect \A { \i 3'000 } 9 | connect \Y \o1 10 | end 11 | 12 | wire output 2 \o2 13 | cell $lut $2 14 | parameter \LUT 16'0110100010010110 15 | parameter \WIDTH 4 16 | connect \A { \i 3'000 } 17 | connect \Y \o2 18 | end 19 | end 20 | -------------------------------------------------------------------------------- /examples/smtbmc/demo5.v: -------------------------------------------------------------------------------- 1 | // Demo for $anyconst 2 | 3 | module demo5 (input clk); 4 | wire [7:0] step_size = $anyconst; 5 | reg [7:0] state = 0, count = 0; 6 | reg [31:0] hash = 0; 7 | 8 | always @(posedge clk) begin 9 | count <= count + 1; 10 | hash <= ((hash << 5) + hash) ^ state; 11 | state <= state + step_size; 12 | end 13 | 14 | always @* begin 15 | if (count == 42) 16 | assert(hash == 32'h A18FAC0A); 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /passes/equiv/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/equiv/equiv_make.o 3 | OBJS += passes/equiv/equiv_miter.o 4 | OBJS += passes/equiv/equiv_simple.o 5 | OBJS += passes/equiv/equiv_status.o 6 | OBJS += passes/equiv/equiv_add.o 7 | OBJS += passes/equiv/equiv_remove.o 8 | OBJS += passes/equiv/equiv_induct.o 9 | OBJS += passes/equiv/equiv_struct.o 10 | OBJS += passes/equiv/equiv_purge.o 11 | OBJS += passes/equiv/equiv_mark.o 12 | OBJS += passes/equiv/equiv_opt.o 13 | -------------------------------------------------------------------------------- /tests/sat/asserts.v: -------------------------------------------------------------------------------- 1 | // http://www.reddit.com/r/yosys/comments/1vljks/new_support_for_systemveriloglike_asserts/ 2 | module test(input clk, input rst, output y); 3 | reg [2:0] state; 4 | always @(posedge clk) begin 5 | if (rst || state == 3) begin 6 | state <= 0; 7 | end else begin 8 | assert(state < 3); 9 | state <= state + 1; 10 | end 11 | end 12 | assign y = state[2]; 13 | assert property (y !== 1'b1); 14 | endmodule 15 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/memdemo.v: -------------------------------------------------------------------------------- 1 | module memdemo(clk, d, y); 2 | 3 | input clk; 4 | input [3:0] d; 5 | output reg [3:0] y; 6 | 7 | integer i; 8 | reg [1:0] s1, s2; 9 | reg [3:0] mem [0:3]; 10 | 11 | always @(posedge clk) begin 12 | for (i = 0; i < 4; i = i+1) 13 | mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4]; 14 | { s2, s1 } = d ? { s1, s2 } ^ d : 4'b0; 15 | mem[s1] <= d; 16 | y <= mem[s2]; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /passes/tests/flowmap/pack2p.v: -------------------------------------------------------------------------------- 1 | // Like pack2.v, but results in a simpler network. 2 | module top(...); 3 | (* $flowmap_level=1 *) input a; 4 | (* $flowmap_level=1 *) input b; 5 | (* $flowmap_level=2 *) input c; 6 | (* $flowmap_level=1 *) input d; 7 | (* $flowmap_level=3 *) input e; 8 | (* $flowmap_level=1 *) input f; 9 | wire u = a&b; 10 | wire w = c|d; 11 | wire v = u|w; 12 | wire n0 = w&e; 13 | wire n1 = n0|f; 14 | output n2 = v&n1; 15 | endmodule 16 | -------------------------------------------------------------------------------- /techlibs/common/pmux2mux.v: -------------------------------------------------------------------------------- 1 | module \$pmux (A, B, S, Y); 2 | 3 | wire [1023:0] _TECHMAP_DO_ = "proc; clean"; 4 | 5 | parameter WIDTH = 1; 6 | parameter S_WIDTH = 1; 7 | 8 | input [WIDTH-1:0] A; 9 | input [WIDTH*S_WIDTH-1:0] B; 10 | input [S_WIDTH-1:0] S; 11 | output reg [WIDTH-1:0] Y; 12 | 13 | integer i; 14 | 15 | always @* begin 16 | Y <= A; 17 | for (i = 0; i < S_WIDTH; i=i+1) 18 | if (S[i]) Y <= B[WIDTH*i +: WIDTH]; 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/vloghtb/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | rm -rf Makefile refdat rtl scripts spec 6 | wget -N http://www.clifford.at/yosys/nogit/vloghammer_tb.tar.bz2 7 | tar --strip=1 -xjf vloghammer_tb.tar.bz2 8 | 9 | make clean 10 | rm -rf log_test_* 11 | 12 | ${MAKE:-make} EXIT_ON_ERROR=1 YOSYS_BIN=$PWD/../../yosys YOSYS_SCRIPT="proc;;" check_yosys 13 | ${MAKE:-make} -f test_makefile MODE=share 14 | ${MAKE:-make} -f test_makefile MODE=mapopt 15 | 16 | -------------------------------------------------------------------------------- /tests/opt/opt_ff.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clk, 3 | input rst, 4 | input [2:0] a, 5 | output [1:0] b 6 | ); 7 | reg [2:0] b_reg; 8 | initial begin 9 | b_reg <= 3'b0; 10 | end 11 | 12 | assign b = b_reg[1:0]; 13 | always @(posedge clk or posedge rst) begin 14 | if(rst) begin 15 | b_reg <= 3'b0; 16 | end else begin 17 | b_reg <= a; 18 | end 19 | end 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /tests/opt/opt_lut_port.il: -------------------------------------------------------------------------------- 1 | module $1 2 | wire width 4 input 2 \_0_ 3 | wire output 4 \_1_ 4 | wire input 3 \_2_ 5 | wire output 1 \o 6 | cell $lut \_3_ 7 | parameter \LUT 16'0011000000000011 8 | parameter \WIDTH 4 9 | connect \A { \_0_ [3] \o 2'00 } 10 | connect \Y \_1_ 11 | end 12 | cell $lut \_4_ 13 | parameter \LUT 4'0001 14 | parameter \WIDTH 4 15 | connect \A { 3'000 \_2_ } 16 | connect \Y \o 17 | end 18 | end 19 | -------------------------------------------------------------------------------- /tests/sva/basic03.sv: -------------------------------------------------------------------------------- 1 | module top (input logic clk, input logic selA, selB, QA, QB, output logic Q); 2 | always @(posedge clk) begin 3 | if (selA) Q <= QA; 4 | if (selB) Q <= QB; 5 | end 6 | 7 | check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) ); 8 | check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) ); 9 | `ifndef FAIL 10 | assume_not_11: assume property ( @(posedge clk) !(selA & selB) ); 11 | `endif 12 | endmodule 13 | -------------------------------------------------------------------------------- /backends/simplec/test00_uut.v: -------------------------------------------------------------------------------- 1 | module test(input [31:0] a, b, c, output [31:0] x, y, z, w); 2 | unit_x unit_x_inst (.a(a), .b(b), .c(c), .x(x)); 3 | unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y)); 4 | assign z = a ^ b ^ c, w = z; 5 | endmodule 6 | 7 | module unit_x(input [31:0] a, b, c, output [31:0] x); 8 | assign x = (a & b) | c; 9 | endmodule 10 | 11 | module unit_y(input [31:0] a, b, c, output [31:0] y); 12 | assign y = a & (b | c); 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_good_code.v: -------------------------------------------------------------------------------- 1 | module addbit ( 2 | a, 3 | b, 4 | ci, 5 | sum, 6 | co); 7 | input a; 8 | input b; 9 | input ci; 10 | output sum; 11 | output co; 12 | wire a; 13 | wire b; 14 | wire ci; 15 | wire sum; 16 | wire co; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/sva/basic01.sv: -------------------------------------------------------------------------------- 1 | module top (input logic clock, ctrl); 2 | logic read = 0, write = 0, ready = 0; 3 | 4 | always @(posedge clock) begin 5 | read <= !ctrl; 6 | write <= ctrl; 7 | ready <= write; 8 | end 9 | 10 | a_rw: assert property ( @(posedge clock) !(read && write) ); 11 | `ifdef FAIL 12 | a_wr: assert property ( @(posedge clock) write |-> ready ); 13 | `else 14 | a_wr: assert property ( @(posedge clock) write |=> ready ); 15 | `endif 16 | endmodule 17 | -------------------------------------------------------------------------------- /techlibs/greenpak4/cells_blackbox.v: -------------------------------------------------------------------------------- 1 | module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); 2 | 3 | input wire CE; 4 | input wire CLK; 5 | output reg OUT; 6 | output reg[WIDTH-1:0] POUT; 7 | input wire RST; 8 | input wire UP; 9 | 10 | parameter COUNT_TO = 1; 11 | parameter RESET_MODE = "RISING"; 12 | parameter RESET_TO_MAX = "1"; 13 | parameter HAS_POUT = 0; 14 | parameter HAS_CE = 0; 15 | parameter WIDTH = 8; 16 | parameter DIRECTION = "DOWN"; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /examples/anlogic/demo.v: -------------------------------------------------------------------------------- 1 | module demo ( 2 | input wire CLK_IN, 3 | output wire R_LED 4 | ); 5 | parameter time1 = 30'd12_000_000; 6 | reg led_state; 7 | reg [29:0] count; 8 | 9 | always @(posedge CLK_IN)begin 10 | if(count == time1)begin 11 | count<= 30'd0; 12 | led_state <= ~led_state; 13 | end 14 | else 15 | count <= count + 1'b1; 16 | end 17 | assign R_LED = led_state; 18 | endmodule 19 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/sym_mul_map.v: -------------------------------------------------------------------------------- 1 | module \$mul (A, B, Y); 2 | parameter A_SIGNED = 0; 3 | parameter B_SIGNED = 0; 4 | parameter A_WIDTH = 1; 5 | parameter B_WIDTH = 1; 6 | parameter Y_WIDTH = 1; 7 | 8 | input [A_WIDTH-1:0] A; 9 | input [B_WIDTH-1:0] B; 10 | output [Y_WIDTH-1:0] Y; 11 | 12 | wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH; 13 | 14 | MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) ); 15 | endmodule 16 | -------------------------------------------------------------------------------- /passes/opt/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += passes/opt/opt.o 3 | OBJS += passes/opt/opt_merge.o 4 | OBJS += passes/opt/opt_muxtree.o 5 | OBJS += passes/opt/opt_reduce.o 6 | OBJS += passes/opt/opt_rmdff.o 7 | OBJS += passes/opt/opt_clean.o 8 | OBJS += passes/opt/opt_expr.o 9 | 10 | ifneq ($(SMALL),1) 11 | OBJS += passes/opt/share.o 12 | OBJS += passes/opt/wreduce.o 13 | OBJS += passes/opt/opt_demorgan.o 14 | OBJS += passes/opt/rmports.o 15 | OBJS += passes/opt/opt_lut.o 16 | endif 17 | 18 | -------------------------------------------------------------------------------- /techlibs/coolrunner2/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/coolrunner2/synth_coolrunner2.o 3 | OBJS += techlibs/coolrunner2/coolrunner2_sop.o 4 | 5 | $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v)) 6 | $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v)) 7 | $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/tff_extract.v)) 8 | $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib)) 9 | -------------------------------------------------------------------------------- /techlibs/coolrunner2/cells_latch.v: -------------------------------------------------------------------------------- 1 | module $_DLATCH_P_(input E, input D, output Q); 2 | LDCP _TECHMAP_REPLACE_ ( 3 | .D(D), 4 | .G(E), 5 | .Q(Q), 6 | .PRE(1'b0), 7 | .CLR(1'b0) 8 | ); 9 | endmodule 10 | 11 | module $_DLATCH_N_(input E, input D, output Q); 12 | LDCP_N _TECHMAP_REPLACE_ ( 13 | .D(D), 14 | .G(E), 15 | .Q(Q), 16 | .PRE(1'b0), 17 | .CLR(1'b0) 18 | ); 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_buffer.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_buffer_1_test.v 3 | module f1_test(input in, output out); 4 | assign out = in; 5 | endmodule 6 | 7 | // test_simulation_buffer_2_test.v 8 | module f2_test(input [1:0] in, output [1:0] out); 9 | assign out[0] = in[0]; 10 | assign out[1] = in[1]; 11 | endmodule 12 | 13 | // test_simulation_buffer_3_test.v 14 | module f3_test(input in, output [1:0] out); 15 | assign out[0] = in; 16 | assign out[1] = in; 17 | endmodule 18 | -------------------------------------------------------------------------------- /examples/cmos/counter.ys: -------------------------------------------------------------------------------- 1 | read_verilog counter.v 2 | read_verilog -lib cmos_cells.v 3 | 4 | synth 5 | dfflibmap -liberty cmos_cells.lib 6 | abc -liberty cmos_cells.lib 7 | opt_clean 8 | 9 | stat -liberty cmos_cells.lib 10 | 11 | # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib 12 | # dfflibmap -liberty osu025_stdcells.lib 13 | # abc -liberty osu025_stdcells.lib;; 14 | 15 | write_verilog synth.v 16 | write_spice synth.sp 17 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_half_adder_gates.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : half_adder_gates 3 | // File Name : half_adder_gates.v 4 | // Function : CCITT Serial CRC 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module half_adder_gates(x,y,sum,carry); 8 | input x,y; 9 | output sum,carry; 10 | 11 | and U_carry (carry,x,y); 12 | xor U_sum (sum,x,y); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /examples/smtbmc/demo7.v: -------------------------------------------------------------------------------- 1 | // Demo for memory initialization 2 | 3 | module demo7; 4 | wire [2:0] addr = $anyseq; 5 | reg [15:0] memory [0:7]; 6 | 7 | initial begin 8 | memory[0] = 1331; 9 | memory[1] = 1331 + 1; 10 | memory[2] = 1331 + 2; 11 | memory[3] = 1331 + 4; 12 | memory[4] = 1331 + 8; 13 | memory[5] = 1331 + 16; 14 | memory[6] = 1331 + 32; 15 | memory[7] = 1331 + 64; 16 | end 17 | 18 | assert property (1000 < memory[addr] && memory[addr] < 2000); 19 | endmodule 20 | -------------------------------------------------------------------------------- /passes/tests/flowmap/pack2.v: -------------------------------------------------------------------------------- 1 | // Exact reproduction of Figure 4(a) from 10.1109/92.285741. 2 | module top(...); 3 | (* $flowmap_level=1 *) input a; 4 | (* $flowmap_level=1 *) input b; 5 | (* $flowmap_level=2 *) input c; 6 | (* $flowmap_level=1 *) input d; 7 | (* $flowmap_level=3 *) input e; 8 | (* $flowmap_level=1 *) input f; 9 | wire u = !(a&b); 10 | wire w = !(c|d); 11 | wire v = !(u|w); 12 | wire n0 = !(w&e); 13 | wire n1 = !(n0|f); 14 | output n2 = !(v&n1); 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_decoder.v: -------------------------------------------------------------------------------- 1 | module decoder (in,out); 2 | input [2:0] in; 3 | output [7:0] out; 4 | wire [7:0] out; 5 | assign out = (in == 3'b000 ) ? 8'b0000_0001 : 6 | (in == 3'b001 ) ? 8'b0000_0010 : 7 | (in == 3'b010 ) ? 8'b0000_0100 : 8 | (in == 3'b011 ) ? 8'b0000_1000 : 9 | (in == 3'b100 ) ? 8'b0001_0000 : 10 | (in == 3'b101 ) ? 8'b0010_0000 : 11 | (in == 3'b110 ) ? 8'b0100_0000 : 12 | (in == 3'b111 ) ? 8'b1000_0000 : 8'h00; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /examples/cmos/counter_digital.ys: -------------------------------------------------------------------------------- 1 | 2 | read_verilog counter.v 3 | read_verilog -lib cmos_cells.v 4 | 5 | proc;; memory;; techmap;; 6 | 7 | dfflibmap -liberty cmos_cells.lib 8 | abc -liberty cmos_cells.lib;; 9 | 10 | # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib 11 | # dfflibmap -liberty osu025_stdcells.lib 12 | # abc -liberty osu025_stdcells.lib;; 13 | 14 | write_verilog synth.v 15 | write_spice -neg 0s -pos 1s synth.sp 16 | 17 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: scrambler_p01.pdf scrambler_p02.pdf equiv.log axis_test.log 3 | 4 | scrambler_p01.pdf: scrambler.ys scrambler.v 5 | ../../yosys scrambler.ys 6 | 7 | scrambler_p02.pdf: scrambler_p01.pdf 8 | 9 | equiv.log: equiv.ys 10 | ../../yosys -l equiv.log_new equiv.ys 11 | mv equiv.log_new equiv.log 12 | 13 | axis_test.log: axis_test.ys axis_master.v axis_test.v 14 | ../../yosys -l axis_test.log_new axis_test.ys 15 | mv axis_test.log_new axis_test.log 16 | 17 | -------------------------------------------------------------------------------- /tests/simple/always03.v: -------------------------------------------------------------------------------- 1 | module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3); 2 | 3 | input clock, in1, in2, in3, in4, in5, in6, in7; 4 | output out1, out2, out3; 5 | reg out1, out2, out3; 6 | 7 | always @(posedge clock) begin 8 | out1 = in1; 9 | if (in2) 10 | out1 = !out1; 11 | out2 <= out1; 12 | if (in3) 13 | out2 <= out2; 14 | if (in4) 15 | if (in5) 16 | out3 <= in6; 17 | else 18 | out3 <= in7; 19 | out1 = out1 ^ out2; 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests/vloghtb/test_febe.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | source common.sh 5 | 6 | f=$1 7 | n=$(basename ${f%.v}) 8 | 9 | test_febe vlog1 "synth" ".v" "write_verilog" "read_verilog" "-ignore_div_by_zero" $n $f 10 | test_febe vlog2 "synth -run coarse" ".v" "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f 11 | test_febe blif "synth; splitnets -ports" ".blif" "write_blif" "read_blif" "-ignore_div_by_zero" $n $f 12 | 13 | exit 0 14 | -------------------------------------------------------------------------------- /examples/gowin/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v 4 | $GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW2A55-PBGA484-6 \ 5 | -warning_all -out demo_out.v -rpt demo.rpt -tr demo_tr.html -bit demo.bit 6 | 7 | # post place&route simulation (icarus verilog) 8 | if false; then 9 | iverilog -D POST_IMPL -o testbench -s testbench testbench.v \ 10 | demo_out.v $(yosys-config --datdir/gowin/cells_sim.v) 11 | vvp -N testbench 12 | fi 13 | -------------------------------------------------------------------------------- /manual/CHAPTER_Prog/Makefile: -------------------------------------------------------------------------------- 1 | test: stubnets.so 2 | yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets" 3 | yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets" 4 | yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits" 5 | tail test1.log test2.log test3.log 6 | 7 | stubnets.so: stubnets.cc 8 | yosys-config --exec --cxx --cxxflags --ldflags -o $@ -shared $^ --ldlibs 9 | 10 | clean: 11 | rm -f test1.log test2.log test3.log 12 | rm -f stubnets.so stubnets.d 13 | -------------------------------------------------------------------------------- /passes/sat/example.ys: -------------------------------------------------------------------------------- 1 | 2 | read_verilog example.v 3 | proc; opt_clean 4 | echo on 5 | 6 | sat -set y 1'b1 example001 7 | sat -set y 1'b1 example002 8 | sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 9 | sat -set y 1'b1 -ignore_unknown_cells example004 10 | sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 11 | 12 | sat -prove y 1'b0 -show rst,counter,y -ignore_unknown_cells example004 13 | sat -prove y 1'b0 -tempinduct -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 14 | 15 | -------------------------------------------------------------------------------- /passes/tests/flowmap/flow.v: -------------------------------------------------------------------------------- 1 | // Exact reproduction of Figure 2(a) from 10.1109/43.273754. 2 | module top(...); 3 | input a,b,c,d,e,f; 4 | wire nA = b&c; 5 | wire A = !nA; 6 | wire nB = c|d; 7 | wire B = !nB; 8 | wire nC = e&f; 9 | wire C = !nC; 10 | wire D = A|B; 11 | wire E = a&D; 12 | wire nF = D&C; 13 | wire F = !nF; 14 | wire nG = F|B; 15 | wire G = !nG; 16 | wire H = a&F; 17 | wire I = E|G; 18 | wire J = G&C; 19 | wire np = H&I; 20 | output p = !np; 21 | output q = A|J; 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests/simple/specify.v: -------------------------------------------------------------------------------- 1 | module test_specify; 2 | 3 | specparam a=1; 4 | 5 | specify 6 | endspecify 7 | 8 | specify 9 | (A => B) = ( 1 ) ; 10 | (A- => B) = ( 1,2 ) ; 11 | (A+ => B) = ( 1,2,3 ) ; 12 | (A => B) = ( 13 | 1.1, 2, 3, 14 | 4, 5.5, 6.6 15 | ) ; 16 | (A => B) = ( 17 | 1.1, 2, 3, 18 | 4, 5.5, 6.6 , 19 | 7.7, 8.8, 9, 20 | 10.1, 11, 12 21 | ) ; 22 | specparam b=1; 23 | specparam [1:2] asasa=1; 24 | endspecify 25 | 26 | specify 27 | specparam c=1:2:3; 28 | endspecify 29 | 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /tests/sva/basic05.sv: -------------------------------------------------------------------------------- 1 | module top (input logic clock, ctrl); 2 | logic read, write, ready; 3 | 4 | demo uut ( 5 | .clock(clock), 6 | .ctrl(ctrl) 7 | ); 8 | 9 | assign read = uut.read; 10 | assign write = uut.write; 11 | assign ready = uut.ready; 12 | 13 | a_rw: assert property ( @(posedge clock) !(read && write) ); 14 | `ifdef FAIL 15 | a_wr: assert property ( @(posedge clock) write |-> ready ); 16 | `else 17 | a_wr: assert property ( @(posedge clock) write |=> ready ); 18 | `endif 19 | endmodule 20 | -------------------------------------------------------------------------------- /examples/osu035/Makefile: -------------------------------------------------------------------------------- 1 | 2 | example.edif: example.ys example.v example.constr osu035_stdcells.lib 3 | yosys -l example.yslog -q example.ys 4 | 5 | osu035_stdcells.lib: 6 | rm -f osu035_stdcells.lib.part osu035_stdcells.lib 7 | wget -O osu035_stdcells.lib.part https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/ami035/signalstorm/osu035_stdcells.lib 8 | mv osu035_stdcells.lib.part osu035_stdcells.lib 9 | 10 | clean: 11 | rm -f osu035_stdcells.lib 12 | rm -f example.yslog example.edif 13 | 14 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_comment.v: -------------------------------------------------------------------------------- 1 | /* This is a 2 | Multi line comment 3 | example */ 4 | module addbit ( 5 | a, 6 | b, 7 | ci, 8 | sum, 9 | co); 10 | 11 | // Input Ports Single line comment 12 | input a; 13 | input b; 14 | input ci; 15 | // Output ports 16 | output sum; 17 | output co; 18 | // Data Types 19 | wire a; 20 | wire b; 21 | wire ci; 22 | wire sum; 23 | wire co; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/sumprod_03.dot: -------------------------------------------------------------------------------- 1 | digraph "sumprod" { 2 | rankdir="LR"; 3 | remincross=true; 4 | n1 [ shape=octagon, label="prod", color="black", fontcolor="black" ]; 5 | v0 [ label="$3_Y" ]; 6 | v1 [ label="c" ]; 7 | c5 [ shape=record, label="{{ A| B}|$4\n$mul|{ Y}}" ]; 8 | c5:p4:e -> n1:w [color="black", style="setlinewidth(3)", label=""]; 9 | v0:e -> c5:p2:w [color="black", style="setlinewidth(3)", label=""]; 10 | v1:e -> c5:p3:w [color="black", style="setlinewidth(3)", label=""]; 11 | } 12 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/always03.v: -------------------------------------------------------------------------------- 1 | module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, 2 | out1, out2, out3); 3 | 4 | input clock, in1, in2, in3, in4, in5, in6, in7; 5 | output out1, out2, out3; 6 | reg out1, out2, out3; 7 | 8 | always @(posedge clock) begin 9 | out1 = in1; 10 | if (in2) 11 | out1 = !out1; 12 | out2 <= out1; 13 | if (in3) 14 | out2 <= out2; 15 | if (in4) 16 | if (in5) 17 | out3 <= in6; 18 | else 19 | out3 <= in7; 20 | out1 = out1 ^ out2; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /techlibs/anlogic/drams_map.v: -------------------------------------------------------------------------------- 1 | module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); 2 | parameter [63:0]INIT = 64'bx; 3 | input CLK1; 4 | 5 | input [3:0] A1ADDR; 6 | output [3:0] A1DATA; 7 | 8 | input [3:0] B1ADDR; 9 | input [3:0] B1DATA; 10 | input B1EN; 11 | 12 | EG_LOGIC_DRAM16X4 #( 13 | `include "dram_init_16x4.vh" 14 | ) _TECHMAP_REPLACE_ ( 15 | .di(B1DATA), 16 | .waddr(B1ADDR), 17 | .wclk(CLK1), 18 | .we(B1EN), 19 | .raddr(A1ADDR), 20 | .do(A1DATA) 21 | ); 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_d_ff_gates.v: -------------------------------------------------------------------------------- 1 | module d_ff_gates(d,clk,q,q_bar); 2 | input d,clk; 3 | output q, q_bar; 4 | 5 | wire n1,n2,n3,q_bar_n; 6 | wire cn,dn,n4,n5,n6; 7 | 8 | // First Latch 9 | not (n1,d); 10 | 11 | nand (n2,d,clk); 12 | nand (n3,n1,clk); 13 | 14 | nand (dn,q_bar_n,n2); 15 | nand (q_bar_n,dn,n3); 16 | 17 | // Second Latch 18 | not (cn,clk); 19 | 20 | not (n4,dn); 21 | 22 | nand (n5,dn,cn); 23 | nand (n6,n4,cn); 24 | 25 | nand (q,q_bar,n5); 26 | nand (q_bar,q,n6); 27 | 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /backends/firrtl/test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | 4 | cd ../../ 5 | make 6 | cd backends/firrtl 7 | 8 | ../../yosys -q -p 'prep -nordff; write_firrtl test.fir' $1 9 | 10 | firrtl -i test.fir -o test_out.v -ll Info 11 | 12 | ../../yosys -p " 13 | read_verilog $1 14 | rename Top gold 15 | 16 | read_verilog test_out.v 17 | rename Top gate 18 | 19 | prep 20 | memory_map 21 | miter -equiv -flatten gold gate miter 22 | hierarchy -top miter 23 | 24 | sat -verify -prove trigger 0 -set-init-zero -seq 10 miter 25 | " 26 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/scrambler.ys: -------------------------------------------------------------------------------- 1 | 2 | read_verilog scrambler.v 3 | 4 | hierarchy; proc;; 5 | 6 | cd scrambler 7 | submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d 8 | cd .. 9 | 10 | show -prefix scrambler_p01 -format pdf -notitle scrambler 11 | show -prefix scrambler_p02 -format pdf -notitle xorshift32 12 | 13 | echo on 14 | 15 | cd xorshift32 16 | rename n2 in 17 | rename n1 out 18 | 19 | eval -set in 1 -show out 20 | eval -set in 270369 -show out 21 | 22 | sat -set out 632435482 23 | 24 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_decoder_always.v: -------------------------------------------------------------------------------- 1 | module decoder_always (in,out); 2 | input [2:0] in; 3 | output [7:0] out; 4 | reg [7:0] out; 5 | 6 | always @ (in) 7 | begin 8 | out = 0; 9 | case (in) 10 | 3'b001 : out = 8'b0000_0001; 11 | 3'b010 : out = 8'b0000_0010; 12 | 3'b011 : out = 8'b0000_0100; 13 | 3'b100 : out = 8'b0000_1000; 14 | 3'b101 : out = 8'b0001_0000; 15 | 3'b110 : out = 8'b0100_0000; 16 | 3'b111 : out = 8'b1000_0000; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_addbit.v: -------------------------------------------------------------------------------- 1 | module addbit ( 2 | a , // first input 3 | b , // Second input 4 | ci , // Carry input 5 | sum , // sum output 6 | co // carry output 7 | ); 8 | //Input declaration 9 | input a; 10 | input b; 11 | input ci; 12 | //Ouput declaration 13 | output sum; 14 | output co; 15 | //Port Data types 16 | wire a; 17 | wire b; 18 | wire ci; 19 | wire sum; 20 | wire co; 21 | //Code starts here 22 | assign {co,sum} = a + b + ci; 23 | 24 | endmodule // End of Module addbit 25 | -------------------------------------------------------------------------------- /techlibs/ice40/tests/test_dsp_model.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v 4 | cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v 5 | for tb in testbench \ 6 | testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ 7 | testbench_seq_16x16_A testbench_seq_16x16_B 8 | do 9 | iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v 10 | vvp -N ./test_dsp_model 11 | done 12 | -------------------------------------------------------------------------------- /tests/simple/run-test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | OPTIND=1 4 | seed="" # default to no seed specified 5 | while getopts "S:" opt 6 | do 7 | case "$opt" in 8 | S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space 9 | seed="SEED=$arg" ;; 10 | esac 11 | done 12 | shift "$((OPTIND-1))" 13 | 14 | # check for Icarus Verilog 15 | if ! which iverilog > /dev/null ; then 16 | echo "$0: Error: Icarus Verilog 'iverilog' not found." 17 | exit 1 18 | fi 19 | 20 | exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v 21 | -------------------------------------------------------------------------------- /examples/basys3/README: -------------------------------------------------------------------------------- 1 | 2 | A simple example design, based on the Digilent BASYS3 board 3 | =========================================================== 4 | 5 | This example uses Yosys for synthesis and Xilinx Vivado 6 | for place&route and bit-stream creation. 7 | 8 | Running Yosys: 9 | yosys run_yosys.ys 10 | 11 | Running Vivado: 12 | vivado -nolog -nojournal -mode batch -source run_vivado.tcl 13 | 14 | Programming board: 15 | vivado -nolog -nojournal -mode batch -source run_prog.tcl 16 | 17 | All of the above: 18 | bash run.sh 19 | 20 | -------------------------------------------------------------------------------- /examples/cmos/README: -------------------------------------------------------------------------------- 1 | 2 | In this directory contains an example for generating a spice output using two 3 | different spice modes, normal analog transient simulation and event-driven 4 | digital simulation as supported by ngspice xspice sub-module. 5 | 6 | Each test bench can be run separately by either running: 7 | 8 | - testbench.sh, to start analog simulation or 9 | - testbench_digital.sh for mixed-signal digital simulation. 10 | 11 | The later case also includes pure verilog simulation using the iverilog 12 | and gtkwave for comparison. 13 | 14 | -------------------------------------------------------------------------------- /examples/gowin/README: -------------------------------------------------------------------------------- 1 | Simple test project for Gowinsemi GW2A-55K Eval Board Mini. 2 | 3 | Follow the install instructions for the Gowinsemi tools below, 4 | then run "bash run.sh" in this directory. 5 | 6 | 7 | Install instructions for gowinTool_linux 8 | ---------------------------------------- 9 | 10 | 1.) extract gowinTool_linux.zip 11 | 12 | 2.) set GOWIN_HOME env variable to the full path to the 13 | gowinTool_linux directory 14 | 15 | 3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to 16 | the full path to the license file. 17 | 18 | -------------------------------------------------------------------------------- /examples/smtbmc/demo1.v: -------------------------------------------------------------------------------- 1 | module demo1(input clk, input addtwo, output iseven); 2 | reg [3:0] cnt; 3 | wire [3:0] next_cnt; 4 | 5 | inc inc_inst (addtwo, iseven, cnt, next_cnt); 6 | 7 | always @(posedge clk) 8 | cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt; 9 | 10 | `ifdef FORMAL 11 | assert property (cnt != 15); 12 | initial assume (!cnt[2]); 13 | `endif 14 | endmodule 15 | 16 | module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y); 17 | assign iseven = !a[0]; 18 | assign y = a + (addtwo ? 2 : 1); 19 | endmodule 20 | -------------------------------------------------------------------------------- /tests/sva/basic00.sv: -------------------------------------------------------------------------------- 1 | module top (input clk, reset, antecedent, output reg consequent); 2 | always @(posedge clk) 3 | consequent <= reset ? 0 : antecedent; 4 | 5 | `ifdef FAIL 6 | test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |-> consequent ) 7 | else $error("Failed with consequent = ", $sampled(consequent)); 8 | `else 9 | test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |=> consequent ) 10 | else $error("Failed with consequent = ", $sampled(consequent)); 11 | `endif 12 | endmodule 13 | -------------------------------------------------------------------------------- /tests/techmap/mem_simple_4x1_tb.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg clk, rst; 4 | wire [7:0] out; 5 | wire [4:0] counter; 6 | 7 | uut uut (clk, rst, out, counter); 8 | 9 | initial begin 10 | #5 clk <= 0; 11 | repeat (100) #5 clk <= ~clk; 12 | #5 $finish; 13 | end 14 | 15 | initial begin 16 | rst <= 1; 17 | repeat (2) @(posedge clk); 18 | rst <= 0; 19 | end 20 | 21 | always @(posedge clk) 22 | $display("%d %d %d", rst, out, counter); 23 | 24 | initial begin 25 | $dumpfile("mem_simple_4x1_tb.vcd"); 26 | $dumpvars(0, uut); 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/sat/share.ys: -------------------------------------------------------------------------------- 1 | read_verilog share.v 2 | proc;; 3 | 4 | copy test_1 gold_1 5 | copy test_2 gold_2 6 | share test_1 test_2;; 7 | 8 | select -assert-count 1 test_1/t:$mul 9 | select -assert-count 1 test_2/t:$mul 10 | select -assert-count 1 test_2/t:$div 11 | 12 | miter -equiv -flatten -make_outputs -make_outcmp gold_1 test_1 miter_1 13 | sat -verify -prove trigger 0 -show-inputs -show-outputs miter_1 14 | 15 | miter -equiv -flatten -make_outputs -make_outcmp gold_2 test_2 miter_2 16 | sat -verify -prove trigger 0 -show-inputs -show-outputs miter_2 17 | 18 | -------------------------------------------------------------------------------- /examples/smtbmc/demo3.v: -------------------------------------------------------------------------------- 1 | // Whatever the initial content of this memory is at reset, it will never change 2 | // see demo3.smtc for assumptions and assertions 3 | 4 | module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data); 5 | reg [31:0] mem [0:2**16-1]; 6 | reg [15:0] addr_q; 7 | 8 | always @(posedge clk) begin 9 | if (rst) begin 10 | data <= mem[0] ^ 123456789; 11 | addr_q <= 0; 12 | end else begin 13 | mem[addr_q] <= data ^ 123456789; 14 | data <= mem[addr] ^ 123456789; 15 | addr_q <= addr; 16 | end 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/simple/carryadd.v: -------------------------------------------------------------------------------- 1 | module carryadd(a, b, y); 2 | 3 | parameter WIDTH = 8; 4 | 5 | input [WIDTH-1:0] a, b; 6 | output [WIDTH-1:0] y; 7 | 8 | genvar i; 9 | generate 10 | for (i = 0; i < WIDTH; i = i+1) begin:STAGE 11 | wire IN1 = a[i], IN2 = b[i]; 12 | wire C, Y; 13 | if (i == 0) 14 | assign C = IN1 & IN2, Y = IN1 ^ IN2; 15 | else 16 | assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C), 17 | Y = IN1 ^ IN2 ^ STAGE[i-1].C; 18 | assign y[i] = Y; 19 | end 20 | endgenerate 21 | 22 | // assert property (y == a + b); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_parity_using_bitwise.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : parity_using_bitwise 3 | // File Name : parity_using_bitwise.v 4 | // Function : Parity using bitwise xor 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module parity_using_bitwise ( 8 | data_in , // 8 bit data in 9 | parity_out // 1 bit parity out 10 | ); 11 | output parity_out ; 12 | input [7:0] data_in ; 13 | 14 | assign parity_out = ^data_in; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/basys3/example.v: -------------------------------------------------------------------------------- 1 | module example(CLK, LD); 2 | input CLK; 3 | output [15:0] LD; 4 | 5 | wire clock; 6 | reg [15:0] leds; 7 | 8 | BUFG CLK_BUF (.I(CLK), .O(clock)); 9 | OBUF LD_BUF[15:0] (.I(leds), .O(LD)); 10 | 11 | parameter COUNTBITS = 26; 12 | reg [COUNTBITS-1:0] counter; 13 | 14 | always @(posedge CLK) begin 15 | counter <= counter + 1; 16 | if (counter[COUNTBITS-1]) 17 | leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5]; 18 | else 19 | leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5]; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/Makefile: -------------------------------------------------------------------------------- 1 | 2 | TARGETS += proc_01 proc_02 proc_03 3 | TARGETS += opt_01 opt_02 opt_03 opt_04 4 | TARGETS += memory_01 memory_02 5 | TARGETS += techmap_01 6 | TARGETS += abc_01 7 | 8 | all: $(addsuffix .pdf,$(TARGETS)) 9 | 10 | define make_pdf_template 11 | $(1).pdf: $(1)*.v $(1)*.ys 12 | ../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf' 13 | endef 14 | 15 | $(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg)))) 16 | 17 | clean: 18 | rm -f $(addsuffix .pdf,$(TARGETS)) 19 | rm -f $(addsuffix .dot,$(TARGETS)) 20 | 21 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_mux_2to1_gates.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : mux_2to1_gates 3 | // File Name : mux_2to1_gates.v 4 | // Function : 2:1 Mux using Gate Primitives 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module mux_2to1_gates(a,b,sel,y); 8 | input a,b,sel; 9 | output y; 10 | 11 | wire sel,a_sel,b_sel; 12 | 13 | not U_inv (inv_sel,sel); 14 | and U_anda (asel,a,inv_sel), 15 | U_andb (bsel,b,sel); 16 | or U_or (y,asel,bsel); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /techlibs/ice40/tests/test_bram.v: -------------------------------------------------------------------------------- 1 | module bram #( 2 | parameter ABITS = 8, DBITS = 8, 3 | parameter INIT_ADDR = 0, INIT_DATA = 0 4 | ) ( 5 | input clk, 6 | 7 | input [ABITS-1:0] WR_ADDR, 8 | input [DBITS-1:0] WR_DATA, 9 | input WR_EN, 10 | 11 | input [ABITS-1:0] RD_ADDR, 12 | output reg [DBITS-1:0] RD_DATA 13 | ); 14 | reg [DBITS-1:0] memory [0:2**ABITS-1]; 15 | 16 | initial begin 17 | memory[INIT_ADDR] <= INIT_DATA; 18 | end 19 | 20 | always @(posedge clk) begin 21 | if (WR_EN) memory[WR_ADDR] <= WR_DATA; 22 | RD_DATA <= memory[RD_ADDR]; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/sumprod_04.dot: -------------------------------------------------------------------------------- 1 | digraph "sumprod" { 2 | rankdir="LR"; 3 | remincross=true; 4 | n2 [ shape=octagon, label="c", color="black", fontcolor="black" ]; 5 | n3 [ shape=octagon, label="prod", color="black", fontcolor="black" ]; 6 | c7 [ shape=record, label="{{ A| B}|$4\n$mul|{ Y}}" ]; 7 | n1 [ shape=diamond, label="$3_Y" ]; 8 | n1:e -> c7:p4:w [color="black", style="setlinewidth(3)", label=""]; 9 | n2:e -> c7:p5:w [color="black", style="setlinewidth(3)", label=""]; 10 | c7:p6:e -> n3:w [color="black", style="setlinewidth(3)", label=""]; 11 | } 12 | -------------------------------------------------------------------------------- /manual/appnotes.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR 5 | do 6 | [ -f $job.ok -a $job.ok -nt $job.tex ] && continue 7 | if [ -f $job/make.sh ]; then 8 | cd $job 9 | bash make.sh 10 | cd .. 11 | fi 12 | old_md5=$([ -f $job.aux ] && md5sum < $job.aux || true) 13 | while 14 | pdflatex -shell-escape -halt-on-error $job.tex || exit 15 | new_md5=$(md5sum < $job.aux) 16 | [ "$old_md5" != "$new_md5" ] 17 | do 18 | old_md5="$new_md5" 19 | done 20 | touch $job.ok 21 | done 22 | 23 | -------------------------------------------------------------------------------- /techlibs/ecp5/bram.txt: -------------------------------------------------------------------------------- 1 | bram $__ECP5_DP16KD 2 | init 1 3 | 4 | abits 10 @a10d18 5 | dbits 18 @a10d18 6 | abits 11 @a11d9 7 | dbits 9 @a11d9 8 | abits 12 @a12d4 9 | dbits 4 @a12d4 10 | abits 13 @a13d2 11 | dbits 2 @a13d2 12 | abits 14 @a14d1 13 | dbits 1 @a14d1 14 | 15 | groups 2 16 | ports 1 1 17 | wrmode 1 0 18 | enable 2 1 @a10d18 19 | enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 20 | transp 0 2 21 | clocks 2 3 22 | clkpol 2 3 23 | endbram 24 | 25 | match $__ECP5_DP16KD 26 | min bits 2048 27 | min efficiency 5 28 | shuffle_enable B 29 | endmatch 30 | -------------------------------------------------------------------------------- /tests/various/submod_extract.ys: -------------------------------------------------------------------------------- 1 | read_verilog << EOT 2 | module test(input [7:0] a, b, c, d, output [7:0] x, y, z); 3 | assign x = a + b, y = b + c, z = c + d; 4 | endmodule 5 | EOT 6 | 7 | copy test gold 8 | rename test gate 9 | 10 | submod -name mycell gate/x %ci* 11 | design -copy-to mymap mycell 12 | extract -map %mymap gate 13 | 14 | select -assert-count 3 gold/t:* 15 | select -assert-count 3 gold/t:$add 16 | 17 | select -assert-count 3 gate/t:* 18 | select -assert-count 3 gate/t:mycell 19 | 20 | miter -equiv -flatten gold gate miter 21 | sat -verify -prove trigger 0 miter 22 | -------------------------------------------------------------------------------- /tests/memories/shared_ports.v: -------------------------------------------------------------------------------- 1 | // expect-wr-ports 1 2 | // expect-rd-ports 1 3 | 4 | module test( 5 | input clk, 6 | input wr_en1, wr_en2, wr_en3, 7 | input [3:0] wr_addr1, wr_addr2, wr_addr3, 8 | input [15:0] wr_data, 9 | input [3:0] rd_addr, 10 | output reg [31:0] rd_data 11 | ); 12 | 13 | reg [31:0] mem [0:15]; 14 | 15 | always @(posedge clk) begin 16 | if (wr_en1) 17 | mem[wr_addr1][15:0] <= wr_data; 18 | else if (wr_en2) 19 | mem[wr_addr2][23:8] <= wr_data; 20 | else if (wr_en3) 21 | mem[wr_addr3][31:16] <= wr_data; 22 | rd_data <= mem[rd_addr]; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /examples/intel/MAX10/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, 3 | input wire [15:0] SW ); 4 | 5 | 6 | sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); 7 | sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); 8 | sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); 9 | sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2)); 10 | sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0])); 11 | sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); 12 | sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); 13 | sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/sva/basic04.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity top is 5 | port ( 6 | clock : in std_logic; 7 | ctrl : in std_logic; 8 | x : out std_logic 9 | ); 10 | end entity; 11 | 12 | architecture rtl of top is 13 | signal read : std_logic := '0'; 14 | signal write : std_logic := '0'; 15 | signal ready : std_logic := '0'; 16 | begin 17 | process (clock) begin 18 | if (rising_edge(clock)) then 19 | read <= not ctrl; 20 | write <= ctrl; 21 | ready <= write; 22 | end if; 23 | end process; 24 | 25 | x <= read xor write xor ready; 26 | end architecture; 27 | -------------------------------------------------------------------------------- /examples/cmos/cmos_cells_digital.sp: -------------------------------------------------------------------------------- 1 | 2 | .SUBCKT BUF A Y 3 | .model buffer1 d_buffer 4 | Abuf A Y buffer1 5 | .ENDS NOT 6 | 7 | .SUBCKT NOT A Y 8 | .model not1 d_inverter 9 | Anot A Y not1 10 | .ENDS NOT 11 | 12 | .SUBCKT NAND A B Y 13 | .model nand1 d_nand 14 | Anand [A B] Y nand1 15 | .ENDS NAND 16 | 17 | .SUBCKT NOR A B Y 18 | .model nor1 d_nor 19 | Anand [A B] Y nor1 20 | .ENDS NOR 21 | 22 | .SUBCKT DLATCH E D Q 23 | .model latch1 d_latch 24 | Alatch D E null null Q nQ latch1 25 | .ENDS DLATCH 26 | 27 | .SUBCKT DFF C D Q 28 | .model dff1 d_dff 29 | Adff D C null null Q nQ dff1 30 | .ENDS DFF 31 | 32 | -------------------------------------------------------------------------------- /examples/intel/DE2i-150/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, 3 | input wire [15:0] SW ); 4 | 5 | 6 | sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); 7 | sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); 8 | sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); 9 | sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2)); 10 | sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0])); 11 | sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); 12 | sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); 13 | sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /tests/sva/basic02.sv: -------------------------------------------------------------------------------- 1 | module top (input logic clock, ctrl); 2 | logic read = 0, write = 0, ready = 0; 3 | 4 | always @(posedge clock) begin 5 | read <= !ctrl; 6 | write <= ctrl; 7 | ready <= write; 8 | end 9 | endmodule 10 | 11 | module top_properties (input logic clock, read, write, ready); 12 | a_rw: assert property ( @(posedge clock) !(read && write) ); 13 | `ifdef FAIL 14 | a_wr: assert property ( @(posedge clock) write |-> ready ); 15 | `else 16 | a_wr: assert property ( @(posedge clock) write |=> ready ); 17 | `endif 18 | endmodule 19 | 20 | bind top top_properties properties_inst (.*); 21 | -------------------------------------------------------------------------------- /tests/sva/basic05.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity demo is 5 | port ( 6 | clock : in std_logic; 7 | ctrl : in std_logic; 8 | x : out std_logic 9 | ); 10 | end entity; 11 | 12 | architecture rtl of demo is 13 | signal read : std_logic := '0'; 14 | signal write : std_logic := '0'; 15 | signal ready : std_logic := '0'; 16 | begin 17 | process (clock) begin 18 | if (rising_edge(clock)) then 19 | read <= not ctrl; 20 | write <= ctrl; 21 | ready <= write; 22 | end if; 23 | end process; 24 | 25 | x <= read xor write xor ready; 26 | end architecture; 27 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/equiv.ys: -------------------------------------------------------------------------------- 1 | # read test design 2 | read_verilog ../PRESENTATION_ExSyn/techmap_01.v 3 | hierarchy -top test 4 | 5 | # create two version of the design: test_orig and test_mapped 6 | copy test test_orig 7 | rename test test_mapped 8 | 9 | # apply the techmap only to test_mapped 10 | techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped 11 | 12 | # create a miter circuit to test equivalence 13 | miter -equiv -make_assert -make_outputs test_orig test_mapped miter 14 | flatten miter 15 | 16 | # run equivalence check 17 | sat -verify -prove-asserts -show-inputs -show-outputs miter 18 | -------------------------------------------------------------------------------- /techlibs/xilinx/drams.txt: -------------------------------------------------------------------------------- 1 | 2 | bram $__XILINX_RAM64X1D 3 | init 1 4 | abits 6 5 | dbits 1 6 | groups 2 7 | ports 1 1 8 | wrmode 0 1 9 | enable 0 1 10 | transp 0 0 11 | clocks 0 1 12 | clkpol 0 2 13 | endbram 14 | 15 | bram $__XILINX_RAM128X1D 16 | init 1 17 | abits 7 18 | dbits 1 19 | groups 2 20 | ports 1 1 21 | wrmode 0 1 22 | enable 0 1 23 | transp 0 0 24 | clocks 0 1 25 | clkpol 0 2 26 | endbram 27 | 28 | match $__XILINX_RAM64X1D 29 | make_outreg 30 | or_next_if_better 31 | endmatch 32 | 33 | match $__XILINX_RAM128X1D 34 | make_outreg 35 | endmatch 36 | 37 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_parallel_if.v: -------------------------------------------------------------------------------- 1 | module parallel_if(); 2 | 3 | reg [3:0] counter; 4 | wire clk,reset,enable, up_en, down_en; 5 | 6 | always @ (posedge clk) 7 | // If reset is asserted 8 | if (reset == 1'b0) begin 9 | counter <= 4'b0000; 10 | end else begin 11 | // If counter is enable and up count is mode 12 | if (enable == 1'b1 && up_en == 1'b1) begin 13 | counter <= counter + 1'b1; 14 | end 15 | // If counter is enable and down count is mode 16 | if (enable == 1'b1 && down_en == 1'b1) begin 17 | counter <= counter - 1'b1; 18 | end 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/bram/run-single.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ 4 | -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v 5 | iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ 6 | temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v 7 | temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt 8 | if grep -q ERROR temp/tb_${1}_${2}.txt; then 9 | grep -HC2 ERROR temp/tb_${1}_${2}.txt | head 10 | exit 1 11 | fi 12 | exit 0 13 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_full_adder_gates.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : full_adder_gates 3 | // File Name : full_adder_gates.v 4 | // Function : Full Adder Using Gates 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module full_adder_gates(x,y,z,sum,carry); 8 | input x,y,z; 9 | output sum,carry; 10 | wire and1,and2,and3,sum1; 11 | 12 | and U_and1 (and1,x,y), 13 | U_and2 (and2,x,z), 14 | U_and3 (and3,y,z); 15 | or U_or (carry,and1,and2,and3); 16 | xor U_sum (sum,x,y,z); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/simple/constmuldivmod.v: -------------------------------------------------------------------------------- 1 | module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y); 2 | always @* begin 3 | case (mode) 4 | 0: Y = A / 8'd0; 5 | 1: Y = A % 8'd0; 6 | 2: Y = A * 8'd0; 7 | 8 | 3: Y = A / 8'd1; 9 | 4: Y = A % 8'd1; 10 | 5: Y = A * 8'd1; 11 | 12 | 6: Y = A / 8'd2; 13 | 7: Y = A % 8'd2; 14 | 8: Y = A * 8'd2; 15 | 16 | 9: Y = A / 8'd4; 17 | 10: Y = A % 8'd4; 18 | 11: Y = A * 8'd4; 19 | 20 | 12: Y = A / 8'd8; 21 | 13: Y = A % 8'd8; 22 | 14: Y = A * 8'd8; 23 | 24 | default: Y = 8'd16 * A; 25 | endcase 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /.github/issue_template.md: -------------------------------------------------------------------------------- 1 | ## Steps to reproduce the issue 2 | 3 | *Provide instructions for reproducing the issue. Make sure to include 4 | all necessary source files. (You can simply drag&drop a .zip file into 5 | the issue editor.)* 6 | 7 | ## Expected behavior 8 | 9 | *Please describe the behavior you would have expected from the tool.* 10 | 11 | ## Actual behavior 12 | 13 | *Please describe how the behavior you see differs from the expected behavior.* 14 | 15 | **Important Note:** Nobody will be able to help you and/or fix the issue if you 16 | do not provide sufficient information for reproducing the problem. 17 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/techmap_01_map.v: -------------------------------------------------------------------------------- 1 | module \$add (A, B, Y); 2 | 3 | parameter A_SIGNED = 0; 4 | parameter B_SIGNED = 0; 5 | parameter A_WIDTH = 1; 6 | parameter B_WIDTH = 1; 7 | parameter Y_WIDTH = 1; 8 | 9 | input [A_WIDTH-1:0] A; 10 | input [B_WIDTH-1:0] B; 11 | output [Y_WIDTH-1:0] Y; 12 | 13 | generate 14 | if ((A_WIDTH == 32) && (B_WIDTH == 32)) 15 | begin 16 | wire [16:0] S1 = A[15:0] + B[15:0]; 17 | wire [15:0] S2 = A[31:16] + B[31:16] + S1[16]; 18 | assign Y = {S2[15:0], S1[15:0]}; 19 | end 20 | else 21 | wire _TECHMAP_FAIL_ = 1; 22 | endgenerate 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_nor.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_nor_1_test.v 3 | module f1_test(input [1:0] in, output out); 4 | assign out = ~(in[0] | in[1]); 5 | endmodule 6 | 7 | // test_simulation_nor_2_test.v 8 | module f2_test(input [2:0] in, output out); 9 | assign out = ~(in[0] | in[1] | in[2]); 10 | endmodule 11 | 12 | // test_simulation_nor_3_test.v 13 | module f3_test(input [3:0] in, output out); 14 | assign out = ~(in[0] | in[1] | in[2] | in[3]); 15 | endmodule 16 | 17 | // test_simulation_nor_4_test.v 18 | module f4_test(input [3:0] in, output out); 19 | nor mynor(out, in[0], in[1], in[2], in[3]); 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_xor.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_xor_1_test.v 3 | module f1_test(input [1:0] in, output out); 4 | assign out = (in[0] ^ in[1]); 5 | endmodule 6 | 7 | // test_simulation_xor_2_test.v 8 | module f2_test(input [2:0] in, output out); 9 | assign out = (in[0] ^ in[1] ^ in[2]); 10 | endmodule 11 | 12 | // test_simulation_xor_3_test.v 13 | module f3_test(input [3:0] in, output out); 14 | assign out = (in[0] ^ in[1] ^ in[2] ^ in[3]); 15 | endmodule 16 | 17 | // test_simulation_xor_4_test.v 18 | module f4_test(input [3:0] in, output out); 19 | xor myxor(out, in[0], in[1], in[2], in[3]); 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/sat/share.v: -------------------------------------------------------------------------------- 1 | module test_1( 2 | input [7:0] a, b, c, 3 | input s, x, 4 | output [7:0] y1, y2 5 | ); 6 | wire [7:0] t1, t2; 7 | assign t1 = s ? a*b : 0, t2 = !s ? b*c : 0; 8 | assign y1 = x ? t2 : t1, y2 = x ? t1 : t2; 9 | endmodule 10 | 11 | 12 | module test_2( 13 | input s, 14 | input [7:0] a, b, c, 15 | output reg [7:0] y 16 | ); 17 | always @* begin 18 | y <= 'bx; 19 | if (s) begin 20 | if (a * b > 8) 21 | y <= b / c; 22 | else 23 | y <= c / b; 24 | end else begin 25 | if (b * c > 8) 26 | y <= a / b; 27 | else 28 | y <= b / a; 29 | end 30 | end 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /tests/simple/aes_kexp128.v: -------------------------------------------------------------------------------- 1 | 2 | // test taken from aes_core from iwls2005 3 | 4 | module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3); 5 | 6 | input clk, kld; 7 | input [15:0] key; 8 | output [3:0] wo_0, wo_1, wo_2, wo_3; 9 | reg [3:0] w[3:0]; 10 | 11 | assign wo_0 = w[0]; 12 | assign wo_1 = w[1]; 13 | assign wo_2 = w[2]; 14 | assign wo_3 = w[3]; 15 | 16 | always @(posedge clk) begin 17 | w[0] <= kld ? key[15:12] : w[0]; 18 | w[1] <= kld ? key[11: 8] : w[0]^w[1]; 19 | w[2] <= kld ? key[ 7: 4] : w[0]^w[1]^w[2]; 20 | w[3] <= kld ? key[ 3: 0] : w[0]^w[1]^w[2]^w[3]; 21 | end 22 | 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /tests/simple/realexpr.v: -------------------------------------------------------------------------------- 1 | 2 | module demo_001(y1, y2, y3, y4); 3 | output [7:0] y1, y2, y3, y4; 4 | 5 | localparam [7:0] p1 = 123.45; 6 | localparam real p2 = 123.45; 7 | localparam real p3 = 123; 8 | localparam p4 = 123.45; 9 | 10 | assign y1 = p1 + 0.2; 11 | assign y2 = p2 + 0.2; 12 | assign y3 = p3 + 0.2; 13 | assign y4 = p4 + 0.2; 14 | endmodule 15 | 16 | module demo_002(y0, y1, y2, y3); 17 | output [63:0] y0, y1, y2, y3; 18 | 19 | assign y0 = 1'bx >= (-1 * -1.17); 20 | assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0; 21 | assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0; 22 | assign y3 = 1 ? -1 : 'd0; 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_counter.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : counter 3 | // File Name : counter.v 4 | // Function : 4 bit up counter 5 | // Coder : Deepak 6 | //----------------------------------------------------- 7 | module counter (clk, reset, enable, count); 8 | input clk, reset, enable; 9 | output [3:0] count; 10 | reg [3:0] count; 11 | 12 | always @ (posedge clk) 13 | if (reset == 1'b1) begin 14 | count <= 0; 15 | end else if ( enable == 1'b1) begin 16 | count <= count + 1; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/submod.ys: -------------------------------------------------------------------------------- 1 | read_verilog memdemo.v 2 | proc; opt; memory; opt 3 | 4 | cd memdemo 5 | select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff 6 | select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d 7 | select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d 8 | submod -name scramble @scramble 9 | submod -name outstage @outstage 10 | submod -name selstage @selstage 11 | 12 | cd .. 13 | show -format dot -prefix submod_00 memdemo 14 | show -format dot -prefix submod_01 scramble 15 | show -format dot -prefix submod_02 outstage 16 | show -format dot -prefix submod_03 selstage 17 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/addshift_map.v: -------------------------------------------------------------------------------- 1 | module \$add (A, B, Y); 2 | parameter A_SIGNED = 0; 3 | parameter B_SIGNED = 0; 4 | parameter A_WIDTH = 1; 5 | parameter B_WIDTH = 1; 6 | parameter Y_WIDTH = 1; 7 | 8 | input [A_WIDTH-1:0] A; 9 | input [B_WIDTH-1:0] B; 10 | output [Y_WIDTH-1:0] Y; 11 | 12 | parameter _TECHMAP_BITS_CONNMAP_ = 0; 13 | parameter _TECHMAP_CONNMAP_A_ = 0; 14 | parameter _TECHMAP_CONNMAP_B_ = 0; 15 | 16 | wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH || 17 | _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_; 18 | 19 | assign Y = A << 1; 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_xnor.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_xnor_1_test.v 3 | module f1_test(input [1:0] in, output out); 4 | assign out = ~(in[0] ^ in[1]); 5 | endmodule 6 | 7 | // test_simulation_xnor_2_test.v 8 | module f2_test(input [2:0] in, output out); 9 | assign out = ~(in[0] ^ in[1] ^ in[2]); 10 | endmodule 11 | 12 | // test_simulation_xnor_3_test.v 13 | module f3_test(input [3:0] in, output out); 14 | assign out = ~(in[0] ^ in[1] ^ in[2] ^ in[3]); 15 | endmodule 16 | 17 | // test_simulation_xnor_4_test.v 18 | module f4_test(input [3:0] in, output out); 19 | xnor myxnor(out, in[0], in[1], in[2], in[3]); 20 | endmodule 21 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v: -------------------------------------------------------------------------------- 1 | (* techmap_celltype = "$mul" *) 2 | module mul_swap_ports (A, B, Y); 3 | 4 | parameter A_SIGNED = 0; 5 | parameter B_SIGNED = 0; 6 | parameter A_WIDTH = 1; 7 | parameter B_WIDTH = 1; 8 | parameter Y_WIDTH = 1; 9 | 10 | input [A_WIDTH-1:0] A; 11 | input [B_WIDTH-1:0] B; 12 | output [Y_WIDTH-1:0] Y; 13 | 14 | wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH; 15 | 16 | \$mul #( 17 | .A_SIGNED(B_SIGNED), 18 | .B_SIGNED(A_SIGNED), 19 | .A_WIDTH(B_WIDTH), 20 | .B_WIDTH(A_WIDTH), 21 | .Y_WIDTH(Y_WIDTH) 22 | ) _TECHMAP_REPLACE_ ( 23 | .A(B), 24 | .B(A), 25 | .Y(Y) 26 | ); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /techlibs/ecp5/drams_map.v: -------------------------------------------------------------------------------- 1 | module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); 2 | parameter [63:0] INIT = 64'bx; 3 | parameter CLKPOL2 = 1; 4 | input CLK1; 5 | 6 | input [3:0] A1ADDR; 7 | output [3:0] A1DATA; 8 | 9 | input [3:0] B1ADDR; 10 | input [3:0] B1DATA; 11 | input B1EN; 12 | 13 | localparam WCKMUX = CLKPOL2 ? "WCK" : "INV"; 14 | 15 | TRELLIS_DPR16X4 #( 16 | .INITVAL(INIT), 17 | .WCKMUX(WCKMUX), 18 | .WREMUX("WRE") 19 | ) _TECHMAP_REPLACE_ ( 20 | .RAD(A1ADDR), 21 | .DO(A1DATA), 22 | 23 | .WAD(B1ADDR), 24 | .DI(B1DATA), 25 | .WCK(CLK1), 26 | .WRE(B1EN) 27 | ); 28 | endmodule 29 | -------------------------------------------------------------------------------- /tests/sat/asserts_seq.ys: -------------------------------------------------------------------------------- 1 | read_verilog -sv asserts_seq.v 2 | hierarchy; proc; opt 3 | 4 | sat -verify -prove-asserts -tempinduct -seq 1 test_001 5 | sat -falsify -prove-asserts -tempinduct -seq 1 test_002 6 | sat -falsify -prove-asserts -tempinduct -seq 1 test_003 7 | sat -falsify -prove-asserts -tempinduct -seq 1 test_004 8 | sat -verify -prove-asserts -tempinduct -seq 1 test_005 9 | 10 | sat -verify -prove-asserts -seq 2 test_001 11 | sat -falsify -prove-asserts -seq 2 test_002 12 | sat -falsify -prove-asserts -seq 2 test_003 13 | sat -falsify -prove-asserts -seq 2 test_004 14 | sat -verify -prove-asserts -seq 2 test_005 15 | 16 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Prog/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: test0.log test1.log test2.log 3 | 4 | my_cmd.so: my_cmd.cc 5 | ../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs 6 | 7 | test0.log: my_cmd.so 8 | ../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v 9 | mv test0.log_new test0.log 10 | 11 | test1.log: my_cmd.so 12 | ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v 13 | mv test1.log_new test1.log 14 | 15 | test2.log: my_cmd.so 16 | ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v 17 | mv test2.log_new test2.log 18 | 19 | -------------------------------------------------------------------------------- /tests/smv/run-single.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cat > $1.tpl < $1.ys <> $1.log 32 | grep "^-- invariant .* is true" $1.log 33 | 34 | -------------------------------------------------------------------------------- /examples/cxx-api/demomain.cc: -------------------------------------------------------------------------------- 1 | // Note: Set ENABLE_LIBYOSYS=1 in Makefile or Makefile.conf to build libyosys.so 2 | // yosys-config --exec --cxx -o demomain --cxxflags --ldflags demomain.cc -lyosys -lstdc++ 3 | 4 | #include 5 | 6 | int main() 7 | { 8 | Yosys::log_streams.push_back(&std::cout); 9 | Yosys::log_error_stderr = true; 10 | 11 | Yosys::yosys_setup(); 12 | Yosys::yosys_banner(); 13 | 14 | Yosys::run_pass("read_verilog example.v"); 15 | Yosys::run_pass("synth -noabc"); 16 | Yosys::run_pass("clean -purge"); 17 | Yosys::run_pass("write_blif example.blif"); 18 | 19 | Yosys::yosys_shutdown(); 20 | return 0; 21 | } 22 | 23 | -------------------------------------------------------------------------------- /techlibs/common/adff2dff.v: -------------------------------------------------------------------------------- 1 | (* techmap_celltype = "$adff" *) 2 | module adff2dff (CLK, ARST, D, Q); 3 | parameter WIDTH = 1; 4 | parameter CLK_POLARITY = 1; 5 | parameter ARST_POLARITY = 1; 6 | parameter ARST_VALUE = 0; 7 | 8 | input CLK, ARST; 9 | input [WIDTH-1:0] D; 10 | output reg [WIDTH-1:0] Q; 11 | wire reg [WIDTH-1:0] NEXT_Q; 12 | 13 | wire [1023:0] _TECHMAP_DO_ = "proc;;"; 14 | 15 | always @* 16 | if (ARST == ARST_POLARITY) 17 | NEXT_Q <= ARST_VALUE; 18 | else 19 | NEXT_Q <= D; 20 | 21 | if (CLK_POLARITY) 22 | always @(posedge CLK) 23 | Q <= NEXT_Q; 24 | else 25 | always @(negedge CLK) 26 | Q <= NEXT_Q; 27 | endmodule 28 | -------------------------------------------------------------------------------- /tests/simple/forgen02.v: -------------------------------------------------------------------------------- 1 | module uut_forgen02(a, b, cin, y, cout); 2 | 3 | parameter WIDTH = 8; 4 | 5 | input [WIDTH-1:0] a, b; 6 | input cin; 7 | 8 | output [WIDTH-1:0] y; 9 | output cout; 10 | 11 | genvar i; 12 | wire [WIDTH-1:0] carry; 13 | 14 | generate 15 | for (i = 0; i < WIDTH; i=i+1) begin:adder 16 | wire [2:0] D; 17 | assign D[1:0] = { a[i], b[i] }; 18 | if (i == 0) begin:chain 19 | assign D[2] = cin; 20 | end else begin:chain 21 | assign D[2] = carry[i-1]; 22 | end 23 | assign y[i] = ^D; 24 | assign carry[i] = &D[1:0] | (^D[1:0] & D[2]); 25 | end 26 | endgenerate 27 | 28 | assign cout = carry[WIDTH-1]; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_v2k_reg.v: -------------------------------------------------------------------------------- 1 | module v2k_reg(); 2 | 3 | // v2k allows to init variables 4 | reg a = 0; 5 | // Here only last variable is set to 0, i.e d = 0 6 | // Rest b, c are set to x 7 | reg b, c, d = 0; 8 | // reg data type can be signed in v2k 9 | // We can assign with signed constants 10 | reg signed [7:0] data = 8'shF0; 11 | 12 | // Function can return signed values 13 | // Its ports can contain signed ports 14 | function signed [7:0] adder; 15 | input a_in; 16 | input b_in; 17 | input c_in; 18 | input signed [7:0] data_in; 19 | begin 20 | adder = a_in + b_in + c_in + data_in; 21 | end 22 | endfunction 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /frontends/verific/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += frontends/verific/verific.o 3 | 4 | ifeq ($(ENABLE_VERIFIC),1) 5 | 6 | OBJS += frontends/verific/verificsva.o 7 | 8 | EXTRA_TARGETS += share/verific 9 | 10 | share/verific: 11 | $(P) rm -rf share/verific.new 12 | $(Q) mkdir -p share/verific.new 13 | $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987 14 | $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993 15 | $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008 16 | $(Q) chmod -R a+rX share/verific.new 17 | $(Q) mv share/verific.new share/verific 18 | 19 | endif 20 | 21 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/forgen02.v: -------------------------------------------------------------------------------- 1 | module uut_forgen02(a, b, cin, y, cout); 2 | 3 | parameter WIDTH = 8; 4 | 5 | input [WIDTH-1:0] a, b; 6 | input cin; 7 | 8 | output [WIDTH-1:0] y; 9 | output cout; 10 | 11 | genvar i; 12 | wire [WIDTH-1:0] carry; 13 | 14 | generate 15 | for (i = 0; i < WIDTH; i=i+1) begin:adder 16 | wire [2:0] D; 17 | assign D[1:0] = { a[i], b[i] }; 18 | if (i == 0) begin:chain 19 | assign D[2] = cin; 20 | end else begin:chain 21 | assign D[2] = carry[i-1]; 22 | end 23 | assign y[i] = ^D; 24 | assign carry[i] = &D[1:0] | (^D[1:0] & D[2]); 25 | end 26 | endgenerate 27 | 28 | assign cout = carry[WIDTH-1]; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /tests/asicworld/code_verilog_tutorial_explicit.v: -------------------------------------------------------------------------------- 1 | module explicit(); 2 | reg clk,d,rst,pre; 3 | wire q; 4 | 5 | // Here q_bar is not connected 6 | // We can connect ports in any order 7 | dff u0 ( 8 | .q (q), 9 | .d (d), 10 | .clk (clk), 11 | .q_bar (), 12 | .rst (rst), 13 | .pre (pre) 14 | ); 15 | 16 | endmodule 17 | 18 | // D fli-flop 19 | module dff (q, q_bar, clk, d, rst, pre); 20 | input clk, d, rst, pre; 21 | output q, q_bar; 22 | reg q; 23 | 24 | assign q_bar = ~q; 25 | 26 | always @ (posedge clk) 27 | if (rst == 1'b1) begin 28 | q <= 0; 29 | end else if (pre == 1'b1) begin 30 | q <= 1; 31 | end else begin 32 | q <= d; 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /tests/sva/sva_not.sv: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, 3 | input reset, 4 | input ping, 5 | input [1:0] cfg, 6 | output reg pong 7 | ); 8 | reg [2:0] cnt; 9 | localparam integer maxdelay = 8; 10 | 11 | always @(posedge clk) begin 12 | if (reset) begin 13 | cnt <= 0; 14 | pong <= 0; 15 | end else begin 16 | cnt <= cnt - |cnt; 17 | pong <= cnt == 1; 18 | if (ping) cnt <= 4 + cfg; 19 | end 20 | end 21 | 22 | assert property ( 23 | @(posedge clk) 24 | disable iff (reset) 25 | not (ping ##1 !pong [*maxdelay]) 26 | ); 27 | 28 | `ifndef FAIL 29 | assume property ( 30 | @(posedge clk) 31 | not (cnt && ping) 32 | ); 33 | `endif 34 | endmodule 35 | -------------------------------------------------------------------------------- /manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch: -------------------------------------------------------------------------------- 1 | --- ./elab_net.cc.orig 2012-10-27 22:11:05.345688820 +0200 2 | +++ ./elab_net.cc 2012-10-27 22:12:23.398075860 +0200 3 | @@ -29,6 +29,7 @@ 4 | 5 | # include 6 | # include 7 | +# include 8 | 9 | /* 10 | * This is a state flag that determines whether an elaborate_net must 11 | --- ./syn-rules.y.orig 2012-10-27 22:25:38.890020489 +0200 12 | +++ ./syn-rules.y 2012-10-27 22:25:49.146071350 +0200 13 | @@ -25,6 +25,7 @@ 14 | # include "config.h" 15 | 16 | # include 17 | +# include 18 | 19 | /* 20 | * This file implements synthesis based on matching threads and 21 | -------------------------------------------------------------------------------- /techlibs/coolrunner2/tff_extract.v: -------------------------------------------------------------------------------- 1 | module FTCP (C, PRE, CLR, T, Q); 2 | input C, PRE, CLR, T; 3 | output wire Q; 4 | 5 | wire xorout; 6 | 7 | $_XOR_ xorgate ( 8 | .A(T), 9 | .B(Q), 10 | .Y(xorout), 11 | ); 12 | 13 | $_DFFSR_PPP_ dff ( 14 | .C(C), 15 | .D(xorout), 16 | .Q(Q), 17 | .S(PRE), 18 | .R(CLR), 19 | ); 20 | endmodule 21 | 22 | module FTCP_N (C, PRE, CLR, T, Q); 23 | input C, PRE, CLR, T; 24 | output wire Q; 25 | 26 | wire xorout; 27 | 28 | $_XOR_ xorgate ( 29 | .A(T), 30 | .B(Q), 31 | .Y(xorout), 32 | ); 33 | 34 | $_DFFSR_NPP_ dff ( 35 | .C(C), 36 | .D(xorout), 37 | .Q(Q), 38 | .S(PRE), 39 | .R(CLR), 40 | ); 41 | endmodule 42 | -------------------------------------------------------------------------------- /tests/sat/counters.v: -------------------------------------------------------------------------------- 1 | 2 | module counter1(clk, rst, ping); 3 | input clk, rst; 4 | output ping; 5 | reg [31:0] count; 6 | 7 | always @(posedge clk) begin 8 | if (rst) 9 | count <= 0; 10 | else 11 | count <= count + 1; 12 | end 13 | 14 | assign ping = &count; 15 | endmodule 16 | 17 | module counter2(clk, rst, ping); 18 | input clk, rst; 19 | output ping; 20 | reg [31:0] count; 21 | 22 | integer i; 23 | reg carry; 24 | 25 | always @(posedge clk) begin 26 | carry = 1; 27 | for (i = 0; i < 32; i = i+1) begin 28 | count[i] <= !rst & (count[i] ^ carry); 29 | carry = count[i] & carry; 30 | end 31 | end 32 | 33 | assign ping = &count; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /techlibs/intel/common/brams.txt: -------------------------------------------------------------------------------- 1 | bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL 2 | init 1 3 | abits 13 @M1 4 | dbits 1 @M1 5 | abits 12 @M2 6 | dbits 2 @M2 7 | abits 11 @M3 8 | dbits 4 @M3 9 | abits 10 @M4 10 | dbits 8 @M4 11 | abits 10 @M5 12 | dbits 9 @M5 13 | abits 9 @M6 14 | dbits 16 @M6 15 | abits 9 @M7 16 | dbits 18 @M7 17 | abits 8 @M8 18 | dbits 32 @M8 19 | abits 8 @M9 20 | dbits 36 @M9 21 | groups 2 22 | ports 1 1 23 | wrmode 0 1 24 | enable 1 1 25 | transp 0 0 26 | clocks 2 3 27 | clkpol 2 3 28 | endbram 29 | 30 | match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL 31 | min efficiency 2 32 | make_transp 33 | endmatch 34 | -------------------------------------------------------------------------------- /tests/simple/hierarchy.v: -------------------------------------------------------------------------------- 1 | 2 | (* top *) 3 | module top(a, b, y1, y2, y3, y4); 4 | input [3:0] a; 5 | input signed [3:0] b; 6 | output [7:0] y1, y2, y3, y4; 7 | 8 | // this version triggers a bug in Icarus Verilog 9 | // submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4); 10 | 11 | // this version is handled correctly by Icarus Verilog 12 | submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4); 13 | 14 | endmodule 15 | 16 | (* gentb_skip *) 17 | module submod(a, b, y1, y2, y3, y4); 18 | parameter c = 0; 19 | parameter [7:0] d = 0; 20 | input [3:0] a, b; 21 | output [7:0] y1, y2, y3, y4; 22 | assign y1 = a; 23 | assign y2 = b; 24 | assign y3 = c; 25 | assign y4 = d; 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_full_subtracter_gates.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : full_subtracter_gates 3 | // File Name : full_subtracter_gates.v 4 | // Function : Full Subtracter Using Gates 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module full_subtracter_gates(x,y,z,difference,borrow); 8 | input x,y,z; 9 | output difference,borrow; 10 | 11 | wire inv_x,borrow1,borrow2,borrow3; 12 | 13 | not (inv_x,x); 14 | and U_borrow1 (borrow1,inv_x,y), 15 | U_borrow2 (borrow2,inv_x,z), 16 | U_borrow3 (borrow3,y,z); 17 | 18 | xor U_diff (difference,borrow1,borrow2,borrows); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /examples/cmos/testbench_digital.sp: -------------------------------------------------------------------------------- 1 | 2 | * load design and library 3 | .include cmos_cells_digital.sp 4 | .include synth.sp 5 | 6 | * input signals 7 | Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) 8 | Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40) 9 | Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8) 10 | 11 | Xuut dclk drst den dout0 dout1 dout2 counter 12 | * Bridge to digital 13 | .model adc_buff adc_bridge(in_low = 0.8 in_high=2) 14 | .model dac_buff dac_bridge(out_high = 3.5) 15 | Aad [clk rst en] [dclk drst den] adc_buff 16 | Ada [dout0 dout1 dout2] [out0 out1 out2] dac_buff 17 | 18 | 19 | .tran 0.01 50 20 | 21 | .control 22 | run 23 | plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30 24 | .endc 25 | 26 | .end 27 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_decoder_using_assign.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : decoder_using_assign 3 | // File Name : decoder_using_assign.v 4 | // Function : decoder using assign 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module decoder_using_assign ( 8 | binary_in , // 4 bit binary input 9 | decoder_out , // 16-bit out 10 | enable // Enable for the decoder 11 | ); 12 | input [3:0] binary_in ; 13 | input enable ; 14 | output [15:0] decoder_out ; 15 | 16 | wire [15:0] decoder_out ; 17 | 18 | assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /examples/intel/MAX10/sevenseg.v: -------------------------------------------------------------------------------- 1 | module sevenseg ( output reg [6:0] HEX0, 2 | input [3:0] SW ); 3 | 4 | always @(*) begin 5 | case(SW) 6 | 4'h1: HEX0 = 7'b1111001; 7 | 4'h2: HEX0 = 7'b0100100; 8 | 4'h3: HEX0 = 7'b0110000; 9 | 4'h4: HEX0 = 7'b0011001; 10 | 4'h5: HEX0 = 7'b0010010; 11 | 4'h6: HEX0 = 7'b0000010; 12 | 4'h7: HEX0 = 7'b1111000; 13 | 4'h8: HEX0 = 7'b0000000; 14 | 4'h9: HEX0 = 7'b0011000; 15 | 4'ha: HEX0 = 7'b0001000; 16 | 4'hb: HEX0 = 7'b0000011; 17 | 4'hc: HEX0 = 7'b1000110; 18 | 4'hd: HEX0 = 7'b0100001; 19 | 4'he: HEX0 = 7'b0000110; 20 | 4'hf: HEX0 = 7'b0001110; 21 | 4'h0: HEX0 = 7'b1000000; 22 | endcase // case (SW) 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/abc_01_cells.v: -------------------------------------------------------------------------------- 1 | 2 | module BUF(A, Y); 3 | input A; 4 | output Y = A; 5 | endmodule 6 | 7 | module NOT(A, Y); 8 | input A; 9 | output Y = ~A; 10 | endmodule 11 | 12 | module NAND(A, B, Y); 13 | input A, B; 14 | output Y = ~(A & B); 15 | endmodule 16 | 17 | module NOR(A, B, Y); 18 | input A, B; 19 | output Y = ~(A | B); 20 | endmodule 21 | 22 | module DFF(C, D, Q); 23 | input C, D; 24 | output reg Q; 25 | always @(posedge C) 26 | Q <= D; 27 | endmodule 28 | 29 | module DFFSR(C, D, Q, S, R); 30 | input C, D, S, R; 31 | output reg Q; 32 | always @(posedge C, posedge S, posedge R) 33 | if (S) 34 | Q <= 1'b1; 35 | else if (R) 36 | Q <= 1'b0; 37 | else 38 | Q <= D; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /manual/PRESENTATION_Intro/counter.ys: -------------------------------------------------------------------------------- 1 | # read design 2 | read_verilog counter.v 3 | hierarchy -check -top counter 4 | 5 | show -notitle -stretch -format pdf -prefix counter_00 6 | 7 | # the high-level stuff 8 | proc; opt; memory; opt; fsm; opt 9 | 10 | show -notitle -stretch -format pdf -prefix counter_01 11 | 12 | # mapping to internal cell library 13 | techmap; opt 14 | 15 | splitnets -ports;; 16 | show -notitle -stretch -format pdf -prefix counter_02 17 | 18 | # mapping flip-flops to mycells.lib 19 | dfflibmap -liberty mycells.lib 20 | 21 | # mapping logic to mycells.lib 22 | abc -liberty mycells.lib 23 | 24 | # cleanup 25 | clean 26 | 27 | show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03 28 | -------------------------------------------------------------------------------- /techlibs/anlogic/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/anlogic/synth_anlogic.o 3 | OBJS += techlibs/anlogic/anlogic_eqn.o 4 | OBJS += techlibs/anlogic/anlogic_determine_init.o 5 | 6 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) 7 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) 8 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) 9 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) 10 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) 11 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) 12 | $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh)) 13 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.d 3 | .*.swp 4 | *.gch 5 | *.gcda 6 | *.gcno 7 | /.cproject 8 | /.project 9 | /.settings 10 | /qtcreator.files 11 | /qtcreator.includes 12 | /qtcreator.config 13 | /qtcreator.creator 14 | /qtcreator.creator.user 15 | /coverage.info 16 | /coverage_html 17 | /Makefile.conf 18 | /abc 19 | /viz.js 20 | /yosys 21 | /yosys.exe 22 | /yosys.js 23 | /yosys-abc 24 | /yosys-abc.exe 25 | /yosys-config 26 | /yosys-smtbmc 27 | /yosys-smtbmc.exe 28 | /yosys-smtbmc-script.py 29 | /yosys-filterlib 30 | /yosys-filterlib.exe 31 | /kernel/version_*.cc 32 | /share 33 | /yosys-win32-mxebin-* 34 | /yosys-win32-vcxsrc-* 35 | /yosysjs-* 36 | /libyosys.so 37 | /tests/unit/bintest/ 38 | /tests/unit/objtest/ 39 | /tests/ystests 40 | -------------------------------------------------------------------------------- /examples/intel/DE2i-150/sevenseg.v: -------------------------------------------------------------------------------- 1 | module sevenseg ( output reg [6:0] HEX0, 2 | input [3:0] SW ); 3 | 4 | always @(*) begin 5 | case(SW) 6 | 4'h1: HEX0 = 7'b1111001; 7 | 4'h2: HEX0 = 7'b0100100; 8 | 4'h3: HEX0 = 7'b0110000; 9 | 4'h4: HEX0 = 7'b0011001; 10 | 4'h5: HEX0 = 7'b0010010; 11 | 4'h6: HEX0 = 7'b0000010; 12 | 4'h7: HEX0 = 7'b1111000; 13 | 4'h8: HEX0 = 7'b0000000; 14 | 4'h9: HEX0 = 7'b0011000; 15 | 4'ha: HEX0 = 7'b0001000; 16 | 4'hb: HEX0 = 7'b0000011; 17 | 4'hc: HEX0 = 7'b1000110; 18 | 4'hd: HEX0 = 7'b0100001; 19 | 4'he: HEX0 = 7'b0000110; 20 | 4'hf: HEX0 = 7'b0001110; 21 | 4'h0: HEX0 = 7'b1000000; 22 | endcase // case (SW) 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /examples/cmos/counter_tb.v: -------------------------------------------------------------------------------- 1 | module counter_tb; 2 | 3 | /* Make a reset pulse and specify dump file */ 4 | reg reset = 0; 5 | initial begin 6 | $dumpfile("counter_tb.vcd"); 7 | $dumpvars(0,counter_tb); 8 | 9 | # 0 reset = 1; 10 | # 4 reset = 0; 11 | # 36 reset = 1; 12 | # 4 reset = 0; 13 | # 6 $finish; 14 | end 15 | 16 | /* Make enable with period of 8 and 6,7 low */ 17 | reg en = 1; 18 | always begin 19 | en = 1; 20 | #6; 21 | en = 0; 22 | #2; 23 | end 24 | 25 | /* Make a regular pulsing clock. */ 26 | reg clk = 0; 27 | always #1 clk = !clk; 28 | 29 | /* UUT */ 30 | wire [2:0] count; 31 | counter c1 (clk, reset, en, count); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /tests/memories/implicit_en.v: -------------------------------------------------------------------------------- 1 | // expect-wr-ports 1 2 | // expect-rd-ports 1 3 | 4 | module test(clk, rd_addr, rd_data, wr_addr, wr_en, wr_data); 5 | 6 | input clk; 7 | 8 | input [3:0] rd_addr; 9 | output reg [31:0] rd_data; 10 | 11 | input [3:0] wr_addr, wr_en; 12 | input [31:0] wr_data; 13 | 14 | reg [31:0] mem [0:15]; 15 | 16 | always @(posedge clk) begin 17 | mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[wr_addr][ 7: 0]; 18 | mem[wr_addr][15: 8] <= wr_en[1] ? wr_data[15: 8] : mem[wr_addr][15: 8]; 19 | mem[wr_addr][23:16] <= wr_en[2] ? wr_data[23:16] : mem[wr_addr][23:16]; 20 | mem[wr_addr][31:24] <= wr_en[3] ? wr_data[31:24] : mem[wr_addr][31:24]; 21 | rd_data <= mem[rd_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /examples/cmos/testbench.sp: -------------------------------------------------------------------------------- 1 | 2 | * supply voltages 3 | .global Vss Vdd 4 | Vss Vss 0 DC 0 5 | Vdd Vdd 0 DC 3 6 | 7 | * simple transistor model 8 | .MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 9 | .MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 10 | 11 | * load design and library 12 | .include cmos_cells.sp 13 | .include synth.sp 14 | 15 | * input signals 16 | Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) 17 | Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40) 18 | Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8) 19 | 20 | Xuut clk rst en out0 out1 out2 COUNTER 21 | 22 | .tran 0.01 50 23 | 24 | .control 25 | run 26 | plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30 27 | .endc 28 | 29 | .end 30 | -------------------------------------------------------------------------------- /examples/intel/asicworld_lfsr/lfsr_updown_tb.v: -------------------------------------------------------------------------------- 1 | module tb(); 2 | reg clk; 3 | reg reset; 4 | reg enable; 5 | reg up_down; 6 | 7 | wire [7 : 0] count; 8 | wire overflow; 9 | 10 | initial begin 11 | $monitor("rst %b en %b updown %b cnt %b overflow %b", 12 | reset,enable,up_down,count, overflow); 13 | clk = 0; 14 | reset = 1; 15 | enable = 0; 16 | up_down = 0; 17 | #10 reset = 0; 18 | #1 enable = 1; 19 | #20 up_down = 1; 20 | #30 $finish; 21 | end 22 | 23 | always #1 clk = ~clk; 24 | 25 | lfsr_updown U( 26 | .clk ( clk ), 27 | .reset ( reset ), 28 | .enable ( enable ), 29 | .up_down ( up_down ), 30 | .count ( count ), 31 | .overflow ( overflow ) 32 | ); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /techlibs/ice40/brams.txt: -------------------------------------------------------------------------------- 1 | bram $__ICE40_RAM4K_M0 2 | init 1 3 | abits 8 4 | dbits 16 5 | groups 2 6 | ports 1 1 7 | wrmode 0 1 8 | enable 1 16 9 | transp 0 0 10 | clocks 2 3 11 | clkpol 2 3 12 | endbram 13 | 14 | bram $__ICE40_RAM4K_M123 15 | init 1 16 | abits 9 @M1 17 | dbits 8 @M1 18 | abits 10 @M2 19 | dbits 4 @M2 20 | abits 11 @M3 21 | dbits 2 @M3 22 | groups 2 23 | ports 1 1 24 | wrmode 0 1 25 | enable 1 1 26 | transp 0 0 27 | clocks 2 3 28 | clkpol 2 3 29 | endbram 30 | 31 | match $__ICE40_RAM4K_M0 32 | min efficiency 2 33 | make_transp 34 | or_next_if_better 35 | endmatch 36 | 37 | match $__ICE40_RAM4K_M123 38 | min efficiency 2 39 | make_transp 40 | endmatch 41 | -------------------------------------------------------------------------------- /techlibs/ice40/brams_init.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | def write_init_vh(filename, initbits): 4 | with open(filename, "w") as f: 5 | for i in range(16): 6 | print("localparam [255:0] INIT_%X = {" % i, file=f) 7 | for k in range(32): 8 | print(" %s%s" % (", ".join(["INIT[%4d]" % initbits[i*256 + 255 - k*8 - l] for l in range(8)]), "," if k != 31 else ""), file=f) 9 | print("};", file=f); 10 | 11 | write_init_vh("techlibs/ice40/brams_init1.vh", [i//2 + 2048*(i%2) for i in range(4096)]) 12 | write_init_vh("techlibs/ice40/brams_init2.vh", [i//4 + 1024*(i%4) for i in range(4096)]) 13 | write_init_vh("techlibs/ice40/brams_init3.vh", [i//8 + 512*(i%8) for i in range(4096)]) 14 | 15 | -------------------------------------------------------------------------------- /backends/btor/test_cells.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | rm -rf test_cells.tmp 6 | mkdir -p test_cells.tmp 7 | cd test_cells.tmp 8 | 9 | ../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod' 10 | 11 | for fn in test_*.il; do 12 | ../../../yosys -p " 13 | read_ilang $fn 14 | rename gold gate 15 | synth 16 | 17 | read_ilang $fn 18 | miter -equiv -make_assert -flatten gold gate main 19 | hierarchy -top main 20 | write_btor ${fn%.il}.btor 21 | " 22 | boolectormc -kmax 1 --trace-gen --stop-first -v ${fn%.il}.btor > ${fn%.il}.out 23 | if grep " SATISFIABLE" ${fn%.il}.out; then 24 | echo "Check failed for ${fn%.il}." 25 | exit 1 26 | fi 27 | done 28 | 29 | echo "OK." 30 | 31 | -------------------------------------------------------------------------------- /tests/memories/no_implicit_en.v: -------------------------------------------------------------------------------- 1 | // expect-wr-ports 1 2 | // expect-rd-ports 2 3 | 4 | module test(clk, rd_addr, rd_data, cp_addr, wr_addr, wr_en, wr_data); 5 | 6 | input clk; 7 | 8 | input [3:0] rd_addr; 9 | output reg [31:0] rd_data; 10 | 11 | input [3:0] cp_addr, wr_addr, wr_en; 12 | input [31:0] wr_data; 13 | 14 | reg [31:0] mem [0:15]; 15 | 16 | always @(posedge clk) begin 17 | mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[cp_addr][ 7: 0]; 18 | mem[wr_addr][15: 8] <= wr_en[1] ? wr_data[15: 8] : mem[cp_addr][15: 8]; 19 | mem[wr_addr][23:16] <= wr_en[2] ? wr_data[23:16] : mem[cp_addr][23:16]; 20 | mem[wr_addr][31:24] <= wr_en[3] ? wr_data[31:24] : mem[cp_addr][31:24]; 21 | rd_data <= mem[rd_addr]; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests/techmap/mem_simple_4x1_runtest.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ev 4 | 5 | ../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v 6 | 7 | iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v 8 | iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v 9 | 10 | ./mem_simple_4x1_gold_tb > mem_simple_4x1_gold_tb.out 11 | ./mem_simple_4x1_gate_tb > mem_simple_4x1_gate_tb.out 12 | 13 | diff -u mem_simple_4x1_gold_tb.out mem_simple_4x1_gate_tb.out 14 | rm -f mem_simple_4x1_synth.v mem_simple_4x1_tb.vcd 15 | rm -f mem_simple_4x1_{gold,gate}_tb{,.out} 16 | : OK 17 | 18 | -------------------------------------------------------------------------------- /examples/cmos/cmos_cells.v: -------------------------------------------------------------------------------- 1 | 2 | module BUF(A, Y); 3 | input A; 4 | output Y; 5 | assign Y = A; 6 | endmodule 7 | 8 | module NOT(A, Y); 9 | input A; 10 | output Y; 11 | assign Y = ~A; 12 | endmodule 13 | 14 | module NAND(A, B, Y); 15 | input A, B; 16 | output Y; 17 | assign Y = ~(A & B); 18 | endmodule 19 | 20 | module NOR(A, B, Y); 21 | input A, B; 22 | output Y; 23 | assign Y = ~(A | B); 24 | endmodule 25 | 26 | module DFF(C, D, Q); 27 | input C, D; 28 | output reg Q; 29 | always @(posedge C) 30 | Q <= D; 31 | endmodule 32 | 33 | module DFFSR(C, D, Q, S, R); 34 | input C, D, S, R; 35 | output reg Q; 36 | always @(posedge C, posedge S, posedge R) 37 | if (S) 38 | Q <= 1'b1; 39 | else if (R) 40 | Q <= 1'b0; 41 | else 42 | Q <= D; 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /frontends/ilang/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | GENFILES += frontends/ilang/ilang_parser.tab.cc 3 | GENFILES += frontends/ilang/ilang_parser.tab.hh 4 | GENFILES += frontends/ilang/ilang_parser.output 5 | GENFILES += frontends/ilang/ilang_lexer.cc 6 | 7 | frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y 8 | $(Q) mkdir -p $(dir $@) 9 | $(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $< 10 | 11 | frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc 12 | 13 | frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l 14 | $(Q) mkdir -p $(dir $@) 15 | $(P) flex -o frontends/ilang/ilang_lexer.cc $< 16 | 17 | OBJS += frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o 18 | OBJS += frontends/ilang/ilang_frontend.o 19 | 20 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExSyn/memory_02.v: -------------------------------------------------------------------------------- 1 | module test( 2 | input WR1_CLK, WR2_CLK, 3 | input WR1_WEN, WR2_WEN, 4 | input [7:0] WR1_ADDR, WR2_ADDR, 5 | input [7:0] WR1_DATA, WR2_DATA, 6 | input RD1_CLK, RD2_CLK, 7 | input [7:0] RD1_ADDR, RD2_ADDR, 8 | output reg [7:0] RD1_DATA, RD2_DATA 9 | ); 10 | 11 | reg [7:0] memory [0:255]; 12 | 13 | always @(posedge WR1_CLK) 14 | if (WR1_WEN) 15 | memory[WR1_ADDR] <= WR1_DATA; 16 | 17 | always @(posedge WR2_CLK) 18 | if (WR2_WEN) 19 | memory[WR2_ADDR] <= WR2_DATA; 20 | 21 | always @(posedge RD1_CLK) 22 | RD1_DATA <= memory[RD1_ADDR]; 23 | 24 | always @(posedge RD2_CLK) 25 | RD2_DATA <= memory[RD2_ADDR]; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_parity_using_assign.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : parity_using_assign 3 | // File Name : parity_using_assign.v 4 | // Function : Parity using assign 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module parity_using_assign ( 8 | data_in , // 8 bit data in 9 | parity_out // 1 bit parity out 10 | ); 11 | output parity_out ; 12 | input [7:0] data_in ; 13 | 14 | wire parity_out ; 15 | 16 | assign parity_out = (data_in[0] ^ data_in[1]) ^ 17 | (data_in[2] ^ data_in[3]) ^ 18 | (data_in[4] ^ data_in[5]) ^ 19 | (data_in[6] ^ data_in[7]); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_nand.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_nand_1_test.v 3 | module f1_test(input [1:0] in, output out); 4 | assign out = ~(in[0] & in[1]); 5 | endmodule 6 | 7 | // test_simulation_nand_3_test.v 8 | module f2_test(input [2:0] in, output out); 9 | assign out = !(in[0] & in[1] & in[2]); 10 | endmodule 11 | 12 | // test_simulation_nand_4_test.v 13 | module f3_test(input [2:0] in, output out); 14 | assign out = ~(in[0] && in[1] && in[2]); 15 | endmodule 16 | 17 | // test_simulation_nand_5_test.v 18 | module f4_test(input [3:0] in, output out); 19 | assign out = !(in[0] & in[1] & in[2] & in[3]); 20 | endmodule 21 | 22 | // test_simulation_nand_6_test.v 23 | module f5_test(input [3:0] in, output out); 24 | assign out = !(in[0] && in[1] && in[2] && in[3]); 25 | endmodule 26 | -------------------------------------------------------------------------------- /libs/ezsat/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CC = clang 3 | CXX = clang 4 | CXXFLAGS = -MD -Wall -Wextra -ggdb 5 | CXXFLAGS += -std=c++11 -O0 6 | LDLIBS = ../minisat/Options.cc ../minisat/SimpSolver.cc ../minisat/Solver.cc ../minisat/System.cc -lm -lstdc++ 7 | 8 | 9 | all: demo_vec demo_bit demo_cmp testbench puzzle3d 10 | 11 | demo_vec: demo_vec.o ezsat.o ezminisat.o 12 | demo_bit: demo_bit.o ezsat.o ezminisat.o 13 | demo_cmp: demo_cmp.o ezsat.o ezminisat.o 14 | testbench: testbench.o ezsat.o ezminisat.o 15 | puzzle3d: puzzle3d.o ezsat.o ezminisat.o 16 | 17 | test: all 18 | ./testbench 19 | ./demo_bit 20 | ./demo_vec 21 | # ./demo_cmp 22 | # ./puzzle3d 23 | 24 | clean: 25 | rm -f demo_bit demo_vec demo_cmp testbench puzzle3d *.o *.d 26 | 27 | .PHONY: all test clean 28 | 29 | -include *.d 30 | 31 | -------------------------------------------------------------------------------- /libs/minisat/00_PATCH_typofixes.patch: -------------------------------------------------------------------------------- 1 | --- Solver.h 2 | +++ Solver.h 3 | @@ -103,7 +103,7 @@ public: 4 | int nFreeVars () const; 5 | void printStats () const; // Print some current statistics to standard output. 6 | 7 | - // Resource contraints: 8 | + // Resource constraints: 9 | // 10 | void setConfBudget(int64_t x); 11 | void setPropBudget(int64_t x); 12 | @@ -230,7 +230,7 @@ protected: 13 | double learntsize_adjust_confl; 14 | int learntsize_adjust_cnt; 15 | 16 | - // Resource contraints: 17 | + // Resource constraints: 18 | // 19 | int64_t conflict_budget; // -1 means no budget. 20 | int64_t propagation_budget; // -1 means no budget. 21 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \ 3 | macc_simple_xmap.pdf macc_xilinx_xmap.pdf 4 | 5 | select.pdf: select.v select.ys 6 | ../../yosys select.ys 7 | 8 | red_or3x1.pdf: red_or3x1_* 9 | ../../yosys red_or3x1_test.ys 10 | 11 | sym_mul.pdf: sym_mul_* 12 | ../../yosys sym_mul_test.ys 13 | 14 | mymul.pdf: mymul_* 15 | ../../yosys mymul_test.ys 16 | 17 | mulshift.pdf: mulshift_* 18 | ../../yosys mulshift_test.ys 19 | 20 | addshift.pdf: addshift_* 21 | ../../yosys addshift_test.ys 22 | 23 | macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys 24 | ../../yosys macc_simple_test.ys 25 | 26 | macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys 27 | ../../yosys macc_xilinx_test.ys 28 | 29 | -------------------------------------------------------------------------------- /examples/smtbmc/demo2.v: -------------------------------------------------------------------------------- 1 | // Nothing to prove in this demo. 2 | // Just an example for memories, vcd dumps and vlog testbench dumps. 3 | 4 | `ifdef FORMAL 5 | `define assume(_expr_) assume(_expr_) 6 | `else 7 | `define assume(_expr_) 8 | `endif 9 | 10 | module demo2(input clk, input [4:0] addr, output reg [31:0] data); 11 | reg [31:0] mem [0:31]; 12 | always @(negedge clk) 13 | data <= mem[addr]; 14 | 15 | reg [31:0] used_addr = 0; 16 | reg [31:0] used_dbits = 0; 17 | reg initstate = 1; 18 | 19 | always @(posedge clk) begin 20 | initstate <= 0; 21 | `assume(!used_addr[addr]); 22 | used_addr[addr] <= 1; 23 | if (!initstate) begin 24 | `assume(data != 0); 25 | `assume((used_dbits & data) == 0); 26 | used_dbits <= used_dbits | data; 27 | end 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/simple/hierdefparam.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module hierdefparam_top(input [7:0] A, output [7:0] Y); 4 | generate begin:foo 5 | hierdefparam_a mod_a(.A(A), .Y(Y)); 6 | end endgenerate 7 | defparam foo.mod_a.bar[0].mod_b.addvalue = 42; 8 | defparam foo.mod_a.bar[1].mod_b.addvalue = 43; 9 | endmodule 10 | 11 | module hierdefparam_a(input [7:0] A, output [7:0] Y); 12 | genvar i; 13 | generate 14 | for (i = 0; i < 2; i=i+1) begin:bar 15 | wire [7:0] a, y; 16 | hierdefparam_b mod_b(.A(a), .Y(y)); 17 | end 18 | endgenerate 19 | assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y; 20 | endmodule 21 | 22 | module hierdefparam_b(input [7:0] A, output [7:0] Y); 23 | parameter [7:0] addvalue = 44; 24 | assign Y = A + addvalue; 25 | endmodule 26 | -------------------------------------------------------------------------------- /techlibs/xilinx/tests/bram2.v: -------------------------------------------------------------------------------- 1 | module myram( 2 | input rd_clk, 3 | input [ 7:0] rd_addr, 4 | output reg [17:0] rd_data, 5 | input wr_clk, 6 | input wr_enable, 7 | input [ 7:0] wr_addr, 8 | input [17:0] wr_data 9 | ); 10 | reg [17:0] memory [0:255]; 11 | integer i; 12 | 13 | function [17:0] hash(input [7:0] k); 14 | reg [31:0] x; 15 | begin 16 | x = {k, ~k, k, ~k}; 17 | x = x ^ (x << 13); 18 | x = x ^ (x >> 17); 19 | x = x ^ (x << 5); 20 | hash = x; 21 | end 22 | endfunction 23 | 24 | initial begin 25 | for (i = 0; i < 256; i = i+1) 26 | memory[i] = hash(i); 27 | end 28 | 29 | always @(posedge rd_clk) 30 | rd_data <= memory[rd_addr]; 31 | 32 | always @(posedge wr_clk) 33 | if (wr_enable) 34 | memory[wr_addr] <= wr_data; 35 | endmodule 36 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/sumprod_05.dot: -------------------------------------------------------------------------------- 1 | digraph "sumprod" { 2 | rankdir="LR"; 3 | remincross=true; 4 | n2 [ shape=octagon, label="c", color="black", fontcolor="black" ]; 5 | n3 [ shape=octagon, label="prod", color="black", fontcolor="black" ]; 6 | v0 [ label="a" ]; 7 | v1 [ label="b" ]; 8 | c7 [ shape=record, label="{{ A| B}|$3\n$mul|{ Y}}" ]; 9 | c8 [ shape=record, label="{{ A| B}|$4\n$mul|{ Y}}" ]; 10 | c7:p6:e -> c8:p4:w [color="black", style="setlinewidth(3)", label=""]; 11 | n2:e -> c8:p5:w [color="black", style="setlinewidth(3)", label=""]; 12 | c8:p6:e -> n3:w [color="black", style="setlinewidth(3)", label=""]; 13 | v0:e -> c7:p4:w [color="black", style="setlinewidth(3)", label=""]; 14 | v1:e -> c7:p5:w [color="black", style="setlinewidth(3)", label=""]; 15 | } 16 | -------------------------------------------------------------------------------- /techlibs/greenpak4/Makefile.inc: -------------------------------------------------------------------------------- 1 | 2 | OBJS += techlibs/greenpak4/synth_greenpak4.o 3 | OBJS += techlibs/greenpak4/greenpak4_dffinv.o 4 | 5 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v)) 6 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v)) 7 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v)) 8 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v)) 9 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_ams.v)) 10 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_digital.v)) 11 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_wip.v)) 12 | $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib)) 13 | -------------------------------------------------------------------------------- /tests/simple/repwhile.v: -------------------------------------------------------------------------------- 1 | module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x); 2 | 3 | function [7:0] mylog2; 4 | input [31:0] value; 5 | begin 6 | mylog2 = 0; 7 | while (value > 0) begin 8 | value = value >> 1; 9 | mylog2 = mylog2 + 1; 10 | end 11 | end 12 | endfunction 13 | 14 | function [31:0] myexp2; 15 | input [7:0] value; 16 | begin 17 | myexp2 = 1; 18 | repeat (value) 19 | myexp2 = myexp2 << 1; 20 | end 21 | endfunction 22 | 23 | reg [7:0] y_table [63:0]; 24 | reg [31:0] x_table [63:0]; 25 | 26 | integer i; 27 | initial begin 28 | for (i = 0; i < 64; i = i+1) begin 29 | y_table[i] <= mylog2(i); 30 | x_table[i] <= myexp2(i); 31 | end 32 | end 33 | 34 | assign y = y_table[a]; 35 | assign x = x_table[a]; 36 | endmodule 37 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | Copyright (C) 2012 - 2018 Clifford Wolf 2 | 3 | Permission to use, copy, modify, and/or distribute this software for any 4 | purpose with or without fee is hereby granted, provided that the above 5 | copyright notice and this permission notice appear in all copies. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExAdv/mulshift_map.v: -------------------------------------------------------------------------------- 1 | module MYMUL(A, B, Y); 2 | parameter WIDTH = 1; 3 | input [WIDTH-1:0] A, B; 4 | output reg [WIDTH-1:0] Y; 5 | 6 | parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx; 7 | parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx; 8 | 9 | reg _TECHMAP_FAIL_; 10 | wire [1023:0] _TECHMAP_DO_ = "proc; clean"; 11 | 12 | integer i; 13 | always @* begin 14 | _TECHMAP_FAIL_ <= 1; 15 | for (i = 0; i < WIDTH; i=i+1) begin 16 | if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin 17 | _TECHMAP_FAIL_ <= 0; 18 | Y <= B << i; 19 | end 20 | if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin 21 | _TECHMAP_FAIL_ <= 0; 22 | Y <= A << i; 23 | end 24 | end 25 | end 26 | endmodule 27 | -------------------------------------------------------------------------------- /manual/PRESENTATION_ExOth/axis_master.v: -------------------------------------------------------------------------------- 1 | module axis_master(aclk, aresetn, tvalid, tready, tdata); 2 | input aclk, aresetn, tready; 3 | output reg tvalid; 4 | output reg [7:0] tdata; 5 | 6 | reg [31:0] state; 7 | always @(posedge aclk) begin 8 | if (!aresetn) begin 9 | state <= 314159265; 10 | tvalid <= 0; 11 | tdata <= 'bx; 12 | end else begin 13 | if (tvalid && tready) 14 | tvalid <= 0; 15 | if (!tvalid || !tready) begin 16 | // ^- should not be inverted! 17 | state = state ^ state << 13; 18 | state = state ^ state >> 7; 19 | state = state ^ state << 17; 20 | if (state[9:8] == 0) begin 21 | tvalid <= 1; 22 | tdata <= state; 23 | end 24 | end 25 | end 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /tests/memories/simple_sram_byte_en.v: -------------------------------------------------------------------------------- 1 | // expect-wr-ports 1 2 | // expect-rd-ports 1 3 | 4 | module generic_sram_byte_en #( 5 | parameter DATA_WIDTH = 32, 6 | parameter ADDRESS_WIDTH = 4 7 | ) ( 8 | input i_clk, 9 | input [DATA_WIDTH-1:0] i_write_data, 10 | input i_write_enable, 11 | input [ADDRESS_WIDTH-1:0] i_address, 12 | input [DATA_WIDTH/8-1:0] i_byte_enable, 13 | output reg [DATA_WIDTH-1:0] o_read_data 14 | ); 15 | 16 | reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1]; 17 | integer i; 18 | 19 | always @(posedge i_clk) begin 20 | for (i=0;i c4:p1:w [color="black", style="setlinewidth(3)", label=""]; 13 | v1:e -> c4:p2:w [color="black", style="setlinewidth(3)", label=""]; 14 | c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""]; 15 | v3:e -> c5:p1:w [color="black", style="setlinewidth(3)", label=""]; 16 | v4:e -> c5:p2:w [color="black", style="setlinewidth(3)", label=""]; 17 | c5:p3:e -> v5:w [color="black", style="setlinewidth(3)", label=""]; 18 | } 19 | -------------------------------------------------------------------------------- /tests/sat/expose_dff.v: -------------------------------------------------------------------------------- 1 | 2 | module test1(input clk, input [3:0] a, output reg [3:0] y); 3 | always @(posedge clk) 4 | y <= a; 5 | endmodule 6 | 7 | module test2(input clk, input [3:0] a, output reg [3:0] y); 8 | wire clk_n = !clk; 9 | always @(negedge clk_n) 10 | y[1:0] <= a[1:0]; 11 | always @(negedge clk_n) 12 | y[3:2] <= a[3:2]; 13 | endmodule 14 | 15 | // ----------------------------------------------------------- 16 | 17 | module test3(input clk, rst, input [3:0] a, output reg [3:0] y); 18 | always @(posedge clk, posedge rst) 19 | if (rst) 20 | y <= 12; 21 | else 22 | y <= |a; 23 | endmodule 24 | 25 | module test4(input clk, rst, input [3:0] a, output reg [3:0] y); 26 | wire rst_n = !rst; 27 | always @(posedge clk, negedge rst_n) 28 | if (!rst_n) 29 | y <= 12; 30 | else 31 | y <= a != 0; 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_mux_using_assign.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : mux_using_assign 3 | // File Name : mux_using_assign.v 4 | // Function : 2:1 Mux using Assign 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module mux_using_assign( 8 | din_0 , // Mux first input 9 | din_1 , // Mux Second input 10 | sel , // Select input 11 | mux_out // Mux output 12 | ); 13 | //-----------Input Ports--------------- 14 | input din_0, din_1, sel ; 15 | //-----------Output Ports--------------- 16 | output mux_out; 17 | //------------Internal Variables-------- 18 | wire mux_out; 19 | //-------------Code Start----------------- 20 | assign mux_out = (sel) ? din_1 : din_0; 21 | 22 | endmodule //End Of Module mux 23 | -------------------------------------------------------------------------------- /tests/simple/usb_phy_tests.v: -------------------------------------------------------------------------------- 1 | 2 | // from usb_rx_phy 3 | module usb_phy_test01(clk, rst, rx_en, fs_ce); 4 | 5 | input clk, rst; 6 | input rx_en; 7 | output reg fs_ce; 8 | reg [1:0] dpll_next_state; 9 | reg [1:0] dpll_state; 10 | 11 | always @(posedge clk) 12 | dpll_state <= rst ? 0 : dpll_next_state; 13 | 14 | always @* 15 | begin 16 | fs_ce = 1'b0; 17 | case(dpll_state) 18 | 2'h0: 19 | if(rx_en) dpll_next_state = 2'h0; 20 | else dpll_next_state = 2'h1; 21 | 2'h1:begin 22 | fs_ce = 1'b1; 23 | if(rx_en) dpll_next_state = 2'h3; 24 | else dpll_next_state = 2'h2; 25 | end 26 | 2'h2: 27 | if(rx_en) dpll_next_state = 2'h0; 28 | else dpll_next_state = 2'h3; 29 | 2'h3: 30 | if(rx_en) dpll_next_state = 2'h0; 31 | else dpll_next_state = 2'h0; 32 | endcase 33 | end 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /examples/cmos/cmos_cells.sp: -------------------------------------------------------------------------------- 1 | 2 | .SUBCKT BUF A Y 3 | X1 A B NOT 4 | X2 B Y NOT 5 | .ENDS NOT 6 | 7 | .SUBCKT NOT A Y 8 | M1 Y A Vdd Vdd cmosp L=1u W=10u 9 | M2 Y A Vss Vss cmosn L=1u W=10u 10 | .ENDS NOT 11 | 12 | .SUBCKT NAND A B Y 13 | M1 Y A Vdd Vdd cmosp L=1u W=10u 14 | M2 Y B Vdd Vdd cmosp L=1u W=10u 15 | M3 Y A M34 Vss cmosn L=1u W=10u 16 | M4 M34 B Vss Vss cmosn L=1u W=10u 17 | .ENDS NAND 18 | 19 | .SUBCKT NOR A B Y 20 | M1 Y A M12 Vdd cmosp L=1u W=10u 21 | M2 M12 B Vdd Vdd cmosp L=1u W=10u 22 | M3 Y A Vss Vss cmosn L=1u W=10u 23 | M4 Y B Vss Vss cmosn L=1u W=10u 24 | .ENDS NOR 25 | 26 | .SUBCKT DLATCH E D Q 27 | X1 D E S NAND 28 | X2 nD E R NAND 29 | X3 S nQ Q NAND 30 | X4 Q R nQ NAND 31 | X5 D nD NOT 32 | .ENDS DLATCH 33 | 34 | .SUBCKT DFF C D Q 35 | X1 nC D t DLATCH 36 | X2 C t Q DLATCH 37 | X3 C nC NOT 38 | .ENDS DFF 39 | 40 | -------------------------------------------------------------------------------- /libs/minisat/00_UPDATE.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -f LICENSE *.cc *.h 4 | git clone --depth 1 https://github.com/niklasso/minisat minisat_upstream 5 | rm minisat_upstream/minisat/*/Main.cc 6 | mv minisat_upstream/LICENSE minisat_upstream/minisat/*/*.{h,cc} . 7 | rm -rf minisat_upstream 8 | 9 | sed -i -e 's,^#include *"minisat/[^/]\+/\?,#include ",' *.cc *.h 10 | sed -i -e 's/Minisat::memUsedPeak()/Minisat::memUsedPeak(bool)/' System.cc 11 | sed -i -e 's/PRI[iu]64/ & /' Options.h Solver.cc 12 | sed -i -e '1 i #ifndef __STDC_LIMIT_MACROS\n#define __STDC_LIMIT_MACROS\n#endif' *.cc 13 | sed -i -e '1 i #ifndef __STDC_FORMAT_MACROS\n#define __STDC_FORMAT_MACROS\n#endif' *.cc 14 | 15 | patch -p0 < 00_PATCH_mkLit_default_arg.patch 16 | patch -p0 < 00_PATCH_remove_zlib.patch 17 | patch -p0 < 00_PATCH_no_fpu_control.patch 18 | patch -p0 < 00_PATCH_typofixes.patch 19 | 20 | -------------------------------------------------------------------------------- /backends/smv/test_cells.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | rm -rf test_cells.tmp 6 | mkdir -p test_cells.tmp 7 | cd test_cells.tmp 8 | 9 | # don't test $mul to reduce runtime 10 | # don't test $div and $mod to reduce runtime and avoid "div by zero" message 11 | ../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$macc /$mul /$div /$mod' 12 | 13 | cat > template.txt << "EOT" 14 | %module main 15 | INVARSPEC ! bool(_trigger); 16 | EOT 17 | 18 | for fn in test_*.il; do 19 | ../../../yosys -p " 20 | read_ilang $fn 21 | rename gold gate 22 | synth 23 | 24 | read_ilang $fn 25 | miter -equiv -flatten gold gate main 26 | hierarchy -top main 27 | write_smv -tpl template.txt ${fn#.il}.smv 28 | " 29 | nuXmv -dynamic ${fn#.il}.smv > ${fn#.il}.out 30 | done 31 | 32 | grep '^-- invariant .* is false' *.out || echo 'All OK.' 33 | 34 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_tff_sync_reset.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : tff_sync_reset 3 | // File Name : tff_sync_reset.v 4 | // Function : T flip-flop sync reset 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module tff_sync_reset ( 8 | data , // Data Input 9 | clk , // Clock Input 10 | reset , // Reset input 11 | q // Q output 12 | ); 13 | //-----------Input Ports--------------- 14 | input data, clk, reset ; 15 | //-----------Output Ports--------------- 16 | output q; 17 | //------------Internal Variables-------- 18 | reg q; 19 | //-------------Code Starts Here--------- 20 | always @ ( posedge clk) 21 | if (~reset) begin 22 | q <= 1'b0; 23 | end else if (data) begin 24 | q <= !q; 25 | end 26 | 27 | endmodule //End Of Module tff_async_reset 28 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_up_counter.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : up_counter 3 | // File Name : up_counter.v 4 | // Function : Up counter 5 | // Coder : Deepak 6 | //----------------------------------------------------- 7 | module up_counter ( 8 | out , // Output of the counter 9 | enable , // enable for counter 10 | clk , // clock Input 11 | reset // reset Input 12 | ); 13 | //----------Output Ports-------------- 14 | output [7:0] out; 15 | //------------Input Ports-------------- 16 | input enable, clk, reset; 17 | //------------Internal Variables-------- 18 | reg [7:0] out; 19 | //-------------Code Starts Here------- 20 | always @(posedge clk) 21 | if (reset) begin 22 | out <= 8'b0 ; 23 | end else if (enable) begin 24 | out <= out + 1; 25 | end 26 | 27 | 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_dff_sync_reset.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : dff_sync_reset 3 | // File Name : dff_sync_reset.v 4 | // Function : D flip-flop sync reset 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module dff_sync_reset ( 8 | data , // Data Input 9 | clk , // Clock Input 10 | reset , // Reset input 11 | q // Q output 12 | ); 13 | //-----------Input Ports--------------- 14 | input data, clk, reset ; 15 | 16 | //-----------Output Ports--------------- 17 | output q; 18 | 19 | //------------Internal Variables-------- 20 | reg q; 21 | 22 | //-------------Code Starts Here--------- 23 | always @ ( posedge clk) 24 | if (~reset) begin 25 | q <= 1'b0; 26 | end else begin 27 | q <= data; 28 | end 29 | 30 | endmodule //End Of Module dff_sync_reset 31 | -------------------------------------------------------------------------------- /tests/asicworld/code_hdl_models_tff_async_reset.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------- 2 | // Design Name : tff_async_reset 3 | // File Name : tff_async_reset.v 4 | // Function : T flip-flop async reset 5 | // Coder : Deepak Kumar Tala 6 | //----------------------------------------------------- 7 | module tff_async_reset ( 8 | data , // Data Input 9 | clk , // Clock Input 10 | reset , // Reset input 11 | q // Q output 12 | ); 13 | //-----------Input Ports--------------- 14 | input data, clk, reset ; 15 | //-----------Output Ports--------------- 16 | output q; 17 | //------------Internal Variables-------- 18 | reg q; 19 | //-------------Code Starts Here--------- 20 | always @ ( posedge clk or negedge reset) 21 | if (~reset) begin 22 | q <= 1'b0; 23 | end else if (data) begin 24 | q <= !q; 25 | end 26 | 27 | endmodule //End Of Module tff_async_reset 28 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_inc.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_inc_16_test.v 3 | module f1_test(input [15:0] in, output [15:0] out); 4 | 5 | assign out = -in; 6 | 7 | endmodule 8 | 9 | // test_simulation_inc_1_test.v 10 | module f2_test(input in, output out); 11 | 12 | assign out = -in; 13 | 14 | endmodule 15 | 16 | // test_simulation_inc_2_test.v 17 | module f3_test(input [1:0] in, output [1:0] out); 18 | 19 | assign out = -in; 20 | 21 | endmodule 22 | 23 | // test_simulation_inc_32_test.v 24 | module f4_test(input [31:0] in, output [31:0] out); 25 | 26 | assign out = -in; 27 | 28 | endmodule 29 | 30 | // test_simulation_inc_4_test.v 31 | module f5_test(input [3:0] in, output [3:0] out); 32 | 33 | assign out = -in; 34 | 35 | endmodule 36 | 37 | // test_simulation_inc_8_test.v 38 | module f6_test(input [7:0] in, output [7:0] out); 39 | 40 | assign out = -in; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /examples/gowin/testbench.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | reg clk; 3 | 4 | initial begin 5 | #5 clk = 0; 6 | forever #5 clk = ~clk; 7 | end 8 | 9 | wire [15:0] leds; 10 | 11 | initial begin 12 | // $dumpfile("testbench.vcd"); 13 | // $dumpvars(0, testbench); 14 | $monitor("%b", leds); 15 | end 16 | 17 | demo uut ( 18 | .clk (clk ), 19 | `ifdef POST_IMPL 20 | .\leds[0] (leds[0]), 21 | .\leds[1] (leds[1]), 22 | .\leds[2] (leds[2]), 23 | .\leds[3] (leds[3]), 24 | .\leds[4] (leds[4]), 25 | .\leds[5] (leds[5]), 26 | .\leds[6] (leds[6]), 27 | .\leds[7] (leds[7]), 28 | .\leds[8] (leds[8]), 29 | .\leds[9] (leds[9]), 30 | .\leds[10] (leds[10]), 31 | .\leds[11] (leds[11]), 32 | .\leds[12] (leds[12]), 33 | .\leds[13] (leds[13]), 34 | .\leds[14] (leds[14]), 35 | .\leds[15] (leds[15]) 36 | `else 37 | .leds(leds) 38 | `endif 39 | ); 40 | endmodule 41 | -------------------------------------------------------------------------------- /tests/hana/test_simulation_or.v: -------------------------------------------------------------------------------- 1 | 2 | // test_simulation_or_1_test.v 3 | module f1_test(input [1:0] in, output out); 4 | assign out = in[0] | in[1]; 5 | endmodule 6 | 7 | // test_simulation_or_2_test.v 8 | module f2_test(input [1:0] in, output out); 9 | assign out = in[0] || in[1]; 10 | endmodule 11 | 12 | // test_simulation_or_3_test.v 13 | module f3_test(input [2:0] in, output out); 14 | assign out = in[0] | in[1] | in[2]; 15 | endmodule 16 | 17 | // test_simulation_or_4_test.v 18 | module f4_test(input [2:0] in, output out); 19 | assign out = in[0] || in[1] || in[2]; 20 | endmodule 21 | 22 | // test_simulation_or_5_test.v 23 | module f5_test(input [3:0] in, output out); 24 | assign out = in[0] | in[1] | in[2] | in[3]; 25 | endmodule 26 | 27 | // test_simulation_or_6_test.v 28 | module f6_test(input [3:0] in, output out); 29 | assign out = in[0] || in[1] || in[2] || in[3]; 30 | endmodule 31 | -------------------------------------------------------------------------------- /manual/APPNOTE_011_Design_Investigation/sumprod_01.dot: -------------------------------------------------------------------------------- 1 | digraph "sumprod" { 2 | rankdir="LR"; 3 | remincross=true; 4 | n2 [ shape=octagon, label="a", color="black", fontcolor="black" ]; 5 | n3 [ shape=octagon, label="b", color="black", fontcolor="black" ]; 6 | n4 [ shape=octagon, label="c", color="black", fontcolor="black" ]; 7 | n5 [ shape=octagon, label="sum", color="black", fontcolor="black" ]; 8 | c9 [ shape=record, label="{{ A| B}|$1\n$add|{ Y}}" ]; 9 | c10 [ shape=record, label="{{ A| B}|$2\n$add|{ Y}}" ]; 10 | c9:p8:e -> c10:p6:w [color="black", style="setlinewidth(3)", label=""]; 11 | n2:e -> c9:p6:w [color="black", style="setlinewidth(3)", label=""]; 12 | n3:e -> c9:p7:w [color="black", style="setlinewidth(3)", label=""]; 13 | n4:e -> c10:p7:w [color="black", style="setlinewidth(3)", label=""]; 14 | c10:p8:e -> n5:w [color="black", style="setlinewidth(3)", label=""]; 15 | } 16 | --------------------------------------------------------------------------------