├── .gitignore ├── README.md ├── XCapstone.pro ├── 3rdparty └── Capstone │ ├── src │ ├── arch │ │ ├── SH │ │ │ ├── SHModule.h │ │ │ ├── SHDisassembler.h │ │ │ ├── SHInstPrinter.h │ │ │ ├── SHModule.c │ │ │ └── SHInsnTable.inc │ │ ├── EVM │ │ │ ├── EVMMapping.h │ │ │ ├── EVMModule.h │ │ │ ├── EVMDisassembler.h │ │ │ ├── EVMInstPrinter.h │ │ │ ├── EVMInstPrinter.c │ │ │ └── EVMModule.c │ │ ├── TriCore │ │ │ ├── TriCoreModule.h │ │ │ ├── TriCoreDisassembler.h │ │ │ ├── TriCoreLinkage.h │ │ │ ├── TriCoreGenCSFeatureName.inc │ │ │ ├── TriCoreMapping.h │ │ │ ├── TriCoreModule.c │ │ │ ├── TriCoreGenSubtargetInfo.inc │ │ │ ├── TriCoreGenCSOpGroup.inc │ │ │ └── TriCoreCallingConv.td │ │ ├── WASM │ │ │ ├── WASMModule.h │ │ │ ├── WASMDisassembler.h │ │ │ ├── WASMMapping.h │ │ │ ├── WASMInstPrinter.h │ │ │ ├── WASMModule.c │ │ │ └── WASMInstPrinter.c │ │ ├── ARM │ │ │ ├── ARMModule.h │ │ │ ├── ARMDisassembler.h │ │ │ ├── ARMMapping.h │ │ │ ├── ARMInstPrinter.h │ │ │ └── ARMModule.c │ │ ├── X86 │ │ │ ├── X86Module.h │ │ │ ├── X86InstPrinterCommon.h │ │ │ ├── X86Disassembler.h │ │ │ ├── X86InstPrinter.h │ │ │ ├── X86BaseInfo.h │ │ │ ├── X86Module.c │ │ │ └── X86Mapping.h │ │ ├── BPF │ │ │ ├── BPFModule.h │ │ │ ├── BPFInstPrinter.h │ │ │ ├── BPFDisassembler.h │ │ │ ├── BPFMapping.h │ │ │ ├── BPFModule.c │ │ │ └── BPFConstants.h │ │ ├── M68K │ │ │ ├── M68KModule.h │ │ │ ├── M68KInstPrinter.h │ │ │ ├── M68KModule.c │ │ │ └── M68KDisassembler.h │ │ ├── Mips │ │ │ ├── MipsModule.h │ │ │ ├── MipsDisassembler.h │ │ │ ├── MipsMapping.h │ │ │ ├── MipsInstPrinter.h │ │ │ ├── MipsModule.c │ │ │ └── MipsGenSubtargetInfo.inc │ │ ├── M680X │ │ │ ├── M680XModule.h │ │ │ ├── M680XDisassembler.h │ │ │ ├── hd6301.inc │ │ │ ├── M680XInstPrinter.h │ │ │ ├── m6801.inc │ │ │ ├── M680XDisassemblerInternals.h │ │ │ ├── M680XModule.c │ │ │ ├── hcs08.inc │ │ │ ├── m6808.inc │ │ │ └── m6811.inc │ │ ├── PowerPC │ │ │ ├── PPCModule.h │ │ │ ├── PPCInstPrinter.h │ │ │ ├── PPCDisassembler.h │ │ │ ├── PPCModule.c │ │ │ ├── PPCMapping.h │ │ │ ├── PPCPredicates.h │ │ │ └── PPCGenSubtargetInfo.inc │ │ ├── Sparc │ │ │ ├── SparcModule.h │ │ │ ├── SparcInstPrinter.h │ │ │ ├── SparcDisassembler.h │ │ │ ├── SparcMapping.h │ │ │ ├── SparcGenSubtargetInfo.inc │ │ │ ├── SparcModule.c │ │ │ └── Sparc.h │ │ ├── XCore │ │ │ ├── XCoreModule.h │ │ │ ├── XCoreDisassembler.h │ │ │ ├── XCoreInstPrinter.h │ │ │ ├── XCoreMapping.h │ │ │ ├── XCoreModule.c │ │ │ └── XCoreGenRegisterInfo.inc │ │ ├── MOS65XX │ │ │ ├── MOS65XXModule.h │ │ │ ├── MOS65XXDisassemblerInternals.h │ │ │ ├── MOS65XXDisassembler.h │ │ │ └── MOS65XXModule.c │ │ ├── RISCV │ │ │ ├── RISCVModule.h │ │ │ ├── RISCVDisassembler.h │ │ │ ├── RISCVMapping.h │ │ │ ├── RISCVInstPrinter.h │ │ │ ├── RISCVModule.c │ │ │ ├── RISCVGenSubtargetInfo.inc │ │ │ └── RISCVBaseInfo.h │ │ ├── AArch64 │ │ │ ├── AArch64Module.h │ │ │ ├── AArch64GenSystemOperands_enum.inc │ │ │ ├── AArch64Disassembler.h │ │ │ ├── AArch64InstPrinter.h │ │ │ ├── AArch64Module.c │ │ │ ├── AArch64Mapping.h │ │ │ ├── AArch64BaseInfo.c │ │ │ └── AArch64GenSubtargetInfo.inc │ │ ├── SystemZ │ │ │ ├── SystemZModule.h │ │ │ ├── SystemZInstPrinter.h │ │ │ ├── SystemZDisassembler.h │ │ │ ├── SystemZMapping.h │ │ │ ├── SystemZModule.c │ │ │ ├── SystemZMCTargetDesc.h │ │ │ └── SystemZGenSubtargetInfo.inc │ │ └── TMS320C64x │ │ │ ├── TMS320C64xModule.h │ │ │ ├── TMS320C64xInstPrinter.h │ │ │ ├── TMS320C64xDisassembler.h │ │ │ ├── TMS320C64xMapping.h │ │ │ └── TMS320C64xModule.c │ ├── MCDisassembler.h │ ├── include │ │ ├── windowsce │ │ │ ├── intrin.h │ │ │ └── stdint.h │ │ ├── platform.h │ │ └── capstone │ │ │ ├── platform.h │ │ │ └── bpf.h │ ├── MCInstrDesc.c │ ├── SStream.h │ ├── LEB128.h │ ├── MCFixedLenDisassembler.h │ ├── LICENSE.TXT │ ├── utils.h │ ├── LICENSE_LLVM.TXT │ ├── cs_priv.h │ ├── utils.c │ ├── MCRegisterInfo.c │ ├── MCInst.c │ ├── capstone │ │ ├── platform.h │ │ └── bpf.h │ └── SStream.c │ ├── Capstone.pri │ ├── Capstone_x86.pri │ ├── x86 │ └── x86.pro │ └── Capstone.pro ├── xcapstone.cmake ├── xcapstone.pri ├── xcapstone_x86.pri ├── LICENSE ├── x86 └── CMakeLists.txt └── xcapstone.h /.gitignore: -------------------------------------------------------------------------------- 1 | 3rdparty/Capstone/libs 2 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # XCapstone 2 | Capstone disasm for Qt. 3 | -------------------------------------------------------------------------------- /XCapstone.pro: -------------------------------------------------------------------------------- 1 | # build libs 2 | TEMPLATE = subdirs 3 | SUBDIRS += 3rdparty/Capstone 4 | SUBDIRS += 3rdparty/Capstone/x86 5 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SH/SHModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Yoshinori Sato, 2022 */ 3 | 4 | #ifndef CS_SH_MODULE_H 5 | #define CS_SH_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err SH_global_init(cs_struct *ud); 10 | cs_err SH_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/EVM/EVMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #include 5 | 6 | void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 7 | const char *EVM_insn_name(csh handle, unsigned int id); 8 | const char *EVM_group_name(csh handle, unsigned int id); 9 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreModule.h: -------------------------------------------------------------------------------- 1 | // 2 | // Created by aya on 3/4/23. 3 | // 4 | 5 | #ifndef CAPSTONE_TRICODEMODULE_H 6 | #define CAPSTONE_TRICODEMODULE_H 7 | 8 | cs_err TRICORE_global_init(cs_struct *ud); 9 | cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value); 10 | 11 | #endif // CAPSTONE_TRICODEMODULE_H 12 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/WASM/WASMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifndef CS_WASM_MODULE_H 5 | #define CS_WASM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err WASM_global_init(cs_struct *ud); 10 | cs_err WASM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/ARM/ARMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_ARM_MODULE_H 5 | #define CS_ARM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err ARM_global_init(cs_struct *ud); 10 | cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/EVM/EVMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_EVM_MODULE_H 5 | #define CS_EVM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err EVM_global_init(cs_struct *ud); 10 | cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86Module.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_X86_MODULE_H 5 | #define CS_X86_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err X86_global_init(cs_struct *ud); 10 | cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/BPF/BPFModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CS_BPF_MODULE_H 5 | #define CS_BPF_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err BPF_global_init(cs_struct *ud); 10 | cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M68K/M68KModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_M68K_MODULE_H 5 | #define CS_M68K_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err M68K_global_init(cs_struct *ud); 10 | cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Mips/MipsModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_MIPS_MODULE_H 5 | #define CS_MIPS_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err Mips_global_init(cs_struct *ud); 10 | cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/M680XModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_M680X_MODULE_H 5 | #define CS_M680X_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err M680X_global_init(cs_struct *ud); 10 | cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_POWERPC_MODULE_H 5 | #define CS_POWERPC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err PPC_global_init(cs_struct *ud); 10 | cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/SparcModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_SPARC_MODULE_H 5 | #define CS_SPARC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err Sparc_global_init(cs_struct *ud); 10 | cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/XCore/XCoreModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_XCORE_MODULE_H 5 | #define CS_XCORE_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err XCore_global_init(cs_struct *ud); 10 | cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/MCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_MCDISASSEMBLER_H 5 | #define CS_MCDISASSEMBLER_H 6 | 7 | typedef enum DecodeStatus { 8 | MCDisassembler_Fail = 0, 9 | MCDisassembler_SoftFail = 1, 10 | MCDisassembler_Success = 3, 11 | } DecodeStatus; 12 | 13 | #endif 14 | 15 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/EVM/EVMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_EVMDISASSEMBLER_H 5 | #define CS_EVMDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/MOS65XX/MOS65XXModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Sebastian Macke , 2018 */ 3 | 4 | #ifndef CS_MOS65XX_MODULE_H 5 | #define CS_MOS65XX_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err MOS65XX_global_init(cs_struct *ud); 10 | cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Shawn Chang , HardenedLinux@2018 */ 3 | 4 | #ifndef CS_RISCV_MODULE_H 5 | #define CS_RISCV_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err RISCV_global_init(cs_struct * ud); 10 | cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/WASM/WASMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifndef CS_WASMDISASSEMBLER_H 5 | #define CS_WASMDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool WASM_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64Module.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_AARCH64_MODULE_H 5 | #define CS_AARCH64_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err AArch64_global_init(cs_struct *ud); 10 | cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_SYSTEMZ_MODULE_H 5 | #define CS_SYSTEMZ_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err SystemZ_global_init(cs_struct *ud); 10 | cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/WASM/WASMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #include 5 | 6 | void WASM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 7 | const char *WASM_insn_name(csh handle, unsigned int id); 8 | const char *WASM_group_name(csh handle, unsigned int id); 9 | const char *WASM_kind_name(unsigned int id); 10 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/include/windowsce/intrin.h: -------------------------------------------------------------------------------- 1 | 2 | #if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN) 3 | #define _STDINT 4 | 5 | #ifdef _M_ARM 6 | #include 7 | #if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) 8 | #include 9 | #endif 10 | #endif // _M_ARM 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TMS320C64x/TMS320C64xModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_TMS320C64X_MODULE_H 5 | #define CS_TMS320C64X_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err TMS320C64x_global_init(cs_struct *ud); 10 | cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/BPF/BPFInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CS_BPFINSTPRINTER_H 5 | #define CS_BPFINSTPRINTER_H 6 | 7 | #include 8 | 9 | #include "../../MCInst.h" 10 | #include "../../SStream.h" 11 | 12 | struct SStream; 13 | 14 | void BPF_printInst(MCInst *MI, struct SStream *O, void *Info); 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/EVM/EVMInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_EVMINSTPRINTER_H 5 | #define CS_EVMINSTPRINTER_H 6 | 7 | 8 | #include "capstone/capstone.h" 9 | #include "../../MCInst.h" 10 | #include "../../SStream.h" 11 | #include "../../cs_priv.h" 12 | 13 | struct SStream; 14 | 15 | void EVM_printInst(MCInst *MI, struct SStream *O, void *Info); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_PPCINSTPRINTER_H 5 | #define CS_PPCINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void PPC_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /3rdparty/Capstone/Capstone.pri: -------------------------------------------------------------------------------- 1 | INCLUDEPATH += $$PWD/src 2 | DEPENDPATH += $$PWD/src 3 | INCLUDEPATH += $$PWD/src/include 4 | DEPENDPATH += $$PWD/src/include 5 | 6 | win32-g++ { 7 | LIBS += $$PWD/libs/libcapstone-win-$${QT_ARCH}.a 8 | } 9 | win32-msvc* { 10 | LIBS += $$PWD/libs/capstone-win-$${QT_ARCH}.lib 11 | } 12 | unix:!macx { 13 | LIBS += $$PWD/libs/libcapstone-unix-$${QT_ARCH}.a 14 | } 15 | unix:macx { 16 | LIBS += $$PWD/libs/libcapstone-macos-$${QT_ARCH}.a 17 | } 18 | -------------------------------------------------------------------------------- /xcapstone.cmake: -------------------------------------------------------------------------------- 1 | include_directories(${CMAKE_CURRENT_LIST_DIR}) 2 | include_directories(${CMAKE_CURRENT_LIST_DIR}/3rdparty/Capstone/src/include/) 3 | 4 | if (NOT DEFINED XBINARY_SOURCES) 5 | include(${CMAKE_CURRENT_LIST_DIR}/../Formats/xbinary.cmake) 6 | set(XCAPSTONE_SOURCES ${XCAPSTONE_SOURCES} ${XBINARY_SOURCES}) 7 | endif() 8 | 9 | set(XCAPSTONE_SOURCES 10 | ${XCAPSTONE_SOURCES} 11 | ${CMAKE_CURRENT_LIST_DIR}/xcapstone.cpp 12 | ${CMAKE_CURRENT_LIST_DIR}/xcapstone.h 13 | ) 14 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SYSZINSTPRINTER_H 5 | #define CS_SYSZINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void SystemZ_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /3rdparty/Capstone/Capstone_x86.pri: -------------------------------------------------------------------------------- 1 | INCLUDEPATH += $$PWD/src 2 | DEPENDPATH += $$PWD/src 3 | INCLUDEPATH += $$PWD/src/include 4 | DEPENDPATH += $$PWD/src/include 5 | 6 | win32-g++ { 7 | LIBS += $$PWD/libs/libcapstone_x86-win-$${QT_ARCH}.a 8 | } 9 | win32-msvc* { 10 | LIBS += $$PWD/libs/capstone_x86-win-$${QT_ARCH}.lib 11 | } 12 | unix:!macx { 13 | LIBS += $$PWD/libs/libcapstone_x86-unix-$${QT_ARCH}.a 14 | } 15 | unix:macx { 16 | LIBS += $$PWD/libs/libcapstone_x86-macos-$${QT_ARCH}.a 17 | } 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/WASM/WASMInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifndef CS_WASMINSTPRINTER_H 5 | #define CS_WASMINSTPRINTER_H 6 | 7 | 8 | #include "capstone/capstone.h" 9 | #include "../../MCInst.h" 10 | #include "../../SStream.h" 11 | #include "../../cs_priv.h" 12 | 13 | struct SStream; 14 | 15 | void WASM_printInst(MCInst *MI, struct SStream *O, void *Info); 16 | void printOperand(MCInst *MI, unsigned OpNo, SStream *O); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86InstPrinterCommon.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_X86_INSTPRINTERCOMMON_H 5 | #define CS_X86_INSTPRINTERCOMMON_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../SStream.h" 9 | 10 | 11 | void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O); 12 | void printXOPCC(MCInst *MI, unsigned Op, SStream *O); 13 | void printRoundingControl(MCInst *MI, unsigned Op, SStream *O); 14 | 15 | #endif 16 | 17 | -------------------------------------------------------------------------------- /xcapstone.pri: -------------------------------------------------------------------------------- 1 | INCLUDEPATH += $$PWD 2 | DEPENDPATH += $$PWD 3 | 4 | HEADERS += \ 5 | $$PWD/xcapstone.h 6 | 7 | SOURCES += \ 8 | $$PWD/xcapstone.cpp 9 | 10 | !contains(XCONFIG, Capstone) { 11 | XCONFIG += Capstone 12 | include($$PWD/3rdparty/Capstone/Capstone.pri) 13 | } 14 | 15 | !contains(XCONFIG, xbinary) { 16 | XCONFIG += xbinary 17 | include($$PWD/../Formats/xbinary.pri) 18 | } 19 | 20 | DISTFILES += \ 21 | $$PWD/LICENSE \ 22 | $$PWD/README.md \ 23 | $$PWD/xcapstone.cmake 24 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TMS320C64x/TMS320C64xInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifndef CS_TMS320C64XINSTPRINTER_H 5 | #define CS_TMS320C64XINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /xcapstone_x86.pri: -------------------------------------------------------------------------------- 1 | INCLUDEPATH += $$PWD 2 | DEPENDPATH += $$PWD 3 | 4 | HEADERS += \ 5 | $$PWD/xcapstone.h 6 | 7 | SOURCES += \ 8 | $$PWD/xcapstone.cpp 9 | 10 | !contains(XCONFIG, Capstone) { 11 | XCONFIG += Capstone 12 | include($$PWD/3rdparty/Capstone/Capstone_x86.pri) 13 | } 14 | 15 | !contains(XCONFIG, xbinary) { 16 | XCONFIG += xbinary 17 | include($$PWD/../Formats/xbinary.pri) 18 | } 19 | 20 | DISTFILES += \ 21 | $$PWD/LICENSE \ 22 | $$PWD/README.md \ 23 | $$PWD/xcapstone.cmake 24 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/MOS65XX/MOS65XXDisassemblerInternals.h: -------------------------------------------------------------------------------- 1 | #ifndef CS_MOS65XXDISASSEMBLERINTERNALS_H 2 | #define CS_MOS65XXDISASSEMBLERINTERNALS_H 3 | 4 | #include "capstone/mos65xx.h" 5 | 6 | enum { 7 | MOS65XX_CPU_TYPE_6502, 8 | MOS65XX_CPU_TYPE_65C02, 9 | MOS65XX_CPU_TYPE_W65C02, 10 | MOS65XX_CPU_TYPE_65816, 11 | }; 12 | 13 | typedef struct mos65xx_info { 14 | 15 | const char *hex_prefix; 16 | unsigned cpu_type; 17 | unsigned long_m; 18 | unsigned long_x; 19 | 20 | } mos65xx_info; 21 | 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Mips/MipsDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_MIPSDISASSEMBLER_H 5 | #define CS_MIPSDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCInst.h" 9 | #include "../../MCRegisterInfo.h" 10 | 11 | void Mips_init(MCRegisterInfo *MRI); 12 | 13 | bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_PPCDISASSEMBLER_H 5 | #define CS_PPCDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void PPC_init(MCRegisterInfo *MRI); 12 | 13 | bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/SparcInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SPARCINSTPRINTER_H 5 | #define CS_SPARCINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void Sparc_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | void Sparc_addReg(MCInst *MI, int reg); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/SparcDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SPARCDISASSEMBLER_H 5 | #define CS_SPARCDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void Sparc_init(MCRegisterInfo *MRI); 12 | 13 | bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/XCore/XCoreDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_XCOREDISASSEMBLER_H 5 | #define CS_XCOREDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void XCore_init(MCRegisterInfo *MRI); 12 | 13 | bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SYSZDISASSEMBLER_H 5 | #define CS_SYSZDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void SystemZ_init(MCRegisterInfo *MRI); 12 | 13 | bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_TRICOREDISASSEMBLER_H 5 | #define CS_TRICOREDISASSEMBLER_H 6 | 7 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 8 | #include 9 | #endif 10 | 11 | #include 12 | #include "../../MCRegisterInfo.h" 13 | #include "../../MCInst.h" 14 | 15 | void TriCore_init_mri(MCRegisterInfo *MRI); 16 | bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SH/SHDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_SHDISASSEMBLER_H 5 | #define CS_SHDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | typedef struct sh_info { 10 | cs_sh op; 11 | } sh_info; 12 | 13 | bool SH_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | void SH_reg_access(const cs_insn *insn, 17 | cs_regs regs_read, uint8_t *regs_read_count, 18 | cs_regs regs_write, uint8_t *regs_write_count); 19 | #endif 20 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64GenSystemOperands_enum.inc: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | enum PStateValues { 5 | AArch64PState_SPSel = 5, 6 | AArch64PState_DAIFSet = 30, 7 | AArch64PState_DAIFClr = 31, 8 | AArch64PState_PAN = 4, 9 | AArch64PState_UAO = 3, 10 | AArch64PState_DIT = 26, 11 | }; 12 | 13 | enum ExactFPImmValues { 14 | AArch64ExactFPImm_zero = 0, 15 | AArch64ExactFPImm_half = 1, 16 | AArch64ExactFPImm_one = 2, 17 | AArch64ExactFPImm_two = 3, 18 | }; 19 | 20 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/XCore/XCoreInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_XCOREINSTPRINTER_H 5 | #define CS_XCOREINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void XCore_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | // extract details from assembly code @code 16 | void XCore_insn_extract(MCInst *MI, const char *code); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64Disassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_AARCH64_DISASSEMBLER_H 5 | #define CS_AARCH64_DISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void AArch64_init(MCRegisterInfo *MRI); 12 | 13 | bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | uint64_t AArch64_getFeatureBits(int feature); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/EVM/EVMInstPrinter.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #include "EVMInstPrinter.h" 5 | #include "EVMMapping.h" 6 | 7 | 8 | void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) 9 | { 10 | SStream_concat(O, EVM_insn_name((csh)MI->csh, MI->Opcode)); 11 | 12 | if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) { 13 | unsigned int i; 14 | 15 | SStream_concat0(O, "\t"); 16 | for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) { 17 | SStream_concat(O, "%02x", MI->evm_data[i]); 18 | } 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TMS320C64x/TMS320C64xDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifndef CS_TMS320C64XDISASSEMBLER_H 5 | #define CS_TMS320C64XDISASSEMBLER_H 6 | 7 | #include 8 | 9 | #include "capstone/capstone.h" 10 | #include "../../MCRegisterInfo.h" 11 | #include "../../MCInst.h" 12 | 13 | void TMS320C64x_init(MCRegisterInfo *MRI); 14 | 15 | bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, 16 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 17 | 18 | #endif 19 | 20 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/MCInstrDesc.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #include "MCInstrDesc.h" 5 | 6 | /// isPredicate - Set if this is one of the operands that made up of 7 | /// the predicate operand that controls an isPredicable() instruction. 8 | bool MCOperandInfo_isPredicate(const MCOperandInfo *m) 9 | { 10 | return m->Flags & (1 << MCOI_Predicate); 11 | } 12 | 13 | /// isOptionalDef - Set if this operand is a optional def. 14 | /// 15 | bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m) 16 | { 17 | return m->Flags & (1 << MCOI_OptionalDef); 18 | } 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* RISC-V Backend By Rodrigo Cortes Porto & 3 | Shawn Chang , HardenedLinux@2018 */ 4 | 5 | #ifndef CS_RISCVDISASSEMBLER_H 6 | #define CS_RISCVDISASSEMBLER_H 7 | 8 | #include "../../include/capstone/capstone.h" 9 | #include "../../MCRegisterInfo.h" 10 | #include "../../MCInst.h" 11 | 12 | void RISCV_init(MCRegisterInfo *MRI); 13 | 14 | bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, 15 | MCInst *instr, uint16_t *size, uint64_t address, 16 | void *info); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/M680XDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M680X Backend by Wolfgang Schwotzer 2017 */ 3 | 4 | #ifndef CS_M680XDISASSEMBLER_H 5 | #define CS_M680XDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 11 | void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 12 | void M680X_reg_access(const cs_insn *insn, 13 | cs_regs regs_read, uint8_t *regs_read_count, 14 | cs_regs regs_write, uint8_t *regs_write_count); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/hd6301.inc: -------------------------------------------------------------------------------- 1 | 2 | // Additional instructions only supported on HD6301/3 3 | static const inst_pageX g_hd6301_inst_overlay_table[] = { 4 | { 0x18, M680X_INS_XGDX, inh_hid, inh_hid }, 5 | { 0x1a, M680X_INS_SLP, inh_hid, inh_hid }, 6 | { 0x61, M680X_INS_AIM, imm8_hid, idxX_hid }, 7 | { 0x62, M680X_INS_OIM, imm8_hid, idxX_hid }, 8 | { 0x65, M680X_INS_EIM, imm8_hid, idxX_hid }, 9 | { 0x6B, M680X_INS_TIM, imm8_hid, idxX_hid }, 10 | { 0x71, M680X_INS_AIM, imm8_hid, dir_hid }, 11 | { 0x72, M680X_INS_OIM, imm8_hid, dir_hid }, 12 | { 0x75, M680X_INS_EIM, imm8_hid, dir_hid }, 13 | { 0x7B, M680X_INS_TIM, imm8_hid, dir_hid }, 14 | }; 15 | 16 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/ARM/ARMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_ARMDISASSEMBLER_H 5 | #define CS_ARMDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | 10 | void ARM_init(MCRegisterInfo *MRI); 11 | 12 | bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 13 | 14 | bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SH/SHInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Yoshinori Sato, 2022 */ 3 | 4 | #ifndef CS_SHINSTPRINTER_H 5 | #define CS_SHINSTPRINTER_H 6 | 7 | 8 | #include "capstone/capstone.h" 9 | #include "../../utils.h" 10 | #include "../../MCInst.h" 11 | #include "../../SStream.h" 12 | #include "../../cs_priv.h" 13 | #include "SHDisassembler.h" 14 | 15 | struct SStream; 16 | 17 | void SH_printInst(MCInst *MI, struct SStream *O, void *Info); 18 | const char* SH_reg_name(csh handle, unsigned int reg); 19 | void SH_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id); 20 | const char* SH_insn_name(csh handle, unsigned int id); 21 | const char *SH_group_name(csh handle, unsigned int id); 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/BPF/BPFDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CS_BPF_DISASSEMBLER_H 5 | #define CS_BPF_DISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | typedef struct bpf_internal { 10 | uint16_t op; 11 | uint64_t k; 12 | /* for cBPF */ 13 | uint8_t jt; 14 | uint8_t jf; 15 | /* for eBPF */ 16 | uint8_t dst; 17 | uint8_t src; 18 | uint16_t offset; 19 | 20 | /* length of this bpf instruction */ 21 | uint8_t insn_size; 22 | } bpf_internal; 23 | 24 | bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len, 25 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVMapping.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef CS_RISCV_MAP_H 3 | #define CS_RISCV_MAP_H 4 | 5 | #include "../../include/capstone/capstone.h" 6 | 7 | // given internal insn id, return public instruction info 8 | void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id); 9 | 10 | const char *RISCV_insn_name(csh handle, unsigned int id); 11 | 12 | const char *RISCV_group_name(csh handle, unsigned int id); 13 | 14 | const char *RISCV_reg_name(csh handle, unsigned int reg); 15 | 16 | // map instruction name to instruction ID 17 | riscv_reg RISCV_map_insn(const char *name); 18 | 19 | // map internal raw register to 'public' register 20 | riscv_reg RISCV_map_register(unsigned int r); 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/BPF/BPFMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CS_BPFMAPPING_H 5 | #define CS_BPFMAPPING_H 6 | 7 | #include 8 | 9 | #include "../../cs_priv.h" 10 | 11 | #define EBPF_MODE(ud) (((cs_struct*)ud)->mode & CS_MODE_BPF_EXTENDED) 12 | 13 | const char *BPF_group_name(csh handle, unsigned int id); 14 | const char *BPF_insn_name(csh handle, unsigned int id); 15 | const char *BPF_reg_name(csh handle, unsigned int reg); 16 | void BPF_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 17 | void BPF_reg_access(const cs_insn *insn, 18 | cs_regs regs_read, uint8_t *regs_read_count, 19 | cs_regs regs_write, uint8_t *regs_write_count); 20 | 21 | #endif 22 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SYSZ_MAP_H 5 | #define CS_SYSZ_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *SystemZ_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *SystemZ_insn_name(csh handle, unsigned int id); 16 | 17 | const char *SystemZ_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | sysz_reg SystemZ_map_register(unsigned int r); 21 | 22 | #endif 23 | 24 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreLinkage.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_TRICORE_LINKAGE_H 5 | #define CS_TRICORE_LINKAGE_H 6 | 7 | // Function defintions to call static LLVM functions. 8 | 9 | #include "../../MCDisassembler.h" 10 | #include "../../MCInst.h" 11 | #include "../../MCRegisterInfo.h" 12 | #include "../../SStream.h" 13 | #include "capstone/capstone.h" 14 | 15 | bool TriCore_LLVM_getInstruction(csh handle, const uint8_t *Bytes, 16 | size_t ByteLen, MCInst *MI, uint16_t *Size, 17 | uint64_t Address, void *Info); 18 | const char *TriCore_LLVM_getRegisterName(unsigned RegNo); 19 | void TriCore_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O); 20 | 21 | #endif // CS_TRICORE_LINKAGE_H 22 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/M680XInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M680X Backend by Wolfgang Schwotzer 2017 */ 3 | 4 | #ifndef CS_M680XINSTPRINTER_H 5 | #define CS_M680XINSTPRINTER_H 6 | 7 | 8 | #include "capstone/capstone.h" 9 | #include "../../MCRegisterInfo.h" 10 | #include "../../MCInst.h" 11 | 12 | struct SStream; 13 | 14 | void M680X_init(MCRegisterInfo *MRI); 15 | 16 | void M680X_printInst(MCInst *MI, struct SStream *O, void *Info); 17 | const char *M680X_reg_name(csh handle, unsigned int reg); 18 | const char *M680X_insn_name(csh handle, unsigned int id); 19 | const char *M680X_group_name(csh handle, unsigned int id); 20 | void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, 21 | MCInst *mci); 22 | 23 | #endif 24 | 25 | 26 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M68K/M68KInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M68K Backend by Daniel Collin 2015 */ 3 | 4 | #ifndef CS_M68KINSTPRINTER_H 5 | #define CS_M68KINSTPRINTER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | struct SStream; 12 | 13 | void M68K_init(MCRegisterInfo *MRI); 14 | void M68K_printInst(MCInst* MI, struct SStream* O, void* Info); 15 | const char* M68K_reg_name(csh handle, unsigned int reg); 16 | void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id); 17 | const char *M68K_insn_name(csh handle, unsigned int id); 18 | const char* M68K_group_name(csh handle, unsigned int id); 19 | void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci); 20 | 21 | #endif 22 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/EVM/EVMModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifdef CAPSTONE_HAS_EVM 5 | 6 | #include "../../cs_priv.h" 7 | #include "EVMDisassembler.h" 8 | #include "EVMInstPrinter.h" 9 | #include "EVMMapping.h" 10 | #include "EVMModule.h" 11 | 12 | cs_err EVM_global_init(cs_struct *ud) 13 | { 14 | // verify if requested mode is valid 15 | if (ud->mode) 16 | return CS_ERR_MODE; 17 | 18 | ud->printer = EVM_printInst; 19 | ud->printer_info = NULL; 20 | ud->insn_id = EVM_get_insn_id; 21 | ud->insn_name = EVM_insn_name; 22 | ud->group_name = EVM_group_name; 23 | ud->disasm = EVM_getInstruction; 24 | 25 | return CS_ERR_OK; 26 | } 27 | 28 | cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value) 29 | { 30 | return CS_ERR_OK; 31 | } 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Mips/MipsMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_MIPS_MAP_H 5 | #define CS_MIPS_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *Mips_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *Mips_insn_name(csh handle, unsigned int id); 16 | 17 | const char *Mips_group_name(csh handle, unsigned int id); 18 | 19 | // map instruction name to instruction ID 20 | mips_reg Mips_map_insn(const char *name); 21 | 22 | // map internal raw register to 'public' register 23 | mips_reg Mips_map_register(unsigned int r); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/WASM/WASMModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #ifdef CAPSTONE_HAS_WASM 5 | 6 | #include "../../cs_priv.h" 7 | #include "WASMDisassembler.h" 8 | #include "WASMInstPrinter.h" 9 | #include "WASMMapping.h" 10 | #include "WASMModule.h" 11 | 12 | cs_err WASM_global_init(cs_struct *ud) 13 | { 14 | // verify if requested mode is valid 15 | if (ud->mode) 16 | return CS_ERR_MODE; 17 | 18 | ud->printer = WASM_printInst; 19 | ud->printer_info = NULL; 20 | ud->insn_id = WASM_get_insn_id; 21 | ud->insn_name = WASM_insn_name; 22 | ud->group_name = WASM_group_name; 23 | ud->disasm = WASM_getInstruction; 24 | 25 | return CS_ERR_OK; 26 | } 27 | 28 | cs_err WASM_option(cs_struct *handle, cs_opt_type type, size_t value) 29 | { 30 | return CS_ERR_OPTION; 31 | } 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/XCore/XCoreMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_XCORE_MAP_H 5 | #define CS_XCORE_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *XCore_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *XCore_insn_name(csh handle, unsigned int id); 16 | 17 | const char *XCore_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | xcore_reg XCore_map_register(unsigned int r); 21 | 22 | // map register name to register ID 23 | xcore_reg XCore_reg_id(char *name); 24 | 25 | #endif 26 | 27 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/MOS65XX/MOS65XXDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* MOS65XX Backend by Sebastian Macke 2018 */ 3 | 4 | #ifndef CAPSTONE_MOS65XXDISASSEMBLER_H 5 | #define CAPSTONE_MOS65XXDISASSEMBLER_H 6 | 7 | #include "../../utils.h" 8 | 9 | void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo); 10 | 11 | void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 12 | 13 | const char *MOS65XX_insn_name(csh handle, unsigned int id); 14 | 15 | const char *MOS65XX_group_name(csh handle, unsigned int id); 16 | 17 | const char* MOS65XX_reg_name(csh handle, unsigned int reg); 18 | 19 | bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len, 20 | MCInst *MI, uint16_t *size, uint64_t address, void *inst_info); 21 | 22 | #endif //CAPSTONE_MOS65XXDISASSEMBLER_H 23 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVInstPrinter.h: -------------------------------------------------------------------------------- 1 | //===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints a RISCV MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef CS_RISCVINSTPRINTER_H 15 | #define CS_RISCVINSTPRINTER_H 16 | 17 | #include "../../MCInst.h" 18 | #include "../../SStream.h" 19 | 20 | void RISCV_printInst(MCInst * MI, SStream * O, void *info); 21 | 22 | void RISCV_post_printer(csh ud, cs_insn * insn, char *insn_asm, MCInst * mci); 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Mips/MipsInstPrinter.h: -------------------------------------------------------------------------------- 1 | //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints a Mips MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2015 */ 16 | 17 | #ifndef CS_MIPSINSTPRINTER_H 18 | #define CS_MIPSINSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../SStream.h" 22 | 23 | void Mips_printInst(MCInst *MI, SStream *O, void *info); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/BPF/BPFModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifdef CAPSTONE_HAS_BPF 5 | 6 | #include "BPFDisassembler.h" 7 | #include "BPFInstPrinter.h" 8 | #include "BPFMapping.h" 9 | #include "BPFModule.h" 10 | 11 | cs_err BPF_global_init(cs_struct *ud) 12 | { 13 | ud->printer = BPF_printInst; 14 | ud->reg_name = BPF_reg_name; 15 | ud->insn_id = BPF_get_insn_id; 16 | ud->insn_name = BPF_insn_name; 17 | ud->group_name = BPF_group_name; 18 | #ifndef CAPSTONE_DIET 19 | ud->reg_access = BPF_reg_access; 20 | #endif 21 | ud->disasm = BPF_getInstruction; 22 | 23 | return CS_ERR_OK; 24 | } 25 | 26 | cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value) 27 | { 28 | if (type == CS_OPT_MODE) 29 | handle->mode = (cs_mode)value; 30 | 31 | return CS_ERR_OK; 32 | } 33 | 34 | #endif 35 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SH/SHModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Yoshinori Sato 2022 */ 3 | 4 | #ifdef CAPSTONE_HAS_SH 5 | 6 | #include "../../cs_priv.h" 7 | #include "SHDisassembler.h" 8 | #include "SHInstPrinter.h" 9 | #include "SHModule.h" 10 | 11 | cs_err SH_global_init(cs_struct *ud) 12 | { 13 | sh_info *info; 14 | 15 | info = cs_mem_malloc(sizeof(sh_info)); 16 | if (!info) { 17 | return CS_ERR_MEM; 18 | } 19 | 20 | ud->printer = SH_printInst; 21 | ud->printer_info = info; 22 | ud->reg_name = SH_reg_name; 23 | ud->insn_id = SH_get_insn_id; 24 | ud->insn_name = SH_insn_name; 25 | ud->group_name = SH_group_name; 26 | ud->disasm = SH_getInstruction; 27 | #ifndef CAPSTONE_DIET 28 | ud->reg_access = SH_reg_access; 29 | #endif 30 | 31 | return CS_ERR_OK; 32 | } 33 | 34 | cs_err SH_option(cs_struct *handle, cs_opt_type type, size_t value) 35 | { 36 | return CS_ERR_OK; 37 | } 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TMS320C64x/TMS320C64xMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifndef CS_TMS320C64X_MAP_H 5 | #define CS_TMS320C64X_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *TMS320C64x_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *TMS320C64x_insn_name(csh handle, unsigned int id); 16 | 17 | const char *TMS320C64x_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | tms320c64x_reg TMS320C64x_map_register(unsigned int r); 21 | 22 | // map register name to register ID 23 | tms320c64x_reg TMS320C64x_reg_id(char *name); 24 | 25 | #endif 26 | 27 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreGenCSFeatureName.inc: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 2 | /* By Nguyen Anh Quynh , 2013-2022, */ 3 | /* Rot127 2022-2023 */ 4 | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ 5 | 6 | /* LLVM-commit: */ 7 | /* LLVM-tag: */ 8 | 9 | /* Do not edit. */ 10 | 11 | /* Capstone's LLVM TableGen Backends: */ 12 | /* https://github.com/capstone-engine/llvm-capstone */ 13 | 14 | { TRICORE_FEATURE_HasV110, "HasV110" }, 15 | { TRICORE_FEATURE_HasV120_UP, "HasV120_UP" }, 16 | { TRICORE_FEATURE_HasV130_UP, "HasV130_UP" }, 17 | { TRICORE_FEATURE_HasV161, "HasV161" }, 18 | { TRICORE_FEATURE_HasV160_UP, "HasV160_UP" }, 19 | { TRICORE_FEATURE_HasV131_UP, "HasV131_UP" }, 20 | { TRICORE_FEATURE_HasV161_UP, "HasV161_UP" }, 21 | { TRICORE_FEATURE_HasV162, "HasV162" }, 22 | { TRICORE_FEATURE_HasV162_UP, "HasV162_UP" }, 23 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86Disassembler.h: -------------------------------------------------------------------------------- 1 | //===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | /* Capstone Disassembly Engine */ 11 | /* By Nguyen Anh Quynh , 2013-2019 */ 12 | 13 | #ifndef CS_X86_DISASSEMBLER_H 14 | #define CS_X86_DISASSEMBLER_H 15 | 16 | #include "capstone/capstone.h" 17 | 18 | #include "../../MCInst.h" 19 | 20 | #include "../../MCRegisterInfo.h" 21 | #include "X86DisassemblerDecoderCommon.h" 22 | 23 | bool X86_getInstruction(csh handle, const uint8_t *code, size_t code_len, 24 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 25 | 26 | void X86_init(MCRegisterInfo *MRI); 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86InstPrinter.h: -------------------------------------------------------------------------------- 1 | //= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an X86 MCInst to Intel style .s file syntax. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2019 */ 16 | 17 | #ifndef CS_X86_INSTPRINTER_H 18 | #define CS_X86_INSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../SStream.h" 22 | 23 | void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info); 24 | void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info); 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64InstPrinter.h: -------------------------------------------------------------------------------- 1 | //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an AArch64 MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2019 */ 16 | 17 | #ifndef CS_LLVM_AARCH64INSTPRINTER_H 18 | #define CS_LLVM_AARCH64INSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../MCRegisterInfo.h" 22 | #include "../../SStream.h" 23 | 24 | void AArch64_printInst(MCInst *MI, SStream *O, void *); 25 | 26 | void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M68K/M68KModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M68K Backend by Daniel Collin 2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_M68K 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "M68KDisassembler.h" 9 | #include "M68KInstPrinter.h" 10 | #include "M68KModule.h" 11 | 12 | cs_err M68K_global_init(cs_struct *ud) 13 | { 14 | m68k_info *info; 15 | 16 | info = cs_mem_malloc(sizeof(m68k_info)); 17 | if (!info) { 18 | return CS_ERR_MEM; 19 | } 20 | 21 | ud->printer = M68K_printInst; 22 | ud->printer_info = info; 23 | ud->getinsn_info = NULL; 24 | ud->disasm = M68K_getInstruction; 25 | ud->skipdata_size = 2; 26 | ud->post_printer = NULL; 27 | 28 | ud->reg_name = M68K_reg_name; 29 | ud->insn_id = M68K_get_insn_id; 30 | ud->insn_name = M68K_insn_name; 31 | ud->group_name = M68K_group_name; 32 | 33 | return CS_ERR_OK; 34 | } 35 | 36 | cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value) 37 | { 38 | return CS_ERR_OK; 39 | } 40 | 41 | #endif 42 | 43 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/SStream.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_SSTREAM_H_ 5 | #define CS_SSTREAM_H_ 6 | 7 | #include "include/capstone/platform.h" 8 | 9 | typedef struct SStream { 10 | char buffer[512]; 11 | int index; 12 | } SStream; 13 | 14 | void SStream_Init(SStream *ss); 15 | 16 | void SStream_concat(SStream *ss, const char *fmt, ...); 17 | 18 | void SStream_concat0(SStream *ss, const char *s); 19 | 20 | void SStream_concat1(SStream *ss, const char c); 21 | 22 | void printInt64Bang(SStream *O, int64_t val); 23 | 24 | void printUInt64Bang(SStream *O, uint64_t val); 25 | 26 | void printInt64(SStream *O, int64_t val); 27 | void printUInt64(SStream *O, uint64_t val); 28 | 29 | void printInt32Bang(SStream *O, int32_t val); 30 | 31 | void printInt32(SStream *O, int32_t val); 32 | 33 | void printUInt32Bang(SStream *O, uint32_t val); 34 | 35 | void printUInt32(SStream *O, uint32_t val); 36 | 37 | // print number in decimal mode 38 | void printInt32BangDec(SStream *O, int32_t val); 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_TRICORE_MAP_H 5 | #define CS_TRICORE_MAP_H 6 | 7 | #include 8 | 9 | // given internal insn id, return public instruction info 10 | void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 11 | 12 | const char *TriCore_insn_name(csh handle, unsigned int id); 13 | 14 | const char *TriCore_group_name(csh handle, unsigned int id); 15 | 16 | void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read, 17 | uint8_t *regs_read_count, cs_regs regs_write, 18 | uint8_t *regs_write_count); 19 | 20 | void TriCore_set_access(MCInst *MI); 21 | 22 | void TriCore_set_instr_map_data(MCInst *MI); 23 | 24 | bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen, 25 | MCInst *MI, uint16_t *Size, uint64_t Address, 26 | void *Info); 27 | 28 | void TriCore_printInst(MCInst *MI, SStream *O, void *Info); 29 | 30 | const char *TriCore_getRegisterName(csh handle, unsigned int RegNo); 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/SparcMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SPARC_MAP_H 5 | #define CS_SPARC_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *Sparc_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *Sparc_insn_name(csh handle, unsigned int id); 16 | 17 | const char *Sparc_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | sparc_reg Sparc_map_register(unsigned int r); 21 | 22 | // map instruction name to instruction ID (public) 23 | // this is for alias instructions only 24 | sparc_reg Sparc_map_insn(const char *name); 25 | 26 | // map CC string to CC id 27 | sparc_cc Sparc_map_ICC(const char *name); 28 | 29 | sparc_cc Sparc_map_FCC(const char *name); 30 | 31 | sparc_hint Sparc_map_hint(const char *name); 32 | 33 | #endif 34 | 35 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifdef CAPSTONE_HAS_TRICORE 5 | 6 | #include "../../utils.h" 7 | #include "TriCoreMapping.h" 8 | #include "TriCoreModule.h" 9 | #include "TriCoreDisassembler.h" 10 | 11 | cs_err TRICORE_global_init(cs_struct *ud) 12 | { 13 | MCRegisterInfo *mri; 14 | 15 | mri = cs_mem_malloc(sizeof(*mri)); 16 | 17 | TriCore_init_mri(mri); 18 | ud->printer = TriCore_printInst; 19 | ud->printer_info = mri; 20 | ud->getinsn_info = mri; 21 | ud->disasm = TriCore_getInstruction; 22 | ud->post_printer = NULL; 23 | 24 | ud->reg_name = TriCore_getRegisterName; 25 | ud->insn_id = TriCore_get_insn_id; 26 | ud->insn_name = TriCore_insn_name; 27 | ud->group_name = TriCore_group_name; 28 | 29 | #ifndef CAPSTONE_DIET 30 | ud->reg_access = TriCore_reg_access; 31 | #endif 32 | 33 | return CS_ERR_OK; 34 | } 35 | 36 | cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value) 37 | { 38 | if (type == CS_OPT_SYNTAX) 39 | handle->syntax = (int)value; 40 | 41 | return CS_ERR_OK; 42 | } 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019-2025 hors 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TMS320C64x/TMS320C64xModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifdef CAPSTONE_HAS_TMS320C64X 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "TMS320C64xDisassembler.h" 9 | #include "TMS320C64xInstPrinter.h" 10 | #include "TMS320C64xMapping.h" 11 | #include "TMS320C64xModule.h" 12 | 13 | cs_err TMS320C64x_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | 17 | mri = cs_mem_malloc(sizeof(*mri)); 18 | 19 | TMS320C64x_init(mri); 20 | ud->printer = TMS320C64x_printInst; 21 | ud->printer_info = mri; 22 | ud->getinsn_info = mri; 23 | ud->disasm = TMS320C64x_getInstruction; 24 | ud->post_printer = TMS320C64x_post_printer; 25 | 26 | ud->reg_name = TMS320C64x_reg_name; 27 | ud->insn_id = TMS320C64x_get_insn_id; 28 | ud->insn_name = TMS320C64x_insn_name; 29 | ud->group_name = TMS320C64x_group_name; 30 | 31 | return CS_ERR_OK; 32 | } 33 | 34 | cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value) 35 | { 36 | return CS_ERR_OK; 37 | } 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* RISC-V Backend By Rodrigo Cortes Porto & 3 | Shawn Chang , HardenedLinux@2018 */ 4 | 5 | #ifdef CAPSTONE_HAS_RISCV 6 | 7 | #include "../../utils.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "RISCVDisassembler.h" 10 | #include "RISCVInstPrinter.h" 11 | #include "RISCVMapping.h" 12 | #include "RISCVModule.h" 13 | 14 | cs_err RISCV_global_init(cs_struct * ud) 15 | { 16 | MCRegisterInfo *mri; 17 | mri = cs_mem_malloc(sizeof(*mri)); 18 | 19 | RISCV_init(mri); 20 | ud->printer = RISCV_printInst; 21 | ud->printer_info = mri; 22 | ud->getinsn_info = mri; 23 | ud->disasm = RISCV_getInstruction; 24 | ud->post_printer = NULL; 25 | 26 | ud->reg_name = RISCV_reg_name; 27 | ud->insn_id = RISCV_get_insn_id; 28 | ud->insn_name = RISCV_insn_name; 29 | ud->group_name = RISCV_group_name; 30 | 31 | return CS_ERR_OK; 32 | } 33 | 34 | cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value) 35 | { 36 | if (type == CS_OPT_SYNTAX) 37 | handle->syntax = (int)value; 38 | 39 | return CS_ERR_OK; 40 | } 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/XCore/XCoreModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_XCORE 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "XCoreDisassembler.h" 9 | #include "XCoreInstPrinter.h" 10 | #include "XCoreMapping.h" 11 | #include "XCoreModule.h" 12 | 13 | cs_err XCore_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | XCore_init(mri); 19 | ud->printer = XCore_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = XCore_getInstruction; 23 | ud->post_printer = XCore_post_printer; 24 | 25 | ud->reg_name = XCore_reg_name; 26 | ud->insn_id = XCore_get_insn_id; 27 | ud->insn_name = XCore_insn_name; 28 | ud->group_name = XCore_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot 36 | // test for CS_MODE_LITTLE_ENDIAN because it is 0 37 | 38 | return CS_ERR_OK; 39 | } 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/SparcGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2015 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | Sparc_FeatureHardQuad = 1ULL << 0, 18 | Sparc_FeatureV8Deprecated = 1ULL << 1, 19 | Sparc_FeatureV9 = 1ULL << 2, 20 | Sparc_FeatureVIS = 1ULL << 3, 21 | Sparc_FeatureVIS2 = 1ULL << 4, 22 | Sparc_FeatureVIS3 = 1ULL << 5, 23 | Sparc_UsePopc = 1ULL << 6 24 | }; 25 | 26 | #endif // GET_SUBTARGETINFO_ENUM 27 | 28 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_POWERPC 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "PPCDisassembler.h" 9 | #include "PPCInstPrinter.h" 10 | #include "PPCMapping.h" 11 | #include "PPCModule.h" 12 | 13 | cs_err PPC_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri)); 17 | 18 | PPC_init(mri); 19 | ud->printer = PPC_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = PPC_getInstruction; 23 | ud->post_printer = PPC_post_printer; 24 | 25 | ud->reg_name = PPC_reg_name; 26 | ud->insn_id = PPC_get_insn_id; 27 | ud->insn_name = PPC_insn_name; 28 | ud->group_name = PPC_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | if (type == CS_OPT_MODE) { 39 | handle->mode = (cs_mode)value; 40 | } 41 | 42 | return CS_ERR_OK; 43 | } 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/SparcModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_SPARC 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "SparcDisassembler.h" 9 | #include "SparcInstPrinter.h" 10 | #include "SparcMapping.h" 11 | #include "SparcModule.h" 12 | 13 | cs_err Sparc_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | Sparc_init(mri); 19 | ud->printer = Sparc_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = Sparc_getInstruction; 23 | ud->post_printer = Sparc_post_printer; 24 | 25 | ud->reg_name = Sparc_reg_name; 26 | ud->insn_id = Sparc_get_insn_id; 27 | ud->insn_name = Sparc_insn_name; 28 | ud->group_name = Sparc_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | if (type == CS_OPT_MODE) { 39 | handle->mode = (cs_mode)value; 40 | } 41 | 42 | return CS_ERR_OK; 43 | } 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M68K/M68KDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M68K Backend by Daniel Collin 2015-2016 */ 3 | 4 | #ifndef CS_M68KDISASSEMBLER_H 5 | #define CS_M68KDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | /* Private, For internal use only */ 10 | typedef struct m68k_info { 11 | const uint8_t *code; 12 | size_t code_len; 13 | uint64_t baseAddress; 14 | MCInst *inst; 15 | unsigned int pc; /* program counter */ 16 | unsigned int ir; /* instruction register */ 17 | unsigned int type; 18 | unsigned int address_mask; /* Address mask to simulate address lines */ 19 | cs_m68k extension; 20 | uint16_t regs_read[20]; // list of implicit registers read by this insn 21 | uint8_t regs_read_count; // number of implicit registers read by this insn 22 | uint16_t regs_write[20]; // list of implicit registers modified by this insn 23 | uint8_t regs_write_count; // number of implicit registers modified by this insn 24 | uint8_t groups[8]; 25 | uint8_t groups_count; 26 | } m68k_info; 27 | 28 | bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info); 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64Module.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_ARM64 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "AArch64Disassembler.h" 9 | #include "AArch64InstPrinter.h" 10 | #include "AArch64Mapping.h" 11 | #include "AArch64Module.h" 12 | 13 | cs_err AArch64_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | AArch64_init(mri); 19 | ud->printer = AArch64_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = AArch64_getInstruction; 23 | ud->reg_name = AArch64_reg_name; 24 | ud->insn_id = AArch64_get_insn_id; 25 | ud->insn_name = AArch64_insn_name; 26 | ud->group_name = AArch64_group_name; 27 | ud->post_printer = AArch64_post_printer; 28 | #ifndef CAPSTONE_DIET 29 | ud->reg_access = AArch64_reg_access; 30 | #endif 31 | 32 | return CS_ERR_OK; 33 | } 34 | 35 | cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value) 36 | { 37 | if (type == CS_OPT_MODE) { 38 | handle->mode = (cs_mode)value; 39 | } 40 | 41 | return CS_ERR_OK; 42 | } 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 2 | /* By Nguyen Anh Quynh , 2013-2022, */ 3 | /* Rot127 2022-2023 */ 4 | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ 5 | 6 | /* LLVM-commit: */ 7 | /* LLVM-tag: */ 8 | 9 | /* Do not edit. */ 10 | 11 | /* Capstone's LLVM TableGen Backends: */ 12 | /* https://github.com/capstone-engine/llvm-capstone */ 13 | 14 | #ifdef GET_SUBTARGETINFO_ENUM 15 | #undef GET_SUBTARGETINFO_ENUM 16 | 17 | enum { 18 | TRICORE_HasV110Ops = 0, 19 | TRICORE_HasV120Ops = 1, 20 | TRICORE_HasV130Ops = 2, 21 | TRICORE_HasV131Ops = 3, 22 | TRICORE_HasV160Ops = 4, 23 | TRICORE_HasV161Ops = 5, 24 | TRICORE_HasV162Ops = 6, 25 | TRICORE_TRICORE_PCP = 7, 26 | TRICORE_TRICORE_PCP2 = 8, 27 | TRICORE_TRICORE_RIDER_A = 9, 28 | TRICORE_TRICORE_V1_1 = 10, 29 | TRICORE_TRICORE_V1_2 = 11, 30 | TRICORE_TRICORE_V1_3 = 12, 31 | TRICORE_TRICORE_V1_3_1 = 13, 32 | TRICORE_TRICORE_V1_6 = 14, 33 | TRICORE_TRICORE_V1_6_1 = 15, 34 | TRICORE_TRICORE_V1_6_2 = 16, 35 | TRICORE_NumSubtargetFeatures = 17 36 | }; 37 | #endif // GET_SUBTARGETINFO_ENUM 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreGenCSOpGroup.inc: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 2 | /* By Nguyen Anh Quynh , 2013-2022, */ 3 | /* Rot127 2022-2023 */ 4 | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ 5 | 6 | /* LLVM-commit: */ 7 | /* LLVM-tag: */ 8 | 9 | /* Do not edit. */ 10 | 11 | /* Capstone's LLVM TableGen Backends: */ 12 | /* https://github.com/capstone-engine/llvm-capstone */ 13 | 14 | TRICORE_OP_GROUP_RegImmShift = 0, 15 | TRICORE_OP_GROUP_LdStmModeOperand = 1, 16 | TRICORE_OP_GROUP_MandatoryInvertedPredicateOperand = 2, 17 | TRICORE_OP_GROUP_Operand = 3, 18 | TRICORE_OP_GROUP_SExtImm_9 = 4, 19 | TRICORE_OP_GROUP_ZExtImm_16 = 5, 20 | TRICORE_OP_GROUP_SExtImm_16 = 6, 21 | TRICORE_OP_GROUP_ZExtImm_2 = 7, 22 | TRICORE_OP_GROUP_SExtImm_4 = 8, 23 | TRICORE_OP_GROUP_ZExtImm_4 = 9, 24 | TRICORE_OP_GROUP_ZExtImm_8 = 10, 25 | TRICORE_OP_GROUP_SExtImm_10 = 11, 26 | TRICORE_OP_GROUP_Disp24Imm = 12, 27 | TRICORE_OP_GROUP_Disp8Imm = 13, 28 | TRICORE_OP_GROUP_Disp15Imm = 14, 29 | TRICORE_OP_GROUP_Disp4Imm = 15, 30 | TRICORE_OP_GROUP_Off18Imm = 16, 31 | TRICORE_OP_GROUP_OExtImm_4 = 17, 32 | TRICORE_OP_GROUP_ZExtImm_9 = 18, 33 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/LEB128.h: -------------------------------------------------------------------------------- 1 | //===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file declares some utility functions for encoding SLEB128 and 11 | // ULEB128 values. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | /* Capstone Disassembly Engine */ 16 | /* By Nguyen Anh Quynh , 2013-2019 */ 17 | 18 | #ifndef CS_LLVM_SUPPORT_LEB128_H 19 | #define CS_LLVM_SUPPORT_LEB128_H 20 | 21 | #include "include/capstone/capstone.h" 22 | 23 | /// Utility function to decode a ULEB128 value. 24 | static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) 25 | { 26 | const uint8_t *orig_p = p; 27 | uint64_t Value = 0; 28 | unsigned Shift = 0; 29 | do { 30 | Value += (uint64_t)(*p & 0x7f) << Shift; 31 | Shift += 7; 32 | } while (*p++ >= 128); 33 | if (n) 34 | *n = (unsigned)(p - orig_p); 35 | return Value; 36 | } 37 | 38 | #endif // LLVM_SYSTEM_LEB128_H 39 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_SYSZ 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "SystemZDisassembler.h" 9 | #include "SystemZInstPrinter.h" 10 | #include "SystemZMapping.h" 11 | #include "SystemZModule.h" 12 | 13 | cs_err SystemZ_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | SystemZ_init(mri); 19 | ud->printer = SystemZ_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = SystemZ_getInstruction; 23 | ud->post_printer = SystemZ_post_printer; 24 | 25 | ud->reg_name = SystemZ_reg_name; 26 | ud->insn_id = SystemZ_get_insn_id; 27 | ud->insn_name = SystemZ_insn_name; 28 | ud->group_name = SystemZ_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot 39 | // test for CS_MODE_LITTLE_ENDIAN because it is 0 40 | 41 | return CS_ERR_OK; 42 | } 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Mips/MipsModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_MIPS 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "MipsDisassembler.h" 9 | #include "MipsInstPrinter.h" 10 | #include "MipsMapping.h" 11 | #include "MipsModule.h" 12 | 13 | // Returns mode value with implied bits set 14 | static cs_mode updated_mode(cs_mode mode) 15 | { 16 | if (mode & CS_MODE_MIPS32R6) { 17 | mode |= CS_MODE_32; 18 | } 19 | 20 | return mode; 21 | } 22 | 23 | cs_err Mips_global_init(cs_struct *ud) 24 | { 25 | MCRegisterInfo *mri; 26 | mri = cs_mem_malloc(sizeof(*mri)); 27 | 28 | Mips_init(mri); 29 | ud->printer = Mips_printInst; 30 | ud->printer_info = mri; 31 | ud->getinsn_info = mri; 32 | ud->reg_name = Mips_reg_name; 33 | ud->insn_id = Mips_get_insn_id; 34 | ud->insn_name = Mips_insn_name; 35 | ud->group_name = Mips_group_name; 36 | 37 | ud->disasm = Mips_getInstruction; 38 | 39 | return CS_ERR_OK; 40 | } 41 | 42 | cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) 43 | { 44 | if (type == CS_OPT_MODE) { 45 | handle->mode = updated_mode(value); 46 | return CS_ERR_OK; 47 | } 48 | 49 | return CS_ERR_OPTION; 50 | } 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |* Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2015 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | /* 17 | Make sure: 18 | CS_MODE_RISCV64 = 0b11111 19 | CS_MODE_RISCV32 = 0b11110 20 | */ 21 | 22 | enum { 23 | RISCV_Feature64Bit = 1ULL << 0, 24 | RISCV_FeatureStdExtA = 1ULL << 1, 25 | RISCV_FeatureStdExtC = 1ULL << 2, 26 | RISCV_FeatureStdExtD = 1ULL << 3, 27 | RISCV_FeatureStdExtF = 1ULL << 4, 28 | RISCV_FeatureStdExtM = 1ULL << 5, 29 | RISCV_FeatureRelax = 1ULL << 6, 30 | }; 31 | 32 | #endif // GET_SUBTARGETINFO_ENUM 33 | 34 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_PPC_MAP_H 5 | #define CS_PPC_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *PPC_reg_name(csh handle, unsigned int reg); 11 | 12 | // return register id, given register name 13 | ppc_reg PPC_name_reg(const char *name); 14 | 15 | // given internal insn id, return public instruction info 16 | void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 17 | 18 | const char *PPC_insn_name(csh handle, unsigned int id); 19 | const char *PPC_group_name(csh handle, unsigned int id); 20 | 21 | struct ppc_alias { 22 | unsigned int id; // instruction id 23 | int cc; // code condition 24 | const char *mnem; 25 | }; 26 | 27 | // map instruction name to public instruction ID 28 | ppc_insn PPC_map_insn(const char *name); 29 | 30 | // check if this insn is relative branch 31 | bool PPC_abs_branch(cs_struct *h, unsigned int id); 32 | 33 | // map internal raw register to 'public' register 34 | ppc_reg PPC_map_register(unsigned int r); 35 | 36 | // given alias mnemonic, return instruction ID & CC 37 | bool PPC_alias_insn(const char *name, struct ppc_alias *alias); 38 | 39 | #endif 40 | 41 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/ARM/ARMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_ARM_MAP_H 5 | #define CS_ARM_MAP_H 6 | 7 | #include "../../include/capstone/capstone.h" 8 | #include "../../utils.h" 9 | 10 | // return name of regiser in friendly string 11 | const char *ARM_reg_name(csh handle, unsigned int reg); 12 | const char *ARM_reg_name2(csh handle, unsigned int reg); 13 | 14 | // given internal insn id, return public instruction ID 15 | void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 16 | 17 | const char *ARM_insn_name(csh handle, unsigned int id); 18 | 19 | const char *ARM_group_name(csh handle, unsigned int id); 20 | 21 | // check if this insn is relative branch 22 | bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); 23 | 24 | bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); 25 | 26 | const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); 27 | 28 | void ARM_reg_access(const cs_insn *insn, 29 | cs_regs regs_read, uint8_t *regs_read_count, 30 | cs_regs regs_write, uint8_t *regs_write_count); 31 | 32 | typedef struct BankedReg { 33 | const char *Name; 34 | arm_sysreg sysreg; 35 | uint16_t Encoding; 36 | } BankedReg; 37 | 38 | const BankedReg *lookupBankedRegByEncoding(uint8_t encoding); 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/WASM/WASMInstPrinter.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Spike, xwings 2019 */ 3 | 4 | #include "WASMInstPrinter.h" 5 | #include "WASMMapping.h" 6 | 7 | 8 | void WASM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) 9 | { 10 | SStream_concat(O, WASM_insn_name((csh)MI->csh, MI->Opcode)); 11 | 12 | switch (MI->wasm_data.type) { 13 | default: 14 | break; 15 | 16 | case WASM_OP_VARUINT32: 17 | SStream_concat(O, "\t0x%x", MI->wasm_data.varuint32); 18 | break; 19 | 20 | case WASM_OP_VARUINT64: 21 | SStream_concat(O, "\t0x%lx", MI->wasm_data.varuint64); 22 | break; 23 | 24 | case WASM_OP_UINT32: 25 | SStream_concat(O, "\t0x%2" PRIx32, MI->wasm_data.uint32); 26 | break; 27 | 28 | case WASM_OP_UINT64: 29 | SStream_concat(O, "\t0x%2" PRIx64, MI->wasm_data.uint64); 30 | break; 31 | 32 | case WASM_OP_IMM: 33 | SStream_concat(O, "\t0x%x, 0x%x", MI->wasm_data.immediate[0], MI->wasm_data.immediate[1]); 34 | break; 35 | 36 | case WASM_OP_INT7: 37 | SStream_concat(O, "\t%d", MI->wasm_data.int7); 38 | break; 39 | 40 | case WASM_OP_BRTABLE: 41 | SStream_concat(O, "\t0x%x, [", MI->wasm_data.brtable.length); 42 | SStream_concat(O, "0x%x", MI->wasm_data.brtable.address); 43 | SStream_concat(O, "], 0x%x", MI->wasm_data.brtable.default_target); 44 | 45 | break; 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64Mapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_ARM64_MAP_H 5 | #define CS_ARM64_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) 10 | 11 | // return name of regiser in friendly string 12 | const char *AArch64_reg_name(csh handle, unsigned int reg); 13 | 14 | // given internal insn id, return public instruction info 15 | void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 16 | 17 | const char *AArch64_insn_name(csh handle, unsigned int id); 18 | 19 | const char *AArch64_group_name(csh handle, unsigned int id); 20 | 21 | // map instruction name to public instruction ID 22 | arm64_insn AArch64_map_insn(const char *name); 23 | 24 | // map internal vregister to public register 25 | arm64_reg AArch64_map_vregister(unsigned int r); 26 | 27 | void arm64_op_addReg(MCInst *MI, int reg); 28 | 29 | void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); 30 | 31 | void arm64_op_addFP(MCInst *MI, float fp); 32 | 33 | void arm64_op_addImm(MCInst *MI, int64_t imm); 34 | 35 | const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id); 36 | 37 | void AArch64_reg_access(const cs_insn *insn, 38 | cs_regs regs_read, uint8_t *regs_read_count, 39 | cs_regs regs_write, uint8_t *regs_write_count); 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/ARM/ARMInstPrinter.h: -------------------------------------------------------------------------------- 1 | //===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an ARM MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2019 */ 16 | 17 | #ifndef CS_ARMINSTPRINTER_H 18 | #define CS_ARMINSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../MCRegisterInfo.h" 22 | #include "../../SStream.h" 23 | 24 | void ARM_printInst(MCInst *MI, SStream *O, void *Info); 25 | void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci); 26 | 27 | // setup handle->get_regname 28 | void ARM_getRegName(cs_struct *handle, int value); 29 | 30 | // specify vector data type for vector instructions 31 | void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd); 32 | 33 | void ARM_addVectorDataSize(MCInst *MI, int size); 34 | 35 | void ARM_addReg(MCInst *MI, int reg); 36 | 37 | // load usermode registers (LDM, STM) 38 | void ARM_addUserMode(MCInst *MI); 39 | 40 | // sysreg for MRS/MSR 41 | void ARM_addSysReg(MCInst *MI, arm_sysreg reg); 42 | 43 | #endif 44 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/MCFixedLenDisassembler.h: -------------------------------------------------------------------------------- 1 | //===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // Fixed length disassembler decoder state machine driver. 10 | //===----------------------------------------------------------------------===// 11 | 12 | /* Capstone Disassembly Engine */ 13 | /* By Nguyen Anh Quynh , 2013-2019 */ 14 | 15 | #ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H 16 | #define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H 17 | 18 | // Disassembler state machine opcodes. 19 | enum DecoderOps { 20 | MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len) 21 | MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip) 22 | MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len, 23 | // uleb128 Val, uint16_t NumToSkip) 24 | MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip) 25 | MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx) 26 | MCD_OPC_TryDecode, // OPC_TryDecode(uleb128 Opcode, uleb128 DIdx, 27 | // uint16_t NumToSkip) 28 | MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask) 29 | MCD_OPC_Fail // OPC_Fail() 30 | }; 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/ARM/ARMModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_ARM 5 | 6 | #include "../../cs_priv.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "ARMDisassembler.h" 9 | #include "ARMInstPrinter.h" 10 | #include "ARMMapping.h" 11 | #include "ARMModule.h" 12 | 13 | cs_err ARM_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | ARM_init(mri); 19 | ARM_getRegName(ud, 0); // use default get_regname 20 | 21 | ud->printer = ARM_printInst; 22 | ud->printer_info = mri; 23 | ud->reg_name = ARM_reg_name; 24 | ud->insn_id = ARM_get_insn_id; 25 | ud->insn_name = ARM_insn_name; 26 | ud->group_name = ARM_group_name; 27 | ud->post_printer = ARM_post_printer; 28 | #ifndef CAPSTONE_DIET 29 | ud->reg_access = ARM_reg_access; 30 | #endif 31 | 32 | if (ud->mode & CS_MODE_THUMB) 33 | ud->disasm = Thumb_getInstruction; 34 | else 35 | ud->disasm = ARM_getInstruction; 36 | 37 | return CS_ERR_OK; 38 | } 39 | 40 | cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value) 41 | { 42 | switch(type) { 43 | case CS_OPT_MODE: 44 | if (value & CS_MODE_THUMB) 45 | handle->disasm = Thumb_getInstruction; 46 | else 47 | handle->disasm = ARM_getInstruction; 48 | 49 | handle->mode = (cs_mode)value; 50 | 51 | break; 52 | case CS_OPT_SYNTAX: 53 | ARM_getRegName(handle, (int)value); 54 | handle->syntax = (int)value; 55 | break; 56 | default: 57 | break; 58 | } 59 | 60 | return CS_ERR_OK; 61 | } 62 | 63 | #endif 64 | -------------------------------------------------------------------------------- /x86/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.14) 2 | 3 | project(capstone_x86 LANGUAGES C) 4 | 5 | set(CMAKE_INCLUDE_CURRENT_DIR ON) 6 | set(CMAKE_CXX_STANDARD 11) 7 | set(CMAKE_CXX_STANDARD_REQUIRED ON) 8 | set(CMAKE_POSITION_INDEPENDENT_CODE ON) 9 | 10 | message(${PROJECT_SOURCE_DIR}) 11 | 12 | if(WIN32) 13 | add_definitions(-DWIN32) 14 | endif() 15 | 16 | add_definitions( 17 | -DCAPSTONE_HAS_X86 18 | -DCAPSTONE_X86_ATT_DISABLE 19 | -DCAPSTONE_X86_REDUCE 20 | -DCAPSTONE_DIET_NO 21 | -DCAPSTONE_USE_SYS_DYN_MEM 22 | -D_LIB 23 | ) 24 | 25 | include_directories(${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/include) 26 | 27 | add_library(capstone_x86 STATIC 28 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/MCInst.c 29 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/MCInstrDesc.c 30 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/MCRegisterInfo.c 31 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/SStream.c 32 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/arch/X86/X86Disassembler.c 33 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/arch/X86/X86DisassemblerDecoder.c 34 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/arch/X86/X86IntelInstPrinter.c 35 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/arch/X86/X86Mapping.c 36 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/arch/X86/X86Module.c 37 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/cs.c 38 | ${PROJECT_SOURCE_DIR}/../3rdparty/Capstone/src/utils.c 39 | ) 40 | 41 | set_target_properties(capstone_x86 PROPERTIES LINKER_LANGUAGE C) 42 | set(CMAKE_WINDOWS_EXPORT_ALL_SYMBOLS ON) 43 | -------------------------------------------------------------------------------- /3rdparty/Capstone/x86/x86.pro: -------------------------------------------------------------------------------- 1 | #------------------------------------------------- 2 | # 3 | # Project created by QtCreator 2019-02-01T10:50:10 4 | # 5 | #------------------------------------------------- 6 | 7 | QT -= core gui 8 | 9 | TARGET = capstone 10 | TEMPLATE = lib 11 | CONFIG += staticlib 12 | 13 | include(../../../build.pri) 14 | 15 | CONFIG(debug, debug|release) { 16 | TARGET = capstone_x86d 17 | } else { 18 | TARGET = capstone_x86 19 | } 20 | 21 | win32{ 22 | TARGET = capstone_x86-win-$${QT_ARCH} 23 | } 24 | unix:!macx { 25 | TARGET = capstone_x86-unix-$${QT_ARCH} 26 | } 27 | unix:macx { 28 | TARGET = capstone_x86-macos-$${QT_ARCH} 29 | } 30 | 31 | win32 { 32 | DEFINES += "WIN32" 33 | } 34 | 35 | CONFIG += c++11 36 | 37 | DEFINES += "CAPSTONE_HAS_X86" 38 | 39 | DEFINES += "CAPSTONE_X86_ATT_DISABLE" 40 | DEFINES += "CAPSTONE_DIET_NO" 41 | DEFINES += "CAPSTONE_X86_REDUCE" 42 | DEFINES += "CAPSTONE_USE_SYS_DYN_MEM" 43 | DEFINES += "_LIB" 44 | 45 | INCLUDEPATH += $$PWD/../src/ 46 | DEPENDPATH += $$PWD/../src/ 47 | INCLUDEPATH += $$PWD/src/include 48 | DEPENDPATH += $$PWD/src/include 49 | 50 | SOURCES += \ 51 | ../src/MCInst.c \ 52 | ../src/MCInstrDesc.c \ 53 | ../src/MCRegisterInfo.c \ 54 | ../src/SStream.c \ 55 | ../src/arch/X86/X86ATTInstPrinter.c \ 56 | ../src/arch/X86/X86Disassembler.c \ 57 | ../src/arch/X86/X86DisassemblerDecoder.c \ 58 | ../src/arch/X86/X86InstPrinterCommon.c \ 59 | ../src/arch/X86/X86IntelInstPrinter.c \ 60 | ../src/arch/X86/X86Mapping.c \ 61 | ../src/arch/X86/X86Module.c \ 62 | ../src/cs.c \ 63 | ../src/utils.c 64 | 65 | TARGETLIB_PATH = $$PWD/../ 66 | 67 | DESTDIR=$${TARGETLIB_PATH}/libs 68 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86BaseInfo.h: -------------------------------------------------------------------------------- 1 | //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains small standalone helper functions and enum definitions for 11 | // the X86 target useful for the compiler back-end and the MC libraries. 12 | // As such, it deliberately does not include references to LLVM core 13 | // code gen types, passes, etc.. 14 | // 15 | //===----------------------------------------------------------------------===// 16 | 17 | #ifndef CS_X86_BASEINFO_H 18 | #define CS_X86_BASEINFO_H 19 | 20 | /* Capstone Disassembly Engine */ 21 | /* By Nguyen Anh Quynh , 2013-2019 */ 22 | 23 | // Enums for memory operand decoding. Each memory operand is represented with 24 | // a 5 operand sequence in the form: 25 | // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 26 | // These enums help decode this. 27 | enum { 28 | X86_AddrBaseReg = 0, 29 | X86_AddrScaleAmt = 1, 30 | X86_AddrIndexReg = 2, 31 | X86_AddrDisp = 3, 32 | 33 | /// AddrSegmentReg - The operand # of the segment in the memory operand. 34 | X86_AddrSegmentReg = 4, 35 | 36 | /// AddrNumOperands - Total number of operands in a memory reference. 37 | X86_AddrNumOperands = 5 38 | }; 39 | 40 | enum IPREFIXES { 41 | X86_IP_NO_PREFIX = 0, 42 | X86_IP_HAS_OP_SIZE = 1, 43 | X86_IP_HAS_AD_SIZE = 2, 44 | X86_IP_HAS_REPEAT_NE = 4, 45 | X86_IP_HAS_REPEAT = 8, 46 | X86_IP_HAS_LOCK = 16, 47 | X86_IP_HAS_NOTRACK = 64 48 | }; 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/LICENSE.TXT: -------------------------------------------------------------------------------- 1 | This is the software license for Capstone disassembly framework. 2 | Capstone has been designed & implemented by Nguyen Anh Quynh 3 | 4 | See http://www.capstone-engine.org for further information. 5 | 6 | Copyright (c) 2013, COSEINC. 7 | All rights reserved. 8 | 9 | Redistribution and use in source and binary forms, with or without 10 | modification, are permitted provided that the following conditions are met: 11 | 12 | * Redistributions of source code must retain the above copyright notice, 13 | this list of conditions and the following disclaimer. 14 | * Redistributions in binary form must reproduce the above copyright notice, 15 | this list of conditions and the following disclaimer in the documentation 16 | and/or other materials provided with the distribution. 17 | * Neither the name of the developer(s) nor the names of its 18 | contributors may be used to endorse or promote products derived from this 19 | software without specific prior written permission. 20 | 21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 | POSSIBILITY OF SUCH DAMAGE. 32 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/m6801.inc: -------------------------------------------------------------------------------- 1 | 2 | // Additional instructions only supported on M6801/3 3 | static const inst_pageX g_m6801_inst_overlay_table[] = { 4 | // 0x0x, inherent instructions 5 | { 0x04, M680X_INS_LSRD, inh_hid, inh_hid }, 6 | { 0x05, M680X_INS_ASLD, inh_hid, inh_hid }, 7 | // 0x2x, relative branch instructions 8 | { 0x21, M680X_INS_BRN, rel8_hid, inh_hid }, 9 | // 0x3x, inherent instructions 10 | { 0x38, M680X_INS_PULX, inh_hid, inh_hid }, 11 | { 0x3A, M680X_INS_ABX, inh_hid, inh_hid }, 12 | { 0x3C, M680X_INS_PSHX, inh_hid, inh_hid }, 13 | { 0x3D, M680X_INS_MUL, inh_hid, inh_hid }, 14 | // 0x8x, immediate instructions with Register D 15 | { 0x83, M680X_INS_SUBD, imm16_hid, inh_hid }, 16 | // 0x9x, direct instructions with register D 17 | { 0x93, M680X_INS_SUBD, dir_hid, inh_hid }, 18 | { 0x9D, M680X_INS_JSR, dir_hid, inh_hid }, 19 | // 0xAx, indexed instructions with Register D 20 | { 0xA3, M680X_INS_SUBD, idxX_hid, inh_hid }, 21 | // 0xBx, extended instructions with register D 22 | { 0xB3, M680X_INS_SUBD, ext_hid, inh_hid }, 23 | // 0xCx, immediate instructions with register D 24 | { 0xC3, M680X_INS_ADDD, imm16_hid, inh_hid }, 25 | { 0xCC, M680X_INS_LDD, imm16_hid, inh_hid }, 26 | // 0xDx direct instructions with register D 27 | { 0xD3, M680X_INS_ADDD, dir_hid, inh_hid }, 28 | { 0xDC, M680X_INS_LDD, dir_hid, inh_hid }, 29 | { 0xDD, M680X_INS_STD, dir_hid, inh_hid }, 30 | // 0xEx, indexed instruction with register D 31 | { 0xE3, M680X_INS_ADDD, idxX_hid, inh_hid }, 32 | { 0xEC, M680X_INS_LDD, idxX_hid, inh_hid }, 33 | { 0xED, M680X_INS_STD, idxX_hid, inh_hid }, 34 | // 0xFx, extended instructions with register D 35 | { 0xF3, M680X_INS_ADDD, ext_hid, inh_hid }, 36 | { 0xFC, M680X_INS_LDD, ext_hid, inh_hid }, 37 | { 0xFD, M680X_INS_STD, ext_hid, inh_hid }, 38 | }; 39 | 40 | -------------------------------------------------------------------------------- /xcapstone.h: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2019-2025 hors 2 | * 3 | * Permission is hereby granted, free of charge, to any person obtaining a copy 4 | * of this software and associated documentation files (the "Software"), to deal 5 | * in the Software without restriction, including without limitation the rights 6 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | * copies of the Software, and to permit persons to whom the Software is 8 | * furnished to do so, subject to the following conditions: 9 | * 10 | * The above copyright notice and this permission notice shall be included in all 11 | * copies or substantial portions of the Software. 12 | * 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 19 | * SOFTWARE. 20 | */ 21 | #ifndef XCAPSTONE_H 22 | #define XCAPSTONE_H 23 | 24 | #include "capstone/capstone.h" 25 | #include "xbinary.h" 26 | #ifdef QT_GUI_LIB 27 | #include 28 | #endif 29 | 30 | class XCapstone : public QObject { 31 | Q_OBJECT 32 | 33 | public: 34 | // TODO error,info signals 35 | // TODO non static 36 | explicit XCapstone(QObject *pParent = nullptr); 37 | 38 | static bool isModeValid(XBinary::DM disasmMode); 39 | static cs_err openHandle(XBinary::DM disasmMode, csh *pHandle, bool bDetails, XBinary::SYNTAX syntax = XBinary::SYNTAX_DEFAULT); 40 | static cs_err closeHandle(csh *pHandle); 41 | 42 | static void printEnabledArchs(); 43 | 44 | private: 45 | static const qint32 N_OPCODE_SIZE = 16; // mb TODO rename set/get 46 | }; 47 | 48 | #endif // XCAPSTONE_H 49 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/M680XDisassemblerInternals.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M680X Backend by Wolfgang Schwotzer 2017 */ 3 | 4 | #ifndef CS_M680XDISASSEMBLERINTERNALS_H 5 | #define CS_M680XDISASSEMBLERINTERNALS_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../include/capstone/m680x.h" 9 | 10 | typedef enum e_cpu_type { 11 | M680X_CPU_TYPE_INVALID, 12 | M680X_CPU_TYPE_6301, // M680X Hitachi HD6301,HD6303 mode 13 | M680X_CPU_TYPE_6309, // M680X Hitachi HD6309 mode 14 | M680X_CPU_TYPE_6800, // M680X Motorola 6800,6802 mode 15 | M680X_CPU_TYPE_6801, // M680X Motorola 6801,6803 mode 16 | M680X_CPU_TYPE_6805, // M680X Motorola/Freescale M68HC05 mode 17 | M680X_CPU_TYPE_6808, // M680X Motorola/Freescale M68HC08 mode 18 | M680X_CPU_TYPE_6809, // M680X Motorola 6809 mode 19 | M680X_CPU_TYPE_6811, // M680X Motorola/Freescale M68HC11 mode 20 | M680X_CPU_TYPE_CPU12, // M680X Motorola/Freescale CPU12 mode 21 | // used on M68HC12/HCS12 22 | M680X_CPU_TYPE_HCS08, // M680X Freescale HCS08 mode 23 | M680X_CPU_TYPE_ENDING, 24 | } e_cpu_type; 25 | 26 | struct inst_page1; 27 | struct inst_pageX; 28 | 29 | typedef struct { 30 | const struct inst_page1 *inst_page1_table; 31 | const struct inst_pageX *inst_overlay_table[2]; 32 | size_t overlay_table_size[2]; 33 | uint8_t pageX_prefix[3]; 34 | const struct inst_pageX *inst_pageX_table[3]; 35 | size_t pageX_table_size[3]; 36 | const uint8_t *reg_byte_size; 37 | const bool *tfr_reg_valid; 38 | m680x_insn insn_cc_not_modified[2]; 39 | } cpu_tables; 40 | 41 | /* Private, For internal use only */ 42 | typedef struct m680x_info { 43 | const uint8_t *code; // code buffer 44 | uint32_t size; // byte size of code 45 | uint16_t offset; // address offset of first byte in code buffer 46 | e_cpu_type cpu_type; // The CPU type to be used for disassembling 47 | cs_m680x m680x; // M680X specific properties 48 | const cpu_tables *cpu; 49 | m680x_insn insn; // Instruction ID 50 | uint8_t insn_size; // byte size of instruction 51 | } m680x_info; 52 | 53 | extern cs_err M680X_disassembler_init(cs_struct *ud); 54 | extern cs_err M680X_instprinter_init(cs_struct *ud); 55 | 56 | #endif 57 | 58 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZMCTargetDesc.h: -------------------------------------------------------------------------------- 1 | //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | /* Capstone Disassembly Engine */ 11 | /* By Nguyen Anh Quynh , 2013-2015 */ 12 | 13 | #ifndef CS_SYSTEMZMCTARGETDESC_H 14 | #define CS_SYSTEMZMCTARGETDESC_H 15 | 16 | // Maps of asm register numbers to LLVM register numbers, with 0 indicating 17 | // an invalid register. In principle we could use 32-bit and 64-bit register 18 | // classes directly, provided that we relegated the GPR allocation order 19 | // in SystemZRegisterInfo.td to an AltOrder and left the default order 20 | // as %r0-%r15. It seems better to provide the same interface for 21 | // all classes though. 22 | extern const unsigned SystemZMC_GR32Regs[16]; 23 | extern const unsigned SystemZMC_GRH32Regs[16]; 24 | extern const unsigned SystemZMC_GR64Regs[16]; 25 | extern const unsigned SystemZMC_GR128Regs[16]; 26 | extern const unsigned SystemZMC_FP32Regs[16]; 27 | extern const unsigned SystemZMC_FP64Regs[16]; 28 | extern const unsigned SystemZMC_FP128Regs[16]; 29 | extern const unsigned SystemZMC_VR32Regs[32]; 30 | extern const unsigned SystemZMC_VR64Regs[32]; 31 | extern const unsigned SystemZMC_VR128Regs[32]; 32 | extern const unsigned SystemZMC_AR32Regs[16]; 33 | extern const unsigned SystemZMC_CR64Regs[16]; 34 | 35 | // Return the 0-based number of the first architectural register that 36 | // contains the given LLVM register. E.g. R1D -> 1. 37 | unsigned SystemZMC_getFirstReg(unsigned Reg); 38 | 39 | // Defines symbolic names for SystemZ registers. 40 | // This defines a mapping from register name to register number. 41 | //#define GET_REGINFO_ENUM 42 | //#include "SystemZGenRegisterInfo.inc" 43 | 44 | // Defines symbolic names for the SystemZ instructions. 45 | //#define GET_INSTRINFO_ENUM 46 | //#include "SystemZGenInstrInfo.inc" 47 | 48 | //#define GET_SUBTARGETINFO_ENUM 49 | //#include "SystemZGenSubtargetInfo.inc" 50 | 51 | #endif 52 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/M680XModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M680X Backend by Wolfgang Schwotzer 2017 */ 3 | 4 | #ifdef CAPSTONE_HAS_M680X 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "M680XDisassembler.h" 9 | #include "M680XDisassemblerInternals.h" 10 | #include "M680XInstPrinter.h" 11 | #include "M680XModule.h" 12 | 13 | cs_err M680X_global_init(cs_struct *ud) 14 | { 15 | m680x_info *info; 16 | cs_err errcode; 17 | 18 | /* Do some validation checks */ 19 | errcode = M680X_disassembler_init(ud); 20 | 21 | if (errcode != CS_ERR_OK) 22 | return errcode; 23 | 24 | errcode = M680X_instprinter_init(ud); 25 | 26 | if (errcode != CS_ERR_OK) 27 | return errcode; 28 | 29 | // verify if requested mode is valid 30 | if (ud->mode & ~(CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | 31 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | 32 | CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | 33 | CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | 34 | CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08)) { 35 | // At least one mode is not supported by M680X 36 | return CS_ERR_MODE; 37 | } 38 | 39 | if (!(ud->mode & (CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | 40 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | 41 | CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | 42 | CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | 43 | CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08))) { 44 | // At least the cpu type has to be selected. No default. 45 | return CS_ERR_MODE; 46 | } 47 | 48 | info = cs_mem_malloc(sizeof(m680x_info)); 49 | 50 | if (!info) 51 | return CS_ERR_MEM; 52 | 53 | ud->printer = M680X_printInst; 54 | ud->printer_info = info; 55 | ud->getinsn_info = NULL; 56 | ud->disasm = M680X_getInstruction; 57 | ud->reg_name = M680X_reg_name; 58 | ud->insn_id = M680X_get_insn_id; 59 | ud->insn_name = M680X_insn_name; 60 | ud->group_name = M680X_group_name; 61 | ud->skipdata_size = 1; 62 | ud->post_printer = NULL; 63 | #ifndef CAPSTONE_DIET 64 | ud->reg_access = M680X_reg_access; 65 | #endif 66 | 67 | return CS_ERR_OK; 68 | } 69 | 70 | cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value) 71 | { 72 | //TODO 73 | return CS_ERR_OK; 74 | } 75 | 76 | #endif 77 | 78 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Sparc/Sparc.h: -------------------------------------------------------------------------------- 1 | //===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the entry points for global functions defined in the LLVM 11 | // Sparc back-end. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | /* Capstone Disassembly Engine */ 16 | /* By Nguyen Anh Quynh , 2013-2015 */ 17 | 18 | #ifndef CS_SPARC_TARGET_SPARC_H 19 | #define CS_SPARC_TARGET_SPARC_H 20 | 21 | #include "capstone/sparc.h" 22 | 23 | inline static const char *SPARCCondCodeToString(sparc_cc CC) 24 | { 25 | switch (CC) { 26 | default: return NULL; // unreachable 27 | case SPARC_CC_ICC_A: return "a"; 28 | case SPARC_CC_ICC_N: return "n"; 29 | case SPARC_CC_ICC_NE: return "ne"; 30 | case SPARC_CC_ICC_E: return "e"; 31 | case SPARC_CC_ICC_G: return "g"; 32 | case SPARC_CC_ICC_LE: return "le"; 33 | case SPARC_CC_ICC_GE: return "ge"; 34 | case SPARC_CC_ICC_L: return "l"; 35 | case SPARC_CC_ICC_GU: return "gu"; 36 | case SPARC_CC_ICC_LEU: return "leu"; 37 | case SPARC_CC_ICC_CC: return "cc"; 38 | case SPARC_CC_ICC_CS: return "cs"; 39 | case SPARC_CC_ICC_POS: return "pos"; 40 | case SPARC_CC_ICC_NEG: return "neg"; 41 | case SPARC_CC_ICC_VC: return "vc"; 42 | case SPARC_CC_ICC_VS: return "vs"; 43 | 44 | case SPARC_CC_FCC_A: return "a"; 45 | case SPARC_CC_FCC_N: return "n"; 46 | case SPARC_CC_FCC_U: return "u"; 47 | case SPARC_CC_FCC_G: return "g"; 48 | case SPARC_CC_FCC_UG: return "ug"; 49 | case SPARC_CC_FCC_L: return "l"; 50 | case SPARC_CC_FCC_UL: return "ul"; 51 | case SPARC_CC_FCC_LG: return "lg"; 52 | case SPARC_CC_FCC_NE: return "ne"; 53 | case SPARC_CC_FCC_E: return "e"; 54 | case SPARC_CC_FCC_UE: return "ue"; 55 | case SPARC_CC_FCC_GE: return "ge"; 56 | case SPARC_CC_FCC_UGE: return "uge"; 57 | case SPARC_CC_FCC_LE: return "le"; 58 | case SPARC_CC_FCC_ULE: return "ule"; 59 | case SPARC_CC_FCC_O: return "o"; 60 | } 61 | } 62 | 63 | #endif 64 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/MOS65XX/MOS65XXModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* MOS65XX Backend by Sebastian Macke 2018 */ 3 | 4 | #ifdef CAPSTONE_HAS_MOS65XX 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "MOS65XXDisassembler.h" 9 | #include "MOS65XXDisassemblerInternals.h" 10 | #include "MOS65XXModule.h" 11 | 12 | cs_err MOS65XX_global_init(cs_struct *ud) 13 | { 14 | mos65xx_info *info; 15 | 16 | info = cs_mem_malloc(sizeof(*info)); 17 | info->hex_prefix = NULL; 18 | info->cpu_type = MOS65XX_CPU_TYPE_6502; 19 | info->long_m = 0; 20 | info->long_x = 0; 21 | 22 | 23 | ud->printer = MOS65XX_printInst; 24 | ud->printer_info = info; 25 | ud->insn_id = MOS65XX_get_insn_id; 26 | ud->insn_name = MOS65XX_insn_name; 27 | ud->group_name = MOS65XX_group_name; 28 | ud->disasm = MOS65XX_getInstruction; 29 | ud->reg_name = MOS65XX_reg_name; 30 | 31 | if (ud->mode) { 32 | MOS65XX_option(ud, CS_OPT_MODE, ud->mode); 33 | } 34 | 35 | return CS_ERR_OK; 36 | } 37 | 38 | cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value) 39 | { 40 | mos65xx_info *info = (mos65xx_info *)handle->printer_info; 41 | switch(type) { 42 | default: 43 | break; 44 | case CS_OPT_MODE: 45 | 46 | if (value & CS_MODE_MOS65XX_6502) 47 | info->cpu_type = MOS65XX_CPU_TYPE_6502; 48 | if (value & CS_MODE_MOS65XX_65C02) 49 | info->cpu_type = MOS65XX_CPU_TYPE_65C02; 50 | if (value & CS_MODE_MOS65XX_W65C02) 51 | info->cpu_type = MOS65XX_CPU_TYPE_W65C02; 52 | if (value & (CS_MODE_MOS65XX_65816|CS_MODE_MOS65XX_65816_LONG_M|CS_MODE_MOS65XX_65816_LONG_X)) 53 | info->cpu_type = MOS65XX_CPU_TYPE_65816; 54 | 55 | info->long_m = value & CS_MODE_MOS65XX_65816_LONG_M ? 1 : 0; 56 | info->long_x = value & CS_MODE_MOS65XX_65816_LONG_X ? 1 : 0; 57 | 58 | handle->mode = (cs_mode)value; 59 | break; 60 | case CS_OPT_SYNTAX: 61 | switch(value) { 62 | default: 63 | // wrong syntax value 64 | handle->errnum = CS_ERR_OPTION; 65 | return CS_ERR_OPTION; 66 | case CS_OPT_SYNTAX_DEFAULT: 67 | info->hex_prefix = NULL; 68 | break; 69 | case CS_OPT_SYNTAX_MOTOROLA: 70 | info->hex_prefix = "$"; 71 | break; 72 | } 73 | handle->syntax = (int)value; 74 | break; 75 | } 76 | return CS_ERR_OK; 77 | } 78 | 79 | #endif 80 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/Mips/MipsGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2015 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | #define Mips_FeatureCnMips (1ULL << 0) 17 | #define Mips_FeatureDSP (1ULL << 1) 18 | #define Mips_FeatureDSPR2 (1ULL << 2) 19 | #define Mips_FeatureFP64Bit (1ULL << 3) 20 | #define Mips_FeatureFPXX (1ULL << 4) 21 | #define Mips_FeatureGP64Bit (1ULL << 5) 22 | #define Mips_FeatureMSA (1ULL << 6) 23 | #define Mips_FeatureMicroMips (1ULL << 7) 24 | #define Mips_FeatureMips1 (1ULL << 8) 25 | #define Mips_FeatureMips2 (1ULL << 9) 26 | #define Mips_FeatureMips3 (1ULL << 10) 27 | #define Mips_FeatureMips3_32 (1ULL << 11) 28 | #define Mips_FeatureMips3_32r2 (1ULL << 12) 29 | #define Mips_FeatureMips4 (1ULL << 13) 30 | #define Mips_FeatureMips4_32 (1ULL << 14) 31 | #define Mips_FeatureMips4_32r2 (1ULL << 15) 32 | #define Mips_FeatureMips5 (1ULL << 16) 33 | #define Mips_FeatureMips5_32r2 (1ULL << 17) 34 | #define Mips_FeatureMips16 (1ULL << 18) 35 | #define Mips_FeatureMips32 (1ULL << 19) 36 | #define Mips_FeatureMips32r2 (1ULL << 20) 37 | #define Mips_FeatureMips32r3 (1ULL << 21) 38 | #define Mips_FeatureMips32r5 (1ULL << 22) 39 | #define Mips_FeatureMips32r6 (1ULL << 23) 40 | #define Mips_FeatureMips64 (1ULL << 24) 41 | #define Mips_FeatureMips64r2 (1ULL << 25) 42 | #define Mips_FeatureMips64r3 (1ULL << 26) 43 | #define Mips_FeatureMips64r5 (1ULL << 27) 44 | #define Mips_FeatureMips64r6 (1ULL << 28) 45 | #define Mips_FeatureNaN2008 (1ULL << 29) 46 | #define Mips_FeatureNoABICalls (1ULL << 30) 47 | #define Mips_FeatureNoOddSPReg (1ULL << 31) 48 | #define Mips_FeatureSingleFloat (1ULL << 32) 49 | #define Mips_FeatureVFPU (1ULL << 33) 50 | 51 | #endif // GET_SUBTARGETINFO_ENUM 52 | 53 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SystemZ/SystemZGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |* Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2015 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | SystemZ_FeatureDFPPackedConversion = 1ULL << 0, 18 | SystemZ_FeatureDFPZonedConversion = 1ULL << 1, 19 | SystemZ_FeatureDistinctOps = 1ULL << 2, 20 | SystemZ_FeatureEnhancedDAT2 = 1ULL << 3, 21 | SystemZ_FeatureExecutionHint = 1ULL << 4, 22 | SystemZ_FeatureFPExtension = 1ULL << 5, 23 | SystemZ_FeatureFastSerialization = 1ULL << 6, 24 | SystemZ_FeatureGuardedStorage = 1ULL << 7, 25 | SystemZ_FeatureHighWord = 1ULL << 8, 26 | SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9, 27 | SystemZ_FeatureInterlockedAccess1 = 1ULL << 10, 28 | SystemZ_FeatureLoadAndTrap = 1ULL << 11, 29 | SystemZ_FeatureLoadAndZeroRightmostByte = 1ULL << 12, 30 | SystemZ_FeatureLoadStoreOnCond = 1ULL << 13, 31 | SystemZ_FeatureLoadStoreOnCond2 = 1ULL << 14, 32 | SystemZ_FeatureMessageSecurityAssist3 = 1ULL << 15, 33 | SystemZ_FeatureMessageSecurityAssist4 = 1ULL << 16, 34 | SystemZ_FeatureMessageSecurityAssist5 = 1ULL << 17, 35 | SystemZ_FeatureMessageSecurityAssist7 = 1ULL << 18, 36 | SystemZ_FeatureMessageSecurityAssist8 = 1ULL << 19, 37 | SystemZ_FeatureMiscellaneousExtensions = 1ULL << 20, 38 | SystemZ_FeatureMiscellaneousExtensions2 = 1ULL << 21, 39 | SystemZ_FeaturePopulationCount = 1ULL << 22, 40 | SystemZ_FeatureProcessorAssist = 1ULL << 23, 41 | SystemZ_FeatureResetReferenceBitsMultiple = 1ULL << 24, 42 | SystemZ_FeatureTransactionalExecution = 1ULL << 25, 43 | SystemZ_FeatureVector = 1ULL << 26, 44 | SystemZ_FeatureVectorEnhancements1 = 1ULL << 27, 45 | SystemZ_FeatureVectorPackedDecimal = 1ULL << 28, 46 | }; 47 | 48 | #endif // GET_SUBTARGETINFO_ENUM 49 | 50 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCPredicates.h: -------------------------------------------------------------------------------- 1 | //===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file describes the PowerPC branch predicates. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2015 */ 16 | 17 | #ifndef CS_POWERPC_PPCPREDICATES_H 18 | #define CS_POWERPC_PPCPREDICATES_H 19 | 20 | #include "capstone/ppc.h" 21 | 22 | // NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM 23 | typedef enum ppc_predicate { 24 | PPC_PRED_LT = (0 << 5) | 12, 25 | PPC_PRED_LE = (1 << 5) | 4, 26 | PPC_PRED_EQ = (2 << 5) | 12, 27 | PPC_PRED_GE = (0 << 5) | 4, 28 | PPC_PRED_GT = (1 << 5) | 12, 29 | PPC_PRED_NE = (2 << 5) | 4, 30 | PPC_PRED_UN = (3 << 5) | 12, 31 | PPC_PRED_NU = (3 << 5) | 4, 32 | PPC_PRED_LT_MINUS = (0 << 5) | 14, 33 | PPC_PRED_LE_MINUS = (1 << 5) | 6, 34 | PPC_PRED_EQ_MINUS = (2 << 5) | 14, 35 | PPC_PRED_GE_MINUS = (0 << 5) | 6, 36 | PPC_PRED_GT_MINUS = (1 << 5) | 14, 37 | PPC_PRED_NE_MINUS = (2 << 5) | 6, 38 | PPC_PRED_UN_MINUS = (3 << 5) | 14, 39 | PPC_PRED_NU_MINUS = (3 << 5) | 6, 40 | PPC_PRED_LT_PLUS = (0 << 5) | 15, 41 | PPC_PRED_LE_PLUS = (1 << 5) | 7, 42 | PPC_PRED_EQ_PLUS = (2 << 5) | 15, 43 | PPC_PRED_GE_PLUS = (0 << 5) | 7, 44 | PPC_PRED_GT_PLUS = (1 << 5) | 15, 45 | PPC_PRED_NE_PLUS = (2 << 5) | 7, 46 | PPC_PRED_UN_PLUS = (3 << 5) | 15, 47 | PPC_PRED_NU_PLUS = (3 << 5) | 7, 48 | 49 | // When dealing with individual condition-register bits, we have simple set 50 | // and unset predicates. 51 | PPC_PRED_BIT_SET = 1024, 52 | PPC_PRED_BIT_UNSET = 1025 53 | } ppc_predicate; 54 | 55 | /// Invert the specified predicate. != -> ==, < -> >=. 56 | ppc_predicate InvertPredicate(ppc_predicate Opcode); 57 | 58 | /// Assume the condition register is set by MI(a,b), return the predicate if 59 | /// we modify the instructions such that condition register is set by MI(b,a). 60 | ppc_predicate getSwappedPredicate(ppc_predicate Opcode); 61 | 62 | #endif 63 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/TriCore/TriCoreCallingConv.td: -------------------------------------------------------------------------------- 1 | //=- TriCoreCallingConv.td - Calling Conventions for TriCore -*- tablegen -*-=// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // This describes the calling conventions for TriCore architecture. 10 | //===----------------------------------------------------------------------===// 11 | 12 | //===----------------------------------------------------------------------===// 13 | // CCDelegate implemented form TriCore LLVM Thesis 14 | //===----------------------------------------------------------------------===// 15 | //def CC_TriCore_StackModel : CallingConv<[ 16 | //CCAssignToStack<4, 4> 17 | //]>; 18 | 19 | //===----------------------------------------------------------------------===// 20 | // TriCore Return Value Calling Convention 21 | //===----------------------------------------------------------------------===// 22 | def RetCC_TriCore : CallingConv<[ 23 | // Promote i8/i16 arguments to i32. 24 | CCIfType<[i8, i16], CCPromoteToType>, 25 | 26 | // i32 are returned in registers D2 27 | CCIfType<[i32], CCAssignToReg<[D2]>>, 28 | 29 | // Integer values get stored in stack slots that are 4 bytes in 30 | // size and 4-byte aligned. 31 | CCIfType<[i32], CCAssignToStack<4, 4>> 32 | ]>; 33 | 34 | //===----------------------------------------------------------------------===// 35 | // TriCore Argument Calling Conventions 36 | //===----------------------------------------------------------------------===// 37 | def CC_TriCore : CallingConv<[ 38 | // Promote i8/i16 arguments to i32. 39 | CCIfType<[i8, i16], CCPromoteToType>, 40 | 41 | 42 | // The first 4 integer arguments are passed in integer registers. 43 | // CCIfType<[i32], CCAssignToReg<[D4, D5, D6, D7]>>, 44 | 45 | //CCIfType<[i32], CCAssignToReg<[A4, A5, A6, A7]>>, 46 | 47 | // Pointer arguments are handled inside TriCoreIselLowering, because 48 | // LLVM lowers i32** type into i32, hence there is no way to distingusish 49 | // beetwen a pointer type and an integer type. 50 | 51 | 52 | 53 | 54 | //CCDelegateTo 55 | 56 | // Integer values get stored in stack slots that are 4 bytes in 57 | // size and 4-byte aligned. 58 | CCIfType<[i32], CCAssignToStack<4, 4>> 59 | ]>; 60 | 61 | //def CC_Save : CalleeSavedRegs<(add R4, R5, R6, R7, R8, R9)>; 62 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64BaseInfo.c: -------------------------------------------------------------------------------- 1 | //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file provides basic encoding and assembly information for AArch64. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2019 */ 16 | 17 | #ifdef CAPSTONE_HAS_ARM64 18 | 19 | #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) 20 | #pragma warning(disable:4996) // disable MSVC's warning on strcpy() 21 | #pragma warning(disable:28719) // disable MSVC's warning on strcpy() 22 | #endif 23 | 24 | #include "../../utils.h" 25 | 26 | #include 27 | #include 28 | 29 | #include "AArch64BaseInfo.h" 30 | 31 | #include "AArch64GenSystemOperands.inc" 32 | 33 | // return a string representing the number X 34 | // NOTE: result must be big enough to contain the data 35 | static void utostr(uint64_t X, bool isNeg, char *result) 36 | { 37 | char Buffer[22]; 38 | char *BufPtr = Buffer + 21; 39 | 40 | Buffer[21] = '\0'; 41 | if (X == 0) *--BufPtr = '0'; // Handle special case... 42 | 43 | while (X) { 44 | *--BufPtr = X % 10 + '0'; 45 | X /= 10; 46 | } 47 | 48 | if (isNeg) *--BufPtr = '-'; // Add negative sign... 49 | 50 | // suppose that result is big enough 51 | strncpy(result, BufPtr, sizeof(Buffer)); 52 | } 53 | 54 | // NOTE: result must be big enough to contain the result 55 | void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result) 56 | { 57 | // assert(Bits < 0x10000); 58 | char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32]; 59 | int dummy; 60 | uint32_t Op0 = (Bits >> 14) & 0x3; 61 | uint32_t Op1 = (Bits >> 11) & 0x7; 62 | uint32_t CRn = (Bits >> 7) & 0xf; 63 | uint32_t CRm = (Bits >> 3) & 0xf; 64 | uint32_t Op2 = Bits & 0x7; 65 | 66 | utostr(Op0, false, Op0Str); 67 | utostr(Op1, false, Op1Str); 68 | utostr(Op2, false, Op2Str); 69 | utostr(CRn, false, CRnStr); 70 | utostr(CRm, false, CRmStr); 71 | 72 | dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s", 73 | Op0Str, Op1Str, CRnStr, CRmStr, Op2Str); 74 | (void)dummy; 75 | } 76 | 77 | #endif 78 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86Module.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_X86 5 | 6 | #include "../../cs_priv.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "X86Disassembler.h" 9 | #include "X86InstPrinter.h" 10 | #include "X86Mapping.h" 11 | #include "X86Module.h" 12 | 13 | cs_err X86_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | X86_init(mri); 19 | 20 | // by default, we use Intel syntax 21 | ud->printer = X86_Intel_printInst; 22 | ud->syntax = CS_OPT_SYNTAX_INTEL; 23 | ud->printer_info = mri; 24 | ud->disasm = X86_getInstruction; 25 | ud->reg_name = X86_reg_name; 26 | ud->insn_id = X86_get_insn_id; 27 | ud->insn_name = X86_insn_name; 28 | ud->group_name = X86_group_name; 29 | ud->post_printer = NULL;; 30 | #ifndef CAPSTONE_DIET 31 | ud->reg_access = X86_reg_access; 32 | #endif 33 | 34 | if (ud->mode == CS_MODE_64) 35 | ud->regsize_map = regsize_map_64; 36 | else 37 | ud->regsize_map = regsize_map_32; 38 | 39 | return CS_ERR_OK; 40 | } 41 | 42 | cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value) 43 | { 44 | switch(type) { 45 | default: 46 | break; 47 | case CS_OPT_MODE: 48 | if (value == CS_MODE_64) 49 | handle->regsize_map = regsize_map_64; 50 | else 51 | handle->regsize_map = regsize_map_32; 52 | 53 | handle->mode = (cs_mode)value; 54 | break; 55 | case CS_OPT_SYNTAX: 56 | switch(value) { 57 | default: 58 | // wrong syntax value 59 | handle->errnum = CS_ERR_OPTION; 60 | return CS_ERR_OPTION; 61 | 62 | case CS_OPT_SYNTAX_DEFAULT: 63 | case CS_OPT_SYNTAX_INTEL: 64 | handle->syntax = CS_OPT_SYNTAX_INTEL; 65 | handle->printer = X86_Intel_printInst; 66 | break; 67 | 68 | case CS_OPT_SYNTAX_MASM: 69 | handle->printer = X86_Intel_printInst; 70 | handle->syntax = (int)value; 71 | break; 72 | 73 | case CS_OPT_SYNTAX_ATT: 74 | #if !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) 75 | handle->printer = X86_ATT_printInst; 76 | handle->syntax = CS_OPT_SYNTAX_ATT; 77 | break; 78 | #elif !defined(CAPSTONE_DIET) && defined(CAPSTONE_X86_ATT_DISABLE) 79 | // ATT syntax is unsupported 80 | handle->errnum = CS_ERR_X86_ATT; 81 | return CS_ERR_X86_ATT; 82 | #else // CAPSTONE_DIET 83 | // this is irrelevant in CAPSTONE_DIET mode 84 | handle->errnum = CS_ERR_DIET; 85 | return CS_ERR_DIET; 86 | #endif 87 | } 88 | break; 89 | } 90 | 91 | return CS_ERR_OK; 92 | } 93 | 94 | #endif 95 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/utils.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_UTILS_H 5 | #define CS_UTILS_H 6 | 7 | #if defined(CAPSTONE_HAS_OSXKERNEL) 8 | #include 9 | #else 10 | #include 11 | #include "include/capstone/capstone.h" 12 | #endif 13 | #include "cs_priv.h" 14 | 15 | // threshold number, so above this number will be printed in hexa mode 16 | #define HEX_THRESHOLD 9 17 | 18 | // map instruction to its characteristics 19 | typedef struct insn_map { 20 | unsigned short id; 21 | unsigned short mapid; 22 | #ifndef CAPSTONE_DIET 23 | uint16_t regs_use[12]; // list of implicit registers used by this instruction 24 | uint16_t regs_mod[20]; // list of implicit registers modified by this instruction 25 | unsigned char groups[8]; // list of group this instruction belong to 26 | bool branch; // branch instruction? 27 | bool indirect_branch; // indirect branch instruction? 28 | #endif 29 | } insn_map; 30 | 31 | // look for @id in @m, given its size in @max. first time call will update @cache. 32 | // return 0 if not found 33 | unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id, unsigned short **cache); 34 | 35 | // map id to string 36 | typedef struct name_map { 37 | unsigned int id; 38 | const char *name; 39 | } name_map; 40 | 41 | // map a name to its ID 42 | // return 0 if not found 43 | int name2id(const name_map* map, int max, const char *name); 44 | 45 | // map ID to a name 46 | // return NULL if not found 47 | const char *id2name(const name_map* map, int max, const unsigned int id); 48 | 49 | // count number of positive members in a list. 50 | // NOTE: list must be guaranteed to end in 0 51 | unsigned int count_positive(const uint16_t *list); 52 | unsigned int count_positive8(const unsigned char *list); 53 | 54 | #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) 55 | #define MATRIX_SIZE(a) (sizeof(a[0])/sizeof(a[0][0])) 56 | 57 | char *cs_strdup(const char *str); 58 | 59 | #define MIN(x, y) ((x) < (y) ? (x) : (y)) 60 | 61 | // we need this since Windows doesn't have snprintf() 62 | int cs_snprintf(char *buffer, size_t size, const char *fmt, ...); 63 | 64 | #define CS_AC_IGNORE (1 << 7) 65 | 66 | // check if an id is existent in an array 67 | bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id); 68 | 69 | bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id); 70 | 71 | struct IndexType { 72 | uint16_t encoding; 73 | unsigned index; 74 | }; 75 | 76 | // binary search for encoding in IndexType array 77 | // return -1 if not found, or index if found 78 | unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding); 79 | 80 | #endif 81 | 82 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/hcs08.inc: -------------------------------------------------------------------------------- 1 | 2 | // Additional instructions only supported on HCS08 3 | static const inst_pageX g_hcs08_inst_overlay_table[] = { 4 | { 0x32, M680X_INS_LDHX, ext_hid, inh_hid }, 5 | { 0x3e, M680X_INS_CPHX, ext_hid, inh_hid }, 6 | { 0x82, M680X_INS_BGND, inh_hid, inh_hid }, 7 | { 0x96, M680X_INS_STHX, ext_hid, inh_hid }, 8 | }; 9 | 10 | // HCS08 PAGE2 instructions (prefix 0x9E) 11 | static const inst_pageX g_hcs08_inst_page2_table[] = { 12 | { 0x60, M680X_INS_NEG, idxS_hid, inh_hid }, 13 | { 0x61, M680X_INS_CBEQ, idxS_hid,rel8_hid }, 14 | { 0x63, M680X_INS_COM, idxS_hid, inh_hid }, 15 | { 0x64, M680X_INS_LSR, idxS_hid, inh_hid }, 16 | { 0x66, M680X_INS_ROR, idxS_hid, inh_hid }, 17 | { 0x67, M680X_INS_ASR, idxS_hid, inh_hid }, 18 | { 0x68, M680X_INS_LSL, idxS_hid, inh_hid }, 19 | { 0x69, M680X_INS_ROL, idxS_hid, inh_hid }, 20 | { 0x6a, M680X_INS_DEC, idxS_hid, inh_hid }, 21 | { 0x6b, M680X_INS_DBNZ, idxS_hid,rel8_hid }, 22 | { 0x6c, M680X_INS_INC, idxS_hid, inh_hid }, 23 | { 0x6d, M680X_INS_TST, idxS_hid, inh_hid }, 24 | { 0x6f, M680X_INS_CLR, idxS_hid, inh_hid }, 25 | { 0xae, M680X_INS_LDHX, idxX0_hid, inh_hid }, 26 | { 0xbe, M680X_INS_LDHX, idxX16_hid, inh_hid }, 27 | { 0xce, M680X_INS_LDHX, idxX_hid, inh_hid }, 28 | { 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid }, 29 | { 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid }, 30 | { 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid }, 31 | { 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid }, 32 | { 0xd4, M680X_INS_AND, idxS16_hid, inh_hid }, 33 | { 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid }, 34 | { 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid }, 35 | { 0xd7, M680X_INS_STA, idxS16_hid, inh_hid }, 36 | { 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid }, 37 | { 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid }, 38 | { 0xda, M680X_INS_ORA, idxS16_hid, inh_hid }, 39 | { 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid }, 40 | { 0xde, M680X_INS_LDX, idxS16_hid, inh_hid }, 41 | { 0xdf, M680X_INS_STX, idxS16_hid, inh_hid }, 42 | { 0xe0, M680X_INS_SUB, idxS_hid, inh_hid }, 43 | { 0xe1, M680X_INS_CMP, idxS_hid, inh_hid }, 44 | { 0xe2, M680X_INS_SBC, idxS_hid, inh_hid }, 45 | { 0xe3, M680X_INS_CPX, idxS_hid, inh_hid }, 46 | { 0xe4, M680X_INS_AND, idxS_hid, inh_hid }, 47 | { 0xe5, M680X_INS_BIT, idxS_hid, inh_hid }, 48 | { 0xe6, M680X_INS_LDA, idxS_hid, inh_hid }, 49 | { 0xe7, M680X_INS_STA, idxS_hid, inh_hid }, 50 | { 0xe8, M680X_INS_EOR, idxS_hid, inh_hid }, 51 | { 0xe9, M680X_INS_ADC, idxS_hid, inh_hid }, 52 | { 0xea, M680X_INS_ORA, idxS_hid, inh_hid }, 53 | { 0xeb, M680X_INS_ADD, idxS_hid, inh_hid }, 54 | { 0xee, M680X_INS_LDX, idxS_hid, inh_hid }, 55 | { 0xef, M680X_INS_STX, idxS_hid, inh_hid }, 56 | { 0xf3, M680X_INS_CPHX, idxS_hid, inh_hid }, 57 | { 0xfe, M680X_INS_LDHX, idxS_hid, inh_hid }, 58 | { 0xff, M680X_INS_STHX, idxS_hid, inh_hid }, 59 | }; 60 | 61 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/PowerPC/PPCGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | 2 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 3 | /* By Nguyen Anh Quynh , 2013-2019 */ 4 | 5 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| 6 | |* Subtarget Enumeration Source Fragment *| 7 | |* *| 8 | |* Automatically generated file, do not edit! *| 9 | |* *| 10 | \*===----------------------------------------------------------------------===*/ 11 | 12 | 13 | enum { 14 | PPC_DeprecatedDST = 0, 15 | PPC_Directive32 = 1, 16 | PPC_Directive64 = 2, 17 | PPC_Directive440 = 3, 18 | PPC_Directive601 = 4, 19 | PPC_Directive602 = 5, 20 | PPC_Directive603 = 6, 21 | PPC_Directive604 = 7, 22 | PPC_Directive620 = 8, 23 | PPC_Directive750 = 9, 24 | PPC_Directive970 = 10, 25 | PPC_Directive7400 = 11, 26 | PPC_DirectiveA2 = 12, 27 | PPC_DirectiveE500 = 13, 28 | PPC_DirectiveE500mc = 14, 29 | PPC_DirectiveE5500 = 15, 30 | PPC_DirectivePwr3 = 16, 31 | PPC_DirectivePwr4 = 17, 32 | PPC_DirectivePwr5 = 18, 33 | PPC_DirectivePwr5x = 19, 34 | PPC_DirectivePwr6 = 20, 35 | PPC_DirectivePwr6x = 21, 36 | PPC_DirectivePwr7 = 22, 37 | PPC_DirectivePwr8 = 23, 38 | PPC_DirectivePwr9 = 24, 39 | PPC_Feature64Bit = 25, 40 | PPC_Feature64BitRegs = 26, 41 | PPC_FeatureAltivec = 27, 42 | PPC_FeatureBPERMD = 28, 43 | PPC_FeatureBookE = 29, 44 | PPC_FeatureCMPB = 30, 45 | PPC_FeatureCRBits = 31, 46 | PPC_FeatureDirectMove = 32, 47 | PPC_FeatureE500 = 33, 48 | PPC_FeatureExtDiv = 34, 49 | PPC_FeatureFCPSGN = 35, 50 | PPC_FeatureFPCVT = 36, 51 | PPC_FeatureFPRND = 37, 52 | PPC_FeatureFPU = 38, 53 | PPC_FeatureFRE = 39, 54 | PPC_FeatureFRES = 40, 55 | PPC_FeatureFRSQRTE = 41, 56 | PPC_FeatureFRSQRTES = 42, 57 | PPC_FeatureFSqrt = 43, 58 | PPC_FeatureFloat128 = 44, 59 | PPC_FeatureFusion = 45, 60 | PPC_FeatureHTM = 46, 61 | PPC_FeatureHardFloat = 47, 62 | PPC_FeatureICBT = 48, 63 | PPC_FeatureISA3_0 = 49, 64 | PPC_FeatureISEL = 50, 65 | PPC_FeatureInvariantFunctionDescriptors = 51, 66 | PPC_FeatureLDBRX = 52, 67 | PPC_FeatureLFIWAX = 53, 68 | PPC_FeatureLongCall = 54, 69 | PPC_FeatureMFOCRF = 55, 70 | PPC_FeatureMFTB = 56, 71 | PPC_FeatureMSYNC = 57, 72 | PPC_FeatureP8Altivec = 58, 73 | PPC_FeatureP8Crypto = 59, 74 | PPC_FeatureP8Vector = 60, 75 | PPC_FeatureP9Altivec = 61, 76 | PPC_FeatureP9Vector = 62, 77 | PPC_FeaturePOPCNTD = 63, 78 | PPC_FeaturePPC4xx = 64, 79 | PPC_FeaturePPC6xx = 65, 80 | PPC_FeaturePartwordAtomic = 66, 81 | PPC_FeatureQPX = 67, 82 | PPC_FeatureRecipPrec = 68, 83 | PPC_FeatureSPE = 69, 84 | PPC_FeatureSTFIWX = 70, 85 | PPC_FeatureSecurePlt = 71, 86 | PPC_FeatureSlowPOPCNTD = 72, 87 | PPC_FeatureVSX = 73, 88 | }; 89 | 90 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/SH/SHInsnTable.inc: -------------------------------------------------------------------------------- 1 | bool (*decode[])(uint16_t code, uint64_t address, MCInst *MI, cs_mode mode, sh_info *info, cs_detail *detail) = { 2 | /// 00000000 3 | NULL, NULL, opSTC, op0xx3, opMOV_B, opMOV_W, opMOV_L, opMUL_L, 4 | /// 00001000 5 | op0xx8, op0xx9, op0xxa, op0xxb, opMOV_B, opMOV_W, opMOV_L, opMAC_L, 6 | /// 00010000 7 | opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, 8 | /// 00011000 9 | opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, 10 | /// 00100000 11 | opMOV_rind, opMOV_rind, opMOV_rind, NULL, opMOV_rpd, opMOV_rpd, opMOV_rpd, opDIV0S, 12 | /// 00101000 13 | opTST, opAND, opXOR, opOR, opCMP_STR, opXTRCT, opMULU_W, opMULS_W, 14 | /// 00110000 15 | opCMP_EQ, NULL, opCMP_HS, opCMP_GE, opDIV1, opDMULU_L, opCMP_HI, opCMP_GT, 16 | /// 00111000 17 | opSUB, NULL, opSUBC, opSUBV, opADD_r, opDMULS_L, opADDC, opADDV, 18 | /// 01000000 19 | op4xx0, op4xx1, op4xx2, opSTC_L, op4xx4, op4xx5, op4xx6, opLDC_L, 20 | /// 01001000 21 | op4xx8, op4xx9, op4xxa, op4xxb, opSHAD, opSHLD, opLDC, opMAC_W, 22 | /// 01010000 23 | opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, 24 | /// 01011000 25 | opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, opMOV_L_dsp, 26 | /// 01100000 27 | opMOV_rind, opMOV_rind, opMOV_rind, opMOV, opMOV_rpi, opMOV_rpi, opMOV_rpi, opNOT, 28 | /// 01101000 29 | opSWAP_B, opSWAP_W, opNEGC, opNEG, opEXTU_B, opEXTU_W, opEXTS_B, opEXTS_W, 30 | /// 01110000 31 | opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, 32 | /// 01111000 33 | opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, opADD_i, 34 | /// 10000000 35 | opMOV_BW_dsp, opMOV_BW_dsp, opSETRC, opJSR_N, opMOV_BW_dsp, opMOV_BW_dsp, op86xx, op87xx, 36 | /// 10001000 37 | opCMP_EQi, opBT, opLDRC, opBF, opLDRS, opBT_S, opLDRE, opBF_S, 38 | /// 10010000 39 | opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, 40 | /// 10011000 41 | opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, 42 | /// 10100000 43 | opBRA, opBRA, opBRA, opBRA, opBRA, opBRA, opBRA, opBRA, 44 | /// 10101000 45 | opBRA, opBRA, opBRA, opBRA, opBRA, opBRA, opBRA, opBRA, 46 | /// 10110000 47 | opBSR, opBSR, opBSR, opBSR, opBSR, opBSR, opBSR, opBSR, 48 | /// 10111000 49 | opBSR, opBSR, opBSR, opBSR, opBSR, opBSR, opBSR, opBSR, 50 | /// 11000000 51 | opMOV_gbr, opMOV_gbr, opMOV_gbr, opTRAPA, opMOV_gbr, opMOV_gbr, opMOV_gbr, opMOVA, 52 | /// 11001000 53 | opTST_i, opAND_i, opXOR_i, opOR_i, opTST_B, opAND_B, opXOR_B, opOR_B, 54 | /// 11010000 55 | opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, 56 | /// 11011000 57 | opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, opMOV_pc, 58 | /// 11100000 59 | opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, 60 | /// 11101000 61 | opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, opMOV_i, 62 | /// 11110000 63 | opFADD, opFSUB, opFMUL, opFDIV, opFCMP_EQ, opFCMP_GT, opfxx6, opfxx7, 64 | /// 11111000 65 | opfxx8, opfxx9, opfxxa, opfxxb, opFMOV, opfxxd, opFMAC, NULL, 66 | }; 67 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/AArch64/AArch64GenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | 2 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 3 | /* By Nguyen Anh Quynh , 2013-2019 */ 4 | 5 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| 6 | |* Subtarget Enumeration Source Fragment *| 7 | |* *| 8 | |* Automatically generated file, do not edit! *| 9 | |* *| 10 | \*===----------------------------------------------------------------------===*/ 11 | 12 | 13 | enum { 14 | AArch64_FeatureAES = 0, 15 | AArch64_FeatureAggressiveFMA = 1, 16 | AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 2, 17 | AArch64_FeatureArithmeticBccFusion = 3, 18 | AArch64_FeatureArithmeticCbzFusion = 4, 19 | AArch64_FeatureBalanceFPOps = 5, 20 | AArch64_FeatureCRC = 6, 21 | AArch64_FeatureCrypto = 7, 22 | AArch64_FeatureCustomCheapAsMoveHandling = 8, 23 | AArch64_FeatureDisableLatencySchedHeuristic = 9, 24 | AArch64_FeatureDotProd = 10, 25 | AArch64_FeatureExynosCheapAsMoveHandling = 11, 26 | AArch64_FeatureFPARMv8 = 12, 27 | AArch64_FeatureFullFP16 = 13, 28 | AArch64_FeatureFuseAES = 14, 29 | AArch64_FeatureFuseAddress = 15, 30 | AArch64_FeatureFuseCCSelect = 16, 31 | AArch64_FeatureFuseLiterals = 17, 32 | AArch64_FeatureLSE = 18, 33 | AArch64_FeatureLSLFast = 19, 34 | AArch64_FeatureNEON = 20, 35 | AArch64_FeatureNoNegativeImmediates = 21, 36 | AArch64_FeaturePerfMon = 22, 37 | AArch64_FeaturePostRAScheduler = 23, 38 | AArch64_FeaturePredictableSelectIsExpensive = 24, 39 | AArch64_FeatureRAS = 25, 40 | AArch64_FeatureRCPC = 26, 41 | AArch64_FeatureRDM = 27, 42 | AArch64_FeatureReserveX18 = 28, 43 | AArch64_FeatureReserveX20 = 29, 44 | AArch64_FeatureSHA2 = 30, 45 | AArch64_FeatureSHA3 = 31, 46 | AArch64_FeatureSM4 = 32, 47 | AArch64_FeatureSPE = 33, 48 | AArch64_FeatureSVE = 34, 49 | AArch64_FeatureSlowMisaligned128Store = 35, 50 | AArch64_FeatureSlowPaired128 = 36, 51 | AArch64_FeatureSlowSTRQro = 37, 52 | AArch64_FeatureStrictAlign = 38, 53 | AArch64_FeatureUseAA = 39, 54 | AArch64_FeatureUseRSqrt = 40, 55 | AArch64_FeatureZCRegMove = 41, 56 | AArch64_FeatureZCZeroing = 42, 57 | AArch64_FeatureZCZeroingFPWorkaround = 43, 58 | AArch64_HasV8_1aOps = 44, 59 | AArch64_HasV8_2aOps = 45, 60 | AArch64_HasV8_3aOps = 46, 61 | AArch64_HasV8_4aOps = 47, 62 | AArch64_ProcA35 = 48, 63 | AArch64_ProcA53 = 49, 64 | AArch64_ProcA55 = 50, 65 | AArch64_ProcA57 = 51, 66 | AArch64_ProcA72 = 52, 67 | AArch64_ProcA73 = 53, 68 | AArch64_ProcA75 = 54, 69 | AArch64_ProcCyclone = 55, 70 | AArch64_ProcExynosM1 = 56, 71 | AArch64_ProcExynosM2 = 57, 72 | AArch64_ProcExynosM3 = 58, 73 | AArch64_ProcFalkor = 59, 74 | AArch64_ProcKryo = 60, 75 | AArch64_ProcSaphira = 61, 76 | AArch64_ProcThunderX = 62, 77 | AArch64_ProcThunderX2T99 = 63, 78 | AArch64_ProcThunderXT81 = 64, 79 | AArch64_ProcThunderXT83 = 65, 80 | AArch64_ProcThunderXT88 = 66, 81 | }; 82 | 83 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/BPF/BPFConstants.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | /* This file defines constants and macros used for parsing a BPF instruction */ 5 | 6 | #ifndef CS_BPF_CONSTANTS_H 7 | #define CS_BPF_CONSTANTS_H 8 | 9 | #define BPF_CLASS(code) ((code) & 0x7) 10 | 11 | ///< Instruction classes 12 | #define BPF_CLASS_LD 0x00 13 | #define BPF_CLASS_LDX 0x01 14 | #define BPF_CLASS_ST 0x02 15 | #define BPF_CLASS_STX 0x03 16 | #define BPF_CLASS_ALU 0x04 17 | #define BPF_CLASS_JMP 0x05 18 | #define BPF_CLASS_RET 0x06 ///< cBPF only 19 | #define BPF_CLASS_MISC 0x07 ///< cBPF only 20 | #define BPF_CLASS_ALU64 0x07 ///< eBPF only 21 | 22 | #define BPF_OP(code) ((code) & 0xf0) 23 | 24 | ///< Types of ALU instruction 25 | #define BPF_ALU_ADD 0x00 26 | #define BPF_ALU_SUB 0x10 27 | #define BPF_ALU_MUL 0x20 28 | #define BPF_ALU_DIV 0x30 29 | #define BPF_ALU_OR 0x40 30 | #define BPF_ALU_AND 0x50 31 | #define BPF_ALU_LSH 0x60 32 | #define BPF_ALU_RSH 0x70 33 | #define BPF_ALU_NEG 0x80 34 | #define BPF_ALU_MOD 0x90 35 | #define BPF_ALU_XOR 0xa0 36 | #define BPF_ALU_MOV 0xb0 ///< eBPF only: mov reg to reg 37 | #define BPF_ALU_ARSH 0xc0 ///< eBPF only: sign extending shift right 38 | #define BPF_ALU_END 0xd0 ///< eBPF only: endianness conversion 39 | 40 | ///< Types of jmp instruction 41 | #define BPF_JUMP_JA 0x00 ///< goto 42 | #define BPF_JUMP_JEQ 0x10 ///< '==' 43 | #define BPF_JUMP_JGT 0x20 ///< unsigned '>' 44 | #define BPF_JUMP_JGE 0x30 ///< unsigned '>=' 45 | #define BPF_JUMP_JSET 0x40 ///< '&' 46 | #define BPF_JUMP_JNE 0x50 ///< eBPF only: '!=' */ 47 | #define BPF_JUMP_JSGT 0x60 ///< eBPF only: signed '>' 48 | #define BPF_JUMP_JSGE 0x70 ///< eBPF only: signed '>=' 49 | #define BPF_JUMP_CALL 0x80 ///< eBPF only: function call 50 | #define BPF_JUMP_EXIT 0x90 ///< eBPF only: exit 51 | #define BPF_JUMP_JLT 0xa0 ///< eBPF only: unsigned '<' 52 | #define BPF_JUMP_JLE 0xb0 ///< eBPF only: unsigned '<=' 53 | #define BPF_JUMP_JSLT 0xc0 ///< eBPF only: signed '<' 54 | #define BPF_JUMP_JSLE 0xd0 ///< eBPF only: signed '<=' 55 | 56 | #define BPF_SRC(code) ((code) & 0x08) 57 | #define BPF_RVAL(code) ((code) & 0x18) /* cBPF only: for return types */ 58 | ///< Source operand 59 | #define BPF_SRC_K 0x00 60 | #define BPF_SRC_X 0x08 61 | #define BPF_SRC_A 0x10 /* cBPF only */ 62 | 63 | #define BPF_SRC_LITTLE BPF_SRC_K 64 | #define BPF_SRC_BIG BPF_SRC_X 65 | 66 | #define BPF_SIZE(code) ((code) & 0x18) 67 | ///< Size modifier 68 | #define BPF_SIZE_W 0x00 ///< word 69 | #define BPF_SIZE_H 0x08 ///< half word 70 | #define BPF_SIZE_B 0x10 ///< byte 71 | #define BPF_SIZE_DW 0x18 ///< eBPF only: double word 72 | 73 | #define BPF_MODE(code) ((code) & 0xe0) 74 | ///< Mode modifier 75 | #define BPF_MODE_IMM 0x00 ///< used for 32-bit mov in cBPF and 64-bit in eBPF 76 | #define BPF_MODE_ABS 0x20 77 | #define BPF_MODE_IND 0x40 78 | #define BPF_MODE_MEM 0x60 79 | #define BPF_MODE_LEN 0x80 ///< cBPF only, reserved in eBPF 80 | #define BPF_MODE_MSH 0xa0 ///< cBPF only, reserved in eBPF 81 | #define BPF_MODE_XADD 0xc0 ///< eBPF only: exclusive add 82 | 83 | #define BPF_MISCOP(code) ((code) & 0x80) 84 | ///< Operation of misc 85 | #define BPF_MISCOP_TAX 0x00 86 | #define BPF_MISCOP_TXA 0x80 87 | 88 | #endif 89 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/RISCV/RISCVBaseInfo.h: -------------------------------------------------------------------------------- 1 | //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains small standalone enum definitions for the RISCV target 11 | // useful for the compiler back-end and the MC libraries. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | #ifndef CS_RISCVBASEINFO_H 15 | #define CS_RISCVBASEINFO_H 16 | #include "../../cs_priv.h" 17 | 18 | //#include "RISCVMCTargetDesc.h" 19 | 20 | // RISCVII - This namespace holds all of the target specific flags that 21 | // instruction info tracks. All definitions must match RISCVInstrFormats.td. 22 | enum { 23 | IRISCVII_InstFormatPseudo = 0, 24 | IRISCVII_InstFormatR = 1, 25 | IRISCVII_InstFormatR4 = 2, 26 | IRISCVII_InstFormatI = 3, 27 | IRISCVII_InstFormatS = 4, 28 | IRISCVII_InstFormatB = 5, 29 | IRISCVII_InstFormatU = 6, 30 | IRISCVII_InstFormatJ = 7, 31 | IRISCVII_InstFormatCR = 8, 32 | IRISCVII_InstFormatCI = 9, 33 | IRISCVII_InstFormatCSS = 10, 34 | IRISCVII_InstFormatCIW = 11, 35 | IRISCVII_InstFormatCL = 12, 36 | IRISCVII_InstFormatCS = 13, 37 | IRISCVII_InstFormatCA = 14, 38 | IRISCVII_InstFormatCB = 15, 39 | IRISCVII_InstFormatCJ = 16, 40 | IRISCVII_InstFormatOther = 17, 41 | 42 | IRISCVII_InstFormatMask = 31 43 | }; 44 | 45 | enum { 46 | RISCVII_MO_None, 47 | RISCVII_MO_LO, 48 | RISCVII_MO_HI, 49 | RISCVII_MO_PCREL_HI, 50 | }; 51 | 52 | // Describes the predecessor/successor bits used in the FENCE instruction. 53 | enum FenceField { 54 | RISCVFenceField_I = 8, 55 | RISCVFenceField_O = 4, 56 | RISCVFenceField_R = 2, 57 | RISCVFenceField_W = 1 58 | }; 59 | 60 | // Describes the supported floating point rounding mode encodings. 61 | enum RoundingMode { 62 | RISCVFPRndMode_RNE = 0, 63 | RISCVFPRndMode_RTZ = 1, 64 | RISCVFPRndMode_RDN = 2, 65 | RISCVFPRndMode_RUP = 3, 66 | RISCVFPRndMode_RMM = 4, 67 | RISCVFPRndMode_DYN = 7, 68 | RISCVFPRndMode_Invalid 69 | }; 70 | 71 | static const char *roundingModeToString(enum RoundingMode RndMode) 72 | { 73 | switch (RndMode) { 74 | default: 75 | CS_ASSERT(0 && "Unknown floating point rounding mode"); 76 | case RISCVFPRndMode_RNE: 77 | return "rne"; 78 | case RISCVFPRndMode_RTZ: 79 | return "rtz"; 80 | case RISCVFPRndMode_RDN: 81 | return "rdn"; 82 | case RISCVFPRndMode_RUP: 83 | return "rup"; 84 | case RISCVFPRndMode_RMM: 85 | return "rmm"; 86 | case RISCVFPRndMode_DYN: 87 | return "dyn"; 88 | } 89 | } 90 | 91 | static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) 92 | { 93 | switch (Mode) { 94 | default: 95 | return false; 96 | case RISCVFPRndMode_RNE: 97 | case RISCVFPRndMode_RTZ: 98 | case RISCVFPRndMode_RDN: 99 | case RISCVFPRndMode_RUP: 100 | case RISCVFPRndMode_RMM: 101 | case RISCVFPRndMode_DYN: 102 | return true; 103 | } 104 | } 105 | 106 | #endif 107 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/X86/X86Mapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_X86_MAP_H 5 | #define CS_X86_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../cs_priv.h" 9 | 10 | // map instruction to its characteristics 11 | typedef struct insn_map_x86 { 12 | unsigned short id; 13 | unsigned short mapid; 14 | unsigned char is64bit; 15 | #ifndef CAPSTONE_DIET 16 | uint16_t regs_use[12]; // list of implicit registers used by this instruction 17 | uint16_t regs_mod[20]; // list of implicit registers modified by this instruction 18 | unsigned char groups[8]; // list of group this instruction belong to 19 | bool branch; // branch instruction? 20 | bool indirect_branch; // indirect branch instruction? 21 | #endif 22 | } insn_map_x86; 23 | 24 | extern const insn_map_x86 insns[]; 25 | 26 | // map sib_base to x86_reg 27 | x86_reg x86_map_sib_base(int r); 28 | 29 | // map sib_index to x86_reg 30 | x86_reg x86_map_sib_index(int r); 31 | 32 | // map seg_override to x86_reg 33 | x86_reg x86_map_segment(int r); 34 | 35 | // return name of regiser in friendly string 36 | const char *X86_reg_name(csh handle, unsigned int reg); 37 | 38 | // given internal insn id, return public instruction info 39 | void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 40 | 41 | // return insn name, given insn id 42 | const char *X86_insn_name(csh handle, unsigned int id); 43 | 44 | // return group name, given group id 45 | const char *X86_group_name(csh handle, unsigned int id); 46 | 47 | // return register of given instruction id 48 | // return 0 if not found 49 | // this is to handle instructions embedding accumulate registers into AsmStrs[] 50 | x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access); 51 | x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access); 52 | bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2); 53 | bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2); 54 | 55 | extern const uint64_t arch_masks[9]; 56 | 57 | // handle LOCK/REP/REPNE prefixes 58 | // return True if we patch mnemonic, like in MULPD case 59 | bool X86_lockrep(MCInst *MI, SStream *O); 60 | 61 | // map registers to sizes 62 | extern const uint8_t regsize_map_32[]; 63 | extern const uint8_t regsize_map_64[]; 64 | 65 | void op_addReg(MCInst *MI, int reg); 66 | void op_addImm(MCInst *MI, int v); 67 | 68 | void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v); 69 | 70 | void op_addXopCC(MCInst *MI, int v); 71 | void op_addSseCC(MCInst *MI, int v); 72 | void op_addAvxCC(MCInst *MI, int v); 73 | 74 | void op_addAvxZeroOpmask(MCInst *MI); 75 | 76 | void op_addAvxSae(MCInst *MI); 77 | 78 | void op_addAvxRoundingMode(MCInst *MI, int v); 79 | 80 | // given internal insn id, return operand access info 81 | const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags); 82 | 83 | void X86_reg_access(const cs_insn *insn, 84 | cs_regs regs_read, uint8_t *regs_read_count, 85 | cs_regs regs_write, uint8_t *regs_write_count); 86 | 87 | // given the instruction id, return the size of its immediate operand (or 0) 88 | uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size); 89 | 90 | unsigned short X86_register_map(unsigned short id); 91 | 92 | unsigned int find_insn(unsigned int id); 93 | 94 | #endif 95 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/LICENSE_LLVM.TXT: -------------------------------------------------------------------------------- 1 | ============================================================================== 2 | LLVM Release License 3 | ============================================================================== 4 | University of Illinois/NCSA 5 | Open Source License 6 | 7 | Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign. 8 | All rights reserved. 9 | 10 | Developed by: 11 | 12 | LLVM Team 13 | 14 | University of Illinois at Urbana-Champaign 15 | 16 | http://llvm.org 17 | 18 | Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | this software and associated documentation files (the "Software"), to deal with 20 | the Software without restriction, including without limitation the rights to 21 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | of the Software, and to permit persons to whom the Software is furnished to do 23 | so, subject to the following conditions: 24 | 25 | * Redistributions of source code must retain the above copyright notice, 26 | this list of conditions and the following disclaimers. 27 | 28 | * Redistributions in binary form must reproduce the above copyright notice, 29 | this list of conditions and the following disclaimers in the 30 | documentation and/or other materials provided with the distribution. 31 | 32 | * Neither the names of the LLVM Team, University of Illinois at 33 | Urbana-Champaign, nor the names of its contributors may be used to 34 | endorse or promote products derived from this Software without specific 35 | prior written permission. 36 | 37 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 38 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 39 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 40 | CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 41 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 42 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE 43 | SOFTWARE. 44 | 45 | ============================================================================== 46 | Copyrights and Licenses for Third Party Software Distributed with LLVM: 47 | ============================================================================== 48 | The LLVM software contains code written by third parties. Such software will 49 | have its own individual LICENSE.TXT file in the directory in which it appears. 50 | This file will describe the copyrights, license, and restrictions which apply 51 | to that code. 52 | 53 | The disclaimer of warranty in the University of Illinois Open Source License 54 | applies to all code in the LLVM Distribution, and nothing in any of the 55 | other licenses gives permission to use the names of the LLVM Team or the 56 | University of Illinois to endorse or promote products derived from this 57 | Software. 58 | 59 | The following pieces of software have additional or alternate copyrights, 60 | licenses, and/or restrictions: 61 | 62 | Program Directory 63 | ------- --------- 64 | Autoconf llvm/autoconf 65 | llvm/projects/ModuleMaker/autoconf 66 | llvm/projects/sample/autoconf 67 | Google Test llvm/utils/unittest/googletest 68 | OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} 69 | pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} 70 | ARM contributions llvm/lib/Target/ARM/LICENSE.TXT 71 | md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h 72 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/cs_priv.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #ifndef CS_PRIV_H 5 | #define CS_PRIV_H 6 | 7 | #ifdef CAPSTONE_DEBUG 8 | #include 9 | #endif 10 | #include 11 | 12 | #include "MCInst.h" 13 | #include "SStream.h" 14 | 15 | typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info); 16 | 17 | // function to be called after Printer_t 18 | // this is the best time to gather insn's characteristics 19 | typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci); 20 | 21 | typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 22 | 23 | typedef const char *(*GetName_t)(csh handle, unsigned int id); 24 | 25 | typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id); 26 | 27 | // return register name, given register ID 28 | typedef const char *(*GetRegisterName_t)(unsigned RegNo); 29 | 30 | // return registers accessed by instruction 31 | typedef void (*GetRegisterAccess_t)(const cs_insn *insn, 32 | cs_regs regs_read, uint8_t *regs_read_count, 33 | cs_regs regs_write, uint8_t *regs_write_count); 34 | 35 | // for ARM only 36 | typedef struct ARM_ITStatus { 37 | unsigned char ITStates[8]; 38 | unsigned int size; 39 | } ARM_ITStatus; 40 | 41 | // Customize mnemonic for instructions with alternative name. 42 | struct customized_mnem { 43 | // ID of instruction to be customized. 44 | unsigned int id; 45 | // Customized instruction mnemonic. 46 | char mnemonic[CS_MNEMONIC_SIZE]; 47 | }; 48 | 49 | struct insn_mnem { 50 | struct customized_mnem insn; 51 | struct insn_mnem *next; // linked list of customized mnemonics 52 | }; 53 | 54 | struct cs_struct { 55 | cs_arch arch; 56 | cs_mode mode; 57 | Printer_t printer; // asm printer 58 | void *printer_info; // aux info for printer 59 | Disasm_t disasm; // disassembler 60 | void *getinsn_info; // auxiliary info for printer 61 | GetName_t reg_name; 62 | GetName_t insn_name; 63 | GetName_t group_name; 64 | GetID_t insn_id; 65 | PostPrinter_t post_printer; 66 | cs_err errnum; 67 | ARM_ITStatus ITBlock; // for Arm only 68 | cs_opt_value detail, imm_unsigned; 69 | int syntax; // asm syntax for simple printer such as ARM, Mips & PPC 70 | bool doing_mem; // handling memory operand in InstPrinter code 71 | unsigned short *insn_cache; // index caching for mapping.c 72 | GetRegisterName_t get_regname; 73 | bool skipdata; // set this to True if we skip data when disassembling 74 | uint8_t skipdata_size; // how many bytes to skip 75 | cs_opt_skipdata skipdata_setup; // user-defined skipdata setup 76 | const uint8_t *regsize_map; // map to register size (x86-only for now) 77 | GetRegisterAccess_t reg_access; 78 | struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic 79 | }; 80 | 81 | #define MAX_ARCH CS_ARCH_MAX 82 | 83 | // Returns a bool (0 or 1) whether big endian is enabled for a mode 84 | #define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0) 85 | 86 | extern cs_malloc_t cs_mem_malloc; 87 | extern cs_calloc_t cs_mem_calloc; 88 | extern cs_realloc_t cs_mem_realloc; 89 | extern cs_free_t cs_mem_free; 90 | extern cs_vsnprintf_t cs_vsnprintf; 91 | 92 | // By defining CAPSTONE_DEBUG assertions can be used. 93 | // For any release build CAPSTONE_DEBUG has to be undefined. 94 | #ifdef CAPSTONE_DEBUG 95 | #define CS_ASSERT(expr) assert(expr) 96 | #else 97 | #define CS_ASSERT(expr) 98 | #endif 99 | 100 | #endif 101 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/include/windowsce/stdint.h: -------------------------------------------------------------------------------- 1 | 2 | #if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT) 3 | #define _STDINT 4 | 5 | typedef __int8 6 | int8_t, 7 | int_least8_t; 8 | 9 | typedef __int16 10 | int16_t, 11 | int_least16_t; 12 | 13 | typedef __int32 14 | int32_t, 15 | int_least32_t, 16 | int_fast8_t, 17 | int_fast16_t, 18 | int_fast32_t; 19 | 20 | typedef __int64 21 | int64_t, 22 | intmax_t, 23 | int_least64_t, 24 | int_fast64_t; 25 | 26 | typedef unsigned __int8 27 | uint8_t, 28 | uint_least8_t; 29 | 30 | typedef unsigned __int16 31 | uint16_t, 32 | uint_least16_t; 33 | 34 | typedef unsigned __int32 35 | uint32_t, 36 | uint_least32_t, 37 | uint_fast8_t, 38 | uint_fast16_t, 39 | uint_fast32_t; 40 | 41 | typedef unsigned __int64 42 | uint64_t, 43 | uintmax_t, 44 | uint_least64_t, 45 | uint_fast64_t; 46 | 47 | #ifndef _INTPTR_T_DEFINED 48 | #define _INTPTR_T_DEFINED 49 | typedef __int32 intptr_t; 50 | #endif 51 | 52 | #ifndef _UINTPTR_T_DEFINED 53 | #define _UINTPTR_T_DEFINED 54 | typedef unsigned __int32 uintptr_t; 55 | #endif 56 | 57 | #define INT8_MIN (-127i8 - 1) 58 | #define INT16_MIN (-32767i16 - 1) 59 | #define INT32_MIN (-2147483647i32 - 1) 60 | #define INT64_MIN (-9223372036854775807i64 - 1) 61 | #define INT8_MAX 127i8 62 | #define INT16_MAX 32767i16 63 | #define INT32_MAX 2147483647i32 64 | #define INT64_MAX 9223372036854775807i64 65 | #define UINT8_MAX 0xffui8 66 | #define UINT16_MAX 0xffffui16 67 | #define UINT32_MAX 0xffffffffui32 68 | #define UINT64_MAX 0xffffffffffffffffui64 69 | 70 | #define INT_LEAST8_MIN INT8_MIN 71 | #define INT_LEAST16_MIN INT16_MIN 72 | #define INT_LEAST32_MIN INT32_MIN 73 | #define INT_LEAST64_MIN INT64_MIN 74 | #define INT_LEAST8_MAX INT8_MAX 75 | #define INT_LEAST16_MAX INT16_MAX 76 | #define INT_LEAST32_MAX INT32_MAX 77 | #define INT_LEAST64_MAX INT64_MAX 78 | #define UINT_LEAST8_MAX UINT8_MAX 79 | #define UINT_LEAST16_MAX UINT16_MAX 80 | #define UINT_LEAST32_MAX UINT32_MAX 81 | #define UINT_LEAST64_MAX UINT64_MAX 82 | 83 | #define INT_FAST8_MIN INT8_MIN 84 | #define INT_FAST16_MIN INT32_MIN 85 | #define INT_FAST32_MIN INT32_MIN 86 | #define INT_FAST64_MIN INT64_MIN 87 | #define INT_FAST8_MAX INT8_MAX 88 | #define INT_FAST16_MAX INT32_MAX 89 | #define INT_FAST32_MAX INT32_MAX 90 | #define INT_FAST64_MAX INT64_MAX 91 | #define UINT_FAST8_MAX UINT8_MAX 92 | #define UINT_FAST16_MAX UINT32_MAX 93 | #define UINT_FAST32_MAX UINT32_MAX 94 | #define UINT_FAST64_MAX UINT64_MAX 95 | 96 | #define INTPTR_MIN INT32_MIN 97 | #define INTPTR_MAX INT32_MAX 98 | #define UINTPTR_MAX UINT32_MAX 99 | 100 | #define INTMAX_MIN INT64_MIN 101 | #define INTMAX_MAX INT64_MAX 102 | #define UINTMAX_MAX UINT64_MAX 103 | 104 | #define PTRDIFF_MIN INTPTR_MIN 105 | #define PTRDIFF_MAX INTPTR_MAX 106 | 107 | #ifndef SIZE_MAX 108 | #define SIZE_MAX UINTPTR_MAX 109 | #endif 110 | 111 | #define SIG_ATOMIC_MIN INT32_MIN 112 | #define SIG_ATOMIC_MAX INT32_MAX 113 | 114 | #define WCHAR_MIN 0x0000 115 | #define WCHAR_MAX 0xffff 116 | 117 | #define WINT_MIN 0x0000 118 | #define WINT_MAX 0xffff 119 | 120 | #define INT8_C(x) (x) 121 | #define INT16_C(x) (x) 122 | #define INT32_C(x) (x) 123 | #define INT64_C(x) (x ## LL) 124 | 125 | #define UINT8_C(x) (x) 126 | #define UINT16_C(x) (x) 127 | #define UINT32_C(x) (x ## U) 128 | #define UINT64_C(x) (x ## ULL) 129 | 130 | #define INTMAX_C(x) INT64_C(x) 131 | #define UINTMAX_C(x) UINT64_C(x) 132 | 133 | #endif 134 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/XCore/XCoreGenRegisterInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Target Register Enum Values *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine */ 10 | /* By Nguyen Anh Quynh , 2013-2019 */ 11 | 12 | 13 | #ifdef GET_REGINFO_ENUM 14 | #undef GET_REGINFO_ENUM 15 | 16 | enum { 17 | XCore_NoRegister, 18 | XCore_CP = 1, 19 | XCore_DP = 2, 20 | XCore_LR = 3, 21 | XCore_SP = 4, 22 | XCore_R0 = 5, 23 | XCore_R1 = 6, 24 | XCore_R2 = 7, 25 | XCore_R3 = 8, 26 | XCore_R4 = 9, 27 | XCore_R5 = 10, 28 | XCore_R6 = 11, 29 | XCore_R7 = 12, 30 | XCore_R8 = 13, 31 | XCore_R9 = 14, 32 | XCore_R10 = 15, 33 | XCore_R11 = 16, 34 | XCore_NUM_TARGET_REGS // 17 35 | }; 36 | 37 | // Register classes 38 | enum { 39 | XCore_RRegsRegClassID = 0, 40 | XCore_GRRegsRegClassID = 1 41 | }; 42 | 43 | #endif // GET_REGINFO_ENUM 44 | 45 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 46 | |* *| 47 | |*MC Register Information *| 48 | |* *| 49 | |* Automatically generated file, do not edit! *| 50 | |* *| 51 | \*===----------------------------------------------------------------------===*/ 52 | 53 | 54 | #ifdef GET_REGINFO_MC_DESC 55 | #undef GET_REGINFO_MC_DESC 56 | 57 | static const MCPhysReg XCoreRegDiffLists[] = { 58 | /* 0 */ 65535, 0, 59 | }; 60 | 61 | static const uint16_t XCoreSubRegIdxLists[] = { 62 | /* 0 */ 0, 63 | }; 64 | 65 | static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors 66 | { 3, 0, 0, 0, 0, 0 }, 67 | { 38, 1, 1, 0, 1, 0 }, 68 | { 41, 1, 1, 0, 1, 0 }, 69 | { 47, 1, 1, 0, 1, 0 }, 70 | { 44, 1, 1, 0, 1, 0 }, 71 | { 4, 1, 1, 0, 1, 0 }, 72 | { 11, 1, 1, 0, 1, 0 }, 73 | { 14, 1, 1, 0, 1, 0 }, 74 | { 17, 1, 1, 0, 1, 0 }, 75 | { 20, 1, 1, 0, 1, 0 }, 76 | { 23, 1, 1, 0, 1, 0 }, 77 | { 26, 1, 1, 0, 1, 0 }, 78 | { 29, 1, 1, 0, 1, 0 }, 79 | { 32, 1, 1, 0, 1, 0 }, 80 | { 35, 1, 1, 0, 1, 0 }, 81 | { 0, 1, 1, 0, 1, 0 }, 82 | { 7, 1, 1, 0, 1, 0 }, 83 | }; 84 | 85 | // RRegs Register Class... 86 | static const MCPhysReg RRegs[] = { 87 | XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR, 88 | }; 89 | 90 | // RRegs Bit set. 91 | static const uint8_t RRegsBits[] = { 92 | 0xfe, 0xff, 0x01, 93 | }; 94 | 95 | // GRRegs Register Class... 96 | static const MCPhysReg GRRegs[] = { 97 | XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, 98 | }; 99 | 100 | // GRRegs Bit set. 101 | static const uint8_t GRRegsBits[] = { 102 | 0xe0, 0xff, 0x01, 103 | }; 104 | 105 | static const MCRegisterClass XCoreMCRegisterClasses[] = { 106 | { RRegs, RRegsBits, sizeof(RRegsBits) }, 107 | { GRRegs, GRRegsBits, sizeof(GRRegsBits) }, 108 | }; 109 | 110 | #endif // GET_REGINFO_MC_DESC 111 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/include/platform.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Axel Souchet & Nguyen Anh Quynh, 2014 */ 3 | 4 | #ifndef CAPSTONE_PLATFORM_H 5 | #define CAPSTONE_PLATFORM_H 6 | 7 | // handle C99 issue (for pre-2013 VisualStudio) 8 | #if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) 9 | // MSVC 10 | 11 | // stdbool.h 12 | #if (_MSC_VER < 1800) || defined(_KERNEL_MODE) 13 | // this system does not have stdbool.h 14 | #ifndef __cplusplus 15 | typedef unsigned char bool; 16 | #define false 0 17 | #define true 1 18 | #endif 19 | 20 | #else 21 | // VisualStudio 2013+ -> C99 is supported 22 | #include 23 | #endif 24 | 25 | #else 26 | // not MSVC -> C99 is supported 27 | #include 28 | #endif 29 | 30 | 31 | // handle C99 issue (for pre-2013 VisualStudio) 32 | #if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) 33 | // this system does not have inttypes.h 34 | 35 | #if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) 36 | // this system does not have stdint.h 37 | typedef signed char int8_t; 38 | typedef signed short int16_t; 39 | typedef signed int int32_t; 40 | typedef unsigned char uint8_t; 41 | typedef unsigned short uint16_t; 42 | typedef unsigned int uint32_t; 43 | typedef signed long long int64_t; 44 | typedef unsigned long long uint64_t; 45 | 46 | #define INT8_MIN (-127i8 - 1) 47 | #define INT16_MIN (-32767i16 - 1) 48 | #define INT32_MIN (-2147483647i32 - 1) 49 | #define INT64_MIN (-9223372036854775807i64 - 1) 50 | #define INT8_MAX 127i8 51 | #define INT16_MAX 32767i16 52 | #define INT32_MAX 2147483647i32 53 | #define INT64_MAX 9223372036854775807i64 54 | #define UINT8_MAX 0xffui8 55 | #define UINT16_MAX 0xffffui16 56 | #define UINT32_MAX 0xffffffffui32 57 | #define UINT64_MAX 0xffffffffffffffffui64 58 | #endif 59 | 60 | #define __PRI_8_LENGTH_MODIFIER__ "hh" 61 | #define __PRI_64_LENGTH_MODIFIER__ "ll" 62 | 63 | #define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" 64 | #define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" 65 | #define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" 66 | #define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" 67 | #define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" 68 | #define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" 69 | 70 | #define PRId16 "hd" 71 | #define PRIi16 "hi" 72 | #define PRIo16 "ho" 73 | #define PRIu16 "hu" 74 | #define PRIx16 "hx" 75 | #define PRIX16 "hX" 76 | 77 | #if defined(_MSC_VER) && _MSC_VER <= 1700 78 | #define PRId32 "ld" 79 | #define PRIi32 "li" 80 | #define PRIo32 "lo" 81 | #define PRIu32 "lu" 82 | #define PRIx32 "lx" 83 | #define PRIX32 "lX" 84 | #else // OSX 85 | #define PRId32 "d" 86 | #define PRIi32 "i" 87 | #define PRIo32 "o" 88 | #define PRIu32 "u" 89 | #define PRIx32 "x" 90 | #define PRIX32 "X" 91 | #endif 92 | 93 | #if defined(_MSC_VER) && _MSC_VER <= 1700 94 | // redefine functions from inttypes.h used in cstool 95 | #define strtoull _strtoui64 96 | #endif 97 | 98 | #define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" 99 | #define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" 100 | #define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" 101 | #define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" 102 | #define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" 103 | #define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" 104 | 105 | #else 106 | // this system has inttypes.h by default 107 | #include 108 | #endif 109 | 110 | #endif 111 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/utils.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #if defined(CAPSTONE_HAS_OSXKERNEL) 5 | #include 6 | #include 7 | #else 8 | #include 9 | #endif 10 | #include 11 | 12 | #include "utils.h" 13 | 14 | // create a cache for fast id lookup 15 | static unsigned short *make_id2insn(const insn_map *insns, unsigned int size) 16 | { 17 | // NOTE: assume that the max id is always put at the end of insns array 18 | unsigned short max_id = insns[size - 1].id; 19 | unsigned short i; 20 | 21 | unsigned short *cache = (unsigned short *)cs_mem_calloc(max_id + 1, sizeof(*cache)); 22 | 23 | for (i = 1; i < size; i++) 24 | cache[insns[i].id] = i; 25 | 26 | return cache; 27 | } 28 | 29 | // look for @id in @insns, given its size in @max. first time call will update @cache. 30 | // return 0 if not found 31 | unsigned short insn_find(const insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache) 32 | { 33 | if (id > insns[max - 1].id) 34 | return 0; 35 | 36 | if (*cache == NULL) 37 | *cache = make_id2insn(insns, max); 38 | 39 | return (*cache)[id]; 40 | } 41 | 42 | int name2id(const name_map* map, int max, const char *name) 43 | { 44 | int i; 45 | 46 | for (i = 0; i < max; i++) { 47 | if (!strcmp(map[i].name, name)) { 48 | return map[i].id; 49 | } 50 | } 51 | 52 | // nothing match 53 | return -1; 54 | } 55 | 56 | const char *id2name(const name_map* map, int max, const unsigned int id) 57 | { 58 | int i; 59 | 60 | for (i = 0; i < max; i++) { 61 | if (map[i].id == id) { 62 | return map[i].name; 63 | } 64 | } 65 | 66 | // nothing match 67 | return NULL; 68 | } 69 | 70 | // count number of positive members in a list. 71 | // NOTE: list must be guaranteed to end in 0 72 | unsigned int count_positive(const uint16_t *list) 73 | { 74 | unsigned int c; 75 | 76 | for (c = 0; list[c] > 0; c++); 77 | 78 | return c; 79 | } 80 | 81 | // count number of positive members in a list. 82 | // NOTE: list must be guaranteed to end in 0 83 | unsigned int count_positive8(const unsigned char *list) 84 | { 85 | unsigned int c; 86 | 87 | for (c = 0; list[c] > 0; c++); 88 | 89 | return c; 90 | } 91 | 92 | char *cs_strdup(const char *str) 93 | { 94 | size_t len = strlen(str)+ 1; 95 | void *new = cs_mem_malloc(len); 96 | 97 | if (new == NULL) 98 | return NULL; 99 | 100 | return (char *)memmove(new, str, len); 101 | } 102 | 103 | // we need this since Windows doesn't have snprintf() 104 | int cs_snprintf(char *buffer, size_t size, const char *fmt, ...) 105 | { 106 | int ret; 107 | 108 | va_list ap; 109 | va_start(ap, fmt); 110 | ret = cs_vsnprintf(buffer, size, fmt, ap); 111 | va_end(ap); 112 | 113 | return ret; 114 | } 115 | 116 | bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id) 117 | { 118 | int i; 119 | 120 | for (i = 0; i < max; i++) { 121 | if (arr[i] == id) 122 | return true; 123 | } 124 | 125 | return false; 126 | } 127 | 128 | bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id) 129 | { 130 | int i; 131 | 132 | for (i = 0; i < max; i++) { 133 | if (arr[i] == id) 134 | return true; 135 | } 136 | 137 | return false; 138 | } 139 | 140 | // binary search for encoding in IndexType array 141 | // return -1 if not found, or index if found 142 | unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding) 143 | { 144 | // binary searching since the index is sorted in encoding order 145 | size_t left, right, m; 146 | 147 | right = size - 1; 148 | 149 | if (encoding < index[0].encoding || encoding > index[right].encoding) 150 | // not found 151 | return -1; 152 | 153 | left = 0; 154 | 155 | while(left <= right) { 156 | m = (left + right) / 2; 157 | if (encoding == index[m].encoding) { 158 | return m; 159 | } 160 | 161 | if (encoding < index[m].encoding) 162 | right = m - 1; 163 | else 164 | left = m + 1; 165 | } 166 | 167 | // not found 168 | return -1; 169 | } 170 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/m6808.inc: -------------------------------------------------------------------------------- 1 | 2 | // Additional instructions only supported on M68HC08 3 | static const inst_pageX g_m6808_inst_overlay_table[] = { 4 | { 0x31, M680X_INS_CBEQ, dir_hid, rel8_hid }, 5 | { 0x35, M680X_INS_STHX, dir_hid, inh_hid }, 6 | { 0x3b, M680X_INS_DBNZ, dir_hid, rel8_hid }, 7 | { 0x41, M680X_INS_CBEQA, imm8rel_hid, inh_hid }, 8 | { 0x45, M680X_INS_LDHX, imm16_hid, inh_hid }, 9 | { 0x4b, M680X_INS_DBNZA, rel8_hid, inh_hid }, 10 | { 0x4e, M680X_INS_MOV, dir_hid, dir_hid }, 11 | { 0x51, M680X_INS_CBEQX, imm8rel_hid, inh_hid }, 12 | { 0x52, M680X_INS_DIV, inh_hid, inh_hid }, 13 | { 0x55, M680X_INS_LDHX, dir_hid, inh_hid }, 14 | { 0x5b, M680X_INS_DBNZX, rel8_hid, inh_hid }, 15 | { 0x5e, M680X_INS_MOV, dir_hid, idxX0p_hid }, 16 | { 0x61, M680X_INS_CBEQ, idxXp_hid, rel8_hid }, 17 | { 0x62, M680X_INS_NSA, inh_hid, inh_hid }, 18 | { 0x65, M680X_INS_CPHX, imm16_hid, inh_hid }, 19 | { 0x6b, M680X_INS_DBNZ, idxX_hid, rel8_hid }, 20 | { 0x6e, M680X_INS_MOV, imm8_hid, dir_hid }, 21 | { 0x71, M680X_INS_CBEQ, idxX0p_hid, rel8_hid }, 22 | { 0x72, M680X_INS_DAA, inh_hid, inh_hid }, 23 | { 0x75, M680X_INS_CPHX, dir_hid, inh_hid }, 24 | { 0x7b, M680X_INS_DBNZ, idxX0_hid, rel8_hid }, 25 | { 0x7e, M680X_INS_MOV, idxX0p_hid, dir_hid }, 26 | { 0x84, M680X_INS_TAP, inh_hid, inh_hid }, 27 | { 0x85, M680X_INS_TPA, inh_hid, inh_hid }, 28 | { 0x86, M680X_INS_PULA, inh_hid, inh_hid }, 29 | { 0x87, M680X_INS_PSHA, inh_hid, inh_hid }, 30 | { 0x88, M680X_INS_PULX, inh_hid, inh_hid }, 31 | { 0x89, M680X_INS_PSHX, inh_hid, inh_hid }, 32 | { 0x8a, M680X_INS_PULH, inh_hid, inh_hid }, 33 | { 0x8b, M680X_INS_PSHH, inh_hid, inh_hid }, 34 | { 0x8c, M680X_INS_CLRH, inh_hid, inh_hid }, 35 | { 0x90, M680X_INS_BGE, rel8_hid, inh_hid }, 36 | { 0x91, M680X_INS_BLT, rel8_hid, inh_hid }, 37 | { 0x92, M680X_INS_BGT, rel8_hid, inh_hid }, 38 | { 0x93, M680X_INS_BLE, rel8_hid, inh_hid }, 39 | { 0x94, M680X_INS_TXS, inh_hid, inh_hid }, 40 | { 0x95, M680X_INS_TSX, inh_hid, inh_hid }, 41 | { 0x97, M680X_INS_TAX, inh_hid, inh_hid }, 42 | { 0x9f, M680X_INS_TXA, inh_hid, inh_hid }, 43 | { 0xa7, M680X_INS_AIS, imm8_hid, inh_hid }, 44 | { 0xaf, M680X_INS_AIX, imm8_hid, inh_hid }, 45 | }; 46 | 47 | // M68HC08 PAGE2 instructions (prefix 0x9E) 48 | static const inst_pageX g_m6808_inst_page2_table[] = { 49 | { 0x60, M680X_INS_NEG, idxS_hid, inh_hid }, 50 | { 0x61, M680X_INS_CBEQ, idxS_hid, rel8_hid }, 51 | { 0x63, M680X_INS_COM, idxS_hid, inh_hid }, 52 | { 0x64, M680X_INS_LSR, idxS_hid, inh_hid }, 53 | { 0x66, M680X_INS_ROR, idxS_hid, inh_hid }, 54 | { 0x67, M680X_INS_ASR, idxS_hid, inh_hid }, 55 | { 0x68, M680X_INS_LSL, idxS_hid, inh_hid }, 56 | { 0x69, M680X_INS_ROL, idxS_hid, inh_hid }, 57 | { 0x6a, M680X_INS_DEC, idxS_hid, inh_hid }, 58 | { 0x6b, M680X_INS_DBNZ, idxS_hid, rel8_hid }, 59 | { 0x6c, M680X_INS_INC, idxS_hid, inh_hid }, 60 | { 0x6d, M680X_INS_TST, idxS_hid, inh_hid }, 61 | { 0x6f, M680X_INS_CLR, idxS_hid, inh_hid }, 62 | { 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid }, 63 | { 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid }, 64 | { 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid }, 65 | { 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid }, 66 | { 0xd4, M680X_INS_AND, idxS16_hid, inh_hid }, 67 | { 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid }, 68 | { 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid }, 69 | { 0xd7, M680X_INS_STA, idxS16_hid, inh_hid }, 70 | { 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid }, 71 | { 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid }, 72 | { 0xda, M680X_INS_ORA, idxS16_hid, inh_hid }, 73 | { 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid }, 74 | { 0xde, M680X_INS_LDX, idxS16_hid, inh_hid }, 75 | { 0xdf, M680X_INS_STX, idxS16_hid, inh_hid }, 76 | { 0xe0, M680X_INS_SUB, idxS_hid, inh_hid }, 77 | { 0xe1, M680X_INS_CMP, idxS_hid, inh_hid }, 78 | { 0xe2, M680X_INS_SBC, idxS_hid, inh_hid }, 79 | { 0xe3, M680X_INS_CPX, idxS_hid, inh_hid }, 80 | { 0xe4, M680X_INS_AND, idxS_hid, inh_hid }, 81 | { 0xe5, M680X_INS_BIT, idxS_hid, inh_hid }, 82 | { 0xe6, M680X_INS_LDA, idxS_hid, inh_hid }, 83 | { 0xe7, M680X_INS_STA, idxS_hid, inh_hid }, 84 | { 0xe8, M680X_INS_EOR, idxS_hid, inh_hid }, 85 | { 0xe9, M680X_INS_ADC, idxS_hid, inh_hid }, 86 | { 0xea, M680X_INS_ORA, idxS_hid, inh_hid }, 87 | { 0xeb, M680X_INS_ADD, idxS_hid, inh_hid }, 88 | { 0xee, M680X_INS_LDX, idxS_hid, inh_hid }, 89 | { 0xef, M680X_INS_STX, idxS_hid, inh_hid }, 90 | }; 91 | 92 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/MCRegisterInfo.c: -------------------------------------------------------------------------------- 1 | //=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements MCRegisterInfo functions. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2019 */ 16 | 17 | #include "MCRegisterInfo.h" 18 | 19 | /// DiffListIterator - Base iterator class that can traverse the 20 | /// differentially encoded register and regunit lists in DiffLists. 21 | /// Don't use this class directly, use one of the specialized sub-classes 22 | /// defined below. 23 | typedef struct DiffListIterator { 24 | uint16_t Val; 25 | const MCPhysReg *List; 26 | } DiffListIterator; 27 | 28 | void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, 29 | const MCRegisterDesc *D, unsigned NR, 30 | unsigned RA, unsigned PC, 31 | const MCRegisterClass *C, unsigned NC, 32 | uint16_t (*RURoots)[2], unsigned NRU, 33 | const MCPhysReg *DL, 34 | const char *Strings, 35 | const uint16_t *SubIndices, unsigned NumIndices, 36 | const uint16_t *RET) 37 | { 38 | RI->Desc = D; 39 | RI->NumRegs = NR; 40 | RI->RAReg = RA; 41 | RI->PCReg = PC; 42 | RI->Classes = C; 43 | RI->DiffLists = DL; 44 | RI->RegStrings = Strings; 45 | RI->NumClasses = NC; 46 | RI->RegUnitRoots = RURoots; 47 | RI->NumRegUnits = NRU; 48 | RI->SubRegIndices = SubIndices; 49 | RI->NumSubRegIndices = NumIndices; 50 | RI->RegEncodingTable = RET; 51 | } 52 | 53 | static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList) 54 | { 55 | d->Val = InitVal; 56 | d->List = DiffList; 57 | } 58 | 59 | static uint16_t DiffListIterator_getVal(DiffListIterator *d) 60 | { 61 | return d->Val; 62 | } 63 | 64 | static bool DiffListIterator_next(DiffListIterator *d) 65 | { 66 | MCPhysReg D; 67 | 68 | if (d->List == 0) 69 | return false; 70 | 71 | D = *d->List; 72 | d->List++; 73 | d->Val += D; 74 | 75 | if (!D) 76 | d->List = 0; 77 | 78 | return (D != 0); 79 | } 80 | 81 | static bool DiffListIterator_isValid(DiffListIterator *d) 82 | { 83 | return (d->List != 0); 84 | } 85 | 86 | unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) 87 | { 88 | DiffListIterator iter; 89 | 90 | if (Reg >= RI->NumRegs) { 91 | return 0; 92 | } 93 | 94 | DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); 95 | DiffListIterator_next(&iter); 96 | 97 | while(DiffListIterator_isValid(&iter)) { 98 | uint16_t val = DiffListIterator_getVal(&iter); 99 | if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) 100 | return val; 101 | 102 | DiffListIterator_next(&iter); 103 | } 104 | 105 | return 0; 106 | } 107 | 108 | unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx) 109 | { 110 | DiffListIterator iter; 111 | const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; 112 | 113 | DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); 114 | DiffListIterator_next(&iter); 115 | 116 | while(DiffListIterator_isValid(&iter)) { 117 | if (*SRI == Idx) 118 | return DiffListIterator_getVal(&iter); 119 | DiffListIterator_next(&iter); 120 | ++SRI; 121 | } 122 | 123 | return 0; 124 | } 125 | 126 | const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i) 127 | { 128 | //assert(i < getNumRegClasses() && "Register Class ID out of range"); 129 | if (i >= RI->NumClasses) 130 | return 0; 131 | return &(RI->Classes[i]); 132 | } 133 | 134 | bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) 135 | { 136 | unsigned InByte = Reg % 8; 137 | unsigned Byte = Reg / 8; 138 | 139 | if (Byte >= c->RegSetSize) 140 | return false; 141 | 142 | return (c->RegSet[Byte] & (1 << InByte)) != 0; 143 | } 144 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/MCInst.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #if defined(CAPSTONE_HAS_OSXKERNEL) 5 | #include 6 | #include 7 | #else 8 | #include 9 | #include 10 | #endif 11 | #include 12 | 13 | #include "MCInst.h" 14 | #include "utils.h" 15 | 16 | #define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1) 17 | 18 | void MCInst_Init(MCInst *inst) 19 | { 20 | unsigned int i; 21 | 22 | for (i = 0; i < 48; i++) { 23 | inst->Operands[i].Kind = kInvalid; 24 | inst->Operands[i].ImmVal = 0; 25 | } 26 | 27 | inst->Opcode = 0; 28 | inst->OpcodePub = 0; 29 | inst->size = 0; 30 | inst->has_imm = false; 31 | inst->op1_size = 0; 32 | inst->writeback = false; 33 | inst->ac_idx = 0; 34 | inst->popcode_adjust = 0; 35 | inst->assembly[0] = '\0'; 36 | inst->wasm_data.type = WASM_OP_INVALID; 37 | inst->xAcquireRelease = 0; 38 | } 39 | 40 | void MCInst_clear(MCInst *inst) 41 | { 42 | inst->size = 0; 43 | } 44 | 45 | // do not free @Op 46 | void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) 47 | { 48 | int i; 49 | 50 | for(i = inst->size; i > index; i--) 51 | //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand)); 52 | inst->Operands[i] = inst->Operands[i-1]; 53 | 54 | inst->Operands[index] = *Op; 55 | inst->size++; 56 | } 57 | 58 | void MCInst_setOpcode(MCInst *inst, unsigned Op) 59 | { 60 | inst->Opcode = Op; 61 | } 62 | 63 | void MCInst_setOpcodePub(MCInst *inst, unsigned Op) 64 | { 65 | inst->OpcodePub = Op; 66 | } 67 | 68 | unsigned MCInst_getOpcode(const MCInst *inst) 69 | { 70 | return inst->Opcode; 71 | } 72 | 73 | unsigned MCInst_getOpcodePub(const MCInst *inst) 74 | { 75 | return inst->OpcodePub; 76 | } 77 | 78 | MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) 79 | { 80 | return &inst->Operands[i]; 81 | } 82 | 83 | unsigned MCInst_getNumOperands(const MCInst *inst) 84 | { 85 | return inst->size; 86 | } 87 | 88 | // This addOperand2 function doesnt free Op 89 | void MCInst_addOperand2(MCInst *inst, MCOperand *Op) 90 | { 91 | inst->Operands[inst->size] = *Op; 92 | 93 | inst->size++; 94 | } 95 | 96 | bool MCOperand_isValid(const MCOperand *op) 97 | { 98 | return op->Kind != kInvalid; 99 | } 100 | 101 | bool MCOperand_isReg(const MCOperand *op) 102 | { 103 | return op->Kind == kRegister; 104 | } 105 | 106 | bool MCOperand_isImm(const MCOperand *op) 107 | { 108 | return op->Kind == kImmediate; 109 | } 110 | 111 | bool MCOperand_isFPImm(const MCOperand *op) 112 | { 113 | return op->Kind == kFPImmediate; 114 | } 115 | 116 | /// getReg - Returns the register number. 117 | unsigned MCOperand_getReg(const MCOperand *op) 118 | { 119 | return op->RegVal; 120 | } 121 | 122 | /// setReg - Set the register number. 123 | void MCOperand_setReg(MCOperand *op, unsigned Reg) 124 | { 125 | op->RegVal = Reg; 126 | } 127 | 128 | int64_t MCOperand_getImm(MCOperand *op) 129 | { 130 | return op->ImmVal; 131 | } 132 | 133 | void MCOperand_setImm(MCOperand *op, int64_t Val) 134 | { 135 | op->ImmVal = Val; 136 | } 137 | 138 | double MCOperand_getFPImm(const MCOperand *op) 139 | { 140 | return op->FPImmVal; 141 | } 142 | 143 | void MCOperand_setFPImm(MCOperand *op, double Val) 144 | { 145 | op->FPImmVal = Val; 146 | } 147 | 148 | MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) 149 | { 150 | MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); 151 | 152 | op->Kind = kRegister; 153 | op->RegVal = Reg; 154 | 155 | return op; 156 | } 157 | 158 | void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) 159 | { 160 | MCOperand *op = &(mcInst->Operands[mcInst->size]); 161 | mcInst->size++; 162 | 163 | op->Kind = kRegister; 164 | op->RegVal = Reg; 165 | } 166 | 167 | MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) 168 | { 169 | MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); 170 | 171 | op->Kind = kImmediate; 172 | op->ImmVal = Val; 173 | 174 | return op; 175 | } 176 | 177 | void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) 178 | { 179 | MCOperand *op = &(mcInst->Operands[mcInst->size]); 180 | mcInst->size++; 181 | 182 | op->Kind = kImmediate; 183 | op->ImmVal = Val; 184 | } 185 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/capstone/platform.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Axel Souchet & Nguyen Anh Quynh, 2014 */ 3 | 4 | #ifndef CAPSTONE_PLATFORM_H 5 | #define CAPSTONE_PLATFORM_H 6 | 7 | 8 | // handle C99 issue (for pre-2013 VisualStudio) 9 | #if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) 10 | // MSVC 11 | 12 | // stdbool.h 13 | #if (_MSC_VER < 1800) || defined(_KERNEL_MODE) 14 | // this system does not have stdbool.h 15 | #ifndef __cplusplus 16 | typedef unsigned char bool; 17 | #define false 0 18 | #define true 1 19 | #endif // __cplusplus 20 | 21 | #else 22 | // VisualStudio 2013+ -> C99 is supported 23 | #include 24 | #endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE) 25 | 26 | #else 27 | // not MSVC -> C99 is supported 28 | #include 29 | #endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) 30 | 31 | 32 | // handle inttypes.h / stdint.h compatibility 33 | #if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) 34 | #include "windowsce/stdint.h" 35 | #endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) 36 | 37 | #if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) 38 | // this system does not have inttypes.h 39 | 40 | #if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) 41 | // this system does not have stdint.h 42 | typedef signed char int8_t; 43 | typedef signed short int16_t; 44 | typedef signed int int32_t; 45 | typedef unsigned char uint8_t; 46 | typedef unsigned short uint16_t; 47 | typedef unsigned int uint32_t; 48 | typedef signed long long int64_t; 49 | typedef unsigned long long uint64_t; 50 | #endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) 51 | 52 | #if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) 53 | #define INT8_MIN (-127i8 - 1) 54 | #define INT16_MIN (-32767i16 - 1) 55 | #define INT32_MIN (-2147483647i32 - 1) 56 | #define INT64_MIN (-9223372036854775807i64 - 1) 57 | #define INT8_MAX 127i8 58 | #define INT16_MAX 32767i16 59 | #define INT32_MAX 2147483647i32 60 | #define INT64_MAX 9223372036854775807i64 61 | #define UINT8_MAX 0xffui8 62 | #define UINT16_MAX 0xffffui16 63 | #define UINT32_MAX 0xffffffffui32 64 | #define UINT64_MAX 0xffffffffffffffffui64 65 | #endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) 66 | 67 | #ifdef CAPSTONE_HAS_OSXKERNEL 68 | // this system has stdint.h 69 | #include 70 | #endif 71 | 72 | #define __PRI_8_LENGTH_MODIFIER__ "hh" 73 | #define __PRI_64_LENGTH_MODIFIER__ "ll" 74 | 75 | #define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" 76 | #define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" 77 | #define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" 78 | #define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" 79 | #define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" 80 | #define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" 81 | 82 | #define PRId16 "hd" 83 | #define PRIi16 "hi" 84 | #define PRIo16 "ho" 85 | #define PRIu16 "hu" 86 | #define PRIx16 "hx" 87 | #define PRIX16 "hX" 88 | 89 | #if defined(_MSC_VER) && _MSC_VER <= 1700 90 | #define PRId32 "ld" 91 | #define PRIi32 "li" 92 | #define PRIo32 "lo" 93 | #define PRIu32 "lu" 94 | #define PRIx32 "lx" 95 | #define PRIX32 "lX" 96 | #else // OSX 97 | #define PRId32 "d" 98 | #define PRIi32 "i" 99 | #define PRIo32 "o" 100 | #define PRIu32 "u" 101 | #define PRIx32 "x" 102 | #define PRIX32 "X" 103 | #endif // defined(_MSC_VER) && _MSC_VER <= 1700 104 | 105 | #if defined(_MSC_VER) && _MSC_VER <= 1700 106 | // redefine functions from inttypes.h used in cstool 107 | #define strtoull _strtoui64 108 | #endif 109 | 110 | #define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" 111 | #define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" 112 | #define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" 113 | #define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" 114 | #define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" 115 | #define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" 116 | 117 | #else 118 | // this system has inttypes.h by default 119 | #include 120 | #endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) 121 | 122 | #endif 123 | -------------------------------------------------------------------------------- /3rdparty/Capstone/Capstone.pro: -------------------------------------------------------------------------------- 1 | #------------------------------------------------- 2 | # 3 | # Project created by QtCreator 2019-02-01T10:50:10 4 | # 5 | #------------------------------------------------- 6 | 7 | QT -= core gui 8 | 9 | TARGET = capstone 10 | TEMPLATE = lib 11 | CONFIG += staticlib 12 | 13 | include(../../build.pri) 14 | 15 | win32{ 16 | TARGET = capstone-win-$${QT_ARCH} 17 | } 18 | unix:!macx { 19 | TARGET = capstone-unix-$${QT_ARCH} 20 | } 21 | unix:macx { 22 | TARGET = capstone-macos-$${QT_ARCH} 23 | } 24 | 25 | win32 { 26 | DEFINES += "WIN32" 27 | } 28 | 29 | CONFIG += c++11 30 | 31 | DEFINES += "CAPSTONE_HAS_ARM" 32 | DEFINES += "CAPSTONE_HAS_ARM64" 33 | DEFINES += "CAPSTONE_HAS_BPF" 34 | DEFINES += "CAPSTONE_HAS_EVM" 35 | DEFINES += "CAPSTONE_HAS_M68K" 36 | DEFINES += "CAPSTONE_HAS_M680X" 37 | DEFINES += "CAPSTONE_HAS_MIPS" 38 | DEFINES += "CAPSTONE_HAS_MOS65XX" 39 | DEFINES += "CAPSTONE_HAS_POWERPC" 40 | DEFINES += "CAPSTONE_HAS_RISCV" 41 | DEFINES += "CAPSTONE_HAS_SPARC" 42 | DEFINES += "CAPSTONE_HAS_SYSZ" 43 | DEFINES += "CAPSTONE_HAS_TMS320C64X" 44 | DEFINES += "CAPSTONE_HAS_WASM" 45 | DEFINES += "CAPSTONE_HAS_X86" 46 | DEFINES += "CAPSTONE_HAS_XCORE" 47 | 48 | DEFINES += "CAPSTONE_X86_ATT_DISABLE_NO" 49 | DEFINES += "CAPSTONE_DIET_NO" 50 | DEFINES += "CAPSTONE_X86_REDUCE_NO" 51 | DEFINES += "CAPSTONE_USE_SYS_DYN_MEM" 52 | DEFINES += "_LIB" 53 | 54 | INCLUDEPATH += $$PWD/src/ 55 | DEPENDPATH += $$PWD/src/ 56 | INCLUDEPATH += $$PWD/src/include 57 | DEPENDPATH += $$PWD/src/include 58 | 59 | SOURCES += \ 60 | src/MCInst.c \ 61 | src/MCInstrDesc.c \ 62 | src/MCRegisterInfo.c \ 63 | src/SStream.c \ 64 | src/arch/AArch64/AArch64BaseInfo.c \ 65 | src/arch/AArch64/AArch64Disassembler.c \ 66 | src/arch/AArch64/AArch64InstPrinter.c \ 67 | src/arch/AArch64/AArch64Mapping.c \ 68 | src/arch/AArch64/AArch64Module.c \ 69 | src/arch/ARM/ARMDisassembler.c \ 70 | src/arch/ARM/ARMInstPrinter.c \ 71 | src/arch/ARM/ARMMapping.c \ 72 | src/arch/ARM/ARMModule.c \ 73 | src/arch/BPF/BPFDisassembler.c \ 74 | src/arch/BPF/BPFInstPrinter.c \ 75 | src/arch/BPF/BPFMapping.c \ 76 | src/arch/BPF/BPFModule.c \ 77 | src/arch/EVM/EVMDisassembler.c \ 78 | src/arch/EVM/EVMInstPrinter.c \ 79 | src/arch/EVM/EVMMapping.c \ 80 | src/arch/EVM/EVMModule.c \ 81 | src/arch/M680X/M680XDisassembler.c \ 82 | src/arch/M680X/M680XInstPrinter.c \ 83 | src/arch/M680X/M680XModule.c \ 84 | src/arch/M68K/M68KDisassembler.c \ 85 | src/arch/M68K/M68KInstPrinter.c \ 86 | src/arch/M68K/M68KModule.c \ 87 | src/arch/MOS65XX/MOS65XXDisassembler.c \ 88 | src/arch/MOS65XX/MOS65XXModule.c \ 89 | src/arch/Mips/MipsDisassembler.c \ 90 | src/arch/Mips/MipsInstPrinter.c \ 91 | src/arch/Mips/MipsMapping.c \ 92 | src/arch/Mips/MipsModule.c \ 93 | src/arch/PowerPC/PPCDisassembler.c \ 94 | src/arch/PowerPC/PPCInstPrinter.c \ 95 | src/arch/PowerPC/PPCMapping.c \ 96 | src/arch/PowerPC/PPCModule.c \ 97 | src/arch/RISCV/RISCVDisassembler.c \ 98 | src/arch/RISCV/RISCVInstPrinter.c \ 99 | src/arch/RISCV/RISCVMapping.c \ 100 | src/arch/RISCV/RISCVModule.c \ 101 | src/arch/Sparc/SparcDisassembler.c \ 102 | src/arch/Sparc/SparcInstPrinter.c \ 103 | src/arch/Sparc/SparcMapping.c \ 104 | src/arch/Sparc/SparcModule.c \ 105 | src/arch/SystemZ/SystemZDisassembler.c \ 106 | src/arch/SystemZ/SystemZInstPrinter.c \ 107 | src/arch/SystemZ/SystemZMCTargetDesc.c \ 108 | src/arch/SystemZ/SystemZMapping.c \ 109 | src/arch/SystemZ/SystemZModule.c \ 110 | src/arch/TMS320C64x/TMS320C64xDisassembler.c \ 111 | src/arch/TMS320C64x/TMS320C64xInstPrinter.c \ 112 | src/arch/TMS320C64x/TMS320C64xMapping.c \ 113 | src/arch/TMS320C64x/TMS320C64xModule.c \ 114 | src/arch/WASM/WASMDisassembler.c \ 115 | src/arch/WASM/WASMInstPrinter.c \ 116 | src/arch/WASM/WASMMapping.c \ 117 | src/arch/WASM/WASMModule.c \ 118 | src/arch/X86/X86ATTInstPrinter.c \ 119 | src/arch/X86/X86Disassembler.c \ 120 | src/arch/X86/X86DisassemblerDecoder.c \ 121 | src/arch/X86/X86InstPrinterCommon.c \ 122 | src/arch/X86/X86IntelInstPrinter.c \ 123 | src/arch/X86/X86Mapping.c \ 124 | src/arch/X86/X86Module.c \ 125 | src/arch/XCore/XCoreDisassembler.c \ 126 | src/arch/XCore/XCoreInstPrinter.c \ 127 | src/arch/XCore/XCoreMapping.c \ 128 | src/arch/XCore/XCoreModule.c \ 129 | src/cs.c \ 130 | src/utils.c 131 | 132 | TARGETLIB_PATH = $$PWD 133 | 134 | DESTDIR=$${TARGETLIB_PATH}/libs 135 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/include/capstone/platform.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Axel Souchet & Nguyen Anh Quynh, 2014 */ 3 | 4 | #ifndef CAPSTONE_PLATFORM_H 5 | #define CAPSTONE_PLATFORM_H 6 | 7 | 8 | // handle C99 issue (for pre-2013 VisualStudio) 9 | #if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) 10 | // MSVC 11 | 12 | // stdbool.h 13 | #if (_MSC_VER < 1800) || defined(_KERNEL_MODE) 14 | // this system does not have stdbool.h 15 | #ifndef __cplusplus 16 | typedef unsigned char bool; 17 | #define false 0 18 | #define true 1 19 | #endif // __cplusplus 20 | 21 | #else 22 | // VisualStudio 2013+ -> C99 is supported 23 | #include 24 | #endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE) 25 | 26 | #else 27 | // not MSVC -> C99 is supported 28 | #include 29 | #endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) 30 | 31 | 32 | // handle inttypes.h / stdint.h compatibility 33 | #if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) 34 | #include "windowsce/stdint.h" 35 | #endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) 36 | 37 | #if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) 38 | // this system does not have inttypes.h 39 | 40 | #if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) 41 | // this system does not have stdint.h 42 | typedef signed char int8_t; 43 | typedef signed short int16_t; 44 | typedef signed int int32_t; 45 | typedef unsigned char uint8_t; 46 | typedef unsigned short uint16_t; 47 | typedef unsigned int uint32_t; 48 | typedef signed long long int64_t; 49 | typedef unsigned long long uint64_t; 50 | #endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) 51 | 52 | #if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) 53 | #define INT8_MIN (-127i8 - 1) 54 | #define INT16_MIN (-32767i16 - 1) 55 | #define INT32_MIN (-2147483647i32 - 1) 56 | #define INT64_MIN (-9223372036854775807i64 - 1) 57 | #define INT8_MAX 127i8 58 | #define INT16_MAX 32767i16 59 | #define INT32_MAX 2147483647i32 60 | #define INT64_MAX 9223372036854775807i64 61 | #define UINT8_MAX 0xffui8 62 | #define UINT16_MAX 0xffffui16 63 | #define UINT32_MAX 0xffffffffui32 64 | #define UINT64_MAX 0xffffffffffffffffui64 65 | #endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) 66 | 67 | #ifdef CAPSTONE_HAS_OSXKERNEL 68 | // this system has stdint.h 69 | #include 70 | #endif 71 | 72 | #define __PRI_8_LENGTH_MODIFIER__ "hh" 73 | #define __PRI_64_LENGTH_MODIFIER__ "ll" 74 | 75 | #define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" 76 | #define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" 77 | #define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" 78 | #define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" 79 | #define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" 80 | #define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" 81 | 82 | #define PRId16 "hd" 83 | #define PRIi16 "hi" 84 | #define PRIo16 "ho" 85 | #define PRIu16 "hu" 86 | #define PRIx16 "hx" 87 | #define PRIX16 "hX" 88 | 89 | #if defined(_MSC_VER) && _MSC_VER <= 1700 90 | #define PRId32 "ld" 91 | #define PRIi32 "li" 92 | #define PRIo32 "lo" 93 | #define PRIu32 "lu" 94 | #define PRIx32 "lx" 95 | #define PRIX32 "lX" 96 | #else // OSX 97 | #define PRId32 "d" 98 | #define PRIi32 "i" 99 | #define PRIo32 "o" 100 | #define PRIu32 "u" 101 | #define PRIx32 "x" 102 | #define PRIX32 "X" 103 | #endif // defined(_MSC_VER) && _MSC_VER <= 1700 104 | 105 | #if defined(_MSC_VER) && _MSC_VER <= 1700 106 | // redefine functions from inttypes.h used in cstool 107 | #define strtoull _strtoui64 108 | #endif 109 | 110 | #define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" 111 | #define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" 112 | #define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" 113 | #define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" 114 | #define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" 115 | #define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" 116 | 117 | #else 118 | // this system has inttypes.h by default 119 | #include 120 | #endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) 121 | 122 | #endif 123 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/SStream.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2019 */ 3 | 4 | #include 5 | #if defined(CAPSTONE_HAS_OSXKERNEL) 6 | #include 7 | #include 8 | #include 9 | #else 10 | #include 11 | #include 12 | #endif 13 | #include 14 | 15 | #include 16 | 17 | #include "SStream.h" 18 | #include "cs_priv.h" 19 | #include "utils.h" 20 | 21 | #ifdef _MSC_VER 22 | #pragma warning(disable: 4996) // disable MSVC's warning on strcpy() 23 | #endif 24 | 25 | void SStream_Init(SStream *ss) 26 | { 27 | ss->index = 0; 28 | ss->buffer[0] = '\0'; 29 | } 30 | 31 | void SStream_concat0(SStream *ss, const char *s) 32 | { 33 | #ifndef CAPSTONE_DIET 34 | unsigned int len = (unsigned int) strlen(s); 35 | 36 | memcpy(ss->buffer + ss->index, s, len); 37 | ss->index += len; 38 | ss->buffer[ss->index] = '\0'; 39 | #endif 40 | } 41 | 42 | void SStream_concat1(SStream *ss, const char c) 43 | { 44 | #ifndef CAPSTONE_DIET 45 | ss->buffer[ss->index] = c; 46 | ss->index++; 47 | ss->buffer[ss->index] = '\0'; 48 | #endif 49 | } 50 | 51 | void SStream_concat(SStream *ss, const char *fmt, ...) 52 | { 53 | #ifndef CAPSTONE_DIET 54 | va_list ap; 55 | int ret; 56 | 57 | va_start(ap, fmt); 58 | ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap); 59 | va_end(ap); 60 | ss->index += ret; 61 | #endif 62 | } 63 | 64 | // print number with prefix # 65 | void printInt64Bang(SStream *O, int64_t val) 66 | { 67 | if (val >= 0) { 68 | if (val > HEX_THRESHOLD) 69 | SStream_concat(O, "#0x%"PRIx64, val); 70 | else 71 | SStream_concat(O, "#%"PRIu64, val); 72 | } else { 73 | if (val <- HEX_THRESHOLD) { 74 | if (val == LONG_MIN) 75 | SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val); 76 | else 77 | SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val); 78 | } else 79 | SStream_concat(O, "#-%"PRIu64, -val); 80 | } 81 | } 82 | 83 | void printUInt64Bang(SStream *O, uint64_t val) 84 | { 85 | if (val > HEX_THRESHOLD) 86 | SStream_concat(O, "#0x%"PRIx64, val); 87 | else 88 | SStream_concat(O, "#%"PRIu64, val); 89 | } 90 | 91 | // print number 92 | void printInt64(SStream *O, int64_t val) 93 | { 94 | if (val >= 0) { 95 | if (val > HEX_THRESHOLD) 96 | SStream_concat(O, "0x%"PRIx64, val); 97 | else 98 | SStream_concat(O, "%"PRIu64, val); 99 | } else { 100 | if (val <- HEX_THRESHOLD) { 101 | if (val == LONG_MIN) 102 | SStream_concat(O, "-0x%"PRIx64, (uint64_t)val); 103 | else 104 | SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val); 105 | } else 106 | SStream_concat(O, "-%"PRIu64, -val); 107 | } 108 | } 109 | 110 | void printUInt64(SStream *O, uint64_t val) 111 | { 112 | if (val > HEX_THRESHOLD) 113 | SStream_concat(O, "0x%"PRIx64, val); 114 | else 115 | SStream_concat(O, "%"PRIu64, val); 116 | } 117 | 118 | // print number in decimal mode 119 | void printInt32BangDec(SStream *O, int32_t val) 120 | { 121 | if (val >= 0) 122 | SStream_concat(O, "#%u", val); 123 | else { 124 | if (val == INT_MIN) 125 | SStream_concat(O, "#-%u", val); 126 | else 127 | SStream_concat(O, "#-%u", (uint32_t)-val); 128 | } 129 | } 130 | 131 | void printInt32Bang(SStream *O, int32_t val) 132 | { 133 | if (val >= 0) { 134 | if (val > HEX_THRESHOLD) 135 | SStream_concat(O, "#0x%x", val); 136 | else 137 | SStream_concat(O, "#%u", val); 138 | } else { 139 | if (val <- HEX_THRESHOLD) { 140 | if (val == INT_MIN) 141 | SStream_concat(O, "#-0x%x", (uint32_t)val); 142 | else 143 | SStream_concat(O, "#-0x%x", (uint32_t)-val); 144 | } else 145 | SStream_concat(O, "#-%u", -val); 146 | } 147 | } 148 | 149 | void printInt32(SStream *O, int32_t val) 150 | { 151 | if (val >= 0) { 152 | if (val > HEX_THRESHOLD) 153 | SStream_concat(O, "0x%x", val); 154 | else 155 | SStream_concat(O, "%u", val); 156 | } else { 157 | if (val <- HEX_THRESHOLD) { 158 | if (val == INT_MIN) 159 | SStream_concat(O, "-0x%x", (uint32_t)val); 160 | else 161 | SStream_concat(O, "-0x%x", (uint32_t)-val); 162 | } else 163 | SStream_concat(O, "-%u", -val); 164 | } 165 | } 166 | 167 | void printUInt32Bang(SStream *O, uint32_t val) 168 | { 169 | if (val > HEX_THRESHOLD) 170 | SStream_concat(O, "#0x%x", val); 171 | else 172 | SStream_concat(O, "#%u", val); 173 | } 174 | 175 | void printUInt32(SStream *O, uint32_t val) 176 | { 177 | if (val > HEX_THRESHOLD) 178 | SStream_concat(O, "0x%x", val); 179 | else 180 | SStream_concat(O, "%u", val); 181 | } 182 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/arch/M680X/m6811.inc: -------------------------------------------------------------------------------- 1 | 2 | // Additional instructions only supported on M68HC11 3 | static const inst_pageX g_m6811_inst_overlay_table[] = { 4 | { 0x00, M680X_INS_TEST, inh_hid, inh_hid }, 5 | { 0x02, M680X_INS_IDIV, inh_hid, inh_hid }, 6 | { 0x03, M680X_INS_FDIV, inh_hid, inh_hid }, 7 | { 0x12, M680X_INS_BRSET, dir_hid, imm8rel_hid }, 8 | { 0x13, M680X_INS_BRCLR, dir_hid, imm8rel_hid }, 9 | { 0x14, M680X_INS_BSET, dir_hid, imm8_hid }, 10 | { 0x15, M680X_INS_BCLR, dir_hid, imm8_hid }, 11 | { 0x1c, M680X_INS_BSET, idxX_hid, imm8_hid }, 12 | { 0x1d, M680X_INS_BCLR, idxX_hid, imm8_hid }, 13 | { 0x1e, M680X_INS_BRSET, idxX_hid, imm8rel_hid }, 14 | { 0x1f, M680X_INS_BRCLR, idxX_hid, imm8rel_hid }, 15 | { 0x8f, M680X_INS_XGDX, inh_hid, inh_hid }, 16 | { 0xcf, M680X_INS_STOP, inh_hid, inh_hid }, 17 | }; 18 | 19 | // M68HC11 PAGE2 instructions 20 | static const inst_pageX g_m6811_inst_page2_table[] = { 21 | { 0x08, M680X_INS_INY, inh_hid, inh_hid }, 22 | { 0x09, M680X_INS_DEY, inh_hid, inh_hid }, 23 | { 0x1c, M680X_INS_BSET, idxY_hid, imm8_hid }, 24 | { 0x1d, M680X_INS_BCLR, idxY_hid, imm8_hid }, 25 | { 0x1e, M680X_INS_BRSET, idxY_hid, imm8rel_hid }, 26 | { 0x1f, M680X_INS_BRCLR, idxY_hid, imm8rel_hid }, 27 | { 0x30, M680X_INS_TSY, inh_hid, inh_hid }, 28 | { 0x35, M680X_INS_TYS, inh_hid, inh_hid }, 29 | { 0x38, M680X_INS_PULY, inh_hid, inh_hid }, 30 | { 0x3a, M680X_INS_ABY, inh_hid, inh_hid }, 31 | { 0x3c, M680X_INS_PSHY, inh_hid, inh_hid }, 32 | { 0x60, M680X_INS_NEG, idxY_hid, inh_hid }, 33 | { 0x63, M680X_INS_COM, idxY_hid, inh_hid }, 34 | { 0x64, M680X_INS_LSR, idxY_hid, inh_hid }, 35 | { 0x66, M680X_INS_ROR, idxY_hid, inh_hid }, 36 | { 0x67, M680X_INS_ASR, idxY_hid, inh_hid }, 37 | { 0x68, M680X_INS_ASL, idxY_hid, inh_hid }, 38 | { 0x69, M680X_INS_ROL, idxY_hid, inh_hid }, 39 | { 0x6a, M680X_INS_DEC, idxY_hid, inh_hid }, 40 | { 0x6c, M680X_INS_INC, idxY_hid, inh_hid }, 41 | { 0x6d, M680X_INS_TST, idxY_hid, inh_hid }, 42 | { 0x6e, M680X_INS_JMP, idxY_hid, inh_hid }, 43 | { 0x6f, M680X_INS_CLR, idxY_hid, inh_hid }, 44 | { 0x8c, M680X_INS_CPY, imm16_hid, inh_hid }, 45 | { 0x8f, M680X_INS_XGDY, inh_hid, inh_hid }, 46 | { 0x9c, M680X_INS_CPY, dir_hid, inh_hid }, 47 | { 0xa0, M680X_INS_SUBA, idxY_hid, inh_hid }, 48 | { 0xa1, M680X_INS_CMPA, idxY_hid, inh_hid }, 49 | { 0xa2, M680X_INS_SBCA, idxY_hid, inh_hid }, 50 | { 0xa3, M680X_INS_SUBD, idxY_hid, inh_hid }, 51 | { 0xa4, M680X_INS_ANDA, idxY_hid, inh_hid }, 52 | { 0xa5, M680X_INS_BITA, idxY_hid, inh_hid }, 53 | { 0xa6, M680X_INS_LDAA, idxY_hid, inh_hid }, 54 | { 0xa7, M680X_INS_STAA, idxY_hid, inh_hid }, 55 | { 0xa8, M680X_INS_EORA, idxY_hid, inh_hid }, 56 | { 0xa9, M680X_INS_ADCA, idxY_hid, inh_hid }, 57 | { 0xaa, M680X_INS_ORAA, idxY_hid, inh_hid }, 58 | { 0xab, M680X_INS_ADDA, idxY_hid, inh_hid }, 59 | { 0xac, M680X_INS_CPY, idxY_hid, inh_hid }, 60 | { 0xad, M680X_INS_JSR, idxY_hid, inh_hid }, 61 | { 0xae, M680X_INS_LDS, idxY_hid, inh_hid }, 62 | { 0xaf, M680X_INS_STS, idxY_hid, inh_hid }, 63 | { 0xbc, M680X_INS_CPY, ext_hid, inh_hid }, 64 | { 0xce, M680X_INS_LDY, imm16_hid, inh_hid }, 65 | { 0xde, M680X_INS_LDY, dir_hid, inh_hid }, 66 | { 0xdf, M680X_INS_STY, dir_hid, inh_hid }, 67 | { 0xe0, M680X_INS_SUBB, idxY_hid, inh_hid }, 68 | { 0xe1, M680X_INS_CMPB, idxY_hid, inh_hid }, 69 | { 0xe2, M680X_INS_SBCB, idxY_hid, inh_hid }, 70 | { 0xe3, M680X_INS_ADDD, idxY_hid, inh_hid }, 71 | { 0xe4, M680X_INS_ANDB, idxY_hid, inh_hid }, 72 | { 0xe5, M680X_INS_BITB, idxY_hid, inh_hid }, 73 | { 0xe6, M680X_INS_LDAB, idxY_hid, inh_hid }, 74 | { 0xe7, M680X_INS_STAB, idxY_hid, inh_hid }, 75 | { 0xe8, M680X_INS_EORB, idxY_hid, inh_hid }, 76 | { 0xe9, M680X_INS_ADCB, idxY_hid, inh_hid }, 77 | { 0xea, M680X_INS_ORAB, idxY_hid, inh_hid }, 78 | { 0xeb, M680X_INS_ADDB, idxY_hid, inh_hid }, 79 | { 0xec, M680X_INS_LDD, idxY_hid, inh_hid }, 80 | { 0xed, M680X_INS_STD, idxY_hid, inh_hid }, 81 | { 0xee, M680X_INS_LDY, idxY_hid, inh_hid }, 82 | { 0xef, M680X_INS_STY, idxY_hid, inh_hid }, 83 | { 0xfe, M680X_INS_LDY, ext_hid, inh_hid }, 84 | { 0xff, M680X_INS_STY, ext_hid, inh_hid }, 85 | }; 86 | 87 | // M68HC11 PAGE3 instructions 88 | static const inst_pageX g_m6811_inst_page3_table[] = { 89 | { 0x83, M680X_INS_CPD, imm16_hid, inh_hid }, 90 | { 0x93, M680X_INS_CPD, dir_hid, inh_hid }, 91 | { 0xa3, M680X_INS_CPD, idxX_hid, inh_hid }, 92 | { 0xac, M680X_INS_CPY, idxX_hid, inh_hid }, 93 | { 0xb3, M680X_INS_CPD, ext_hid, inh_hid }, 94 | { 0xee, M680X_INS_LDY, idxX_hid, inh_hid }, 95 | { 0xef, M680X_INS_STY, idxX_hid, inh_hid }, 96 | }; 97 | 98 | // M68HC11 PAGE4 instructions 99 | static const inst_pageX g_m6811_inst_page4_table[] = { 100 | { 0xa3, M680X_INS_CPD, idxY_hid, inh_hid }, 101 | { 0xac, M680X_INS_CPX, idxY_hid, inh_hid }, 102 | { 0xee, M680X_INS_LDX, idxY_hid, inh_hid }, 103 | { 0xef, M680X_INS_STX, idxY_hid, inh_hid }, 104 | }; 105 | 106 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/capstone/bpf.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CAPSTONE_BPF_H 5 | #define CAPSTONE_BPF_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include "platform.h" 12 | 13 | #ifdef _MSC_VER 14 | #pragma warning(disable:4201) 15 | #endif 16 | 17 | /// Operand type for instruction's operands 18 | typedef enum bpf_op_type { 19 | BPF_OP_INVALID = 0, 20 | 21 | BPF_OP_REG, 22 | BPF_OP_IMM, 23 | BPF_OP_OFF, 24 | BPF_OP_MEM, 25 | BPF_OP_MMEM, ///< M[k] in cBPF 26 | BPF_OP_MSH, ///< corresponds to cBPF's BPF_MSH mode 27 | BPF_OP_EXT, ///< cBPF's extension (not eBPF) 28 | } bpf_op_type; 29 | 30 | /// BPF registers 31 | typedef enum bpf_reg { 32 | BPF_REG_INVALID = 0, 33 | 34 | ///< cBPF 35 | BPF_REG_A, 36 | BPF_REG_X, 37 | 38 | ///< eBPF 39 | BPF_REG_R0, 40 | BPF_REG_R1, 41 | BPF_REG_R2, 42 | BPF_REG_R3, 43 | BPF_REG_R4, 44 | BPF_REG_R5, 45 | BPF_REG_R6, 46 | BPF_REG_R7, 47 | BPF_REG_R8, 48 | BPF_REG_R9, 49 | BPF_REG_R10, 50 | 51 | BPF_REG_ENDING, 52 | } bpf_reg; 53 | 54 | /// Instruction's operand referring to memory 55 | /// This is associated with BPF_OP_MEM operand type above 56 | typedef struct bpf_op_mem { 57 | bpf_reg base; ///< base register 58 | uint32_t disp; ///< offset value 59 | } bpf_op_mem; 60 | 61 | typedef enum bpf_ext_type { 62 | BPF_EXT_INVALID = 0, 63 | 64 | BPF_EXT_LEN, 65 | } bpf_ext_type; 66 | 67 | /// Instruction operand 68 | typedef struct cs_bpf_op { 69 | bpf_op_type type; 70 | union { 71 | uint8_t reg; ///< register value for REG operand 72 | uint64_t imm; ///< immediate value IMM operand 73 | uint32_t off; ///< offset value, used in jump & call 74 | bpf_op_mem mem; ///< base/disp value for MEM operand 75 | /* cBPF only */ 76 | uint32_t mmem; ///< M[k] in cBPF 77 | uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode 78 | uint32_t ext; ///< cBPF's extension (not eBPF) 79 | }; 80 | 81 | /// How is this operand accessed? (READ, WRITE or READ|WRITE) 82 | /// This field is combined of cs_ac_type. 83 | /// NOTE: this field is irrelevant if engine is compiled in DIET mode. 84 | uint8_t access; 85 | } cs_bpf_op; 86 | 87 | /// Instruction structure 88 | typedef struct cs_bpf { 89 | uint8_t op_count; 90 | cs_bpf_op operands[4]; 91 | } cs_bpf; 92 | 93 | /// BPF instruction 94 | typedef enum bpf_insn { 95 | BPF_INS_INVALID = 0, 96 | 97 | ///< ALU 98 | BPF_INS_ADD, 99 | BPF_INS_SUB, 100 | BPF_INS_MUL, 101 | BPF_INS_DIV, 102 | BPF_INS_OR, 103 | BPF_INS_AND, 104 | BPF_INS_LSH, 105 | BPF_INS_RSH, 106 | BPF_INS_NEG, 107 | BPF_INS_MOD, 108 | BPF_INS_XOR, 109 | BPF_INS_MOV, ///< eBPF only 110 | BPF_INS_ARSH, ///< eBPF only 111 | 112 | ///< ALU64, eBPF only 113 | BPF_INS_ADD64, 114 | BPF_INS_SUB64, 115 | BPF_INS_MUL64, 116 | BPF_INS_DIV64, 117 | BPF_INS_OR64, 118 | BPF_INS_AND64, 119 | BPF_INS_LSH64, 120 | BPF_INS_RSH64, 121 | BPF_INS_NEG64, 122 | BPF_INS_MOD64, 123 | BPF_INS_XOR64, 124 | BPF_INS_MOV64, 125 | BPF_INS_ARSH64, 126 | 127 | ///< Byteswap, eBPF only 128 | BPF_INS_LE16, 129 | BPF_INS_LE32, 130 | BPF_INS_LE64, 131 | BPF_INS_BE16, 132 | BPF_INS_BE32, 133 | BPF_INS_BE64, 134 | 135 | ///< Load 136 | BPF_INS_LDW, ///< eBPF only 137 | BPF_INS_LDH, 138 | BPF_INS_LDB, 139 | BPF_INS_LDDW, ///< eBPF only: load 64-bit imm 140 | BPF_INS_LDXW, ///< eBPF only 141 | BPF_INS_LDXH, ///< eBPF only 142 | BPF_INS_LDXB, ///< eBPF only 143 | BPF_INS_LDXDW, ///< eBPF only 144 | 145 | ///< Store 146 | BPF_INS_STW, ///< eBPF only 147 | BPF_INS_STH, ///< eBPF only 148 | BPF_INS_STB, ///< eBPF only 149 | BPF_INS_STDW, ///< eBPF only 150 | BPF_INS_STXW, ///< eBPF only 151 | BPF_INS_STXH, ///< eBPF only 152 | BPF_INS_STXB, ///< eBPF only 153 | BPF_INS_STXDW, ///< eBPF only 154 | BPF_INS_XADDW, ///< eBPF only 155 | BPF_INS_XADDDW, ///< eBPF only 156 | 157 | ///< Jump 158 | BPF_INS_JMP, 159 | BPF_INS_JEQ, 160 | BPF_INS_JGT, 161 | BPF_INS_JGE, 162 | BPF_INS_JSET, 163 | BPF_INS_JNE, ///< eBPF only 164 | BPF_INS_JSGT, ///< eBPF only 165 | BPF_INS_JSGE, ///< eBPF only 166 | BPF_INS_CALL, ///< eBPF only 167 | BPF_INS_EXIT, ///< eBPF only 168 | BPF_INS_JLT, ///< eBPF only 169 | BPF_INS_JLE, ///< eBPF only 170 | BPF_INS_JSLT, ///< eBPF only 171 | BPF_INS_JSLE, ///< eBPF only 172 | 173 | ///< Return, cBPF only 174 | BPF_INS_RET, 175 | 176 | ///< Misc, cBPF only 177 | BPF_INS_TAX, 178 | BPF_INS_TXA, 179 | 180 | BPF_INS_ENDING, 181 | 182 | // alias instructions 183 | BPF_INS_LD = BPF_INS_LDW, ///< cBPF only 184 | BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only 185 | BPF_INS_ST = BPF_INS_STW, ///< cBPF only 186 | BPF_INS_STX = BPF_INS_STXW, ///< cBPF only 187 | } bpf_insn; 188 | 189 | /// Group of BPF instructions 190 | typedef enum bpf_insn_group { 191 | BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID 192 | 193 | BPF_GRP_LOAD, 194 | BPF_GRP_STORE, 195 | BPF_GRP_ALU, 196 | BPF_GRP_JUMP, 197 | BPF_GRP_CALL, ///< eBPF only 198 | BPF_GRP_RETURN, 199 | BPF_GRP_MISC, ///< cBPF only 200 | 201 | BPF_GRP_ENDING, 202 | } bpf_insn_group; 203 | 204 | #ifdef __cplusplus 205 | } 206 | #endif 207 | 208 | #endif 209 | -------------------------------------------------------------------------------- /3rdparty/Capstone/src/include/capstone/bpf.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* BPF Backend by david942j , 2019 */ 3 | 4 | #ifndef CAPSTONE_BPF_H 5 | #define CAPSTONE_BPF_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include "platform.h" 12 | 13 | #ifdef _MSC_VER 14 | #pragma warning(disable:4201) 15 | #endif 16 | 17 | /// Operand type for instruction's operands 18 | typedef enum bpf_op_type { 19 | BPF_OP_INVALID = 0, 20 | 21 | BPF_OP_REG, 22 | BPF_OP_IMM, 23 | BPF_OP_OFF, 24 | BPF_OP_MEM, 25 | BPF_OP_MMEM, ///< M[k] in cBPF 26 | BPF_OP_MSH, ///< corresponds to cBPF's BPF_MSH mode 27 | BPF_OP_EXT, ///< cBPF's extension (not eBPF) 28 | } bpf_op_type; 29 | 30 | /// BPF registers 31 | typedef enum bpf_reg { 32 | BPF_REG_INVALID = 0, 33 | 34 | ///< cBPF 35 | BPF_REG_A, 36 | BPF_REG_X, 37 | 38 | ///< eBPF 39 | BPF_REG_R0, 40 | BPF_REG_R1, 41 | BPF_REG_R2, 42 | BPF_REG_R3, 43 | BPF_REG_R4, 44 | BPF_REG_R5, 45 | BPF_REG_R6, 46 | BPF_REG_R7, 47 | BPF_REG_R8, 48 | BPF_REG_R9, 49 | BPF_REG_R10, 50 | 51 | BPF_REG_ENDING, 52 | } bpf_reg; 53 | 54 | /// Instruction's operand referring to memory 55 | /// This is associated with BPF_OP_MEM operand type above 56 | typedef struct bpf_op_mem { 57 | bpf_reg base; ///< base register 58 | uint32_t disp; ///< offset value 59 | } bpf_op_mem; 60 | 61 | typedef enum bpf_ext_type { 62 | BPF_EXT_INVALID = 0, 63 | 64 | BPF_EXT_LEN, 65 | } bpf_ext_type; 66 | 67 | /// Instruction operand 68 | typedef struct cs_bpf_op { 69 | bpf_op_type type; 70 | union { 71 | uint8_t reg; ///< register value for REG operand 72 | uint64_t imm; ///< immediate value IMM operand 73 | uint32_t off; ///< offset value, used in jump & call 74 | bpf_op_mem mem; ///< base/disp value for MEM operand 75 | /* cBPF only */ 76 | uint32_t mmem; ///< M[k] in cBPF 77 | uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode 78 | uint32_t ext; ///< cBPF's extension (not eBPF) 79 | }; 80 | 81 | /// How is this operand accessed? (READ, WRITE or READ|WRITE) 82 | /// This field is combined of cs_ac_type. 83 | /// NOTE: this field is irrelevant if engine is compiled in DIET mode. 84 | uint8_t access; 85 | } cs_bpf_op; 86 | 87 | /// Instruction structure 88 | typedef struct cs_bpf { 89 | uint8_t op_count; 90 | cs_bpf_op operands[4]; 91 | } cs_bpf; 92 | 93 | /// BPF instruction 94 | typedef enum bpf_insn { 95 | BPF_INS_INVALID = 0, 96 | 97 | ///< ALU 98 | BPF_INS_ADD, 99 | BPF_INS_SUB, 100 | BPF_INS_MUL, 101 | BPF_INS_DIV, 102 | BPF_INS_OR, 103 | BPF_INS_AND, 104 | BPF_INS_LSH, 105 | BPF_INS_RSH, 106 | BPF_INS_NEG, 107 | BPF_INS_MOD, 108 | BPF_INS_XOR, 109 | BPF_INS_MOV, ///< eBPF only 110 | BPF_INS_ARSH, ///< eBPF only 111 | 112 | ///< ALU64, eBPF only 113 | BPF_INS_ADD64, 114 | BPF_INS_SUB64, 115 | BPF_INS_MUL64, 116 | BPF_INS_DIV64, 117 | BPF_INS_OR64, 118 | BPF_INS_AND64, 119 | BPF_INS_LSH64, 120 | BPF_INS_RSH64, 121 | BPF_INS_NEG64, 122 | BPF_INS_MOD64, 123 | BPF_INS_XOR64, 124 | BPF_INS_MOV64, 125 | BPF_INS_ARSH64, 126 | 127 | ///< Byteswap, eBPF only 128 | BPF_INS_LE16, 129 | BPF_INS_LE32, 130 | BPF_INS_LE64, 131 | BPF_INS_BE16, 132 | BPF_INS_BE32, 133 | BPF_INS_BE64, 134 | 135 | ///< Load 136 | BPF_INS_LDW, ///< eBPF only 137 | BPF_INS_LDH, 138 | BPF_INS_LDB, 139 | BPF_INS_LDDW, ///< eBPF only: load 64-bit imm 140 | BPF_INS_LDXW, ///< eBPF only 141 | BPF_INS_LDXH, ///< eBPF only 142 | BPF_INS_LDXB, ///< eBPF only 143 | BPF_INS_LDXDW, ///< eBPF only 144 | 145 | ///< Store 146 | BPF_INS_STW, ///< eBPF only 147 | BPF_INS_STH, ///< eBPF only 148 | BPF_INS_STB, ///< eBPF only 149 | BPF_INS_STDW, ///< eBPF only 150 | BPF_INS_STXW, ///< eBPF only 151 | BPF_INS_STXH, ///< eBPF only 152 | BPF_INS_STXB, ///< eBPF only 153 | BPF_INS_STXDW, ///< eBPF only 154 | BPF_INS_XADDW, ///< eBPF only 155 | BPF_INS_XADDDW, ///< eBPF only 156 | 157 | ///< Jump 158 | BPF_INS_JMP, 159 | BPF_INS_JEQ, 160 | BPF_INS_JGT, 161 | BPF_INS_JGE, 162 | BPF_INS_JSET, 163 | BPF_INS_JNE, ///< eBPF only 164 | BPF_INS_JSGT, ///< eBPF only 165 | BPF_INS_JSGE, ///< eBPF only 166 | BPF_INS_CALL, ///< eBPF only 167 | BPF_INS_EXIT, ///< eBPF only 168 | BPF_INS_JLT, ///< eBPF only 169 | BPF_INS_JLE, ///< eBPF only 170 | BPF_INS_JSLT, ///< eBPF only 171 | BPF_INS_JSLE, ///< eBPF only 172 | 173 | ///< Return, cBPF only 174 | BPF_INS_RET, 175 | 176 | ///< Misc, cBPF only 177 | BPF_INS_TAX, 178 | BPF_INS_TXA, 179 | 180 | BPF_INS_ENDING, 181 | 182 | // alias instructions 183 | BPF_INS_LD = BPF_INS_LDW, ///< cBPF only 184 | BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only 185 | BPF_INS_ST = BPF_INS_STW, ///< cBPF only 186 | BPF_INS_STX = BPF_INS_STXW, ///< cBPF only 187 | } bpf_insn; 188 | 189 | /// Group of BPF instructions 190 | typedef enum bpf_insn_group { 191 | BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID 192 | 193 | BPF_GRP_LOAD, 194 | BPF_GRP_STORE, 195 | BPF_GRP_ALU, 196 | BPF_GRP_JUMP, 197 | BPF_GRP_CALL, ///< eBPF only 198 | BPF_GRP_RETURN, 199 | BPF_GRP_MISC, ///< cBPF only 200 | 201 | BPF_GRP_ENDING, 202 | } bpf_insn_group; 203 | 204 | #ifdef __cplusplus 205 | } 206 | #endif 207 | 208 | #endif 209 | --------------------------------------------------------------------------------