├── B_Router_Mesh5x5.v ├── B_Router_Mesh5x5_tb.v ├── Base_Router.v ├── Collector_000_000.v ├── Collector_000_001.v ├── Collector_000_010.v ├── Collector_000_011.v ├── Collector_000_100.v ├── Collector_001_000.v ├── Collector_001_001.v ├── Collector_001_010.v ├── Collector_001_011.v ├── Collector_001_100.v ├── Collector_010_000.v ├── Collector_010_001.v ├── Collector_010_010.v ├── Collector_010_011.v ├── Collector_010_100.v ├── Collector_011_000.v ├── Collector_011_001.v ├── Collector_011_010.v ├── Collector_011_011.v ├── Collector_011_100.v ├── Collector_100_000.v ├── Collector_100_001.v ├── Collector_100_010.v ├── Collector_100_011.v ├── Collector_100_100.v ├── FIFO.v ├── Injector_000_000.v ├── Injector_000_001.v ├── Injector_000_010.v ├── Injector_000_011.v ├── Injector_000_100.v ├── Injector_001_000.v ├── Injector_001_001.v ├── Injector_001_010.v ├── Injector_001_011.v ├── Injector_001_100.v ├── Injector_010_000.v ├── Injector_010_001.v ├── Injector_010_010.v ├── Injector_010_011.v ├── Injector_010_100.v ├── Injector_011_000.v ├── Injector_011_001.v ├── Injector_011_010.v ├── Injector_011_011.v ├── Injector_011_100.v ├── Injector_100_000.v ├── Injector_100_001.v ├── Injector_100_010.v ├── Injector_100_011.v ├── Injector_100_100.v ├── InputPort.v ├── InputPortController.v ├── LICENSE ├── OutputController.v ├── README.md ├── RR_arbiter.v ├── mux.v └── ram.v /B_Router_Mesh5x5_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 23:35:59 07/13/2013 8 | // Design Name: F_Router_Mesh5x5 9 | // Module Name: D:/Master2012-2013/NoC_Codes/RouterDesign2013/F_Router_Mesh5x5/F_Router_Mesh5x5_tb.v 10 | // Project Name: F_Router_Mesh5x5 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: F_Router_Mesh5x5 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module B_Router_Mesh5x5_tb; 26 | 27 | // Inputs 28 | reg clk; 29 | reg reset; 30 | 31 | // Instantiate the Unit Under Test (UUT) 32 | B_Router_Mesh5x5 uut ( 33 | .clk(clk), 34 | .reset(reset) 35 | ); 36 | 37 | // Clock generator 38 | always 39 | #5 clk = ~clk; 40 | 41 | initial 42 | begin 43 | // Initialize Inputs 44 | clk = 0; 45 | reset = 0; 46 | repeat(3) @(posedge clk); 47 | reset = 1; 48 | repeat(250000) @(posedge clk); 49 | $finish; // to shut down the simulation 50 | end 51 | 52 | 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /Collector_000_000.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_000_000 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID =6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_0; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_0 = $fopen("Collector_Log_0.txt","w"); 54 | //$fdisplay(Collector_Log_0, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_0, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_000_001.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_000_001 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_5; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_5 = $fopen("Collector_Log_5.txt","w"); 54 | //$fdisplay(Collector_Log_5, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_5, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_000_010.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_000_010 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_10; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_10 = $fopen("Collector_Log_10.txt","w"); 54 | //$fdisplay(Collector_Log_10, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_10, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_000_011.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_000_011 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_15; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_15 = $fopen("Collector_Log_15.txt","w"); 54 | //$fdisplay(Collector_Log_15, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_15, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_000_100.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_000_100 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 29 | // --------------------------- Wire Declarations ----------------------------- // 30 | wire clk; 31 | wire reset; 32 | wire ReqUpStr; // request from Local Port to Collector 33 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 34 | // ------------------------ Registers Declarations --------------------------- // 35 | reg UpStrFull;// Always Not full it is the destination 36 | reg GntUpStr; 37 | // data buffer register to accept the packet and Indicate its Information 38 | reg [dataWidth-1:0] dataBuf; 39 | //Packet Contents 40 | reg [9:0] PacketID; 41 | reg [31:0] CYCLE_COUNTER; //Timestamp 42 | reg STATE_Collector; //reg [1:0] STATE_Collector; 43 | reg [((dim-1)*2)-1:0] SenderID; 44 | //reg [5:0] SenderID; 45 | //for Simulation log 46 | integer Collector_Log_20; 47 | initial 48 | begin 49 | dataBuf <= 0; PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 50 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 51 | //for Simulation log 52 | Collector_Log_20 = $fopen("Collector_Log_20.txt","w"); 53 | //$fdisplay(Collector_Log_20, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 54 | end 55 | 56 | always @(posedge clk) 57 | begin 58 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 59 | end 60 | //########################### Modules(PEs) Collector ################################### 61 | always @(posedge clk or negedge reset) 62 | begin 63 | if( !reset)// reset all registers 64 | begin 65 | dataBuf <= 0; PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 66 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 67 | end 68 | else //if (ReqUpStr ) 69 | begin 70 | UpStrFull <=0; //send UpStrFull to Local Port 71 | case(STATE_Collector) 72 | WAIT_REQ: 73 | begin 74 | if(ReqUpStr) 75 | begin 76 | STATE_Collector <= RECEIVE_DATA; 77 | GntUpStr <=1; 78 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 79 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 80 | end 81 | end//WAIT_REQ 82 | RECEIVE_DATA: 83 | begin 84 | GntUpStr <=0; 85 | STATE_Collector <= WAIT_REQ; 86 | $fdisplay(Collector_Log_20, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 87 | end // RECEIVE_DATA 88 | endcase 89 | end // else 90 | end // always 91 | endmodule 92 | -------------------------------------------------------------------------------- /Collector_001_000.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_001_000 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_1; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_1 = $fopen("Collector_Log_1.txt","w"); 54 | //$fdisplay(Collector_Log_1, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_1, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_001_001.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_001_001 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_6; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_6 = $fopen("Collector_Log_6.txt","w"); 54 | //$fdisplay(Collector_Log_6, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_6, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_001_010.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_001_010 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_11; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_11 = $fopen("Collector_Log_11.txt","w"); 54 | //$fdisplay(Collector_Log_11, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_11, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_001_011.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_001_011 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_16; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_16 = $fopen("Collector_Log_16.txt","w"); 54 | //$fdisplay(Collector_Log_16, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_16, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_001_100.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_001_100 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_21; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_21 = $fopen("Collector_Log_21.txt","w"); 54 | //$fdisplay(Collector_Log_21, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_21, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_010_000.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_010_000 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_2; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_2 = $fopen("Collector_Log_2.txt","w"); 54 | //$fdisplay(Collector_Log_2, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_2, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_010_001.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_010_001 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_7; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_7 = $fopen("Collector_Log_7.txt","w"); 54 | //$fdisplay(Collector_Log_7, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_7, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_010_010.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_010_010 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_12; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_12 = $fopen("Collector_Log_12.txt","w"); 54 | //$fdisplay(Collector_Log_12, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_12, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_010_011.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_010_011 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_17; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_17 = $fopen("Collector_Log_17.txt","w"); 54 | //$fdisplay(Collector_Log_17, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_17, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_010_100.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_010_100 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_22; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_22 = $fopen("Collector_Log_22.txt","w"); 54 | //$fdisplay(Collector_Log_22, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_22, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_011_000.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_011_000 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_3; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_3 = $fopen("Collector_Log_3.txt","w"); 54 | //$fdisplay(Collector_Log_3, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_3, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_011_001.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_011_001 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_8; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_8 = $fopen("Collector_Log_8.txt","w"); 54 | //$fdisplay(Collector_Log_8, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_8, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_011_010.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_011_010 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_13; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_13 = $fopen("Collector_Log_13.txt","w"); 54 | //$fdisplay(Collector_Log_13, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_13, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_011_011.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_011_011 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_18; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_18 = $fopen("Collector_Log_18.txt","w"); 54 | //$fdisplay(Collector_Log_18, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_18, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_011_100.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_011_100 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_23; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_23 = $fopen("Collector_Log_23.txt","w"); 54 | //$fdisplay(Collector_Log_23, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_23, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_100_000.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_100_000 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_4; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_4 = $fopen("Collector_Log_4.txt","w"); 54 | //$fdisplay(Collector_Log_4, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_4, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_100_001.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_100_001 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_9; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_9 = $fopen("Collector_Log_9.txt","w"); 54 | //$fdisplay(Collector_Log_9, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_9, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_100_010.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_100_010 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_14; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_14 = $fopen("Collector_Log_14.txt","w"); 54 | //$fdisplay(Collector_Log_14, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_14, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_100_011.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_100_011 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_19; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_19 = $fopen("Collector_Log_19.txt","w"); 54 | //$fdisplay(Collector_Log_19, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_19, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /Collector_100_100.v: -------------------------------------------------------------------------------- 1 | 2 | module Collector_100_100 3 | ( 4 | // Global Settings 5 | clk, 6 | reset, 7 | // -- Input Port Traffic: -- Collector 8 | PacketIn, //connect to localpacketOut, 9 | UpStrFull, // connect to localDnStrFull, // it will be 0 where the task is to always collect packets 10 | ReqUpStr, // connect to localReqDnStr, 11 | GntUpStr 12 | ); 13 | // ------------------------ Parameter Declarations --------------------------- // 14 | //for 4x4 mesh 15 | parameter routerID = 6'b000_000; 16 | parameter ModuleID = 6'b000_000; 17 | parameter dataWidth = 32;// number of bits for data bus 18 | parameter dim = 4;// dimension of x,y fields in source and destination 19 | parameter WAIT_REQ=1'b0, 20 | RECEIVE_DATA=1'b1; 21 | // ------------------------ Inputs Declarations ------------------------------ // 22 | input clk; 23 | input reset; 24 | input ReqUpStr;// routers' Local Port send request to collector to receive packets -- always receive 25 | // ------------------------ Outputs Declarations ----------------------------- // 26 | output UpStrFull; // Collector send Full to router -- Always Not full it is the destination 27 | output GntUpStr; 28 | 29 | input [dataWidth-1:0] PacketIn;// output data packet form Local Port to Collector 30 | // --------------------------- Wire Declarations ----------------------------- // 31 | wire clk; 32 | wire reset; 33 | wire ReqUpStr; // request from Local Port to Collector 34 | wire [dataWidth-1:0] PacketIn;// Input data packet form Local Port 35 | // ------------------------ Registers Declarations --------------------------- // 36 | reg UpStrFull;// Always Not full it is the destination 37 | reg GntUpStr; 38 | // data buffer register to accept the packet and Indicate its Information 39 | reg [dataWidth-1:0] dataBuf; 40 | //Packet Contents 41 | reg [9:0] PacketID; 42 | reg [31:0] CYCLE_COUNTER; //Timestamp 43 | reg STATE_Collector; //reg [1:0] STATE_Collector; 44 | reg [((dim-1)*2)-1:0] SenderID; 45 | //reg [5:0] SenderID; 46 | //for Simulation log 47 | integer Collector_Log_24; 48 | initial 49 | begin 50 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 51 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 52 | //for Simulation log 53 | Collector_Log_24 = $fopen("Collector_Log_24.txt","w"); 54 | //$fdisplay(Collector_Log_24, " SimulationTime ; ReceiveTime ; SenderID ; ReceiverID ; PacketID "); 55 | end 56 | 57 | always @(posedge clk) 58 | begin 59 | CYCLE_COUNTER = CYCLE_COUNTER + 1'b1; 60 | end 61 | //########################### Modules(PEs) Collector ################################### 62 | always @(posedge clk or negedge reset) 63 | begin 64 | if( !reset)// reset all registers 65 | begin 66 | PacketID <= 0; UpStrFull <= 0; GntUpStr <=0; 67 | CYCLE_COUNTER <= 0; SenderID <= 0; STATE_Collector <= WAIT_REQ; 68 | end 69 | else //if (ReqUpStr ) 70 | begin 71 | UpStrFull <=0; //send UpStrFull to Local Port 72 | case(STATE_Collector) 73 | WAIT_REQ: 74 | begin 75 | if(ReqUpStr) 76 | begin 77 | STATE_Collector <= RECEIVE_DATA; 78 | GntUpStr <=1; 79 | PacketID <= PacketIn[((dim*4)-1) : ((dim*4)-1)-9]; 80 | SenderID <= PacketIn[((dim*4)-1)-10 : 0]; 81 | end 82 | end//WAIT_REQ 83 | RECEIVE_DATA: 84 | begin 85 | GntUpStr <=0; 86 | STATE_Collector <= WAIT_REQ; 87 | $fdisplay(Collector_Log_24, $time, " ; %d; %d ; %d ; %d ", CYCLE_COUNTER,SenderID, ModuleID,PacketID); 88 | end // RECEIVE_DATA 89 | endcase 90 | end // else 91 | end // always 92 | endmodule 93 | -------------------------------------------------------------------------------- /FIFO.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:11:49 12/25/2012 7 | // Design Name: 8 | // Module Name: FIFO_M 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module FIFO ( clk, reset, reqUpStr , gntUpStr , full, PacketIn, 22 | reqInCtr , gntInCtr , empty, PacketOut ); 23 | // --------------------------------------------------------------------------- // 24 | // ------------------------ Parameter Declarations --------------------------- // 25 | parameter dataWidth = 32; // number of bits for data bus 26 | parameter addressWidth = 4;// number of bits for address bus 27 | parameter fifoDepth = ( ( 1 << addressWidth ) - 1 ); // number of entries in fifo buffer 28 | parameter dim = 2;// dimension of x,y fields in source and destination 29 | // ------------------------ Inputs Declarations ------------------------------ // 30 | input clk; 31 | input reset; 32 | input reqUpStr;// Up stream router request 33 | input reqInCtr;// Input controller request 34 | input [dataWidth-1:0] PacketIn;// input data Packet to fifo 35 | // ------------------------ Outputs Declarations ----------------------------- // 36 | output gntUpStr;// Up stream router grant 37 | output gntInCtr;// Input controller grant 38 | output full;// indicator for FIFO buffer .. if full = 1 else = 0 39 | output empty;// indicator for FIFO buffer .. if empty = 1 else = 0 40 | output [dataWidth-1:0] PacketOut;// output data Packet form fifo 41 | // --------------------------- Wire Declarations ----------------------------- // 42 | wire clk; 43 | wire reset; 44 | wire reqUpStr;// Up stream router request 45 | reg gntUpStr;// Up stream router grant 46 | wire reqInCtr;// Input controller request 47 | wire [dataWidth-1:0] PacketIn;// input data Packet to fifo 48 | reg [dataWidth-1:0] PacketOut;// output data Packet form fifo 49 | wire full;// indicator for FIFO buffer .. if full = 1 else = 0 50 | wire empty;// indicator for FIFO buffer .. if empty = 1 else = 0 51 | //reg writeEnable;// write enable to ram buffer 52 | //reg readEnable;// read enable to ram buffer 53 | //wire [addressWidth-1:0] compAddr;// variable used to compare address 54 | //wire [addressWidth:0] compAddr;// i add extra bit due to addition 55 | // ------------------------ Registers Declarations --------------------------- // 56 | reg gntInCtr;// Input controller grant 57 | wire [addressWidth-1:0] writeAddr;// write address to ram buffer 58 | wire [addressWidth-1:0] readAddr;// read address from ram buffer 59 | reg [addressWidth:0] write_ptr;// write pointer to get Full and Empty flags 60 | reg [addressWidth:0] read_ptr;// write pointer to get Full and Empty flags 61 | reg EnableGnt; 62 | reg [dataWidth-1:0] ram[2**addressWidth-1:0]; 63 | //============================================================================= 64 | // Extracting read and write address from corrosponding pointers 65 | assign readAddr = read_ptr [addressWidth-1:0]; 66 | assign writeAddr = write_ptr [addressWidth-1:0]; 67 | assign read_buf = reqInCtr && !empty;// read signal ... 68 | assign write_buf = reqUpStr && !full && EnableGnt ;// write signal ... 69 | // Generating fifo full status 70 | // FIFO full is asserted when both pointers point to same address but their 71 | // MSBs are different 72 | assign full = ( (writeAddr == readAddr) && 73 | (write_ptr[addressWidth] ^ read_ptr[addressWidth]) ); 74 | //FIFO is empty when read pointer is same as write pointer 75 | assign empty = ( read_ptr == write_ptr ); // MSBs are idintical 76 | 77 | 78 | 79 | always @(posedge clk or negedge reset) 80 | begin 81 | if( !reset)//reset all registers 82 | begin 83 | gntInCtr <= 0; gntUpStr <= 0; EnableGnt <= 1; //DataBuffer = 0; 84 | write_ptr <= {(addressWidth+1){1'b0}}; //readEnable <= 0; writeEnable <= 0; 85 | read_ptr <= {(addressWidth+1){1'b0}}; 86 | end 87 | else 88 | begin 89 | // handle request from up stream router 90 | if ( !reqUpStr) 91 | EnableGnt <= 1; 92 | // ---------------------------- write process ------------------------- // 93 | if (write_buf)// Buffer not Full 94 | begin 95 | gntUpStr <= 1; EnableGnt <= 0; //writeEnable <= 1; 96 | //write_ptr <= write_ptr + {{addressWidth{1'b0}},1'b1}; 97 | write_ptr <= write_ptr + 1'b1; 98 | //writeAddr <= writeAddr + 1'b1; 99 | ram[writeAddr] <= PacketIn; 100 | end 101 | else 102 | begin 103 | gntUpStr <= 0; //writeEnable <= 0; 104 | end 105 | // ----------------------------- read process -------------------------- // 106 | if (read_buf ) 107 | begin 108 | gntInCtr <= 1; //readEnable <= 1; 109 | //read_ptr <= read_ptr + {{addressWidth{1'b0}},1'b1}; 110 | read_ptr <= read_ptr + 1'b1; 111 | //readAddr <= readAddr + 1'b1; 112 | PacketOut <= ram[readAddr]; 113 | end 114 | else 115 | begin 116 | gntInCtr <= 0; //readEnable <= 0; 117 | end 118 | end // reset 119 | end // always 120 | 121 | //// Memory write 122 | //always @(posedge clk or negedge reset) 123 | //begin 124 | //if (writeEnable) 125 | //ram[writeAddr] <= PacketIn; 126 | //end 127 | //// Memory Read 128 | //always @(posedge clk) 129 | //begin 130 | //if (readEnable) 131 | //begin 132 | //PacketOut <= ram[readAddr]; 133 | //end 134 | //end 135 | 136 | endmodule 137 | 138 | // ------------------------ instantiation Devices --------------------------- // 139 | 140 | /* instantiate ram to buffer received Packet. */ 141 | //ram # (.dataWidth(dataWidth),.addressWidth(addressWidth)) fifoBuffer 142 | //( 143 | //.clk(clk), 144 | //.reset(reset), 145 | //.writeEn(writeEnable), 146 | //.readEn(readEnable), 147 | //.writeAddr(writeAddr), 148 | //.readAddr(readAddr), 149 | //.dataIn(PacketIn), 150 | //.dataOut(PacketOut) 151 | //); 152 | //initial 153 | // begin 154 | // gntInCtr <= 0; 155 | // gntUpStr <= 0; 156 | // writeEnable <= 0; 157 | // readEnable <= 0; 158 | // writeAddr <= 0; 159 | // readAddr <= 0; 160 | // EnableGnt <= 1; 161 | // end 162 | // 163 | //// ----------------------- Sequential Logic -------------------------------- // 164 | //always @(posedge clk or negedge reset) 165 | // begin 166 | // if( !reset)//reset all registers 167 | // begin 168 | // gntInCtr <= 0; 169 | // gntUpStr <= 0; 170 | // readEnable <= 0; 171 | // writeEnable <= 0; 172 | // writeAddr <= 0; 173 | // readAddr <= 0; 174 | // EnableGnt <= 1; 175 | // end 176 | // // --------------------------------------------------------------------- // 177 | // else 178 | // begin 179 | //// handle request from up stream router 180 | // if ( !reqUpStr) 181 | // EnableGnt <= 1; 182 | // 183 | // if ( reqUpStr && ! full && EnableGnt)// Buffer not Full 184 | // begin 185 | // gntUpStr <= 1; 186 | // EnableGnt <= 0; 187 | // writeEnable <= 1; 188 | // writeAddr <= writeAddr + 1'b1; 189 | // end 190 | // else 191 | // begin 192 | // gntUpStr <= 0; 193 | // writeEnable <= 0; 194 | // end 195 | // 196 | // if ( reqInCtr && ! empty ) 197 | // begin 198 | // gntInCtr <= 1; 199 | // readEnable <= 1; 200 | // readAddr <= readAddr +1'b1; 201 | // end 202 | // else 203 | // begin 204 | // readEnable <= 0; 205 | // gntInCtr <= 0; 206 | // end 207 | // end // reset 208 | // end // always 209 | //// ----------------------- Combinational Logic ------------------------------ // 210 | //// enabel writing to fifo when request is applied from Up stream Router 211 | ////assign writeEnable = (! gntUpStr )? reqUpStr : 1'b0 ; // if full writeEn=req else 0; 212 | // /*(cond) ? (result if cond true):(result if cond false)*/ 213 | //// enable reading from fifo when request is applied from input Controller 214 | ////assign gntInCtr = (! empty )? reqInCtr : 1'b0 ; 215 | // 216 | ////assign readEnable = (! empty )? reqInCtr : 1'b0 ; 217 | //// address compare signal 218 | //assign compAddr = readAddr + fifoDepth ; 219 | //// full indicator when write address equals to fifo depth 220 | //assign full = ( writeAddr == compAddr ); // shalaby 221 | ////assign full_FFC = ( writeAddr == (compAddr-4) ); // shalaby 222 | ////assign full = ( (writeAddr == compAddr) & writeEnable ); // maher 223 | //// empty indicator when read address equals to read address. 224 | //assign empty = ( writeAddr == readAddr ); 225 | //// --------------------------------------------------------------------------- // 226 | //endmodule 227 | -------------------------------------------------------------------------------- /Injector_000_000.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_000_000( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_0; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_0 = $fopen("Injector_Log_0.txt","w"); 65 | //$fdisplay(Injector_Log_0, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 4) 102 | begin //to 001_000 103 | //1bit direction +3bit position 104 | xDst <= 4'b1_001; yDst <= 4'b0_000; 105 | end 106 | else if(num >= 4 && num < 8) 107 | begin //to 010_000 108 | //1bit direction +3bit position 109 | xDst <= 4'b1_010; yDst <= 4'b0_000; 110 | end 111 | else if(num >= 8 && num < 12) 112 | begin //to 011_000 113 | //1bit direction +3bit position 114 | xDst <= 4'b1_011; yDst <= 4'b0_000; 115 | end 116 | else if(num >= 12 && num < 16) 117 | begin //to 100_000 118 | //1bit direction +3bit position 119 | xDst <= 4'b1_100; yDst <= 4'b0_000; 120 | end 121 | //################### Second Row #################### 122 | else if(num >= 16 && num < 20) 123 | begin //to 000_001 124 | //1bit direction +3bit position 125 | xDst <= 4'b0_000; yDst <= 4'b0_001; 126 | end 127 | else if(num >= 20 && num < 24) 128 | begin //to 001_001 129 | //1bit direction +3bit position 130 | xDst <= 4'b1_001; yDst <= 4'b0_001; 131 | end 132 | else if(num >= 24 && num < 28) 133 | begin //to 010_001 134 | //1bit direction +3bit position 135 | xDst <= 4'b1_010; yDst <= 4'b0_001; 136 | end 137 | else if(num >= 28 && num < 32) 138 | begin //to 011_001 139 | //1bit direction +3bit position 140 | xDst <= 4'b1_011; yDst <= 4'b0_001; 141 | end 142 | else if(num >= 32 && num < 36) 143 | begin //to 100_001 144 | //1bit direction +3bit position 145 | xDst <= 4'b1_100; yDst <= 4'b0_001; 146 | end 147 | //################### Third Row #################### 148 | else if(num >= 36 && num < 40) 149 | begin //to 000_010 150 | //1bit direction +3bit position 151 | xDst <= 4'b0_000; yDst <= 4'b0_010; 152 | end 153 | else if(num >= 40 && num < 44) 154 | begin //to 001_010 155 | //1bit direction +3bit position 156 | xDst <= 4'b1_001; yDst <= 4'b0_010; 157 | end 158 | else if(num >= 44 && num < 48) 159 | begin //to 010_010 160 | //1bit direction +3bit position 161 | xDst <= 4'b1_010; yDst <= 4'b0_010; 162 | end 163 | else if(num >= 48 && num < 52) 164 | begin //to 011_010 165 | //1bit direction +3bit position 166 | xDst <= 4'b1_011; yDst <= 4'b0_010; 167 | end 168 | else if(num >= 52 && num < 56) 169 | begin //to 100_010 170 | //1bit direction +3bit position 171 | xDst <= 4'b1_100; yDst <= 4'b0_010; 172 | end 173 | //################### Fourth Row #################### 174 | else if(num >= 56 && num < 60) 175 | begin //to 000_011 176 | //1bit direction +3bit position 177 | xDst <= 4'b0_000; yDst <= 4'b0_011; 178 | end 179 | else if(num >= 60 && num < 64) 180 | begin //to 001_011 181 | //1bit direction +3bit position 182 | xDst <= 4'b1_001; yDst <= 4'b0_011; 183 | end 184 | else if(num >= 64 && num < 68) 185 | begin //to 010_011 186 | //1bit direction +3bit position 187 | xDst <= 4'b1_010; yDst <= 4'b0_011; 188 | end 189 | else if(num >= 68 && num < 72) 190 | begin //to 011_011 191 | //1bit direction +3bit position 192 | xDst <= 4'b1_011; yDst <= 4'b0_011; 193 | end 194 | else if(num >= 72 && num < 76) 195 | begin //to 100_011 196 | //1bit direction +3bit position 197 | xDst <= 4'b1_100; yDst <= 4'b0_011; 198 | end 199 | //################### Fifth Row #################### 200 | else if(num >= 76 && num < 80) 201 | begin //to 000_100 202 | //1bit direction +3bit position 203 | xDst <= 4'b0_000; yDst <= 4'b0_100; 204 | end 205 | else if(num >= 80 && num < 84) 206 | begin //to 001_100 207 | //1bit direction +3bit position 208 | xDst <= 4'b1_001; yDst <= 4'b0_100; 209 | end 210 | else if(num >= 84 && num < 88) 211 | begin //to 010_100 212 | //1bit direction +3bit position 213 | xDst <= 4'b1_010; yDst <= 4'b0_100; 214 | end 215 | else if(num >= 88 && num < 92) 216 | begin //to 011_100 217 | //1bit direction +3bit position 218 | xDst <= 4'b1_011; yDst <= 4'b0_100; 219 | end 220 | else if(num >= 92 && num < 96) 221 | begin //to 100_100 222 | //1bit direction +3bit position 223 | xDst <= 4'b1_100; yDst <= 4'b0_100; 224 | end 225 | //###################################################################### 226 | PacketID <= PacketID + 1'b1; 227 | RandomInfo <= $random; 228 | xSrc <= 0; 229 | ySrc <= 0; 230 | STATE <= SEND_REQ; 231 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 232 | end 233 | //###################################################################### 234 | SEND_REQ:begin 235 | //###################################################################### 236 | if (PacketID != 1023) 237 | begin 238 | if (Count == Delay) 239 | begin 240 | if (!DnStrFull) // Buffer not Full !=1 241 | begin 242 | ReqDnStr <= 1; //send request to Local Port 243 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 244 | //PacketOut <= dataBuf; 245 | STATE <= WAIT_GRANT; 246 | Count <= 0; 247 | $fdisplay(Injector_Log_0, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 248 | end //if 249 | else 250 | begin 251 | STATE <= SEND_REQ; 252 | end 253 | end//if delay 254 | else 255 | begin 256 | Count <= Count+1'b1; 257 | end 258 | 259 | end //if (PacketID != 1023) 260 | end //SEND_REQ 261 | //###################################################################### 262 | WAIT_GRANT: begin 263 | //###################################################################### 264 | if (GntDnStr) // Buffer not Full 265 | begin 266 | ReqDnStr <=0; //send request to Local Port 267 | STATE <= IDLE; 268 | end 269 | else 270 | begin 271 | STATE <= WAIT_GRANT; 272 | end 273 | end 274 | endcase 275 | end //else 276 | end // always 277 | assign PacketOut = dataBuf; 278 | endmodule 279 | 280 | //######################################################################################################### -------------------------------------------------------------------------------- /Injector_000_001.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_000_001( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_5; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_5 = $fopen("Injector_Log_5.txt","w"); 65 | //$fdisplay(Injector_Log_5, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 000_010 103 | xDst = 4'b0_000; yDst = 4'b0_001; 104 | end 105 | //############################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_5, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### -------------------------------------------------------------------------------- /Injector_000_010.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module Injector_000_010( 5 | // Global Settings 6 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 7 | Top module i.e. Traffic Generator.*/ 8 | reset, 9 | clk, 10 | // -- Output Port Traffic: -- 11 | ReqDnStr, 12 | GntDnStr, 13 | DnStrFull, 14 | PacketOut 15 | ); 16 | // ------------------------ Parameter Declarations --------------------------- // 17 | //for 5x5 mesh 18 | parameter routerID=6'b000_000; // change depends on mesh size 19 | parameter ModuleID =6'b000_000; 20 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 21 | parameter dataWidth = 32;// number of bits for data bus 22 | parameter dim = 4;// dimension of x,y fields in source and destination 23 | //Injector States 24 | parameter IDLE =2'b00, 25 | PKT_PREP =2'b01, 26 | SEND_REQ =2'b10, 27 | WAIT_GRANT =2'b11; 28 | // ------------------------ Inputs Declarations ------------------------------ // 29 | input clk; 30 | input reset; 31 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 32 | input GntDnStr; // Grant from Down Stream Router 33 | // ------------------------ Outputs Declarations ----------------------------- // 34 | output ReqDnStr; // Injector send request to router to send packets 35 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 36 | // --------------------------- Wire Declarations ----------------------------- // 37 | wire clk; 38 | wire reset; 39 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 40 | wire GntDnStr; // Grant from Down Stream Router 41 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 42 | // --------------------------------------------------------------------------- // 43 | // ------------------------ Registers Declarations --------------------------- // 44 | reg ReqDnStr; // request to Local Port FIFO Buffer 45 | reg [dataWidth-1:0] dataBuf;// data buffer register 46 | //Packet Contents 47 | // source and destination registers 48 | // 3 bit for position and 1 bit for direction 49 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 50 | reg [1:0] STATE; 51 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 52 | reg [9:0] PacketID; // 0:1023 53 | reg [9:0] RandomInfo; // 54 | reg [31:0] CYCLE_COUNTER; //Timestamp 55 | integer Delay, Count; 56 | //for Simulation log 57 | integer Injector_Log_10; 58 | reg [7:0] num; //0 : 255 59 | // --------------------------------------------------------------------------- // 60 | initial 61 | begin 62 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 63 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 64 | //for Simulation log 65 | Injector_Log_10 = $fopen("Injector_Log_10.txt","w"); 66 | //$fdisplay(Injector_Log_10, " SimulationTime ; SendTime ; SenderID ; PacketID "); 67 | end 68 | 69 | always @(posedge clk) 70 | begin 71 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 72 | end 73 | //########################### Modules(PEs) Injector ################################### 74 | always @(posedge clk or negedge reset) 75 | begin 76 | if( !reset) 77 | begin 78 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 79 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 80 | ReqDnStr <= 0; Count <= 0; 81 | STATE <= IDLE; 82 | end 83 | //######################################################################################################### 84 | else 85 | begin 86 | case(STATE) 87 | //################## STATE ############################################### 88 | IDLE:begin 89 | //###################################################################### 90 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 91 | //Delay between two consequence packets. to be changed to change Injection Rate 92 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 93 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 94 | STATE <= PKT_PREP; 95 | end 96 | //###################################################################### 97 | PKT_PREP:begin 98 | //################### Packeckt Preparation ############################# 99 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 100 | // West -> 0 South -> 0 //1bit direction +3bit position 101 | //################### #################### 102 | if(num >= 0 && num < 96) 103 | begin //to 000_100 104 | xDst <= 4'b0_000; yDst <= 4'b0_010; 105 | end 106 | //###################################################################### 107 | PacketID <= PacketID + 1'b1; 108 | RandomInfo <= $random; 109 | xSrc <= 0; 110 | ySrc <= 0; 111 | STATE <= SEND_REQ; 112 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 113 | end 114 | //###################################################################### 115 | SEND_REQ:begin 116 | //###################################################################### 117 | if (PacketID != 1023) 118 | begin 119 | if (Count == Delay) 120 | begin 121 | if (!DnStrFull) // Buffer not Full !=1 122 | begin 123 | ReqDnStr <= 1; //send request to Local Port 124 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 125 | //PacketOut <= dataBuf; 126 | STATE <= WAIT_GRANT; 127 | Count <= 0; 128 | $fdisplay(Injector_Log_10, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 129 | end //if 130 | else 131 | begin 132 | STATE <= SEND_REQ; 133 | end 134 | end//if delay 135 | else 136 | begin 137 | Count <= Count+1'b1; 138 | end 139 | 140 | end //if (PacketID != 1023) 141 | end //SEND_REQ 142 | //###################################################################### 143 | WAIT_GRANT: begin 144 | //###################################################################### 145 | if (GntDnStr) // Buffer not Full 146 | begin 147 | ReqDnStr <=0; //send request to Local Port 148 | STATE <= IDLE; 149 | end 150 | else 151 | begin 152 | STATE <= WAIT_GRANT; 153 | end 154 | end 155 | endcase 156 | end //else 157 | end // always 158 | assign PacketOut = dataBuf; 159 | endmodule 160 | 161 | //######################################################################################################### -------------------------------------------------------------------------------- /Injector_000_100.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_000_100( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_20; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_20 = $fopen("Injector_Log_20.txt","w"); 65 | //$fdisplay(Injector_Log_20, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 001_000 103 | xDst <= 4'b1_001; yDst <= 4'b1_100; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_20, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### -------------------------------------------------------------------------------- /Injector_001_000.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_001_000( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_1; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_1 = $fopen("Injector_Log_1.txt","w"); 65 | //$fdisplay(Injector_Log_1, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 010_000 103 | xDst <= 4'b1_001; yDst <= 4'b0_000; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_1, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### -------------------------------------------------------------------------------- /Injector_001_001.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_001_001( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_6; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_6 = $fopen("Injector_Log_6.txt","w"); 65 | //$fdisplay(Injector_Log_6, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 010_010 103 | xDst <= 4'b1_001; yDst <= 4'b0_001; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_6, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### 161 | -------------------------------------------------------------------------------- /Injector_001_010.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_001_010( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_11; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_11 = $fopen("Injector_Log_11.txt","w"); 65 | //$fdisplay(Injector_Log_11, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 010_100 103 | xDst <= 4'b1_001; yDst <= 4'b0_010; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_11, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### 161 | -------------------------------------------------------------------------------- /Injector_001_100.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_001_100( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_21; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_21 = $fopen("Injector_Log_21.txt","w"); 65 | //$fdisplay(Injector_Log_21, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 011_000 103 | xDst <= 4'b1_010; yDst <= 4'b1_100; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_21, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### 161 | 162 | 163 | 164 | -------------------------------------------------------------------------------- /Injector_010_000.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_010_000( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_2; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_2 = $fopen("Injector_Log_2.txt","w"); 65 | //$fdisplay(Injector_Log_2, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 100_000 103 | //1bit direction +3bit position 104 | xDst <= 4'b1_010; yDst <= 4'b0_000; 105 | end 106 | //###################################################################### 107 | PacketID <= PacketID + 1'b1; 108 | RandomInfo <= $random; 109 | xSrc <= 0; 110 | ySrc <= 0; 111 | STATE <= SEND_REQ; 112 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 113 | end 114 | //###################################################################### 115 | SEND_REQ:begin 116 | //###################################################################### 117 | if (PacketID != 1023) 118 | begin 119 | if (Count == Delay) 120 | begin 121 | if (!DnStrFull) // Buffer not Full !=1 122 | begin 123 | ReqDnStr <= 1; //send request to Local Port 124 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 125 | //PacketOut <= dataBuf; 126 | STATE <= WAIT_GRANT; 127 | Count <= 0; 128 | $fdisplay(Injector_Log_2, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 129 | end //if 130 | else 131 | begin 132 | STATE <= SEND_REQ; 133 | end 134 | end//if delay 135 | else 136 | begin 137 | Count <= Count+1'b1; 138 | end 139 | 140 | end //if (PacketID != 1023) 141 | end //SEND_REQ 142 | //###################################################################### 143 | WAIT_GRANT: begin 144 | //###################################################################### 145 | if (GntDnStr) // Buffer not Full 146 | begin 147 | ReqDnStr <=0; //send request to Local Port 148 | STATE <= IDLE; 149 | end 150 | else 151 | begin 152 | STATE <= WAIT_GRANT; 153 | end 154 | end 155 | endcase 156 | end //else 157 | end // always 158 | assign PacketOut = dataBuf; 159 | endmodule 160 | 161 | //######################################################################################################### 162 | 163 | 164 | -------------------------------------------------------------------------------- /Injector_010_001.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_010_001( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_7; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_7 = $fopen("Injector_Log_7.txt","w"); 65 | //$fdisplay(Injector_Log_7, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 100_010 103 | xDst <= 4'b1_010; yDst <= 4'b0_001; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_7, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### 161 | 162 | 163 | -------------------------------------------------------------------------------- /Injector_010_010.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_010_010( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_12; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_12 = $fopen("Injector_Log_12.txt","w"); 65 | //$fdisplay(Injector_Log_12, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 100_100 103 | xDst <= 4'b1_010; yDst <= 4'b0_010; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_12, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### 161 | 162 | 163 | -------------------------------------------------------------------------------- /Injector_100_000.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module Injector_100_000( 5 | // Global Settings 6 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 7 | Top module i.e. Traffic Generator.*/ 8 | reset, 9 | clk, 10 | // -- Output Port Traffic: -- 11 | ReqDnStr, 12 | GntDnStr, 13 | DnStrFull, 14 | PacketOut 15 | ); 16 | // ------------------------ Parameter Declarations --------------------------- // 17 | //for 5x5 mesh 18 | parameter routerID=6'b000_000; // change depends on mesh size 19 | parameter ModuleID =6'b000_000; 20 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 21 | parameter dataWidth = 32;// number of bits for data bus 22 | parameter dim = 4;// dimension of x,y fields in source and destination 23 | //Injector States 24 | parameter IDLE =2'b00, 25 | PKT_PREP =2'b01, 26 | SEND_REQ =2'b10, 27 | WAIT_GRANT =2'b11; 28 | // ------------------------ Inputs Declarations ------------------------------ // 29 | input clk; 30 | input reset; 31 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 32 | input GntDnStr; // Grant from Down Stream Router 33 | // ------------------------ Outputs Declarations ----------------------------- // 34 | output ReqDnStr; // Injector send request to router to send packets 35 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 36 | // --------------------------- Wire Declarations ----------------------------- // 37 | wire clk; 38 | wire reset; 39 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 40 | wire GntDnStr; // Grant from Down Stream Router 41 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 42 | // --------------------------------------------------------------------------- // 43 | // ------------------------ Registers Declarations --------------------------- // 44 | reg ReqDnStr; // request to Local Port FIFO Buffer 45 | reg [dataWidth-1:0] dataBuf;// data buffer register 46 | //Packet Contents 47 | // source and destination registers 48 | // 3 bit for position and 1 bit for direction 49 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 50 | reg [1:0] STATE; 51 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 52 | reg [9:0] PacketID; // 0:1023 53 | reg [9:0] RandomInfo; // 54 | reg [31:0] CYCLE_COUNTER; //Timestamp 55 | integer Delay, Count; 56 | //for Simulation log 57 | integer Injector_Log_4; 58 | reg [7:0] num; //0 : 255 59 | // --------------------------------------------------------------------------- // 60 | initial 61 | begin 62 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 63 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 64 | //for Simulation log 65 | Injector_Log_4 = $fopen("Injector_Log_4.txt","w"); 66 | //$fdisplay(Injector_Log_4, " SimulationTime ; SendTime ; SenderID ; PacketID "); 67 | end 68 | 69 | always @(posedge clk) 70 | begin 71 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 72 | end 73 | //########################### Modules(PEs) Injector ################################### 74 | always @(posedge clk or negedge reset) 75 | begin 76 | if( !reset) 77 | begin 78 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 79 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 80 | ReqDnStr <= 0; Count <= 0; 81 | STATE <= IDLE; 82 | end 83 | //######################################################################################################### 84 | else 85 | begin 86 | case(STATE) 87 | //################## STATE ############################################### 88 | IDLE:begin 89 | //###################################################################### 90 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 91 | //Delay between two consequence packets. to be changed to change Injection Rate 92 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 93 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 94 | STATE <= PKT_PREP; 95 | end 96 | //###################################################################### 97 | PKT_PREP:begin 98 | //################### Packeckt Preparation ############################# 99 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 100 | // West -> 0 South -> 0 //1bit direction +3bit position 101 | //################### First Row #################### 102 | if(num >= 0 && num < 96) 103 | begin //to 000_001 104 | xDst <= 4'b0_100; yDst <= 4'b0_001; 105 | end 106 | //###################################################################### 107 | PacketID <= PacketID + 1'b1; 108 | RandomInfo <= $random; 109 | xSrc <= 0; 110 | ySrc <= 0; 111 | STATE <= SEND_REQ; 112 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 113 | end 114 | //###################################################################### 115 | SEND_REQ:begin 116 | //###################################################################### 117 | if (PacketID != 1023) 118 | begin 119 | if (Count == Delay) 120 | begin 121 | if (!DnStrFull) // Buffer not Full !=1 122 | begin 123 | ReqDnStr <= 1; //send request to Local Port 124 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 125 | //PacketOut <= dataBuf; 126 | STATE <= WAIT_GRANT; 127 | Count <= 0; 128 | $fdisplay(Injector_Log_4, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 129 | end //if 130 | else 131 | begin 132 | STATE <= SEND_REQ; 133 | end 134 | end//if delay 135 | else 136 | begin 137 | Count <= Count+1'b1; 138 | end 139 | 140 | end //if (PacketID != 1023) 141 | end //SEND_REQ 142 | //###################################################################### 143 | WAIT_GRANT: begin 144 | //###################################################################### 145 | if (GntDnStr) // Buffer not Full 146 | begin 147 | ReqDnStr <=0; //send request to Local Port 148 | STATE <= IDLE; 149 | end 150 | else 151 | begin 152 | STATE <= WAIT_GRANT; 153 | end 154 | end 155 | endcase 156 | end //else 157 | end // always 158 | assign PacketOut = dataBuf; 159 | endmodule 160 | 161 | //######################################################################################################### 162 | 163 | -------------------------------------------------------------------------------- /Injector_100_001.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Injector_100_001( 4 | // Global Settings 5 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 6 | Top module i.e. Traffic Generator.*/ 7 | reset, 8 | clk, 9 | // -- Output Port Traffic: -- 10 | ReqDnStr, 11 | GntDnStr, 12 | DnStrFull, 13 | PacketOut 14 | ); 15 | // ------------------------ Parameter Declarations --------------------------- // 16 | //for 5x5 mesh 17 | parameter routerID=6'b000_000; // change depends on mesh size 18 | parameter ModuleID =6'b000_000; 19 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 20 | parameter dataWidth = 32;// number of bits for data bus 21 | parameter dim = 4;// dimension of x,y fields in source and destination 22 | //Injector States 23 | parameter IDLE =2'b00, 24 | PKT_PREP =2'b01, 25 | SEND_REQ =2'b10, 26 | WAIT_GRANT =2'b11; 27 | // ------------------------ Inputs Declarations ------------------------------ // 28 | input clk; 29 | input reset; 30 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 31 | input GntDnStr; // Grant from Down Stream Router 32 | // ------------------------ Outputs Declarations ----------------------------- // 33 | output ReqDnStr; // Injector send request to router to send packets 34 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 35 | // --------------------------- Wire Declarations ----------------------------- // 36 | wire clk; 37 | wire reset; 38 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 39 | wire GntDnStr; // Grant from Down Stream Router 40 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ Registers Declarations --------------------------- // 43 | reg ReqDnStr; // request to Local Port FIFO Buffer 44 | reg [dataWidth-1:0] dataBuf;// data buffer register 45 | //Packet Contents 46 | // source and destination registers 47 | // 3 bit for position and 1 bit for direction 48 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 49 | reg [1:0] STATE; 50 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 51 | reg [9:0] PacketID; // 0:1023 52 | reg [9:0] RandomInfo; // 53 | reg [31:0] CYCLE_COUNTER; //Timestamp 54 | integer Delay, Count; 55 | //for Simulation log 56 | integer Injector_Log_9; 57 | reg [7:0] num; //0 : 255 58 | // --------------------------------------------------------------------------- // 59 | initial 60 | begin 61 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 62 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 63 | //for Simulation log 64 | Injector_Log_9 = $fopen("Injector_Log_9.txt","w"); 65 | //$fdisplay(Injector_Log_9, " SimulationTime ; SendTime ; SenderID ; PacketID "); 66 | end 67 | 68 | always @(posedge clk) 69 | begin 70 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 71 | end 72 | //########################### Modules(PEs) Injector ################################### 73 | always @(posedge clk or negedge reset) 74 | begin 75 | if( !reset) 76 | begin 77 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 78 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 79 | ReqDnStr <= 0; Count <= 0; 80 | STATE <= IDLE; 81 | end 82 | //######################################################################################################### 83 | else 84 | begin 85 | case(STATE) 86 | //################## STATE ############################################### 87 | IDLE:begin 88 | //###################################################################### 89 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 90 | //Delay between two consequence packets. to be changed to change Injection Rate 91 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 92 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 93 | STATE <= PKT_PREP; 94 | end 95 | //###################################################################### 96 | PKT_PREP:begin 97 | //################### Packeckt Preparation ############################# 98 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 99 | // West -> 0 South -> 0 //1bit direction +3bit position 100 | //################### First Row #################### 101 | if(num >= 0 && num < 96) 102 | begin //to 000_011 103 | xDst <= 4'b0_100; yDst <= 4'b0_010; 104 | end 105 | //###################################################################### 106 | PacketID <= PacketID + 1'b1; 107 | RandomInfo <= $random; 108 | xSrc <= 0; 109 | ySrc <= 0; 110 | STATE <= SEND_REQ; 111 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 112 | end 113 | //###################################################################### 114 | SEND_REQ:begin 115 | //###################################################################### 116 | if (PacketID != 1023) 117 | begin 118 | if (Count == Delay) 119 | begin 120 | if (!DnStrFull) // Buffer not Full !=1 121 | begin 122 | ReqDnStr <= 1; //send request to Local Port 123 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 124 | //PacketOut <= dataBuf; 125 | STATE <= WAIT_GRANT; 126 | Count <= 0; 127 | $fdisplay(Injector_Log_9, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 128 | end //if 129 | else 130 | begin 131 | STATE <= SEND_REQ; 132 | end 133 | end//if delay 134 | else 135 | begin 136 | Count <= Count+1'b1; 137 | end 138 | 139 | end //if (PacketID != 1023) 140 | end //SEND_REQ 141 | //###################################################################### 142 | WAIT_GRANT: begin 143 | //###################################################################### 144 | if (GntDnStr) // Buffer not Full 145 | begin 146 | ReqDnStr <=0; //send request to Local Port 147 | STATE <= IDLE; 148 | end 149 | else 150 | begin 151 | STATE <= WAIT_GRANT; 152 | end 153 | end 154 | endcase 155 | end //else 156 | end // always 157 | assign PacketOut = dataBuf; 158 | endmodule 159 | 160 | //######################################################################################################### 161 | 162 | -------------------------------------------------------------------------------- /Injector_100_100.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Injector_100_100( 3 | // Global Settings 4 | /*-- for Injection rate (load) and typr of traffic (Random, ..etc) it will be defined in the 5 | Top module i.e. Traffic Generator.*/ 6 | reset, 7 | clk, 8 | // -- Output Port Traffic: -- 9 | ReqDnStr, 10 | GntDnStr, 11 | DnStrFull, 12 | PacketOut 13 | ); 14 | // ------------------------ Parameter Declarations --------------------------- // 15 | //for 5x5 mesh 16 | parameter routerID=6'b000_000; // change depends on mesh size 17 | parameter ModuleID =6'b000_000; 18 | parameter CLOCK_MULT=3'b001; //// packet injection rate (percentage of cycles) 19 | parameter dataWidth = 32;// number of bits for data bus 20 | parameter dim = 4;// dimension of x,y fields in source and destination 21 | //Injector States 22 | parameter IDLE =2'b00, 23 | PKT_PREP =2'b01, 24 | SEND_REQ =2'b10, 25 | WAIT_GRANT =2'b11; 26 | // ------------------------ Inputs Declarations ------------------------------ // 27 | input clk; 28 | input reset; 29 | input DnStrFull; // indicator from Local about FIFO buffer status.. if full = 1 else = 0 30 | input GntDnStr; // Grant from Down Stream Router 31 | // ------------------------ Outputs Declarations ----------------------------- // 32 | output ReqDnStr; // Injector send request to router to send packets 33 | output [dataWidth-1:0] PacketOut;// output data packet form Injector 34 | // --------------------------- Wire Declarations ----------------------------- // 35 | wire clk; 36 | wire reset; 37 | wire DnStrFull;// indicator for Injector about Local FIFO buffer status .. if full = 1 else = 0 38 | wire GntDnStr; // Grant from Down Stream Router 39 | wire [dataWidth-1:0] PacketOut;// output data packet form fifo 40 | // --------------------------------------------------------------------------- // 41 | // ------------------------ Registers Declarations --------------------------- // 42 | reg ReqDnStr; // request to Local Port FIFO Buffer 43 | reg [dataWidth-1:0] dataBuf;// data buffer register 44 | //Packet Contents 45 | // source and destination registers 46 | // 3 bit for position and 1 bit for direction 47 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 48 | reg [1:0] STATE; 49 | //PacketID and RandomInfo can be adjusted to fit the diminsion bits 50 | reg [9:0] PacketID; // 0:1023 51 | reg [9:0] RandomInfo; // 52 | reg [31:0] CYCLE_COUNTER; //Timestamp 53 | integer Delay, Count; 54 | //for Simulation log 55 | integer Injector_Log_24; 56 | reg [7:0] num; //0 : 255 57 | // --------------------------------------------------------------------------- // 58 | initial 59 | begin 60 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; STATE <= IDLE; CYCLE_COUNTER <= 0; 61 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; Count <= 0; Delay <= 0; 62 | //for Simulation log 63 | Injector_Log_24 = $fopen("Injector_Log_24.txt","w"); 64 | //$fdisplay(Injector_Log_24, " SimulationTime ; SendTime ; SenderID ; PacketID "); 65 | end 66 | 67 | always @(posedge clk) 68 | begin 69 | CYCLE_COUNTER <= CYCLE_COUNTER + 1'b1; 70 | end 71 | //########################### Modules(PEs) Injector ################################### 72 | always @(posedge clk or negedge reset) 73 | begin 74 | if( !reset) 75 | begin 76 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; 77 | dataBuf <= 0; PacketID <= 0; num <= 0; RandomInfo <= 0; 78 | ReqDnStr <= 0; Count <= 0; 79 | STATE <= IDLE; 80 | end 81 | //######################################################################################################### 82 | else 83 | begin 84 | case(STATE) 85 | //################## STATE ############################################### 86 | IDLE:begin 87 | //###################################################################### 88 | //Note: Comment Delay and Its Condition If you want to see Full Signal Or increase the Probability 89 | //Delay between two consequence packets. to be changed to change Injection Rate 90 | Delay <= {$random}% 16;//{$random}%3;// 0,1,2,3 are selected randomly 91 | num <= {$random}% 95;// 0,1,2,3, ... to 95 are selected randomly 92 | STATE <= PKT_PREP; 93 | end 94 | //###################################################################### 95 | PKT_PREP:begin 96 | //################### Packeckt Preparation ############################# 97 | //Directions: East -> 1 North -> 1 //xDst <= 4'b0_011; yDst <= 4'b1_010; 98 | // West -> 0 South -> 0 //1bit direction +3bit position 99 | //################### #################### 100 | if(num >= 0 && num < 96) 101 | begin //to 001_001 102 | xDst <= 4'b0_011; yDst <= 4'b1_011; 103 | end 104 | //###################################################################### 105 | PacketID <= PacketID + 1'b1; 106 | RandomInfo <= $random; 107 | xSrc <= 0; 108 | ySrc <= 0; 109 | STATE <= SEND_REQ; 110 | //%%%%%%%%%%%%%%%%%%%%%%%%%%% END of Packeckt Preparation %%%%%%%%%%%%%%%%%%%%%%%%%%% 111 | end 112 | //###################################################################### 113 | SEND_REQ:begin 114 | //###################################################################### 115 | if (PacketID != 1023) 116 | begin 117 | if (Count == Delay) 118 | begin 119 | if (!DnStrFull) // Buffer not Full !=1 120 | begin 121 | ReqDnStr <= 1; //send request to Local Port 122 | dataBuf <= {xDst, yDst, xSrc,ySrc,PacketID, ModuleID};//, RandomInfo} ; 123 | //PacketOut <= dataBuf; 124 | STATE <= WAIT_GRANT; 125 | Count <= 0; 126 | $fdisplay(Injector_Log_24, $time, " ; %d ; %d ; %d ", CYCLE_COUNTER, ModuleID,PacketID); 127 | end //if 128 | else 129 | begin 130 | STATE <= SEND_REQ; 131 | end 132 | end//if delay 133 | else 134 | begin 135 | Count <= Count+1'b1; 136 | end 137 | 138 | end //if (PacketID != 1023) 139 | end //SEND_REQ 140 | //###################################################################### 141 | WAIT_GRANT: begin 142 | //###################################################################### 143 | if (GntDnStr) // Buffer not Full 144 | begin 145 | ReqDnStr <=0; //send request to Local Port 146 | STATE <= IDLE; 147 | end 148 | else 149 | begin 150 | STATE <= WAIT_GRANT; 151 | end 152 | end 153 | endcase 154 | end //else 155 | end // always 156 | assign PacketOut = dataBuf; 157 | endmodule 158 | 159 | //######################################################################################################### 160 | -------------------------------------------------------------------------------- /InputPort.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | ##################################################################################### 4 | Company: 5 | Engineer: 6 | 7 | Create Date: 18:52:19 06/22/2013 8 | Design Name: 9 | Module Name: InputPort 10 | Project Name: 11 | Target Devices: 12 | Tool versions: 13 | Description: This file implements Input Controller by connection inController 14 | Unit with fifo 15 | 16 | Dependencies: 17 | 18 | Revision: 19 | Revision 0.01 - File Created 20 | Additional Comments: 21 | 22 | ##################################################################################### 23 | */ 24 | 25 | module InputPort ( clk, reset, reqUpStr , gntUpStr , full, PacketIn, 26 | reqOutCntr, gntOutCntr, PacketOut ); 27 | // ------------------------ Parameter Declarations --------------------------- // 28 | parameter routerNo = 24; // change depends on mesh size 29 | parameter dataWidth = 32; // number of bits for data bus 30 | parameter addressWidth = 2;//4;// number of bits for address bus 31 | parameter fifoDepth = ( ( 1 << addressWidth ) - 1 ); // number of entries in fifo buffer 32 | parameter dim = 2;// dimension of x,y fields in source and destination 33 | // ------------------------ Inputs Declarations ------------------------------ // 34 | input clk; 35 | input reset; 36 | input reqUpStr;// Up stream router request 37 | // grant bus from output controller which grant communication with other routers 38 | input [4:0] gntOutCntr; 39 | input [dataWidth-1:0] PacketIn;// input data Packet to fifo 40 | // ------------------------ Outputs Declarations ----------------------------- // 41 | output full; // full indication from up stream router 42 | output gntUpStr;// Up stream router grant 43 | output [dataWidth-1:0] PacketOut;// output data Packet form fifo 44 | /* request bus to output controller which establish connection to other routers 45 | 4 ports + Local Network Inerface 46 | ports in order ( East(0) - North(1) - West(2) - South(3) - Local(4) ) 47 | North (1) 48 | | 49 | | 50 | East(0)---- Local(4) ---- West (2) 51 | | 52 | | 53 | South (3) 54 | */ 55 | output [4:0] reqOutCntr; 56 | // --------------------------------------------------------------------------- // 57 | // --------------------------- Wire Declarations ----------------------------- // 58 | wire clk; 59 | wire reset; 60 | wire reqUpStr , gntUpStr;// request & grant fifo buffer 61 | // full indication from up stream router 62 | wire full; //shalaby 63 | // grant bus from output controller which grant communication with other routers 64 | wire [4:0] gntOutCntr; 65 | wire [dataWidth-1:0] PacketIn;// input data Packet from fifo 66 | wire [dataWidth-1:0] PacketOut;// output data Packet to output Controller 67 | // connection between fifo and Input Controller 68 | wire emptyFifoInCntr, reqFifoInCntr, gntFifoInCntr; 69 | wire [dataWidth-1:0] PacketFifoInCntr; 70 | // --------------------------------------------------------------------------- // 71 | // ------------------------ Registers Declarations --------------------------- // 72 | // --------------------------------------------------------------------------- // 73 | // ------------------------ instantiation Devices --------------------------- // 74 | /* instantiate FIFO buffer */ 75 | FIFO # (.dataWidth(dataWidth),.addressWidth(addressWidth), 76 | .fifoDepth(fifoDepth)) fifo 77 | ( 78 | .clk(clk), 79 | .reset(reset), 80 | .reqUpStr(reqUpStr), 81 | .gntUpStr(gntUpStr), 82 | .full(full), 83 | .PacketIn(PacketIn), 84 | .reqInCtr(reqFifoInCntr), 85 | .gntInCtr(gntFifoInCntr), 86 | .empty(emptyFifoInCntr), 87 | .PacketOut(PacketFifoInCntr) 88 | ); 89 | // --------------------------------------------------------------------------- // 90 | 91 | InputPortController # (.dataWidth(dataWidth),.dim(dim)) InputPortController 92 | ( 93 | .clk(clk), 94 | .reset(reset), 95 | .req(reqFifoInCntr), 96 | .gnt(gntFifoInCntr), 97 | .empty(emptyFifoInCntr), 98 | .PacketIn(PacketFifoInCntr), 99 | .reqOutCntr(reqOutCntr), 100 | .gntOutCntr(gntOutCntr), 101 | .PacketOut(PacketOut) 102 | ); 103 | // --------------------------------------------------------------------------- // 104 | // ----------------------- Sequential Logic -------------------------------- // 105 | // --------------------------------------------------------------------------- // 106 | // ----------------------- Combinational Logic ------------------------------ // 107 | // --------------------------------------------------------------------------- // 108 | endmodule 109 | // ----------------------------- End of File --------------------------------- // 110 | 111 | -------------------------------------------------------------------------------- /InputPortController.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | ##################################################################################### 4 | Company: 5 | Engineer: 6 | 7 | Create Date: 18:54:00 06/22/2013 8 | Design Name: 9 | Module Name: InputPortController 10 | Project Name: 11 | Target Devices: 12 | Tool versions: 13 | Description: This file implements Input Controller which implements routing 14 | algorithm and set up commnication between output Controller and 15 | fifo buffer. 16 | Network On Chip Router. 17 | 18 | Dependencies: 19 | 20 | Revision: 21 | Revision 0.01 - File Created 22 | Additional Comments: 23 | 24 | ##################################################################################### 25 | */ 26 | module InputPortController ( clk, reset, req , gnt , empty , PacketIn, 27 | reqOutCntr, gntOutCntr, PacketOut ); 28 | // --------------------------------------------------------------------------- // 29 | // ------------------------ Parameter Declarations --------------------------- // 30 | parameter routerNo = 24; // change depends on mesh size 31 | parameter dataWidth = 32;// number of bits for data bus 32 | // dimension of x,y fields in source and destination 33 | parameter dim = 4; 34 | // names of states of FSM 35 | parameter Idle = 2'b00, 36 | Read = 2'b01, 37 | Route = 2'b10, 38 | Grant = 2'b11; 39 | // ------------------------ Inputs Declarations ------------------------------ // 40 | input clk; 41 | input reset; 42 | input gnt;// grant from FIFO Buffer 43 | input empty;// indicator from FIFO buffer .. if empty = 1 else = 0 44 | input [dataWidth-1:0] PacketIn;// input data Packet to fifo 45 | // grant bus from output controller which grant communication with other routers 46 | input [4:0] gntOutCntr; 47 | // ------------------------ Outputs Declarations ----------------------------- // 48 | output req;// request to FIFO Buffer 49 | output [dataWidth-1:0] PacketOut;// output data Packet form fifo 50 | /* request bus to output controller which establish connection to other routers 51 | 4 ports + Local Network Inerface 52 | ports in order ( East(0) - North(1) - West(2) - South(3) - Local(4) ) 53 | North (1) 54 | | 55 | | 56 | East(0)---- Local(4) ---- West (2) 57 | | 58 | | 59 | South (3) 60 | */ 61 | output [4:0] reqOutCntr; 62 | // --------------------------- Wire Declarations ----------------------------- // 63 | wire clk; 64 | wire reset; 65 | wire gnt;// grant from fifo buffer 66 | // grant bus from output controller which grant communication with other routers 67 | wire [4:0] gntOutCntr; 68 | wire [dataWidth-1:0] PacketIn;// input data Packet from fifo 69 | wire [dataWidth-1:0] PacketOut;// output data Packet to output Controller 70 | wire empty;// indicator from FIFO buffer .. if empty = 1 else = 0 71 | // ------------------------ Registers Declarations --------------------------- // 72 | reg req, EnableRoute;// request to FIFO Buffer 73 | // request bus to output controller which establish connection to other routers 74 | // 4 ports + Local Network Inerface 75 | reg [4:0] reqOutCntr; 76 | reg [dataWidth-1:0] dataBuf,Temp;// data buffer register 77 | // source and destination registers for 2X2 mesh x and y has 2 bit each one 1 bit for direction and 1 bit for position 78 | reg [dim-1:0] xDst, yDst, xSrc, ySrc; 79 | // FSM register 80 | reg [1:0] State; 81 | //for Simulation log 82 | integer Routing_Log; 83 | //INITIALIZATIONS 84 | initial 85 | begin 86 | req <= 0; EnableRoute <= 0; 87 | xSrc <= 0; ySrc <= 0; xDst <= 0; yDst <= 0; //x_Dir <= 0; y_Dir <= 0; 88 | req <= 0; 89 | dataBuf <= 0; 90 | Temp <= 0; 91 | State <= Idle; 92 | reqOutCntr <= 0; 93 | Routing_Log = $fopen("Routing_Log.txt","w"); 94 | $fdisplay(Routing_Log, " Routing_Log "); 95 | end 96 | // ------------------------ instantiation Devices --------------------------- // 97 | // ----------------------- Sequential Logic -------------------------------- // 98 | 99 | //always @(*) 100 | //begin 101 | // $fdisplay(Routing_Log, $time, " ; %b ;%d ", PacketIn,routerNo); 102 | // xDst = PacketIn[dataWidth-1:dataWidth-dim]; //31:30 103 | // yDst = PacketIn[dataWidth-dim-1:dataWidth-(dim*2)]; //29:28 104 | // xSrc = PacketIn[dataWidth-(dim*2)-1:dataWidth-(dim*3)]; //27:26 105 | // ySrc = PacketIn[dataWidth-(dim*3)-1:dataWidth-(dim*4)]; //25:24 106 | //end 107 | 108 | always @(posedge clk or negedge reset) 109 | begin 110 | if( !reset)//reset all registers 111 | begin 112 | req <= 0; 113 | dataBuf <= 0; 114 | Temp <= 0; 115 | State <= Idle; 116 | reqOutCntr <= 0; 117 | end 118 | else 119 | begin 120 | case (State)// FSM 121 | // Ideal state .. check if fifo buffer is empty or not , 122 | // if not empty .. Input Controller get one data Packet. 123 | Idle : 124 | begin 125 | if ( !empty ) 126 | begin 127 | State <= Read; 128 | req <= 1; 129 | end 130 | // else if (empty && (PacketIn != Temp) && (Temp != 0)) 131 | // begin 132 | // State <= Read; 133 | // EnableRoute <= 1; 134 | // end 135 | else 136 | begin 137 | req <= 0; 138 | //EnableRoute <= 0; 139 | State <= Idle; 140 | end 141 | 142 | end//Idle 143 | // read data Packet ..extract source and destnation 144 | Read : 145 | begin 146 | if ( gnt )// | EnableRoute ) 147 | begin 148 | req <= 0; 149 | State <= Route; 150 | //EnableRoute <= 0; 151 | // if (PacketIn) 152 | // begin 153 | // State <= Route; 154 | //// xDst <= PacketIn[dataWidth-1:dataWidth-dim]; //31:30 155 | //// yDst <= PacketIn[dataWidth-dim-1:dataWidth-(dim*2)]; //29:28 156 | //// xSrc <= PacketIn[dataWidth-(dim*2)-1:dataWidth-(dim*3)]; //27:26 157 | //// ySrc <= PacketIn[dataWidth-(dim*3)-1:dataWidth-(dim*4)]; //25:24 158 | //// Temp[dataWidth-1:dataWidth-(dim*4)] <= PacketIn[dataWidth-1:dataWidth-(dim*4)]; 159 | //// Temp[dataWidth-(dim*4)-1:0] <= PacketIn[dataWidth-(dim*4)-1:0]; 160 | // end 161 | // else State <= Idle; 162 | end 163 | else 164 | begin 165 | req <= 0; 166 | State <= Read; 167 | end 168 | end//Read 169 | // Routing algorithm .. x-y algorithm 170 | Route : 171 | begin 172 | State <= Grant; 173 | dataBuf[dataWidth-1:dataWidth-(dim*4)] <= PacketIn[dataWidth-1:dataWidth-(dim*4)]; 174 | dataBuf[dataWidth-(dim*4)-1:0] <= PacketIn[dataWidth-(dim*4)-1:0]; 175 | // ######################## define direction ##################################### 176 | 177 | //if ( xDst[dim-2:0] > xSrc[ dim-2:0] ) // Optmaize compartor 178 | if ( PacketIn[dataWidth-2:dataWidth-dim] > PacketIn[dataWidth-(dim*2)-2:dataWidth-(dim*3)] ) // Optmaize compartor 179 | begin 180 | dataBuf[dataWidth-(dim*2)-1:dataWidth-(dim*3)] <= PacketIn[dataWidth-(dim*2)-1:dataWidth-(dim*3)]+1; 181 | dataBuf[dataWidth-(dim*3)-1:dataWidth-(dim*4)] <= PacketIn[dataWidth-(dim*3)-1:dataWidth-(dim*4)]; 182 | //if ( xDst[dim-1] ) // negative sign .. MSB 183 | if ( PacketIn[dataWidth-1] ) 184 | begin 185 | reqOutCntr[0] <= 1; // move east direction 186 | end 187 | else 188 | begin 189 | reqOutCntr[2] <= 1; // move west direction 190 | end 191 | end//end if 192 | // ######################## define direction ##################################### 193 | //// xDst <= PacketIn[dataWidth-1:dataWidth-dim]; //31:30 194 | //// yDst <= PacketIn[dataWidth-dim-1:dataWidth-(dim*2)]; //29:28 195 | //// xSrc <= PacketIn[dataWidth-(dim*2)-1:dataWidth-(dim*3)]; //27:26 196 | //// ySrc <= PacketIn[dataWidth-(dim*3)-1:dataWidth-(dim*4)]; //25:24 197 | else if ( PacketIn[dataWidth-dim-2:dataWidth-(dim*2)] > PacketIn[dataWidth-(dim*3)-2:dataWidth-(dim*4)] ) // Optmaize compartor 198 | //else if ( yDst[dim-2:0] > ySrc[dim-2:0] ) // Optmaize compartor 199 | begin 200 | dataBuf[dataWidth-(dim*2)-1:dataWidth-(dim*3)] <= PacketIn[dataWidth-(dim*2)-1:dataWidth-(dim*3)]; 201 | dataBuf[dataWidth-(dim*3)-1:dataWidth-(dim*4)] <= PacketIn[dataWidth-(dim*3)-1:dataWidth-(dim*4)]+1; 202 | //if ( yDst[dim-1] ) // negative sign ... MSB 203 | if ( PacketIn[dataWidth-dim-1] ) // negative sign ... MSB 204 | begin 205 | reqOutCntr[1] <= 1; // move north direction 206 | end 207 | else 208 | begin 209 | reqOutCntr[3] <= 1; // move south direction 210 | end 211 | end 212 | // ######################## define direction ##################################### 213 | else 214 | begin 215 | reqOutCntr[4] <= 1; //Local Port 216 | dataBuf[dataWidth-(dim*2)-1:dataWidth-(dim*3)] <= PacketIn[dataWidth-(dim*2)-1:dataWidth-(dim*3)]; 217 | dataBuf[dataWidth-(dim*3)-1:dataWidth-(dim*4)] <= PacketIn[dataWidth-(dim*3)-1:dataWidth-(dim*4)]; 218 | end 219 | end 220 | // Grant communication between Output controller and Input Controller 221 | // ------------------------------------------------------------------- // 222 | Grant : 223 | if ( gntOutCntr)// 224 | begin 225 | State <= Idle; 226 | reqOutCntr <= 0; 227 | end 228 | endcase 229 | end // reset 230 | end // always 231 | // ----------------------- Combinational Logic ------------------------------ // 232 | assign PacketOut = dataBuf; 233 | // --------------------------------------------------------------------------- // 234 | endmodule 235 | // ----------------------------- End of File --------------------------------- // 236 | -------------------------------------------------------------------------------- /OutputController.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | /* 4 | Company: 5 | Engineer: 6 | 7 | Create Date: 18:45:32 06/17/2013 8 | Design Name: 9 | Module Name: OutputController 10 | Project Name: 11 | Target Devices: 12 | Tool versions: 13 | Description: 14 | input data Packets from differents ports 15 | ports in order ( East(0) - North(1) - West(2) - South(3) - Local(4) ) 16 | North (1) 17 | | 18 | | 19 | East(0)---- Local(4) ---- West (2) 20 | | 21 | | 22 | South (3) 23 | 24 | 25 | Dependencies: 26 | 27 | Revision: 28 | Revision 0.01 - File Created 29 | Additional Comments: 30 | */ 31 | ////////////////////////////////////////////////////////////////////////////////// 32 | module OutputController( clk, reset, reqDnStr, gntDnStr, full, 33 | PacketInPort_0, PacketInPort_1, PacketInPort_2 , PacketInPort_3,PacketInPort_4, 34 | reqInCntr, gntInCntr, PacketOut ); 35 | // ------------------------ Parameter Declarations --------------------------- // 36 | parameter routerNo = 24; // change depends on mesh size 37 | parameter dataWidth = 32;// number of bits for data bus 38 | parameter SEND_REQ=1'b0, 39 | WAIT_GRANT=1'b1; 40 | // ------------------------ Inputs Declarations ------------------------------ // 41 | input clk; 42 | input reset; 43 | input gntDnStr;// grant from down Stram router 44 | input full;// indicator from FIFO buffer of down stream router .. if full = 1 else = 0 45 | input [dataWidth-1:0] PacketInPort_0, PacketInPort_1, PacketInPort_2, PacketInPort_3,PacketInPort_4; 46 | input [4:0] reqInCntr;// request bus from input controller to handle communication with other ports 47 | // ------------------------ Outputs Declarations ----------------------------- // 48 | output reqDnStr;// request to down Stram router 49 | output [dataWidth-1:0] PacketOut;// output data Packet form fifo 50 | output [4:0] gntInCntr;// grants to other ports 51 | // --------------------------- Wire Declarations ----------------------------- // 52 | wire clk; 53 | wire reset; 54 | wire gntDnStr;// grant from down Stram router 55 | wire full;// indicator from FIFO buffer of down stream router .. if full = 1 else = 0 56 | // input data Packet from fifo 57 | wire [dataWidth-1:0] PacketInPort_0, PacketInPort_1, PacketInPort_2, PacketInPort_3,PacketInPort_4; 58 | reg [dataWidth-1:0] PacketOut;// output data Packet to output Controller 59 | wire [4:0] reqInCntr;// request bus from input controller to handle communication with other ports 60 | wire [4:0] reqInCntr_wEn;// to handle enable signal to Arbiter 61 | wire [4:0] gntInCntr;// grants to other ports 62 | wire [2:0] select;// select wires between Mux and Arbiter 63 | // ------------------------ Registers Declarations --------------------------- // 64 | reg reqDnStr;// request to down Stram router 65 | //register to hold Packet out until makeing arbitration and grant 66 | wire [dataWidth-1:0] DataBuff; 67 | reg STATE; 68 | reg Enable_RRA;// Anding reqInCntr with Enable_RRA 69 | ///********* 70 | //assign anygrant = |gntInCntr;//(gnt[0] | gnt[1] | gnt[2] | gnt[3]) ;//--and anyrequest; 71 | //assign select = {anygrant, (gntInCntr[3] | gntInCntr[2]) , (gntInCntr[3] | gntInCntr[1])}; //& {,} 72 | assign select = { gntInCntr[4] ,(gntInCntr[3] | gntInCntr[2]) , (gntInCntr[3] | gntInCntr[1])}; //& {,} 73 | /* g4 g3 g2 g1 g0 s2 s1 s0 74 | 0 0 0 0 1 0 0 0 --> 75 | 0 0 0 1 0 0 0 1 -1-> | 76 | 0 0 1 0 0 0 1 0 | g1 or g3 77 | 0 1 0 0 0 0 1 1 -1-> | 78 | 1 0 0 0 0 1 0 0 79 | z z z z z 1 0 1 Don't Care 80 | z z z z z 1 1 0 Don't Care 81 | z z z z z 1 1 1 Don't Care 82 | */ 83 | assign reqInCntr_wEn = reqInCntr & {5{! full & Enable_RRA }};///{5{Enable_RRA}}; // 84 | //Initializations 85 | initial 86 | begin 87 | Enable_RRA <= 1; 88 | reqDnStr <= 0; 89 | PacketOut <= 0; 90 | STATE <= SEND_REQ; 91 | end 92 | // ----------------------- Sequential Logic -------------------------------- // 93 | always @(posedge clk or negedge reset) 94 | begin 95 | if( !reset)//reset all registers 96 | begin 97 | reqDnStr <= 0; 98 | PacketOut <= 0; 99 | STATE <= SEND_REQ; 100 | end 101 | else 102 | begin 103 | // handle request to down stream router 104 | case(STATE) 105 | SEND_REQ: 106 | begin 107 | // if ( ! full )//& (gntInCntr[0] | gntInCntr[1] | gntInCntr[2] | gntInCntr[3]) ) 108 | // begin 109 | // if (gntInCntr[0] | gntInCntr[1] | gntInCntr[2] | gntInCntr[3]) 110 | // begin 111 | // STATE <= WAIT_GRANT; 112 | // reqDnStr <= 1; 113 | // PacketOut <= DataBuff; 114 | // Enable_RRA <= 0; 115 | // end 116 | // end 117 | // else //if(full) 118 | // begin 119 | // STATE <= SEND_REQ; 120 | // Enable_RRA <= 1; 121 | // end 122 | // end 123 | if ( ! full & (gntInCntr[0] | gntInCntr[1] | gntInCntr[2] | gntInCntr[3] | gntInCntr[4]) ) 124 | begin 125 | STATE <= WAIT_GRANT; 126 | reqDnStr <= 1; 127 | PacketOut <= DataBuff; 128 | Enable_RRA <= 0; 129 | end 130 | else if(full) 131 | begin 132 | STATE <= SEND_REQ; 133 | Enable_RRA <= 0; 134 | end 135 | else 136 | Enable_RRA <= 1; 137 | end 138 | WAIT_GRANT: 139 | begin 140 | if ( gntDnStr ) 141 | begin 142 | STATE <= SEND_REQ; 143 | reqDnStr <= 0; 144 | Enable_RRA <= 1; 145 | end 146 | else 147 | begin 148 | STATE <= WAIT_GRANT; 149 | end 150 | end 151 | endcase 152 | end//else 153 | end // always 154 | //assign PacketOut = DataBuff; 155 | // ----------------------- Combinational Logic ------------------------------ // 156 | // --------------------------------------------------------------------------- // 157 | // ------------------------ instantiation Devices --------------------------- // 158 | /* instantiate round robin arbiter */ 159 | RR_arbiter roundRobinArbiter 160 | ( 161 | .clock(clk), 162 | .rst(reset), 163 | .req4(reqInCntr_wEn[4]), 164 | .req3(reqInCntr_wEn[3]), 165 | .req2(reqInCntr_wEn[2]), 166 | .req1(reqInCntr_wEn[1]), 167 | .req0(reqInCntr_wEn[0]), 168 | .gnt4(gntInCntr[4]), 169 | .gnt3(gntInCntr[3]), 170 | .gnt2(gntInCntr[2]), 171 | .gnt1(gntInCntr[1]), 172 | .gnt0(gntInCntr[0]) 173 | ); 174 | 175 | // --------------------------------------------------------------------------- // 176 | /* instantiate mux */ 177 | mux # (.dataWidth(dataWidth)) selectPort 178 | ( 179 | .PacketInPort_0(PacketInPort_0), 180 | .PacketInPort_1(PacketInPort_1), 181 | .PacketInPort_2(PacketInPort_2), 182 | .PacketInPort_3(PacketInPort_3), 183 | .PacketInPort_4(PacketInPort_4), 184 | .sel(select), 185 | .PacketOut(DataBuff) 186 | ); 187 | endmodule 188 | // ----------------------------- End of File --------------------------------- // -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verilog-Bsed-NoC-Simulator 2 | 3 | Verilog-Bsed-NoC-Simulator 4 | 5 | If you use our Open Source Verilog-Bsed-NoC-Simulator in your research, we would appreciate the following citation in any publications to which it has contributed: 6 | 7 | 1. H. El-Sayed, M. Ragab, M. S. Sayed and V. Goulart, "Hardware implementation and evaluation of the Flexible router architecture for NoCs," Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on, Abu Dhabi, 2013, pp. 621-624. 8 | doi: 10.1109/ICECS.2013.6815491 9 | 10 | 2. H. Hassan, A. Shalaby and H. Kim, "DPSB: Dual port shared buffer mechanism for efficient buffer utilization in Network on Chip routers," 2015 International SoC Design Conference (ISOCC), Gyungju, 2015, pp. 135-136. 11 | doi: 10.1109/ISOCC.2015.7401695 12 | 13 | 14 | -------------------------------------------------------------------------------- /RR_arbiter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:06:04 06/17/2013 7 | // Design Name: 8 | // Module Name: RR_arbiter2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | /* 23 | A VERIOG-HDL IMPLEMENTATION OF VIRTUAL CHANNELS IN A NETWORK-ON-CHIP ROUTER 24 | A Thesis by SUNGHO PARK 25 | Fig. 52. Verilog code of a round-robin arbiter in a generic and ViChaR router 26 | Main Ref: "Arbiters: Design Ideas and Coding Styles" 27 | Page 19 -- Listing 12 - mask_expand round-robin arbiter 28 | */ 29 | 30 | module RR_arbiter( 31 | clock, 32 | rst, 33 | req4, 34 | req3, 35 | req2, 36 | req1, 37 | req0, 38 | gnt4, 39 | gnt3, 40 | gnt2, 41 | gnt1, 42 | gnt0 43 | ); 44 | parameter [4:0] N = 5'd5; 45 | input clock; 46 | input rst; 47 | input req4; 48 | input req3; 49 | input req2; 50 | input req1; 51 | input req0; 52 | output gnt4; 53 | output gnt3; 54 | output gnt2; 55 | output gnt1; 56 | output gnt0; 57 | //Declarations 58 | reg [N-1:0] pointer_reg;//priority vector 59 | wire [N-1:0] req;//request vector 60 | // ----------------------- Combinational Logic ------------------------------ // 61 | assign req = {req4,req3, req2, req1, req0}; 62 | //Declarations 63 | wire [N-1:0] gnt; 64 | // ----------------------- Combinational Logic ------------------------------ // 65 | assign gnt4 = gnt[4]; 66 | assign gnt3 = gnt[3]; 67 | assign gnt2 = gnt[2]; 68 | assign gnt1 = gnt[1]; 69 | assign gnt0 = gnt[0]; 70 | 71 | //************ Masked Path -- FPA******** 72 | // Simple priority arbitration for masked portion 73 | //Declarations 74 | wire [N-1:0] req_masked; 75 | wire [N-1:0] mask_higher_pri_regs; 76 | wire [N-1:0] gnt_masked; 77 | // ----------------------- Combinational Logic ------------------------------ // 78 | assign req_masked = req & pointer_reg; // masking 79 | assign mask_higher_pri_regs[N-1:1] = mask_higher_pri_regs[N-2:0] | req_masked[N-2:0]; //shifting 80 | assign mask_higher_pri_regs[0] = 1'b0; 81 | assign gnt_masked[N-1:0] = req_masked[N-1:0] & ~mask_higher_pri_regs[N-1:0]; //granting 82 | 83 | //********* Un Masked Path -- FPA ********** 84 | // Simple priority arbitration for unmasked portion 85 | //Declarations 86 | wire [N-1:0] unmask_higher_pri_regs; 87 | wire [N-1:0] gnt_unmasked; 88 | // ----------------------- Combinational Logic ------------------------------ // 89 | assign unmask_higher_pri_regs[N-1:1] = unmask_higher_pri_regs[N-2:0] | req[N-2:0]; 90 | assign unmask_higher_pri_regs[0] = 1'b0; 91 | assign gnt_unmasked[N-1:0] = req[N-1:0] & ~unmask_higher_pri_regs[N-1:0]; 92 | 93 | // Use grant_masked if there is any there, otherwise use grant_unmasked. 94 | //Declarations 95 | wire no_req_masked; 96 | // ----------------------- Combinational Logic ------------------------------ // 97 | assign no_req_masked = ~(|req_masked); // not OR tree 98 | assign gnt = ({N{no_req_masked}} & gnt_unmasked) | gnt_masked; //Red MUX 99 | 100 | //*********** Sequential Logic ****************** 101 | // Pointer update 102 | always @(negedge rst or posedge clock) 103 | begin 104 | if(!rst) 105 | begin 106 | pointer_reg <= {N{1'b1}}; 107 | end 108 | else 109 | begin 110 | if(|req_masked) pointer_reg <= mask_higher_pri_regs;// Which arbiter was used? 111 | else if(|req) pointer_reg <= unmask_higher_pri_regs;// Only update if there's a req 112 | else pointer_reg <= pointer_reg; 113 | end 114 | end 115 | 116 | endmodule 117 | -------------------------------------------------------------------------------- /mux.v: -------------------------------------------------------------------------------- 1 | // --------------------------------------------------------------------------- // 2 | /* 3 | FILE NAME: mux.v 4 | 5 | VERSION: $Revision: 1.0 $ 6 | 7 | AUTHOR(S): Ahmed Shalaby 8 | 9 | DATE CREATED: 31/08/2011 10 | 11 | DESCRIPTION: This file implements mux used by output controller. 12 | */ 13 | //********************************************************* 14 | // --------------------------------------------------------------------------- // 15 | module mux ( PacketInPort_0, PacketInPort_1, PacketInPort_2 , PacketInPort_3, 16 | PacketInPort_4, sel, PacketOut ); 17 | // --------------------------------------------------------------------------- // 18 | // ------------------------ Parameter Declarations --------------------------- // 19 | // number of bits for data bus 20 | parameter dataWidth = 100; 21 | // --------------------------------------------------------------------------- // 22 | // ------------------------ Inputs Declarations ------------------------------ // 23 | // input data packet from all other ports and Network Interface to Mux 24 | input [dataWidth-1:0] PacketInPort_0,PacketInPort_1,PacketInPort_2,PacketInPort_3,PacketInPort_4; 25 | // select input 26 | input [2:0] sel; 27 | // --------------------------------------------------------------------------- // 28 | // ------------------------ Outputs Declarations ----------------------------- // 29 | // output data packet form Mux 30 | output [dataWidth-1:0] PacketOut; 31 | // --------------------------------------------------------------------------- // 32 | // --------------------------- Wire Declarations ----------------------------- // 33 | // input data packet from all other ports and Network Interface to Mux 34 | wire [dataWidth-1:0] PacketInPort_0,PacketInPort_1,PacketInPort_2,PacketInPort_3,PacketInPort_4; 35 | // select input 36 | wire [2:0] sel; 37 | // --------------------------------------------------------------------------- // 38 | // ------------------------ Registers Declarations --------------------------- // 39 | // output data packet form Mux 40 | reg [dataWidth-1:0] PacketOut; 41 | // --------------------------------------------------------------------------- // 42 | // ------------------------ instantiation Devices --------------------------- // 43 | // --------------------------------------------------------------------------- // 44 | // ----------------------- Sequential Logic -------------------------------- // 45 | always @ (sel or PacketInPort_0 or PacketInPort_1 or 46 | PacketInPort_2 or PacketInPort_3 or PacketInPort_4 ) 47 | begin 48 | case (sel) 49 | // depend on sel , output port connected to selected input port. 50 | // 4 ports .. NI + 3 other ports than Input 51 | 3'b000: PacketOut = PacketInPort_0; 52 | 3'b001: PacketOut = PacketInPort_1; 53 | 3'b010: PacketOut = PacketInPort_2; 54 | 3'b011: PacketOut = PacketInPort_3; 55 | 3'b100: PacketOut = PacketInPort_4; 56 | default: PacketOut = 0; // Don't Care 57 | //default: PacketOut = 32'hxxxx_xxxx; //xxxx_xxxx Don't Care 58 | //32'hXXXX_XXXX 59 | endcase 60 | end 61 | // ----------------------- Combinational Logic ------------------------------ // 62 | // --------------------------------------------------------------------------- // 63 | endmodule 64 | // ----------------------------- End of File --------------------------------- // 65 | 66 | ///********************************************************************** 67 | // * Date: Aug. 28, 1999 68 | // * File: Mux 4 to 1.v (440 Examples) 69 | // * 70 | // * Behavioral Model of a 4 to 1 MUX (16 data inputs) 71 | //http://www.cecs.csulb.edu/~rallison/pdf/Mux_4_to_1.pdf 72 | // **********************************************************************/ 73 | ////********************************************************* 74 | // module mux_4to1(Y, A, B, C, D, sel); 75 | ////********************************************************* 76 | // output [15:0] Y; 77 | // input [15:0] A, B, C, D; 78 | // input [1:0] sel; 79 | // reg [15:0] Y; 80 | // always @(A or B or C or D or sel) 81 | // case ( sel ) 82 | // 2'b00: Y = A; 83 | // 2'b01: Y = B; 84 | // 2'b10: Y = C; 85 | // 2'b11: Y = D; 86 | // default: Y = 16'hxxxx; 87 | // endcase 88 | // endmodule 89 | 90 | /************************************************************************ 91 | * Date: Aug. 16, 2006 92 | * File: Test Mux 4 to 1.v (440 Examples) 93 | * 94 | * Testbench to generate some stimulus and display the results for the 95 | * Mux 4 to 1 module -- with 4 sets of 16 data inputs and 2 select lines 96 | ************************************************************************/ 97 | ////********************************************************* 98 | //module Test_mux_4to1; 99 | ////********************************************************* 100 | //wire [15:0] MuxOut; //use wire data type for outputs from instantiated module 101 | //reg [15:0] A, B, C, D; //use reg data type for all inputs 102 | //reg [1:0] sel; // to the instantiated module 103 | //reg clk; //to be used for timing of WHEN to change input values 104 | //// Instantiate the MUX (named DUT {device under test}) 105 | // mux_4to1 DUT(MuxOut, A, B, C, D, sel); 106 | ////This block generates a clock pulse with a 20 ns period 107 | //always 108 | // #10 clk = ~clk; 109 | ////This initial block will provide values for the inputs 110 | //// of the mux so that both inputs/outputs can be displayed 111 | //initial begin 112 | //$timeformat(-9, 1, " ns", 6); 113 | //clk = 1'b0; // time = 0 114 | //A = 16'hAAAA; B = 16'h5555; C = 16'h00FF; D = 16'hFF00; sel = 2'b00; 115 | //@(negedge clk) //will wait for next negative edge of the clock (t=20) 116 | // A = 16'h0000; 117 | //@(negedge clk) //will wait for next negative edge of the clock (t=40) 118 | // sel = 2'b01; 119 | //@(negedge clk) //will wait for next negative edge of the clock (t=60) 120 | // B = 16'hFFFF; 121 | //@(negedge clk) //will wait for next negative edge of the clock (t=80) 122 | // sel = 2'b10; 123 | // A = 16'hA5A5; 124 | //@(negedge clk) //will wait for next negative edge of the clock (t=100) 125 | // sel = 2'b00; 126 | //@(negedge clk) //will wait for next negative edge of the clock (t=120) 127 | // $finish; // to shut down the simulation 128 | //end //initial 129 | //// this block is sensitive to changes on ANY of the inputs and will 130 | //// then display both the inputs and corresponding output 131 | //always @(A or B or C or D or sel) 132 | // #1 $display("At t=%t / sel=%b A=%h B=%h C=%h D=%h / MuxOut=%h", 133 | // $time, sel, A, B, C, D, MuxOut); 134 | //endmodule -------------------------------------------------------------------------------- /ram.v: -------------------------------------------------------------------------------- 1 | // --------------------------------------------------------------------------- // 2 | module ram (clk,reset, writeEn,readEn,writeAddr,readAddr,dataIn,dataOut); 3 | // -------------------------- Parameters declarations ------------------------ // 4 | // data bits number 5 | parameter dataWidth = 100; 6 | // address bits number 7 | parameter addressWidth = 4; 8 | // ------------------- Clock and Reset signal declarations ------------------- // 9 | // clock input 10 | input clk; 11 | // reset input 12 | input reset; 13 | // --------------------------- Input Ports ----------------------------------- // 14 | // write enable; 15 | input writeEn; 16 | // read enable 17 | input readEn; 18 | // writting address .. 19 | input [addressWidth-1:0] writeAddr; 20 | // reading address 21 | input [addressWidth-1:0] readAddr; 22 | // Input data to be written 23 | input [dataWidth-1:0] dataIn; 24 | // ------------------------------ Output Ports ------------------------------- // 25 | // output data to be read 26 | output [dataWidth-1:0] dataOut; 27 | // ------------------------ Register Declarations ---------------------------- // 28 | // ram is an array with ( width = dataWidth & size 2^addressWidth-1 ) 29 | reg [dataWidth-1:0] ram[2**addressWidth-1:0]; 30 | reg [dataWidth-1:0] dataOut; 31 | // ------------------ Wire Declarations--------------------------------------- // 32 | wire [dataWidth-1:0] dataIn; 33 | // -------------------------------- Logic ------------------------------------ // 34 | //initial 35 | // begin 36 | // dataOut <= 0; 37 | // end 38 | always @(posedge clk or negedge reset) 39 | begin 40 | // ---------------------------- reset all registers ---------------------- // 41 | if( !reset) 42 | begin 43 | dataOut <= 0; 44 | end 45 | // --------------------------------------------------------------------- // 46 | else 47 | // --------------------------------------------------------------------- // 48 | begin 49 | // ---------------------------- write process ------------------------- // 50 | if (writeEn) 51 | ram[writeAddr] <= dataIn; 52 | // --------------------------------------------------------------------- // 53 | // ----------------------------- read process -------------------------- // 54 | if (readEn) 55 | dataOut <= ram[readAddr]; 56 | // --------------------------------------------------------------------- // 57 | end 58 | // ----------------------------------------------------------------------- // 59 | end 60 | // ------------------------------------------------------------------------- // 61 | endmodule 62 | // --------------------------------------------------------------------------- // --------------------------------------------------------------------------------