├── .gitignore
├── CORE
├── core_cm3.h
├── startup_stm32f10x_cl.s
├── startup_stm32f10x_hd.s
├── startup_stm32f10x_hd_vl.s
├── startup_stm32f10x_ld.s
├── startup_stm32f10x_ld_vl.s
├── startup_stm32f10x_md.s
├── startup_stm32f10x_md_vl.s
├── startup_stm32f10x_xl.s
├── stm32_flash.ld
├── stm32f10x.h
├── stm32f10x_conf.h
├── stm32f10x_it.c
├── stm32f10x_it.h
├── system_stm32f10x.c
└── system_stm32f10x.h
├── HARDWARE
├── delay.c
├── delay.h
├── led.c
├── led.h
├── sys.h
├── usart.c
└── usart.h
├── Makefile
├── OSAL
├── application
│ ├── osal_main.c
│ └── serial_task.c
├── hal
│ └── timer.c
├── include
│ ├── application.h
│ ├── osal.h
│ ├── osal_event.h
│ ├── osal_memory.h
│ ├── osal_msg.h
│ ├── osal_timer.h
│ ├── timer.h
│ └── type.h
├── osal
│ ├── osal.c
│ ├── osal_event.c
│ ├── osal_memory.c
│ ├── osal_msg.c
│ └── osal_timer.c
├── readme.txt
└── 动态内存管理拓展.txt
├── README.txt
├── STM32F10x_FWLib
├── inc
│ ├── misc.h
│ ├── stm32f10x_adc.h
│ ├── stm32f10x_bkp.h
│ ├── stm32f10x_can.h
│ ├── stm32f10x_cec.h
│ ├── stm32f10x_crc.h
│ ├── stm32f10x_dac.h
│ ├── stm32f10x_dbgmcu.h
│ ├── stm32f10x_dma.h
│ ├── stm32f10x_exti.h
│ ├── stm32f10x_flash.h
│ ├── stm32f10x_fsmc.h
│ ├── stm32f10x_gpio.h
│ ├── stm32f10x_i2c.h
│ ├── stm32f10x_iwdg.h
│ ├── stm32f10x_pwr.h
│ ├── stm32f10x_rcc.h
│ ├── stm32f10x_rtc.h
│ ├── stm32f10x_sdio.h
│ ├── stm32f10x_spi.h
│ ├── stm32f10x_tim.h
│ ├── stm32f10x_usart.h
│ └── stm32f10x_wwdg.h
└── src
│ ├── misc.c
│ ├── stm32f10x_adc.c
│ ├── stm32f10x_bkp.c
│ ├── stm32f10x_can.c
│ ├── stm32f10x_cec.c
│ ├── stm32f10x_crc.c
│ ├── stm32f10x_dac.c
│ ├── stm32f10x_dbgmcu.c
│ ├── stm32f10x_dma.c
│ ├── stm32f10x_exti.c
│ ├── stm32f10x_flash.c
│ ├── stm32f10x_fsmc.c
│ ├── stm32f10x_gpio.c
│ ├── stm32f10x_i2c.c
│ ├── stm32f10x_iwdg.c
│ ├── stm32f10x_pwr.c
│ ├── stm32f10x_rcc.c
│ ├── stm32f10x_rtc.c
│ ├── stm32f10x_sdio.c
│ ├── stm32f10x_spi.c
│ ├── stm32f10x_tim.c
│ ├── stm32f10x_usart.c
│ └── stm32f10x_wwdg.c
├── tags
└── 全局宏定义.txt
/.gitignore:
--------------------------------------------------------------------------------
1 | # Prerequisites
2 | *.d
3 |
4 | # Object files
5 | *.o
6 | *.ko
7 | *.obj
8 | *.elf
9 |
10 | # Linker output
11 | *.ilk
12 | *.map
13 | *.exp
14 |
15 | # Precompiled Headers
16 | *.gch
17 | *.pch
18 |
19 | # Libraries
20 | *.lib
21 | *.a
22 | *.la
23 | *.lo
24 |
25 | # Shared objects (inc. Windows DLLs)
26 | *.dll
27 | *.so
28 | *.so.*
29 | *.dylib
30 |
31 | # Executables
32 | *.exe
33 | *.out
34 | *.app
35 | *.i*86
36 | *.x86_64
37 | *.hex
38 |
39 | # Debug files
40 | *.dSYM/
41 | *.su
42 | *.idb
43 | *.pdb
44 |
45 | # Kernel Module Compile Results
46 | *.mod*
47 | *.cmd
48 | .tmp_versions/
49 | modules.order
50 | Module.symvers
51 | Mkfile.old
52 | dkms.conf
53 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_ld.s:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file startup_stm32f10x_ld.s
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief STM32F10x Low Density Devices vector table for Atollic toolchain.
8 | * This module performs:
9 | * - Set the initial SP
10 | * - Set the initial PC == Reset_Handler,
11 | * - Set the vector table entries with the exceptions ISR address.
12 | * - Configure the clock system
13 | * - Branches to main in the C library (which eventually
14 | * calls main()).
15 | * After Reset the Cortex-M3 processor is in Thread mode,
16 | * priority is Privileged, and the Stack is set to Main.
17 | ******************************************************************************
18 | * @attention
19 | *
20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
26 | *
27 | * © COPYRIGHT 2011 STMicroelectronics
28 | ******************************************************************************
29 | */
30 |
31 | .syntax unified
32 | .cpu cortex-m3
33 | .fpu softvfp
34 | .thumb
35 |
36 | .global g_pfnVectors
37 | .global Default_Handler
38 |
39 | /* start address for the initialization values of the .data section.
40 | defined in linker script */
41 | .word _sidata
42 | /* start address for the .data section. defined in linker script */
43 | .word _sdata
44 | /* end address for the .data section. defined in linker script */
45 | .word _edata
46 | /* start address for the .bss section. defined in linker script */
47 | .word _sbss
48 | /* end address for the .bss section. defined in linker script */
49 | .word _ebss
50 |
51 | .equ BootRAM, 0xF108F85F
52 | /**
53 | * @brief This is the code that gets called when the processor first
54 | * starts execution following a reset event. Only the absolutely
55 | * necessary set is performed, after which the application
56 | * supplied main() routine is called.
57 | * @param None
58 | * @retval : None
59 | */
60 |
61 | .section .text.Reset_Handler
62 | .weak Reset_Handler
63 | .type Reset_Handler, %function
64 | Reset_Handler:
65 |
66 | /* Copy the data segment initializers from flash to SRAM */
67 | movs r1, #0
68 | b LoopCopyDataInit
69 |
70 | CopyDataInit:
71 | ldr r3, =_sidata
72 | ldr r3, [r3, r1]
73 | str r3, [r0, r1]
74 | adds r1, r1, #4
75 |
76 | LoopCopyDataInit:
77 | ldr r0, =_sdata
78 | ldr r3, =_edata
79 | adds r2, r0, r1
80 | cmp r2, r3
81 | bcc CopyDataInit
82 | ldr r2, =_sbss
83 | b LoopFillZerobss
84 | /* Zero fill the bss segment. */
85 | FillZerobss:
86 | movs r3, #0
87 | str r3, [r2], #4
88 |
89 | LoopFillZerobss:
90 | ldr r3, = _ebss
91 | cmp r2, r3
92 | bcc FillZerobss
93 |
94 | /* Call the clock system intitialization function.*/
95 | bl SystemInit
96 | /* Call static constructors */
97 | bl __libc_init_array
98 | /* Call the application's entry point.*/
99 | bl main
100 | bx lr
101 | .size Reset_Handler, .-Reset_Handler
102 |
103 | /**
104 | * @brief This is the code that gets called when the processor receives an
105 | * unexpected interrupt. This simply enters an infinite loop, preserving
106 | * the system state for examination by a debugger.
107 | *
108 | * @param None
109 | * @retval : None
110 | */
111 | .section .text.Default_Handler,"ax",%progbits
112 | Default_Handler:
113 | Infinite_Loop:
114 | b Infinite_Loop
115 | .size Default_Handler, .-Default_Handler
116 | /******************************************************************************
117 | *
118 | * The minimal vector table for a Cortex M3. Note that the proper constructs
119 | * must be placed on this to ensure that it ends up at physical address
120 | * 0x0000.0000.
121 | *
122 | ******************************************************************************/
123 | .section .isr_vector,"a",%progbits
124 | .type g_pfnVectors, %object
125 | .size g_pfnVectors, .-g_pfnVectors
126 |
127 |
128 | g_pfnVectors:
129 | .word _estack
130 | .word Reset_Handler
131 | .word NMI_Handler
132 | .word HardFault_Handler
133 | .word MemManage_Handler
134 | .word BusFault_Handler
135 | .word UsageFault_Handler
136 | .word 0
137 | .word 0
138 | .word 0
139 | .word 0
140 | .word SVC_Handler
141 | .word DebugMon_Handler
142 | .word 0
143 | .word PendSV_Handler
144 | .word SysTick_Handler
145 | .word WWDG_IRQHandler
146 | .word PVD_IRQHandler
147 | .word TAMPER_IRQHandler
148 | .word RTC_IRQHandler
149 | .word FLASH_IRQHandler
150 | .word RCC_IRQHandler
151 | .word EXTI0_IRQHandler
152 | .word EXTI1_IRQHandler
153 | .word EXTI2_IRQHandler
154 | .word EXTI3_IRQHandler
155 | .word EXTI4_IRQHandler
156 | .word DMA1_Channel1_IRQHandler
157 | .word DMA1_Channel2_IRQHandler
158 | .word DMA1_Channel3_IRQHandler
159 | .word DMA1_Channel4_IRQHandler
160 | .word DMA1_Channel5_IRQHandler
161 | .word DMA1_Channel6_IRQHandler
162 | .word DMA1_Channel7_IRQHandler
163 | .word ADC1_2_IRQHandler
164 | .word USB_HP_CAN1_TX_IRQHandler
165 | .word USB_LP_CAN1_RX0_IRQHandler
166 | .word CAN1_RX1_IRQHandler
167 | .word CAN1_SCE_IRQHandler
168 | .word EXTI9_5_IRQHandler
169 | .word TIM1_BRK_IRQHandler
170 | .word TIM1_UP_IRQHandler
171 | .word TIM1_TRG_COM_IRQHandler
172 | .word TIM1_CC_IRQHandler
173 | .word TIM2_IRQHandler
174 | .word TIM3_IRQHandler
175 | .word 0
176 | .word I2C1_EV_IRQHandler
177 | .word I2C1_ER_IRQHandler
178 | .word 0
179 | .word 0
180 | .word SPI1_IRQHandler
181 | .word 0
182 | .word USART1_IRQHandler
183 | .word USART2_IRQHandler
184 | .word 0
185 | .word EXTI15_10_IRQHandler
186 | .word RTCAlarm_IRQHandler
187 | .word USBWakeUp_IRQHandler
188 | .word 0
189 | .word 0
190 | .word 0
191 | .word 0
192 | .word 0
193 | .word 0
194 | .word 0
195 | .word BootRAM /* @0x108. This is for boot in RAM mode for
196 | STM32F10x Low Density devices.*/
197 |
198 | /*******************************************************************************
199 | *
200 | * Provide weak aliases for each Exception handler to the Default_Handler.
201 | * As they are weak aliases, any function with the same name will override
202 | * this definition.
203 | *
204 | *******************************************************************************/
205 |
206 | .weak NMI_Handler
207 | .thumb_set NMI_Handler,Default_Handler
208 |
209 | .weak HardFault_Handler
210 | .thumb_set HardFault_Handler,Default_Handler
211 |
212 | .weak MemManage_Handler
213 | .thumb_set MemManage_Handler,Default_Handler
214 |
215 | .weak BusFault_Handler
216 | .thumb_set BusFault_Handler,Default_Handler
217 |
218 | .weak UsageFault_Handler
219 | .thumb_set UsageFault_Handler,Default_Handler
220 |
221 | .weak SVC_Handler
222 | .thumb_set SVC_Handler,Default_Handler
223 |
224 | .weak DebugMon_Handler
225 | .thumb_set DebugMon_Handler,Default_Handler
226 |
227 | .weak PendSV_Handler
228 | .thumb_set PendSV_Handler,Default_Handler
229 |
230 | .weak SysTick_Handler
231 | .thumb_set SysTick_Handler,Default_Handler
232 |
233 | .weak WWDG_IRQHandler
234 | .thumb_set WWDG_IRQHandler,Default_Handler
235 |
236 | .weak PVD_IRQHandler
237 | .thumb_set PVD_IRQHandler,Default_Handler
238 |
239 | .weak TAMPER_IRQHandler
240 | .thumb_set TAMPER_IRQHandler,Default_Handler
241 |
242 | .weak RTC_IRQHandler
243 | .thumb_set RTC_IRQHandler,Default_Handler
244 |
245 | .weak FLASH_IRQHandler
246 | .thumb_set FLASH_IRQHandler,Default_Handler
247 |
248 | .weak RCC_IRQHandler
249 | .thumb_set RCC_IRQHandler,Default_Handler
250 |
251 | .weak EXTI0_IRQHandler
252 | .thumb_set EXTI0_IRQHandler,Default_Handler
253 |
254 | .weak EXTI1_IRQHandler
255 | .thumb_set EXTI1_IRQHandler,Default_Handler
256 |
257 | .weak EXTI2_IRQHandler
258 | .thumb_set EXTI2_IRQHandler,Default_Handler
259 |
260 | .weak EXTI3_IRQHandler
261 | .thumb_set EXTI3_IRQHandler,Default_Handler
262 |
263 | .weak EXTI4_IRQHandler
264 | .thumb_set EXTI4_IRQHandler,Default_Handler
265 |
266 | .weak DMA1_Channel1_IRQHandler
267 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
268 |
269 | .weak DMA1_Channel2_IRQHandler
270 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
271 |
272 | .weak DMA1_Channel3_IRQHandler
273 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
274 |
275 | .weak DMA1_Channel4_IRQHandler
276 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
277 |
278 | .weak DMA1_Channel5_IRQHandler
279 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
280 |
281 | .weak DMA1_Channel6_IRQHandler
282 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
283 |
284 | .weak DMA1_Channel7_IRQHandler
285 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
286 |
287 | .weak ADC1_2_IRQHandler
288 | .thumb_set ADC1_2_IRQHandler,Default_Handler
289 |
290 | .weak USB_HP_CAN1_TX_IRQHandler
291 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
292 |
293 | .weak USB_LP_CAN1_RX0_IRQHandler
294 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
295 |
296 | .weak CAN1_RX1_IRQHandler
297 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler
298 |
299 | .weak CAN1_SCE_IRQHandler
300 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler
301 |
302 | .weak EXTI9_5_IRQHandler
303 | .thumb_set EXTI9_5_IRQHandler,Default_Handler
304 |
305 | .weak TIM1_BRK_IRQHandler
306 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler
307 |
308 | .weak TIM1_UP_IRQHandler
309 | .thumb_set TIM1_UP_IRQHandler,Default_Handler
310 |
311 | .weak TIM1_TRG_COM_IRQHandler
312 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
313 |
314 | .weak TIM1_CC_IRQHandler
315 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
316 |
317 | .weak TIM2_IRQHandler
318 | .thumb_set TIM2_IRQHandler,Default_Handler
319 |
320 | .weak TIM3_IRQHandler
321 | .thumb_set TIM3_IRQHandler,Default_Handler
322 |
323 | .weak I2C1_EV_IRQHandler
324 | .thumb_set I2C1_EV_IRQHandler,Default_Handler
325 |
326 | .weak I2C1_ER_IRQHandler
327 | .thumb_set I2C1_ER_IRQHandler,Default_Handler
328 |
329 | .weak SPI1_IRQHandler
330 | .thumb_set SPI1_IRQHandler,Default_Handler
331 |
332 | .weak USART1_IRQHandler
333 | .thumb_set USART1_IRQHandler,Default_Handler
334 |
335 | .weak USART2_IRQHandler
336 | .thumb_set USART2_IRQHandler,Default_Handler
337 |
338 | .weak EXTI15_10_IRQHandler
339 | .thumb_set EXTI15_10_IRQHandler,Default_Handler
340 |
341 | .weak RTCAlarm_IRQHandler
342 | .thumb_set RTCAlarm_IRQHandler,Default_Handler
343 |
344 | .weak USBWakeUp_IRQHandler
345 | .thumb_set USBWakeUp_IRQHandler,Default_Handler
346 |
347 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
348 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_ld_vl.s:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file startup_stm32f10x_ld_vl.s
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain.
8 | * This module performs:
9 | * - Set the initial SP
10 | * - Set the initial PC == Reset_Handler,
11 | * - Set the vector table entries with the exceptions ISR address
12 | * - Configure the clock system
13 | * - Branches to main in the C library (which eventually
14 | * calls main()).
15 | * After Reset the Cortex-M3 processor is in Thread mode,
16 | * priority is Privileged, and the Stack is set to Main.
17 | ******************************************************************************
18 | * @attention
19 | *
20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
26 | *
27 | * © COPYRIGHT 2011 STMicroelectronics
28 | ******************************************************************************
29 | */
30 |
31 | .syntax unified
32 | .cpu cortex-m3
33 | .fpu softvfp
34 | .thumb
35 |
36 | .global g_pfnVectors
37 | .global Default_Handler
38 |
39 | /* start address for the initialization values of the .data section.
40 | defined in linker script */
41 | .word _sidata
42 | /* start address for the .data section. defined in linker script */
43 | .word _sdata
44 | /* end address for the .data section. defined in linker script */
45 | .word _edata
46 | /* start address for the .bss section. defined in linker script */
47 | .word _sbss
48 | /* end address for the .bss section. defined in linker script */
49 | .word _ebss
50 |
51 | .equ BootRAM, 0xF108F85F
52 | /**
53 | * @brief This is the code that gets called when the processor first
54 | * starts execution following a reset event. Only the absolutely
55 | * necessary set is performed, after which the application
56 | * supplied main() routine is called.
57 | * @param None
58 | * @retval : None
59 | */
60 |
61 | .section .text.Reset_Handler
62 | .weak Reset_Handler
63 | .type Reset_Handler, %function
64 | Reset_Handler:
65 |
66 | /* Copy the data segment initializers from flash to SRAM */
67 | movs r1, #0
68 | b LoopCopyDataInit
69 |
70 | CopyDataInit:
71 | ldr r3, =_sidata
72 | ldr r3, [r3, r1]
73 | str r3, [r0, r1]
74 | adds r1, r1, #4
75 |
76 | LoopCopyDataInit:
77 | ldr r0, =_sdata
78 | ldr r3, =_edata
79 | adds r2, r0, r1
80 | cmp r2, r3
81 | bcc CopyDataInit
82 | ldr r2, =_sbss
83 | b LoopFillZerobss
84 | /* Zero fill the bss segment. */
85 | FillZerobss:
86 | movs r3, #0
87 | str r3, [r2], #4
88 |
89 | LoopFillZerobss:
90 | ldr r3, = _ebss
91 | cmp r2, r3
92 | bcc FillZerobss
93 |
94 | /* Call the clock system intitialization function.*/
95 | bl SystemInit
96 | /* Call static constructors */
97 | bl __libc_init_array
98 | /* Call the application's entry point.*/
99 | bl main
100 | bx lr
101 | .size Reset_Handler, .-Reset_Handler
102 |
103 | /**
104 | * @brief This is the code that gets called when the processor receives an
105 | * unexpected interrupt. This simply enters an infinite loop, preserving
106 | * the system state for examination by a debugger.
107 | *
108 | * @param None
109 | * @retval : None
110 | */
111 | .section .text.Default_Handler,"ax",%progbits
112 | Default_Handler:
113 | Infinite_Loop:
114 | b Infinite_Loop
115 | .size Default_Handler, .-Default_Handler
116 | /******************************************************************************
117 | *
118 | * The minimal vector table for a Cortex M3. Note that the proper constructs
119 | * must be placed on this to ensure that it ends up at physical address
120 | * 0x0000.0000.
121 | *
122 | ******************************************************************************/
123 | .section .isr_vector,"a",%progbits
124 | .type g_pfnVectors, %object
125 | .size g_pfnVectors, .-g_pfnVectors
126 |
127 |
128 | g_pfnVectors:
129 | .word _estack
130 | .word Reset_Handler
131 | .word NMI_Handler
132 | .word HardFault_Handler
133 | .word MemManage_Handler
134 | .word BusFault_Handler
135 | .word UsageFault_Handler
136 | .word 0
137 | .word 0
138 | .word 0
139 | .word 0
140 | .word SVC_Handler
141 | .word DebugMon_Handler
142 | .word 0
143 | .word PendSV_Handler
144 | .word SysTick_Handler
145 | .word WWDG_IRQHandler
146 | .word PVD_IRQHandler
147 | .word TAMPER_IRQHandler
148 | .word RTC_IRQHandler
149 | .word FLASH_IRQHandler
150 | .word RCC_IRQHandler
151 | .word EXTI0_IRQHandler
152 | .word EXTI1_IRQHandler
153 | .word EXTI2_IRQHandler
154 | .word EXTI3_IRQHandler
155 | .word EXTI4_IRQHandler
156 | .word DMA1_Channel1_IRQHandler
157 | .word DMA1_Channel2_IRQHandler
158 | .word DMA1_Channel3_IRQHandler
159 | .word DMA1_Channel4_IRQHandler
160 | .word DMA1_Channel5_IRQHandler
161 | .word DMA1_Channel6_IRQHandler
162 | .word DMA1_Channel7_IRQHandler
163 | .word ADC1_IRQHandler
164 | .word 0
165 | .word 0
166 | .word 0
167 | .word 0
168 | .word EXTI9_5_IRQHandler
169 | .word TIM1_BRK_TIM15_IRQHandler
170 | .word TIM1_UP_TIM16_IRQHandler
171 | .word TIM1_TRG_COM_TIM17_IRQHandler
172 | .word TIM1_CC_IRQHandler
173 | .word TIM2_IRQHandler
174 | .word TIM3_IRQHandler
175 | .word 0
176 | .word I2C1_EV_IRQHandler
177 | .word I2C1_ER_IRQHandler
178 | .word 0
179 | .word 0
180 | .word SPI1_IRQHandler
181 | .word 0
182 | .word USART1_IRQHandler
183 | .word USART2_IRQHandler
184 | .word 0
185 | .word EXTI15_10_IRQHandler
186 | .word RTCAlarm_IRQHandler
187 | .word CEC_IRQHandler
188 | .word 0
189 | .word 0
190 | .word 0
191 | .word 0
192 | .word 0
193 | .word 0
194 | .word 0
195 | .word 0
196 | .word 0
197 | .word 0
198 | .word 0
199 | .word TIM6_DAC_IRQHandler
200 | .word TIM7_IRQHandler
201 | .word 0
202 | .word 0
203 | .word 0
204 | .word 0
205 | .word 0
206 | .word 0
207 | .word 0
208 | .word 0
209 | .word 0
210 | .word 0
211 | .word 0
212 | .word 0
213 | .word 0
214 | .word 0
215 | .word 0
216 | .word 0
217 | .word 0
218 | .word 0
219 | .word 0
220 | .word 0
221 | .word 0
222 | .word 0
223 | .word 0
224 | .word 0
225 | .word 0
226 | .word 0
227 | .word 0
228 | .word 0
229 | .word 0
230 | .word 0
231 | .word 0
232 | .word 0
233 | .word 0
234 | .word 0
235 | .word 0
236 | .word 0
237 | .word 0
238 | .word 0
239 | .word 0
240 | .word 0
241 | .word 0
242 | .word 0
243 | .word 0
244 | .word BootRAM /* @0x01CC. This is for boot in RAM mode for
245 | STM32F10x Medium Value Line Density devices. */
246 |
247 | /*******************************************************************************
248 | *
249 | * Provide weak aliases for each Exception handler to the Default_Handler.
250 | * As they are weak aliases, any function with the same name will override
251 | * this definition.
252 | *
253 | *******************************************************************************/
254 |
255 |
256 | .weak NMI_Handler
257 | .thumb_set NMI_Handler,Default_Handler
258 |
259 | .weak HardFault_Handler
260 | .thumb_set HardFault_Handler,Default_Handler
261 |
262 | .weak MemManage_Handler
263 | .thumb_set MemManage_Handler,Default_Handler
264 |
265 | .weak BusFault_Handler
266 | .thumb_set BusFault_Handler,Default_Handler
267 |
268 | .weak UsageFault_Handler
269 | .thumb_set UsageFault_Handler,Default_Handler
270 |
271 | .weak SVC_Handler
272 | .thumb_set SVC_Handler,Default_Handler
273 |
274 | .weak DebugMon_Handler
275 | .thumb_set DebugMon_Handler,Default_Handler
276 |
277 | .weak PendSV_Handler
278 | .thumb_set PendSV_Handler,Default_Handler
279 |
280 | .weak SysTick_Handler
281 | .thumb_set SysTick_Handler,Default_Handler
282 |
283 | .weak WWDG_IRQHandler
284 | .thumb_set WWDG_IRQHandler,Default_Handler
285 |
286 | .weak PVD_IRQHandler
287 | .thumb_set PVD_IRQHandler,Default_Handler
288 |
289 | .weak TAMPER_IRQHandler
290 | .thumb_set TAMPER_IRQHandler,Default_Handler
291 |
292 | .weak RTC_IRQHandler
293 | .thumb_set RTC_IRQHandler,Default_Handler
294 |
295 | .weak FLASH_IRQHandler
296 | .thumb_set FLASH_IRQHandler,Default_Handler
297 |
298 | .weak RCC_IRQHandler
299 | .thumb_set RCC_IRQHandler,Default_Handler
300 |
301 | .weak EXTI0_IRQHandler
302 | .thumb_set EXTI0_IRQHandler,Default_Handler
303 |
304 | .weak EXTI1_IRQHandler
305 | .thumb_set EXTI1_IRQHandler,Default_Handler
306 |
307 | .weak EXTI2_IRQHandler
308 | .thumb_set EXTI2_IRQHandler,Default_Handler
309 |
310 | .weak EXTI3_IRQHandler
311 | .thumb_set EXTI3_IRQHandler,Default_Handler
312 |
313 | .weak EXTI4_IRQHandler
314 | .thumb_set EXTI4_IRQHandler,Default_Handler
315 |
316 | .weak DMA1_Channel1_IRQHandler
317 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
318 |
319 | .weak DMA1_Channel2_IRQHandler
320 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
321 |
322 | .weak DMA1_Channel3_IRQHandler
323 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
324 |
325 | .weak DMA1_Channel4_IRQHandler
326 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
327 |
328 | .weak DMA1_Channel5_IRQHandler
329 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
330 |
331 | .weak DMA1_Channel6_IRQHandler
332 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
333 |
334 | .weak DMA1_Channel7_IRQHandler
335 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
336 |
337 | .weak ADC1_IRQHandler
338 | .thumb_set ADC1_IRQHandler,Default_Handler
339 |
340 | .weak EXTI9_5_IRQHandler
341 | .thumb_set EXTI9_5_IRQHandler,Default_Handler
342 |
343 | .weak TIM1_BRK_TIM15_IRQHandler
344 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
345 |
346 | .weak TIM1_UP_TIM16_IRQHandler
347 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
348 |
349 | .weak TIM1_TRG_COM_TIM17_IRQHandler
350 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
351 |
352 | .weak TIM1_CC_IRQHandler
353 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
354 |
355 | .weak TIM2_IRQHandler
356 | .thumb_set TIM2_IRQHandler,Default_Handler
357 |
358 | .weak TIM3_IRQHandler
359 | .thumb_set TIM3_IRQHandler,Default_Handler
360 |
361 | .weak I2C1_EV_IRQHandler
362 | .thumb_set I2C1_EV_IRQHandler,Default_Handler
363 |
364 | .weak I2C1_ER_IRQHandler
365 | .thumb_set I2C1_ER_IRQHandler,Default_Handler
366 |
367 | .weak SPI1_IRQHandler
368 | .thumb_set SPI1_IRQHandler,Default_Handler
369 |
370 | .weak USART1_IRQHandler
371 | .thumb_set USART1_IRQHandler,Default_Handler
372 |
373 | .weak USART2_IRQHandler
374 | .thumb_set USART2_IRQHandler,Default_Handler
375 |
376 | .weak EXTI15_10_IRQHandler
377 | .thumb_set EXTI15_10_IRQHandler,Default_Handler
378 |
379 | .weak RTCAlarm_IRQHandler
380 | .thumb_set RTCAlarm_IRQHandler,Default_Handler
381 |
382 | .weak CEC_IRQHandler
383 | .thumb_set CEC_IRQHandler,Default_Handler
384 |
385 | .weak TIM6_DAC_IRQHandler
386 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler
387 |
388 | .weak TIM7_IRQHandler
389 | .thumb_set TIM7_IRQHandler,Default_Handler
390 |
391 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
392 |
393 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_md.s:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file startup_stm32f10x_md.s
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain.
8 | * This module performs:
9 | * - Set the initial SP
10 | * - Set the initial PC == Reset_Handler,
11 | * - Set the vector table entries with the exceptions ISR address
12 | * - Configure the clock system
13 | * - Branches to main in the C library (which eventually
14 | * calls main()).
15 | * After Reset the Cortex-M3 processor is in Thread mode,
16 | * priority is Privileged, and the Stack is set to Main.
17 | ******************************************************************************
18 | * @attention
19 | *
20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
26 | *
27 | * © COPYRIGHT 2011 STMicroelectronics
28 | ******************************************************************************
29 | */
30 |
31 | .syntax unified
32 | .cpu cortex-m3
33 | .fpu softvfp
34 | .thumb
35 |
36 | .global g_pfnVectors
37 | .global Default_Handler
38 |
39 | /* start address for the initialization values of the .data section.
40 | defined in linker script */
41 | .word _sidata
42 | /* start address for the .data section. defined in linker script */
43 | .word _sdata
44 | /* end address for the .data section. defined in linker script */
45 | .word _edata
46 | /* start address for the .bss section. defined in linker script */
47 | .word _sbss
48 | /* end address for the .bss section. defined in linker script */
49 | .word _ebss
50 |
51 | .equ BootRAM, 0xF108F85F
52 | /**
53 | * @brief This is the code that gets called when the processor first
54 | * starts execution following a reset event. Only the absolutely
55 | * necessary set is performed, after which the application
56 | * supplied main() routine is called.
57 | * @param None
58 | * @retval : None
59 | */
60 |
61 | .section .text.Reset_Handler
62 | .weak Reset_Handler
63 | .type Reset_Handler, %function
64 | Reset_Handler:
65 |
66 | /* Copy the data segment initializers from flash to SRAM */
67 | movs r1, #0
68 | b LoopCopyDataInit
69 |
70 | CopyDataInit:
71 | ldr r3, =_sidata
72 | ldr r3, [r3, r1]
73 | str r3, [r0, r1]
74 | adds r1, r1, #4
75 |
76 | LoopCopyDataInit:
77 | ldr r0, =_sdata
78 | ldr r3, =_edata
79 | adds r2, r0, r1
80 | cmp r2, r3
81 | bcc CopyDataInit
82 | ldr r2, =_sbss
83 | b LoopFillZerobss
84 | /* Zero fill the bss segment. */
85 | FillZerobss:
86 | movs r3, #0
87 | str r3, [r2], #4
88 |
89 | LoopFillZerobss:
90 | ldr r3, = _ebss
91 | cmp r2, r3
92 | bcc FillZerobss
93 |
94 | /* Call the clock system intitialization function.*/
95 | bl SystemInit
96 | /* Call static constructors */
97 | bl __libc_init_array
98 | /* Call the application's entry point.*/
99 | bl main
100 | bx lr
101 | .size Reset_Handler, .-Reset_Handler
102 |
103 | /**
104 | * @brief This is the code that gets called when the processor receives an
105 | * unexpected interrupt. This simply enters an infinite loop, preserving
106 | * the system state for examination by a debugger.
107 | *
108 | * @param None
109 | * @retval : None
110 | */
111 | .section .text.Default_Handler,"ax",%progbits
112 | Default_Handler:
113 | Infinite_Loop:
114 | b Infinite_Loop
115 | .size Default_Handler, .-Default_Handler
116 | /******************************************************************************
117 | *
118 | * The minimal vector table for a Cortex M3. Note that the proper constructs
119 | * must be placed on this to ensure that it ends up at physical address
120 | * 0x0000.0000.
121 | *
122 | ******************************************************************************/
123 | .section .isr_vector,"a",%progbits
124 | .type g_pfnVectors, %object
125 | .size g_pfnVectors, .-g_pfnVectors
126 |
127 |
128 | g_pfnVectors:
129 | .word _estack
130 | .word Reset_Handler
131 | .word NMI_Handler
132 | .word HardFault_Handler
133 | .word MemManage_Handler
134 | .word BusFault_Handler
135 | .word UsageFault_Handler
136 | .word 0
137 | .word 0
138 | .word 0
139 | .word 0
140 | .word SVC_Handler
141 | .word DebugMon_Handler
142 | .word 0
143 | .word PendSV_Handler
144 | .word SysTick_Handler
145 | .word WWDG_IRQHandler
146 | .word PVD_IRQHandler
147 | .word TAMPER_IRQHandler
148 | .word RTC_IRQHandler
149 | .word FLASH_IRQHandler
150 | .word RCC_IRQHandler
151 | .word EXTI0_IRQHandler
152 | .word EXTI1_IRQHandler
153 | .word EXTI2_IRQHandler
154 | .word EXTI3_IRQHandler
155 | .word EXTI4_IRQHandler
156 | .word DMA1_Channel1_IRQHandler
157 | .word DMA1_Channel2_IRQHandler
158 | .word DMA1_Channel3_IRQHandler
159 | .word DMA1_Channel4_IRQHandler
160 | .word DMA1_Channel5_IRQHandler
161 | .word DMA1_Channel6_IRQHandler
162 | .word DMA1_Channel7_IRQHandler
163 | .word ADC1_2_IRQHandler
164 | .word USB_HP_CAN1_TX_IRQHandler
165 | .word USB_LP_CAN1_RX0_IRQHandler
166 | .word CAN1_RX1_IRQHandler
167 | .word CAN1_SCE_IRQHandler
168 | .word EXTI9_5_IRQHandler
169 | .word TIM1_BRK_IRQHandler
170 | .word TIM1_UP_IRQHandler
171 | .word TIM1_TRG_COM_IRQHandler
172 | .word TIM1_CC_IRQHandler
173 | .word TIM2_IRQHandler
174 | .word TIM3_IRQHandler
175 | .word TIM4_IRQHandler
176 | .word I2C1_EV_IRQHandler
177 | .word I2C1_ER_IRQHandler
178 | .word I2C2_EV_IRQHandler
179 | .word I2C2_ER_IRQHandler
180 | .word SPI1_IRQHandler
181 | .word SPI2_IRQHandler
182 | .word USART1_IRQHandler
183 | .word USART2_IRQHandler
184 | .word USART3_IRQHandler
185 | .word EXTI15_10_IRQHandler
186 | .word RTCAlarm_IRQHandler
187 | .word USBWakeUp_IRQHandler
188 | .word 0
189 | .word 0
190 | .word 0
191 | .word 0
192 | .word 0
193 | .word 0
194 | .word 0
195 | .word BootRAM /* @0x108. This is for boot in RAM mode for
196 | STM32F10x Medium Density devices. */
197 |
198 | /*******************************************************************************
199 | *
200 | * Provide weak aliases for each Exception handler to the Default_Handler.
201 | * As they are weak aliases, any function with the same name will override
202 | * this definition.
203 | *
204 | *******************************************************************************/
205 |
206 | .weak NMI_Handler
207 | .thumb_set NMI_Handler,Default_Handler
208 |
209 | .weak HardFault_Handler
210 | .thumb_set HardFault_Handler,Default_Handler
211 |
212 | .weak MemManage_Handler
213 | .thumb_set MemManage_Handler,Default_Handler
214 |
215 | .weak BusFault_Handler
216 | .thumb_set BusFault_Handler,Default_Handler
217 |
218 | .weak UsageFault_Handler
219 | .thumb_set UsageFault_Handler,Default_Handler
220 |
221 | .weak SVC_Handler
222 | .thumb_set SVC_Handler,Default_Handler
223 |
224 | .weak DebugMon_Handler
225 | .thumb_set DebugMon_Handler,Default_Handler
226 |
227 | .weak PendSV_Handler
228 | .thumb_set PendSV_Handler,Default_Handler
229 |
230 | .weak SysTick_Handler
231 | .thumb_set SysTick_Handler,Default_Handler
232 |
233 | .weak WWDG_IRQHandler
234 | .thumb_set WWDG_IRQHandler,Default_Handler
235 |
236 | .weak PVD_IRQHandler
237 | .thumb_set PVD_IRQHandler,Default_Handler
238 |
239 | .weak TAMPER_IRQHandler
240 | .thumb_set TAMPER_IRQHandler,Default_Handler
241 |
242 | .weak RTC_IRQHandler
243 | .thumb_set RTC_IRQHandler,Default_Handler
244 |
245 | .weak FLASH_IRQHandler
246 | .thumb_set FLASH_IRQHandler,Default_Handler
247 |
248 | .weak RCC_IRQHandler
249 | .thumb_set RCC_IRQHandler,Default_Handler
250 |
251 | .weak EXTI0_IRQHandler
252 | .thumb_set EXTI0_IRQHandler,Default_Handler
253 |
254 | .weak EXTI1_IRQHandler
255 | .thumb_set EXTI1_IRQHandler,Default_Handler
256 |
257 | .weak EXTI2_IRQHandler
258 | .thumb_set EXTI2_IRQHandler,Default_Handler
259 |
260 | .weak EXTI3_IRQHandler
261 | .thumb_set EXTI3_IRQHandler,Default_Handler
262 |
263 | .weak EXTI4_IRQHandler
264 | .thumb_set EXTI4_IRQHandler,Default_Handler
265 |
266 | .weak DMA1_Channel1_IRQHandler
267 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
268 |
269 | .weak DMA1_Channel2_IRQHandler
270 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
271 |
272 | .weak DMA1_Channel3_IRQHandler
273 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
274 |
275 | .weak DMA1_Channel4_IRQHandler
276 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
277 |
278 | .weak DMA1_Channel5_IRQHandler
279 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
280 |
281 | .weak DMA1_Channel6_IRQHandler
282 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
283 |
284 | .weak DMA1_Channel7_IRQHandler
285 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
286 |
287 | .weak ADC1_2_IRQHandler
288 | .thumb_set ADC1_2_IRQHandler,Default_Handler
289 |
290 | .weak USB_HP_CAN1_TX_IRQHandler
291 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
292 |
293 | .weak USB_LP_CAN1_RX0_IRQHandler
294 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
295 |
296 | .weak CAN1_RX1_IRQHandler
297 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler
298 |
299 | .weak CAN1_SCE_IRQHandler
300 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler
301 |
302 | .weak EXTI9_5_IRQHandler
303 | .thumb_set EXTI9_5_IRQHandler,Default_Handler
304 |
305 | .weak TIM1_BRK_IRQHandler
306 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler
307 |
308 | .weak TIM1_UP_IRQHandler
309 | .thumb_set TIM1_UP_IRQHandler,Default_Handler
310 |
311 | .weak TIM1_TRG_COM_IRQHandler
312 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
313 |
314 | .weak TIM1_CC_IRQHandler
315 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
316 |
317 | .weak TIM2_IRQHandler
318 | .thumb_set TIM2_IRQHandler,Default_Handler
319 |
320 | .weak TIM3_IRQHandler
321 | .thumb_set TIM3_IRQHandler,Default_Handler
322 |
323 | .weak TIM4_IRQHandler
324 | .thumb_set TIM4_IRQHandler,Default_Handler
325 |
326 | .weak I2C1_EV_IRQHandler
327 | .thumb_set I2C1_EV_IRQHandler,Default_Handler
328 |
329 | .weak I2C1_ER_IRQHandler
330 | .thumb_set I2C1_ER_IRQHandler,Default_Handler
331 |
332 | .weak I2C2_EV_IRQHandler
333 | .thumb_set I2C2_EV_IRQHandler,Default_Handler
334 |
335 | .weak I2C2_ER_IRQHandler
336 | .thumb_set I2C2_ER_IRQHandler,Default_Handler
337 |
338 | .weak SPI1_IRQHandler
339 | .thumb_set SPI1_IRQHandler,Default_Handler
340 |
341 | .weak SPI2_IRQHandler
342 | .thumb_set SPI2_IRQHandler,Default_Handler
343 |
344 | .weak USART1_IRQHandler
345 | .thumb_set USART1_IRQHandler,Default_Handler
346 |
347 | .weak USART2_IRQHandler
348 | .thumb_set USART2_IRQHandler,Default_Handler
349 |
350 | .weak USART3_IRQHandler
351 | .thumb_set USART3_IRQHandler,Default_Handler
352 |
353 | .weak EXTI15_10_IRQHandler
354 | .thumb_set EXTI15_10_IRQHandler,Default_Handler
355 |
356 | .weak RTCAlarm_IRQHandler
357 | .thumb_set RTCAlarm_IRQHandler,Default_Handler
358 |
359 | .weak USBWakeUp_IRQHandler
360 | .thumb_set USBWakeUp_IRQHandler,Default_Handler
361 |
362 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
363 |
364 |
--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_md_vl.s:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file startup_stm32f10x_md_vl.s
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic
8 | * toolchain.
9 | * This module performs:
10 | * - Set the initial SP
11 | * - Set the initial PC == Reset_Handler,
12 | * - Set the vector table entries with the exceptions ISR address
13 | * - Configure the clock system
14 | * - Branches to main in the C library (which eventually
15 | * calls main()).
16 | * After Reset the Cortex-M3 processor is in Thread mode,
17 | * priority is Privileged, and the Stack is set to Main.
18 | ******************************************************************************
19 | * @attention
20 | *
21 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
22 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
23 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
24 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
25 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
26 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
27 | *
28 | * © COPYRIGHT 2011 STMicroelectronics
29 | ******************************************************************************
30 | */
31 |
32 | .syntax unified
33 | .cpu cortex-m3
34 | .fpu softvfp
35 | .thumb
36 |
37 | .global g_pfnVectors
38 | .global Default_Handler
39 |
40 | /* start address for the initialization values of the .data section.
41 | defined in linker script */
42 | .word _sidata
43 | /* start address for the .data section. defined in linker script */
44 | .word _sdata
45 | /* end address for the .data section. defined in linker script */
46 | .word _edata
47 | /* start address for the .bss section. defined in linker script */
48 | .word _sbss
49 | /* end address for the .bss section. defined in linker script */
50 | .word _ebss
51 |
52 | .equ BootRAM, 0xF108F85F
53 | /**
54 | * @brief This is the code that gets called when the processor first
55 | * starts execution following a reset event. Only the absolutely
56 | * necessary set is performed, after which the application
57 | * supplied main() routine is called.
58 | * @param None
59 | * @retval : None
60 | */
61 |
62 | .section .text.Reset_Handler
63 | .weak Reset_Handler
64 | .type Reset_Handler, %function
65 | Reset_Handler:
66 |
67 | /* Copy the data segment initializers from flash to SRAM */
68 | movs r1, #0
69 | b LoopCopyDataInit
70 |
71 | CopyDataInit:
72 | ldr r3, =_sidata
73 | ldr r3, [r3, r1]
74 | str r3, [r0, r1]
75 | adds r1, r1, #4
76 |
77 | LoopCopyDataInit:
78 | ldr r0, =_sdata
79 | ldr r3, =_edata
80 | adds r2, r0, r1
81 | cmp r2, r3
82 | bcc CopyDataInit
83 | ldr r2, =_sbss
84 | b LoopFillZerobss
85 | /* Zero fill the bss segment. */
86 | FillZerobss:
87 | movs r3, #0
88 | str r3, [r2], #4
89 |
90 | LoopFillZerobss:
91 | ldr r3, = _ebss
92 | cmp r2, r3
93 | bcc FillZerobss
94 |
95 | /* Call the clock system intitialization function.*/
96 | bl SystemInit
97 | /* Call static constructors */
98 | bl __libc_init_array
99 | /* Call the application's entry point.*/
100 | bl main
101 | bx lr
102 | .size Reset_Handler, .-Reset_Handler
103 |
104 | /**
105 | * @brief This is the code that gets called when the processor receives an
106 | * unexpected interrupt. This simply enters an infinite loop, preserving
107 | * the system state for examination by a debugger.
108 | *
109 | * @param None
110 | * @retval : None
111 | */
112 | .section .text.Default_Handler,"ax",%progbits
113 | Default_Handler:
114 | Infinite_Loop:
115 | b Infinite_Loop
116 | .size Default_Handler, .-Default_Handler
117 | /******************************************************************************
118 | *
119 | * The minimal vector table for a Cortex M3. Note that the proper constructs
120 | * must be placed on this to ensure that it ends up at physical address
121 | * 0x0000.0000.
122 | *
123 | ******************************************************************************/
124 | .section .isr_vector,"a",%progbits
125 | .type g_pfnVectors, %object
126 | .size g_pfnVectors, .-g_pfnVectors
127 |
128 |
129 | g_pfnVectors:
130 | .word _estack
131 | .word Reset_Handler
132 | .word NMI_Handler
133 | .word HardFault_Handler
134 | .word MemManage_Handler
135 | .word BusFault_Handler
136 | .word UsageFault_Handler
137 | .word 0
138 | .word 0
139 | .word 0
140 | .word 0
141 | .word SVC_Handler
142 | .word DebugMon_Handler
143 | .word 0
144 | .word PendSV_Handler
145 | .word SysTick_Handler
146 | .word WWDG_IRQHandler
147 | .word PVD_IRQHandler
148 | .word TAMPER_IRQHandler
149 | .word RTC_IRQHandler
150 | .word FLASH_IRQHandler
151 | .word RCC_IRQHandler
152 | .word EXTI0_IRQHandler
153 | .word EXTI1_IRQHandler
154 | .word EXTI2_IRQHandler
155 | .word EXTI3_IRQHandler
156 | .word EXTI4_IRQHandler
157 | .word DMA1_Channel1_IRQHandler
158 | .word DMA1_Channel2_IRQHandler
159 | .word DMA1_Channel3_IRQHandler
160 | .word DMA1_Channel4_IRQHandler
161 | .word DMA1_Channel5_IRQHandler
162 | .word DMA1_Channel6_IRQHandler
163 | .word DMA1_Channel7_IRQHandler
164 | .word ADC1_IRQHandler
165 | .word 0
166 | .word 0
167 | .word 0
168 | .word 0
169 | .word EXTI9_5_IRQHandler
170 | .word TIM1_BRK_TIM15_IRQHandler
171 | .word TIM1_UP_TIM16_IRQHandler
172 | .word TIM1_TRG_COM_TIM17_IRQHandler
173 | .word TIM1_CC_IRQHandler
174 | .word TIM2_IRQHandler
175 | .word TIM3_IRQHandler
176 | .word TIM4_IRQHandler
177 | .word I2C1_EV_IRQHandler
178 | .word I2C1_ER_IRQHandler
179 | .word I2C2_EV_IRQHandler
180 | .word I2C2_ER_IRQHandler
181 | .word SPI1_IRQHandler
182 | .word SPI2_IRQHandler
183 | .word USART1_IRQHandler
184 | .word USART2_IRQHandler
185 | .word USART3_IRQHandler
186 | .word EXTI15_10_IRQHandler
187 | .word RTCAlarm_IRQHandler
188 | .word CEC_IRQHandler
189 | .word 0
190 | .word 0
191 | .word 0
192 | .word 0
193 | .word 0
194 | .word 0
195 | .word 0
196 | .word 0
197 | .word 0
198 | .word 0
199 | .word 0
200 | .word TIM6_DAC_IRQHandler
201 | .word TIM7_IRQHandler
202 | .word 0
203 | .word 0
204 | .word 0
205 | .word 0
206 | .word 0
207 | .word 0
208 | .word 0
209 | .word 0
210 | .word 0
211 | .word 0
212 | .word 0
213 | .word 0
214 | .word 0
215 | .word 0
216 | .word 0
217 | .word 0
218 | .word 0
219 | .word 0
220 | .word 0
221 | .word 0
222 | .word 0
223 | .word 0
224 | .word 0
225 | .word 0
226 | .word 0
227 | .word 0
228 | .word 0
229 | .word 0
230 | .word 0
231 | .word 0
232 | .word 0
233 | .word 0
234 | .word 0
235 | .word 0
236 | .word 0
237 | .word 0
238 | .word 0
239 | .word 0
240 | .word 0
241 | .word 0
242 | .word 0
243 | .word 0
244 | .word 0
245 | .word BootRAM /* @0x01CC. This is for boot in RAM mode for
246 | STM32F10x Medium Value Line Density devices. */
247 |
248 | /*******************************************************************************
249 | *
250 | * Provide weak aliases for each Exception handler to the Default_Handler.
251 | * As they are weak aliases, any function with the same name will override
252 | * this definition.
253 | *
254 | *******************************************************************************/
255 |
256 |
257 | .weak NMI_Handler
258 | .thumb_set NMI_Handler,Default_Handler
259 |
260 | .weak HardFault_Handler
261 | .thumb_set HardFault_Handler,Default_Handler
262 |
263 | .weak MemManage_Handler
264 | .thumb_set MemManage_Handler,Default_Handler
265 |
266 | .weak BusFault_Handler
267 | .thumb_set BusFault_Handler,Default_Handler
268 |
269 | .weak UsageFault_Handler
270 | .thumb_set UsageFault_Handler,Default_Handler
271 |
272 | .weak SVC_Handler
273 | .thumb_set SVC_Handler,Default_Handler
274 |
275 | .weak DebugMon_Handler
276 | .thumb_set DebugMon_Handler,Default_Handler
277 |
278 | .weak PendSV_Handler
279 | .thumb_set PendSV_Handler,Default_Handler
280 |
281 | .weak SysTick_Handler
282 | .thumb_set SysTick_Handler,Default_Handler
283 |
284 | .weak WWDG_IRQHandler
285 | .thumb_set WWDG_IRQHandler,Default_Handler
286 |
287 | .weak PVD_IRQHandler
288 | .thumb_set PVD_IRQHandler,Default_Handler
289 |
290 | .weak TAMPER_IRQHandler
291 | .thumb_set TAMPER_IRQHandler,Default_Handler
292 |
293 | .weak RTC_IRQHandler
294 | .thumb_set RTC_IRQHandler,Default_Handler
295 |
296 | .weak FLASH_IRQHandler
297 | .thumb_set FLASH_IRQHandler,Default_Handler
298 |
299 | .weak RCC_IRQHandler
300 | .thumb_set RCC_IRQHandler,Default_Handler
301 |
302 | .weak EXTI0_IRQHandler
303 | .thumb_set EXTI0_IRQHandler,Default_Handler
304 |
305 | .weak EXTI1_IRQHandler
306 | .thumb_set EXTI1_IRQHandler,Default_Handler
307 |
308 | .weak EXTI2_IRQHandler
309 | .thumb_set EXTI2_IRQHandler,Default_Handler
310 |
311 | .weak EXTI3_IRQHandler
312 | .thumb_set EXTI3_IRQHandler,Default_Handler
313 |
314 | .weak EXTI4_IRQHandler
315 | .thumb_set EXTI4_IRQHandler,Default_Handler
316 |
317 | .weak DMA1_Channel1_IRQHandler
318 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
319 |
320 | .weak DMA1_Channel2_IRQHandler
321 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
322 |
323 | .weak DMA1_Channel3_IRQHandler
324 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
325 |
326 | .weak DMA1_Channel4_IRQHandler
327 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
328 |
329 | .weak DMA1_Channel5_IRQHandler
330 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
331 |
332 | .weak DMA1_Channel6_IRQHandler
333 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
334 |
335 | .weak DMA1_Channel7_IRQHandler
336 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
337 |
338 | .weak ADC1_IRQHandler
339 | .thumb_set ADC1_IRQHandler,Default_Handler
340 |
341 | .weak EXTI9_5_IRQHandler
342 | .thumb_set EXTI9_5_IRQHandler,Default_Handler
343 |
344 | .weak TIM1_BRK_TIM15_IRQHandler
345 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
346 |
347 | .weak TIM1_UP_TIM16_IRQHandler
348 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
349 |
350 | .weak TIM1_TRG_COM_TIM17_IRQHandler
351 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
352 |
353 | .weak TIM1_CC_IRQHandler
354 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
355 |
356 | .weak TIM2_IRQHandler
357 | .thumb_set TIM2_IRQHandler,Default_Handler
358 |
359 | .weak TIM3_IRQHandler
360 | .thumb_set TIM3_IRQHandler,Default_Handler
361 |
362 | .weak TIM4_IRQHandler
363 | .thumb_set TIM4_IRQHandler,Default_Handler
364 |
365 | .weak I2C1_EV_IRQHandler
366 | .thumb_set I2C1_EV_IRQHandler,Default_Handler
367 |
368 | .weak I2C1_ER_IRQHandler
369 | .thumb_set I2C1_ER_IRQHandler,Default_Handler
370 |
371 | .weak I2C2_EV_IRQHandler
372 | .thumb_set I2C2_EV_IRQHandler,Default_Handler
373 |
374 | .weak I2C2_ER_IRQHandler
375 | .thumb_set I2C2_ER_IRQHandler,Default_Handler
376 |
377 | .weak SPI1_IRQHandler
378 | .thumb_set SPI1_IRQHandler,Default_Handler
379 |
380 | .weak SPI2_IRQHandler
381 | .thumb_set SPI2_IRQHandler,Default_Handler
382 |
383 | .weak USART1_IRQHandler
384 | .thumb_set USART1_IRQHandler,Default_Handler
385 |
386 | .weak USART2_IRQHandler
387 | .thumb_set USART2_IRQHandler,Default_Handler
388 |
389 | .weak USART3_IRQHandler
390 | .thumb_set USART3_IRQHandler,Default_Handler
391 |
392 | .weak EXTI15_10_IRQHandler
393 | .thumb_set EXTI15_10_IRQHandler,Default_Handler
394 |
395 | .weak RTCAlarm_IRQHandler
396 | .thumb_set RTCAlarm_IRQHandler,Default_Handler
397 |
398 | .weak CEC_IRQHandler
399 | .thumb_set CEC_IRQHandler,Default_Handler
400 |
401 | .weak TIM6_DAC_IRQHandler
402 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler
403 |
404 | .weak TIM7_IRQHandler
405 | .thumb_set TIM7_IRQHandler,Default_Handler
406 |
407 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
408 |
409 |
--------------------------------------------------------------------------------
/CORE/stm32_flash.ld:
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/CORE/stm32f10x.h:
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/CORE/stm32f10x_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CONF_H
24 | #define __STM32F10x_CONF_H
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
28 | #include "stm32f10x_adc.h"
29 | #include "stm32f10x_bkp.h"
30 | #include "stm32f10x_can.h"
31 | #include "stm32f10x_cec.h"
32 | #include "stm32f10x_crc.h"
33 | #include "stm32f10x_dac.h"
34 | #include "stm32f10x_dbgmcu.h"
35 | #include "stm32f10x_dma.h"
36 | #include "stm32f10x_exti.h"
37 | #include "stm32f10x_flash.h"
38 | #include "stm32f10x_fsmc.h"
39 | #include "stm32f10x_gpio.h"
40 | #include "stm32f10x_i2c.h"
41 | #include "stm32f10x_iwdg.h"
42 | #include "stm32f10x_pwr.h"
43 | #include "stm32f10x_rcc.h"
44 | #include "stm32f10x_rtc.h"
45 | #include "stm32f10x_sdio.h"
46 | #include "stm32f10x_spi.h"
47 | #include "stm32f10x_tim.h"
48 | #include "stm32f10x_usart.h"
49 | #include "stm32f10x_wwdg.h"
50 | #include "misc.h"/* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
51 |
52 | /* Exported types ------------------------------------------------------------*/
53 | /* Exported constants --------------------------------------------------------*/
54 | /* Uncomment the line below to expanse the "assert_param" macro in the
55 | Standard Peripheral Library drivers code */
56 | /* #define USE_FULL_ASSERT 1 */
57 |
58 | /* Exported macro ------------------------------------------------------------*/
59 | #ifdef USE_FULL_ASSERT
60 |
61 | /**
62 | * @brief The assert_param macro is used for function's parameters check.
63 | * @param expr: If expr is false, it calls assert_failed function which reports
64 | * the name of the source file and the source line number of the call
65 | * that failed. If expr is true, it returns no value.
66 | * @retval None
67 | */
68 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
69 | /* Exported functions ------------------------------------------------------- */
70 | void assert_failed(uint8_t* file, uint32_t line);
71 | #else
72 | #define assert_param(expr) ((void)0)
73 | #endif /* USE_FULL_ASSERT */
74 |
75 | #endif /* __STM32F10x_CONF_H */
76 |
77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
78 |
--------------------------------------------------------------------------------
/CORE/stm32f10x_it.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Main Interrupt Service Routines.
8 | * This file provides template for all exceptions handler and
9 | * peripherals interrupt service routine.
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
15 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
16 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
17 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
18 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 | *
20 | * © COPYRIGHT 2011 STMicroelectronics
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes ------------------------------------------------------------------*/
25 | #include "stm32f10x_it.h"
26 |
27 | /** @addtogroup STM32F10x_StdPeriph_Template
28 | * @{
29 | */
30 |
31 | /* Private typedef -----------------------------------------------------------*/
32 | /* Private define ------------------------------------------------------------*/
33 | /* Private macro -------------------------------------------------------------*/
34 | /* Private variables ---------------------------------------------------------*/
35 | /* Private function prototypes -----------------------------------------------*/
36 | /* Private functions ---------------------------------------------------------*/
37 |
38 | /******************************************************************************/
39 | /* Cortex-M3 Processor Exceptions Handlers */
40 | /******************************************************************************/
41 |
42 | /**
43 | * @brief This function handles NMI exception.
44 | * @param None
45 | * @retval None
46 | */
47 | void NMI_Handler(void)
48 | {
49 | }
50 |
51 | /**
52 | * @brief This function handles Hard Fault exception.
53 | * @param None
54 | * @retval None
55 | */
56 | void HardFault_Handler(void)
57 | {
58 | /* Go to infinite loop when Hard Fault exception occurs */
59 | while (1)
60 | {
61 | }
62 | }
63 |
64 | /**
65 | * @brief This function handles Memory Manage exception.
66 | * @param None
67 | * @retval None
68 | */
69 | void MemManage_Handler(void)
70 | {
71 | /* Go to infinite loop when Memory Manage exception occurs */
72 | while (1)
73 | {
74 | }
75 | }
76 |
77 | /**
78 | * @brief This function handles Bus Fault exception.
79 | * @param None
80 | * @retval None
81 | */
82 | void BusFault_Handler(void)
83 | {
84 | /* Go to infinite loop when Bus Fault exception occurs */
85 | while (1)
86 | {
87 | }
88 | }
89 |
90 | /**
91 | * @brief This function handles Usage Fault exception.
92 | * @param None
93 | * @retval None
94 | */
95 | void UsageFault_Handler(void)
96 | {
97 | /* Go to infinite loop when Usage Fault exception occurs */
98 | while (1)
99 | {
100 | }
101 | }
102 |
103 | /**
104 | * @brief This function handles SVCall exception.
105 | * @param None
106 | * @retval None
107 | */
108 | void SVC_Handler(void)
109 | {
110 | }
111 |
112 | /**
113 | * @brief This function handles Debug Monitor exception.
114 | * @param None
115 | * @retval None
116 | */
117 | void DebugMon_Handler(void)
118 | {
119 | }
120 |
121 | /**
122 | * @brief This function handles PendSVC exception.
123 | * @param None
124 | * @retval None
125 | */
126 | void PendSV_Handler(void)
127 | {
128 | }
129 |
130 | /**
131 | * @brief This function handles SysTick Handler.
132 | * @param None
133 | * @retval None
134 | */
135 | // void SysTick_Handler(void)
136 | // {
137 | // }
138 |
139 | /******************************************************************************/
140 | /* STM32F10x Peripherals Interrupt Handlers */
141 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
142 | /* available peripheral interrupt handler's name please refer to the startup */
143 | /* file (startup_stm32f10x_xx.s). */
144 | /******************************************************************************/
145 |
146 | /**
147 | * @brief This function handles PPP interrupt request.
148 | * @param None
149 | * @retval None
150 | */
151 | /*void PPP_IRQHandler(void)
152 | {
153 | }*/
154 |
155 | /**
156 | * @}
157 | */
158 |
159 |
160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
161 |
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/CORE/stm32f10x_it.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief This file contains the headers of the interrupt handlers.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_IT_H
24 | #define __STM32F10x_IT_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f10x.h"
32 |
33 | /* Exported types ------------------------------------------------------------*/
34 | /* Exported constants --------------------------------------------------------*/
35 | /* Exported macro ------------------------------------------------------------*/
36 | /* Exported functions ------------------------------------------------------- */
37 |
38 | void NMI_Handler(void);
39 | void HardFault_Handler(void);
40 | void MemManage_Handler(void);
41 | void BusFault_Handler(void);
42 | void UsageFault_Handler(void);
43 | void SVC_Handler(void);
44 | void DebugMon_Handler(void);
45 | void PendSV_Handler(void);
46 | void SysTick_Handler(void);
47 |
48 | #ifdef __cplusplus
49 | }
50 | #endif
51 |
52 | #endif /* __STM32F10x_IT_H */
53 |
54 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
55 |
--------------------------------------------------------------------------------
/CORE/system_stm32f10x.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /** @addtogroup CMSIS
23 | * @{
24 | */
25 |
26 | /** @addtogroup stm32f10x_system
27 | * @{
28 | */
29 |
30 | /**
31 | * @brief Define to prevent recursive inclusion
32 | */
33 | #ifndef __SYSTEM_STM32F10X_H
34 | #define __SYSTEM_STM32F10X_H
35 |
36 | #ifdef __cplusplus
37 | extern "C" {
38 | #endif
39 |
40 | /** @addtogroup STM32F10x_System_Includes
41 | * @{
42 | */
43 |
44 | /**
45 | * @}
46 | */
47 |
48 |
49 | /** @addtogroup STM32F10x_System_Exported_types
50 | * @{
51 | */
52 |
53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @addtogroup STM32F10x_System_Exported_Constants
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @addtogroup STM32F10x_System_Exported_Macros
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @addtogroup STM32F10x_System_Exported_Functions
76 | * @{
77 | */
78 |
79 | extern void SystemInit(void);
80 | extern void SystemCoreClockUpdate(void);
81 | /**
82 | * @}
83 | */
84 |
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 |
89 | #endif /*__SYSTEM_STM32F10X_H */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
99 |
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/HARDWARE/delay.c:
--------------------------------------------------------------------------------
1 | /****************************************************************************************
2 | *文件名 ：delay.c
3 | *描述 ：STM32F1微秒延时函数，systick时钟为72MHz
4 | *实验平台：STM32F1
5 | ***************************************************************************************/
6 | #include "stm32f10x.h"
7 |
8 | void delay_us(uint32_t nus)
9 | {
10 | uint32_t ticks;
11 | uint32_t told,tnow,tcnt=0;
12 | uint32_t reload=SysTick->LOAD; //systick定时器重装值
13 | ticks=nus*72; //需要延时的节拍数，systick计数频率被设置为72MHz
14 | told=SysTick->VAL; //刚进入时的计数器值
15 | while(1)
16 | {
17 | tnow=SysTick->VAL;
18 | if(tnow!=told)
19 | {
20 | if(tnow=ticks)break; //时间超过/等于要延迟的时间,则退出.
24 | }
25 | }
26 | }
27 |
--------------------------------------------------------------------------------
/HARDWARE/delay.h:
--------------------------------------------------------------------------------
1 | #ifndef __DELAY_H
2 | #define __DELAY_H
3 |
4 | void delay_us(uint32_t nus);
5 |
6 | #endif
7 |
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/HARDWARE/led.c:
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/HARDWARE/led.h:
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/HARDWARE/sys.h:
--------------------------------------------------------------------------------
1 | #ifndef __SYS_H
2 | #define __SYS_H
3 |
4 | #include "stm32f10x.h"
5 |
6 | //位带操作,实现51类似的GPIO控制功能
7 | //具体实现思想,参考<>第五章(87页~92页).
8 | //IO口操作宏定义
9 | #define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
10 | #define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
11 | #define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
12 | //IO口地址映射
13 | #define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
14 | #define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
15 | #define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
16 | #define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
17 | #define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
18 | #define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
19 | #define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
20 |
21 | #define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
22 | #define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
23 | #define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
24 | #define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
25 | #define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
26 | #define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
27 | #define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
28 |
29 | //IO口操作,只对单一的IO口!
30 | //确保n的值小于16!
31 | #define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出
32 | #define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入
33 |
34 | #define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
35 | #define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
36 |
37 | #define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
38 | #define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
39 |
40 | #define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出
41 | #define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入
42 |
43 | #define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
44 | #define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
45 |
46 | #define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出
47 | #define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入
48 |
49 | #define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出
50 | #define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入
51 |
52 | // void NVIC_Configuration(void)
53 | // {
54 | // NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); //设置NVIC中断分组2:2位抢占优先级，2位响应优先级
55 | // }
56 |
57 | #endif
58 |
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/HARDWARE/usart.c:
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https://raw.githubusercontent.com/hotsauce1861/gcc-stm32-osal/d307fb21c0bbe871bff93a1daffe723fbe781677/HARDWARE/usart.c
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/HARDWARE/usart.h:
--------------------------------------------------------------------------------
1 | #ifndef __USART2_H
2 | #define __USART2_H
3 |
4 | #include
5 | #include
6 | #include "stm32f10x.h"
7 |
8 | #define COM1 0
9 | #define COM2 1
10 | #define COM3 2
11 | #define COM4 3
12 | #define COM5 4
13 |
14 | #define STOP_1_B 1
15 | #define STOP_0_5_B 3
16 | #define STOP_1_5_B 4
17 | #define STOP_2_B 2
18 |
19 | #define WROD_LEN_7B 7
20 | #define WROD_LEN_8B 8
21 | #define WROD_LEN_9B 9
22 |
23 | #define PARITY_NO 0
24 | #define PARITY_ODD 1
25 | #define PARITY_EVEN 2
26 |
27 | #define HARD_NO 1
28 | #define HARD_RTS 2
29 | #define HARD_CTS 3
30 | #define HARD_RTS_CTS 4
31 |
32 | void Usart_Init( uint8_t Com,uint32_t Baud,uint8_t StopBit,
33 | uint8_t Datalen,uint8_t Parity,uint8_t HardControl);
34 | void Usart_Transmit(uint8_t Com,unsigned int data);
35 | void Usart_Puts(uint8_t Com,char *string);
36 | void Usart_Printf(uint8_t Com,char *format, ...);
37 |
38 | #endif
39 |
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/Makefile:
--------------------------------------------------------------------------------
1 | #工程名称
2 | TARGET = OSAL_example
3 |
4 | #设置编译器
5 | CC = arm-none-eabi-gcc
6 | #CC = /opt/arm-none-gcc-5.4/bin/arm-none-eabi-gcc
7 | OBJCOPY = arm-none-eabi-objcopy
8 | #OBJCOPY = /opt/arm-none-gcc-5.4/bin/arm-none-eabi-objcopy
9 | ARMSIZE = arm-none-eabi-size
10 |
11 | #获取当前工作目录
12 | TOP=.
13 |
14 | #设置源文件后缀，c或cpp
15 | EXT = c
16 |
17 | #设置源文件搜索路径
18 | VPATH += $(TOP)/APP:$(TOP)/CORE:$(TOP)/HARDWARE
19 | VPATH += $(TOP)/OSAL/application:$(TOP)/OSAL/hal:$(TOP)/OSAL/osal
20 | VPATH += $(TOP)/STM32F10x_FWLib/src
21 |
22 | #设置自定义源文件目录
23 | APP_DIR = $(TOP)/APP
24 | HARD_DIR = $(TOP)/HARDWARE
25 |
26 | #设置中间目标文件目录
27 | OBJ_DIR = $(TOP)/OBJ
28 |
29 | #设定头文件包含目录
30 | INC_FLAGS += -I $(TOP)/APP
31 | INC_FLAGS += -I $(TOP)/CORE
32 | INC_FLAGS += -I $(TOP)/HARDWARE
33 | INC_FLAGS += -I $(TOP)/OSAL/include
34 | INC_FLAGS += -I $(TOP)/STM32F10x_FWLib/inc
35 |
36 | #编译选项
37 | CFLAGS += -W -Wall -g -mcpu=cortex-m3 -mthumb -O2 -std=gnu11
38 | CFLAGS += -D STM32F10X_HD -D USE_STDPERIPH_DRIVER
39 |
40 | #链接选项
41 | LFLAGS += -mthumb -mcpu=cortex-m3 -Wl,--start-group -lc -lm -Wl,--end-group -specs=nano.specs
42 | LFLAGS += -specs=nosys.specs -static -Wl,-cref,-u,Reset_Handler -Wl,-Map=Project.map -Wl,--gc-sections
43 | LFLAGS += -Wl,--defsym=malloc_getpagesize_P=0x80
44 |
45 | #链接启动文件和链接脚本
46 | LFLAGS += $(TOP)/CORE/startup_stm32f10x_hd.s
47 | LFLAGS += -T $(TOP)/CORE/stm32_flash.ld
48 |
49 | #固定源文件添加
50 | C_SRC += $(shell find $(TOP)/CORE -name '*.$(EXT)')
51 | C_SRC += $(shell find $(TOP)/OSAL -name '*.$(EXT)')
52 | C_SRC += $(shell find $(TOP)/STM32F10x_FWLib/src -name '*.$(EXT)')
53 |
54 | #自定义源文件添加
55 | C_SRC += $(HARD_DIR)/usart.c $(HARD_DIR)/led.c
56 |
57 | #中间目标文件
58 | #C_OBJ += $(C_SRC:%.$(EXT)=%.o)
59 | C_SRC_NODIR = $(notdir $(C_SRC))
60 | C_OBJ = $(patsubst %.$(EXT), $(OBJ_DIR)/%.o,$(C_SRC_NODIR))
61 |
62 | #依赖文件
63 | C_DEP = $(patsubst %.$(EXT), $(OBJ_DIR)/%.d,$(C_SRC_NODIR))
64 |
65 | .PHONY: all clean rebuild upload test ctags
66 |
67 | all:$(C_OBJ)
68 | @echo "linking object to $(TARGET).elf"
69 | @$(CC) $(C_OBJ) -o $(TARGET).elf $(LFLAGS)
70 | @$(ARMSIZE) $(TARGET).elf
71 | @echo "create $(TARGET).hex from $(TARGET).elf"
72 | @$(OBJCOPY) $(TARGET).elf $(TARGET).hex -Oihex
73 | @$(ARMSIZE) $(TARGET).hex
74 | #$(OBJCOPY) $(TARGET).elf $(TARGET).bin -Obinary
75 |
76 | #静态模式
77 | #$(C_OBJ):%.o:%.$(EXT)
78 | # $(CC) -c $(CFLAGS) -o $@ $<
79 |
80 | $(OBJ_DIR)/%.o:%.$(EXT)
81 | @mkdir -p OBJ
82 | @echo "building $<"
83 | @$(CC) -c $(CFLAGS) $(INC_FLAGS) -o $@ $<
84 |
85 | -include $(C_DEP)
86 | $(OBJ_DIR)/%.d:%.$(EXT)
87 | @mkdir -p OBJ
88 | @echo "making $@"
89 | @set -e;rm -f $@;$(CC) -MM $(CFLAGS) $(INC_FLAGS) $< > $@.$$$$;sed 's,\($*\)\.o[ :]*,$(OBJ_DIR)/\1.o $(OBJ_DIR)/\1.d:,g' < $@.$$$$ > $@;rm -f $@.$$$$
90 |
91 | clean:
92 | -rm -f $(OBJ_DIR)/*
93 | -rm -f $(shell find ./ -name '*.map')
94 | -rm -f $(shell find ./ -name '*.elf')
95 | -rm -f $(shell find ./ -name '*.bin')
96 | -rm -f $(shell find ./ -name '*.hex')
97 |
98 | rebuild: clean all
99 |
100 | test:
101 | @echo "Test !"
102 |
103 | ctags:
104 | @ctags -R *
105 |
106 | upload:
107 | #openocd -f /usr/local/share/openocd/scripts/interface/jlink.cfg -f /usr/local/share/openocd/scripts/target/stm32f1x.cfg -c init -c "reset halt" -c "flash write_image erase $(TOP)/$(TARGET).hex" -c reset -c shutdown
108 | openocd -f /usr/local/share/openocd/scripts/interface/stlink-v2.cfg -f /usr/local/share/openocd/scripts/target/stm32f1x.cfg -c init -c "reset halt" -c "flash write_image erase $(TOP)/$(TARGET).hex" -c reset -c shutdown
109 |
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/OSAL/application/osal_main.c:
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https://raw.githubusercontent.com/hotsauce1861/gcc-stm32-osal/d307fb21c0bbe871bff93a1daffe723fbe781677/OSAL/application/osal_main.c
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/OSAL/application/serial_task.c:
--------------------------------------------------------------------------------
1 | /****************************************************************************************
2 | * 文件名 ：serial_task.c
3 | * 描述 ：系统串口通信任务
4 | * 开发平台：
5 | * 库版本 ：
6 | ***************************************************************************************/
7 | #include "application.h"
8 |
9 | #include
10 | #include
11 | #include
12 |
13 | #include "usart.h"
14 | #include "led.h"
15 |
16 | uint8 Serial_TaskID; //系统串口通信任务ID
17 |
18 | /*********************************************************************
19 | * LOCAL FUNCTION PROTOTYPES
20 | */
21 |
22 | /*********************************************************************
23 | * FUNCTIONS
24 | *********************************************************************/
25 | //串口通信任务初始化
26 | void Serial_Task_Init(uint8 task_id)
27 | {
28 | Serial_TaskID = task_id;
29 |
30 | //串口配置初始化
31 | Usart_Init(COM1,115200,STOP_1_B,WROD_LEN_8B,PARITY_NO,HARD_NO);
32 | LED_Init();
33 | }
34 |
35 | //串口通信任务事件处理
36 | uint16 Serial_Task_EventProcess(uint8 task_id,uint16 task_event)
37 | {
38 | if ( task_event & SYS_EVENT_MSG ) //判断系统消息事件
39 | {
40 | osal_sys_msg_t *MSGpkt; //定义一个指向接受系统消息结构体的指针
41 | //从消息队列获取消息
42 | MSGpkt = (osal_sys_msg_t *)osal_msg_receive( task_id );
43 |
44 | while ( MSGpkt )
45 | {
46 | switch ( MSGpkt->hdr.event ) //判断消息事件
47 | {
48 | case OSAL_PRINTF:
49 | break;
50 |
51 | default:
52 | break;
53 | }
54 |
55 | // Release the memory
56 | osal_msg_deallocate( (uint8 *)MSGpkt );
57 |
58 | // Next 获取下一个消息
59 | MSGpkt = (osal_sys_msg_t *)osal_msg_receive( task_id );
60 | }
61 |
62 | // return unprocessed events
63 | return (task_event ^ SYS_EVENT_MSG);
64 | }
65 |
66 | if(task_event & PRINTF_STR)
67 | {
68 | static int dir = 1;
69 |
70 | if(dir)
71 | {
72 | dir = 0;
73 | LED0 = 0;
74 | }
75 | else
76 | {
77 | dir = 1;
78 | LED0 = 1;
79 | }
80 |
81 | Usart_Printf(COM1,"Linux GCC STM32F103 printf !\r\n");
82 |
83 | return task_event ^ PRINTF_STR;
84 | }
85 |
86 | return 0;
87 | }
88 |
--------------------------------------------------------------------------------
/OSAL/hal/timer.c:
--------------------------------------------------------------------------------
1 | /****************************************************************************************
2 | * 文件名 ：timer.c
3 | * 描述 ：硬件定时器配置文件，为osal操作系统提供系统时钟，移植时需要修改的文件
4 | * 开发平台：
5 | * 库版本 ：
6 | ***************************************************************************************/
7 | #include "timer.h"
8 | #include "osal_timer.h"
9 |
10 | //硬件定时器初始化，设定系统时钟
11 | void OSAL_TIMER_TICKINIT(void)
12 | {
13 | SysTick_Config(SystemCoreClock / 1000);
14 | }
15 |
16 | //开启硬件定时器
17 | void OSAL_TIMER_TICKSTART(void )
18 | {
19 |
20 | }
21 |
22 | //关闭硬件定时器
23 | void OSAL_TIMER_TICKSTOP(void )
24 | {
25 |
26 | }
27 |
28 | //此处添加硬件定时器中断溢出函数，并调用系统时钟更新函数osal_update_timers()
29 | /**
30 | * @brief This function handles SysTick Handler.
31 | * @param None
32 | * @retval None
33 | */
34 | void SysTick_Handler(void)
35 | {
36 | osal_update_timers();
37 | }
38 |
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/OSAL/include/application.h:
--------------------------------------------------------------------------------
1 | #ifndef APPLICATION_H
2 | #define APPLICATION_H
3 |
4 | #include "osal.h"
5 | #include "osal_timer.h"
6 | #include "osal_event.h"
7 | #include "osal_memory.h"
8 | #include "osal_msg.h"
9 |
10 | //全局变量声明
11 | /*****************************************************************************/
12 |
13 | typedef struct
14 | {
15 | osal_event_hdr_t hdr; //操作系统事件结构
16 | unsigned char *Data; //命令帧操作数
17 | } General_SerialData_t; //OSAL中通用串口打印消息的格式结构体
18 |
19 | /*****************************************************************************/
20 |
21 | //所有任务的任务ID、初始化函数、事件处理函数、任务事件都统一在此文件声明或定义
22 | /*****************************************************************************/
23 |
24 | //任务ID声明
25 | extern uint8 Serial_TaskID;
26 |
27 | //任务初始化函数声明
28 | extern void Serial_Task_Init(uint8 task_id);
29 |
30 | //任务事件处理函数声明
31 | extern uint16 Serial_Task_EventProcess(uint8 task_id,uint16 task_event);
32 |
33 | extern void osal_printf(char *format, ...); //打印通用串口数据
34 |
35 | //任务事件定义
36 | //系统消息事件
37 | #define SYS_EVENT_MSG 0x8000
38 |
39 | //串口通信任务事件定义
40 | #define PRINTF_STR 0X0001 //打印字符串事件
41 | //串口通信任务系统消息事件定义
42 | #define OSAL_PRINTF 0X01 //系统打印
43 |
44 | /*****************************************************************************/
45 |
46 | #endif
47 |
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/OSAL/include/osal.h:
--------------------------------------------------------------------------------
1 | #ifndef OSAL_H
2 | #define OSAL_H
3 |
4 | #include "type.h"
5 |
6 | typedef struct
7 | {
8 | void *next;
9 | uint16 len;
10 | uint8 dest_id;
11 | } osal_msg_hdr_t;
12 |
13 | typedef struct
14 | {
15 | uint8 event;
16 | uint8 status;
17 | } osal_event_hdr_t;
18 |
19 | typedef struct
20 | {
21 | osal_event_hdr_t hdr;
22 | uint8* Data_t;
23 | } osal_sys_msg_t; //默认系统消息结构体
24 |
25 | typedef void *osal_msg_q_t;
26 |
27 | extern osal_msg_q_t osal_qHead;
28 | extern uint8 tasksCnt; //任务数量统计
29 |
30 | extern uint8 osal_init_system( void );
31 | int osal_strlen( char *pString );
32 | void *osal_memcpy( void *dst, const void *src, unsigned int len );
33 | void *osal_revmemcpy( void *dst, const void *src, unsigned int len );
34 | void *osal_memdup( const void *src, unsigned int len );
35 | uint8 osal_memcmp( const void *src1, const void *src2, unsigned int len );
36 | void *osal_memset( void *dest, uint8 value, int len );
37 |
38 | #endif
39 |
--------------------------------------------------------------------------------
/OSAL/include/osal_event.h:
--------------------------------------------------------------------------------
1 | #ifndef OSAL_EVENT_H
2 | #define OSAL_EVENT_H
3 |
4 | #include "type.h"
5 | #include "osal_timer.h"
6 |
7 | typedef void (*pTaskInitFn)( uint8 task_id );
8 | typedef uint16 (*pTaskEventHandlerFn)(uint8 task_id,uint16 task_event);
9 |
10 | //任务链表
11 | typedef struct OSALTaskREC
12 | {
13 | struct OSALTaskREC *next;
14 | pTaskInitFn pfnInit; //任务初始化函数指针
15 | pTaskEventHandlerFn pfnEventProcessor; //任务事件处理函数指针
16 | uint8 taskID; //任务ID
17 | uint8 taskPriority; //任务优先级
18 | uint16 events; //任务事件
19 | } OsalTadkREC_t;
20 |
21 | extern OsalTadkREC_t *TaskActive;
22 |
23 | extern void osal_start_system(void);
24 | extern void osal_add_Task( pTaskInitFn pfnInit,
25 | pTaskEventHandlerFn pfnEventProcessor,
26 | uint8 taskPriority);
27 | extern void osal_Task_init(void);
28 | extern void osal_init_TaskHead(void);
29 | extern OsalTadkREC_t *osalNextActiveTask(void);
30 | extern OsalTadkREC_t *osalFindTask(uint8 taskID);
31 | extern uint8 osal_set_event( byte task_id, uint16 event_flag );
32 | extern uint8 osal_clear_event( uint8 task_id, uint16 event_flag );
33 |
34 | #endif
35 |
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/OSAL/include/osal_memory.h:
--------------------------------------------------------------------------------
1 | #ifndef OSALMEM_METRICS_H
2 | #define OSALMEM_METRICS_H
3 |
4 | #include "type.h"
5 |
6 | #define MAXMEMHEAP 1024*6 //内存池大小，单位字节
7 |
8 | #define OSALMEM_METRICS 1 //定义有效则开启内存统计
9 |
10 | void osal_mem_init( void );
11 | void osal_mem_kick( void );
12 | void *osal_mem_alloc( uint16 size );
13 | void osal_mem_free( void *ptr );
14 |
15 | #if OSALMEM_METRICS
16 | uint16 osal_heap_block_max( void );
17 | uint16 osal_heap_block_cnt( void );
18 | uint16 osal_heap_block_free( void );
19 | uint16 osal_heap_mem_used( void );
20 | uint16 osal_heap_high_water( void );
21 | uint16 osal_heap_mem_usage_rate( void );
22 | #endif
23 |
24 | #endif
25 |
--------------------------------------------------------------------------------
/OSAL/include/osal_msg.h:
--------------------------------------------------------------------------------
1 | #ifndef OSAL_MSG_H
2 | #define OSAL_MSG_H
3 |
4 | #include "osal.h"
5 | #include "type.h"
6 | #include "application.h"
7 |
8 | #define OSAL_MSG_NEXT(msg_ptr) ((osal_msg_hdr_t *) (msg_ptr) - 1)->next
9 | #define OSAL_MSG_ID(msg_ptr) ((osal_msg_hdr_t *) (msg_ptr) - 1)->dest_id
10 |
11 | extern uint8 * osal_msg_allocate( uint16 len );
12 | extern uint8 osal_msg_deallocate( uint8 *msg_ptr );
13 | extern uint8 osal_msg_send( uint8 destination_task, uint8 *msg_ptr );
14 | extern uint8 *osal_msg_receive( uint8 task_id );
15 | extern osal_event_hdr_t *osal_msg_find( uint8 task_id, uint8 event );
16 | extern void osal_msg_enqueue( osal_msg_q_t *q_ptr, void *msg_ptr );
17 | extern uint8 osal_msg_enqueue_max( osal_msg_q_t *q_ptr, void *msg_ptr, uint8 max );
18 | extern void *osal_msg_dequeue( osal_msg_q_t *q_ptr );
19 | extern void osal_msg_push( osal_msg_q_t *q_ptr, void *msg_ptr );
20 | extern void osal_msg_extract( osal_msg_q_t *q_ptr, void *msg_ptr, void *prev_ptr );
21 |
22 | #endif
23 |
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/OSAL/include/osal_timer.h:
--------------------------------------------------------------------------------
1 | #ifndef OSAL_TIMER_H
2 | #define OSAL_TIMER_H
3 |
4 | #include "type.h"
5 | #include "timer.h"
6 |
7 | #define TIMER_DECR_TIME 1 //任务定时器更新时自减的数值单位
8 |
9 | extern void osalTimerInit( void );
10 | extern uint8 osal_start_timerEx( uint8 task_id, uint16 event_id, uint16 timeout_value );
11 | extern uint8 osal_start_reload_timer( uint8 taskID, uint16 event_id, uint16 timeout_value );
12 | extern uint8 osal_stop_timerEx( uint8 task_id, uint16 event_id );
13 | extern uint16 osal_get_timeoutEx( uint8 task_id, uint16 event_id );
14 | extern uint8 osal_timer_num_active( void );
15 | extern uint32 osal_GetSystemClock( void );
16 | extern void osal_update_timers( void );
17 |
18 | #endif
19 |
--------------------------------------------------------------------------------
/OSAL/include/timer.h:
--------------------------------------------------------------------------------
1 | #ifndef TIMER_H
2 | #define TIMER_H
3 |
4 | #include "type.h"
5 |
6 | extern void OSAL_TIMER_TICKINIT(void);
7 | extern void OSAL_TIMER_TICKSTART(void);
8 | extern void OSAL_TIMER_TICKSTOP(void);
9 |
10 | #endif
11 |
--------------------------------------------------------------------------------
/OSAL/include/type.h:
--------------------------------------------------------------------------------
1 | #ifndef TYPE_H
2 | #define TYPE_H
3 |
4 | //此处添加实际使用芯片的对应头文件
5 | #include "stm32f10x.h"
6 |
7 | #define ZSUCCESS 1
8 | #define INVALID_TASK 2
9 | #define INVALID_MSG_POINTER 3
10 | #define INVALID_EVENT_ID 4
11 | #define NO_TIMER_AVAIL 5
12 | #define TASK_NO_TASK 6
13 | #define MSG_BUFFER_NOT_AVAIL 7
14 |
15 | typedef unsigned char BOOL;
16 |
17 | //芯片硬件字长
18 | typedef unsigned int halDataAlign_t;
19 |
20 | // Unsigned numbers
21 | typedef unsigned char uint8;
22 | typedef unsigned char byte;
23 | typedef unsigned short uint16;
24 | typedef unsigned short int16U;
25 | typedef unsigned int uint32;
26 | typedef unsigned int int32U;
27 |
28 | // Signed numbers
29 | typedef signed char int8;
30 | typedef signed short int16;
31 | typedef signed int int32;
32 |
33 | #ifndef FALSE
34 | #define FALSE 0
35 | #endif
36 |
37 | #ifndef ARRAY_NULL
38 | #define ARRAY_NULL '\0'
39 | #endif
40 |
41 | #ifndef TRUE
42 | #define TRUE 1
43 | #endif
44 |
45 | #ifndef OPEN
46 | #define OPEN 1
47 | #endif
48 |
49 | #ifndef CLOSE
50 | #define CLOSE 0
51 | #endif
52 |
53 | #ifndef NULL
54 | #define NULL ((void*) 0 )
55 | #endif
56 |
57 | #ifndef HIGH
58 | #define HIGH 1
59 | #endif
60 |
61 | #ifndef LOW
62 | #define LOW 0
63 | #endif
64 |
65 | #ifndef SUCCESS
66 | #define SUCCESS 1
67 | #endif
68 |
69 | #ifndef ERROR
70 | #define ERROR 0
71 | #endif
72 |
73 | //#define CLI() __set_PRIMASK(1) // Disable Interrupts
74 | //#define SEI() __set_PRIMASK(0) // Enable Interrupts
75 | #define CLI() ; // Disable Interrupts
76 | #define SEI() ; // Enable Interrupts
77 |
78 | #define HAL_ENABLE_INTERRUPTS() SEI() // Enable Interrupts
79 | #define HAL_DISABLE_INTERRUPTS() CLI() // Disable Interrupts
80 | #define HAL_INTERRUPTS_ARE_ENABLED() SEI() // Enable Interrupts
81 |
82 | #define HAL_ENTER_CRITICAL_SECTION() CLI()
83 | #define HAL_EXIT_CRITICAL_SECTION() SEI()
84 |
85 | #endif
86 |
--------------------------------------------------------------------------------
/OSAL/osal/osal.c:
--------------------------------------------------------------------------------
1 | #include "osal.h"
2 | #include "osal_event.h"
3 | #include "osal_memory.h"
4 |
5 | #include
6 |
7 | osal_msg_q_t osal_qHead;
8 |
9 | /*********************************************************************
10 | * @fn osal_init_system
11 | *
12 | * @brief
13 | *
14 | * This function initializes the "task" system by creating the
15 | * tasks defined in the task table (OSAL_Tasks.h).
16 | *
17 | * @param void
18 | *
19 | * @return ZSUCCESS
20 | */
21 | uint8 osal_init_system( void )
22 | {
23 | // Initialize the Memory Allocation System
24 | osal_mem_init();
25 |
26 | // Initialize the message queue
27 | osal_qHead = NULL;
28 |
29 | #if defined( OSAL_TOTAL_MEM )
30 | osal_msg_cnt = 0;
31 | #endif
32 |
33 | osalTimerInit();
34 | osal_init_TaskHead();
35 |
36 | return ( ZSUCCESS );
37 | }
38 |
39 | /*********************************************************************
40 | * @fn osal_start_system
41 | *
42 | * @brief
43 | *
44 | * This function is the main loop function of the task system. It
45 | * will look through all task events and call the task_event_processor()
46 | * function for the task with the event. If there are no events (for
47 | * all tasks), this function puts the processor into Sleep.
48 | * This Function doesn't return.
49 | *
50 | * @param void
51 | *
52 | * @return none
53 | */
54 | void osal_start_system( void )
55 | {
56 | uint16 events;
57 | uint16 retEvents;
58 |
59 | while(1)
60 | {
61 | TaskActive = osalNextActiveTask();
62 | if ( TaskActive )
63 | {
64 | HAL_ENTER_CRITICAL_SECTION();
65 | events = TaskActive->events;
66 | // Clear the Events for this task
67 | TaskActive->events = 0;
68 | HAL_EXIT_CRITICAL_SECTION();
69 |
70 | if ( events != 0 )
71 | {
72 | // Call the task to process the event(s)
73 | if ( TaskActive->pfnEventProcessor )
74 | {
75 | retEvents = (TaskActive->pfnEventProcessor)( TaskActive->taskID, events );
76 |
77 | // Add back unprocessed events to the current task
78 | HAL_ENTER_CRITICAL_SECTION();
79 | TaskActive->events |= retEvents;
80 | HAL_EXIT_CRITICAL_SECTION();
81 | }
82 | }
83 | }
84 | }
85 | }
86 |
87 | /*********************************************************************
88 | * @fn osal_strlen
89 | *
90 | * @brief
91 | *
92 | * Calculates the length of a string. The string must be null
93 | * terminated.
94 | *
95 | * @param char *pString - pointer to text string
96 | *
97 | * @return int - number of characters
98 | */
99 | int osal_strlen( char *pString )
100 | {
101 | return (int)( strlen( pString ) );
102 | }
103 |
104 | /*********************************************************************
105 | * @fn osal_memcpy
106 | *
107 | * @brief
108 | *
109 | * Generic memory copy.
110 | *
111 | * Note: This function differs from the standard memcpy(), since
112 | * it returns the pointer to the next destination uint8. The
113 | * standard memcpy() returns the original destination address.
114 | *
115 | * @param dst - destination address
116 | * @param src - source address
117 | * @param len - number of bytes to copy
118 | *
119 | * @return pointer to end of destination buffer
120 | */
121 | void *osal_memcpy( void *dst, const void *src, unsigned int len )
122 | {
123 | uint8 *pDst;
124 | const uint8 *pSrc;
125 |
126 | pSrc = src;
127 | pDst = dst;
128 |
129 | while ( len-- )
130 | *pDst++ = *pSrc++;
131 |
132 | return ( pDst );
133 | }
134 |
135 | /*********************************************************************
136 | * @fn osal_revmemcpy
137 | *
138 | * @brief Generic reverse memory copy. Starts at the end of the
139 | * source buffer, by taking the source address pointer and moving
140 | * pointer ahead "len" bytes, then decrementing the pointer.
141 | *
142 | * Note: This function differs from the standard memcpy(), since
143 | * it returns the pointer to the next destination uint8. The
144 | * standard memcpy() returns the original destination address.
145 | *
146 | * @param dst - destination address
147 | * @param src - source address
148 | * @param len - number of bytes to copy
149 | *
150 | * @return pointer to end of destination buffer
151 | */
152 | void *osal_revmemcpy( void *dst, const void *src, unsigned int len )
153 | {
154 | uint8 *pDst;
155 | const uint8 *pSrc;
156 |
157 | pSrc = src;
158 | pSrc += (len-1);
159 | pDst = dst;
160 |
161 | while ( len-- )
162 | *pDst++ = *pSrc--;
163 |
164 | return ( pDst );
165 | }
166 |
167 | /*********************************************************************
168 | * @fn osal_memdup
169 | *
170 | * @brief Allocates a buffer [with osal_mem_alloc()] and copies
171 | * the src buffer into the newly allocated space.
172 | *
173 | * @param src - source address
174 | * @param len - number of bytes to copy
175 | *
176 | * @return pointer to the new allocated buffer, or NULL if
177 | * allocation problem.
178 | */
179 | void *osal_memdup( const void *src, unsigned int len )
180 | {
181 | uint8 *pDst;
182 |
183 | pDst = osal_mem_alloc( len );
184 | if ( pDst )
185 | {
186 | osal_memcpy( pDst, src, len );
187 | }
188 |
189 | return ( (void *)pDst );
190 | }
191 |
192 | /*********************************************************************
193 | * @fn osal_memcmp
194 | *
195 | * @brief
196 | *
197 | * Generic memory compare.
198 | *
199 | * @param src1 - source 1 addrexx
200 | * @param src2 - source 2 address
201 | * @param len - number of bytes to compare
202 | *
203 | * @return TRUE - same, FALSE - different
204 | */
205 | uint8 osal_memcmp( const void *src1, const void *src2, unsigned int len )
206 | {
207 | const uint8 *pSrc1;
208 | const uint8 *pSrc2;
209 |
210 | pSrc1 = src1;
211 | pSrc2 = src2;
212 |
213 | while ( len-- )
214 | {
215 | if( *pSrc1++ != *pSrc2++ )
216 | return FALSE;
217 | }
218 | return TRUE;
219 | }
220 |
221 | /*********************************************************************
222 | * @fn osal_memset
223 | *
224 | * @brief
225 | *
226 | * Set memory buffer to value.
227 | *
228 | * @param dest - pointer to buffer
229 | * @param value - what to set each uint8 of the message
230 | * @param size - how big
231 | *
232 | * @return pointer to destination buffer
233 | */
234 | void *osal_memset( void *dest, uint8 value, int len )
235 | {
236 | return memset( dest, value, len );
237 | }
238 |
--------------------------------------------------------------------------------
/OSAL/osal/osal_event.c:
--------------------------------------------------------------------------------
1 | #include "osal_event.h"
2 | #include "osal_memory.h"
3 |
4 | OsalTadkREC_t *TaskHead;
5 | OsalTadkREC_t *TaskActive;
6 |
7 | uint8 Task_id; //任务ID统计
8 | uint8 tasksCnt; //任务数量统计
9 |
10 | /*********************************************************************
11 | * @fn osal_set_event
12 | *
13 | * @brief
14 | *
15 | * This function is called to set the event flags for a task. The
16 | * event passed in is OR'd into the task's event variable.
17 | *
18 | * @param byte task_id - receiving tasks ID
19 | * @param byte event_flag - what event to set
20 | *
21 | * @return ZSUCCESS, INVALID_TASK
22 | */
23 | uint8 osal_set_event( byte task_id, uint16 event_flag )
24 | {
25 | OsalTadkREC_t *srchTask;
26 |
27 | srchTask = osalFindTask( task_id );
28 | if ( srchTask )
29 | {
30 | // Hold off interrupts
31 | HAL_ENTER_CRITICAL_SECTION();
32 | // Stuff the event bit(s)
33 | srchTask->events |= event_flag;
34 | // Release interrupts
35 | HAL_EXIT_CRITICAL_SECTION();
36 | }
37 | else
38 | return ( INVALID_TASK );
39 |
40 | return ( ZSUCCESS );
41 | }
42 |
43 | /*********************************************************************
44 | * @fn osal_clear_event
45 | *
46 | * @brief
47 | *
48 | * This function is called to clear the event flags for a task. The
49 | * event passed in is masked out of the task's event variable.
50 | *
51 | * @param uint8 task_id - receiving tasks ID
52 | * @param uint8 event_flag - what event to clear
53 | *
54 | * @return SUCCESS, INVALID_TASK
55 | */
56 | uint8 osal_clear_event( uint8 task_id, uint16 event_flag )
57 | {
58 | OsalTadkREC_t *srchTask;
59 |
60 | srchTask = osalFindTask( task_id );
61 | if ( srchTask )
62 | {
63 | // Hold off interrupts
64 | HAL_ENTER_CRITICAL_SECTION();
65 | // Stuff the event bit(s)
66 | srchTask->events &= ~event_flag;
67 | // Release interrupts
68 | HAL_EXIT_CRITICAL_SECTION();
69 | }
70 | else
71 | return ( INVALID_TASK );
72 |
73 | return ( ZSUCCESS );
74 | }
75 | /***************************************************************************
76 | * @fn osal_init_TaskHead
77 | *
78 | * @brief init task link's head
79 | *
80 | * @param none
81 | *
82 | * @return
83 | */
84 | void osal_init_TaskHead( void )
85 | {
86 | TaskHead = (OsalTadkREC_t *)NULL;
87 | TaskActive = (OsalTadkREC_t *)NULL;
88 | Task_id = 0;
89 | }
90 |
91 | /***************************************************************************
92 | * @fn osal_Task_init
93 | *
94 | * @brief init task
95 | *
96 | * @param none
97 | *
98 | * @return
99 | */
100 | void osal_Task_init(void)
101 | {
102 | TaskActive = TaskHead;
103 | while(TaskActive)
104 | {
105 | if(TaskActive->pfnInit)
106 | {
107 | TaskActive->pfnInit(TaskActive->taskID);
108 | }
109 | TaskActive = TaskActive->next;
110 | }
111 | TaskActive = (OsalTadkREC_t *)NULL;
112 | }
113 | /***************************************************************************
114 | * @fn osal_add_Task
115 | *
116 | * @brief osal_add_Task
117 | *
118 | * @param none
119 | *
120 | * @return
121 | */
122 | void osal_add_Task(pTaskInitFn pfnInit,
123 | pTaskEventHandlerFn pfnEventProcessor,
124 | uint8 taskPriority)
125 | {
126 | OsalTadkREC_t *TaskNew;
127 | OsalTadkREC_t *TaskSech;
128 | OsalTadkREC_t **TaskPTR;
129 | TaskNew = osal_mem_alloc(sizeof(OsalTadkREC_t));
130 | if(TaskNew)
131 | {
132 | TaskNew->pfnInit = pfnInit;
133 | TaskNew->pfnEventProcessor = pfnEventProcessor;
134 | TaskNew->taskID = Task_id++;
135 | TaskNew->events = 0;
136 | TaskNew->taskPriority = taskPriority;
137 | TaskNew->next = (OsalTadkREC_t *)NULL;
138 |
139 | TaskPTR = &TaskHead;
140 | TaskSech = TaskHead;
141 |
142 | tasksCnt++; //任务数量统计
143 |
144 | while(TaskSech)
145 | {
146 | if(TaskNew->taskPriority > TaskSech->taskPriority)
147 | {
148 | TaskNew->next = TaskSech;
149 | *TaskPTR = TaskNew;
150 | return;
151 | }
152 | TaskPTR = &TaskSech->next;
153 | TaskSech = TaskSech->next;
154 | }
155 | *TaskPTR = TaskNew;
156 | }
157 | return;
158 | }
159 |
160 | /*********************************************************************
161 | * @fn osalNextActiveTask
162 | *
163 | * @brief This function will return the next active task.
164 | *
165 | * NOTE: Task queue is in priority order. We can stop at the
166 | * first task that is "ready" (events element non-zero)
167 | *
168 | * @param none
169 | *
170 | * @return pointer to the found task, NULL if not found
171 | */
172 | OsalTadkREC_t *osalNextActiveTask( void )
173 | {
174 | OsalTadkREC_t *TaskSech;
175 |
176 | // Start at the beginning
177 | TaskSech = TaskHead;
178 |
179 | // When found or not
180 | while ( TaskSech )
181 | {
182 | if ( TaskSech->events)
183 | {
184 | // task is highest priority that is ready
185 | return TaskSech;
186 | }
187 | TaskSech = TaskSech->next;
188 | }
189 | return NULL;
190 | }
191 |
192 | /*********************************************************************
193 | * @fn osalFindActiveTask
194 | *
195 | * @brief This function will return the taskid task.
196 | *
197 | * NOTE: Task queue is in priority order. We can stop at the
198 | * first task that is "ready" (events element non-zero)
199 | *
200 | * @param task_id
201 | *
202 | * @return pointer to the found task, NULL if not found
203 | */
204 |
205 | OsalTadkREC_t *osalFindTask( uint8 taskID )
206 | {
207 | OsalTadkREC_t *TaskSech;
208 | TaskSech = TaskHead;
209 | while(TaskSech)
210 | {
211 | if(TaskSech->taskID == taskID)
212 | {
213 | return (TaskSech);
214 | }
215 | TaskSech = TaskSech->next;
216 | }
217 | return ((OsalTadkREC_t *)NULL);
218 | }
219 |
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/OSAL/readme.txt:
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/OSAL/动态内存管理拓展.txt:
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/README.txt:
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1 | STM32F1工程模板，运行OSAL操作系统，基于linux-arm-gcc交叉编译环境开发，编译器版本gcc-arm-none-eabi-5_4-2016q2
2 |
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/STM32F10x_FWLib/inc/misc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file misc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the miscellaneous
8 | * firmware library functions (add-on to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __MISC_H
25 | #define __MISC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup MISC
39 | * @{
40 | */
41 |
42 | /** @defgroup MISC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief NVIC Init Structure definition
48 | */
49 |
50 | typedef struct
51 | {
52 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
53 | This parameter can be a value of @ref IRQn_Type
54 | (For the complete STM32 Devices IRQ Channels list, please
55 | refer to stm32f10x.h file) */
56 |
57 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
58 | specified in NVIC_IRQChannel. This parameter can be a value
59 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */
60 |
61 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
62 | in NVIC_IRQChannel. This parameter can be a value
63 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */
64 |
65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
66 | will be enabled or disabled.
67 | This parameter can be set either to ENABLE or DISABLE */
68 | } NVIC_InitTypeDef;
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup NVIC_Priority_Table
75 | * @{
76 | */
77 |
78 | /**
79 | @code
80 | The table below gives the allowed values of the pre-emption priority and subpriority according
81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
82 | ============================================================================================================================
83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
84 | ============================================================================================================================
85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
86 | | | | 4 bits for subpriority
87 | ----------------------------------------------------------------------------------------------------------------------------
88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
89 | | | | 3 bits for subpriority
90 | ----------------------------------------------------------------------------------------------------------------------------
91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
92 | | | | 2 bits for subpriority
93 | ----------------------------------------------------------------------------------------------------------------------------
94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
95 | | | | 1 bits for subpriority
96 | ----------------------------------------------------------------------------------------------------------------------------
97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
98 | | | | 0 bits for subpriority
99 | ============================================================================================================================
100 | @endcode
101 | */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /** @defgroup MISC_Exported_Constants
108 | * @{
109 | */
110 |
111 | /** @defgroup Vector_Table_Base
112 | * @{
113 | */
114 |
115 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
116 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
117 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
118 | ((VECTTAB) == NVIC_VectTab_FLASH))
119 | /**
120 | * @}
121 | */
122 |
123 | /** @defgroup System_Low_Power
124 | * @{
125 | */
126 |
127 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
128 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
129 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
130 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
131 | ((LP) == NVIC_LP_SLEEPDEEP) || \
132 | ((LP) == NVIC_LP_SLEEPONEXIT))
133 | /**
134 | * @}
135 | */
136 |
137 | /** @defgroup Preemption_Priority_Group
138 | * @{
139 | */
140 |
141 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
142 | 4 bits for subpriority */
143 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
144 | 3 bits for subpriority */
145 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
146 | 2 bits for subpriority */
147 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
148 | 1 bits for subpriority */
149 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
150 | 0 bits for subpriority */
151 |
152 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
153 | ((GROUP) == NVIC_PriorityGroup_1) || \
154 | ((GROUP) == NVIC_PriorityGroup_2) || \
155 | ((GROUP) == NVIC_PriorityGroup_3) || \
156 | ((GROUP) == NVIC_PriorityGroup_4))
157 |
158 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
159 |
160 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
161 |
162 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
163 |
164 | /**
165 | * @}
166 | */
167 |
168 | /** @defgroup SysTick_clock_source
169 | * @{
170 | */
171 |
172 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
173 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
174 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
175 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
176 | /**
177 | * @}
178 | */
179 |
180 | /**
181 | * @}
182 | */
183 |
184 | /** @defgroup MISC_Exported_Macros
185 | * @{
186 | */
187 |
188 | /**
189 | * @}
190 | */
191 |
192 | /** @defgroup MISC_Exported_Functions
193 | * @{
194 | */
195 |
196 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
197 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
198 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
200 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
201 |
202 | #ifdef __cplusplus
203 | }
204 | #endif
205 |
206 | #endif /* __MISC_H */
207 |
208 | /**
209 | * @}
210 | */
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /**
217 | * @}
218 | */
219 |
220 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
221 |
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/STM32F10x_FWLib/inc/stm32f10x_bkp.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_bkp.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the BKP firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_BKP_H
25 | #define __STM32F10x_BKP_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup BKP
39 | * @{
40 | */
41 |
42 | /** @defgroup BKP_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup BKP_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup Tamper_Pin_active_level
55 | * @{
56 | */
57 |
58 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000)
59 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
60 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
61 | ((LEVEL) == BKP_TamperPinLevel_Low))
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
67 | * @{
68 | */
69 |
70 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000)
71 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
72 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
73 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
74 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
75 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
76 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
77 | ((SOURCE) == BKP_RTCOutputSource_Second))
78 | /**
79 | * @}
80 | */
81 |
82 | /** @defgroup Data_Backup_Register
83 | * @{
84 | */
85 |
86 | #define BKP_DR1 ((uint16_t)0x0004)
87 | #define BKP_DR2 ((uint16_t)0x0008)
88 | #define BKP_DR3 ((uint16_t)0x000C)
89 | #define BKP_DR4 ((uint16_t)0x0010)
90 | #define BKP_DR5 ((uint16_t)0x0014)
91 | #define BKP_DR6 ((uint16_t)0x0018)
92 | #define BKP_DR7 ((uint16_t)0x001C)
93 | #define BKP_DR8 ((uint16_t)0x0020)
94 | #define BKP_DR9 ((uint16_t)0x0024)
95 | #define BKP_DR10 ((uint16_t)0x0028)
96 | #define BKP_DR11 ((uint16_t)0x0040)
97 | #define BKP_DR12 ((uint16_t)0x0044)
98 | #define BKP_DR13 ((uint16_t)0x0048)
99 | #define BKP_DR14 ((uint16_t)0x004C)
100 | #define BKP_DR15 ((uint16_t)0x0050)
101 | #define BKP_DR16 ((uint16_t)0x0054)
102 | #define BKP_DR17 ((uint16_t)0x0058)
103 | #define BKP_DR18 ((uint16_t)0x005C)
104 | #define BKP_DR19 ((uint16_t)0x0060)
105 | #define BKP_DR20 ((uint16_t)0x0064)
106 | #define BKP_DR21 ((uint16_t)0x0068)
107 | #define BKP_DR22 ((uint16_t)0x006C)
108 | #define BKP_DR23 ((uint16_t)0x0070)
109 | #define BKP_DR24 ((uint16_t)0x0074)
110 | #define BKP_DR25 ((uint16_t)0x0078)
111 | #define BKP_DR26 ((uint16_t)0x007C)
112 | #define BKP_DR27 ((uint16_t)0x0080)
113 | #define BKP_DR28 ((uint16_t)0x0084)
114 | #define BKP_DR29 ((uint16_t)0x0088)
115 | #define BKP_DR30 ((uint16_t)0x008C)
116 | #define BKP_DR31 ((uint16_t)0x0090)
117 | #define BKP_DR32 ((uint16_t)0x0094)
118 | #define BKP_DR33 ((uint16_t)0x0098)
119 | #define BKP_DR34 ((uint16_t)0x009C)
120 | #define BKP_DR35 ((uint16_t)0x00A0)
121 | #define BKP_DR36 ((uint16_t)0x00A4)
122 | #define BKP_DR37 ((uint16_t)0x00A8)
123 | #define BKP_DR38 ((uint16_t)0x00AC)
124 | #define BKP_DR39 ((uint16_t)0x00B0)
125 | #define BKP_DR40 ((uint16_t)0x00B4)
126 | #define BKP_DR41 ((uint16_t)0x00B8)
127 | #define BKP_DR42 ((uint16_t)0x00BC)
128 |
129 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
130 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
131 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
132 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
133 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
134 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
135 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
136 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
137 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
138 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
139 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
140 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
141 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
142 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
143 |
144 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
145 | /**
146 | * @}
147 | */
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /** @defgroup BKP_Exported_Macros
154 | * @{
155 | */
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /** @defgroup BKP_Exported_Functions
162 | * @{
163 | */
164 |
165 | void BKP_DeInit(void);
166 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
167 | void BKP_TamperPinCmd(FunctionalState NewState);
168 | void BKP_ITConfig(FunctionalState NewState);
169 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
170 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
171 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
172 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
173 | FlagStatus BKP_GetFlagStatus(void);
174 | void BKP_ClearFlag(void);
175 | ITStatus BKP_GetITStatus(void);
176 | void BKP_ClearITPendingBit(void);
177 |
178 | #ifdef __cplusplus
179 | }
180 | #endif
181 |
182 | #endif /* __STM32F10x_BKP_H */
183 | /**
184 | * @}
185 | */
186 |
187 | /**
188 | * @}
189 | */
190 |
191 | /**
192 | * @}
193 | */
194 |
195 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
196 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_cec.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_cec.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the CEC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CEC_H
25 | #define __STM32F10x_CEC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup CEC
39 | * @{
40 | */
41 |
42 |
43 | /** @defgroup CEC_Exported_Types
44 | * @{
45 | */
46 |
47 | /**
48 | * @brief CEC Init structure definition
49 | */
50 | typedef struct
51 | {
52 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
53 | This parameter can be a value of @ref CEC_BitTiming_Mode */
54 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
55 | This parameter can be a value of @ref CEC_BitPeriod_Mode */
56 | }CEC_InitTypeDef;
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /** @defgroup CEC_Exported_Constants
63 | * @{
64 | */
65 |
66 | /** @defgroup CEC_BitTiming_Mode
67 | * @{
68 | */
69 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
70 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
71 |
72 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
73 | ((MODE) == CEC_BitTimingErrFreeMode))
74 | /**
75 | * @}
76 | */
77 |
78 | /** @defgroup CEC_BitPeriod_Mode
79 | * @{
80 | */
81 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
82 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
83 |
84 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
85 | ((MODE) == CEC_BitPeriodFlexibleMode))
86 | /**
87 | * @}
88 | */
89 |
90 |
91 | /** @defgroup CEC_interrupts_definition
92 | * @{
93 | */
94 | #define CEC_IT_TERR CEC_CSR_TERR
95 | #define CEC_IT_TBTRF CEC_CSR_TBTRF
96 | #define CEC_IT_RERR CEC_CSR_RERR
97 | #define CEC_IT_RBTF CEC_CSR_RBTF
98 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
99 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
100 | /**
101 | * @}
102 | */
103 |
104 |
105 | /** @defgroup CEC_Own_Address
106 | * @{
107 | */
108 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
109 | /**
110 | * @}
111 | */
112 |
113 | /** @defgroup CEC_Prescaler
114 | * @{
115 | */
116 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
117 |
118 | /**
119 | * @}
120 | */
121 |
122 | /** @defgroup CEC_flags_definition
123 | * @{
124 | */
125 |
126 | /**
127 | * @brief ESR register flags
128 | */
129 | #define CEC_FLAG_BTE ((uint32_t)0x10010000)
130 | #define CEC_FLAG_BPE ((uint32_t)0x10020000)
131 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
132 | #define CEC_FLAG_SBE ((uint32_t)0x10080000)
133 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000)
134 | #define CEC_FLAG_LINE ((uint32_t)0x10200000)
135 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
136 |
137 | /**
138 | * @brief CSR register flags
139 | */
140 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002)
141 | #define CEC_FLAG_TERR ((uint32_t)0x00000004)
142 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
143 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010)
144 | #define CEC_FLAG_REOM ((uint32_t)0x00000020)
145 | #define CEC_FLAG_RERR ((uint32_t)0x00000040)
146 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080)
147 |
148 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
149 |
150 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
151 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
152 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
153 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
154 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
155 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
156 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /** @defgroup CEC_Exported_Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /** @defgroup CEC_Exported_Functions
175 | * @{
176 | */
177 | void CEC_DeInit(void);
178 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
179 | void CEC_Cmd(FunctionalState NewState);
180 | void CEC_ITConfig(FunctionalState NewState);
181 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
182 | void CEC_SetPrescaler(uint16_t CEC_Prescaler);
183 | void CEC_SendDataByte(uint8_t Data);
184 | uint8_t CEC_ReceiveDataByte(void);
185 | void CEC_StartOfMessage(void);
186 | void CEC_EndOfMessageCmd(FunctionalState NewState);
187 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
188 | void CEC_ClearFlag(uint32_t CEC_FLAG);
189 | ITStatus CEC_GetITStatus(uint8_t CEC_IT);
190 | void CEC_ClearITPendingBit(uint16_t CEC_IT);
191 |
192 | #ifdef __cplusplus
193 | }
194 | #endif
195 |
196 | #endif /* __STM32F10x_CEC_H */
197 |
198 | /**
199 | * @}
200 | */
201 |
202 | /**
203 | * @}
204 | */
205 |
206 | /**
207 | * @}
208 | */
209 |
210 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
211 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CRC_H
25 | #define __STM32F10x_CRC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup CRC
39 | * @{
40 | */
41 |
42 | /** @defgroup CRC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup CRC_Exported_Constants
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup CRC_Exported_Macros
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup CRC_Exported_Functions
67 | * @{
68 | */
69 |
70 | void CRC_ResetDR(void);
71 | uint32_t CRC_CalcCRC(uint32_t Data);
72 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
73 | uint32_t CRC_GetCRC(void);
74 | void CRC_SetIDRegister(uint8_t IDValue);
75 | uint8_t CRC_GetIDRegister(void);
76 |
77 | #ifdef __cplusplus
78 | }
79 | #endif
80 |
81 | #endif /* __STM32F10x_CRC_H */
82 | /**
83 | * @}
84 | */
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
95 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the DBGMCU
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_DBGMCU_H
25 | #define __STM32F10x_DBGMCU_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup DBGMCU
39 | * @{
40 | */
41 |
42 | /** @defgroup DBGMCU_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup DBGMCU_Exported_Constants
51 | * @{
52 | */
53 |
54 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
55 | #define DBGMCU_STOP ((uint32_t)0x00000002)
56 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
57 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
58 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
59 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
60 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
61 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
62 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
63 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
64 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
65 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
66 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
67 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
68 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
69 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
70 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
71 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
72 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
73 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
74 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
75 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
76 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
77 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
78 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
79 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
80 |
81 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup DBGMCU_Exported_Macros
87 | * @{
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup DBGMCU_Exported_Functions
95 | * @{
96 | */
97 |
98 | uint32_t DBGMCU_GetREVID(void);
99 | uint32_t DBGMCU_GetDEVID(void);
100 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
101 |
102 | #ifdef __cplusplus
103 | }
104 | #endif
105 |
106 | #endif /* __STM32F10x_DBGMCU_H */
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
120 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_exti.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the EXTI firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_EXTI_H
25 | #define __STM32F10x_EXTI_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup EXTI
39 | * @{
40 | */
41 |
42 | /** @defgroup EXTI_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief EXTI mode enumeration
48 | */
49 |
50 | typedef enum
51 | {
52 | EXTI_Mode_Interrupt = 0x00,
53 | EXTI_Mode_Event = 0x04
54 | }EXTIMode_TypeDef;
55 |
56 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
57 |
58 | /**
59 | * @brief EXTI Trigger enumeration
60 | */
61 |
62 | typedef enum
63 | {
64 | EXTI_Trigger_Rising = 0x08,
65 | EXTI_Trigger_Falling = 0x0C,
66 | EXTI_Trigger_Rising_Falling = 0x10
67 | }EXTITrigger_TypeDef;
68 |
69 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
70 | ((TRIGGER) == EXTI_Trigger_Falling) || \
71 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
72 | /**
73 | * @brief EXTI Init Structure definition
74 | */
75 |
76 | typedef struct
77 | {
78 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
79 | This parameter can be any combination of @ref EXTI_Lines */
80 |
81 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
82 | This parameter can be a value of @ref EXTIMode_TypeDef */
83 |
84 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
85 | This parameter can be a value of @ref EXTIMode_TypeDef */
86 |
87 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
88 | This parameter can be set either to ENABLE or DISABLE */
89 | }EXTI_InitTypeDef;
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup EXTI_Exported_Constants
96 | * @{
97 | */
98 |
99 | /** @defgroup EXTI_Lines
100 | * @{
101 | */
102 |
103 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
104 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
105 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
106 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
107 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
108 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
109 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
110 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
111 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
112 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
113 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
114 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
115 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
116 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
117 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
118 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
119 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
120 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
121 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
122 | Wakeup from suspend event */
123 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
124 |
125 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
126 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
127 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
128 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
129 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
130 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
131 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
132 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
133 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
134 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
135 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
136 |
137 |
138 | /**
139 | * @}
140 | */
141 |
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup EXTI_Exported_Macros
147 | * @{
148 | */
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /** @defgroup EXTI_Exported_Functions
155 | * @{
156 | */
157 |
158 | void EXTI_DeInit(void);
159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
162 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
163 | void EXTI_ClearFlag(uint32_t EXTI_Line);
164 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
165 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
166 |
167 | #ifdef __cplusplus
168 | }
169 | #endif
170 |
171 | #endif /* __STM32F10x_EXTI_H */
172 | /**
173 | * @}
174 | */
175 |
176 | /**
177 | * @}
178 | */
179 |
180 | /**
181 | * @}
182 | */
183 |
184 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
185 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_IWDG_H
25 | #define __STM32F10x_IWDG_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup IWDG
39 | * @{
40 | */
41 |
42 | /** @defgroup IWDG_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup IWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup IWDG_WriteAccess
55 | * @{
56 | */
57 |
58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
61 | ((ACCESS) == IWDG_WriteAccess_Disable))
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup IWDG_prescaler
67 | * @{
68 | */
69 |
70 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
71 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
72 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
73 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
74 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
75 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
76 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
77 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
78 | ((PRESCALER) == IWDG_Prescaler_8) || \
79 | ((PRESCALER) == IWDG_Prescaler_16) || \
80 | ((PRESCALER) == IWDG_Prescaler_32) || \
81 | ((PRESCALER) == IWDG_Prescaler_64) || \
82 | ((PRESCALER) == IWDG_Prescaler_128)|| \
83 | ((PRESCALER) == IWDG_Prescaler_256))
84 | /**
85 | * @}
86 | */
87 |
88 | /** @defgroup IWDG_Flag
89 | * @{
90 | */
91 |
92 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
93 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
94 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
95 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
96 | /**
97 | * @}
98 | */
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | /** @defgroup IWDG_Exported_Macros
105 | * @{
106 | */
107 |
108 | /**
109 | * @}
110 | */
111 |
112 | /** @defgroup IWDG_Exported_Functions
113 | * @{
114 | */
115 |
116 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
117 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
118 | void IWDG_SetReload(uint16_t Reload);
119 | void IWDG_ReloadCounter(void);
120 | void IWDG_Enable(void);
121 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
122 |
123 | #ifdef __cplusplus
124 | }
125 | #endif
126 |
127 | #endif /* __STM32F10x_IWDG_H */
128 | /**
129 | * @}
130 | */
131 |
132 | /**
133 | * @}
134 | */
135 |
136 | /**
137 | * @}
138 | */
139 |
140 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
141 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_PWR_H
25 | #define __STM32F10x_PWR_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup PWR
39 | * @{
40 | */
41 |
42 | /** @defgroup PWR_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup PWR_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup PVD_detection_level
55 | * @{
56 | */
57 |
58 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
59 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
60 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
61 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
62 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
63 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
64 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
65 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
67 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
68 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
69 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup Regulator_state_is_STOP_mode
75 | * @{
76 | */
77 |
78 | #define PWR_Regulator_ON ((uint32_t)0x00000000)
79 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001)
80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
81 | ((REGULATOR) == PWR_Regulator_LowPower))
82 | /**
83 | * @}
84 | */
85 |
86 | /** @defgroup STOP_mode_entry
87 | * @{
88 | */
89 |
90 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
91 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup PWR_Flag
99 | * @{
100 | */
101 |
102 | #define PWR_FLAG_WU ((uint32_t)0x00000001)
103 | #define PWR_FLAG_SB ((uint32_t)0x00000002)
104 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
106 | ((FLAG) == PWR_FLAG_PVDO))
107 |
108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
109 | /**
110 | * @}
111 | */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /** @defgroup PWR_Exported_Macros
118 | * @{
119 | */
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /** @defgroup PWR_Exported_Functions
126 | * @{
127 | */
128 |
129 | void PWR_DeInit(void);
130 | void PWR_BackupAccessCmd(FunctionalState NewState);
131 | void PWR_PVDCmd(FunctionalState NewState);
132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
133 | void PWR_WakeUpPinCmd(FunctionalState NewState);
134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
135 | void PWR_EnterSTANDBYMode(void);
136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
137 | void PWR_ClearFlag(uint32_t PWR_FLAG);
138 |
139 | #ifdef __cplusplus
140 | }
141 | #endif
142 |
143 | #endif /* __STM32F10x_PWR_H */
144 | /**
145 | * @}
146 | */
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
157 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_rtc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rtc.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the RTC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_RTC_H
25 | #define __STM32F10x_RTC_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup RTC
39 | * @{
40 | */
41 |
42 | /** @defgroup RTC_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup RTC_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup RTC_interrupts_define
55 | * @{
56 | */
57 |
58 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
59 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
60 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
61 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
62 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
63 | ((IT) == RTC_IT_SEC))
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup RTC_interrupts_flags
69 | * @{
70 | */
71 |
72 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
73 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
74 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
75 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
76 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
77 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
78 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
79 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
80 | ((FLAG) == RTC_FLAG_SEC))
81 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @defgroup RTC_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @defgroup RTC_Exported_Functions
100 | * @{
101 | */
102 |
103 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
104 | void RTC_EnterConfigMode(void);
105 | void RTC_ExitConfigMode(void);
106 | uint32_t RTC_GetCounter(void);
107 | void RTC_SetCounter(uint32_t CounterValue);
108 | void RTC_SetPrescaler(uint32_t PrescalerValue);
109 | void RTC_SetAlarm(uint32_t AlarmValue);
110 | uint32_t RTC_GetDivider(void);
111 | void RTC_WaitForLastTask(void);
112 | void RTC_WaitForSynchro(void);
113 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
114 | void RTC_ClearFlag(uint16_t RTC_FLAG);
115 | ITStatus RTC_GetITStatus(uint16_t RTC_IT);
116 | void RTC_ClearITPendingBit(uint16_t RTC_IT);
117 |
118 | #ifdef __cplusplus
119 | }
120 | #endif
121 |
122 | #endif /* __STM32F10x_RTC_H */
123 | /**
124 | * @}
125 | */
126 |
127 | /**
128 | * @}
129 | */
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
136 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_wwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file contains all the functions prototypes for the WWDG firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_WWDG_H
25 | #define __STM32F10x_WWDG_H
26 |
27 | #ifdef __cplusplus
28 | extern "C" {
29 | #endif
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 |
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @addtogroup WWDG
39 | * @{
40 | */
41 |
42 | /** @defgroup WWDG_Exported_Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup WWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup WWDG_Prescaler
55 | * @{
56 | */
57 |
58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
63 | ((PRESCALER) == WWDG_Prescaler_2) || \
64 | ((PRESCALER) == WWDG_Prescaler_4) || \
65 | ((PRESCALER) == WWDG_Prescaler_8))
66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup WWDG_Exported_Macros
78 | * @{
79 | */
80 | /**
81 | * @}
82 | */
83 |
84 | /** @defgroup WWDG_Exported_Functions
85 | * @{
86 | */
87 |
88 | void WWDG_DeInit(void);
89 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
90 | void WWDG_SetWindowValue(uint8_t WindowValue);
91 | void WWDG_EnableIT(void);
92 | void WWDG_SetCounter(uint8_t Counter);
93 | void WWDG_Enable(uint8_t Counter);
94 | FlagStatus WWDG_GetFlagStatus(void);
95 | void WWDG_ClearFlag(void);
96 |
97 | #ifdef __cplusplus
98 | }
99 | #endif
100 |
101 | #endif /* __STM32F10x_WWDG_H */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
116 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/misc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file misc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the miscellaneous firmware functions (add-on
8 | * to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 | *
19 | * © COPYRIGHT 2011 STMicroelectronics
20 | ******************************************************************************
21 | */
22 |
23 | /* Includes ------------------------------------------------------------------*/
24 | #include "misc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup MISC
31 | * @brief MISC driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup MISC_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup MISC_Private_Defines
44 | * @{
45 | */
46 |
47 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
48 | /**
49 | * @}
50 | */
51 |
52 | /** @defgroup MISC_Private_Macros
53 | * @{
54 | */
55 |
56 | /**
57 | * @}
58 | */
59 |
60 | /** @defgroup MISC_Private_Variables
61 | * @{
62 | */
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup MISC_Private_FunctionPrototypes
69 | * @{
70 | */
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup MISC_Private_Functions
77 | * @{
78 | */
79 |
80 | /**
81 | * @brief Configures the priority grouping: pre-emption priority and subpriority.
82 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
83 | * This parameter can be one of the following values:
84 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
85 | * 4 bits for subpriority
86 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
87 | * 3 bits for subpriority
88 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
89 | * 2 bits for subpriority
90 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
91 | * 1 bits for subpriority
92 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
93 | * 0 bits for subpriority
94 | * @retval None
95 | */
96 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
97 | {
98 | /* Check the parameters */
99 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
100 |
101 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
102 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
103 | }
104 |
105 | /**
106 | * @brief Initializes the NVIC peripheral according to the specified
107 | * parameters in the NVIC_InitStruct.
108 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
109 | * the configuration information for the specified NVIC peripheral.
110 | * @retval None
111 | */
112 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
113 | {
114 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
115 |
116 | /* Check the parameters */
117 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
118 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
119 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
120 |
121 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
122 | {
123 | /* Compute the Corresponding IRQ Priority --------------------------------*/
124 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
125 | tmppre = (0x4 - tmppriority);
126 | tmpsub = tmpsub >> tmppriority;
127 |
128 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
129 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
130 | tmppriority = tmppriority << 0x04;
131 |
132 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
133 |
134 | /* Enable the Selected IRQ Channels --------------------------------------*/
135 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
136 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
137 | }
138 | else
139 | {
140 | /* Disable the Selected IRQ Channels -------------------------------------*/
141 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
143 | }
144 | }
145 |
146 | /**
147 | * @brief Sets the vector table location and Offset.
148 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
149 | * This parameter can be one of the following values:
150 | * @arg NVIC_VectTab_RAM
151 | * @arg NVIC_VectTab_FLASH
152 | * @param Offset: Vector Table base offset field. This value must be a multiple
153 | * of 0x200.
154 | * @retval None
155 | */
156 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
157 | {
158 | /* Check the parameters */
159 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
160 | assert_param(IS_NVIC_OFFSET(Offset));
161 |
162 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
163 | }
164 |
165 | /**
166 | * @brief Selects the condition for the system to enter low power mode.
167 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
168 | * This parameter can be one of the following values:
169 | * @arg NVIC_LP_SEVONPEND
170 | * @arg NVIC_LP_SLEEPDEEP
171 | * @arg NVIC_LP_SLEEPONEXIT
172 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
173 | * @retval None
174 | */
175 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
176 | {
177 | /* Check the parameters */
178 | assert_param(IS_NVIC_LP(LowPowerMode));
179 | assert_param(IS_FUNCTIONAL_STATE(NewState));
180 |
181 | if (NewState != DISABLE)
182 | {
183 | SCB->SCR |= LowPowerMode;
184 | }
185 | else
186 | {
187 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
188 | }
189 | }
190 |
191 | /**
192 | * @brief Configures the SysTick clock source.
193 | * @param SysTick_CLKSource: specifies the SysTick clock source.
194 | * This parameter can be one of the following values:
195 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
196 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
197 | * @retval None
198 | */
199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
200 | {
201 | /* Check the parameters */
202 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
203 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
204 | {
205 | SysTick->CTRL |= SysTick_CLKSource_HCLK;
206 | }
207 | else
208 | {
209 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
210 | }
211 | }
212 |
213 | /**
214 | * @}
215 | */
216 |
217 | /**
218 | * @}
219 | */
220 |
221 | /**
222 | * @}
223 | */
224 |
225 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
226 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_bkp.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_bkp.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the BKP firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_bkp.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup BKP
31 | * @brief BKP driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup BKP_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup BKP_Private_Defines
44 | * @{
45 | */
46 |
47 | /* ------------ BKP registers bit address in the alias region --------------- */
48 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
49 |
50 | /* --- CR Register ----*/
51 |
52 | /* Alias word address of TPAL bit */
53 | #define CR_OFFSET (BKP_OFFSET + 0x30)
54 | #define TPAL_BitNumber 0x01
55 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
56 |
57 | /* Alias word address of TPE bit */
58 | #define TPE_BitNumber 0x00
59 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
60 |
61 | /* --- CSR Register ---*/
62 |
63 | /* Alias word address of TPIE bit */
64 | #define CSR_OFFSET (BKP_OFFSET + 0x34)
65 | #define TPIE_BitNumber 0x02
66 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
67 |
68 | /* Alias word address of TIF bit */
69 | #define TIF_BitNumber 0x09
70 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
71 |
72 | /* Alias word address of TEF bit */
73 | #define TEF_BitNumber 0x08
74 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
75 |
76 | /* ---------------------- BKP registers bit mask ------------------------ */
77 |
78 | /* RTCCR register bit mask */
79 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80)
80 | #define RTCCR_MASK ((uint16_t)0xFC7F)
81 |
82 | /**
83 | * @}
84 | */
85 |
86 |
87 | /** @defgroup BKP_Private_Macros
88 | * @{
89 | */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup BKP_Private_Variables
96 | * @{
97 | */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup BKP_Private_FunctionPrototypes
104 | * @{
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /** @defgroup BKP_Private_Functions
112 | * @{
113 | */
114 |
115 | /**
116 | * @brief Deinitializes the BKP peripheral registers to their default reset values.
117 | * @param None
118 | * @retval None
119 | */
120 | void BKP_DeInit(void)
121 | {
122 | RCC_BackupResetCmd(ENABLE);
123 | RCC_BackupResetCmd(DISABLE);
124 | }
125 |
126 | /**
127 | * @brief Configures the Tamper Pin active level.
128 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
129 | * This parameter can be one of the following values:
130 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
131 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
132 | * @retval None
133 | */
134 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
135 | {
136 | /* Check the parameters */
137 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
138 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
139 | }
140 |
141 | /**
142 | * @brief Enables or disables the Tamper Pin activation.
143 | * @param NewState: new state of the Tamper Pin activation.
144 | * This parameter can be: ENABLE or DISABLE.
145 | * @retval None
146 | */
147 | void BKP_TamperPinCmd(FunctionalState NewState)
148 | {
149 | /* Check the parameters */
150 | assert_param(IS_FUNCTIONAL_STATE(NewState));
151 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
152 | }
153 |
154 | /**
155 | * @brief Enables or disables the Tamper Pin Interrupt.
156 | * @param NewState: new state of the Tamper Pin Interrupt.
157 | * This parameter can be: ENABLE or DISABLE.
158 | * @retval None
159 | */
160 | void BKP_ITConfig(FunctionalState NewState)
161 | {
162 | /* Check the parameters */
163 | assert_param(IS_FUNCTIONAL_STATE(NewState));
164 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
165 | }
166 |
167 | /**
168 | * @brief Select the RTC output source to output on the Tamper pin.
169 | * @param BKP_RTCOutputSource: specifies the RTC output source.
170 | * This parameter can be one of the following values:
171 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
172 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
173 | * divided by 64 on the Tamper pin.
174 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
175 | * the Tamper pin.
176 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
177 | * the Tamper pin.
178 | * @retval None
179 | */
180 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
181 | {
182 | uint16_t tmpreg = 0;
183 | /* Check the parameters */
184 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
185 | tmpreg = BKP->RTCCR;
186 | /* Clear CCO, ASOE and ASOS bits */
187 | tmpreg &= RTCCR_MASK;
188 |
189 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
190 | tmpreg |= BKP_RTCOutputSource;
191 | /* Store the new value */
192 | BKP->RTCCR = tmpreg;
193 | }
194 |
195 | /**
196 | * @brief Sets RTC Clock Calibration value.
197 | * @param CalibrationValue: specifies the RTC Clock Calibration value.
198 | * This parameter must be a number between 0 and 0x7F.
199 | * @retval None
200 | */
201 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
202 | {
203 | uint16_t tmpreg = 0;
204 | /* Check the parameters */
205 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
206 | tmpreg = BKP->RTCCR;
207 | /* Clear CAL[6:0] bits */
208 | tmpreg &= RTCCR_CAL_MASK;
209 | /* Set CAL[6:0] bits according to CalibrationValue value */
210 | tmpreg |= CalibrationValue;
211 | /* Store the new value */
212 | BKP->RTCCR = tmpreg;
213 | }
214 |
215 | /**
216 | * @brief Writes user data to the specified Data Backup Register.
217 | * @param BKP_DR: specifies the Data Backup Register.
218 | * This parameter can be BKP_DRx where x:[1, 42]
219 | * @param Data: data to write
220 | * @retval None
221 | */
222 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
223 | {
224 | __IO uint32_t tmp = 0;
225 |
226 | /* Check the parameters */
227 | assert_param(IS_BKP_DR(BKP_DR));
228 |
229 | tmp = (uint32_t)BKP_BASE;
230 | tmp += BKP_DR;
231 |
232 | *(__IO uint32_t *) tmp = Data;
233 | }
234 |
235 | /**
236 | * @brief Reads data from the specified Data Backup Register.
237 | * @param BKP_DR: specifies the Data Backup Register.
238 | * This parameter can be BKP_DRx where x:[1, 42]
239 | * @retval The content of the specified Data Backup Register
240 | */
241 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
242 | {
243 | __IO uint32_t tmp = 0;
244 |
245 | /* Check the parameters */
246 | assert_param(IS_BKP_DR(BKP_DR));
247 |
248 | tmp = (uint32_t)BKP_BASE;
249 | tmp += BKP_DR;
250 |
251 | return (*(__IO uint16_t *) tmp);
252 | }
253 |
254 | /**
255 | * @brief Checks whether the Tamper Pin Event flag is set or not.
256 | * @param None
257 | * @retval The new state of the Tamper Pin Event flag (SET or RESET).
258 | */
259 | FlagStatus BKP_GetFlagStatus(void)
260 | {
261 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
262 | }
263 |
264 | /**
265 | * @brief Clears Tamper Pin Event pending flag.
266 | * @param None
267 | * @retval None
268 | */
269 | void BKP_ClearFlag(void)
270 | {
271 | /* Set CTE bit to clear Tamper Pin Event flag */
272 | BKP->CSR |= BKP_CSR_CTE;
273 | }
274 |
275 | /**
276 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
277 | * @param None
278 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
279 | */
280 | ITStatus BKP_GetITStatus(void)
281 | {
282 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
283 | }
284 |
285 | /**
286 | * @brief Clears Tamper Pin Interrupt pending bit.
287 | * @param None
288 | * @retval None
289 | */
290 | void BKP_ClearITPendingBit(void)
291 | {
292 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
293 | BKP->CSR |= BKP_CSR_CTI;
294 | }
295 |
296 | /**
297 | * @}
298 | */
299 |
300 | /**
301 | * @}
302 | */
303 |
304 | /**
305 | * @}
306 | */
307 |
308 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
309 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_crc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_crc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the CRC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_crc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup CRC
30 | * @brief CRC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup CRC_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup CRC_Private_Defines
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /** @defgroup CRC_Private_Macros
51 | * @{
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /** @defgroup CRC_Private_Variables
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup CRC_Private_FunctionPrototypes
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup CRC_Private_Functions
75 | * @{
76 | */
77 |
78 | /**
79 | * @brief Resets the CRC Data register (DR).
80 | * @param None
81 | * @retval None
82 | */
83 | void CRC_ResetDR(void)
84 | {
85 | /* Reset CRC generator */
86 | CRC->CR = CRC_CR_RESET;
87 | }
88 |
89 | /**
90 | * @brief Computes the 32-bit CRC of a given data word(32-bit).
91 | * @param Data: data word(32-bit) to compute its CRC
92 | * @retval 32-bit CRC
93 | */
94 | uint32_t CRC_CalcCRC(uint32_t Data)
95 | {
96 | CRC->DR = Data;
97 |
98 | return (CRC->DR);
99 | }
100 |
101 | /**
102 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
103 | * @param pBuffer: pointer to the buffer containing the data to be computed
104 | * @param BufferLength: length of the buffer to be computed
105 | * @retval 32-bit CRC
106 | */
107 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
108 | {
109 | uint32_t index = 0;
110 |
111 | for(index = 0; index < BufferLength; index++)
112 | {
113 | CRC->DR = pBuffer[index];
114 | }
115 | return (CRC->DR);
116 | }
117 |
118 | /**
119 | * @brief Returns the current CRC value.
120 | * @param None
121 | * @retval 32-bit CRC
122 | */
123 | uint32_t CRC_GetCRC(void)
124 | {
125 | return (CRC->DR);
126 | }
127 |
128 | /**
129 | * @brief Stores a 8-bit data in the Independent Data(ID) register.
130 | * @param IDValue: 8-bit value to be stored in the ID register
131 | * @retval None
132 | */
133 | void CRC_SetIDRegister(uint8_t IDValue)
134 | {
135 | CRC->IDR = IDValue;
136 | }
137 |
138 | /**
139 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register
140 | * @param None
141 | * @retval 8-bit value of the ID register
142 | */
143 | uint8_t CRC_GetIDRegister(void)
144 | {
145 | return (CRC->IDR);
146 | }
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
161 |
--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_dbgmcu.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the DBGMCU firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_dbgmcu.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup DBGMCU
30 | * @brief DBGMCU driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup DBGMCU_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup DBGMCU_Private_Defines
43 | * @{
44 | */
45 |
46 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
47 | /**
48 | * @}
49 | */
50 |
51 | /** @defgroup DBGMCU_Private_Macros
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @defgroup DBGMCU_Private_Variables
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup DBGMCU_Private_FunctionPrototypes
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup DBGMCU_Private_Functions
76 | * @{
77 | */
78 |
79 | /**
80 | * @brief Returns the device revision identifier.
81 | * @param None
82 | * @retval Device revision identifier
83 | */
84 | uint32_t DBGMCU_GetREVID(void)
85 | {
86 | return(DBGMCU->IDCODE >> 16);
87 | }
88 |
89 | /**
90 | * @brief Returns the device identifier.
91 | * @param None
92 | * @retval Device identifier
93 | */
94 | uint32_t DBGMCU_GetDEVID(void)
95 | {
96 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
97 | }
98 |
99 | /**
100 | * @brief Configures the specified peripheral and low power mode behavior
101 | * when the MCU under Debug mode.
102 | * @param DBGMCU_Periph: specifies the peripheral and low power mode.
103 | * This parameter can be any combination of the following values:
104 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
105 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
106 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
107 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
108 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
109 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
110 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
111 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
112 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
113 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
114 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
115 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
116 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
117 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
118 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
119 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
120 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
121 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
122 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
123 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
124 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
125 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
126 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
127 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
128 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
129 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
130 | * @param NewState: new state of the specified peripheral in Debug mode.
131 | * This parameter can be: ENABLE or DISABLE.
132 | * @retval None
133 | */
134 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
135 | {
136 | /* Check the parameters */
137 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
138 | assert_param(IS_FUNCTIONAL_STATE(NewState));
139 |
140 | if (NewState != DISABLE)
141 | {
142 | DBGMCU->CR |= DBGMCU_Periph;
143 | }
144 | else
145 | {
146 | DBGMCU->CR &= ~DBGMCU_Periph;
147 | }
148 | }
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /**
155 | * @}
156 | */
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
163 |
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/STM32F10x_FWLib/src/stm32f10x_exti.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_exti.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the EXTI firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_exti.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup EXTI
30 | * @brief EXTI driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup EXTI_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup EXTI_Private_Defines
43 | * @{
44 | */
45 |
46 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
47 |
48 | /**
49 | * @}
50 | */
51 |
52 | /** @defgroup EXTI_Private_Macros
53 | * @{
54 | */
55 |
56 | /**
57 | * @}
58 | */
59 |
60 | /** @defgroup EXTI_Private_Variables
61 | * @{
62 | */
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup EXTI_Private_FunctionPrototypes
69 | * @{
70 | */
71 |
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup EXTI_Private_Functions
77 | * @{
78 | */
79 |
80 | /**
81 | * @brief Deinitializes the EXTI peripheral registers to their default reset values.
82 | * @param None
83 | * @retval None
84 | */
85 | void EXTI_DeInit(void)
86 | {
87 | EXTI->IMR = 0x00000000;
88 | EXTI->EMR = 0x00000000;
89 | EXTI->RTSR = 0x00000000;
90 | EXTI->FTSR = 0x00000000;
91 | EXTI->PR = 0x000FFFFF;
92 | }
93 |
94 | /**
95 | * @brief Initializes the EXTI peripheral according to the specified
96 | * parameters in the EXTI_InitStruct.
97 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
98 | * that contains the configuration information for the EXTI peripheral.
99 | * @retval None
100 | */
101 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
102 | {
103 | uint32_t tmp = 0;
104 |
105 | /* Check the parameters */
106 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
107 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
108 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
109 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
110 |
111 | tmp = (uint32_t)EXTI_BASE;
112 |
113 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
114 | {
115 | /* Clear EXTI line configuration */
116 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
117 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
118 |
119 | tmp += EXTI_InitStruct->EXTI_Mode;
120 |
121 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
122 |
123 | /* Clear Rising Falling edge configuration */
124 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
125 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
126 |
127 | /* Select the trigger for the selected external interrupts */
128 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
129 | {
130 | /* Rising Falling edge */
131 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
132 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
133 | }
134 | else
135 | {
136 | tmp = (uint32_t)EXTI_BASE;
137 | tmp += EXTI_InitStruct->EXTI_Trigger;
138 |
139 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
140 | }
141 | }
142 | else
143 | {
144 | tmp += EXTI_InitStruct->EXTI_Mode;
145 |
146 | /* Disable the selected external lines */
147 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
148 | }
149 | }
150 |
151 | /**
152 | * @brief Fills each EXTI_InitStruct member with its reset value.
153 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
154 | * be initialized.
155 | * @retval None
156 | */
157 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
158 | {
159 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
160 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
161 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
162 | EXTI_InitStruct->EXTI_LineCmd = DISABLE;
163 | }
164 |
165 | /**
166 | * @brief Generates a Software interrupt.
167 | * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
168 | * This parameter can be any combination of EXTI_Linex where x can be (0..19).
169 | * @retval None
170 | */
171 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
172 | {
173 | /* Check the parameters */
174 | assert_param(IS_EXTI_LINE(EXTI_Line));
175 |
176 | EXTI->SWIER |= EXTI_Line;
177 | }
178 |
179 | /**
180 | * @brief Checks whether the specified EXTI line flag is set or not.
181 | * @param EXTI_Line: specifies the EXTI line flag to check.
182 | * This parameter can be:
183 | * @arg EXTI_Linex: External interrupt line x where x(0..19)
184 | * @retval The new state of EXTI_Line (SET or RESET).
185 | */
186 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
187 | {
188 | FlagStatus bitstatus = RESET;
189 | /* Check the parameters */
190 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
191 |
192 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
193 | {
194 | bitstatus = SET;
195 | }
196 | else
197 | {
198 | bitstatus = RESET;
199 | }
200 | return bitstatus;
201 | }
202 |
203 | /**
204 | * @brief Clears the EXTI's line pending flags.
205 | * @param EXTI_Line: specifies the EXTI lines flags to clear.
206 | * This parameter can be any combination of EXTI_Linex where x can be (0..19).
207 | * @retval None
208 | */
209 | void EXTI_ClearFlag(uint32_t EXTI_Line)
210 | {
211 | /* Check the parameters */
212 | assert_param(IS_EXTI_LINE(EXTI_Line));
213 |
214 | EXTI->PR = EXTI_Line;
215 | }
216 |
217 | /**
218 | * @brief Checks whether the specified EXTI line is asserted or not.
219 | * @param EXTI_Line: specifies the EXTI line to check.
220 | * This parameter can be:
221 | * @arg EXTI_Linex: External interrupt line x where x(0..19)
222 | * @retval The new state of EXTI_Line (SET or RESET).
223 | */
224 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
225 | {
226 | ITStatus bitstatus = RESET;
227 | uint32_t enablestatus = 0;
228 | /* Check the parameters */
229 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
230 |
231 | enablestatus = EXTI->IMR & EXTI_Line;
232 | if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
233 | {
234 | bitstatus = SET;
235 | }
236 | else
237 | {
238 | bitstatus = RESET;
239 | }
240 | return bitstatus;
241 | }
242 |
243 | /**
244 | * @brief Clears the EXTI's line pending bits.
245 | * @param EXTI_Line: specifies the EXTI lines to clear.
246 | * This parameter can be any combination of EXTI_Linex where x can be (0..19).
247 | * @retval None
248 | */
249 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
250 | {
251 | /* Check the parameters */
252 | assert_param(IS_EXTI_LINE(EXTI_Line));
253 |
254 | EXTI->PR = EXTI_Line;
255 | }
256 |
257 | /**
258 | * @}
259 | */
260 |
261 | /**
262 | * @}
263 | */
264 |
265 | /**
266 | * @}
267 | */
268 |
269 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
270 |
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/STM32F10x_FWLib/src/stm32f10x_flash.c:
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/STM32F10x_FWLib/src/stm32f10x_i2c.c:
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/STM32F10x_FWLib/src/stm32f10x_iwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_iwdg.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the IWDG firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_iwdg.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup IWDG
30 | * @brief IWDG driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup IWDG_Private_TypesDefinitions
35 | * @{
36 | */
37 |
38 | /**
39 | * @}
40 | */
41 |
42 | /** @defgroup IWDG_Private_Defines
43 | * @{
44 | */
45 |
46 | /* ---------------------- IWDG registers bit mask ----------------------------*/
47 |
48 | /* KR register bit mask */
49 | #define KR_KEY_Reload ((uint16_t)0xAAAA)
50 | #define KR_KEY_Enable ((uint16_t)0xCCCC)
51 |
52 | /**
53 | * @}
54 | */
55 |
56 | /** @defgroup IWDG_Private_Macros
57 | * @{
58 | */
59 |
60 | /**
61 | * @}
62 | */
63 |
64 | /** @defgroup IWDG_Private_Variables
65 | * @{
66 | */
67 |
68 | /**
69 | * @}
70 | */
71 |
72 | /** @defgroup IWDG_Private_FunctionPrototypes
73 | * @{
74 | */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 | /** @defgroup IWDG_Private_Functions
81 | * @{
82 | */
83 |
84 | /**
85 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
86 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
87 | * This parameter can be one of the following values:
88 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
89 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
90 | * @retval None
91 | */
92 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
93 | {
94 | /* Check the parameters */
95 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
96 | IWDG->KR = IWDG_WriteAccess;
97 | }
98 |
99 | /**
100 | * @brief Sets IWDG Prescaler value.
101 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
102 | * This parameter can be one of the following values:
103 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
104 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
105 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
106 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
107 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
108 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
109 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
110 | * @retval None
111 | */
112 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
113 | {
114 | /* Check the parameters */
115 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
116 | IWDG->PR = IWDG_Prescaler;
117 | }
118 |
119 | /**
120 | * @brief Sets IWDG Reload value.
121 | * @param Reload: specifies the IWDG Reload value.
122 | * This parameter must be a number between 0 and 0x0FFF.
123 | * @retval None
124 | */
125 | void IWDG_SetReload(uint16_t Reload)
126 | {
127 | /* Check the parameters */
128 | assert_param(IS_IWDG_RELOAD(Reload));
129 | IWDG->RLR = Reload;
130 | }
131 |
132 | /**
133 | * @brief Reloads IWDG counter with value defined in the reload register
134 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
135 | * @param None
136 | * @retval None
137 | */
138 | void IWDG_ReloadCounter(void)
139 | {
140 | IWDG->KR = KR_KEY_Reload;
141 | }
142 |
143 | /**
144 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
145 | * @param None
146 | * @retval None
147 | */
148 | void IWDG_Enable(void)
149 | {
150 | IWDG->KR = KR_KEY_Enable;
151 | }
152 |
153 | /**
154 | * @brief Checks whether the specified IWDG flag is set or not.
155 | * @param IWDG_FLAG: specifies the flag to check.
156 | * This parameter can be one of the following values:
157 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
158 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
159 | * @retval The new state of IWDG_FLAG (SET or RESET).
160 | */
161 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
162 | {
163 | FlagStatus bitstatus = RESET;
164 | /* Check the parameters */
165 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
166 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
167 | {
168 | bitstatus = SET;
169 | }
170 | else
171 | {
172 | bitstatus = RESET;
173 | }
174 | /* Return the flag status */
175 | return bitstatus;
176 | }
177 |
178 | /**
179 | * @}
180 | */
181 |
182 | /**
183 | * @}
184 | */
185 |
186 | /**
187 | * @}
188 | */
189 |
190 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
191 |
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/STM32F10x_FWLib/src/stm32f10x_pwr.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_pwr.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the PWR firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_pwr.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup PWR
31 | * @brief PWR driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup PWR_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup PWR_Private_Defines
44 | * @{
45 | */
46 |
47 | /* --------- PWR registers bit address in the alias region ---------- */
48 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
49 |
50 | /* --- CR Register ---*/
51 |
52 | /* Alias word address of DBP bit */
53 | #define CR_OFFSET (PWR_OFFSET + 0x00)
54 | #define DBP_BitNumber 0x08
55 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
56 |
57 | /* Alias word address of PVDE bit */
58 | #define PVDE_BitNumber 0x04
59 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
60 |
61 | /* --- CSR Register ---*/
62 |
63 | /* Alias word address of EWUP bit */
64 | #define CSR_OFFSET (PWR_OFFSET + 0x04)
65 | #define EWUP_BitNumber 0x08
66 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
67 |
68 | /* ------------------ PWR registers bit mask ------------------------ */
69 |
70 | /* CR register bit mask */
71 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
72 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
73 |
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /** @defgroup PWR_Private_Macros
80 | * @{
81 | */
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /** @defgroup PWR_Private_Variables
88 | * @{
89 | */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup PWR_Private_FunctionPrototypes
96 | * @{
97 | */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup PWR_Private_Functions
104 | * @{
105 | */
106 |
107 | /**
108 | * @brief Deinitializes the PWR peripheral registers to their default reset values.
109 | * @param None
110 | * @retval None
111 | */
112 | void PWR_DeInit(void)
113 | {
114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
115 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
116 | }
117 |
118 | /**
119 | * @brief Enables or disables access to the RTC and backup registers.
120 | * @param NewState: new state of the access to the RTC and backup registers.
121 | * This parameter can be: ENABLE or DISABLE.
122 | * @retval None
123 | */
124 | void PWR_BackupAccessCmd(FunctionalState NewState)
125 | {
126 | /* Check the parameters */
127 | assert_param(IS_FUNCTIONAL_STATE(NewState));
128 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
129 | }
130 |
131 | /**
132 | * @brief Enables or disables the Power Voltage Detector(PVD).
133 | * @param NewState: new state of the PVD.
134 | * This parameter can be: ENABLE or DISABLE.
135 | * @retval None
136 | */
137 | void PWR_PVDCmd(FunctionalState NewState)
138 | {
139 | /* Check the parameters */
140 | assert_param(IS_FUNCTIONAL_STATE(NewState));
141 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
142 | }
143 |
144 | /**
145 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
146 | * @param PWR_PVDLevel: specifies the PVD detection level
147 | * This parameter can be one of the following values:
148 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
149 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
150 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
151 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
152 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
153 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
154 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
155 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
156 | * @retval None
157 | */
158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
159 | {
160 | uint32_t tmpreg = 0;
161 | /* Check the parameters */
162 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
163 | tmpreg = PWR->CR;
164 | /* Clear PLS[7:5] bits */
165 | tmpreg &= CR_PLS_MASK;
166 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */
167 | tmpreg |= PWR_PVDLevel;
168 | /* Store the new value */
169 | PWR->CR = tmpreg;
170 | }
171 |
172 | /**
173 | * @brief Enables or disables the WakeUp Pin functionality.
174 | * @param NewState: new state of the WakeUp Pin functionality.
175 | * This parameter can be: ENABLE or DISABLE.
176 | * @retval None
177 | */
178 | void PWR_WakeUpPinCmd(FunctionalState NewState)
179 | {
180 | /* Check the parameters */
181 | assert_param(IS_FUNCTIONAL_STATE(NewState));
182 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
183 | }
184 |
185 | /**
186 | * @brief Enters STOP mode.
187 | * @param PWR_Regulator: specifies the regulator state in STOP mode.
188 | * This parameter can be one of the following values:
189 | * @arg PWR_Regulator_ON: STOP mode with regulator ON
190 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
191 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
192 | * This parameter can be one of the following values:
193 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
194 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
195 | * @retval None
196 | */
197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
198 | {
199 | uint32_t tmpreg = 0;
200 | /* Check the parameters */
201 | assert_param(IS_PWR_REGULATOR(PWR_Regulator));
202 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
203 |
204 | /* Select the regulator state in STOP mode ---------------------------------*/
205 | tmpreg = PWR->CR;
206 | /* Clear PDDS and LPDS bits */
207 | tmpreg &= CR_DS_MASK;
208 | /* Set LPDS bit according to PWR_Regulator value */
209 | tmpreg |= PWR_Regulator;
210 | /* Store the new value */
211 | PWR->CR = tmpreg;
212 | /* Set SLEEPDEEP bit of Cortex System Control Register */
213 | SCB->SCR |= SCB_SCR_SLEEPDEEP;
214 |
215 | /* Select STOP mode entry --------------------------------------------------*/
216 | if(PWR_STOPEntry == PWR_STOPEntry_WFI)
217 | {
218 | /* Request Wait For Interrupt */
219 | __WFI();
220 | }
221 | else
222 | {
223 | /* Request Wait For Event */
224 | __WFE();
225 | }
226 |
227 | /* Reset SLEEPDEEP bit of Cortex System Control Register */
228 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
229 | }
230 |
231 | /**
232 | * @brief Enters STANDBY mode.
233 | * @param None
234 | * @retval None
235 | */
236 | void PWR_EnterSTANDBYMode(void)
237 | {
238 | /* Clear Wake-up flag */
239 | PWR->CR |= PWR_CR_CWUF;
240 | /* Select STANDBY mode */
241 | PWR->CR |= PWR_CR_PDDS;
242 | /* Set SLEEPDEEP bit of Cortex System Control Register */
243 | SCB->SCR |= SCB_SCR_SLEEPDEEP;
244 | /* This option is used to ensure that store operations are completed */
245 | #if defined ( __CC_ARM )
246 | __force_stores();
247 | #endif
248 | /* Request Wait For Interrupt */
249 | __WFI();
250 | }
251 |
252 | /**
253 | * @brief Checks whether the specified PWR flag is set or not.
254 | * @param PWR_FLAG: specifies the flag to check.
255 | * This parameter can be one of the following values:
256 | * @arg PWR_FLAG_WU: Wake Up flag
257 | * @arg PWR_FLAG_SB: StandBy flag
258 | * @arg PWR_FLAG_PVDO: PVD Output
259 | * @retval The new state of PWR_FLAG (SET or RESET).
260 | */
261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
262 | {
263 | FlagStatus bitstatus = RESET;
264 | /* Check the parameters */
265 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
266 |
267 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
268 | {
269 | bitstatus = SET;
270 | }
271 | else
272 | {
273 | bitstatus = RESET;
274 | }
275 | /* Return the flag status */
276 | return bitstatus;
277 | }
278 |
279 | /**
280 | * @brief Clears the PWR's pending flags.
281 | * @param PWR_FLAG: specifies the flag to clear.
282 | * This parameter can be one of the following values:
283 | * @arg PWR_FLAG_WU: Wake Up flag
284 | * @arg PWR_FLAG_SB: StandBy flag
285 | * @retval None
286 | */
287 | void PWR_ClearFlag(uint32_t PWR_FLAG)
288 | {
289 | /* Check the parameters */
290 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
291 |
292 | PWR->CR |= PWR_FLAG << 2;
293 | }
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | /**
304 | * @}
305 | */
306 |
307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
308 |
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/STM32F10x_FWLib/src/stm32f10x_rtc.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_rtc.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the RTC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_rtc.h"
24 |
25 | /** @addtogroup STM32F10x_StdPeriph_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup RTC
30 | * @brief RTC driver modules
31 | * @{
32 | */
33 |
34 | /** @defgroup RTC_Private_TypesDefinitions
35 | * @{
36 | */
37 | /**
38 | * @}
39 | */
40 |
41 | /** @defgroup RTC_Private_Defines
42 | * @{
43 | */
44 | #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
45 | #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
46 |
47 | /**
48 | * @}
49 | */
50 |
51 | /** @defgroup RTC_Private_Macros
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @defgroup RTC_Private_Variables
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup RTC_Private_FunctionPrototypes
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @defgroup RTC_Private_Functions
76 | * @{
77 | */
78 |
79 | /**
80 | * @brief Enables or disables the specified RTC interrupts.
81 | * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
82 | * This parameter can be any combination of the following values:
83 | * @arg RTC_IT_OW: Overflow interrupt
84 | * @arg RTC_IT_ALR: Alarm interrupt
85 | * @arg RTC_IT_SEC: Second interrupt
86 | * @param NewState: new state of the specified RTC interrupts.
87 | * This parameter can be: ENABLE or DISABLE.
88 | * @retval None
89 | */
90 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
91 | {
92 | /* Check the parameters */
93 | assert_param(IS_RTC_IT(RTC_IT));
94 | assert_param(IS_FUNCTIONAL_STATE(NewState));
95 |
96 | if (NewState != DISABLE)
97 | {
98 | RTC->CRH |= RTC_IT;
99 | }
100 | else
101 | {
102 | RTC->CRH &= (uint16_t)~RTC_IT;
103 | }
104 | }
105 |
106 | /**
107 | * @brief Enters the RTC configuration mode.
108 | * @param None
109 | * @retval None
110 | */
111 | void RTC_EnterConfigMode(void)
112 | {
113 | /* Set the CNF flag to enter in the Configuration Mode */
114 | RTC->CRL |= RTC_CRL_CNF;
115 | }
116 |
117 | /**
118 | * @brief Exits from the RTC configuration mode.
119 | * @param None
120 | * @retval None
121 | */
122 | void RTC_ExitConfigMode(void)
123 | {
124 | /* Reset the CNF flag to exit from the Configuration Mode */
125 | RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
126 | }
127 |
128 | /**
129 | * @brief Gets the RTC counter value.
130 | * @param None
131 | * @retval RTC counter value.
132 | */
133 | uint32_t RTC_GetCounter(void)
134 | {
135 | uint16_t tmp = 0;
136 | tmp = RTC->CNTL;
137 | return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
138 | }
139 |
140 | /**
141 | * @brief Sets the RTC counter value.
142 | * @param CounterValue: RTC counter new value.
143 | * @retval None
144 | */
145 | void RTC_SetCounter(uint32_t CounterValue)
146 | {
147 | RTC_EnterConfigMode();
148 | /* Set RTC COUNTER MSB word */
149 | RTC->CNTH = CounterValue >> 16;
150 | /* Set RTC COUNTER LSB word */
151 | RTC->CNTL = (CounterValue & RTC_LSB_MASK);
152 | RTC_ExitConfigMode();
153 | }
154 |
155 | /**
156 | * @brief Sets the RTC prescaler value.
157 | * @param PrescalerValue: RTC prescaler new value.
158 | * @retval None
159 | */
160 | void RTC_SetPrescaler(uint32_t PrescalerValue)
161 | {
162 | /* Check the parameters */
163 | assert_param(IS_RTC_PRESCALER(PrescalerValue));
164 |
165 | RTC_EnterConfigMode();
166 | /* Set RTC PRESCALER MSB word */
167 | RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
168 | /* Set RTC PRESCALER LSB word */
169 | RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
170 | RTC_ExitConfigMode();
171 | }
172 |
173 | /**
174 | * @brief Sets the RTC alarm value.
175 | * @param AlarmValue: RTC alarm new value.
176 | * @retval None
177 | */
178 | void RTC_SetAlarm(uint32_t AlarmValue)
179 | {
180 | RTC_EnterConfigMode();
181 | /* Set the ALARM MSB word */
182 | RTC->ALRH = AlarmValue >> 16;
183 | /* Set the ALARM LSB word */
184 | RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
185 | RTC_ExitConfigMode();
186 | }
187 |
188 | /**
189 | * @brief Gets the RTC divider value.
190 | * @param None
191 | * @retval RTC Divider value.
192 | */
193 | uint32_t RTC_GetDivider(void)
194 | {
195 | uint32_t tmp = 0x00;
196 | tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
197 | tmp |= RTC->DIVL;
198 | return tmp;
199 | }
200 |
201 | /**
202 | * @brief Waits until last write operation on RTC registers has finished.
203 | * @note This function must be called before any write to RTC registers.
204 | * @param None
205 | * @retval None
206 | */
207 | void RTC_WaitForLastTask(void)
208 | {
209 | /* Loop until RTOFF flag is set */
210 | while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
211 | {
212 | }
213 | }
214 |
215 | /**
216 | * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
217 | * are synchronized with RTC APB clock.
218 | * @note This function must be called before any read operation after an APB reset
219 | * or an APB clock stop.
220 | * @param None
221 | * @retval None
222 | */
223 | void RTC_WaitForSynchro(void)
224 | {
225 | /* Clear RSF flag */
226 | RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
227 | /* Loop until RSF flag is set */
228 | while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
229 | {
230 | }
231 | }
232 |
233 | /**
234 | * @brief Checks whether the specified RTC flag is set or not.
235 | * @param RTC_FLAG: specifies the flag to check.
236 | * This parameter can be one the following values:
237 | * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
238 | * @arg RTC_FLAG_RSF: Registers Synchronized flag
239 | * @arg RTC_FLAG_OW: Overflow flag
240 | * @arg RTC_FLAG_ALR: Alarm flag
241 | * @arg RTC_FLAG_SEC: Second flag
242 | * @retval The new state of RTC_FLAG (SET or RESET).
243 | */
244 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
245 | {
246 | FlagStatus bitstatus = RESET;
247 |
248 | /* Check the parameters */
249 | assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
250 |
251 | if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
252 | {
253 | bitstatus = SET;
254 | }
255 | else
256 | {
257 | bitstatus = RESET;
258 | }
259 | return bitstatus;
260 | }
261 |
262 | /**
263 | * @brief Clears the RTC's pending flags.
264 | * @param RTC_FLAG: specifies the flag to clear.
265 | * This parameter can be any combination of the following values:
266 | * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
267 | * an APB reset or an APB Clock stop.
268 | * @arg RTC_FLAG_OW: Overflow flag
269 | * @arg RTC_FLAG_ALR: Alarm flag
270 | * @arg RTC_FLAG_SEC: Second flag
271 | * @retval None
272 | */
273 | void RTC_ClearFlag(uint16_t RTC_FLAG)
274 | {
275 | /* Check the parameters */
276 | assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
277 |
278 | /* Clear the corresponding RTC flag */
279 | RTC->CRL &= (uint16_t)~RTC_FLAG;
280 | }
281 |
282 | /**
283 | * @brief Checks whether the specified RTC interrupt has occurred or not.
284 | * @param RTC_IT: specifies the RTC interrupts sources to check.
285 | * This parameter can be one of the following values:
286 | * @arg RTC_IT_OW: Overflow interrupt
287 | * @arg RTC_IT_ALR: Alarm interrupt
288 | * @arg RTC_IT_SEC: Second interrupt
289 | * @retval The new state of the RTC_IT (SET or RESET).
290 | */
291 | ITStatus RTC_GetITStatus(uint16_t RTC_IT)
292 | {
293 | ITStatus bitstatus = RESET;
294 | /* Check the parameters */
295 | assert_param(IS_RTC_GET_IT(RTC_IT));
296 |
297 | bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
298 | if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
299 | {
300 | bitstatus = SET;
301 | }
302 | else
303 | {
304 | bitstatus = RESET;
305 | }
306 | return bitstatus;
307 | }
308 |
309 | /**
310 | * @brief Clears the RTC's interrupt pending bits.
311 | * @param RTC_IT: specifies the interrupt pending bit to clear.
312 | * This parameter can be any combination of the following values:
313 | * @arg RTC_IT_OW: Overflow interrupt
314 | * @arg RTC_IT_ALR: Alarm interrupt
315 | * @arg RTC_IT_SEC: Second interrupt
316 | * @retval None
317 | */
318 | void RTC_ClearITPendingBit(uint16_t RTC_IT)
319 | {
320 | /* Check the parameters */
321 | assert_param(IS_RTC_IT(RTC_IT));
322 |
323 | /* Clear the corresponding RTC pending bit */
324 | RTC->CRL &= (uint16_t)~RTC_IT;
325 | }
326 |
327 | /**
328 | * @}
329 | */
330 |
331 | /**
332 | * @}
333 | */
334 |
335 | /**
336 | * @}
337 | */
338 |
339 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
340 |
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/STM32F10x_FWLib/src/stm32f10x_usart.c:
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https://raw.githubusercontent.com/hotsauce1861/gcc-stm32-osal/d307fb21c0bbe871bff93a1daffe723fbe781677/STM32F10x_FWLib/src/stm32f10x_usart.c
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/STM32F10x_FWLib/src/stm32f10x_wwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f10x_wwdg.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief This file provides all the WWDG firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32f10x_wwdg.h"
24 | #include "stm32f10x_rcc.h"
25 |
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
27 | * @{
28 | */
29 |
30 | /** @defgroup WWDG
31 | * @brief WWDG driver modules
32 | * @{
33 | */
34 |
35 | /** @defgroup WWDG_Private_TypesDefinitions
36 | * @{
37 | */
38 |
39 | /**
40 | * @}
41 | */
42 |
43 | /** @defgroup WWDG_Private_Defines
44 | * @{
45 | */
46 |
47 | /* ----------- WWDG registers bit address in the alias region ----------- */
48 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
49 |
50 | /* Alias word address of EWI bit */
51 | #define CFR_OFFSET (WWDG_OFFSET + 0x04)
52 | #define EWI_BitNumber 0x09
53 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
54 |
55 | /* --------------------- WWDG registers bit mask ------------------------ */
56 |
57 | /* CR register bit mask */
58 | #define CR_WDGA_Set ((uint32_t)0x00000080)
59 |
60 | /* CFR register bit mask */
61 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
62 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80)
63 | #define BIT_Mask ((uint8_t)0x7F)
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /** @defgroup WWDG_Private_Macros
70 | * @{
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /** @defgroup WWDG_Private_Variables
78 | * @{
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /** @defgroup WWDG_Private_FunctionPrototypes
86 | * @{
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /** @defgroup WWDG_Private_Functions
94 | * @{
95 | */
96 |
97 | /**
98 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
99 | * @param None
100 | * @retval None
101 | */
102 | void WWDG_DeInit(void)
103 | {
104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
106 | }
107 |
108 | /**
109 | * @brief Sets the WWDG Prescaler.
110 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
111 | * This parameter can be one of the following values:
112 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
113 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
114 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
115 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
116 | * @retval None
117 | */
118 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
119 | {
120 | uint32_t tmpreg = 0;
121 | /* Check the parameters */
122 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
123 | /* Clear WDGTB[1:0] bits */
124 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
125 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
126 | tmpreg |= WWDG_Prescaler;
127 | /* Store the new value */
128 | WWDG->CFR = tmpreg;
129 | }
130 |
131 | /**
132 | * @brief Sets the WWDG window value.
133 | * @param WindowValue: specifies the window value to be compared to the downcounter.
134 | * This parameter value must be lower than 0x80.
135 | * @retval None
136 | */
137 | void WWDG_SetWindowValue(uint8_t WindowValue)
138 | {
139 | __IO uint32_t tmpreg = 0;
140 |
141 | /* Check the parameters */
142 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
143 | /* Clear W[6:0] bits */
144 |
145 | tmpreg = WWDG->CFR & CFR_W_Mask;
146 |
147 | /* Set W[6:0] bits according to WindowValue value */
148 | tmpreg |= WindowValue & (uint32_t) BIT_Mask;
149 |
150 | /* Store the new value */
151 | WWDG->CFR = tmpreg;
152 | }
153 |
154 | /**
155 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
156 | * @param None
157 | * @retval None
158 | */
159 | void WWDG_EnableIT(void)
160 | {
161 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
162 | }
163 |
164 | /**
165 | * @brief Sets the WWDG counter value.
166 | * @param Counter: specifies the watchdog counter value.
167 | * This parameter must be a number between 0x40 and 0x7F.
168 | * @retval None
169 | */
170 | void WWDG_SetCounter(uint8_t Counter)
171 | {
172 | /* Check the parameters */
173 | assert_param(IS_WWDG_COUNTER(Counter));
174 | /* Write to T[6:0] bits to configure the counter value, no need to do
175 | a read-modify-write; writing a 0 to WDGA bit does nothing */
176 | WWDG->CR = Counter & BIT_Mask;
177 | }
178 |
179 | /**
180 | * @brief Enables WWDG and load the counter value.
181 | * @param Counter: specifies the watchdog counter value.
182 | * This parameter must be a number between 0x40 and 0x7F.
183 | * @retval None
184 | */
185 | void WWDG_Enable(uint8_t Counter)
186 | {
187 | /* Check the parameters */
188 | assert_param(IS_WWDG_COUNTER(Counter));
189 | WWDG->CR = CR_WDGA_Set | Counter;
190 | }
191 |
192 | /**
193 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
194 | * @param None
195 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
196 | */
197 | FlagStatus WWDG_GetFlagStatus(void)
198 | {
199 | return (FlagStatus)(WWDG->SR);
200 | }
201 |
202 | /**
203 | * @brief Clears Early Wakeup interrupt flag.
204 | * @param None
205 | * @retval None
206 | */
207 | void WWDG_ClearFlag(void)
208 | {
209 | WWDG->SR = (uint32_t)RESET;
210 | }
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /**
217 | * @}
218 | */
219 |
220 | /**
221 | * @}
222 | */
223 |
224 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
225 |
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