├── #vga-small.vhd# ├── .#vga-small.vhd ├── .gitattributes ├── .gitignore ├── 4k-blank.bin ├── 4k-blank.hex ├── A-C8V4Pins ├── CHARSET.BIN ├── DIE-LEG2.BIN ├── DIE-LEG2.hex ├── Makefile ├── README.md ├── VGA-ROM-8x16.hex ├── VGA-ROM.bin ├── bin2hex.exe ├── bootrom.cmp ├── bootrom.qip ├── bootrom.vhd ├── charset.hex ├── colour-rom.vhd ├── components ├── T16450.vhd ├── T80.vhd ├── T80_ALU.vhd ├── T80_MCode.vhd ├── T80_Pack.vhd ├── T80_Reg.vhd ├── T80_RegX.vhd ├── T80a.vhd ├── T80s.vhd └── T80se.vhd ├── constants.vhd ├── debounce.vhd ├── displayram.cmp ├── displayram.qip ├── displayram.vhd ├── font_rom.cmp ├── font_rom.qip ├── font_rom.vhd ├── hex2rom.exe ├── ps2_keyboard.vhd ├── rom1.asm ├── rom1.bin ├── rom1.hex ├── simulation └── modelsim │ ├── testbench.vhd │ ├── vga_gfx_testbench.vhd │ └── vga_testbench.vhd ├── sram.cmp ├── sram.qip ├── sram.vhd ├── trunc.exe ├── update-z80.bat ├── vga-controller.vhd ├── vga-rom.hex ├── vga-small.vhd ├── vga_textmode.vhd ├── vt100.qpf ├── vt100.qsf ├── vt100.sdc └── vt100.vhd /#vga-small.vhd#: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 4 | use IEEE.NUMERIC_STD.all; 5 | 6 | entity mod_m_counter is 7 | generic( 8 | N : integer := 7; -- number of bits 9 | M : integer := 80 -- mod-M 10 | ); 11 | port ( 12 | q : out std_logic_vector((N-1) downto 0); 13 | wrap : out std_logic; 14 | clear : in std_logic; 15 | clock : in std_logic); 16 | end mod_m_counter; 17 | 18 | architecture Behav of mod_m_counter is 19 | signal tmp : std_logic_vector((N-1) downto 0) := (others => '0'); 20 | begin 21 | process(clock, clear) 22 | begin 23 | if (rising_edge(clock)) then 24 | if (clear = '1') then 25 | tmp <= (others => '0'); 26 | else 27 | if unsigned(tmp) = M then -- binary 80 28 | tmp <= (others => '0'); -- equivalent to "0000000" 29 | wrap <= '1'; 30 | else 31 | tmp <= std_logic_vector(unsigned(tmp) + 1); 32 | wrap <= '0'; 33 | end if; 34 | end if; 35 | end if; 36 | 37 | end process; 38 | 39 | q <= tmp; 40 | 41 | end Behav; 42 | 43 | --------------------------------------------------------------------------------------- 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 48 | use IEEE.NUMERIC_STD.all; 49 | 50 | entity shiftreg is 51 | generic( 52 | N : integer := 9 -- number of bits 53 | ); 54 | port ( 55 | q : out std_logic; 56 | load : in std_logic; 57 | input : in std_logic_vector((N-1) downto 0); 58 | clock : in std_logic); 59 | end shiftreg; 60 | 61 | architecture Behavioral of shiftreg is 62 | signal latch : std_logic_vector((N-1) downto 0); 63 | signal tmp_out : std_logic; 64 | begin 65 | 66 | process (clock, input, load) 67 | begin 68 | if (rising_edge(clock)) then 69 | if(load = '1') then 70 | latch <= input; 71 | else 72 | latch((N-1) downto 0) <= latch((N-2) downto 0) & '0'; 73 | end if; 74 | end if; 75 | 76 | end process; 77 | 78 | q <= latch(N-1); 79 | 80 | end Behavioral; 81 | 82 | --------------------------------------------------------------------------------------- 83 | 84 | library ieee; 85 | use ieee.std_logic_1164.all; 86 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 87 | use IEEE.NUMERIC_STD.all; 88 | 89 | entity attr_selector is 90 | port ( 91 | input : in std_logic; 92 | outR : out std_logic_vector(1 downto 0); 93 | outG : out std_logic_vector(1 downto 0); 94 | outB : out std_logic_vector(1 downto 0); 95 | disp_enable : in std_logic; 96 | load : in std_logic; 97 | fg : in std_logic_vector(5 downto 0); 98 | bg : in std_logic_vector(5 downto 0); 99 | flashing : in std_logic; 100 | flashclk : in std_logic; 101 | clock : in std_logic; 102 | blanking : in std_logic 103 | ); 104 | end attr_selector; 105 | 106 | 107 | architecture Behavioral of attr_selector is 108 | signal fg_latch : std_logic_vector(5 downto 0); 109 | signal bg_latch : std_logic_vector(5 downto 0); 110 | signal result : std_logic_vector(5 downto 0); 111 | signal flash_latch : std_logic; 112 | begin 113 | 114 | process (clock, input, load) 115 | begin 116 | if (rising_edge(clock)) then 117 | if(load = '1') then 118 | fg_latch <= fg; 119 | bg_latch <= bg; 120 | flash_latch <= flashing; 121 | end if; 122 | 123 | if (disp_enable = '0') then 124 | result <= "000000"; 125 | else 126 | if (input = '0' or (flashclk and flash_latch) = '1') then 127 | result <= bg_latch; 128 | else 129 | result <= fg_latch; 130 | end if; 131 | end if; 132 | 133 | end if; 134 | 135 | end process; 136 | 137 | outR <= result(5 downto 4); 138 | outG <= result(3 downto 2); 139 | outB <= result(1 downto 0); 140 | 141 | end Behavioral; 142 | -------------------------------------------------------------------------------- /.#vga-small.vhd: -------------------------------------------------------------------------------- 1 | Howard Jones@HOWARDJONES-PC.3040:1444140520 -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Altera Quartus 2 | *~ 3 | *.pof 4 | *.sof 5 | *.bak 6 | *.rpt 7 | incremental_db/ 8 | db/ 9 | output_files/ 10 | roms/ 11 | greybox_tmp/ 12 | .qsys_edit/ 13 | simulation/ 14 | *.chg 15 | 16 | 17 | ################# 18 | ## Eclipse 19 | ################# 20 | 21 | *.pydevproject 22 | .project 23 | .metadata 24 | bin/ 25 | tmp/ 26 | *.tmp 27 | *.bak 28 | *.swp 29 | *~.nib 30 | local.properties 31 | .classpath 32 | .settings/ 33 | .loadpath 34 | 35 | # External tool builders 36 | .externalToolBuilders/ 37 | 38 | # Locally stored "Eclipse launch configurations" 39 | *.launch 40 | 41 | # CDT-specific 42 | .cproject 43 | 44 | # PDT-specific 45 | .buildpath 46 | 47 | 48 | ################# 49 | ## Visual Studio 50 | ################# 51 | 52 | ## Ignore Visual Studio temporary files, build results, and 53 | ## files generated by popular Visual Studio add-ons. 54 | 55 | # User-specific files 56 | *.suo 57 | *.user 58 | *.sln.docstates 59 | 60 | # Build results 61 | 62 | [Dd]ebug/ 63 | [Rr]elease/ 64 | x64/ 65 | build/ 66 | [Bb]in/ 67 | [Oo]bj/ 68 | 69 | # MSTest test Results 70 | [Tt]est[Rr]esult*/ 71 | [Bb]uild[Ll]og.* 72 | 73 | *_i.c 74 | *_p.c 75 | *.ilk 76 | *.meta 77 | *.obj 78 | *.pch 79 | *.pdb 80 | *.pgc 81 | *.pgd 82 | *.rsp 83 | *.sbr 84 | *.tlb 85 | *.tli 86 | *.tlh 87 | *.tmp 88 | *.tmp_proj 89 | *.log 90 | *.vspscc 91 | *.vssscc 92 | .builds 93 | *.pidb 94 | *.log 95 | *.scc 96 | 97 | # Visual C++ cache files 98 | ipch/ 99 | *.aps 100 | *.ncb 101 | *.opensdf 102 | *.sdf 103 | *.cachefile 104 | 105 | # Visual Studio profiler 106 | *.psess 107 | *.vsp 108 | *.vspx 109 | 110 | # Guidance Automation Toolkit 111 | *.gpState 112 | 113 | # ReSharper is a .NET coding add-in 114 | _ReSharper*/ 115 | *.[Rr]e[Ss]harper 116 | 117 | # TeamCity is a build add-in 118 | _TeamCity* 119 | 120 | # DotCover is a Code Coverage Tool 121 | *.dotCover 122 | 123 | # NCrunch 124 | *.ncrunch* 125 | .*crunch*.local.xml 126 | 127 | # Installshield output folder 128 | [Ee]xpress/ 129 | 130 | # DocProject is a documentation generator add-in 131 | DocProject/buildhelp/ 132 | DocProject/Help/*.HxT 133 | DocProject/Help/*.HxC 134 | DocProject/Help/*.hhc 135 | DocProject/Help/*.hhk 136 | DocProject/Help/*.hhp 137 | DocProject/Help/Html2 138 | DocProject/Help/html 139 | 140 | # Click-Once directory 141 | publish/ 142 | 143 | # Publish Web Output 144 | *.Publish.xml 145 | *.pubxml 146 | *.publishproj 147 | 148 | # NuGet Packages Directory 149 | ## TODO: If you have NuGet Package Restore enabled, uncomment the next line 150 | #packages/ 151 | 152 | # Windows Azure Build Output 153 | csx 154 | *.build.csdef 155 | 156 | # Windows Store app package directory 157 | AppPackages/ 158 | 159 | # Others 160 | sql/ 161 | *.Cache 162 | ClientBin/ 163 | [Ss]tyle[Cc]op.* 164 | ~$* 165 | *~ 166 | *.dbmdl 167 | *.[Pp]ublish.xml 168 | *.pfx 169 | *.publishsettings 170 | 171 | # RIA/Silverlight projects 172 | Generated_Code/ 173 | 174 | # Backup & report files from converting an old project file to a newer 175 | # Visual Studio version. Backup files are not needed, because we have git ;-) 176 | _UpgradeReport_Files/ 177 | Backup*/ 178 | UpgradeLog*.XML 179 | UpgradeLog*.htm 180 | 181 | # SQL Server files 182 | App_Data/*.mdf 183 | App_Data/*.ldf 184 | 185 | ############# 186 | ## Windows detritus 187 | ############# 188 | 189 | # Windows image file caches 190 | Thumbs.db 191 | ehthumbs.db 192 | 193 | # Folder config file 194 | Desktop.ini 195 | 196 | # Recycle Bin used on file shares 197 | $RECYCLE.BIN/ 198 | 199 | # Mac crap 200 | .DS_Store 201 | 202 | 203 | ############# 204 | ## Python 205 | ############# 206 | 207 | *.py[cod] 208 | 209 | # Packages 210 | *.egg 211 | *.egg-info 212 | dist/ 213 | build/ 214 | eggs/ 215 | parts/ 216 | var/ 217 | sdist/ 218 | develop-eggs/ 219 | .installed.cfg 220 | 221 | # Installer logs 222 | pip-log.txt 223 | 224 | # Unit test / coverage reports 225 | .coverage 226 | .tox 227 | 228 | #Translations 229 | *.mo 230 | 231 | #Mr Developer 232 | .mr.developer.cfg 233 | -------------------------------------------------------------------------------- /4k-blank.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/4k-blank.bin -------------------------------------------------------------------------------- /4k-blank.hex: -------------------------------------------------------------------------------- 1 | :2000000031FE833E01D3FF2100807756BA20043EAAD3FF3E16F52100F0115D001A47131AC1 2 | :200020007713233ECF772310F61160043E002100F01906107723237723233C10F7763E41C1 3 | :200040002100F00619C5064F77232310FBC13C10F4F51620DBFFAAD3FFF1C340003254682A 4 | :20006000697320697320746865204650474120767431303020656D756C61746F722E204E49 5 | :200080006F7468696E6720776F726B7320796574000000000000000000000000000000000F 6 | :2000A000000000000000000000000000000000000000000000000000000000000000000040 7 | :2000C000000000000000000000000000000000000000000000000000000000000000000020 8 | :2000E000000000000000000000000000000000000000000000000000000000000000000000 9 | :200100000000000000000000000000000000000000000000000000000000000000000000DF 10 | :200120000000000000000000000000000000000000000000000000000000000000000000BF 11 | :2001400000000000000000000000000000000000000000000000000000000000000000009F 12 | :2001600000000000000000000000000000000000000000000000000000000000000000007F 13 | :2001800000000000000000000000000000000000000000000000000000000000000000005F 14 | :2001A00000000000000000000000000000000000000000000000000000000000000000003F 15 | :2001C00000000000000000000000000000000000000000000000000000000000000000001F 16 | :2001E0000000000000000000000000000000000000000000000000000000000000000000FF 17 | :200200000000000000000000000000000000000000000000000000000000000000000000DE 18 | :200220000000000000000000000000000000000000000000000000000000000000000000BE 19 | :2002400000000000000000000000000000000000000000000000000000000000000000009E 20 | :2002600000000000000000000000000000000000000000000000000000000000000000007E 21 | :2002800000000000000000000000000000000000000000000000000000000000000000005E 22 | :2002A00000000000000000000000000000000000000000000000000000000000000000003E 23 | :2002C00000000000000000000000000000000000000000000000000000000000000000001E 24 | :2002E0000000000000000000000000000000000000000000000000000000000000000000FE 25 | :200300000000000000000000000000000000000000000000000000000000000000000000DD 26 | :200320000000000000000000000000000000000000000000000000000000000000000000BD 27 | :2003400000000000000000000000000000000000000000000000000000000000000000009D 28 | :2003600000000000000000000000000000000000000000000000000000000000000000007D 29 | :2003800000000000000000000000000000000000000000000000000000000000000000005D 30 | :2003A00000000000000000000000000000000000000000000000000000000000000000003D 31 | :2003C00000000000000000000000000000000000000000000000000000000000000000001D 32 | :2003E0000000000000000000000000000000000000000000000000000000000000000000FD 33 | :200400000000000000000000000000000000000000000000000000000000000000000000DC 34 | :200420000000000000000000000000000000000000000000000000000000000000000000BC 35 | :2004400000000000000000000000000000000000000000000000000000000000000000009C 36 | :2004600000000000000000000000000000000000000000000000000000000000000000007C 37 | :2004800000000000000000000000000000000000000000000000000000000000000000005C 38 | :2004A00000000000000000000000000000000000000000000000000000000000000000003C 39 | :2004C00000000000000000000000000000000000000000000000000000000000000000001C 40 | :2004E0000000000000000000000000000000000000000000000000000000000000000000FC 41 | :200500000000000000000000000000000000000000000000000000000000000000000000DB 42 | :200520000000000000000000000000000000000000000000000000000000000000000000BB 43 | :2005400000000000000000000000000000000000000000000000000000000000000000009B 44 | :2005600000000000000000000000000000000000000000000000000000000000000000007B 45 | :2005800000000000000000000000000000000000000000000000000000000000000000005B 46 | :2005A00000000000000000000000000000000000000000000000000000000000000000003B 47 | :2005C00000000000000000000000000000000000000000000000000000000000000000001B 48 | :2005E0000000000000000000000000000000000000000000000000000000000000000000FB 49 | :200600000000000000000000000000000000000000000000000000000000000000000000DA 50 | :200620000000000000000000000000000000000000000000000000000000000000000000BA 51 | :2006400000000000000000000000000000000000000000000000000000000000000000009A 52 | :2006600000000000000000000000000000000000000000000000000000000000000000007A 53 | :2006800000000000000000000000000000000000000000000000000000000000000000005A 54 | :2006A00000000000000000000000000000000000000000000000000000000000000000003A 55 | :2006C00000000000000000000000000000000000000000000000000000000000000000001A 56 | :2006E0000000000000000000000000000000000000000000000000000000000000000000FA 57 | :200700000000000000000000000000000000000000000000000000000000000000000000D9 58 | :200720000000000000000000000000000000000000000000000000000000000000000000B9 59 | :20074000000000000000000000000000000000000000000000000000000000000000000099 60 | :20076000000000000000000000000000000000000000000000000000000000000000000079 61 | :20078000000000000000000000000000000000000000000000000000000000000000000059 62 | :2007A000000000000000000000000000000000000000000000000000000000000000000039 63 | :2007C000000000000000000000000000000000000000000000000000000000000000000019 64 | :2007E0000000000000000000000000000000000000000000000000000000000000000000F9 65 | :200800000000000000000000000000000000000000000000000000000000000000000000D8 66 | :200820000000000000000000000000000000000000000000000000000000000000000000B8 67 | :20084000000000000000000000000000000000000000000000000000000000000000000098 68 | :20086000000000000000000000000000000000000000000000000000000000000000000078 69 | :20088000000000000000000000000000000000000000000000000000000000000000000058 70 | :2008A000000000000000000000000000000000000000000000000000000000000000000038 71 | :2008C000000000000000000000000000000000000000000000000000000000000000000018 72 | :2008E0000000000000000000000000000000000000000000000000000000000000000000F8 73 | :200900000000000000000000000000000000000000000000000000000000000000000000D7 74 | :200920000000000000000000000000000000000000000000000000000000000000000000B7 75 | :20094000000000000000000000000000000000000000000000000000000000000000000097 76 | :20096000000000000000000000000000000000000000000000000000000000000000000077 77 | :20098000000000000000000000000000000000000000000000000000000000000000000057 78 | :2009A000000000000000000000000000000000000000000000000000000000000000000037 79 | :2009C000000000000000000000000000000000000000000000000000000000000000000017 80 | :2009E0000000000000000000000000000000000000000000000000000000000000000000F7 81 | :200A00000000000000000000000000000000000000000000000000000000000000000000D6 82 | :200A20000000000000000000000000000000000000000000000000000000000000000000B6 83 | :200A4000000000000000000000000000000000000000000000000000000000000000000096 84 | :200A6000000000000000000000000000000000000000000000000000000000000000000076 85 | :200A8000000000000000000000000000000000000000000000000000000000000000000056 86 | :200AA000000000000000000000000000000000000000000000000000000000000000000036 87 | :200AC000000000000000000000000000000000000000000000000000000000000000000016 88 | :200AE0000000000000000000000000000000000000000000000000000000000000000000F6 89 | :200B00000000000000000000000000000000000000000000000000000000000000000000D5 90 | :200B20000000000000000000000000000000000000000000000000000000000000000000B5 91 | :200B4000000000000000000000000000000000000000000000000000000000000000000095 92 | :200B6000000000000000000000000000000000000000000000000000000000000000000075 93 | :200B8000000000000000000000000000000000000000000000000000000000000000000055 94 | :200BA000000000000000000000000000000000000000000000000000000000000000000035 95 | :200BC000000000000000000000000000000000000000000000000000000000000000000015 96 | :200BE0000000000000000000000000000000000000000000000000000000000000000000F5 97 | :200C00000000000000000000000000000000000000000000000000000000000000000000D4 98 | :200C20000000000000000000000000000000000000000000000000000000000000000000B4 99 | :200C4000000000000000000000000000000000000000000000000000000000000000000094 100 | :200C6000000000000000000000000000000000000000000000000000000000000000000074 101 | :200C8000000000000000000000000000000000000000000000000000000000000000000054 102 | :200CA000000000000000000000000000000000000000000000000000000000000000000034 103 | :200CC000000000000000000000000000000000000000000000000000000000000000000014 104 | :200CE0000000000000000000000000000000000000000000000000000000000000000000F4 105 | :200D00000000000000000000000000000000000000000000000000000000000000000000D3 106 | :200D20000000000000000000000000000000000000000000000000000000000000000000B3 107 | :200D4000000000000000000000000000000000000000000000000000000000000000000093 108 | :200D6000000000000000000000000000000000000000000000000000000000000000000073 109 | :200D8000000000000000000000000000000000000000000000000000000000000000000053 110 | :200DA000000000000000000000000000000000000000000000000000000000000000000033 111 | :200DC000000000000000000000000000000000000000000000000000000000000000000013 112 | :200DE0000000000000000000000000000000000000000000000000000000000000000000F3 113 | :200E00000000000000000000000000000000000000000000000000000000000000000000D2 114 | :200E20000000000000000000000000000000000000000000000000000000000000000000B2 115 | :200E4000000000000000000000000000000000000000000000000000000000000000000092 116 | :200E6000000000000000000000000000000000000000000000000000000000000000000072 117 | :200E8000000000000000000000000000000000000000000000000000000000000000000052 118 | :200EA000000000000000000000000000000000000000000000000000000000000000000032 119 | :200EC000000000000000000000000000000000000000000000000000000000000000000012 120 | :200EE0000000000000000000000000000000000000000000000000000000000000000000F2 121 | :200F00000000000000000000000000000000000000000000000000000000000000000000D1 122 | :200F20000000000000000000000000000000000000000000000000000000000000000000B1 123 | :200F4000000000000000000000000000000000000000000000000000000000000000000091 124 | :200F6000000000000000000000000000000000000000000000000000000000000000000071 125 | :200F8000000000000000000000000000000000000000000000000000000000000000000051 126 | :200FA000000000000000000000000000000000000000000000000000000000000000000031 127 | :200FC000000000000000000000000000000000000000000000000000000000000000000011 128 | :200FE0000000000000000000000000000000000000000000000000000000000000000000F1 129 | :00000001FF 130 | -------------------------------------------------------------------------------- /A-C8V4Pins: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/A-C8V4Pins -------------------------------------------------------------------------------- /CHARSET.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/CHARSET.BIN -------------------------------------------------------------------------------- /DIE-LEG2.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/DIE-LEG2.BIN -------------------------------------------------------------------------------- /DIE-LEG2.hex: -------------------------------------------------------------------------------- 1 | :20000000FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE0298 2 | :20002000FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0D60 3 | :20004000FE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0A55 4 | :20006000FE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0C2B 5 | :20008000FE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09200FE4 6 | :2000A0001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D101076 7 | :2000C000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE197F 8 | :2000E00010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE1910093D 9 | :200100001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102005 10 | :20012000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100910202007EE 11 | :200140001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010D5 12 | :20016000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19DE 13 | :2001800010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE1910099C 14 | :2001A0001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102065 15 | :2001C000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102020074E 16 | :2001E0001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D101035 17 | :20020000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE193D 18 | :2002200010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009FB 19 | :200240001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE1910091020C4 20 | :20026000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100910202007AD 21 | :200280001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D101094 22 | :2002A000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE199D 23 | :2002C00010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE1910095B 24 | :2002E0001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102024 25 | :20030000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102020070C 26 | :200320001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010F3 27 | :20034000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19FC 28 | :2003600010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009BA 29 | :200380001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102083 30 | :2003A000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102020076C 31 | :2003C0001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D101053 32 | :2003E000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE195C 33 | :2004000010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100919 34 | :200420001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE1910091020E2 35 | :20044000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100910202007CB 36 | :200460001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010B2 37 | :20048000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19BB 38 | :2004A00010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100979 39 | :2004C0001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102042 40 | :2004E000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102020072B 41 | :200500001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D101011 42 | :20052000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191A 43 | :2005400010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009D8 44 | :200560001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE1910091020A1 45 | :20058000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102020078A 46 | :2005A0001010DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D101071 47 | :2005C000DE1910091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE197A 48 | :2005E00010091020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100938 49 | :200600001020DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE191009102000 50 | :20062000DE2A100A1060DE6E100E1040DE4C100C1050DE5D100D1010DE19100910202007E9 51 | :20064000FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE0252 52 | :20066000FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0D1A 53 | :20068000FE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0A0F 54 | :2006A000FE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CE5 55 | :2006C000FE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09200F9E 56 | :2006E000B015DD012005DD05DB5DB20DB00D2004200420042004DD04B2042004B104200478 57 | :20070000B004200720072007200720072007200720072004DB06DD6CB04E206C20062006C9 58 | :2007200020062006B0062006B1062006B060DD06B27E207EDD7EB20EDE0EB20EB00EDD7E13 59 | :20074000207EDB7EDE7EB001200AB20ADB7A2002DD7ADD0AB002DD7ADD7A207AB27ADE02F4 60 | :200760002001B009B219B0192001B2012001B1012001B001DB19DB19DB19B01FDB192007CC 61 | :20078000B051DD052005DD05B27DDD7D20052004B005B2502004DB04B04CDB04DB04B04C2D 62 | :2007A000B24CB04CB24CB20CDB4CB24CDB4CB27CB07CDD07B067DE062006DB06DE06B06003 63 | :2007C000B206B064DB06B216206E206EB06EB06EB26EB26EDB6EDB6EDE0EDB0E200EDB0E8E 64 | :2007E000DB0EDB0EB20EB00E200EDE02DB2A2002DB2ADD0AB202DB2ADB7ADB7AB22ADE0269 65 | :20080000B029B129B229DB09B209DB19B279B279B079B07920792079DD792079DD79200771 66 | :2008200020072007200720072007DB5D20072007200720072007B04CB24CB04CDB04B2046F 67 | :20084000B004200720072007200720072007200720072007B076B267B067B27620072007B9 68 | :2008600020072007200720072007200720072007B06EB06EB26EB26EDE0EB26E200EB20ECA 69 | :20088000DB0EDB0EDB0E200EB00BDE02DB2A2002B27ADD0AB002DB0AB22AB22AB02ADE0291 70 | :2008A000B00720012001200120012001DE09B00920072007DD09200720072007B0072007B5 71 | :2008C000DD04DB05B05DB25DDB5DB27D2005B05DB0542004B254DB04B04CDD04DB04B10C1C 72 | :2008E0002004B24CDD0C2004DB04DE04B10CB24CDD0CB27CDC7CDE7C2006DE06B06EB26E3C 73 | :200900002006DE06B0682004DE062006B06EDD06B065206EB06EB06E200E200E20072007FD 74 | :200920002007DE0EB27EB27EDB6EDE02B22A2007B00A20072007200220022002DE02B02AF0 75 | :20094000DE09DE09DD09B01FDB19B002DE09200720072007B219B209DB19B01FDE092007BB 76 | :20096000DD05B04DDD05B10DB25DB25D2005B054B0452004B04CDB04DB04DD04B045DB0429 77 | :200980002007B04CDD042004DB04DE04B04CB24CDD0CB24CB24CDB4CB004DE06DB06B06ED1 78 | :2009A0002006DE06DB062004DE062006DB06DD06DB06206CB064206EDE0EDB0EB20EDB0ECD 79 | :2009C000DD0EDE0EDB3EDB0EB22EDE02B22A2002DD02DB02B02ADD02DE022002DE02B02356 80 | :2009E000DE09DE09DD09DB19B2192001DE09200720072007B019B219B219DB19DE092007A6 81 | :200A0000DD05B050DD05DE05B05DB05D2005B045B040B004B040DB04B10CDD04204CB04C82 82 | :200A2000B004B040DD04B004B204DE04B045B04CDD04B04CB04CB24CB00CDE06B216B060A5 83 | :200A4000B006DE06B060B006DE06DB06B10CDB06DB06B216B068B068DE0EB20EB00E200E62 84 | :200A6000DD0EDE0EB22EB22EB02EDE02B02AB002DD02DB02B10ADD02DE022002DE02B0218C 85 | :200A8000DE09DE09DD09B219B0192001DE09200120012001DB01B019B019B219DE0920095A 86 | :200AA000200520052005DE05DB05B054B005B250200720072007200720072007B048DB0488 87 | :200AC0002004200720072007200420072007200720072004200720072007200720072007AF 88 | :200AE0002007200720062006DE06B064200420042004200420042004DE0EB27EB20E200E82 89 | :200B0000DD0E200EB00E200E200BDE02B02A2002200720072007200720072007DE02B02A25 90 | :200B200020072007200720072019B019B219200720072007200720072007B019B2192007A7 91 | :200B4000DB052005DD05DE05B05CDB05DB05B05DDD05B25DDF7DB27D20042004B248B0483C 92 | :200B6000B04CB24CB24CB27CDD7C2004B004B040DD04DB06DB06B065DD06DB06B06EDD06B1 93 | :200B80002004B206B06EB26EDE06DB062004B26EDB0EDB0EB20EDD0EDE0EB17EB27E200E3C 94 | :200BA000DD0EDE0EB20E200EDD0EDE02B202B021B02AB22ADE022002B02A2002DE02DB02AF 95 | :200BC000B0022001B219B019DB01DD01B279B0072001DD01DB19B209B009DB01B0192007DF 96 | :200BE000B0502005DD05DE05DB052005DE052005DD05DB5DDC7DDB5DB0072004DD08DB04B4 97 | :200C00002004B04CDD042004B24C20042004B048DD04DB06DD06DB06DD06B0642064DD068D 98 | :200C20002004B0652006B16EDE06B0682004DB6EDD0EB27EB00EDD0EDE0EB27EDB0E200ED6 99 | :200C4000DD0EDE0EDB0E200EDD0ADE02B002DE02DE02B02ADE022002DB022002DE02B021E1 100 | :200C600020012001B1192019DD01DD01DB1920012001DD01B219DB192001DB01DB012007A0 101 | :200C8000B0512005DD05DE05B10DB005DE052005DD05B25DB25DDB5DB00D2004DD08DB0411 102 | :200CA0002004DB04DD042004B04C20042004B148DD04B061DD06DB06DD06DB06DB06DD06B1 103 | :200CC0002004DB062006B06EDE06B1682004B26EDD0EDB0E200EDD0EDE0EDB7EB26E200E0A 104 | :200CE000DD0EDE0EB22E200EDD02DE022002DE02DE022021DE022002B0212002DE02B11295 105 | :200D000020012001B019B018DD01DD01B21920012001DD01B019B2192001B109B0182007FB 106 | :200D2000B0152005DD05DE05B050B205DB05DB05DB05B05DB05DB25D20042004B248B0484A 107 | :200D4000DB04204CB04C204C2045B045B048B248DD08B016B061B216DD06DB06DB06B206B3 108 | :200D6000B006B206DB06DB06DE06B2682004B06EB26EDB6EDB0EB20EDB0EB26EB06E200E9C 109 | :200D8000DB0EB22EB02E200EB202DE02DB02B0232021B021DE022002B0122002DE01B012A1 110 | :200DA000B0012001B201DB01B109DD01B019B0092001DD01DB01B0192001B018B21820073A 111 | :200DC000FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02CB 112 | :200DE000FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0D93 113 | :200E0000FE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0A87 114 | :200E2000FE02FE0EFE06FE04FE0CFE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0C5D 115 | :200E4000FE0DFE05FE01FE09FE03FE0AFE02FE0EFE06FE04FE0CFE0DFE05FE01FE09200F16 116 | :200E60004A0755074C075907FA083207390754074807FA0839073807FA0872076107690719 117 | :200E80006E0762076F0777077307FA08650776076507720779077707680765077207650778 118 | :200EA000FA08FA08FA08FA08FA08FA08FA08FA08FA08FA0820016C052007200765042007AE 119 | :200EC0002007670620072007690E200720076F02200720076E012001FA08FA08FA08FA0814 120 | :200EE000FA08FA08FA08FA08FA08FA08FA086407690765077A076E07790769076B0720071E 121 | :200F0000200720072007200720072007200720072007200720072007200720072007200761 122 | :200F2000200720072007200720072007200720072007200720072007200720072007200741 123 | :200F4000200720072007200720072007200720072007200720072007200720072007200721 124 | :200F6000200720072007200720072007200720072007200720072007200720072007200701 125 | :200F80002007200720072007200720072007200720072007200720072007200720072007E1 126 | :00000001FF 127 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | # Project Configuration: 3 | # 4 | # Specify the name of the design (project) and the Quartus II 5 | # Settings File (.qsf) 6 | ################################################################### 7 | 8 | PROJECT = vt100 9 | TOP_LEVEL_ENTITY = vt100 10 | ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf 11 | 12 | ################################################################### 13 | # Part, Family, Boardfile DE1 or DE2, or A-C8V4 14 | FAMILY = "Cyclone II" 15 | PART = EP2C8Q208C8 16 | BOARDFILE = A-C8V4Pins 17 | ################################################################### 18 | 19 | ################################################################### 20 | # Setup your sources here 21 | SRCS = vt100.vhd vga-controller.vhd vga_textmode.vhd vga-small.vhd \ 22 | font_rom.vhd bootrom.vhd displayram.vhd sram.vhd colour-rom.vhd \ 23 | components/T16450.vhd \ 24 | components/T80s.vhd components/T80_Pack.vhd components/T80.vhd components/T80_ALU.vhd components/T80_Reg.vhd components/T80_MCode.vhd 25 | 26 | OTHER_INPUT = rom1.hex charset.hex vga-rom.hex 27 | 28 | 29 | %.bin: %.asm 30 | # z80asm -v -l -a $< 31 | pasmo -1 -v $< $@.bin 32 | 33 | %.hex: %.bin 34 | trunc $< 4096 35 | bin2hex $< $@ 36 | 37 | SOF = output_files/$(PROJECT).sof 38 | POF = output_files/$(PROJECT).pof 39 | 40 | ################################################################### 41 | # Main Targets 42 | # 43 | # all: build everything 44 | # clean: remove output files and database 45 | # program: program your device with the compiled design 46 | ################################################################### 47 | 48 | all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt $(SOF) 49 | 50 | rom1.bin: rom1.asm 51 | 52 | clean: 53 | rm -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db 54 | 55 | map: smart.log $(PROJECT).map.rpt 56 | fit: smart.log $(PROJECT).fit.rpt 57 | asm: smart.log $(PROJECT).asm.rpt 58 | sta: smart.log $(PROJECT).sta.rpt 59 | smart: smart.log 60 | 61 | ################################################################### 62 | # Executable Configuration 63 | ################################################################### 64 | 65 | MAP_ARGS = --read_settings_files=on $(addprefix --source=,$(SRCS)) 66 | 67 | FIT_ARGS = --part=$(PART) --read_settings_files=on 68 | ASM_ARGS = 69 | STA_ARGS = 70 | 71 | ################################################################### 72 | # Target implementations 73 | ################################################################### 74 | 75 | STAMP = echo done > 76 | 77 | $(PROJECT).map.rpt: map.chg $(SOURCE_FILES) 78 | quartus_map $(MAP_ARGS) $(PROJECT) 79 | $(STAMP) fit.chg 80 | 81 | $(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt 82 | quartus_fit $(FIT_ARGS) $(PROJECT) 83 | $(STAMP) asm.chg 84 | $(STAMP) sta.chg 85 | 86 | $(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt 87 | quartus_asm $(ASM_ARGS) $(PROJECT) 88 | 89 | $(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt 90 | quartus_sta $(STA_ARGS) $(PROJECT) 91 | 92 | smart.log: $(ASSIGNMENT_FILES) 93 | quartus_sh --determine_smart_action $(PROJECT) > smart.log 94 | 95 | ################################################################### 96 | # Project initialization 97 | ################################################################### 98 | 99 | $(ASSIGNMENT_FILES): 100 | quartus_sh --prepare -f $(FAMILY) -t $(TOP_LEVEL_ENTITY) $(PROJECT) 101 | -cat $(BOARDFILE) >> $(PROJECT).qsf 102 | map.chg: 103 | $(STAMP) map.chg 104 | fit.chg: 105 | $(STAMP) fit.chg 106 | sta.chg: 107 | $(STAMP) sta.chg 108 | asm.chg: 109 | $(STAMP) asm.chg 110 | 111 | ################################################################### 112 | # Programming the device 113 | ################################################################### 114 | 115 | refresh_memory: $(SOF) $(OTHER_INPUT) 116 | quartus_cdb $(PROJECT) -c $(PROJECT) --update_mif 117 | quartus_asm $(PROJECT) 118 | 119 | program: $(SOF) $(OTHER_INPUT) 120 | quartus_pgm --no_banner --mode=jtag -o "P;$(SOF)" 121 | 122 | programflash: $(POF) $(OTHER_INPUT) 123 | quartus_pgm --no_banner --mode=as -o "P;$(POF)" 124 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # fpga-vt 2 | VT100-style terminal implemented on FPGA in VHDL 3 | 4 | This is a project to implement a DEC VT100 style serial terminal entirely in an FPGA (aside from a few supporting components). 5 | 6 | * VGA-style 16-colour 80x25 Text Mode display controller with 8x16 fonts on 9x16 grid (first focus of work) 7 | * T80 soft core Z80 processor (from opencores) 8 | * 16450 soft core UART (from opencores) 9 | * PS/2 keyboard interface (I have a nice IBM Model M for the authentic 80s feel) 10 | * Z80 software for terminal emulation 11 | 12 | The target FPGA board is the ebay Altera Cyclone II EPC5 mini-board, with 5000 LEs, 113Kbits of blockram and just I/O headers, so a small protoboard is necessary to add a VGA DAC and connector, an RS232 level-shifter and DB9 serial port, and finally a PS/2 keyboard port. 13 | 14 | A secondary aim is to end up with something that's a few pin-swaps away from Grant Searle's Multicomp, so I can play with that, too. 15 | -------------------------------------------------------------------------------- /VGA-ROM-8x16.hex: -------------------------------------------------------------------------------- 1 | :200000000000000000000000000000000000000000007E81A58181BD9981817E0000000064 2 | :2000200000007EFFDBFFFFC3E7FFFF7E00000000000000006CFEFEFEFE7C3810000000001C 3 | :200040000000000010387CFE7C38100000000000000000183C3CE7E7E718183C0000000069 4 | :20006000000000183C7EFFFF7E18183C00000000000000000000183C3C180000000000001E 5 | :20008000FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF00000000003C664242663C000000000050 6 | :2000A000FFFFFFFFFFC399BDBD99C3FFFFFFFFFF00001E0E1A3278CCCCCCCC780000000080 7 | :2000C00000003C666666663C187E18180000000000003F333F3030303070F0E00000000099 8 | :2000E00000007F637F6363636367E7E6C00000000000001818DB3CE73CDB181800000000AA 9 | :200100000080C0E0F0F8FEF8F0E0C080000000000002060E1E3EFE3E1E0E060200000000EF 10 | :200120000000183C7E1818187E3C180000000000000066666666666666006666000000003D 11 | :2001400000007FDBDBDB7B1B1B1B1B1B00000000007CC660386CC6C66C380CC67C000000C9 12 | :200160000000000000000000FEFEFEFE000000000000183C7E1818187E3C187E000000001D 13 | :200180000000183C7E18181818181818000000000000181818181818187E3C18000000006B 14 | :2001A0000000000000180CFE0C1800000000000000000000003060FE6030000000000000DB 15 | :2001C000000000000000C0C0C0FE00000000000000000000002466FF6624000000000000CE 16 | :2001E000000000001038387C7CFEFE000000000000000000FEFE7C7C383810000000000017 17 | :20020000000000000000000000000000000000000000183C3C3C181818001818000000009A 18 | :20022000006666662400000000000000000000000000006C6CFE6C6C6CFE6C6C0000000078 19 | :2002400018187CC6C2C07C060686C67C1818000000000000C2C60C183060C68600000000A2 20 | :200260000000386C6C3876DCCCCCCC7600000000003030306000000000000000000000001A 21 | :2002800000000C18303030303030180C00000000000030180C0C0C0C0C0C1830000000001E 22 | :2002A0000000000000663CFF3C66000000000000000000000018187E18180000000000001D 23 | :2002C0000000000000000000001818183000000000000000000000FE0000000000000000A8 24 | :2002E000000000000000000000001818000000000000000002060C183060C08000000000D2 25 | :2003000000003C66C3C3DBDBC3C3663C0000000000001838781818181818187E0000000001 26 | :2003200000007CC6060C183060C0C6FE0000000000007CC606063C060606C67C000000005F 27 | :2003400000000C1C3C6CCCFE0C0C0C1E000000000000FEC0C0C0FC060606C67C0000000033 28 | :2003600000003860C0C0FCC6C6C6C67C000000000000FEC606060C18303030300000000021 29 | :2003800000007CC6C6C67CC6C6C6C67C0000000000007CC6C6C67E0606060C78000000009D 30 | :2003A00000000000181800000018180000000000000000001818000000181830000000004D 31 | :2003C000000000060C18306030180C060000000000000000007E00007E000000000000000D 32 | :2003E0000000006030180C060C1830600000000000007CC6C60C1818180018180000000003 33 | :200400000000007CC6C6DEDEDEDCC07C00000000000010386CC6C6FEC6C6C6C600000000CC 34 | :200420000000FC6666667C66666666FC0000000000003C66C2C0C0C0C0C2663C00000000B6 35 | :200440000000F86C6666666666666CF8000000000000FE6662687868606266FE000000003C 36 | :200460000000FE6662687868606060F00000000000003C66C2C0C0DEC6C6663A0000000070 37 | :200480000000C6C6C6C6FEC6C6C6C6C60000000000003C18181818181818183C0000000030 38 | :2004A00000001E0C0C0C0C0CCCCCCC78000000000000E666666C78786C6666E600000000DA 39 | :2004C0000000F06060606060606266FE000000000000C3E7FFFFDBC3C3C3C3C300000000D4 40 | :2004E0000000C6E6F6FEDECEC6C6C6C60000000000007CC6C6C6C6C6C6C6C67C0000000070 41 | :200500000000FC6666667C60606060F00000000000007CC6C6C6C6C6C6D6DE7C0C0E000057 42 | :200520000000FC6666667C6C666666E60000000000007CC6C660380C06C6C67C00000000D3 43 | :200540000000FFDB991818181818183C000000000000C6C6C6C6C6C6C6C6C67C00000000EA 44 | :200560000000C3C3C3C3C3C3C3663C18000000000000C3C3C3C3C3DBDBFF6666000000001C 45 | :200580000000C3C3663C18183C66C3C3000000000000C3C3C3663C181818183C0000000054 46 | :2005A0000000FFC3860C183060C1C3FF0000000000003C30303030303030303C00000000C4 47 | :2005C00000000080C0E070381C0E06020000000000003C0C0C0C0C0C0C0C0C3C0000000049 48 | :2005E00010386CC600000000000000000000000000000000000000000000000000FF000082 49 | :20060000303018000000000000000000000000000000000000780C7CCCCCCC760000000088 50 | :200620000000E06060786C666666667C0000000000000000007CC6C0C0C0C67C000000005E 51 | :2006400000001C0C0C3C6CCCCCCCCC760000000000000000007CC6FEC0C0C67C0000000016 52 | :200660000000386C6460F060606060F000000000000000000076CCCCCCCCCC7C0CCC780074 53 | :200680000000E060606C7666666666E60000000000001818003818181818183C000000003E 54 | :2006A00000000606000E06060606060666663C000000E06060666C78786C66E600000000DA 55 | :2006C00000003818181818181818183C000000000000000000E6FFDBDBDBDBDB00000000BA 56 | :2006E0000000000000DC6666666666660000000000000000007CC6C6C6C6C67C00000000E4 57 | :200700000000000000DC66666666667C6060F000000000000076CCCCCCCCCC7C0C0C1E00AF 58 | :200720000000000000DC7666606060F00000000000000000007CC660380CC67C00000000C9 59 | :200740000000103030FC30303030361C000000000000000000CCCCCCCCCCCC7600000000DD 60 | :200760000000000000C3C3C3C3663C18000000000000000000C3C3C3DBDBFF66000000004F 61 | :200780000000000000C3663C183C66C3000000000000000000C6C6C6C6C6C67E060CF8004B 62 | :2007A0000000000000FECC183060C6FE0000000000000E18181870181818180E00000000CF 63 | :2007C000000018181818001818181818000000000000701818180E181818187000000000AB 64 | :2007E000000076DC0000000000000000000000000000000010386CC6C6C6FE0000000000A3 65 | :2008000000003C66C2C0C0C0C2663C0C067C00000000CC0000CCCCCCCCCCCC760000000038 66 | :20082000000C1830007CC6FEC0C0C67C000000000010386C00780C7CCCCCCC7600000000D4 67 | :200840000000CC0000780C7CCCCCCC76000000000060301800780C7CCCCCCC760000000070 68 | :2008600000386C3800780C7CCCCCCC7600000000000000003C666060663C0C063C00000070 69 | :200880000010386C007CC6FEC0C0C67C000000000000C600007CC6FEC0C0C67C00000000DA 70 | :2008A00000603018007CC6FEC0C0C67C0000000000006600003818181818183C000000003C 71 | :2008C00000183C66003818181818183C0000000000603018003818181818183C00000000DE 72 | :2008E00000C60010386CC6C6FEC6C6C600000000386C3800386CC6C6FEC6C6C60000000046 73 | :2009000018306000FE66607C606066FE0000000000000000006E3B1B7ED8DC77000000005E 74 | :2009200000003E6CCCCCFECCCCCCCCCE000000000010386C007CC6C6C6C6C67C00000000EF 75 | :200940000000C600007CC6C6C6C6C67C0000000000603018007CC6C6C6C6C67C000000007D 76 | :20096000003078CC00CCCCCCCCCCCC76000000000060301800CCCCCCCCCCCC7600000000DF 77 | :200980000000C60000C6C6C6C6C6C67E060C780000C6007CC6C6C6C6C6C6C67C00000000BD 78 | :2009A00000C600C6C6C6C6C6C6C6C67C000000000018187EC3C0C0C0C37E181800000000A3 79 | :2009C00000386C6460F060606060E6FC000000000000C3663C18FF18FF1818180000000082 80 | :2009E00000FC66667C62666F666666F300000000000E1B1818187E1818181818D8700000A8 81 | :200A00000018306000780C7CCCCCCC7600000000000C1830003818181818183C0000000014 82 | :200A200000183060007CC6C6C6C6C67C000000000018306000CCCCCCCCCCCC760000000052 83 | :200A4000000076DC00DC6666666666660000000076DC00C6E6F6FEDECEC6C6C60000000014 84 | :200A6000003C6C6C3E007E00000000000000000000386C6C38007C000000000000000000E2 85 | :200A80000000303000303060C0C6C67C00000000000000000000FEC0C0C0C0000000000070 86 | :200AA000000000000000FE06060606000000000000C0C0C2C6CC183060CE9B060C1F00000A 87 | :200AC00000C0C0C2C6CC183066CE963E0606000000001818001818183C3C3C1800000000A2 88 | :200AE0000000000000366CD86C360000000000000000000000D86C366CD80000000000001C 89 | :200B00001144114411441144114411441144114455AA55AA55AA55AA55AA55AA55AA55AA35 90 | :200B2000DD77DD77DD77DD77DD77DD77DD77DD771818181818181818181818181818181895 91 | :200B400018181818181818F818181818181818181818181818F818F81818181818181818F5 92 | :200B600036363636363636F6363636363636363600000000000000FE3636363636363636A7 93 | :200B80000000000000F818F818181818181818183636363636F606F63636363636363636DD 94 | :200BA000363636363636363636363636363636360000000000FE06F636363636363636362B 95 | :200BC0003636363636F606FE000000000000000036363636363636FE000000000000000095 96 | :200BE0001818181818F818F8000000000000000000000000000000F81818181818181818BD 97 | :200C0000181818181818181F000000000000000018181818181818FF000000000000000066 98 | :200C200000000000000000FF1818181818181818181818181818181F18181818181818186E 99 | :200C400000000000000000FF000000000000000018181818181818FF18181818181818182E 100 | :200C600018181818181F181F18181818181818183636363636363637363636363636363685 101 | :200C8000363636363637303F000000000000000000000000003F303736363636363636364A 102 | :200CA0003636363636F700FF00000000000000000000000000FF00F736363636363636368A 103 | :200CC000363636363637303736363636363636360000000000FF00FF0000000000000000BA 104 | :200CE0003636363636F700F736363636363636361818181818FF00FF0000000000000000D2 105 | :200D000036363636363636FF00000000000000000000000000FF00FF18181818181818189C 106 | :200D200000000000000000FF3636363636363636363636363636363F00000000000000004B 107 | :200D400018181818181F181F000000000000000000000000001F181F1818181818181818AF 108 | :200D6000000000000000003F363636363636363636363636363636FF36363636363636365B 109 | :200D80001818181818FF18FF181818181818181818181818181818F8000000000000000065 110 | :200DA000000000000000001F1818181818181818FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF64 111 | :200DC00000000000000000FFFFFFFFFFFFFFFFFFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01C 112 | :200DE0000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0FFFFFFFFFFFFFFF0000000000000000000A 113 | :200E0000000000000076DCD8D8D8DC7600000000000078CCCCCCD8CCC6C6C6CC0000000008 114 | :200E20000000FEC6C6C0C0C0C0C0C0C00000000000000000FE6C6C6C6C6C6C6C00000000F6 115 | :200E4000000000FEC66030183060C6FE0000000000000000007ED8D8D8D8D87000000000AC 116 | :200E60000000000066666666667C6060C00000000000000076DC1818181818180000000096 117 | :200E80000000007E183C6666663C187E00000000000000386CC6C6FEC6C66C38000000001E 118 | :200EA0000000386CC6C6C66C6C6C6CEE0000000000001E30180C3E666666663C000000001A 119 | :200EC00000000000007EDBDBDB7E00000000000000000003067EDBDBF37E60C000000000B7 120 | :200EE00000001C3060607C606060301C000000000000007CC6C6C6C6C6C6C6C60000000052 121 | :200F000000000000FE0000FE0000FE00000000000000000018187E18180000FF00000000FA 122 | :200F200000000030180C060C1830007E000000000000000C18306030180C007E00000000FF 123 | :200F400000000E1B1B18181818181818181818181818181818181818D8D8D870000000008D 124 | :200F6000000000001818007E0018180000000000000000000076DC0076DC000000000000EF 125 | :200F800000386C6C38000000000000000000000000000000000000181800000000000000D9 126 | :200FA00000000000000000001800000000000000000F0C0C0C0C0CEC6C6C3C1C00000000B2 127 | :200FC00000D86C6C6C6C6C0000000000000000000070D83060C8F800000000000000000085 128 | :200FE000000000007C7C7C7C7C7C7C0000000000000000000000000000000000000000008D 129 | :00000001FF 130 | -------------------------------------------------------------------------------- /VGA-ROM.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/VGA-ROM.bin -------------------------------------------------------------------------------- /bin2hex.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/bin2hex.exe -------------------------------------------------------------------------------- /bootrom.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2013 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component bootrom 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 20 | clock : IN STD_LOGIC := '1'; 21 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 22 | ); 23 | end component; 24 | -------------------------------------------------------------------------------- /bootrom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "bootrom.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "bootrom.cmp"] 5 | -------------------------------------------------------------------------------- /bootrom.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ROM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: bootrom.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2013 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY bootrom IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 46 | clock : IN STD_LOGIC := '1'; 47 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 48 | ); 49 | END bootrom; 50 | 51 | 52 | ARCHITECTURE SYN OF bootrom IS 53 | 54 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 55 | 56 | 57 | 58 | COMPONENT altsyncram 59 | GENERIC ( 60 | clock_enable_input_a : STRING; 61 | clock_enable_output_a : STRING; 62 | init_file : STRING; 63 | intended_device_family : STRING; 64 | lpm_hint : STRING; 65 | lpm_type : STRING; 66 | numwords_a : NATURAL; 67 | operation_mode : STRING; 68 | outdata_aclr_a : STRING; 69 | outdata_reg_a : STRING; 70 | widthad_a : NATURAL; 71 | width_a : NATURAL; 72 | width_byteena_a : NATURAL 73 | ); 74 | PORT ( 75 | address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 76 | clock0 : IN STD_LOGIC ; 77 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 78 | ); 79 | END COMPONENT; 80 | 81 | BEGIN 82 | q <= sub_wire0(7 DOWNTO 0); 83 | 84 | altsyncram_component : altsyncram 85 | GENERIC MAP ( 86 | clock_enable_input_a => "BYPASS", 87 | clock_enable_output_a => "BYPASS", 88 | init_file => "rom1.hex", 89 | intended_device_family => "Cyclone II", 90 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM", 91 | lpm_type => "altsyncram", 92 | numwords_a => 4096, 93 | operation_mode => "ROM", 94 | outdata_aclr_a => "NONE", 95 | outdata_reg_a => "UNREGISTERED", 96 | widthad_a => 12, 97 | width_a => 8, 98 | width_byteena_a => 1 99 | ) 100 | PORT MAP ( 101 | address_a => address, 102 | clock0 => clock, 103 | q_a => sub_wire0 104 | ); 105 | 106 | 107 | 108 | END SYN; 109 | 110 | -- ============================================================ 111 | -- CNX file retrieval info 112 | -- ============================================================ 113 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 114 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 115 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 116 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 117 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 118 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 119 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 120 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 121 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 122 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 123 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 124 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 125 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 126 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 127 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 128 | -- Retrieval info: PRIVATE: JTAG_ID STRING "ROM" 129 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 130 | -- Retrieval info: PRIVATE: MIFfilename STRING "rom1.hex" 131 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 132 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 133 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 134 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 135 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 138 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 139 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 140 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 141 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 142 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 143 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 144 | -- Retrieval info: CONSTANT: INIT_FILE STRING "rom1.hex" 145 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 146 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM" 147 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 148 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 149 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 150 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 151 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 152 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 153 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 154 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 155 | -- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 156 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 157 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 158 | -- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 159 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 160 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 161 | -- Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.vhd TRUE 162 | -- Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.inc FALSE 163 | -- Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.cmp TRUE 164 | -- Retrieval info: GEN_FILE: TYPE_NORMAL bootrom.bsf FALSE 165 | -- Retrieval info: GEN_FILE: TYPE_NORMAL bootrom_inst.vhd FALSE 166 | -- Retrieval info: LIB_FILE: altera_mf 167 | -------------------------------------------------------------------------------- /charset.hex: -------------------------------------------------------------------------------- 1 | :100000004F07480720074C074F074F074B072107AB 2 | :10001000200749077407270773072007720765073A 3 | :1000200061076C0720076F0775077407700775076E 4 | :1000300074072007660772076F076D0720074607DA 5 | :100040005007470741072D07760774073107300728 6 | :10005000300721072007200720072007DA07C407F9 7 | :10006000C407C407BF072007DA07C407C407C407CB 8 | :10007000C407C407C407C407C407C407C407C40728 9 | :10008000C407C407C407C407C407C407C407C40718 10 | :10009000C407C407C407C407C407C407C407BF070D 11 | :1000A000410742074307440745074607470720071C 12 | :1000B0002007300731073207200720076107620752 13 | :1000C000630764076507660767072007200720079F 14 | :1000D00021074007230724072507200720072007BB 15 | :1000E0007E072007600720072B072007200720072F 16 | :1000F000200720072007200720072007B3075F07F6 17 | :100100005F075F07B3072007B3074E076F07200796 18 | :100110007407650773077407200766076F07720780 19 | :10012000200746874C8741875387488720077907F0 20 | :100130006507740720072007200720072007B3075B 21 | :10014000480749074A074B074C074D074E0720074A 22 | :10015000200733073407350720072007680769079A 23 | :100160006A076B076C076D076E07200720072007DB 24 | :100170005E0726072A0728072907200720072007E8 25 | :100180003B0720073A0720073D07200720072007E5 26 | :10019000200720072007200720072007B3072D0787 27 | :1001A0002D072D07B3072007B307200720072007D7 28 | :1001B0002007200720072007200720072007200707 29 | :1001C00020072007200720072007200720072007F7 30 | :1001D0002007200720072007200720072007B30754 31 | :1001E0004F07500751075207530754075507200779 32 | :1001F0002007360737073807200720076F077007E3 33 | :100200007107720773077407750720072007200717 34 | :100210007B077D075B075D073C073E07200720073C 35 | :10022000270720072207200720072007200720078D 36 | :10023000200720072007200720072007B3075807BB 37 | :1002400058075807B3072007B307200720072007E0 38 | :100250002007200720072007200720072007200766 39 | :100260002007200720072007200720072007200756 40 | :100270002007200720072007200720072007B307B3 41 | :10028000200756075707580759075A07200720071E 42 | :1002900020072007300720072007200720077607C0 43 | :1002A0007707780779077A072007200720072007B4 44 | :1002B0002E072C072F073F075C077C072007200726 45 | :1002C0002D0720075F0720072007200720072007AA 46 | :1002D000200720072007200720072007B3077C07F7 47 | :1002E0007C077C07B3072007B307200720072007F8 48 | :1002F00020072007200720072007200720072007C6 49 | :1003000020072007200720072007200720072007B5 50 | :100310002007200720072007200720072007B30712 51 | :1003200041076E076407200773076F076D076507AE 52 | :10033000200763076F076C076F077507720773075E 53 | :100340003A0720072007200720072007200720075B 54 | :100350002007200720072007200720072007200765 55 | :100360002007200720072007200720072007200755 56 | :10037000200720072007200720072007C007C40701 57 | :10038000C407C407D9072007C007C407C407C407A8 58 | :10039000C407C407C407C407C407C407C407C40705 59 | :1003A000C407C407C407C407C407C407C407C407F5 60 | :1003B000C407C407C407C407C407C407C407D907D0 61 | :1003C000DA02C402C402C402C402BF022007D60378 62 | :1003D000C403C403C403B70320072007D604B7042B 63 | :1003E0002007D605B7052007D606B706D607B707F4 64 | :1003F000D608B708D609B709D60AB70AD60BB70B7D 65 | :10040000D60CB70CD60DB70DD60EB70ED60FB70F4C 66 | :1004100020072007200720072007200720072007A4 67 | :100420002007200720072007200720072007200794 68 | :100430002007200720072007200720072007200784 69 | :100440002007200720072007200720072007200774 70 | :100450002007200720072007200720072007200764 71 | :10046000B3022007200720072007B3022007BA03A2 72 | :10047000200720072007BA0320072007D304BD0464 73 | :100480002007D305BD052007D306BD06D307BD074A 74 | :10049000D308BD08D309BD09D30ABD0AD30BBD0BD0 75 | :1004A000D30CBD0CD30DBD0DD30EBD0ED30FBD0FA0 76 | :1004B0002007200720072007460747072007630774 77 | :1004C0006F076C076F077507720773072007200710 78 | :1004D00020072007200720072007200720072007E4 79 | :1004E00020072007200720072007200720072007D4 80 | :1004F00020072007200720072007200720072007C4 81 | :10050000C002C402C402C402C402D9022007D30339 82 | :10051000C403C403C403BD0320072007200720072A 83 | :100520002007200720072007200720072007200793 84 | :100530002007200720072007200720072007200783 85 | :100540002007200720072007200720072007200773 86 | :100550002007200720072007200720072007200763 87 | :100560002007200720072007200720072007200753 88 | :100570002007200720072007200720072007200743 89 | :100580002007200720072007200720072007200733 90 | :100590002007200720072007200720072007200723 91 | :1005A0002007200720072007200720072007200713 92 | :1005B0002007200720072007200720072007200703 93 | :1005C00020072007200720072007200720072007F3 94 | :1005D00020072007200720072007200720072007E3 95 | :1005E00020072007200720072007200720072007D3 96 | :1005F00020072007200720072007200720072007C3 97 | :1006000020072007200720072007200720072007B2 98 | :1006100020072007200720072007200720072007A2 99 | :100620002007200720072007200720072007200792 100 | :100630002007200720072007200720072007200782 101 | :10064000D61FB71FD62FB72FD63FB73FD64FB74FBE 102 | :10065000D65FB75FD66FB76FD67FB77FD60FB70FAE 103 | :100660002007200742074707200763076F076C072B 104 | :100670006F07750772077307200720072007C91443 105 | :10068000BB142007C91EBB1E2007C92EBB2E200786 106 | :10069000C925BB252007C91BBB1B2007C95FBB5F42 107 | :1006A0002007C94FBB4F2007740F6F0F670F650FEF 108 | :1006B000740F680F650F720F200F610F740F200FFA 109 | :1006C0006C0F610F730F740F210F20072007200795 110 | :1006D00020072007200720072007200720072007E2 111 | :1006E000D31FBD1FD32FBD2FD33FBD3FD34FBD4F12 112 | :1006F000D35FBD5FD36FBD6FD37FBD7FD30FBD0F02 113 | :1007000020072007200720072007200720072007B1 114 | :100710002007200720072007200720072007C814EC 115 | :10072000BC142007C81EBC1E2007C82EBC2E2007E4 116 | :10073000C825BC252007C81BBC1B2007C85FBC5FA1 117 | :100740002007C84FBC4F200720072007200720079D 118 | :100750002007200720072007200720072007200761 119 | :100760002007200720072007200720072007200751 120 | :100770002007200720072007200720072007200741 121 | :100780002007200720072007200720072007200731 122 | :100790002007200720072007200720072007200721 123 | :1007A0002007200720072007200720072007200711 124 | :1007B0002007200720072007200720072007200701 125 | :1007C00020072007200720072007200720072007F1 126 | :1007D00020072007200720072007200720072007E1 127 | :1007E00020072007200720072007200720072007D1 128 | :1007F0002007200720072007C50F2007CE0F20075E 129 | :10080000D80F2007D70F2007E80F2007E90F200790 130 | :100810009B0F20079C0F2007990F2007EF0F200741 131 | :100820002007200720072007200720072007200790 132 | :100830002007200720072007200720072007200780 133 | :100840002007200720072007200720072007200770 134 | :100850002007200720072007200720072007200760 135 | :100860002007200720072007200720072007200750 136 | :100870002007200720072007200720072007200740 137 | :100880002007200720072007200720072007200730 138 | :100890002007200720072007200720072007200720 139 | :1008A0002007200720072007200720072007200710 140 | :1008B0002007200720072007200720072007200700 141 | :1008C00054076F076F0720076D07750763076807F1 142 | :1008D00020076F07660720076107200767076F0774 143 | :1008E0006F07640720077407680769076E076707C3 144 | :1008F000200769077307200757074F074E0744076C 145 | :1009000045075207460755074C07210720072D07C3 146 | :1009100020074D076107650720075707650773071D 147 | :10092000740720072007200720072007200720073B 148 | :100930002007200720072007D60F2007B70F200722 149 | :10094000D30F2007BD0F2007C40F2007BA0F2007C1 150 | :10095000C70F2007B60F2007D00F2007D20F2007A0 151 | :10096000200720072007200720072007200720074F 152 | :10097000200720072007200720072007200720073F 153 | :10098000200720072007200720072007200720072F 154 | :10099000200720072007200720072007200720071F 155 | :1009A000200720072007200720072007200720070F 156 | :1009B00020072007200720072007200720072007FF 157 | :1009C00020072007200720072007200720072007EF 158 | :1009D0002007200720072007200F200F200F200FBF 159 | :1009E000200F200F200F200F200F200F200F200F8F 160 | :1009F000200F200F200F200F200F200F200F200787 161 | :100A0000B00FB00FB00FB10FB10FB10FB20FB20FE7 162 | :100A1000B20FDB0FDB0FDB0FDF0FDF0FDF0FDC0FA2 163 | :100A2000DC0FDC0FDD0FDD0FDD0FDE0FDE0FDE0F65 164 | :100A3000200720072007200720072007200720077E 165 | :100A4000200720072007200720072007200720076E 166 | :100A5000200720072007200720072007200720075E 167 | :100A6000200720072007200720072007200720074E 168 | :100A70002007200720072007D50F2007B80F2007E1 169 | :100A8000D40F2007BE0F2007CD0F2007B30F20077C 170 | :100A9000C60F2007B50F2007CF0F2007D10F200763 171 | :100AA000200720072007200720072007200720070E 172 | :100AB00020072007200720072007200720072007FE 173 | :100AC00020072007200720072007200720072007EE 174 | :100AD00020072007200720072007200720072007DE 175 | :100AE00020072007200720072007200720072007CE 176 | :100AF00020072007200720072007200720072007BE 177 | :100B000020072007200720072007200720072007AD 178 | :100B1000200720072007200720072007200720079D 179 | :100B2000200720072007200720072007200720078D 180 | :100B3000200720072007200720072007200720077D 181 | :100B4000010F2007020F2007030F2007040F2007C3 182 | :100B5000050F2007060F2007F00F20077F0F200743 183 | :100B60000E0F20070F0F2007E30F2007F10F2007BC 184 | :100B7000F40F2007F50F2007EA0F20079D0F20072D 185 | :100B8000E40F2007F80F2007FB0F2007FC0F2007BA 186 | :100B9000830F2007840F2007850F2007A00F200751 187 | :100BA000A60F2007860F20078E0F20078F0F200724 188 | :100BB000910F2007920F2007C50F2007CE0F2007A7 189 | :100BC000D80F2007D70F2007E80F2007E90F2007CD 190 | :100BD0009B0F20079C0F2007990F2007EF0F20077E 191 | :100BE00020072007200720072007200720072007CD 192 | :100BF00020072007200720072007200720072007BD 193 | :100C000020072007200720072007200720072007AC 194 | :100C1000200720072007200720072007200720079C 195 | :100C2000200720072007200720072007200720078C 196 | :100C3000200720072007200720072007200720077C 197 | :100C4000200720072007200720072007200720076C 198 | :100C5000200720072007200720072007200720075C 199 | :100C6000200720072007200720072007200720074C 200 | :100C7000200720072007200720072007200720073C 201 | :100C8000180F2007190F20071E0F20071F0F20071E 202 | :100C9000100F2007110F2007120F20071D0F20072C 203 | :100CA000140F2007150F2007E00F2007E10F200782 204 | :100CB000E20F2007E50F2007E60F2007E70F2007C8 205 | :100CC000EB0F2007EC0F2007ED0F2007EE0F20079A 206 | :100CD000880F2007890F20078A0F2007820F20071F 207 | :100CE000900F20078C0F20078B0F20078D0F2007F8 208 | :100CF000A10F20079E0F2007DA0F2007BF0F200744 209 | :100D0000C00F2007D90F2007C40F2007B30F2007FB 210 | :100D1000C30F2007B40F2007C10F2007C20F200701 211 | :100D2000200720072007200720072007200720078B 212 | :100D3000200720072007200720072007200720077B 213 | :100D4000200720072007200720072007200720076B 214 | :100D5000200720072007200720072007200720075B 215 | :100D6000200720072007200720072007200720074B 216 | :100D7000200720072007200720072007200720073B 217 | :100D8000200720072007200720072007200720072B 218 | :100D9000200720072007200720072007200720071B 219 | :100DA000200720072007200720072007200720070B 220 | :100DB00020072007200720072007200720072007FB 221 | :100DC000AE0F2007AF0F2007F20F2007F30F200709 222 | :100DD000A90F2007AA0F2007FD0F2007F60F2007F5 223 | :100DE000AB0F2007AC0F2007800F2007870F2007CD 224 | :100DF000A50F2007A40F2007980F20079F0F20079B 225 | :100E0000F70F2007F90F2007AD0F2007A80F2007C5 226 | :100E1000930F2007940F2007950F2007A20F20079C 227 | :100E2000A70F2007960F2007810F2007970F200795 228 | :100E3000A30F20079A0F2007C90F2007BB0F200719 229 | :100E4000C80F2007BC0F2007CD0F2007BA0F2007BF 230 | :100E5000CC0F2007B90F2007CA0F2007CB0F2007A0 231 | :100E6000200720072007200720072007200720074A 232 | :100E7000200720072007200720072007200720073A 233 | :100E8000200720072007200720072007200720072A 234 | :100E9000200720072007200720072007200720071A 235 | :100EA000200720072007200720072007200720070A 236 | :100EB00020072007200720072007200720072007FA 237 | :100EC00020072007200720072007200720072007EA 238 | :100ED00020072007200720072007200720072007DA 239 | :100EE00020072007200720072007200720072007CA 240 | :100EF00020072007200720072007200720072007BA 241 | :100F000042074F07540754074F074D0720074C0768 242 | :100F100049074E074507200742074F075407540764 243 | :100F20004F074D0720074C0749074E074507200785 244 | :100F300042074F07540754074F074D0720074C0738 245 | :100F400049074E074507200742074F075407540734 246 | :100F50004F074D0720074C0749074E074507200755 247 | :100F60002D072D072D072D072D072D072D072D07E1 248 | :100F70002D072D072D072D072D072D072D072D07D1 249 | :100F80002D072D072D072D072D072D072D072D07C1 250 | :100F90002D072D072D072D072D072D073E072007AD 251 | :100FA0000000000000000000000000000000000041 252 | :100FB0000000000000000000000000000000000031 253 | :100FC0000000000000000000000000000000000021 254 | :100FD0000000000000000000000000000000000011 255 | :100FE0000000000000000000000000000000000001 256 | :100FF00000000000000000000000000000000000F1 257 | :00000001FF 258 | -------------------------------------------------------------------------------- /colour-rom.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | entity COLOUR_ROM is 7 | port( 8 | A : in std_logic_vector(3 downto 0); 9 | D : out std_logic_vector(5 downto 0) 10 | ); 11 | end COLOUR_ROM; 12 | 13 | -- VGA palette taken from http://cpansearch.perl.org/src/BRICAS/Image-TextMode-0.25/lib/Image/TextMode/Palette/VGA.pm 14 | 15 | -- generate a 2-bit per channel RGB value from a VGA colour number 16 | 17 | architecture rtl of COLOUR_ROM is 18 | subtype ROM_WORD is std_logic_vector(5 downto 0); 19 | type ROM_TABLE is array(0 to 15) of ROM_WORD; 20 | constant ROM : ROM_TABLE := ROM_TABLE'( 21 | "000000", 22 | "000010", 23 | "001000", 24 | "001010", 25 | "100000", 26 | "100010", 27 | "100100", 28 | "101010", 29 | "010101", 30 | "010111", 31 | "011101", 32 | "011111", 33 | "110101", 34 | "110111", 35 | "111101", 36 | "111111" 37 | ); -- 0x0FFF 38 | begin 39 | D <= ROM(to_integer(unsigned(A))); 40 | end; 41 | -------------------------------------------------------------------------------- /components/T80_ALU.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Z80 compatible microprocessor core 3 | -- 4 | -- Version : 0247 5 | -- 6 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 7 | -- 8 | -- All rights reserved 9 | -- 10 | -- Redistribution and use in source and synthezised forms, with or without 11 | -- modification, are permitted provided that the following conditions are met: 12 | -- 13 | -- Redistributions of source code must retain the above copyright notice, 14 | -- this list of conditions and the following disclaimer. 15 | -- 16 | -- Redistributions in synthesized form must reproduce the above copyright 17 | -- notice, this list of conditions and the following disclaimer in the 18 | -- documentation and/or other materials provided with the distribution. 19 | -- 20 | -- Neither the name of the author nor the names of other contributors may 21 | -- be used to endorse or promote products derived from this software without 22 | -- specific prior written permission. 23 | -- 24 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 28 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 | -- POSSIBILITY OF SUCH DAMAGE. 35 | -- 36 | -- Please report bugs to the author, but before you do so, please 37 | -- make sure that this is not a derivative work and that 38 | -- you have the latest version of this file. 39 | -- 40 | -- The latest version of this file can be found at: 41 | -- http://www.opencores.org/cvsweb.shtml/t80/ 42 | -- 43 | -- Limitations : 44 | -- 45 | -- File history : 46 | -- 47 | -- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test 48 | -- 49 | -- 0238 : Fixed zero flag for 16 bit SBC and ADC 50 | -- 51 | -- 0240 : Added GB operations 52 | -- 53 | -- 0242 : Cleanup 54 | -- 55 | -- 0247 : Cleanup 56 | -- 57 | 58 | library IEEE; 59 | use IEEE.std_logic_1164.all; 60 | use IEEE.numeric_std.all; 61 | 62 | entity T80_ALU is 63 | generic( 64 | Mode : integer := 0; 65 | Flag_C : integer := 0; 66 | Flag_N : integer := 1; 67 | Flag_P : integer := 2; 68 | Flag_X : integer := 3; 69 | Flag_H : integer := 4; 70 | Flag_Y : integer := 5; 71 | Flag_Z : integer := 6; 72 | Flag_S : integer := 7 73 | ); 74 | port( 75 | Arith16 : in std_logic; 76 | Z16 : in std_logic; 77 | ALU_Op : in std_logic_vector(3 downto 0); 78 | IR : in std_logic_vector(5 downto 0); 79 | ISet : in std_logic_vector(1 downto 0); 80 | BusA : in std_logic_vector(7 downto 0); 81 | BusB : in std_logic_vector(7 downto 0); 82 | F_In : in std_logic_vector(7 downto 0); 83 | Q : out std_logic_vector(7 downto 0); 84 | F_Out : out std_logic_vector(7 downto 0) 85 | ); 86 | end T80_ALU; 87 | 88 | architecture rtl of T80_ALU is 89 | 90 | procedure AddSub(A : std_logic_vector; 91 | B : std_logic_vector; 92 | Sub : std_logic; 93 | Carry_In : std_logic; 94 | signal Res : out std_logic_vector; 95 | signal Carry : out std_logic) is 96 | variable B_i : unsigned(A'length - 1 downto 0); 97 | variable Res_i : unsigned(A'length + 1 downto 0); 98 | begin 99 | if Sub = '1' then 100 | B_i := not unsigned(B); 101 | else 102 | B_i := unsigned(B); 103 | end if; 104 | Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); 105 | Carry <= Res_i(A'length + 1); 106 | Res <= std_logic_vector(Res_i(A'length downto 1)); 107 | end; 108 | 109 | -- AddSub variables (temporary signals) 110 | signal UseCarry : std_logic; 111 | signal Carry7_v : std_logic; 112 | signal Overflow_v : std_logic; 113 | signal HalfCarry_v : std_logic; 114 | signal Carry_v : std_logic; 115 | signal Q_v : std_logic_vector(7 downto 0); 116 | 117 | signal BitMask : std_logic_vector(7 downto 0); 118 | 119 | begin 120 | 121 | with IR(5 downto 3) select BitMask <= "00000001" when "000", 122 | "00000010" when "001", 123 | "00000100" when "010", 124 | "00001000" when "011", 125 | "00010000" when "100", 126 | "00100000" when "101", 127 | "01000000" when "110", 128 | "10000000" when others; 129 | 130 | UseCarry <= not ALU_Op(2) and ALU_Op(0); 131 | AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); 132 | AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); 133 | AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); 134 | OverFlow_v <= Carry_v xor Carry7_v; 135 | 136 | process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) 137 | variable Q_t : std_logic_vector(7 downto 0); 138 | variable DAA_Q : unsigned(8 downto 0); 139 | begin 140 | Q_t := "--------"; 141 | F_Out <= F_In; 142 | DAA_Q := "---------"; 143 | case ALU_Op is 144 | when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => 145 | F_Out(Flag_N) <= '0'; 146 | F_Out(Flag_C) <= '0'; 147 | case ALU_OP(2 downto 0) is 148 | when "000" | "001" => -- ADD, ADC 149 | Q_t := Q_v; 150 | F_Out(Flag_C) <= Carry_v; 151 | F_Out(Flag_H) <= HalfCarry_v; 152 | F_Out(Flag_P) <= OverFlow_v; 153 | when "010" | "011" | "111" => -- SUB, SBC, CP 154 | Q_t := Q_v; 155 | F_Out(Flag_N) <= '1'; 156 | F_Out(Flag_C) <= not Carry_v; 157 | F_Out(Flag_H) <= not HalfCarry_v; 158 | F_Out(Flag_P) <= OverFlow_v; 159 | when "100" => -- AND 160 | Q_t(7 downto 0) := BusA and BusB; 161 | F_Out(Flag_H) <= '1'; 162 | when "101" => -- XOR 163 | Q_t(7 downto 0) := BusA xor BusB; 164 | F_Out(Flag_H) <= '0'; 165 | when others => -- OR "110" 166 | Q_t(7 downto 0) := BusA or BusB; 167 | F_Out(Flag_H) <= '0'; 168 | end case; 169 | if ALU_Op(2 downto 0) = "111" then -- CP 170 | F_Out(Flag_X) <= BusB(3); 171 | F_Out(Flag_Y) <= BusB(5); 172 | else 173 | F_Out(Flag_X) <= Q_t(3); 174 | F_Out(Flag_Y) <= Q_t(5); 175 | end if; 176 | if Q_t(7 downto 0) = "00000000" then 177 | F_Out(Flag_Z) <= '1'; 178 | if Z16 = '1' then 179 | F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC 180 | end if; 181 | else 182 | F_Out(Flag_Z) <= '0'; 183 | end if; 184 | F_Out(Flag_S) <= Q_t(7); 185 | case ALU_Op(2 downto 0) is 186 | when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP 187 | when others => 188 | F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor 189 | Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); 190 | end case; 191 | if Arith16 = '1' then 192 | F_Out(Flag_S) <= F_In(Flag_S); 193 | F_Out(Flag_Z) <= F_In(Flag_Z); 194 | F_Out(Flag_P) <= F_In(Flag_P); 195 | end if; 196 | when "1100" => 197 | -- DAA 198 | F_Out(Flag_H) <= F_In(Flag_H); 199 | F_Out(Flag_C) <= F_In(Flag_C); 200 | DAA_Q(7 downto 0) := unsigned(BusA); 201 | DAA_Q(8) := '0'; 202 | if F_In(Flag_N) = '0' then 203 | -- After addition 204 | -- Alow > 9 or H = 1 205 | if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then 206 | if (DAA_Q(3 downto 0) > 9) then 207 | F_Out(Flag_H) <= '1'; 208 | else 209 | F_Out(Flag_H) <= '0'; 210 | end if; 211 | DAA_Q := DAA_Q + 6; 212 | end if; 213 | -- new Ahigh > 9 or C = 1 214 | if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then 215 | DAA_Q := DAA_Q + 96; -- 0x60 216 | end if; 217 | else 218 | -- After subtraction 219 | if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then 220 | if DAA_Q(3 downto 0) > 5 then 221 | F_Out(Flag_H) <= '0'; 222 | end if; 223 | DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; 224 | end if; 225 | if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then 226 | DAA_Q := DAA_Q - 352; -- 0x160 227 | end if; 228 | end if; 229 | F_Out(Flag_X) <= DAA_Q(3); 230 | F_Out(Flag_Y) <= DAA_Q(5); 231 | F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); 232 | Q_t := std_logic_vector(DAA_Q(7 downto 0)); 233 | if DAA_Q(7 downto 0) = "00000000" then 234 | F_Out(Flag_Z) <= '1'; 235 | else 236 | F_Out(Flag_Z) <= '0'; 237 | end if; 238 | F_Out(Flag_S) <= DAA_Q(7); 239 | F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor 240 | DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); 241 | when "1101" | "1110" => 242 | -- RLD, RRD 243 | Q_t(7 downto 4) := BusA(7 downto 4); 244 | if ALU_Op(0) = '1' then 245 | Q_t(3 downto 0) := BusB(7 downto 4); 246 | else 247 | Q_t(3 downto 0) := BusB(3 downto 0); 248 | end if; 249 | F_Out(Flag_H) <= '0'; 250 | F_Out(Flag_N) <= '0'; 251 | F_Out(Flag_X) <= Q_t(3); 252 | F_Out(Flag_Y) <= Q_t(5); 253 | if Q_t(7 downto 0) = "00000000" then 254 | F_Out(Flag_Z) <= '1'; 255 | else 256 | F_Out(Flag_Z) <= '0'; 257 | end if; 258 | F_Out(Flag_S) <= Q_t(7); 259 | F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor 260 | Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); 261 | when "1001" => 262 | -- BIT 263 | Q_t(7 downto 0) := BusB and BitMask; 264 | F_Out(Flag_S) <= Q_t(7); 265 | if Q_t(7 downto 0) = "00000000" then 266 | F_Out(Flag_Z) <= '1'; 267 | F_Out(Flag_P) <= '1'; 268 | else 269 | F_Out(Flag_Z) <= '0'; 270 | F_Out(Flag_P) <= '0'; 271 | end if; 272 | F_Out(Flag_H) <= '1'; 273 | F_Out(Flag_N) <= '0'; 274 | F_Out(Flag_X) <= '0'; 275 | F_Out(Flag_Y) <= '0'; 276 | if IR(2 downto 0) /= "110" then 277 | F_Out(Flag_X) <= BusB(3); 278 | F_Out(Flag_Y) <= BusB(5); 279 | end if; 280 | when "1010" => 281 | -- SET 282 | Q_t(7 downto 0) := BusB or BitMask; 283 | when "1011" => 284 | -- RES 285 | Q_t(7 downto 0) := BusB and not BitMask; 286 | when "1000" => 287 | -- ROT 288 | case IR(5 downto 3) is 289 | when "000" => -- RLC 290 | Q_t(7 downto 1) := BusA(6 downto 0); 291 | Q_t(0) := BusA(7); 292 | F_Out(Flag_C) <= BusA(7); 293 | when "010" => -- RL 294 | Q_t(7 downto 1) := BusA(6 downto 0); 295 | Q_t(0) := F_In(Flag_C); 296 | F_Out(Flag_C) <= BusA(7); 297 | when "001" => -- RRC 298 | Q_t(6 downto 0) := BusA(7 downto 1); 299 | Q_t(7) := BusA(0); 300 | F_Out(Flag_C) <= BusA(0); 301 | when "011" => -- RR 302 | Q_t(6 downto 0) := BusA(7 downto 1); 303 | Q_t(7) := F_In(Flag_C); 304 | F_Out(Flag_C) <= BusA(0); 305 | when "100" => -- SLA 306 | Q_t(7 downto 1) := BusA(6 downto 0); 307 | Q_t(0) := '0'; 308 | F_Out(Flag_C) <= BusA(7); 309 | when "110" => -- SLL (Undocumented) / SWAP 310 | if Mode = 3 then 311 | Q_t(7 downto 4) := BusA(3 downto 0); 312 | Q_t(3 downto 0) := BusA(7 downto 4); 313 | F_Out(Flag_C) <= '0'; 314 | else 315 | Q_t(7 downto 1) := BusA(6 downto 0); 316 | Q_t(0) := '1'; 317 | F_Out(Flag_C) <= BusA(7); 318 | end if; 319 | when "101" => -- SRA 320 | Q_t(6 downto 0) := BusA(7 downto 1); 321 | Q_t(7) := BusA(7); 322 | F_Out(Flag_C) <= BusA(0); 323 | when others => -- SRL 324 | Q_t(6 downto 0) := BusA(7 downto 1); 325 | Q_t(7) := '0'; 326 | F_Out(Flag_C) <= BusA(0); 327 | end case; 328 | F_Out(Flag_H) <= '0'; 329 | F_Out(Flag_N) <= '0'; 330 | F_Out(Flag_X) <= Q_t(3); 331 | F_Out(Flag_Y) <= Q_t(5); 332 | F_Out(Flag_S) <= Q_t(7); 333 | if Q_t(7 downto 0) = "00000000" then 334 | F_Out(Flag_Z) <= '1'; 335 | else 336 | F_Out(Flag_Z) <= '0'; 337 | end if; 338 | F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor 339 | Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); 340 | if ISet = "00" then 341 | F_Out(Flag_P) <= F_In(Flag_P); 342 | F_Out(Flag_S) <= F_In(Flag_S); 343 | F_Out(Flag_Z) <= F_In(Flag_Z); 344 | end if; 345 | when others => 346 | null; 347 | end case; 348 | Q <= Q_t; 349 | end process; 350 | 351 | end; 352 | -------------------------------------------------------------------------------- /components/T80_Pack.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Z80 compatible microprocessor core 3 | -- 4 | -- Version : 0242 5 | -- 6 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 7 | -- 8 | -- All rights reserved 9 | -- 10 | -- Redistribution and use in source and synthezised forms, with or without 11 | -- modification, are permitted provided that the following conditions are met: 12 | -- 13 | -- Redistributions of source code must retain the above copyright notice, 14 | -- this list of conditions and the following disclaimer. 15 | -- 16 | -- Redistributions in synthesized form must reproduce the above copyright 17 | -- notice, this list of conditions and the following disclaimer in the 18 | -- documentation and/or other materials provided with the distribution. 19 | -- 20 | -- Neither the name of the author nor the names of other contributors may 21 | -- be used to endorse or promote products derived from this software without 22 | -- specific prior written permission. 23 | -- 24 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 28 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 | -- POSSIBILITY OF SUCH DAMAGE. 35 | -- 36 | -- Please report bugs to the author, but before you do so, please 37 | -- make sure that this is not a derivative work and that 38 | -- you have the latest version of this file. 39 | -- 40 | -- The latest version of this file can be found at: 41 | -- http://www.opencores.org/cvsweb.shtml/t80/ 42 | -- 43 | -- Limitations : 44 | -- 45 | -- File history : 46 | -- 47 | 48 | library IEEE; 49 | use IEEE.std_logic_1164.all; 50 | 51 | package T80_Pack is 52 | 53 | component T80 54 | generic( 55 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 56 | IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle 57 | Flag_C : integer := 0; 58 | Flag_N : integer := 1; 59 | Flag_P : integer := 2; 60 | Flag_X : integer := 3; 61 | Flag_H : integer := 4; 62 | Flag_Y : integer := 5; 63 | Flag_Z : integer := 6; 64 | Flag_S : integer := 7 65 | ); 66 | port( 67 | RESET_n : in std_logic; 68 | CLK_n : in std_logic; 69 | CEN : in std_logic; 70 | WAIT_n : in std_logic; 71 | INT_n : in std_logic; 72 | NMI_n : in std_logic; 73 | BUSRQ_n : in std_logic; 74 | M1_n : out std_logic; 75 | IORQ : out std_logic; 76 | NoRead : out std_logic; 77 | Write : out std_logic; 78 | RFSH_n : out std_logic; 79 | HALT_n : out std_logic; 80 | BUSAK_n : out std_logic; 81 | A : out std_logic_vector(15 downto 0); 82 | DInst : in std_logic_vector(7 downto 0); 83 | DI : in std_logic_vector(7 downto 0); 84 | DO : out std_logic_vector(7 downto 0); 85 | MC : out std_logic_vector(2 downto 0); 86 | TS : out std_logic_vector(2 downto 0); 87 | IntCycle_n : out std_logic; 88 | IntE : out std_logic; 89 | Stop : out std_logic 90 | ); 91 | end component; 92 | 93 | component T80_Reg 94 | port( 95 | Clk : in std_logic; 96 | CEN : in std_logic; 97 | WEH : in std_logic; 98 | WEL : in std_logic; 99 | AddrA : in std_logic_vector(2 downto 0); 100 | AddrB : in std_logic_vector(2 downto 0); 101 | AddrC : in std_logic_vector(2 downto 0); 102 | DIH : in std_logic_vector(7 downto 0); 103 | DIL : in std_logic_vector(7 downto 0); 104 | DOAH : out std_logic_vector(7 downto 0); 105 | DOAL : out std_logic_vector(7 downto 0); 106 | DOBH : out std_logic_vector(7 downto 0); 107 | DOBL : out std_logic_vector(7 downto 0); 108 | DOCH : out std_logic_vector(7 downto 0); 109 | DOCL : out std_logic_vector(7 downto 0) 110 | ); 111 | end component; 112 | 113 | component T80_MCode 114 | generic( 115 | Mode : integer := 0; 116 | Flag_C : integer := 0; 117 | Flag_N : integer := 1; 118 | Flag_P : integer := 2; 119 | Flag_X : integer := 3; 120 | Flag_H : integer := 4; 121 | Flag_Y : integer := 5; 122 | Flag_Z : integer := 6; 123 | Flag_S : integer := 7 124 | ); 125 | port( 126 | IR : in std_logic_vector(7 downto 0); 127 | ISet : in std_logic_vector(1 downto 0); 128 | MCycle : in std_logic_vector(2 downto 0); 129 | F : in std_logic_vector(7 downto 0); 130 | NMICycle : in std_logic; 131 | IntCycle : in std_logic; 132 | MCycles : out std_logic_vector(2 downto 0); 133 | TStates : out std_logic_vector(2 downto 0); 134 | Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD 135 | Inc_PC : out std_logic; 136 | Inc_WZ : out std_logic; 137 | IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc 138 | Read_To_Reg : out std_logic; 139 | Read_To_Acc : out std_logic; 140 | Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F 141 | Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 142 | ALU_Op : out std_logic_vector(3 downto 0); 143 | -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None 144 | Save_ALU : out std_logic; 145 | PreserveC : out std_logic; 146 | Arith16 : out std_logic; 147 | Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI 148 | IORQ : out std_logic; 149 | Jump : out std_logic; 150 | JumpE : out std_logic; 151 | JumpXY : out std_logic; 152 | Call : out std_logic; 153 | RstP : out std_logic; 154 | LDZ : out std_logic; 155 | LDW : out std_logic; 156 | LDSPHL : out std_logic; 157 | Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None 158 | ExchangeDH : out std_logic; 159 | ExchangeRp : out std_logic; 160 | ExchangeAF : out std_logic; 161 | ExchangeRS : out std_logic; 162 | I_DJNZ : out std_logic; 163 | I_CPL : out std_logic; 164 | I_CCF : out std_logic; 165 | I_SCF : out std_logic; 166 | I_RETN : out std_logic; 167 | I_BT : out std_logic; 168 | I_BC : out std_logic; 169 | I_BTR : out std_logic; 170 | I_RLD : out std_logic; 171 | I_RRD : out std_logic; 172 | I_INRC : out std_logic; 173 | SetDI : out std_logic; 174 | SetEI : out std_logic; 175 | IMode : out std_logic_vector(1 downto 0); 176 | Halt : out std_logic; 177 | NoRead : out std_logic; 178 | Write : out std_logic 179 | ); 180 | end component; 181 | 182 | component T80_ALU 183 | generic( 184 | Mode : integer := 0; 185 | Flag_C : integer := 0; 186 | Flag_N : integer := 1; 187 | Flag_P : integer := 2; 188 | Flag_X : integer := 3; 189 | Flag_H : integer := 4; 190 | Flag_Y : integer := 5; 191 | Flag_Z : integer := 6; 192 | Flag_S : integer := 7 193 | ); 194 | port( 195 | Arith16 : in std_logic; 196 | Z16 : in std_logic; 197 | ALU_Op : in std_logic_vector(3 downto 0); 198 | IR : in std_logic_vector(5 downto 0); 199 | ISet : in std_logic_vector(1 downto 0); 200 | BusA : in std_logic_vector(7 downto 0); 201 | BusB : in std_logic_vector(7 downto 0); 202 | F_In : in std_logic_vector(7 downto 0); 203 | Q : out std_logic_vector(7 downto 0); 204 | F_Out : out std_logic_vector(7 downto 0) 205 | ); 206 | end component; 207 | 208 | end; 209 | -------------------------------------------------------------------------------- /components/T80_Reg.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- T80 Registers, technology independent 3 | -- 4 | -- Version : 0244 5 | -- 6 | -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) 7 | -- 8 | -- All rights reserved 9 | -- 10 | -- Redistribution and use in source and synthezised forms, with or without 11 | -- modification, are permitted provided that the following conditions are met: 12 | -- 13 | -- Redistributions of source code must retain the above copyright notice, 14 | -- this list of conditions and the following disclaimer. 15 | -- 16 | -- Redistributions in synthesized form must reproduce the above copyright 17 | -- notice, this list of conditions and the following disclaimer in the 18 | -- documentation and/or other materials provided with the distribution. 19 | -- 20 | -- Neither the name of the author nor the names of other contributors may 21 | -- be used to endorse or promote products derived from this software without 22 | -- specific prior written permission. 23 | -- 24 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 28 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 | -- POSSIBILITY OF SUCH DAMAGE. 35 | -- 36 | -- Please report bugs to the author, but before you do so, please 37 | -- make sure that this is not a derivative work and that 38 | -- you have the latest version of this file. 39 | -- 40 | -- The latest version of this file can be found at: 41 | -- http://www.opencores.org/cvsweb.shtml/t51/ 42 | -- 43 | -- Limitations : 44 | -- 45 | -- File history : 46 | -- 47 | -- 0242 : Initial release 48 | -- 49 | -- 0244 : Changed to single register file 50 | -- 51 | 52 | library IEEE; 53 | use IEEE.std_logic_1164.all; 54 | use IEEE.numeric_std.all; 55 | 56 | entity T80_Reg is 57 | port( 58 | Clk : in std_logic; 59 | CEN : in std_logic; 60 | WEH : in std_logic; 61 | WEL : in std_logic; 62 | AddrA : in std_logic_vector(2 downto 0); 63 | AddrB : in std_logic_vector(2 downto 0); 64 | AddrC : in std_logic_vector(2 downto 0); 65 | DIH : in std_logic_vector(7 downto 0); 66 | DIL : in std_logic_vector(7 downto 0); 67 | DOAH : out std_logic_vector(7 downto 0); 68 | DOAL : out std_logic_vector(7 downto 0); 69 | DOBH : out std_logic_vector(7 downto 0); 70 | DOBL : out std_logic_vector(7 downto 0); 71 | DOCH : out std_logic_vector(7 downto 0); 72 | DOCL : out std_logic_vector(7 downto 0) 73 | ); 74 | end T80_Reg; 75 | 76 | architecture rtl of T80_Reg is 77 | 78 | type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); 79 | signal RegsH : Register_Image(0 to 7); 80 | signal RegsL : Register_Image(0 to 7); 81 | 82 | begin 83 | 84 | process (Clk) 85 | begin 86 | if Clk'event and Clk = '1' then 87 | if CEN = '1' then 88 | if WEH = '1' then 89 | RegsH(to_integer(unsigned(AddrA))) <= DIH; 90 | end if; 91 | if WEL = '1' then 92 | RegsL(to_integer(unsigned(AddrA))) <= DIL; 93 | end if; 94 | end if; 95 | end if; 96 | end process; 97 | 98 | DOAH <= RegsH(to_integer(unsigned(AddrA))); 99 | DOAL <= RegsL(to_integer(unsigned(AddrA))); 100 | DOBH <= RegsH(to_integer(unsigned(AddrB))); 101 | DOBL <= RegsL(to_integer(unsigned(AddrB))); 102 | DOCH <= RegsH(to_integer(unsigned(AddrC))); 103 | DOCL <= RegsL(to_integer(unsigned(AddrC))); 104 | 105 | end; 106 | -------------------------------------------------------------------------------- /components/T80_RegX.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- T80 Registers for Xilinx Select RAM 3 | -- 4 | -- Version : 0244 5 | -- 6 | -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) 7 | -- 8 | -- All rights reserved 9 | -- 10 | -- Redistribution and use in source and synthezised forms, with or without 11 | -- modification, are permitted provided that the following conditions are met: 12 | -- 13 | -- Redistributions of source code must retain the above copyright notice, 14 | -- this list of conditions and the following disclaimer. 15 | -- 16 | -- Redistributions in synthesized form must reproduce the above copyright 17 | -- notice, this list of conditions and the following disclaimer in the 18 | -- documentation and/or other materials provided with the distribution. 19 | -- 20 | -- Neither the name of the author nor the names of other contributors may 21 | -- be used to endorse or promote products derived from this software without 22 | -- specific prior written permission. 23 | -- 24 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 28 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 | -- POSSIBILITY OF SUCH DAMAGE. 35 | -- 36 | -- Please report bugs to the author, but before you do so, please 37 | -- make sure that this is not a derivative work and that 38 | -- you have the latest version of this file. 39 | -- 40 | -- The latest version of this file can be found at: 41 | -- http://www.opencores.org/cvsweb.shtml/t51/ 42 | -- 43 | -- Limitations : 44 | -- 45 | -- File history : 46 | -- 47 | -- 0242 : Initial release 48 | -- 49 | -- 0244 : Removed UNISIM library and added componet declaration 50 | -- 51 | 52 | library IEEE; 53 | use IEEE.std_logic_1164.all; 54 | use IEEE.numeric_std.all; 55 | 56 | entity T80_Reg is 57 | port( 58 | Clk : in std_logic; 59 | CEN : in std_logic; 60 | WEH : in std_logic; 61 | WEL : in std_logic; 62 | AddrA : in std_logic_vector(2 downto 0); 63 | AddrB : in std_logic_vector(2 downto 0); 64 | AddrC : in std_logic_vector(2 downto 0); 65 | DIH : in std_logic_vector(7 downto 0); 66 | DIL : in std_logic_vector(7 downto 0); 67 | DOAH : out std_logic_vector(7 downto 0); 68 | DOAL : out std_logic_vector(7 downto 0); 69 | DOBH : out std_logic_vector(7 downto 0); 70 | DOBL : out std_logic_vector(7 downto 0); 71 | DOCH : out std_logic_vector(7 downto 0); 72 | DOCL : out std_logic_vector(7 downto 0) 73 | ); 74 | end T80_Reg; 75 | 76 | architecture rtl of T80_Reg is 77 | 78 | component RAM16X1D 79 | port( 80 | DPO : out std_ulogic; 81 | SPO : out std_ulogic; 82 | A0 : in std_ulogic; 83 | A1 : in std_ulogic; 84 | A2 : in std_ulogic; 85 | A3 : in std_ulogic; 86 | D : in std_ulogic; 87 | DPRA0 : in std_ulogic; 88 | DPRA1 : in std_ulogic; 89 | DPRA2 : in std_ulogic; 90 | DPRA3 : in std_ulogic; 91 | WCLK : in std_ulogic; 92 | WE : in std_ulogic); 93 | end component; 94 | 95 | signal ENH : std_logic; 96 | signal ENL : std_logic; 97 | 98 | begin 99 | 100 | ENH <= CEN and WEH; 101 | ENL <= CEN and WEL; 102 | 103 | bG1: for I in 0 to 7 generate 104 | begin 105 | Reg1H : RAM16X1D 106 | port map( 107 | DPO => DOBH(i), 108 | SPO => DOAH(i), 109 | A0 => AddrA(0), 110 | A1 => AddrA(1), 111 | A2 => AddrA(2), 112 | A3 => '0', 113 | D => DIH(i), 114 | DPRA0 => AddrB(0), 115 | DPRA1 => AddrB(1), 116 | DPRA2 => AddrB(2), 117 | DPRA3 => '0', 118 | WCLK => Clk, 119 | WE => ENH); 120 | Reg1L : RAM16X1D 121 | port map( 122 | DPO => DOBL(i), 123 | SPO => DOAL(i), 124 | A0 => AddrA(0), 125 | A1 => AddrA(1), 126 | A2 => AddrA(2), 127 | A3 => '0', 128 | D => DIL(i), 129 | DPRA0 => AddrB(0), 130 | DPRA1 => AddrB(1), 131 | DPRA2 => AddrB(2), 132 | DPRA3 => '0', 133 | WCLK => Clk, 134 | WE => ENL); 135 | Reg2H : RAM16X1D 136 | port map( 137 | DPO => DOCH(i), 138 | SPO => open, 139 | A0 => AddrA(0), 140 | A1 => AddrA(1), 141 | A2 => AddrA(2), 142 | A3 => '0', 143 | D => DIH(i), 144 | DPRA0 => AddrC(0), 145 | DPRA1 => AddrC(1), 146 | DPRA2 => AddrC(2), 147 | DPRA3 => '0', 148 | WCLK => Clk, 149 | WE => ENH); 150 | Reg2L : RAM16X1D 151 | port map( 152 | DPO => DOCL(i), 153 | SPO => open, 154 | A0 => AddrA(0), 155 | A1 => AddrA(1), 156 | A2 => AddrA(2), 157 | A3 => '0', 158 | D => DIL(i), 159 | DPRA0 => AddrC(0), 160 | DPRA1 => AddrC(1), 161 | DPRA2 => AddrC(2), 162 | DPRA3 => '0', 163 | WCLK => Clk, 164 | WE => ENL); 165 | end generate; 166 | 167 | end; 168 | -------------------------------------------------------------------------------- /components/T80a.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Z80 compatible microprocessor core, asynchronous top level 3 | -- 4 | -- Version : 0247 5 | -- 6 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 7 | -- 8 | -- All rights reserved 9 | -- 10 | -- Redistribution and use in source and synthezised forms, with or without 11 | -- modification, are permitted provided that the following conditions are met: 12 | -- 13 | -- Redistributions of source code must retain the above copyright notice, 14 | -- this list of conditions and the following disclaimer. 15 | -- 16 | -- Redistributions in synthesized form must reproduce the above copyright 17 | -- notice, this list of conditions and the following disclaimer in the 18 | -- documentation and/or other materials provided with the distribution. 19 | -- 20 | -- Neither the name of the author nor the names of other contributors may 21 | -- be used to endorse or promote products derived from this software without 22 | -- specific prior written permission. 23 | -- 24 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 28 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 | -- POSSIBILITY OF SUCH DAMAGE. 35 | -- 36 | -- Please report bugs to the author, but before you do so, please 37 | -- make sure that this is not a derivative work and that 38 | -- you have the latest version of this file. 39 | -- 40 | -- The latest version of this file can be found at: 41 | -- http://www.opencores.org/cvsweb.shtml/t80/ 42 | -- 43 | -- Limitations : 44 | -- 45 | -- File history : 46 | -- 47 | -- 0208 : First complete release 48 | -- 49 | -- 0211 : Fixed interrupt cycle 50 | -- 51 | -- 0235 : Updated for T80 interface change 52 | -- 53 | -- 0238 : Updated for T80 interface change 54 | -- 55 | -- 0240 : Updated for T80 interface change 56 | -- 57 | -- 0242 : Updated for T80 interface change 58 | -- 59 | -- 0247 : Fixed bus req/ack cycle 60 | -- 61 | 62 | library IEEE; 63 | use IEEE.std_logic_1164.all; 64 | use IEEE.numeric_std.all; 65 | use work.T80_Pack.all; 66 | 67 | entity T80a is 68 | generic( 69 | Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 70 | ); 71 | port( 72 | RESET_n : in std_logic; 73 | CLK_n : in std_logic; 74 | WAIT_n : in std_logic; 75 | INT_n : in std_logic; 76 | NMI_n : in std_logic; 77 | BUSRQ_n : in std_logic; 78 | M1_n : out std_logic; 79 | MREQ_n : out std_logic; 80 | IORQ_n : out std_logic; 81 | RD_n : out std_logic; 82 | WR_n : out std_logic; 83 | RFSH_n : out std_logic; 84 | HALT_n : out std_logic; 85 | BUSAK_n : out std_logic; 86 | A : out std_logic_vector(15 downto 0); 87 | D : inout std_logic_vector(7 downto 0) 88 | ); 89 | end T80a; 90 | 91 | architecture rtl of T80a is 92 | 93 | signal CEN : std_logic; 94 | signal Reset_s : std_logic; 95 | signal IntCycle_n : std_logic; 96 | signal IORQ : std_logic; 97 | signal NoRead : std_logic; 98 | signal Write : std_logic; 99 | signal MREQ : std_logic; 100 | signal MReq_Inhibit : std_logic; 101 | signal Req_Inhibit : std_logic; 102 | signal RD : std_logic; 103 | signal MREQ_n_i : std_logic; 104 | signal IORQ_n_i : std_logic; 105 | signal RD_n_i : std_logic; 106 | signal WR_n_i : std_logic; 107 | signal RFSH_n_i : std_logic; 108 | signal BUSAK_n_i : std_logic; 109 | signal A_i : std_logic_vector(15 downto 0); 110 | signal DO : std_logic_vector(7 downto 0); 111 | signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser 112 | signal Wait_s : std_logic; 113 | signal MCycle : std_logic_vector(2 downto 0); 114 | signal TState : std_logic_vector(2 downto 0); 115 | 116 | begin 117 | 118 | CEN <= '1'; 119 | 120 | BUSAK_n <= BUSAK_n_i; 121 | MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); 122 | RD_n_i <= not RD or Req_Inhibit; 123 | 124 | MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; 125 | IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; 126 | RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; 127 | WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; 128 | RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; 129 | A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); 130 | D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); 131 | 132 | process (RESET_n, CLK_n) 133 | begin 134 | if RESET_n = '0' then 135 | Reset_s <= '0'; 136 | elsif CLK_n'event and CLK_n = '1' then 137 | Reset_s <= '1'; 138 | end if; 139 | end process; 140 | 141 | u0 : T80 142 | generic map( 143 | Mode => Mode, 144 | IOWait => 1) 145 | port map( 146 | CEN => CEN, 147 | M1_n => M1_n, 148 | IORQ => IORQ, 149 | NoRead => NoRead, 150 | Write => Write, 151 | RFSH_n => RFSH_n_i, 152 | HALT_n => HALT_n, 153 | WAIT_n => Wait_s, 154 | INT_n => INT_n, 155 | NMI_n => NMI_n, 156 | RESET_n => Reset_s, 157 | BUSRQ_n => BUSRQ_n, 158 | BUSAK_n => BUSAK_n_i, 159 | CLK_n => CLK_n, 160 | A => A_i, 161 | DInst => D, 162 | DI => DI_Reg, 163 | DO => DO, 164 | MC => MCycle, 165 | TS => TState, 166 | IntCycle_n => IntCycle_n); 167 | 168 | process (CLK_n) 169 | begin 170 | if CLK_n'event and CLK_n = '0' then 171 | Wait_s <= WAIT_n; 172 | if TState = "011" and BUSAK_n_i = '1' then 173 | DI_Reg <= to_x01(D); 174 | end if; 175 | end if; 176 | end process; 177 | 178 | process (Reset_s,CLK_n) 179 | begin 180 | if Reset_s = '0' then 181 | WR_n_i <= '1'; 182 | elsif CLK_n'event and CLK_n = '1' then 183 | WR_n_i <= '1'; 184 | if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! 185 | WR_n_i <= not Write; 186 | end if; 187 | end if; 188 | end process; 189 | 190 | process (Reset_s,CLK_n) 191 | begin 192 | if Reset_s = '0' then 193 | Req_Inhibit <= '0'; 194 | elsif CLK_n'event and CLK_n = '1' then 195 | if MCycle = "001" and TState = "010" then 196 | Req_Inhibit <= '1'; 197 | else 198 | Req_Inhibit <= '0'; 199 | end if; 200 | end if; 201 | end process; 202 | 203 | process (Reset_s,CLK_n) 204 | begin 205 | if Reset_s = '0' then 206 | MReq_Inhibit <= '0'; 207 | elsif CLK_n'event and CLK_n = '0' then 208 | if MCycle = "001" and TState = "010" then 209 | MReq_Inhibit <= '1'; 210 | else 211 | MReq_Inhibit <= '0'; 212 | end if; 213 | end if; 214 | end process; 215 | 216 | process(Reset_s,CLK_n) 217 | begin 218 | if Reset_s = '0' then 219 | RD <= '0'; 220 | IORQ_n_i <= '1'; 221 | MREQ <= '0'; 222 | elsif CLK_n'event and CLK_n = '0' then 223 | 224 | if MCycle = "001" then 225 | if TState = "001" then 226 | RD <= IntCycle_n; 227 | MREQ <= IntCycle_n; 228 | IORQ_n_i <= IntCycle_n; 229 | end if; 230 | if TState = "011" then 231 | RD <= '0'; 232 | IORQ_n_i <= '1'; 233 | MREQ <= '1'; 234 | end if; 235 | if TState = "100" then 236 | MREQ <= '0'; 237 | end if; 238 | else 239 | if TState = "001" and NoRead = '0' then 240 | RD <= not Write; 241 | IORQ_n_i <= not IORQ; 242 | MREQ <= not IORQ; 243 | end if; 244 | if TState = "011" then 245 | RD <= '0'; 246 | IORQ_n_i <= '1'; 247 | MREQ <= '0'; 248 | end if; 249 | end if; 250 | end if; 251 | end process; 252 | 253 | end; 254 | -------------------------------------------------------------------------------- /components/T80s.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Z80 compatible microprocessor core, synchronous top level 3 | -- Different timing than the original z80 4 | -- Inputs needs to be synchronous and outputs may glitch 5 | -- 6 | -- Version : 0242 7 | -- 8 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t80/ 44 | -- 45 | -- Limitations : 46 | -- 47 | -- File history : 48 | -- 49 | -- 0208 : First complete release 50 | -- 51 | -- 0210 : Fixed read with wait 52 | -- 53 | -- 0211 : Fixed interrupt cycle 54 | -- 55 | -- 0235 : Updated for T80 interface change 56 | -- 57 | -- 0236 : Added T2Write generic 58 | -- 59 | -- 0237 : Fixed T2Write with wait state 60 | -- 61 | -- 0238 : Updated for T80 interface change 62 | -- 63 | -- 0240 : Updated for T80 interface change 64 | -- 65 | -- 0242 : Updated for T80 interface change 66 | -- 67 | 68 | library IEEE; 69 | use IEEE.std_logic_1164.all; 70 | use IEEE.numeric_std.all; 71 | use work.T80_Pack.all; 72 | 73 | entity T80s is 74 | generic( 75 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 76 | T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 77 | IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle 78 | ); 79 | port( 80 | RESET_n : in std_logic; 81 | CLK_n : in std_logic; 82 | WAIT_n : in std_logic; 83 | INT_n : in std_logic; 84 | NMI_n : in std_logic; 85 | BUSRQ_n : in std_logic; 86 | M1_n : out std_logic; 87 | MREQ_n : out std_logic; 88 | IORQ_n : out std_logic; 89 | RD_n : out std_logic; 90 | WR_n : out std_logic; 91 | RFSH_n : out std_logic; 92 | HALT_n : out std_logic; 93 | BUSAK_n : out std_logic; 94 | A : out std_logic_vector(15 downto 0); 95 | DI : in std_logic_vector(7 downto 0); 96 | DO : out std_logic_vector(7 downto 0) 97 | ); 98 | end T80s; 99 | 100 | architecture rtl of T80s is 101 | 102 | signal CEN : std_logic; 103 | signal IntCycle_n : std_logic; 104 | signal NoRead : std_logic; 105 | signal Write : std_logic; 106 | signal IORQ : std_logic; 107 | signal DI_Reg : std_logic_vector(7 downto 0); 108 | signal MCycle : std_logic_vector(2 downto 0); 109 | signal TState : std_logic_vector(2 downto 0); 110 | 111 | begin 112 | 113 | CEN <= '1'; 114 | 115 | u0 : T80 116 | generic map( 117 | Mode => Mode, 118 | IOWait => IOWait) 119 | port map( 120 | CEN => CEN, 121 | M1_n => M1_n, 122 | IORQ => IORQ, 123 | NoRead => NoRead, 124 | Write => Write, 125 | RFSH_n => RFSH_n, 126 | HALT_n => HALT_n, 127 | WAIT_n => Wait_n, 128 | INT_n => INT_n, 129 | NMI_n => NMI_n, 130 | RESET_n => RESET_n, 131 | BUSRQ_n => BUSRQ_n, 132 | BUSAK_n => BUSAK_n, 133 | CLK_n => CLK_n, 134 | A => A, 135 | DInst => DI, 136 | DI => DI_Reg, 137 | DO => DO, 138 | MC => MCycle, 139 | TS => TState, 140 | IntCycle_n => IntCycle_n); 141 | 142 | process (RESET_n, CLK_n) 143 | begin 144 | if RESET_n = '0' then 145 | RD_n <= '1'; 146 | WR_n <= '1'; 147 | IORQ_n <= '1'; 148 | MREQ_n <= '1'; 149 | DI_Reg <= "00000000"; 150 | elsif CLK_n'event and CLK_n = '1' then 151 | RD_n <= '1'; 152 | WR_n <= '1'; 153 | IORQ_n <= '1'; 154 | MREQ_n <= '1'; 155 | if MCycle = "001" then 156 | if TState = "001" or (TState = "010" and Wait_n = '0') then 157 | RD_n <= not IntCycle_n; 158 | MREQ_n <= not IntCycle_n; 159 | IORQ_n <= IntCycle_n; 160 | end if; 161 | if TState = "011" then 162 | MREQ_n <= '0'; 163 | end if; 164 | else 165 | if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then 166 | RD_n <= '0'; 167 | IORQ_n <= not IORQ; 168 | MREQ_n <= IORQ; 169 | end if; 170 | if T2Write = 0 then 171 | if TState = "010" and Write = '1' then 172 | WR_n <= '0'; 173 | IORQ_n <= not IORQ; 174 | MREQ_n <= IORQ; 175 | end if; 176 | else 177 | if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then 178 | WR_n <= '0'; 179 | IORQ_n <= not IORQ; 180 | MREQ_n <= IORQ; 181 | end if; 182 | end if; 183 | end if; 184 | if TState = "010" and Wait_n = '1' then 185 | DI_Reg <= DI; 186 | end if; 187 | end if; 188 | end process; 189 | 190 | end; 191 | -------------------------------------------------------------------------------- /components/T80se.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Z80 compatible microprocessor core, synchronous top level with clock enable 3 | -- Different timing than the original z80 4 | -- Inputs needs to be synchronous and outputs may glitch 5 | -- 6 | -- Version : 0242 7 | -- 8 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t80/ 44 | -- 45 | -- Limitations : 46 | -- 47 | -- File history : 48 | -- 49 | -- 0235 : First release 50 | -- 51 | -- 0236 : Added T2Write generic 52 | -- 53 | -- 0237 : Fixed T2Write with wait state 54 | -- 55 | -- 0238 : Updated for T80 interface change 56 | -- 57 | -- 0240 : Updated for T80 interface change 58 | -- 59 | -- 0242 : Updated for T80 interface change 60 | -- 61 | 62 | library IEEE; 63 | use IEEE.std_logic_1164.all; 64 | use IEEE.numeric_std.all; 65 | use work.T80_Pack.all; 66 | 67 | entity T80se is 68 | generic( 69 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 70 | T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 71 | IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle 72 | ); 73 | port( 74 | RESET_n : in std_logic; 75 | CLK_n : in std_logic; 76 | CLKEN : in std_logic; 77 | WAIT_n : in std_logic; 78 | INT_n : in std_logic; 79 | NMI_n : in std_logic; 80 | BUSRQ_n : in std_logic; 81 | M1_n : out std_logic; 82 | MREQ_n : out std_logic; 83 | IORQ_n : out std_logic; 84 | RD_n : out std_logic; 85 | WR_n : out std_logic; 86 | RFSH_n : out std_logic; 87 | HALT_n : out std_logic; 88 | BUSAK_n : out std_logic; 89 | A : out std_logic_vector(15 downto 0); 90 | DI : in std_logic_vector(7 downto 0); 91 | DO : out std_logic_vector(7 downto 0) 92 | ); 93 | end T80se; 94 | 95 | architecture rtl of T80se is 96 | 97 | signal IntCycle_n : std_logic; 98 | signal NoRead : std_logic; 99 | signal Write : std_logic; 100 | signal IORQ : std_logic; 101 | signal DI_Reg : std_logic_vector(7 downto 0); 102 | signal MCycle : std_logic_vector(2 downto 0); 103 | signal TState : std_logic_vector(2 downto 0); 104 | 105 | begin 106 | 107 | u0 : T80 108 | generic map( 109 | Mode => Mode, 110 | IOWait => IOWait) 111 | port map( 112 | CEN => CLKEN, 113 | M1_n => M1_n, 114 | IORQ => IORQ, 115 | NoRead => NoRead, 116 | Write => Write, 117 | RFSH_n => RFSH_n, 118 | HALT_n => HALT_n, 119 | WAIT_n => Wait_n, 120 | INT_n => INT_n, 121 | NMI_n => NMI_n, 122 | RESET_n => RESET_n, 123 | BUSRQ_n => BUSRQ_n, 124 | BUSAK_n => BUSAK_n, 125 | CLK_n => CLK_n, 126 | A => A, 127 | DInst => DI, 128 | DI => DI_Reg, 129 | DO => DO, 130 | MC => MCycle, 131 | TS => TState, 132 | IntCycle_n => IntCycle_n); 133 | 134 | process (RESET_n, CLK_n) 135 | begin 136 | if RESET_n = '0' then 137 | RD_n <= '1'; 138 | WR_n <= '1'; 139 | IORQ_n <= '1'; 140 | MREQ_n <= '1'; 141 | DI_Reg <= "00000000"; 142 | elsif CLK_n'event and CLK_n = '1' then 143 | if CLKEN = '1' then 144 | RD_n <= '1'; 145 | WR_n <= '1'; 146 | IORQ_n <= '1'; 147 | MREQ_n <= '1'; 148 | if MCycle = "001" then 149 | if TState = "001" or (TState = "010" and Wait_n = '0') then 150 | RD_n <= not IntCycle_n; 151 | MREQ_n <= not IntCycle_n; 152 | IORQ_n <= IntCycle_n; 153 | end if; 154 | if TState = "011" then 155 | MREQ_n <= '0'; 156 | end if; 157 | else 158 | if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then 159 | RD_n <= '0'; 160 | IORQ_n <= not IORQ; 161 | MREQ_n <= IORQ; 162 | end if; 163 | if T2Write = 0 then 164 | if TState = "010" and Write = '1' then 165 | WR_n <= '0'; 166 | IORQ_n <= not IORQ; 167 | MREQ_n <= IORQ; 168 | end if; 169 | else 170 | if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then 171 | WR_n <= '0'; 172 | IORQ_n <= not IORQ; 173 | MREQ_n <= IORQ; 174 | end if; 175 | end if; 176 | end if; 177 | if TState = "010" and Wait_n = '1' then 178 | DI_Reg <= DI; 179 | end if; 180 | end if; 181 | end if; 182 | end process; 183 | 184 | end; 185 | -------------------------------------------------------------------------------- /constants.vhd: -------------------------------------------------------------------------------- 1 | 2 | constant BITS_PER_COLOUR : integer := 2; 3 | constant CHAR_PER_LINE : integer := 80; 4 | constant LINES_PER_SCREEN : integer := 25; 5 | 6 | -------------------------------------------------------------------------------- /debounce.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- FileName: debounce.vhd 4 | -- Dependencies: none 5 | -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version 6 | -- 7 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 8 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 9 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 10 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 11 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 12 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 13 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 14 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 15 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 16 | -- 17 | -- Version History 18 | -- Version 1.0 3/26/2012 Scott Larson 19 | -- Initial Public Release 20 | -- 21 | -------------------------------------------------------------------------------- 22 | 23 | LIBRARY ieee; 24 | USE ieee.std_logic_1164.all; 25 | USE ieee.std_logic_unsigned.all; 26 | 27 | ENTITY debounce IS 28 | GENERIC( 29 | counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) 30 | PORT( 31 | clk : IN STD_LOGIC; --input clock 32 | button : IN STD_LOGIC; --input signal to be debounced 33 | result : OUT STD_LOGIC); --debounced signal 34 | END debounce; 35 | 36 | ARCHITECTURE logic OF debounce IS 37 | SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops 38 | SIGNAL counter_set : STD_LOGIC; --sync reset to zero 39 | SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output 40 | BEGIN 41 | 42 | counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter 43 | 44 | PROCESS(clk) 45 | BEGIN 46 | IF(clk'EVENT and clk = '1') THEN 47 | flipflops(0) <= button; 48 | flipflops(1) <= flipflops(0); 49 | If(counter_set = '1') THEN --reset counter because input is changing 50 | counter_out <= (OTHERS => '0'); 51 | ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met 52 | counter_out <= counter_out + 1; 53 | ELSE --stable input time is met 54 | result <= flipflops(1); 55 | END IF; 56 | END IF; 57 | END PROCESS; 58 | END logic; 59 | -------------------------------------------------------------------------------- /displayram.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2013 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component displayram 17 | PORT 18 | ( 19 | address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 20 | address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 21 | clock_a : IN STD_LOGIC := '1'; 22 | clock_b : IN STD_LOGIC ; 23 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 24 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 25 | enable_a : IN STD_LOGIC := '1'; 26 | enable_b : IN STD_LOGIC := '1'; 27 | wren_a : IN STD_LOGIC := '0'; 28 | wren_b : IN STD_LOGIC := '0'; 29 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 30 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 31 | ); 32 | end component; 33 | -------------------------------------------------------------------------------- /displayram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "displayram.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "displayram.cmp"] 5 | -------------------------------------------------------------------------------- /displayram.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 2-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: displayram.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2013 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY displayram IS 43 | PORT 44 | ( 45 | address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 46 | address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 47 | clock_a : IN STD_LOGIC := '1'; 48 | clock_b : IN STD_LOGIC ; 49 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 50 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 51 | enable_a : IN STD_LOGIC := '1'; 52 | enable_b : IN STD_LOGIC := '1'; 53 | wren_a : IN STD_LOGIC := '0'; 54 | wren_b : IN STD_LOGIC := '0'; 55 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 56 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 57 | ); 58 | END displayram; 59 | 60 | 61 | ARCHITECTURE SYN OF displayram IS 62 | 63 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 64 | SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); 65 | 66 | 67 | 68 | COMPONENT altsyncram 69 | GENERIC ( 70 | address_reg_b : STRING; 71 | clock_enable_input_a : STRING; 72 | clock_enable_input_b : STRING; 73 | clock_enable_output_a : STRING; 74 | clock_enable_output_b : STRING; 75 | indata_reg_b : STRING; 76 | init_file : STRING; 77 | init_file_layout : STRING; 78 | intended_device_family : STRING; 79 | lpm_type : STRING; 80 | numwords_a : NATURAL; 81 | numwords_b : NATURAL; 82 | operation_mode : STRING; 83 | outdata_aclr_a : STRING; 84 | outdata_aclr_b : STRING; 85 | outdata_reg_a : STRING; 86 | outdata_reg_b : STRING; 87 | power_up_uninitialized : STRING; 88 | widthad_a : NATURAL; 89 | widthad_b : NATURAL; 90 | width_a : NATURAL; 91 | width_b : NATURAL; 92 | width_byteena_a : NATURAL; 93 | width_byteena_b : NATURAL; 94 | wrcontrol_wraddress_reg_b : STRING 95 | ); 96 | PORT ( 97 | clock0 : IN STD_LOGIC ; 98 | clocken1 : IN STD_LOGIC ; 99 | wren_a : IN STD_LOGIC ; 100 | address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 101 | clock1 : IN STD_LOGIC ; 102 | clocken0 : IN STD_LOGIC ; 103 | data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 104 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 105 | wren_b : IN STD_LOGIC ; 106 | address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 107 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 108 | q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 109 | ); 110 | END COMPONENT; 111 | 112 | BEGIN 113 | q_a <= sub_wire0(7 DOWNTO 0); 114 | q_b <= sub_wire1(7 DOWNTO 0); 115 | 116 | altsyncram_component : altsyncram 117 | GENERIC MAP ( 118 | address_reg_b => "CLOCK1", 119 | clock_enable_input_a => "NORMAL", 120 | clock_enable_input_b => "NORMAL", 121 | clock_enable_output_a => "BYPASS", 122 | clock_enable_output_b => "BYPASS", 123 | indata_reg_b => "CLOCK1", 124 | init_file => "./charset.hex", 125 | init_file_layout => "PORT_A", 126 | intended_device_family => "Cyclone II", 127 | lpm_type => "altsyncram", 128 | numwords_a => 4096, 129 | numwords_b => 4096, 130 | operation_mode => "BIDIR_DUAL_PORT", 131 | outdata_aclr_a => "NONE", 132 | outdata_aclr_b => "NONE", 133 | outdata_reg_a => "UNREGISTERED", 134 | outdata_reg_b => "UNREGISTERED", 135 | power_up_uninitialized => "FALSE", 136 | widthad_a => 12, 137 | widthad_b => 12, 138 | width_a => 8, 139 | width_b => 8, 140 | width_byteena_a => 1, 141 | width_byteena_b => 1, 142 | wrcontrol_wraddress_reg_b => "CLOCK1" 143 | ) 144 | PORT MAP ( 145 | clock0 => clock_a, 146 | clocken1 => enable_b, 147 | wren_a => wren_a, 148 | address_b => address_b, 149 | clock1 => clock_b, 150 | clocken0 => enable_a, 151 | data_b => data_b, 152 | wren_b => wren_b, 153 | address_a => address_a, 154 | data_a => data_a, 155 | q_a => sub_wire0, 156 | q_b => sub_wire1 157 | ); 158 | 159 | 160 | 161 | END SYN; 162 | 163 | -- ============================================================ 164 | -- CNX file retrieval info 165 | -- ============================================================ 166 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 167 | -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 168 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 169 | -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 170 | -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 171 | -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 172 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 173 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 174 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 175 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" 176 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 177 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" 178 | -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" 179 | -- Retrieval info: PRIVATE: CLRq NUMERIC "0" 180 | -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 181 | -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" 182 | -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 183 | -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" 184 | -- Retrieval info: PRIVATE: Clock NUMERIC "5" 185 | -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" 186 | -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" 187 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 188 | -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 189 | -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 190 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 191 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 192 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 193 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 194 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 195 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 196 | -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768" 197 | -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 198 | -- Retrieval info: PRIVATE: MIFfilename STRING "../charset.hex" 199 | -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 200 | -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 201 | -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 202 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 203 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 204 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 205 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 206 | -- Retrieval info: PRIVATE: REGdata NUMERIC "1" 207 | -- Retrieval info: PRIVATE: REGq NUMERIC "0" 208 | -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 209 | -- Retrieval info: PRIVATE: REGrren NUMERIC "0" 210 | -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 211 | -- Retrieval info: PRIVATE: REGwren NUMERIC "1" 212 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 213 | -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 214 | -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 215 | -- Retrieval info: PRIVATE: VarWidth NUMERIC "1" 216 | -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" 217 | -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" 218 | -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" 219 | -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" 220 | -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 221 | -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 222 | -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 223 | -- Retrieval info: PRIVATE: enable NUMERIC "1" 224 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 225 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 226 | -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" 227 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 228 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" 229 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 230 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 231 | -- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" 232 | -- Retrieval info: CONSTANT: INIT_FILE STRING "../charset.hex" 233 | -- Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_A" 234 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 235 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 236 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 237 | -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096" 238 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 239 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 240 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 241 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 242 | -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 243 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 244 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 245 | -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12" 246 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 247 | -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" 248 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 249 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 250 | -- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" 251 | -- Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]" 252 | -- Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL "address_b[11..0]" 253 | -- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" 254 | -- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" 255 | -- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" 256 | -- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" 257 | -- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a" 258 | -- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b" 259 | -- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" 260 | -- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" 261 | -- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 262 | -- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 263 | -- Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0 264 | -- Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0 265 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 266 | -- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 267 | -- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0 268 | -- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0 269 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 270 | -- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 271 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 272 | -- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 273 | -- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 274 | -- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 275 | -- Retrieval info: GEN_FILE: TYPE_NORMAL displayram.vhd TRUE 276 | -- Retrieval info: GEN_FILE: TYPE_NORMAL displayram.inc FALSE 277 | -- Retrieval info: GEN_FILE: TYPE_NORMAL displayram.cmp TRUE 278 | -- Retrieval info: GEN_FILE: TYPE_NORMAL displayram.bsf FALSE 279 | -- Retrieval info: GEN_FILE: TYPE_NORMAL displayram_inst.vhd FALSE 280 | -- Retrieval info: LIB_FILE: altera_mf 281 | -------------------------------------------------------------------------------- /font_rom.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2013 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component font_rom 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 20 | clock : IN STD_LOGIC := '1'; 21 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 22 | ); 23 | end component; 24 | -------------------------------------------------------------------------------- /font_rom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "font_rom.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "font_rom.cmp"] 5 | -------------------------------------------------------------------------------- /font_rom.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ROM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: font_rom.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2013 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY font_rom IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 46 | clock : IN STD_LOGIC := '1'; 47 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 48 | ); 49 | END font_rom; 50 | 51 | 52 | ARCHITECTURE SYN OF font_rom IS 53 | 54 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 55 | 56 | 57 | 58 | COMPONENT altsyncram 59 | GENERIC ( 60 | clock_enable_input_a : STRING; 61 | clock_enable_output_a : STRING; 62 | init_file : STRING; 63 | intended_device_family : STRING; 64 | lpm_hint : STRING; 65 | lpm_type : STRING; 66 | numwords_a : NATURAL; 67 | operation_mode : STRING; 68 | outdata_aclr_a : STRING; 69 | outdata_reg_a : STRING; 70 | widthad_a : NATURAL; 71 | width_a : NATURAL; 72 | width_byteena_a : NATURAL 73 | ); 74 | PORT ( 75 | address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 76 | clock0 : IN STD_LOGIC ; 77 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 78 | ); 79 | END COMPONENT; 80 | 81 | BEGIN 82 | q <= sub_wire0(7 DOWNTO 0); 83 | 84 | altsyncram_component : altsyncram 85 | GENERIC MAP ( 86 | clock_enable_input_a => "BYPASS", 87 | clock_enable_output_a => "BYPASS", 88 | init_file => "./VGA-ROM-8x16.hex", 89 | intended_device_family => "Cyclone II", 90 | lpm_hint => "ENABLE_RUNTIME_MOD=NO", 91 | lpm_type => "altsyncram", 92 | numwords_a => 4096, 93 | operation_mode => "ROM", 94 | outdata_aclr_a => "NONE", 95 | outdata_reg_a => "UNREGISTERED", 96 | widthad_a => 12, 97 | width_a => 8, 98 | width_byteena_a => 1 99 | ) 100 | PORT MAP ( 101 | address_a => address, 102 | clock0 => clock, 103 | q_a => sub_wire0 104 | ); 105 | 106 | 107 | 108 | END SYN; 109 | 110 | -- ============================================================ 111 | -- CNX file retrieval info 112 | -- ============================================================ 113 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 114 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 115 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 116 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 117 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 118 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 119 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 120 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 121 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 122 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 123 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 124 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 125 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 126 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 127 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 128 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 129 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 130 | -- Retrieval info: PRIVATE: MIFfilename STRING "../VGA-ROM-8x16.hex" 131 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 132 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 133 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 134 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 135 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 138 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 139 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 140 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 141 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 142 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 143 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 144 | -- Retrieval info: CONSTANT: INIT_FILE STRING "../VGA-ROM-8x16.hex" 145 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 146 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 147 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 148 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 149 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 150 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 151 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 152 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 153 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 154 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 155 | -- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 156 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 157 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 158 | -- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 159 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 160 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 161 | -- Retrieval info: GEN_FILE: TYPE_NORMAL font_rom.vhd TRUE 162 | -- Retrieval info: GEN_FILE: TYPE_NORMAL font_rom.inc FALSE 163 | -- Retrieval info: GEN_FILE: TYPE_NORMAL font_rom.cmp TRUE 164 | -- Retrieval info: GEN_FILE: TYPE_NORMAL font_rom.bsf FALSE 165 | -- Retrieval info: GEN_FILE: TYPE_NORMAL font_rom_inst.vhd FALSE 166 | -- Retrieval info: LIB_FILE: altera_mf 167 | -------------------------------------------------------------------------------- /hex2rom.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/hex2rom.exe -------------------------------------------------------------------------------- /ps2_keyboard.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- FileName: ps2_keyboard.vhd 4 | -- Dependencies: debounce.vhd 5 | -- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version 6 | -- 7 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 8 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 9 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 10 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 11 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 12 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 13 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 14 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 15 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 16 | -- 17 | -- Version History 18 | -- Version 1.0 11/25/2013 Scott Larson 19 | -- Initial Public Release 20 | -- 21 | -------------------------------------------------------------------------------- 22 | 23 | LIBRARY ieee; 24 | USE ieee.std_logic_1164.all; 25 | 26 | ENTITY ps2_keyboard IS 27 | GENERIC( 28 | clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz 29 | debounce_counter_size : INTEGER := 8); --set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz) 30 | PORT( 31 | clk : IN STD_LOGIC; --system clock 32 | ps2_clk : IN STD_LOGIC; --clock signal from PS/2 keyboard 33 | ps2_data : IN STD_LOGIC; --data signal from PS/2 keyboard 34 | ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus 35 | ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --code received from PS/2 36 | END ps2_keyboard; 37 | 38 | ARCHITECTURE logic OF ps2_keyboard IS 39 | SIGNAL sync_ffs : STD_LOGIC_VECTOR(1 DOWNTO 0); --synchronizer flip-flops for PS/2 signals 40 | SIGNAL ps2_clk_int : STD_LOGIC; --debounced clock signal from PS/2 keyboard 41 | SIGNAL ps2_data_int : STD_LOGIC; --debounced data signal from PS/2 keyboard 42 | SIGNAL ps2_word : STD_LOGIC_VECTOR(10 DOWNTO 0); --stores the ps2 data word 43 | SIGNAL error : STD_LOGIC; --validate parity, start, and stop bits 44 | SIGNAL count_idle : INTEGER RANGE 0 TO clk_freq/18_000; --counter to determine PS/2 is idle 45 | 46 | --declare debounce component for debouncing PS2 input signals 47 | COMPONENT debounce IS 48 | GENERIC( 49 | counter_size : INTEGER); --debounce period (in seconds) = 2^counter_size/(clk freq in Hz) 50 | PORT( 51 | clk : IN STD_LOGIC; --input clock 52 | button : IN STD_LOGIC; --input signal to be debounced 53 | result : OUT STD_LOGIC); --debounced signal 54 | END COMPONENT; 55 | BEGIN 56 | 57 | --synchronizer flip-flops 58 | PROCESS(clk) 59 | BEGIN 60 | IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock 61 | sync_ffs(0) <= ps2_clk; --synchronize PS/2 clock signal 62 | sync_ffs(1) <= ps2_data; --synchronize PS/2 data signal 63 | END IF; 64 | END PROCESS; 65 | 66 | --debounce PS2 input signals 67 | debounce_ps2_clk: debounce 68 | GENERIC MAP(counter_size => debounce_counter_size) 69 | PORT MAP(clk => clk, button => sync_ffs(0), result => ps2_clk_int); 70 | debounce_ps2_data: debounce 71 | GENERIC MAP(counter_size => debounce_counter_size) 72 | PORT MAP(clk => clk, button => sync_ffs(1), result => ps2_data_int); 73 | 74 | --input PS2 data 75 | PROCESS(ps2_clk_int) 76 | BEGIN 77 | IF(ps2_clk_int'EVENT AND ps2_clk_int = '0') THEN --falling edge of PS2 clock 78 | ps2_word <= ps2_data_int & ps2_word(10 DOWNTO 1); --shift in PS2 data bit 79 | END IF; 80 | END PROCESS; 81 | 82 | --verify that parity, start, and stop bits are all correct 83 | error <= NOT (NOT ps2_word(0) AND ps2_word(10) AND (ps2_word(9) XOR ps2_word(8) XOR 84 | ps2_word(7) XOR ps2_word(6) XOR ps2_word(5) XOR ps2_word(4) XOR ps2_word(3) XOR 85 | ps2_word(2) XOR ps2_word(1))); 86 | 87 | --determine if PS2 port is idle (i.e. last transaction is finished) and output result 88 | PROCESS(clk) 89 | BEGIN 90 | IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock 91 | 92 | IF(ps2_clk_int = '0') THEN --low PS2 clock, PS/2 is active 93 | count_idle <= 0; --reset idle counter 94 | ELSIF(count_idle /= clk_freq/18_000) THEN --PS2 clock has been high less than a half clock period (<55us) 95 | count_idle <= count_idle + 1; --continue counting 96 | END IF; 97 | 98 | IF(count_idle = clk_freq/18_000 AND error = '0') THEN --idle threshold reached and no errors detected 99 | ps2_code_new <= '1'; --set flag that new PS/2 code is available 100 | ps2_code <= ps2_word(8 DOWNTO 1); --output new PS/2 code 101 | ELSE --PS/2 port active or error detected 102 | ps2_code_new <= '0'; --set flag that PS/2 transaction is in progress 103 | END IF; 104 | 105 | END IF; 106 | END PROCESS; 107 | 108 | END logic; 109 | -------------------------------------------------------------------------------- /rom1.asm: -------------------------------------------------------------------------------- 1 | ; z80asm -v -a rom1.asm 2 | 3 | SCREEN EQU 61440 4 | STACKTOP EQU 33790 5 | MEMSTART EQU 32768 6 | 7 | ORG 00h 8 | START: 9 | ld sp,STACKTOP 10 | JP MAIN 11 | 12 | ORG 08h 13 | 14 | ORG 10h 15 | 16 | ORG 20h 17 | 18 | ORG 28h 19 | 20 | ORG 30h 21 | 22 | ORG 38h 23 | ; interrupt handler 24 | ei 25 | reti 26 | 27 | ORG 66h 28 | ; NMI handler 29 | exx 30 | ex af,af' 31 | 32 | ld a, 'X' 33 | ld hl, SCREEN 34 | ld (hl), a 35 | 36 | ex af,af' 37 | exx 38 | retn 39 | 40 | ; CP/M style - real stuff starts here 41 | ORG 100h 42 | MAIN: 43 | 44 | ld a,01h ; first led 45 | out (0ffh),a 46 | 47 | ; save something to RAM and see if we get it back 48 | ld hl, MEMSTART 49 | ld (hl), a 50 | ld d,(hl) 51 | 52 | cp d 53 | jr nz, fail 54 | 55 | ld a,0AAh ; every second led 56 | out (0ffh),a 57 | 58 | fail: 59 | 60 | ld a, 22 61 | ; just to test that the RAM is working! 62 | push af 63 | 64 | startmessage: 65 | ld hl,SCREEN 66 | ld de,message 67 | ld a,(de) 68 | ld b,a 69 | inc de 70 | msgloop: 71 | ld a,(de) 72 | ld (hl),a 73 | inc de 74 | inc hl 75 | ld a,%11001111 ; white on red flashing 76 | ld (hl),a 77 | inc hl 78 | djnz msgloop 79 | 80 | ; The first byte on the start of the 7th row (160*7 + 1) 81 | ld de, 960 82 | 83 | ld a,0 84 | ld c, '*' 85 | ld hl, SCREEN 86 | add hl, de 87 | 88 | ld b,8 89 | row1: 90 | push bc 91 | ld b,16 92 | col1: 93 | ld (hl),c 94 | inc hl 95 | ld (hl),a 96 | inc hl 97 | ld (hl),c 98 | inc hl 99 | ld (hl),a 100 | inc hl 101 | inc a 102 | djnz col1 103 | 104 | ld de, 96 105 | add hl, de 106 | 107 | pop bc 108 | djnz row1 109 | 110 | 111 | halt 112 | 113 | ; this is the high-speed character spew. We don't need that now. 114 | 115 | ld a,65 116 | startscreen: 117 | ld hl,SCREEN 118 | 119 | ld b, 25 120 | rowloop: 121 | push bc 122 | ld b,79 123 | lineloop: 124 | ld (hl),a 125 | inc hl 126 | inc hl 127 | 128 | djnz lineloop 129 | 130 | pop bc 131 | inc a 132 | djnz rowloop 133 | 134 | push af 135 | ; toggle LED 6 136 | ld d,32 137 | in a,(0ffh) 138 | xor d 139 | out (0ffh),a 140 | pop af 141 | 142 | jp startscreen 143 | 144 | message: 145 | DEFB 50 146 | DEFM "This is the FPGA vt100 emulator. Nothing works yet" 147 | 148 | -------------------------------------------------------------------------------- /rom1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/rom1.bin -------------------------------------------------------------------------------- /rom1.hex: -------------------------------------------------------------------------------- 1 | :2000000031FE83C3000100000000000000000000000000000000000000000000000000006A 2 | :20002000000000000000000000000000000000000000000000000000FBED4D00000000008B 3 | :200040000000000000000000000000000000000000000000000000000000000000000000A0 4 | :20006000000000000000D9083E582100F07708D9ED4500000000000000000000000000006E 5 | :20008000000000000000000000000000000000000000000000000000000000000000000060 6 | :2000A000000000000000000000000000000000000000000000000000000000000000000040 7 | :2000C000000000000000000000000000000000000000000000000000000000000000000020 8 | :2000E000000000000000000000000000000000000000000000000000000000000000000000 9 | :200100003E01D3FF2100807756BA20043EAAD3FF3E16F52100F01168011A47131A771323B9 10 | :200120003ECF772310F611C0033E000E2A2100F0190608C5061071237723712377233C100D 11 | :20014000F511600019C110EB763E412100F00619C5064F77232310FBC13C10F4F51620DB56 12 | :20016000FFAAD3FFF1C34B01325468697320697320746865204650474120767431303020E4 13 | :20018000656D756C61746F722E204E6F7468696E6720776F726B7320796574000000000009 14 | :2001A00000000000000000000000000000000000000000000000000000000000000000003F 15 | :2001C00000000000000000000000000000000000000000000000000000000000000000001F 16 | :2001E0000000000000000000000000000000000000000000000000000000000000000000FF 17 | :200200000000000000000000000000000000000000000000000000000000000000000000DE 18 | :200220000000000000000000000000000000000000000000000000000000000000000000BE 19 | :2002400000000000000000000000000000000000000000000000000000000000000000009E 20 | :2002600000000000000000000000000000000000000000000000000000000000000000007E 21 | :2002800000000000000000000000000000000000000000000000000000000000000000005E 22 | :2002A00000000000000000000000000000000000000000000000000000000000000000003E 23 | :2002C00000000000000000000000000000000000000000000000000000000000000000001E 24 | :2002E0000000000000000000000000000000000000000000000000000000000000000000FE 25 | :200300000000000000000000000000000000000000000000000000000000000000000000DD 26 | :200320000000000000000000000000000000000000000000000000000000000000000000BD 27 | :2003400000000000000000000000000000000000000000000000000000000000000000009D 28 | :2003600000000000000000000000000000000000000000000000000000000000000000007D 29 | :2003800000000000000000000000000000000000000000000000000000000000000000005D 30 | :2003A00000000000000000000000000000000000000000000000000000000000000000003D 31 | :2003C00000000000000000000000000000000000000000000000000000000000000000001D 32 | :2003E0000000000000000000000000000000000000000000000000000000000000000000FD 33 | :200400000000000000000000000000000000000000000000000000000000000000000000DC 34 | :200420000000000000000000000000000000000000000000000000000000000000000000BC 35 | :2004400000000000000000000000000000000000000000000000000000000000000000009C 36 | :2004600000000000000000000000000000000000000000000000000000000000000000007C 37 | :2004800000000000000000000000000000000000000000000000000000000000000000005C 38 | :2004A00000000000000000000000000000000000000000000000000000000000000000003C 39 | :2004C00000000000000000000000000000000000000000000000000000000000000000001C 40 | :2004E0000000000000000000000000000000000000000000000000000000000000000000FC 41 | :200500000000000000000000000000000000000000000000000000000000000000000000DB 42 | :200520000000000000000000000000000000000000000000000000000000000000000000BB 43 | :2005400000000000000000000000000000000000000000000000000000000000000000009B 44 | :2005600000000000000000000000000000000000000000000000000000000000000000007B 45 | :2005800000000000000000000000000000000000000000000000000000000000000000005B 46 | :2005A00000000000000000000000000000000000000000000000000000000000000000003B 47 | :2005C00000000000000000000000000000000000000000000000000000000000000000001B 48 | :2005E0000000000000000000000000000000000000000000000000000000000000000000FB 49 | :200600000000000000000000000000000000000000000000000000000000000000000000DA 50 | :200620000000000000000000000000000000000000000000000000000000000000000000BA 51 | :2006400000000000000000000000000000000000000000000000000000000000000000009A 52 | :2006600000000000000000000000000000000000000000000000000000000000000000007A 53 | :2006800000000000000000000000000000000000000000000000000000000000000000005A 54 | :2006A00000000000000000000000000000000000000000000000000000000000000000003A 55 | :2006C00000000000000000000000000000000000000000000000000000000000000000001A 56 | :2006E0000000000000000000000000000000000000000000000000000000000000000000FA 57 | :200700000000000000000000000000000000000000000000000000000000000000000000D9 58 | :200720000000000000000000000000000000000000000000000000000000000000000000B9 59 | :20074000000000000000000000000000000000000000000000000000000000000000000099 60 | :20076000000000000000000000000000000000000000000000000000000000000000000079 61 | :20078000000000000000000000000000000000000000000000000000000000000000000059 62 | :2007A000000000000000000000000000000000000000000000000000000000000000000039 63 | :2007C000000000000000000000000000000000000000000000000000000000000000000019 64 | :2007E0000000000000000000000000000000000000000000000000000000000000000000F9 65 | :200800000000000000000000000000000000000000000000000000000000000000000000D8 66 | :200820000000000000000000000000000000000000000000000000000000000000000000B8 67 | :20084000000000000000000000000000000000000000000000000000000000000000000098 68 | :20086000000000000000000000000000000000000000000000000000000000000000000078 69 | :20088000000000000000000000000000000000000000000000000000000000000000000058 70 | :2008A000000000000000000000000000000000000000000000000000000000000000000038 71 | :2008C000000000000000000000000000000000000000000000000000000000000000000018 72 | :2008E0000000000000000000000000000000000000000000000000000000000000000000F8 73 | :200900000000000000000000000000000000000000000000000000000000000000000000D7 74 | :200920000000000000000000000000000000000000000000000000000000000000000000B7 75 | :20094000000000000000000000000000000000000000000000000000000000000000000097 76 | :20096000000000000000000000000000000000000000000000000000000000000000000077 77 | :20098000000000000000000000000000000000000000000000000000000000000000000057 78 | :2009A000000000000000000000000000000000000000000000000000000000000000000037 79 | :2009C000000000000000000000000000000000000000000000000000000000000000000017 80 | :2009E0000000000000000000000000000000000000000000000000000000000000000000F7 81 | :200A00000000000000000000000000000000000000000000000000000000000000000000D6 82 | :200A20000000000000000000000000000000000000000000000000000000000000000000B6 83 | :200A4000000000000000000000000000000000000000000000000000000000000000000096 84 | :200A6000000000000000000000000000000000000000000000000000000000000000000076 85 | :200A8000000000000000000000000000000000000000000000000000000000000000000056 86 | :200AA000000000000000000000000000000000000000000000000000000000000000000036 87 | :200AC000000000000000000000000000000000000000000000000000000000000000000016 88 | :200AE0000000000000000000000000000000000000000000000000000000000000000000F6 89 | :200B00000000000000000000000000000000000000000000000000000000000000000000D5 90 | :200B20000000000000000000000000000000000000000000000000000000000000000000B5 91 | :200B4000000000000000000000000000000000000000000000000000000000000000000095 92 | :200B6000000000000000000000000000000000000000000000000000000000000000000075 93 | :200B8000000000000000000000000000000000000000000000000000000000000000000055 94 | :200BA000000000000000000000000000000000000000000000000000000000000000000035 95 | :200BC000000000000000000000000000000000000000000000000000000000000000000015 96 | :200BE0000000000000000000000000000000000000000000000000000000000000000000F5 97 | :200C00000000000000000000000000000000000000000000000000000000000000000000D4 98 | :200C20000000000000000000000000000000000000000000000000000000000000000000B4 99 | :200C4000000000000000000000000000000000000000000000000000000000000000000094 100 | :200C6000000000000000000000000000000000000000000000000000000000000000000074 101 | :200C8000000000000000000000000000000000000000000000000000000000000000000054 102 | :200CA000000000000000000000000000000000000000000000000000000000000000000034 103 | :200CC000000000000000000000000000000000000000000000000000000000000000000014 104 | :200CE0000000000000000000000000000000000000000000000000000000000000000000F4 105 | :200D00000000000000000000000000000000000000000000000000000000000000000000D3 106 | :200D20000000000000000000000000000000000000000000000000000000000000000000B3 107 | :200D4000000000000000000000000000000000000000000000000000000000000000000093 108 | :200D6000000000000000000000000000000000000000000000000000000000000000000073 109 | :200D8000000000000000000000000000000000000000000000000000000000000000000053 110 | :200DA000000000000000000000000000000000000000000000000000000000000000000033 111 | :200DC000000000000000000000000000000000000000000000000000000000000000000013 112 | :200DE0000000000000000000000000000000000000000000000000000000000000000000F3 113 | :200E00000000000000000000000000000000000000000000000000000000000000000000D2 114 | :200E20000000000000000000000000000000000000000000000000000000000000000000B2 115 | :200E4000000000000000000000000000000000000000000000000000000000000000000092 116 | :200E6000000000000000000000000000000000000000000000000000000000000000000072 117 | :200E8000000000000000000000000000000000000000000000000000000000000000000052 118 | :200EA000000000000000000000000000000000000000000000000000000000000000000032 119 | :200EC000000000000000000000000000000000000000000000000000000000000000000012 120 | :200EE0000000000000000000000000000000000000000000000000000000000000000000F2 121 | :200F00000000000000000000000000000000000000000000000000000000000000000000D1 122 | :200F20000000000000000000000000000000000000000000000000000000000000000000B1 123 | :200F4000000000000000000000000000000000000000000000000000000000000000000091 124 | :200F6000000000000000000000000000000000000000000000000000000000000000000071 125 | :200F8000000000000000000000000000000000000000000000000000000000000000000051 126 | :200FA000000000000000000000000000000000000000000000000000000000000000000031 127 | :200FC000000000000000000000000000000000000000000000000000000000000000000011 128 | :200FE0000000000000000000000000000000000000000000000000000000000000000000F1 129 | :00000001FF 130 | -------------------------------------------------------------------------------- /simulation/modelsim/testbench.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee ; 2 | LIBRARY std ; 3 | USE ieee.std_logic_1164.all ; 4 | USE ieee.std_logic_arith.all ; 5 | USE ieee.std_logic_textio.all ; 6 | USE ieee.STD_LOGIC_UNSIGNED.all ; 7 | USE ieee.std_logic_unsigned.all ; 8 | USE std.textio.all ; 9 | ENTITY testbench IS 10 | END ; 11 | 12 | ARCHITECTURE testbench_arch OF testbench IS 13 | SIGNAL Reset_n : STD_LOGIC ; 14 | SIGNAL hSync : STD_LOGIC ; 15 | SIGNAL videoB : std_logic_vector (1 downto 0) ; 16 | SIGNAL videoR : std_logic_vector (1 downto 0) ; 17 | SIGNAL videoG : std_logic_vector (1 downto 0) ; 18 | SIGNAL clk : STD_LOGIC ; 19 | SIGNAL vSync : STD_LOGIC ; 20 | 21 | BEGIN 22 | DUT : entity work.vt100 23 | PORT MAP ( 24 | Reset_n => Reset_n , 25 | hSync => hSync , 26 | videoB => videoB , 27 | videoR => videoR , 28 | videoG => videoG , 29 | 30 | NMI_n => '1', 31 | 32 | RXD0 => '0', 33 | CTS0 => '0', 34 | DSR0 => '0', 35 | RI0 => '0', 36 | DCD0 => '0', 37 | 38 | clk => clk , 39 | vSync => vSync ) ; 40 | 41 | 42 | 43 | -- "Clock Pattern" : dutyCycle = 50 44 | -- Start Time = 0 ns, End Time = 1 us, Period = 20 ns 45 | Process 46 | Begin 47 | clk <= '0' ; 48 | wait for 10 ns ; 49 | -- 10 ns, single loop till start period. 50 | for Z in 1 to 360000 51 | loop 52 | clk <= '1' ; 53 | wait for 10 ns ; 54 | clk <= '0' ; 55 | wait for 10 ns ; 56 | -- 990 ns, repeat pattern in loop. 57 | end loop; 58 | clk <= '1' ; 59 | wait for 10 ns ; 60 | -- dumped values till 1 us 61 | wait; 62 | End Process; 63 | 64 | -- hold reset low for a few clocks to make sure the counters get reset 65 | Process 66 | Begin 67 | Reset_n <= '0'; 68 | wait for 100 ns; 69 | Reset_n <= '1'; 70 | wait; 71 | End Process; 72 | 73 | END; 74 | -------------------------------------------------------------------------------- /simulation/modelsim/vga_gfx_testbench.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee ; 2 | LIBRARY std ; 3 | USE ieee.std_logic_1164.all ; 4 | USE ieee.std_logic_textio.all ; 5 | USE ieee.std_logic_unsigned.all ; 6 | use IEEE.NUMERIC_STD.all; 7 | 8 | ENTITY vga_gfx_testbench IS 9 | END ; 10 | 11 | ARCHITECTURE testbench_arch OF vga_gfx_testbench IS 12 | SIGNAL n_reset : STD_LOGIC ; 13 | SIGNAL hSync : STD_LOGIC ; 14 | SIGNAL clk : STD_LOGIC ; 15 | SIGNAL vSync : STD_LOGIC ; 16 | 17 | SIGNAL row : unsigned(9 downto 0); 18 | SIGNAL col : unsigned(9 downto 0); 19 | 20 | SIGNAL enable : std_LOGIC; 21 | 22 | SIGNAL row_start : std_logic; 23 | SIGNAL frame_start : std_logic; 24 | 25 | SIGNAL videoR : std_logic_vector(1 downto 0); 26 | SIGNAL videoG : std_logic_vector(1 downto 0); 27 | SIGNAL videoB : std_logic_vector(1 downto 0); 28 | 29 | signal dispram_addr_b : std_logic_vector(10 downto 0) := "00000000000"; 30 | signal dispram_output_b : std_logic_vector(15 downto 0); 31 | 32 | COMPONENT vga_controller 33 | PORT ( 34 | n_reset : in STD_LOGIC ; 35 | hSync : out STD_LOGIC ; 36 | pixelClk : in STD_LOGIC ; 37 | disp_enable : out std_logic; 38 | column : out unsigned(9 downto 0); 39 | row : out unsigned(9 downto 0); 40 | frame_start : out std_logic := '0'; 41 | row_start : out std_logic := '0'; 42 | vSync : out STD_LOGIC ); 43 | END COMPONENT ; 44 | 45 | BEGIN 46 | DUT : vga_controller 47 | PORT MAP ( 48 | n_reset => n_reset , 49 | hSync => hSync , 50 | pixelClk => clk , 51 | disp_enable => enable, 52 | row_start => row_start, 53 | frame_start => frame_start, 54 | row => row, 55 | column => col, 56 | vSync => vSync ) ; 57 | 58 | vgagfx1: entity work.vga_textmode 59 | port map( 60 | n_reset => n_reset, 61 | pixelClk => clk, 62 | row => std_logic_vector(row), 63 | column => std_logic_vector(col), 64 | disp_enable => enable, 65 | row_start => row_start, 66 | frame_start => frame_start, 67 | display_mem_addr => dispram_addr_b, 68 | display_mem_data => dispram_output_b, 69 | videoR => videoR, 70 | videoG => videoG, 71 | videoB => videoB 72 | ); 73 | 74 | displaymem: entity work.displayram 75 | port map ( 76 | clock_a => clk, 77 | address_a => "000000000000", 78 | --q_a => "00000000", 79 | data_a => "00000000", 80 | 81 | clock_b => clk, 82 | address_b => dispram_addr_b, 83 | q_b => dispram_output_b, 84 | data_b => "0000000000000000" 85 | ); 86 | 87 | -- "Clock Pattern" : dutyCycle = 50 88 | -- Start Time = 0 ns, End Time = 1 us, Period = 20 ns 89 | Process 90 | Begin 91 | clk <= '0' ; 92 | wait for 10 ns ; 93 | -- 10 ns, single loop till start period. 94 | -- this is 18ms (one frame is 13.8ms) 95 | for Z in 1 to 1800000 96 | loop 97 | clk <= '1' ; 98 | wait for 10 ns ; 99 | clk <= '0' ; 100 | wait for 10 ns ; 101 | -- 990 ns, repeat pattern in loop. 102 | end loop; 103 | clk <= '1' ; 104 | wait for 10 ns ; 105 | -- dumped values till 1 us 106 | wait; 107 | End Process; 108 | 109 | -- hold reset low for a few clocks to make sure the counters get reset 110 | Process 111 | Begin 112 | n_reset <= '0'; 113 | wait for 100 ns; 114 | n_reset <= '1'; 115 | wait; 116 | End Process; 117 | 118 | END; -------------------------------------------------------------------------------- /simulation/modelsim/vga_testbench.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee ; 2 | LIBRARY std ; 3 | USE ieee.std_logic_1164.all ; 4 | USE ieee.std_logic_textio.all ; 5 | USE ieee.std_logic_unsigned.all ; 6 | use IEEE.NUMERIC_STD.all; 7 | 8 | ENTITY vga_testbench IS 9 | END ; 10 | 11 | ARCHITECTURE testbench_arch OF vga_testbench IS 12 | SIGNAL n_reset : STD_LOGIC ; 13 | SIGNAL hSync : STD_LOGIC ; 14 | SIGNAL clk : STD_LOGIC ; 15 | SIGNAL vSync : STD_LOGIC ; 16 | 17 | SIGNAL row : unsigned(9 downto 0); 18 | SIGNAL col : unsigned(9 downto 0); 19 | 20 | SIGNAL enable : std_LOGIC; 21 | 22 | COMPONENT vga_controller 23 | PORT ( 24 | n_reset : in STD_LOGIC ; 25 | hSync : out STD_LOGIC ; 26 | pixelClk : in STD_LOGIC ; 27 | disp_enable : out std_logic; 28 | column : out unsigned(9 downto 0); 29 | row : out unsigned(9 downto 0); 30 | vSync : out STD_LOGIC ); 31 | END COMPONENT ; 32 | 33 | BEGIN 34 | DUT : vga_controller 35 | PORT MAP ( 36 | n_reset => n_reset , 37 | hSync => hSync , 38 | pixelClk => clk , 39 | disp_enable => enable, 40 | row => row, 41 | column => col, 42 | vSync => vSync ) ; 43 | 44 | -- "Clock Pattern" : dutyCycle = 50 45 | -- Start Time = 0 ns, End Time = 1 us, Period = 20 ns 46 | Process 47 | Begin 48 | clk <= '0' ; 49 | wait for 10 ns ; 50 | -- 10 ns, single loop till start period. 51 | -- this is 18ms (one frame is 13.8ms) 52 | for Z in 1 to 1800000 53 | loop 54 | clk <= '1' ; 55 | wait for 10 ns ; 56 | clk <= '0' ; 57 | wait for 10 ns ; 58 | -- 990 ns, repeat pattern in loop. 59 | end loop; 60 | clk <= '1' ; 61 | wait for 10 ns ; 62 | -- dumped values till 1 us 63 | wait; 64 | End Process; 65 | 66 | -- hold reset low for a few clocks to make sure the counters get reset 67 | Process 68 | Begin 69 | n_reset <= '0'; 70 | wait for 100 ns; 71 | n_reset <= '1'; 72 | wait; 73 | End Process; 74 | 75 | END; -------------------------------------------------------------------------------- /sram.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2013 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component sram 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 20 | clock : IN STD_LOGIC := '1'; 21 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 22 | wren : IN STD_LOGIC ; 23 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 24 | ); 25 | end component; 26 | -------------------------------------------------------------------------------- /sram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sram.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sram.cmp"] 5 | -------------------------------------------------------------------------------- /sram.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %RAM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: sram.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2013 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY sram IS 43 | PORT 44 | ( 45 | address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 46 | clock : IN STD_LOGIC := '1'; 47 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 48 | wren : IN STD_LOGIC ; 49 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 50 | ); 51 | END sram; 52 | 53 | 54 | ARCHITECTURE SYN OF sram IS 55 | 56 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); 57 | 58 | 59 | 60 | COMPONENT altsyncram 61 | GENERIC ( 62 | clock_enable_input_a : STRING; 63 | clock_enable_output_a : STRING; 64 | intended_device_family : STRING; 65 | lpm_hint : STRING; 66 | lpm_type : STRING; 67 | numwords_a : NATURAL; 68 | operation_mode : STRING; 69 | outdata_aclr_a : STRING; 70 | outdata_reg_a : STRING; 71 | power_up_uninitialized : STRING; 72 | widthad_a : NATURAL; 73 | width_a : NATURAL; 74 | width_byteena_a : NATURAL 75 | ); 76 | PORT ( 77 | address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 78 | clock0 : IN STD_LOGIC ; 79 | data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 80 | wren_a : IN STD_LOGIC ; 81 | q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 82 | ); 83 | END COMPONENT; 84 | 85 | BEGIN 86 | q <= sub_wire0(7 DOWNTO 0); 87 | 88 | altsyncram_component : altsyncram 89 | GENERIC MAP ( 90 | clock_enable_input_a => "BYPASS", 91 | clock_enable_output_a => "BYPASS", 92 | intended_device_family => "Cyclone II", 93 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SRAM", 94 | lpm_type => "altsyncram", 95 | numwords_a => 1024, 96 | operation_mode => "SINGLE_PORT", 97 | outdata_aclr_a => "NONE", 98 | outdata_reg_a => "UNREGISTERED", 99 | power_up_uninitialized => "FALSE", 100 | widthad_a => 10, 101 | width_a => 8, 102 | width_byteena_a => 1 103 | ) 104 | PORT MAP ( 105 | address_a => address, 106 | clock0 => clock, 107 | data_a => data, 108 | wren_a => wren, 109 | q_a => sub_wire0 110 | ); 111 | 112 | 113 | 114 | END SYN; 115 | 116 | -- ============================================================ 117 | -- CNX file retrieval info 118 | -- ============================================================ 119 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 120 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 121 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 122 | -- Retrieval info: PRIVATE: AclrData NUMERIC "0" 123 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 124 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 125 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 126 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 127 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 128 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 129 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 130 | -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 131 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 132 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 133 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 134 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 135 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 136 | -- Retrieval info: PRIVATE: JTAG_ID STRING "SRAM" 137 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 138 | -- Retrieval info: PRIVATE: MIFfilename STRING "" 139 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" 140 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 141 | -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 142 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 143 | -- Retrieval info: PRIVATE: RegData NUMERIC "1" 144 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 145 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 146 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 147 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 148 | -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 149 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" 150 | -- Retrieval info: PRIVATE: WidthData NUMERIC "8" 151 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 152 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 153 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 154 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 155 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 156 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SRAM" 157 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 158 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" 159 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 160 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 161 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 162 | -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 163 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" 164 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 165 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 166 | -- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" 167 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 168 | -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 169 | -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 170 | -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 171 | -- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 172 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 173 | -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 174 | -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 175 | -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 176 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.vhd TRUE 177 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.inc FALSE 178 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.cmp TRUE 179 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram.bsf FALSE 180 | -- Retrieval info: GEN_FILE: TYPE_NORMAL sram_inst.vhd FALSE 181 | -- Retrieval info: LIB_FILE: altera_mf 182 | -------------------------------------------------------------------------------- /trunc.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardjones/fpga-vt/9cad5042b080e131ffd2913c856c802c1a327192/trunc.exe -------------------------------------------------------------------------------- /update-z80.bat: -------------------------------------------------------------------------------- 1 | rem Assemble 2 | z80asm -v -a rom1.asm 3 | 4 | rem pad to 4K ROM size 5 | trunc rom1.bin 4096 6 | 7 | rem convert to intel hex format for Quartus 8 | bin2hex rom1.bin 4k-blank.hex 9 | 10 | rem Update the MIF files from the .hex files 11 | c:\altera\13.0sp1\quartus\bin\quartus_cdb vt100 -c vt100 --update_mif 12 | rem update the actual bitstream without resynthesising everything 13 | c:\altera\13.0sp1\quartus\bin\quartus_asm vt100 14 | -------------------------------------------------------------------------------- /vga-controller.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | -- use IEEE.STD_LOGIC_ARITH.all; 4 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 5 | use IEEE.NUMERIC_STD.all; 6 | 7 | entity vga_controller is 8 | generic( 9 | h_pulse : integer := 120; 10 | h_backporch : integer := 64; 11 | h_pixels : integer := 800; 12 | h_frontporch : integer := 56; 13 | h_syncpol : std_logic := '1'; 14 | 15 | v_pulse : integer := 6; 16 | v_backporch : integer := 23; 17 | v_pixels : integer := 600; 18 | v_frontporch : integer := 37; 19 | v_syncpol : std_logic := '1' 20 | ); 21 | port( 22 | n_reset : in std_logic; 23 | pixelClk : in std_logic; -- pixel clock (50MHz) 24 | 25 | disp_enable : out std_logic; 26 | column : out unsigned(9 downto 0); 27 | row : out unsigned(9 downto 0); 28 | 29 | frame_start : out std_logic := '0'; 30 | row_start : out std_logic := '0'; 31 | 32 | hSync : out std_logic; 33 | vSync : out std_logic 34 | ); 35 | 36 | end vga_controller; 37 | 38 | architecture behavior of vga_controller is 39 | constant horiz_period : integer := h_pulse + h_pixels + h_backporch + h_frontporch; 40 | constant vert_period : integer := v_pulse + v_pixels + v_backporch + v_frontporch; 41 | begin 42 | 43 | process(pixelClk, n_reset) 44 | variable h_count : integer range 0 to horiz_period := 0; 45 | variable v_count : integer range 0 to vert_period := 0; 46 | 47 | begin 48 | 49 | if(n_reset = '0') then 50 | h_count := 0; 51 | v_count := 0; 52 | 53 | hSync <= not h_syncpol; 54 | vSync <= not v_syncpol; 55 | 56 | disp_enable <= '0'; 57 | column <= "0000000000"; 58 | row <= "0000000000"; 59 | 60 | elsif(rising_edge(pixelClk)) then 61 | 62 | -- handle coordinate counters 63 | if(h_count < horiz_period) then 64 | h_count := h_count + 1; 65 | else 66 | h_count := 0; 67 | 68 | if(v_count < vert_period) then 69 | v_count := v_count + 1; 70 | else 71 | v_count := 0; 72 | end if; 73 | end if; 74 | 75 | if(h_count < h_pixels + h_frontporch or h_count > h_pixels + h_frontporch + h_pulse) then 76 | hSync <= not h_syncpol; 77 | else 78 | hSync <= h_syncpol; 79 | end if; 80 | 81 | if(v_count < v_pixels + v_frontporch or v_count > v_pixels + v_frontporch + v_pulse) then 82 | vSync <= not v_syncpol; 83 | else 84 | vSync <= v_syncpol; 85 | end if; 86 | 87 | if(h_count < h_pixels) then 88 | column <= to_unsigned(h_count, 10); 89 | end if; 90 | 91 | if(v_count < v_pixels) then 92 | row <= to_unsigned(v_count, 10); 93 | end if; 94 | 95 | if(h_count < h_pixels and v_count < v_pixels) then 96 | disp_enable <= '1'; 97 | 98 | if (h_count = 0 and v_count = 0) then 99 | frame_start <= '1'; 100 | else 101 | frame_start <= '0'; 102 | end if; 103 | 104 | if (h_count = 0) then 105 | row_start <= '1'; 106 | else 107 | row_start <= '0'; 108 | end if; 109 | else 110 | disp_enable <= '0'; 111 | end if; 112 | 113 | end if; 114 | 115 | end process; 116 | 117 | end behavior; 118 | -------------------------------------------------------------------------------- /vga-rom.hex: -------------------------------------------------------------------------------- 1 | :200000000000000000000000000000000000000000007E81A58181BD9981817E0000000064 2 | :2000200000007EFFDBFFFFC3E7FFFF7E00000000000000006CFEFEFEFE7C3810000000001C 3 | :200040000000000010387CFE7C38100000000000000000183C3CE7E7E718183C0000000069 4 | :20006000000000183C7EFFFF7E18183C00000000000000000000183C3C180000000000001E 5 | :20008000FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF00000000003C664242663C000000000050 6 | :2000A000FFFFFFFFFFC399BDBD99C3FFFFFFFFFF00001E0E1A3278CCCCCCCC780000000080 7 | :2000C00000003C666666663C187E18180000000000003F333F3030303070F0E00000000099 8 | :2000E00000007F637F6363636367E7E6C00000000000001818DB3CE73CDB181800000000AA 9 | :200100000080C0E0F0F8FEF8F0E0C080000000000002060E1E3EFE3E1E0E060200000000EF 10 | :200120000000183C7E1818187E3C180000000000000066666666666666006666000000003D 11 | :2001400000007FDBDBDB7B1B1B1B1B1B00000000007CC660386CC6C66C380CC67C000000C9 12 | :200160000000000000000000FEFEFEFE000000000000183C7E1818187E3C187E000000001D 13 | :200180000000183C7E18181818181818000000000000181818181818187E3C18000000006B 14 | :2001A0000000000000180CFE0C1800000000000000000000003060FE6030000000000000DB 15 | :2001C000000000000000C0C0C0FE00000000000000000000002466FF6624000000000000CE 16 | :2001E000000000001038387C7CFEFE000000000000000000FEFE7C7C383810000000000017 17 | :20020000000000000000000000000000000000000000183C3C3C181818001818000000009A 18 | :20022000006666662400000000000000000000000000006C6CFE6C6C6CFE6C6C0000000078 19 | :2002400018187CC6C2C07C060686C67C1818000000000000C2C60C183060C68600000000A2 20 | :200260000000386C6C3876DCCCCCCC7600000000003030306000000000000000000000001A 21 | :2002800000000C18303030303030180C00000000000030180C0C0C0C0C0C1830000000001E 22 | :2002A0000000000000663CFF3C66000000000000000000000018187E18180000000000001D 23 | :2002C0000000000000000000001818183000000000000000000000FE0000000000000000A8 24 | :2002E000000000000000000000001818000000000000000002060C183060C08000000000D2 25 | :2003000000003C66C3C3DBDBC3C3663C0000000000001838781818181818187E0000000001 26 | :2003200000007CC6060C183060C0C6FE0000000000007CC606063C060606C67C000000005F 27 | :2003400000000C1C3C6CCCFE0C0C0C1E000000000000FEC0C0C0FC060606C67C0000000033 28 | :2003600000003860C0C0FCC6C6C6C67C000000000000FEC606060C18303030300000000021 29 | :2003800000007CC6C6C67CC6C6C6C67C0000000000007CC6C6C67E0606060C78000000009D 30 | :2003A00000000000181800000018180000000000000000001818000000181830000000004D 31 | :2003C000000000060C18306030180C060000000000000000007E00007E000000000000000D 32 | :2003E0000000006030180C060C1830600000000000007CC6C60C1818180018180000000003 33 | :200400000000007CC6C6DEDEDEDCC07C00000000000010386CC6C6FEC6C6C6C600000000CC 34 | :200420000000FC6666667C66666666FC0000000000003C66C2C0C0C0C0C2663C00000000B6 35 | :200440000000F86C6666666666666CF8000000000000FE6662687868606266FE000000003C 36 | :200460000000FE6662687868606060F00000000000003C66C2C0C0DEC6C6663A0000000070 37 | :200480000000C6C6C6C6FEC6C6C6C6C60000000000003C18181818181818183C0000000030 38 | :2004A00000001E0C0C0C0C0CCCCCCC78000000000000E666666C78786C6666E600000000DA 39 | :2004C0000000F06060606060606266FE000000000000C3E7FFFFDBC3C3C3C3C300000000D4 40 | :2004E0000000C6E6F6FEDECEC6C6C6C60000000000007CC6C6C6C6C6C6C6C67C0000000070 41 | :200500000000FC6666667C60606060F00000000000007CC6C6C6C6C6C6D6DE7C0C0E000057 42 | :200520000000FC6666667C6C666666E60000000000007CC6C660380C06C6C67C00000000D3 43 | :200540000000FFDB991818181818183C000000000000C6C6C6C6C6C6C6C6C67C00000000EA 44 | :200560000000C3C3C3C3C3C3C3663C18000000000000C3C3C3C3C3DBDBFF6666000000001C 45 | :200580000000C3C3663C18183C66C3C3000000000000C3C3C3663C181818183C0000000054 46 | :2005A0000000FFC3860C183060C1C3FF0000000000003C30303030303030303C00000000C4 47 | :2005C00000000080C0E070381C0E06020000000000003C0C0C0C0C0C0C0C0C3C0000000049 48 | :2005E00010386CC600000000000000000000000000000000000000000000000000FF000082 49 | :20060000303018000000000000000000000000000000000000780C7CCCCCCC760000000088 50 | :200620000000E06060786C666666667C0000000000000000007CC6C0C0C0C67C000000005E 51 | :2006400000001C0C0C3C6CCCCCCCCC760000000000000000007CC6FEC0C0C67C0000000016 52 | :200660000000386C6460F060606060F000000000000000000076CCCCCCCCCC7C0CCC780074 53 | :200680000000E060606C7666666666E60000000000001818003818181818183C000000003E 54 | :2006A00000000606000E06060606060666663C000000E06060666C78786C66E600000000DA 55 | :2006C00000003818181818181818183C000000000000000000E6FFDBDBDBDBDB00000000BA 56 | :2006E0000000000000DC6666666666660000000000000000007CC6C6C6C6C67C00000000E4 57 | :200700000000000000DC66666666667C6060F000000000000076CCCCCCCCCC7C0C0C1E00AF 58 | :200720000000000000DC7666606060F00000000000000000007CC660380CC67C00000000C9 59 | :200740000000103030FC30303030361C000000000000000000CCCCCCCCCCCC7600000000DD 60 | :200760000000000000C3C3C3C3663C18000000000000000000C3C3C3DBDBFF66000000004F 61 | :200780000000000000C3663C183C66C3000000000000000000C6C6C6C6C6C67E060CF8004B 62 | :2007A0000000000000FECC183060C6FE0000000000000E18181870181818180E00000000CF 63 | :2007C000000018181818001818181818000000000000701818180E181818187000000000AB 64 | :2007E000000076DC0000000000000000000000000000000010386CC6C6C6FE0000000000A3 65 | :2008000000003C66C2C0C0C0C2663C0C067C00000000CC0000CCCCCCCCCCCC760000000038 66 | :20082000000C1830007CC6FEC0C0C67C000000000010386C00780C7CCCCCCC7600000000D4 67 | :200840000000CC0000780C7CCCCCCC76000000000060301800780C7CCCCCCC760000000070 68 | :2008600000386C3800780C7CCCCCCC7600000000000000003C666060663C0C063C00000070 69 | :200880000010386C007CC6FEC0C0C67C000000000000C600007CC6FEC0C0C67C00000000DA 70 | :2008A00000603018007CC6FEC0C0C67C0000000000006600003818181818183C000000003C 71 | :2008C00000183C66003818181818183C0000000000603018003818181818183C00000000DE 72 | :2008E00000C60010386CC6C6FEC6C6C600000000386C3800386CC6C6FEC6C6C60000000046 73 | :2009000018306000FE66607C606066FE0000000000000000006E3B1B7ED8DC77000000005E 74 | :2009200000003E6CCCCCFECCCCCCCCCE000000000010386C007CC6C6C6C6C67C00000000EF 75 | :200940000000C600007CC6C6C6C6C67C0000000000603018007CC6C6C6C6C67C000000007D 76 | :20096000003078CC00CCCCCCCCCCCC76000000000060301800CCCCCCCCCCCC7600000000DF 77 | :200980000000C60000C6C6C6C6C6C67E060C780000C6007CC6C6C6C6C6C6C67C00000000BD 78 | :2009A00000C600C6C6C6C6C6C6C6C67C000000000018187EC3C0C0C0C37E181800000000A3 79 | :2009C00000386C6460F060606060E6FC000000000000C3663C18FF18FF1818180000000082 80 | :2009E00000FC66667C62666F666666F300000000000E1B1818187E1818181818D8700000A8 81 | :200A00000018306000780C7CCCCCCC7600000000000C1830003818181818183C0000000014 82 | :200A200000183060007CC6C6C6C6C67C000000000018306000CCCCCCCCCCCC760000000052 83 | :200A4000000076DC00DC6666666666660000000076DC00C6E6F6FEDECEC6C6C60000000014 84 | :200A6000003C6C6C3E007E00000000000000000000386C6C38007C000000000000000000E2 85 | :200A80000000303000303060C0C6C67C00000000000000000000FEC0C0C0C0000000000070 86 | :200AA000000000000000FE06060606000000000000C0C0C2C6CC183060CE9B060C1F00000A 87 | :200AC00000C0C0C2C6CC183066CE963E0606000000001818001818183C3C3C1800000000A2 88 | :200AE0000000000000366CD86C360000000000000000000000D86C366CD80000000000001C 89 | :200B00001144114411441144114411441144114455AA55AA55AA55AA55AA55AA55AA55AA35 90 | :200B2000DD77DD77DD77DD77DD77DD77DD77DD771818181818181818181818181818181895 91 | :200B400018181818181818F818181818181818181818181818F818F81818181818181818F5 92 | :200B600036363636363636F6363636363636363600000000000000FE3636363636363636A7 93 | :200B80000000000000F818F818181818181818183636363636F606F63636363636363636DD 94 | :200BA000363636363636363636363636363636360000000000FE06F636363636363636362B 95 | :200BC0003636363636F606FE000000000000000036363636363636FE000000000000000095 96 | :200BE0001818181818F818F8000000000000000000000000000000F81818181818181818BD 97 | :200C0000181818181818181F000000000000000018181818181818FF000000000000000066 98 | :200C200000000000000000FF1818181818181818181818181818181F18181818181818186E 99 | :200C400000000000000000FF000000000000000018181818181818FF18181818181818182E 100 | :200C600018181818181F181F18181818181818183636363636363637363636363636363685 101 | :200C8000363636363637303F000000000000000000000000003F303736363636363636364A 102 | :200CA0003636363636F700FF00000000000000000000000000FF00F736363636363636368A 103 | :200CC000363636363637303736363636363636360000000000FF00FF0000000000000000BA 104 | :200CE0003636363636F700F736363636363636361818181818FF00FF0000000000000000D2 105 | :200D000036363636363636FF00000000000000000000000000FF00FF18181818181818189C 106 | :200D200000000000000000FF3636363636363636363636363636363F00000000000000004B 107 | :200D400018181818181F181F000000000000000000000000001F181F1818181818181818AF 108 | :200D6000000000000000003F363636363636363636363636363636FF36363636363636365B 109 | :200D80001818181818FF18FF181818181818181818181818181818F8000000000000000065 110 | :200DA000000000000000001F1818181818181818FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF64 111 | :200DC00000000000000000FFFFFFFFFFFFFFFFFFF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01C 112 | :200DE0000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0FFFFFFFFFFFFFFF0000000000000000000A 113 | :200E0000000000000076DCD8D8D8DC7600000000000078CCCCCCD8CCC6C6C6CC0000000008 114 | :200E20000000FEC6C6C0C0C0C0C0C0C00000000000000000FE6C6C6C6C6C6C6C00000000F6 115 | :200E4000000000FEC66030183060C6FE0000000000000000007ED8D8D8D8D87000000000AC 116 | :200E60000000000066666666667C6060C00000000000000076DC1818181818180000000096 117 | :200E80000000007E183C6666663C187E00000000000000386CC6C6FEC6C66C38000000001E 118 | :200EA0000000386CC6C6C66C6C6C6CEE0000000000001E30180C3E666666663C000000001A 119 | :200EC00000000000007EDBDBDB7E00000000000000000003067EDBDBF37E60C000000000B7 120 | :200EE00000001C3060607C606060301C000000000000007CC6C6C6C6C6C6C6C60000000052 121 | :200F000000000000FE0000FE0000FE00000000000000000018187E18180000FF00000000FA 122 | :200F200000000030180C060C1830007E000000000000000C18306030180C007E00000000FF 123 | :200F400000000E1B1B18181818181818181818181818181818181818D8D8D870000000008D 124 | :200F6000000000001818007E0018180000000000000000000076DC0076DC000000000000EF 125 | :200F800000386C6C38000000000000000000000000000000000000181800000000000000D9 126 | :200FA00000000000000000001800000000000000000F0C0C0C0C0CEC6C6C3C1C00000000B2 127 | :200FC00000D86C6C6C6C6C0000000000000000000070D83060C8F800000000000000000085 128 | :200FE000000000007C7C7C7C7C7C7C0000000000000000000000000000000000000000008D 129 | :00000001FF 130 | -------------------------------------------------------------------------------- /vga-small.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 4 | use IEEE.NUMERIC_STD.all; 5 | 6 | entity mod_m_counter is 7 | generic( 8 | N : integer := 7; -- number of bits 9 | M : integer := 80 -- mod-M 10 | ); 11 | port ( 12 | q : out std_logic_vector((N-1) downto 0); 13 | wrap : out std_logic; 14 | clear : in std_logic; 15 | clock : in std_logic); 16 | end mod_m_counter; 17 | 18 | architecture Behav of mod_m_counter is 19 | signal tmp : std_logic_vector((N-1) downto 0) := (others => '0'); 20 | begin 21 | process(clock, clear) 22 | begin 23 | if (rising_edge(clock)) then 24 | if (clear = '1') then 25 | tmp <= (others => '0'); 26 | else 27 | if unsigned(tmp) = M then -- binary 80 28 | tmp <= (others => '0'); -- equivalent to "0000000" 29 | wrap <= '1'; 30 | else 31 | tmp <= std_logic_vector(unsigned(tmp) + 1); 32 | wrap <= '0'; 33 | end if; 34 | end if; 35 | end if; 36 | 37 | end process; 38 | 39 | q <= tmp; 40 | 41 | end Behav; 42 | 43 | --------------------------------------------------------------------------------------- 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 48 | use IEEE.NUMERIC_STD.all; 49 | 50 | entity shiftreg is 51 | generic( 52 | N : integer := 9 -- number of bits 53 | ); 54 | port ( 55 | q : out std_logic; 56 | load : in std_logic; 57 | input : in std_logic_vector((N-1) downto 0); 58 | clock : in std_logic); 59 | end shiftreg; 60 | 61 | architecture Behavioral of shiftreg is 62 | signal latch : std_logic_vector((N-1) downto 0); 63 | signal tmp_out : std_logic; 64 | begin 65 | 66 | process (clock, input, load) 67 | begin 68 | if (rising_edge(clock)) then 69 | if(load = '1') then 70 | latch <= input; 71 | else 72 | latch((N-1) downto 0) <= latch((N-2) downto 0) & '0'; 73 | end if; 74 | end if; 75 | 76 | end process; 77 | 78 | q <= latch(N-1); 79 | 80 | end Behavioral; 81 | 82 | --------------------------------------------------------------------------------------- 83 | 84 | library ieee; 85 | use ieee.std_logic_1164.all; 86 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 87 | use IEEE.NUMERIC_STD.all; 88 | 89 | entity attr_selector is 90 | port ( 91 | input : in std_logic; 92 | outR : out std_logic_vector(3 downto 0); 93 | outG : out std_logic_vector(3 downto 0); 94 | outB : out std_logic_vector(3 downto 0); 95 | disp_enable : in std_logic; 96 | load : in std_logic; 97 | fg : in std_logic_vector(5 downto 0); 98 | bg : in std_logic_vector(5 downto 0); 99 | flashing : in std_logic; 100 | flashclk : in std_logic; 101 | clock : in std_logic 102 | -- blanking : in std_logic 103 | ); 104 | end attr_selector; 105 | 106 | 107 | architecture Behavioral of attr_selector is 108 | signal fg_latch : std_logic_vector(5 downto 0); 109 | signal bg_latch : std_logic_vector(5 downto 0); 110 | signal result : std_logic_vector(5 downto 0); 111 | signal flash_latch : std_logic; 112 | begin 113 | 114 | process (clock, input, load) 115 | begin 116 | if (rising_edge(clock)) then 117 | if(load = '1') then 118 | fg_latch <= fg; 119 | bg_latch <= bg; 120 | flash_latch <= flashing; 121 | end if; 122 | 123 | if (disp_enable = '0') then 124 | result <= "000000"; 125 | else 126 | if (input = '0' or (flashclk and flash_latch) = '1') then 127 | result <= bg_latch; 128 | else 129 | result <= fg_latch; 130 | end if; 131 | end if; 132 | 133 | end if; 134 | 135 | end process; 136 | 137 | outR <= result(5 downto 4) & "00"; 138 | outG <= result(3 downto 2) & "00"; 139 | outB <= result(1 downto 0) & "00"; 140 | 141 | end Behavioral; 142 | -------------------------------------------------------------------------------- /vga_textmode.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 4 | use IEEE.NUMERIC_STD.all; 5 | 6 | entity vga_textmode is 7 | port( 8 | n_reset : in std_logic; 9 | pixelClk : in std_logic; -- pixel clock (50MHz) 10 | 11 | disp_enable : in std_logic; 12 | column : in std_logic_vector(9 downto 0); 13 | row : in std_logic_vector(9 downto 0); 14 | 15 | frame_start : in std_logic; 16 | row_start : in std_logic; 17 | 18 | display_mem_addr : out std_logic_vector(11 downto 0); 19 | display_mem_data : in std_logic_vector(7 downto 0); 20 | 21 | videoR : out std_logic_vector(3 downto 0); 22 | videoG : out std_logic_vector(3 downto 0); 23 | videoB : out std_logic_vector(3 downto 0) 24 | ); 25 | end vga_textmode; 26 | 27 | architecture vga_textmode_arch of vga_textmode is 28 | signal ch_row : std_logic_vector(7 downto 0) := "00000000"; 29 | signal ch_col : std_logic_vector(6 downto 0) := "0000000"; 30 | 31 | signal glyph_row : std_logic_vector(3 downto 0) := "0000"; 32 | 33 | signal ch_clock : std_logic := '0'; 34 | signal char_address : std_logic_vector(11 downto 0) := "000000000000"; 35 | signal chardata_row : std_logic_vector(7 downto 0) := "00110011"; 36 | 37 | -- signal shifter : std_logic_vector(8 downto 0) := "001010101"; 38 | signal shift_load : std_logic := '0'; 39 | 40 | signal flash_flag : std_logic := '0'; 41 | signal cursor_flash_flag : std_logic := '0'; 42 | signal jiffy_counter : integer := 0; 43 | 44 | signal chr : std_logic_vector(7 downto 0) := X"00"; 45 | 46 | signal pix_counter : std_logic_vector(3 downto 0) := "0000"; 47 | signal pix_clear : std_logic := '0'; 48 | signal pix_wrap : std_logic := '0'; 49 | 50 | signal line_wrap : std_logic := '0'; 51 | 52 | signal displayClock : std_logic; 53 | 54 | -- signal v_row : std_logic_vector(9 downto 0); 55 | -- signal v_col : std_logic_vector(9 downto 0); 56 | 57 | signal pixel : std_logic := '0'; 58 | 59 | signal attr_fg : std_logic_vector(3 downto 0) := "1111"; 60 | signal attr_bg : std_logic_vector(3 downto 0) := "0000"; -- high bit will always be 0 (only 3 stored in display attr byte) 61 | signal attr_flash : std_logic := '0'; 62 | 63 | signal next_attr_fg : std_logic_vector(3 downto 0) := "1111"; 64 | signal next_attr_bg : std_logic_vector(3 downto 0) := "0000"; -- high bit will always be 0 (only 3 stored in display attr byte) 65 | signal next_attr_flash : std_logic := '0'; 66 | 67 | signal selector_bg_in : std_logic_vector(5 downto 0); 68 | signal selector_fg_in : std_logic_vector(5 downto 0); 69 | 70 | signal display_mem_addr_tmp : std_logic_vector(15 downto 0); 71 | 72 | signal dispram_attrbyte : std_logic_vector(7 downto 0); 73 | signal dispram_codepoint : std_logic_vector(7 downto 0); 74 | 75 | signal character_extend : std_logic; 76 | 77 | begin 78 | 79 | font_rom_inst : entity work.font_rom 80 | port map( 81 | clock => pixelClk, 82 | address => char_address, 83 | q => chardata_row 84 | ); 85 | 86 | pixcounter_inst : entity work.mod_m_counter 87 | generic map(N => 4, M => 8) 88 | port map( 89 | clock => pixelClk, 90 | clear => pix_clear, 91 | wrap => pix_wrap, 92 | q => pix_counter 93 | ); 94 | 95 | chcounter_inst : entity work.mod_m_counter 96 | generic map(N => 7, M => 80) 97 | port map( 98 | clock => pix_wrap or row_start, 99 | clear => pix_clear, 100 | q => ch_col, 101 | wrap => line_wrap 102 | ); 103 | 104 | shifter_inst : entity work.shiftreg 105 | port map( 106 | clock => pixelClk, 107 | load => shift_load, 108 | input => chardata_row & (character_extend and chardata_row(0)), 109 | q => pixel 110 | ); 111 | 112 | palette_selector_inst : entity work.attr_selector 113 | port map( 114 | fg => selector_fg_in, 115 | bg => selector_bg_in, 116 | flashing => next_attr_flash, 117 | clock => pixelClk, 118 | flashclk => flash_flag, 119 | load => shift_load, 120 | disp_enable => disp_enable, 121 | outR => videoR, 122 | outG => videoG, 123 | outB => videoB, 124 | input => pixel 125 | ); 126 | 127 | fg_palette_inst : entity work.COLOUR_ROM 128 | port map( 129 | A => next_attr_fg, 130 | D => selector_fg_in 131 | ); 132 | 133 | 134 | bg_palette_inst : entity work.COLOUR_ROM 135 | port map( 136 | A => next_attr_bg, 137 | D => selector_bg_in 138 | ); 139 | 140 | displayClock <= pixelClk and disp_enable; 141 | 142 | chr <= dispram_codepoint(7 downto 0); 143 | 144 | -- decide whether column 9 is blank, or extended from column 8 145 | character_extend <= '1' when chr(7 downto 4) = "1011" else 146 | '1' when chr(7 downto 4) = "1101" else 147 | '1' when chr(7 downto 4) = "1100" else 148 | '0'; 149 | 150 | next_attr_fg <= dispram_attrbyte(3 downto 0); 151 | next_attr_bg <= '0' & dispram_attrbyte(6 downto 4); 152 | next_attr_flash <= dispram_attrbyte(7); 153 | 154 | -- fetch the relevant row of font data 155 | char_address <= chr & glyph_row; 156 | -- ch_clock <= pix_counter(2); -- clocks every 4 pixels, sort of... 157 | pix_clear <= frame_start or row_start; 158 | 159 | -- display_mem_addr <= ch_row(4 downto 0) & ch_col(5 downto 0); 160 | display_mem_addr_tmp <= std_logic_vector(unsigned(ch_row) * 80 + unsigned(ch_col)); 161 | 162 | -- set up the row signals at the start of each row 163 | process (row_start) 164 | begin 165 | if (rising_edge(row_start)) then 166 | ch_row(5 downto 0) <= row(9 downto 4); 167 | glyph_row(3 downto 0) <= row(3 downto 0); 168 | end if; 169 | end process; 170 | 171 | -- load the shifter at the start of the new character 172 | process (pix_counter, pixelClk) 173 | begin 174 | if (pix_counter = "0000") then 175 | shift_load <= '1'; 176 | else 177 | shift_load <= '0'; 178 | end if; 179 | 180 | -- fetch the character 181 | if (pix_counter = "0001") then 182 | display_mem_addr <= display_mem_addr_tmp(10 downto 0) & '0'; 183 | end if; 184 | 185 | if (pix_counter = "0010") then 186 | dispram_codepoint <= display_mem_data; 187 | end if; 188 | 189 | -- fetch the attributes 190 | if (pix_counter = "0011") then 191 | display_mem_addr <= display_mem_addr_tmp(10 downto 0) & '1'; 192 | end if; 193 | 194 | if (pix_counter = "0100") then 195 | dispram_attrbyte <= display_mem_data; 196 | end if; 197 | 198 | end process; 199 | 200 | process(frame_start) 201 | begin 202 | if(rising_edge(frame_start)) then 203 | 204 | jiffy_counter <= jiffy_counter + 1; 205 | 206 | if (jiffy_counter mod 32 = 0) then 207 | flash_flag <= not flash_flag; 208 | end if; 209 | 210 | if (jiffy_counter mod 24 = 0) then 211 | cursor_flash_flag <= not cursor_flash_flag; 212 | end if; 213 | 214 | end if; 215 | end process; 216 | 217 | end vga_textmode_arch; 218 | -------------------------------------------------------------------------------- /vt100.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 08:49:40 September 11, 2015 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "08:49:40 September 11, 2015" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "vt100" 31 | -------------------------------------------------------------------------------- /vt100.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 22:17:10 August 05, 2015 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # vt100_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone II" 40 | set_global_assignment -name DEVICE EP2C5T144C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY vt100 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:17:10 AUGUST 05, 2015" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | 49 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" 50 | set_global_assignment -name SMART_RECOMPILE ON 51 | set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON 52 | set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON 53 | set_global_assignment -name VHDL_FILE ps2_keyboard.vhd 54 | set_global_assignment -name VHDL_FILE debounce.vhd 55 | set_global_assignment -name VHDL_FILE sram.vhd 56 | set_global_assignment -name VHDL_FILE font_rom.vhd 57 | set_global_assignment -name VHDL_FILE displayram.vhd 58 | set_global_assignment -name VHDL_FILE bootrom.vhd 59 | set_global_assignment -name VHDL_FILE components/T16450.vhd 60 | set_global_assignment -name VHDL_FILE components/T80s.vhd 61 | set_global_assignment -name VHDL_FILE components/T80a.vhd 62 | set_global_assignment -name VHDL_FILE components/T80_Reg.vhd 63 | set_global_assignment -name VHDL_FILE components/T80_Pack.vhd 64 | set_global_assignment -name VHDL_FILE components/T80_MCode.vhd 65 | set_global_assignment -name VHDL_FILE components/T80_ALU.vhd 66 | set_global_assignment -name VHDL_FILE components/T80.vhd 67 | set_global_assignment -name HEX_FILE "VGA-ROM-8x16.hex" 68 | set_global_assignment -name VHDL_FILE "vga-controller.vhd" 69 | set_global_assignment -name VHDL_FILE "colour-rom.vhd" 70 | set_global_assignment -name VHDL_FILE simulation/modelsim/testbench.vhd 71 | set_global_assignment -name VHDL_FILE vt100.vhd 72 | set_global_assignment -name VHDL_FILE simulation/modelsim/vga_testbench.vhd 73 | set_global_assignment -name VHDL_FILE vga_textmode.vhd 74 | set_global_assignment -name QIP_FILE font_rom.qip 75 | set_global_assignment -name VHDL_FILE simulation/modelsim/vga_gfx_testbench.vhd 76 | set_global_assignment -name VHDL_FILE "vga-small.vhd" 77 | set_global_assignment -name QIP_FILE displayram.qip 78 | set_global_assignment -name QIP_FILE bootrom.qip 79 | set_global_assignment -name QIP_FILE sram.qip 80 | set_global_assignment -name SDC_FILE vt100.sdc 81 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 82 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 83 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 84 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 85 | set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 86 | set_location_assignment PIN_31 -to blinkenlight[0] 87 | set_location_assignment PIN_25 -to blinkenlight[1] 88 | set_location_assignment PIN_30 -to blinkenlight[2] 89 | set_location_assignment PIN_28 -to blinkenlight[3] 90 | set_location_assignment PIN_24 -to blinkenlight[4] 91 | set_location_assignment PIN_32 -to blinkenlight[5] 92 | 93 | set_location_assignment PIN_112 -to hSync 94 | set_location_assignment PIN_113 -to vSync 95 | 96 | set_location_assignment PIN_126 -to videoR[0] 97 | set_location_assignment PIN_132 -to videoR[1] 98 | set_location_assignment PIN_134 -to videoR[2] 99 | set_location_assignment PIN_136 -to videoR[3] 100 | 101 | set_location_assignment PIN_125 -to videoG[0] 102 | set_location_assignment PIN_121 -to videoG[1] 103 | set_location_assignment PIN_119 -to videoG[2] 104 | set_location_assignment PIN_115 -to videoG[3] 105 | 106 | set_location_assignment PIN_122 -to videoB[0] 107 | set_location_assignment PIN_120 -to videoB[1] 108 | set_location_assignment PIN_118 -to videoB[2] 109 | set_location_assignment PIN_114 -to videoB[3] 110 | 111 | set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE 112 | 113 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /vt100.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 20.000 2 | create_generated_clock -name cpuClock -source clk 3 | create_generated_clock -name row_start -source clk 4 | create_generated_clock -name frame_start -source clk 5 | 6 | -------------------------------------------------------------------------------- /vt100.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | -- use IEEE.STD_LOGIC_ARITH.all; 4 | -- use IEEE.STD_LOGIC_UNSIGNED.all; 5 | use IEEE.NUMERIC_STD.all; 6 | 7 | 8 | 9 | entity vt100 is 10 | port( 11 | Reset_n : in std_logic; 12 | clk : in std_logic; 13 | 14 | junkBuzzer : out std_logic; 15 | 16 | videoR : out std_logic_vector(3 downto 0); 17 | videoG : out std_logic_vector(3 downto 0); 18 | videoB : out std_logic_vector(3 downto 0); 19 | hSync : out std_logic; 20 | vSync : out std_logic; 21 | 22 | blinkenlight : out std_logic_vector(5 downto 0); 23 | 24 | NMI_n : in std_logic; 25 | 26 | RXD0 : in std_logic; 27 | CTS0 : in std_logic; 28 | DSR0 : in std_logic; 29 | RI0 : in std_logic; 30 | DCD0 : in std_logic; 31 | TXD0 : out std_logic; 32 | RTS0 : out std_logic; 33 | DTR0 : out std_logic; 34 | 35 | ps2Clk : inout std_logic; 36 | ps2Data : inout std_logic 37 | ); 38 | end vt100; 39 | 40 | 41 | architecture struct of vt100 is 42 | signal pixelClk : std_logic; 43 | signal row : unsigned(9 downto 0); 44 | signal col : unsigned(9 downto 0); 45 | signal display_enable : std_logic; 46 | signal frame_start : std_logic; 47 | signal row_start : std_logic; 48 | 49 | signal dispram_addr_b : std_logic_vector(11 downto 0) := "000000000000"; 50 | signal dispram_output_b : std_logic_vector(7 downto 0); 51 | 52 | signal serialClkCount : unsigned(15 downto 0); 53 | signal cpuClkCount : unsigned(7 downto 0); 54 | signal cpuClock : std_logic; 55 | signal serialClock : std_logic; 56 | signal kbdClock : std_logic; 57 | signal kbdClkCount : unsigned(11 downto 0); 58 | 59 | signal M1_n : std_logic; 60 | signal MREQ_n : std_logic; 61 | signal IORQ_n : std_logic; 62 | signal RD_n : std_logic; 63 | signal WR_n : std_logic; 64 | signal RFSH_n : std_logic; 65 | signal HALT_n : std_logic; 66 | signal WAIT_n : std_logic; 67 | signal INT_n : std_logic; 68 | signal RESET_s : std_logic; 69 | signal BUSRQ_n : std_logic; 70 | signal BUSAK_n : std_logic; 71 | signal A : std_logic_vector(15 downto 0); 72 | signal D : std_logic_vector(7 downto 0); 73 | signal ROM_D : std_logic_vector(7 downto 0); 74 | signal SRAM_D : std_logic_vector(7 downto 0); 75 | signal UART0_D : std_logic_vector(7 downto 0); 76 | signal UART1_D : std_logic_vector(7 downto 0); 77 | signal CPU_D : std_logic_vector(7 downto 0); 78 | 79 | signal DISPRAM_D : std_logic_vector(7 downto 0); 80 | signal BLINKEN_D : std_logic_vector(7 downto 0); 81 | 82 | 83 | signal Mirror : std_logic; 84 | 85 | signal IOWR_n : std_logic; 86 | signal RAMCS_n : std_logic; 87 | signal ROMCS_n : std_logic; 88 | signal DISPRAMCS_n : std_logic; 89 | 90 | signal UART0CS_n : std_logic; 91 | signal UART1CS_n : std_logic; 92 | signal BLINKCS_n : std_logic; 93 | 94 | signal BaudOut0 : std_logic; 95 | signal BaudOut1 : std_logic; 96 | 97 | signal PS2NewDataFlag : std_logic; 98 | signal PS2Character : std_logic_vector(7 downto 0); 99 | 100 | begin 101 | 102 | pixelClk <= clk; 103 | 104 | 105 | Wait_n <= '1'; 106 | BusRq_n <= '1'; 107 | INT_n <= '1'; 108 | 109 | process (Reset_n, cpuClock) 110 | begin 111 | if Reset_n = '0' then 112 | Reset_s <= '0'; 113 | --Mirror <= '0'; 114 | elsif cpuClock'event and cpuClock = '1' then 115 | Reset_s <= '1'; 116 | --if IORQ_n = '0' and A(7 downto 4) = "1111" then 117 | -- Mirror <= D(0); 118 | --end if; 119 | end if; 120 | end process; 121 | 122 | process (Clk) 123 | begin 124 | if(rising_edge(Clk)) then 125 | 126 | if cpuClkCount < 20 then 127 | cpuClkCount <= cpuClkCount + 1; 128 | else 129 | cpuClkCount <= (others => '0'); 130 | end if; 131 | 132 | if cpuClkCount < 10 then 133 | cpuClock <= '1'; 134 | else 135 | cpuClock <= '0'; 136 | end if; 137 | 138 | -- 1.8432 MHz clock (ish) from 50 MHz 139 | if (serialClkCount < 271) then 140 | serialClkCount <= serialClkCount + 1; 141 | else 142 | serialClkCount <= (others => '0'); 143 | end if; 144 | 145 | if (serialClkCount < 135) then 146 | serialClock <= '1'; 147 | else 148 | serialClock <= '0'; 149 | end if; 150 | 151 | end if; 152 | end process; 153 | 154 | -- Memory decoding 155 | IOWR_n <= WR_n or IORQ_n; 156 | 157 | -- 1K RAM at 8000-83FF 158 | RAMCS_n <= '0' when A(15 downto 10) = "100000" and MREQ_n = '0' else '1'; 159 | -- 4K display ram at F000-FFFF 160 | DISPRAMCS_n <= '0' when A(15 downto 12) = "1111" and MREQ_n = '0' else '1'; 161 | -- 4K ROM at anywhere else (but mainly 0000-0fff) 162 | ROMCS_n <= '0' when RAMCS_n = '1' and DISPRAMCS_n = '1' and MREQ_n = '0' else '1'; 163 | 164 | -- I/O Decoding - port 00-07 and 08-15 are UARTS, port 255 is the blinkenlights 165 | BLINKCS_n <= '0' when IORQ_n = '0' and A(7 downto 0) = "11111111" else '1'; 166 | UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1'; 167 | UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00001" else '1'; 168 | 169 | -- data bus selection 170 | CPU_D <= 171 | SRAM_D when RAMCS_n = '0' else 172 | DISPRAM_D when DISPRAMCS_n = '0' else 173 | UART0_D when UART0CS_n = '0' else 174 | UART1_D when UART1CS_n = '0' else 175 | BLINKEN_D when BLINKCS_n = '0' else 176 | ROM_D; 177 | 178 | ps2kbd: entity work.ps2_keyboard 179 | port map( 180 | clk => clk, 181 | ps2_clk => PS2Clk, 182 | ps2_data => PS2Data, 183 | ps2_code_new => PS2NewDataFlag, 184 | ps2_code => PS2Character 185 | ); 186 | 187 | vgactrl1 : entity work.vga_controller 188 | port map( 189 | n_reset => Reset_n, 190 | pixelClk => pixelClk, 191 | hSync => hSync, 192 | vSync => vSync, 193 | frame_start => frame_start, 194 | row_start => row_start, 195 | disp_enable => display_enable, 196 | row => row, 197 | column => col 198 | ); 199 | 200 | vgagfx1 : entity work.vga_textmode 201 | port map( 202 | n_reset => Reset_n, 203 | pixelClk => pixelClk, 204 | row => std_logic_vector(row), 205 | column => std_logic_vector(col), 206 | disp_enable => display_enable, 207 | frame_start => frame_start, 208 | row_start => row_start, 209 | display_mem_addr => dispram_addr_b, 210 | display_mem_data => dispram_output_b, 211 | videoR => videoR, 212 | videoG => videoG, 213 | videoB => videoB 214 | ); 215 | 216 | displaymem : entity work.displayram 217 | port map ( 218 | -- clock_a => cpuClock, 219 | -- address_a => A(11 downto 0), 220 | clock_a => cpuClock, 221 | address_a => A(11 downto 0), 222 | q_a => DISPRAM_D, 223 | data_a => D, 224 | enable_a => not DISPRAMCS_n, 225 | wren_a => not (WR_n or DISPRAMCS_n), 226 | 227 | enable_b => '1', 228 | clock_b => pixelClk, 229 | address_b => dispram_addr_b, 230 | q_b => dispram_output_b, 231 | data_b => "00000000" 232 | ); 233 | 234 | cpu0 : entity work.T80s 235 | generic map(Mode => 1, T2Write => 1, IOWait => 0) 236 | port map( 237 | RESET_n => RESET_s, 238 | CLK_n => cpuClock, 239 | WAIT_n => WAIT_n, 240 | INT_n => INT_n, 241 | NMI_n => NMI_n, 242 | BUSRQ_n => BUSRQ_n, 243 | M1_n => M1_n, 244 | MREQ_n => MREQ_n, 245 | IORQ_n => IORQ_n, 246 | RD_n => RD_n, 247 | WR_n => WR_n, 248 | RFSH_n => RFSH_n, 249 | HALT_n => HALT_n, 250 | BUSAK_n => BUSAK_n, 251 | A => A, 252 | DI => CPU_D, 253 | DO => D); 254 | 255 | uart0 : entity work.T16450 256 | port map( 257 | MR_n => Reset_s, 258 | XIn => Clk, 259 | RClk => BaudOut0, 260 | CS_n => UART0CS_n, 261 | Rd_n => RD_n, 262 | Wr_n => IOWR_n, 263 | A => A(2 downto 0), 264 | D_In => D, 265 | D_Out => UART0_D, 266 | SIn => RXD0, 267 | CTS_n => CTS0, 268 | DSR_n => DSR0, 269 | RI_n => RI0, 270 | DCD_n => DCD0, 271 | SOut => TXD0, 272 | RTS_n => RTS0, 273 | DTR_n => DTR0, 274 | OUT1_n => open, 275 | OUT2_n => open, 276 | BaudOut => BaudOut0, 277 | Intr => open); 278 | 279 | rom0 : entity work.bootrom 280 | port map ( 281 | address => A(11 downto 0), 282 | clock => cpuClock, 283 | q => ROM_D 284 | ); 285 | 286 | sram0 : entity work.sram 287 | port map ( 288 | -- missing RAMCS_n 289 | -- clken => not RAMCS_n, 290 | address => A(9 downto 0), 291 | clock => cpuClock, 292 | data => D, 293 | q => SRAM_D, 294 | wren => not (WR_n or RAMCS_n) 295 | ); 296 | 297 | -- Allow Z80 to update LED states - only 6 of the 8 bits are wired to LEDs though 298 | process(cpuClkCount, reset_n) 299 | begin 300 | if (reset_n = '0') then 301 | BLINKEN_D <= "00000000"; 302 | elsif (rising_edge(cpuClock)) then 303 | if BLINKCS_n = '0' and WR_n = '0' then 304 | BLINKEN_D <= D; 305 | end if; 306 | end if; 307 | end process; 308 | 309 | 310 | junkBuzzer <= '1'; 311 | 312 | blinkenlight(0) <= not BLINKEN_D(0); 313 | blinkenlight(1) <= not BLINKEN_D(1); 314 | blinkenlight(2) <= not BLINKEN_D(2); 315 | blinkenlight(3) <= not BLINKEN_D(3); 316 | blinkenlight(4) <= not BLINKEN_D(4); 317 | blinkenlight(5) <= not BLINKEN_D(5); 318 | 319 | end; 320 | 321 | --------------------------------------------------------------------------------