├── resource ├── cloud.bmp ├── font.bmp ├── map.tbl ├── mario.bmp ├── music.mid ├── objs.bmp ├── athletic.mid ├── bg_sprites.bmp ├── frequency.lst ├── midi_note.dat ├── platforms.bmp ├── water_melody.timing ├── super_mario_world.png ├── SNES - Super Mario World - Tileset.png ├── font.hex.v ├── bg_rom.hex.v ├── mario.hex.v ├── cloud_bg.hex.v ├── platform.hex.v ├── platforms.hex.v ├── hello.hex ├── music_process.py ├── img_process.py ├── platform.hex └── platforms.hex ├── README.md └── src ├── bg_rom.hex.v ├── mario.hex.v ├── cloud_bg.hex.v ├── splash.bin ├── display.v ├── seg_mux.v ├── bcd_7seg.v ├── vga_num.v ├── background_engine.v ├── game_over_text.v ├── object_engine.v ├── clock_div.v ├── vga_sync.v ├── ram.v ├── flapga_mario.v ├── mario.v ├── vga_cons.xdc ├── text.v ├── game_engine.v └── audio_unit.v /resource/cloud.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/cloud.bmp -------------------------------------------------------------------------------- /resource/font.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/font.bmp -------------------------------------------------------------------------------- /resource/map.tbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/map.tbl -------------------------------------------------------------------------------- /resource/mario.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/mario.bmp -------------------------------------------------------------------------------- /resource/music.mid: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/music.mid -------------------------------------------------------------------------------- /resource/objs.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/objs.bmp -------------------------------------------------------------------------------- /resource/athletic.mid: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/athletic.mid -------------------------------------------------------------------------------- /resource/bg_sprites.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/bg_sprites.bmp -------------------------------------------------------------------------------- /resource/frequency.lst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/frequency.lst -------------------------------------------------------------------------------- /resource/midi_note.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/midi_note.dat -------------------------------------------------------------------------------- /resource/platforms.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/platforms.bmp -------------------------------------------------------------------------------- /resource/water_melody.timing: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/water_melody.timing -------------------------------------------------------------------------------- /resource/super_mario_world.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/super_mario_world.png -------------------------------------------------------------------------------- /resource/SNES - Super Mario World - Tileset.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/howardlau1999/flapga-mario/HEAD/resource/SNES - Super Mario World - Tileset.png -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FlaPGA Mario 2 | 3 | This is a flappy-bird like video game written in Verilog for Basys 3. This project was also submitted as a school project in my freshmen year. The report is available here: [FlaPGA_Mario.pdf](https://howardlau.me/wp-content/uploads/2018/11/FlapPGA_Mario.pdf) 4 | 5 | 中文博客介绍：[FlapPGA Mario - 用 FPGA 编写游戏](https://howardlau.me/projects/flappga-mario-a-video-game-in-fpga.html) 6 | 7 | # Demo 8 | 9 | You can watch the demo here: [https://www.youtube.com/watch?v=SdphC7bAz7M](https://www.youtube.com/watch?v=SdphC7bAz7M) 10 | 11 | -------------------------------------------------------------------------------- /resource/font.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module font_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 12; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [5:0] x; 11 | input wire [5:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("font.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /src/bg_rom.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module bg_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 14; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [6:0] x; 11 | input wire [6:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("bg_rom.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /src/mario.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module mario_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 12; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [5:0] x; 11 | input wire [5:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("mario.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /resource/bg_rom.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module bg_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 14; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [6:0] x; 11 | input wire [6:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("bg_rom.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /resource/mario.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module mario_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 12; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [5:0] x; 11 | input wire [5:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("mario.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /src/cloud_bg.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module cloud_bg(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 16; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [7:0] x; 11 | input wire [7:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("cloud_bg.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /resource/cloud_bg.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module cloud_bg(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 16; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [7:0] x; 11 | input wire [7:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("cloud_bg.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /resource/platform.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module platform_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 11; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [5:0] x; 11 | input wire [4:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("platform.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /resource/platforms.hex.v: -------------------------------------------------------------------------------- 1 | 2 | module platform_rom(clk, video_on, x, y, color); 3 | parameter ROM_WIDTH = 12; 4 | parameter ROM_ADDR_BITS = 11; 5 | 6 | (* rom_style="block" *) 7 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 8 | input wire clk; 9 | input wire video_on; 10 | input wire [5:0] x; 11 | input wire [4:0] y; 12 | reg [ROM_ADDR_BITS-1:0] address; 13 | output reg [ROM_WIDTH-1:0] color; 14 | 15 | initial 16 | $readmemh("platforms.hex", rom); 17 | 18 | always @(posedge clk) 19 | if (video_on) begin 20 | address <= {y, x}; 21 | color <= rom[address]; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /src/splash.bin: -------------------------------------------------------------------------------- 1 | @23b 2 | 11a 3 | @23c 4 | 10e 5 | @23d 6 | 10a 7 | @23e 8 | 10d 9 | @23f 10 | 121 11 | @240 12 | 125 13 | @241 14 | 118 15 | @242 16 | 114 17 | @243 18 | 10a 19 | @244 20 | 121 21 | @245 22 | 10e 23 | @246 24 | 11a 25 | @247 26 | 125 27 | @248 28 | 117 29 | @249 30 | 116 31 | @24a 32 | 10e 33 | @1ed 34 | 10f 35 | @1ee 36 | 114 37 | @1ef 38 | 10a 39 | @1f0 40 | 118 41 | @1f1 42 | 126 43 | @1f2 44 | 10a 45 | @1f3 46 | 125 47 | @1f4 48 | 115 49 | @1f5 50 | 10a 51 | @1f6 52 | 11a 53 | @1f7 54 | 111 55 | @1f8 56 | 117 57 | @3f1 58 | 118 59 | @3f2 60 | 11a 61 | @3f3 62 | 117 63 | @3f4 64 | 126 65 | @3f5 66 | 11a 67 | @3f6 68 | 10a 69 | @3f7 70 | 115 71 | @3f8 72 | 125 73 | @3f9 74 | 10b 75 | @3fa 76 | 121 77 | @3fb 78 | 125 79 | @3fc 80 | 110 81 | @3fd 82 | 117 83 | @3fe 84 | 11f 85 | @3ff 86 | 10a 87 | @400 88 | 11a 89 | @401 90 | 10d 91 | @402 92 | 125 93 | @403 94 | 114 95 | @404 96 | 10a 97 | @405 98 | 11d 99 | -------------------------------------------------------------------------------- /src/display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05/19/2018 02:04:57 PM 7 | // Design Name: 8 | // Module Name: display 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module display( 24 | output wire [6:0] seg, 25 | output wire [3:0] ano, 26 | input wire [15:0] nums, 27 | input wire basys3_clk 28 | ); 29 | wire [1:0] s; 30 | wire clk; 31 | clock_div clock_div(.clk(basys3_clk), .clr(0), .out_clk(clk), .s(s)); 32 | seg_mux seg_mux(.s(s), .seg(seg), .ano(ano), .nums(nums)); 33 | endmodule 34 | -------------------------------------------------------------------------------- /resource/hello.hex: -------------------------------------------------------------------------------- 1 | 1_111111111111_000_100_0000000000_0000000000 2 | 1_111111111111_101_011_0000000000_0000001000 3 | 1_111111111111_100_100_0000000000_0000010000 4 | 1_111111111111_100_100_0000000000_0000011000 5 | 1_111111111111_111_100_0000000000_0000100000 6 | 1_111111111111_000_000_0000000000_0000101000 7 | 1_111111111111_111_101_0000000000_0000110000 8 | 1_111111111111_111_100_0000000000_0000111000 9 | 1_111111111111_010_101_0000000000_0001000000 10 | 1_111111111111_100_100_0000000000_0001001000 11 | 1_111111111111_100_011_0000000000_0001010000 12 | 1_111111111111_001_000_0000000000_0001100000 13 | 14 | 1_000011111111_100_100_0000001000_0000000000 15 | 1_000011111111_001_100_0000001000_0000001000 16 | 1_000011111111_101_101_0000001000_0000010000 17 | 1_000011001100_000_100_0000001000_0000011000 18 | 1_000011001100_001_011_0000001000_0000100000 19 | 1_000011001100_111_100_0000001000_0000101000 20 | 1_000000110011_000_100_0000001000_0000110000 21 | 1_000000110011_101_101_0000001000_0000111000 22 | 1_000000110011_001_011_0000001000_0001000000 -------------------------------------------------------------------------------- /src/seg_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05/19/2018 09:21:40 PM 7 | // Design Name: 8 | // Module Name: seg_mux 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module seg_mux( 24 | input wire [1:0] s, 25 | input wire [15:0] nums, 26 | output wire [6:0] seg, 27 | output wire [3:0] ano 28 | ); 29 | reg [3:0] digit; 30 | always @ (*) 31 | begin 32 | case(s) 33 | 2'b00: 34 | digit = nums[3:0]; 35 | 2'b01: 36 | digit = nums[7:4]; 37 | 2'b10: 38 | digit = nums[11:8]; 39 | 2'b11: 40 | digit = nums[15:12]; 41 | default: digit = nums[3:0]; 42 | endcase 43 | end 44 | assign ano[0] = s[0] | s[1]; 45 | assign ano[1] = ~s[0] | s[1]; 46 | assign ano[2] = s[0] | ~s[1]; 47 | assign ano[3] = ~(s[0] & s[1]); 48 | bcd_7seg_anode bcd_7seg(.seg(seg), .bcd(digit)); 49 | endmodule 50 | -------------------------------------------------------------------------------- /src/bcd_7seg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05/19/2018 02:05:29 PM 7 | // Design Name: 8 | // Module Name: bcd_7seg 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module bcd_7seg_anode( 24 | input wire [3:0] bcd, 25 | output reg [6:0] seg 26 | ); 27 | always @ (*) begin 28 | case (bcd) 29 | 0: seg = 7'b0000001; 30 | 1: seg = 7'b1001111; 31 | 2: seg = 7'b0010010; 32 | 3: seg = 7'b0000110; 33 | 4: seg = 7'b1001100; 34 | 5: seg = 7'b0100100; 35 | 6: seg = 7'b0100000; 36 | 7: seg = 7'b0001111; 37 | 8: seg = 7'b0000000; 38 | 9: seg = 7'b0000100; 39 | 10: seg = 7'b0001000; 40 | 11: seg = 7'b1100000; 41 | 12: seg = 7'b1110010; 42 | 13: seg = 7'b1000010; 43 | 14: seg = 7'b0110000; 44 | 15: seg = 7'b0111000; 45 | endcase 46 | end 47 | endmodule 48 | -------------------------------------------------------------------------------- /src/vga_num.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05/25/2018 07:25:03 PM 7 | // Design Name: 8 | // Module Name: vga_clock 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module vga_num( 24 | input wire clk, 25 | input wire enable, 26 | input wire [15:0] nums, 27 | output wire [15:0] addr, 28 | output wire [15:0] dina 29 | ); 30 | 31 | reg [3:0] num; 32 | wire [2:0] num_row, num_col; 33 | reg [2:0] writing_digit; 34 | reg [2:0] writing_digit_next; 35 | 36 | always @ (posedge clk) 37 | begin 38 | if (enable) begin 39 | case (writing_digit_next) 40 | 3'b000: num <= (nums / 1000) % 10; 41 | 3'b001: num <= (nums / 100) % 10; 42 | 3'b010: num <= (nums / 10) % 10; 43 | 3'b011: num <= nums % 10; 44 | endcase 45 | 46 | writing_digit <= writing_digit_next; 47 | if (writing_digit == 3) 48 | writing_digit_next <= 0; 49 | else 50 | writing_digit_next <= writing_digit + 1; 51 | end 52 | end 53 | 54 | assign num_col = num % 8; 55 | assign num_row = num / 8; 56 | assign dina = {3'b100, num_row, num_col}; 57 | assign addr = writing_digit + 17; 58 | 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /src/background_engine.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | module background_engine( 4 | input wire clk, 5 | input wire video_on, 6 | input wire [3:0] x_offset, 7 | input wire [9:0] x, y, 8 | input wire [15:0] ram_data, 9 | output reg [15:0] ram_addr, 10 | output wire pixel_on, 11 | output wire [11:0] color 12 | ); 13 | reg [13:0] rom_addr; 14 | reg [6:0] rom_x, rom_y; 15 | wire [11:0] rom_data; 16 | parameter TILE_WIDTH = 16; 17 | parameter TILE_HEIGHT = 16; 18 | parameter TILE_COLS = 640 / TILE_WIDTH; 19 | parameter TILE_ROWS = 480 / TILE_HEIGHT; 20 | 21 | `define TILE_COL ram_data[2:0] 22 | `define TILE_ROW ram_data[5:3] 23 | `define X_FILP ram_data[6:6] 24 | `define Y_FLIP ram_data[7:7] 25 | `define ENABLE ram_data[8:8] 26 | `define POS_X ((x + x_offset) / TILE_WIDTH) 27 | `define POS_Y (y / TILE_HEIGHT) 28 | 29 | bg_rom bg_rom(.clk(clk), .video_on(video_on), .x(rom_x), .y(rom_y), .color(rom_data)); 30 | 31 | always @ * begin 32 | ram_addr = `POS_X + `POS_Y * TILE_COLS; 33 | if (`X_FILP == 0) 34 | rom_x = `TILE_COL * TILE_WIDTH + ((x + x_offset) % TILE_WIDTH); 35 | else 36 | rom_x = `TILE_COL * TILE_WIDTH + (TILE_WIDTH - 1 - ((x + x_offset) % TILE_WIDTH)); 37 | 38 | if (`Y_FLIP == 0) 39 | rom_y = `TILE_ROW * TILE_HEIGHT + (y % TILE_HEIGHT); 40 | else 41 | rom_y = `TILE_ROW * TILE_HEIGHT + TILE_HEIGHT - 1 - (y % TILE_HEIGHT); 42 | end 43 | 44 | assign pixel_on = ~(rom_data == 12'h00f | `ENABLE == 0); 45 | assign color = (rom_data == 12'h00f | `ENABLE == 0) ? 12'b0 : rom_data; 46 | 47 | endmodule // background_engine 48 | -------------------------------------------------------------------------------- /src/game_over_text.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05/25/2018 07:25:03 PM 7 | // Design Name: 8 | // Module Name: vga_clock 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module game_over_text( 24 | input wire clk, 25 | input wire enable, 26 | output wire [15:0] addr, 27 | output wire [15:0] dina 28 | ); 29 | 30 | reg [5:0] glyph; 31 | reg [2:0] writing_text; 32 | reg [2:0] writing_text_next; 33 | 34 | always @ (posedge clk) 35 | begin 36 | if (enable) begin 37 | case (writing_text_next) 38 | 3'b000: glyph <= 6'b011100; 39 | 3'b001: glyph <= 6'b010111; 40 | 3'b010: glyph <= 6'b010111; 41 | 3'b011: glyph <= 6'b100101; 42 | 3'b100: glyph <= 6'b001011; 43 | 3'b101: glyph <= 6'b001010; 44 | 3'b110: glyph <= 6'b001101; 45 | 3'b111: glyph <= 6'b100011; 46 | endcase 47 | 48 | writing_text <= writing_text_next; 49 | if (writing_text == 7) 50 | writing_text_next <= 0; 51 | else 52 | writing_text_next <= writing_text + 1; 53 | end 54 | end 55 | 56 | assign dina = {enable, 2'b00, glyph}; 57 | assign addr = writing_text + 55; 58 | 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /resource/music_process.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import math 3 | parser = argparse.ArgumentParser(description='midi converter') 4 | parser.add_argument('midi_path', type=str, help='path to the midi that you want to convert') 5 | parser.add_argument('track', type=int, help='track number') 6 | args = parser.parse_args() 7 | 8 | 9 | import mido 10 | mid = mido.MidiFile(args.midi_path) 11 | timing = {0: []} 12 | current_time = 0 13 | max_notes_in_track = 0 14 | track = args.track 15 | for i, msg in enumerate(mid.tracks[track]): 16 | if isinstance(msg, mido.Message): 17 | if msg.type.startswith( 'note_'): 18 | print(i, msg) 19 | prev_notes = list(timing.get(current_time, [])) 20 | current_time += msg.time 21 | print(current_time) 22 | if msg.type == 'note_on' and msg.velocity > 0: 23 | prev_notes.append(msg.note) 24 | else: 25 | prev_notes.remove(msg.note) 26 | timing[current_time] = prev_notes 27 | max_notes_in_track = max(len(prev_notes), max_notes_in_track) 28 | ticks_per_beat = mid.ticks_per_beat 29 | tempo = 375000 30 | 31 | for i in timing: 32 | timing[i].extend([0] * (max_notes_in_track - len(timing[i]))) 33 | 34 | import pickle 35 | timing_index = list(timing) 36 | midi_freq = pickle.load(open('midi_note.dat', 'rb')) 37 | files = list(map(lambda ch : open("track_{}_ch_{}.hex".format(track, ch), "w"), range(max_notes_in_track))) 38 | for i in range(len(timing_index) - 1): 39 | delta_ticks = timing_index[i + 1] - timing_index[i] 40 | idx = timing_index[i] 41 | duration = int(mido.tick2second(delta_ticks, ticks_per_beat, tempo) * 1000) 42 | data = list(map(lambda x : 0 if x == 0 else 100000000 // (midi_freq[x] * 64), timing[idx])) 43 | print(duration) 44 | print(data) 45 | list(map(lambda t : t[1].write("{0:04x}{1:04x}\n".format(int(data[t[0]]), duration)), enumerate(files))) 46 | -------------------------------------------------------------------------------- /src/object_engine.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | module object_engine #( 4 | parameter OAM_WIDTH = 32, 5 | parameter OAM_DEPTH = 8, 6 | parameter TILE_WIDTH = 32, 7 | parameter TILE_HEIGHT = 32, 8 | parameter OAM_CACHE_DEPTH = 8 9 | ) ( 10 | input wire clk, 11 | input wire video_on, 12 | input wire [9:0] x, y, 13 | input wire [31:0] oam_data, 14 | output reg [2:0] oam_addr, 15 | output wire sprite_on, 16 | output wire [11:0] color 17 | ); 18 | 19 | reg [11:0] color_reg; 20 | reg [6:0] rom_x, rom_y; 21 | reg evaluating; 22 | wire [11:0] rom_data; 23 | 24 | integer i; 25 | reg [OAM_WIDTH - 1:0] oam_cache [OAM_CACHE_DEPTH - 1:0]; 26 | reg [3:0] len; 27 | reg [7:0] in_range, display_something; 28 | `define SPRITE_ENABLE oam_cache[i][31:31] 29 | `define X_FLIP oam_cache[i][26:26] 30 | `define OBJ_POS_X oam_cache[i][25:16] 31 | `define OBJ_POS_Y oam_cache[i][15:6] 32 | `define SPRITE_COL oam_cache[i][2:0] 33 | `define SPRITE_ROW oam_cache[i][5:3] 34 | 35 | mario_rom mario_rom(.clk(clk), .video_on(video_on), .x(rom_x), .y(rom_y), .color(rom_data)); 36 | 37 | always @ (posedge clk) begin 38 | oam_addr <= oam_addr + 1; 39 | oam_cache[oam_addr] <= oam_data; 40 | for (i = 0; i < OAM_CACHE_DEPTH; i = i + 1) begin 41 | if (`SPRITE_ENABLE) 42 | if (x >= `OBJ_POS_X & x < `OBJ_POS_X + TILE_WIDTH & y >= `OBJ_POS_Y & y < `OBJ_POS_Y + TILE_HEIGHT) begin 43 | if (`X_FLIP) 44 | rom_x <= `SPRITE_COL * TILE_WIDTH + TILE_WIDTH - 1 - (x - `OBJ_POS_X); 45 | else 46 | rom_x <= `SPRITE_COL * TILE_WIDTH + (x - `OBJ_POS_X); 47 | rom_y <= `SPRITE_ROW * TILE_HEIGHT + (y - `OBJ_POS_Y); 48 | color_reg <= rom_data; 49 | in_range[i] <= 1; 50 | end else in_range[i] <= 0; 51 | end 52 | // object evaluation 53 | /* if (video_on == 0) begin 54 | if (evaluating) begin 55 | if (len < 8) begin 56 | oam_addr <= oam_addr + 1; 57 | if (y >= oam_data[oam_addr][19:10] & y < oam_data[oam_addr][19:10] + TILE_HEIGHT) begin 58 | oam_cache[len] <= oam_data; 59 | len <= len + 1; 60 | end 61 | end else begin 62 | evaluating <= 0; 63 | end 64 | end else begin 65 | evaluating <= 1; 66 | end 67 | */ 68 | end 69 | assign sprite_on = (rom_data == 12'h00f | ~(|in_range) ) ? 0 : 1; 70 | assign color = color_reg; 71 | endmodule 72 | -------------------------------------------------------------------------------- /src/clock_div.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module clock_div( 3 | input wire clk, 4 | input wire clr, 5 | output wire out_clk, 6 | output reg[1:0] s 7 | ); 8 | parameter MAX_COUNT = 50_000 - 1; 9 | reg [31:0] counter; 10 | initial begin 11 | counter <= 0; 12 | s <= 2'b00; 13 | end 14 | always @ (posedge clk or posedge clr) 15 | begin 16 | if (clr == 1) 17 | counter <= 0; 18 | else if (counter == MAX_COUNT) begin 19 | counter <= 0; 20 | s <= s + 1; 21 | end 22 | else 23 | counter <= counter + 1; 24 | end 25 | assign out_clk = counter == 0; 26 | endmodule 27 | 28 | module clock_normal( 29 | input wire clk, 30 | input wire clr, 31 | output wire out_clk, 32 | output reg[15:0] clock 33 | ); 34 | parameter MAX_COUNT = 100_000_000 - 1; 35 | reg [31:0] counter; 36 | 37 | always @ (posedge clk or posedge clr) 38 | begin 39 | if (clr == 1) 40 | counter <= 0; 41 | else if (counter == MAX_COUNT) begin 42 | counter <= 0; 43 | if (clock[3:0] < 9) 44 | clock[3:0] = clock[3:0] + 1; 45 | else begin 46 | clock[3:0] = 0; 47 | if (clock[7:4] < 5) 48 | clock[7:4] = clock[7:4] + 1; 49 | else begin 50 | clock[7:4] = 0; 51 | if (clock[11:8] < 9) 52 | clock[11:8] = clock[11:8] + 1; 53 | else begin 54 | clock[11:8] = 0; 55 | if (clock[15:12] < 5) 56 | clock[15:12] = clock[15:12] + 1; 57 | else begin 58 | clock[15:12] = 0; 59 | end 60 | end 61 | end 62 | end 63 | 64 | end 65 | else 66 | counter <= counter + 1; 67 | end 68 | assign out_clk = counter == 0; 69 | endmodule 70 | 71 | module clock_div_n #( 72 | parameter MAX_COUNT = 15 - 1 73 | )( 74 | input wire clk, 75 | input wire clr, 76 | output wire out_clk, 77 | output reg wlk 78 | ); 79 | 80 | reg [31:0] counter; 81 | initial begin 82 | counter <= 0; 83 | end 84 | always @ (posedge clk or posedge clr) 85 | begin 86 | if (clr == 1) 87 | counter <= 0; 88 | else if (counter == MAX_COUNT) begin 89 | counter <= 0; 90 | wlk <= ~wlk; 91 | end 92 | else 93 | counter <= counter + 1; 94 | 95 | end 96 | assign out_clk = counter == 0; 97 | endmodule 98 | -------------------------------------------------------------------------------- /src/vga_sync.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | module vga_sync( 3 | input wire clk, clr, 4 | output wire hsync, vsync, video_on, p_tick, f_tick, 5 | output wire [9:0] x, y 6 | ); 7 | parameter DISPLAY_H = 640; 8 | parameter DISPLAY_V = 480; 9 | 10 | parameter BORDER_LEFT = 48; 11 | parameter BORDER_RIGHT = 16; 12 | 13 | parameter BORDER_TOP = 10; 14 | parameter BORDER_BOTTOM = 33; 15 | 16 | parameter RETRACE_H = 96; 17 | parameter RETRACE_V = 2; 18 | 19 | parameter H_MAX = DISPLAY_H + BORDER_LEFT + BORDER_RIGHT + RETRACE_H - 1; 20 | parameter V_MAX = DISPLAY_V + BORDER_TOP + BORDER_BOTTOM + RETRACE_V - 1; 21 | 22 | parameter H_RETRACE_START = DISPLAY_H + BORDER_RIGHT; 23 | parameter H_RETRACE_END = H_RETRACE_START + RETRACE_H - 1; 24 | 25 | parameter V_RETRACE_START = DISPLAY_V + BORDER_BOTTOM; 26 | parameter V_RETRACE_END = V_RETRACE_START + RETRACE_V - 1; 27 | 28 | reg [1:0] pixel_reg; 29 | wire [1:0] pixel_next; 30 | wire pixel_tick; 31 | 32 | always @(posedge clk, posedge clr) 33 | if (clr) 34 | pixel_reg <= 0; 35 | else 36 | pixel_reg <= pixel_next; 37 | 38 | assign pixel_next = pixel_reg + 1; // increment pixel_reg 39 | 40 | assign pixel_tick = (pixel_reg == 0); // assert tick 1/4 of the time 41 | 42 | // registers to keep track of current pixel location 43 | reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next; 44 | reg vsync_reg, hsync_reg; 45 | wire vsync_next, hsync_next; 46 | always @ (posedge clk, posedge clr) 47 | if (clr) 48 | begin 49 | v_count_reg <= 0; 50 | h_count_reg <= 0; 51 | vsync_reg <= 0; 52 | hsync_reg <= 0; 53 | end 54 | else 55 | begin 56 | v_count_reg <= v_count_next; 57 | h_count_reg <= h_count_next; 58 | vsync_reg <= vsync_next; 59 | hsync_reg <= hsync_next; 60 | end 61 | 62 | always @ (*) 63 | begin 64 | h_count_next = pixel_tick ? 65 | h_count_reg == H_MAX ? 0 : h_count_reg + 1 66 | : h_count_reg; 67 | 68 | v_count_next = pixel_tick && h_count_reg == H_MAX ? 69 | (v_count_reg == V_MAX ? 0 : v_count_reg + 1) 70 | : v_count_reg; 71 | end 72 | 73 | // hsync and vsync are active low signals 74 | // hsync signal asserted during horizontal retrace 75 | assign hsync_next = h_count_reg >= H_RETRACE_START 76 | && h_count_reg <= H_RETRACE_END; 77 | 78 | // vsync signal asserted during vertical retrace 79 | assign vsync_next = v_count_reg >= V_RETRACE_START 80 | && v_count_reg <= V_RETRACE_END; 81 | 82 | // video only on when pixels are in both horizontal and vertical display region 83 | assign video_on = (h_count_reg < DISPLAY_H) 84 | && (v_count_reg < DISPLAY_V); 85 | 86 | // output signals 87 | assign hsync = hsync_reg; 88 | assign vsync = vsync_reg; 89 | assign x = h_count_reg; 90 | assign y = v_count_reg; 91 | assign p_tick = pixel_tick; 92 | assign f_tick = x == 0 && y == 0; 93 | endmodule // -------------------------------------------------------------------------------- /resource/img_process.py: -------------------------------------------------------------------------------- 1 | from PIL import Image 2 | import argparse 3 | import math 4 | parser = argparse.ArgumentParser(description='Convert normal RGB pictures for Basys 3 4-bit RGB') 5 | parser.add_argument('img_path', type=str, help='path to the image that you want to convert') 6 | parser.add_argument('rom_name', type=str, help='the name of the rom module') 7 | parser.add_argument('--width', type=int, help='new width', default=None) 8 | parser.add_argument('--height', type=int, help='new height', default=None) 9 | parser.add_argument('--mono', action='store_true', help='apply further compression if the picture is monochromic', default=False) 10 | parser.add_argument('--file', type=str, help='save output to file') 11 | args = parser.parse_args() 12 | 13 | def bin_rom(rom_name, total, x_high, y_high, bin_file): 14 | template = """ 15 | module {}(clk, video_on, x, y, color); 16 | parameter ROM_WIDTH = 12; 17 | parameter ROM_ADDR_BITS = {}; 18 | 19 | (* rom_style="block" *) 20 | reg [ROM_WIDTH-1:0] rom [(2**ROM_ADDR_BITS)-1:0]; 21 | input wire clk; 22 | input wire video_on; 23 | input wire [{}:0] x; 24 | input wire [{}:0] y; 25 | reg [ROM_ADDR_BITS-1:0] address; 26 | output reg [ROM_WIDTH-1:0] color; 27 | 28 | initial 29 | $readmemh("{}", rom); 30 | 31 | always @(posedge clk) 32 | if (video_on) begin 33 | address <= {{y, x}}; 34 | color <= rom[address]; 35 | end 36 | endmodule 37 | """.format(rom_name, total, x_high, y_high, bin_file) 38 | return template 39 | 40 | def main(): 41 | lines = [] 42 | im = Image.open(args.img_path) 43 | width = args.width 44 | height = args.height 45 | if width is not None and height is not None: 46 | im = im.resize((width, height)) 47 | w, h = im.size 48 | y_digits = math.ceil(math.log2(h)) 49 | x_digits = math.ceil(math.log2(w)) 50 | total = y_digits + x_digits 51 | y_high = y_digits - 1 52 | x_high = x_digits - 1 53 | if args.mono: 54 | for y in range(h): 55 | for x in range(w): 56 | concat_bin = ('{0:0' + str(y_digits) + 'b}{1:0' + str(x_digits) + 'b}').format(y,x) 57 | lines.append(('@{0:x}').format(int(concat_bin, 2))) 58 | r, g, b = im.getpixel((x, y)) 59 | 60 | if (r + g + b) >= 225 * 3: 61 | lines.append('1') 62 | else: 63 | lines.append('0') 64 | else: 65 | for y in range(h): 66 | for x in range(w): 67 | r, g, b = im.getpixel((x, y)) 68 | r = r // 16 69 | g = g // 16 70 | b = b // 16 71 | 72 | concat_bin = ('{0:0' + str(y_digits) + 'b}{1:0' + str(x_digits) + 'b}').format(y,x) 73 | lines.append(('@{0:x}').format(int(concat_bin, 2))) 74 | lines.append('{0:x}{1:x}{2:x}'.format(r, g, b)) 75 | if args.file is not None: 76 | with open(args.file, 'w') as f: 77 | for line in lines: 78 | f.write(line + '\n') 79 | with open(args.file + '.v', 'w') as f: 80 | f.write(bin_rom(args.rom_name, total, x_high, y_high, args.file)) 81 | else: 82 | for line in lines: 83 | print(line) 84 | 85 | if __name__ == '__main__': 86 | main() 87 | -------------------------------------------------------------------------------- /src/ram.v: -------------------------------------------------------------------------------- 1 | 2 | // Xilinx Simple Dual Port Single Clock RAM 3 | // This code implements a parameterizable SDP single clock memory. 4 | // If a reset or enable is not necessary, it may be tied off or removed from the code. 5 | 6 | module ram #( 7 | parameter RAM_WIDTH = 64, // Specify RAM data width 8 | parameter RAM_DEPTH = 512, // Specify RAM depth (number of entries) 9 | parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 10 | parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not) 11 | ) ( 12 | input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH 13 | input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH 14 | input [RAM_WIDTH-1:0] dina, // RAM input data 15 | input clka, // Clock 16 | input wea, // Write enable 17 | input enb, // Read Enable, for additional power savings, disable when not in use 18 | input rstb, // Output reset (does not affect memory contents) 19 | input regceb, // Output register enable 20 | output [RAM_WIDTH-1:0] doutb // RAM output data 21 | ); 22 | 23 | reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0]; 24 | reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}}; 25 | 26 | // The following code either initializes the memory values to a specified file or to all zeros to match hardware 27 | generate 28 | if (INIT_FILE != "") begin: use_init_file 29 | initial 30 | $readmemh(INIT_FILE, BRAM); 31 | end else begin: init_bram_to_zero 32 | integer ram_index; 33 | initial 34 | for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) 35 | BRAM[ram_index] = {RAM_WIDTH{1'b0}}; 36 | end 37 | endgenerate 38 | 39 | always @(posedge clka) begin 40 | if (wea) 41 | BRAM[addra] <= dina; 42 | if (enb) 43 | ram_data <= BRAM[addrb]; 44 | end 45 | 46 | // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) 47 | generate 48 | if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register 49 | 50 | // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing 51 | assign doutb = ram_data; 52 | 53 | end else begin: output_register 54 | 55 | // The following is a 2 clock cycle read latency with improve clock-to-out timing 56 | 57 | reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; 58 | 59 | always @(posedge clka) 60 | if (rstb) 61 | doutb_reg <= {RAM_WIDTH{1'b0}}; 62 | else if (regceb) 63 | doutb_reg <= ram_data; 64 | 65 | assign doutb = doutb_reg; 66 | 67 | end 68 | endgenerate 69 | 70 | // The following function calculates the address width based on specified RAM depth 71 | function integer clogb2; 72 | input integer depth; 73 | for (clogb2=0; depth>0; clogb2=clogb2+1) 74 | depth = depth >> 1; 75 | endfunction 76 | 77 | endmodule 78 | 79 | // The following is an instantiation template for xilinx_simple_dual_port_1_clock_ram 80 | /* 81 | // Xilinx Simple Dual Port Single Clock RAM 82 | xilinx_simple_dual_port_1_clock_ram #( 83 | .RAM_WIDTH(18), // Specify RAM data width 84 | .RAM_DEPTH(1024), // Specify RAM depth (number of entries) 85 | .RAM_PERFORMANCE("HIGH_PERFORMANCE"), // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 86 | .INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not) 87 | ) your_instance_name ( 88 | .addra(addra), // Write address bus, width determined from RAM_DEPTH 89 | .addrb(addrb), // Read address bus, width determined from RAM_DEPTH 90 | .dina(dina), // RAM input data, width determined from RAM_WIDTH 91 | .clka(clka), // Clock 92 | .wea(wea), // Write enable 93 | .enb(enb), // Read Enable, for additional power savings, disable when not in use 94 | .rstb(rstb), // Output reset (does not affect memory contents) 95 | .regceb(regceb), // Output register enable 96 | .doutb(doutb) // RAM output data, width determined from RAM_WIDTH 97 | ); 98 | */ 99 | 100 | -------------------------------------------------------------------------------- /src/flapga_mario.v: -------------------------------------------------------------------------------- 1 | module flapga_mario 2 | ( 3 | input wire clk, clr, 4 | input wire [15:0] sw, 5 | input wire up, down, left, right, 6 | output wire hsync, vsync, 7 | output wire [11:0] rgb, 8 | output wire [6:0] seg, 9 | output wire [3:0] ano, 10 | output wire dp, 11 | output wire out 12 | ); 13 | integer z_index; 14 | parameter LAYERS = 3; 15 | reg [11:0] rgb_reg; 16 | reg [11:0] ctrl; 17 | wire bg_wea; 18 | wire wlk; 19 | 20 | wire [11:0] rgb_pic[0:LAYERS - 1]; 21 | wire layer_on[0:LAYERS - 1]; 22 | wire video_on, f_tick, clock_clk, walk_clk; 23 | wire [9:0] x, y; 24 | wire [15:0] nums; 25 | wire [38:0] dina[0:1]; 26 | wire [38:0] data; 27 | wire [15:0] addr[0:1]; 28 | wire [15:0] bg_data; 29 | wire [15:0] bg_ram_addr; 30 | wire [15:0] splash_data; 31 | wire [15:0] splash_addr; 32 | wire [31:0] oam_data; 33 | wire [2:0] oam_addr; 34 | wire [15:0] bam_data; 35 | wire [3:0] bg_x_offset; 36 | reg [9:0] cloud_x_offset; 37 | 38 | parameter GAME_BEGIN_DELAY = 500_000_000; 39 | reg [31:0] splash_timer; 40 | reg game_begin = 0; 41 | clock_normal clock_normal(.clk(clk), .clr(0), .out_clk(clock_clk), .clock(nums)); 42 | vga_sync vga_sync_unit (.clk(clk), .clr(0), .hsync(hsync), .vsync(vsync), 43 | .video_on(video_on), .p_tick(), .f_tick(f_tick), .x(x), .y(y)); 44 | 45 | display display(.basys3_clk(clk), .seg(seg), .ano(ano), .nums(nums)); 46 | audio_output audio(clk, out); 47 | ram #( 48 | .RAM_WIDTH(9), 49 | .RAM_DEPTH(1208), 50 | .RAM_PERFORMANCE("HIGH_PERFORMANCE"), 51 | .INIT_FILE("splash.bin") 52 | ) splash_ram ( 53 | .addra(0), 54 | .addrb(bg_ram_addr), 55 | .dina(0), 56 | .clka(clk), 57 | .wea(0), 58 | .enb(1), .rstb(0), 59 | .regceb(1), .doutb(splash_data) 60 | ); 61 | ram #( 62 | .RAM_WIDTH(9), 63 | .RAM_DEPTH(1208), 64 | .RAM_PERFORMANCE("HIGH_PERFORMANCE"), 65 | .INIT_FILE("") 66 | ) bg_ram ( 67 | .addra(addr[0]), 68 | .addrb(bg_ram_addr), 69 | .dina(dina[0]), 70 | .clka(clk), 71 | .wea(bg_wea), 72 | .enb(1), .rstb(0), 73 | .regceb(1), .doutb(bg_data) 74 | ); 75 | 76 | ram #(.RAM_WIDTH(32), .RAM_DEPTH(8), .RAM_PERFORMANCE("HIGH_PERFORMANCE"),.INIT_FILE()) oam ( 77 | .addra(addr[1]), 78 | .addrb(oam_addr), 79 | .dina(dina[1]), 80 | .clka(clk), 81 | .wea(bg_wea), 82 | .enb(1), .rstb(0), 83 | .regceb(1), .doutb(oam_data) 84 | ); 85 | cloud_bg cloud_bg(clk, video_on, ((x + cloud_x_offset) / 3) % 213, y / 3, rgb_pic[0]); 86 | background_engine bg_engine(clk, video_on, bg_x_offset, x, y, bam_data, bg_ram_addr, layer_on[1], rgb_pic[1]); 87 | object_engine obj_eng (clk, video_on, x, y, oam_data, oam_addr, layer_on[2], rgb_pic[2]); 88 | game_engine game_eng (clk, clr, video_on, game_begin, up, down, left, right, f_tick, x, y, bg_x_offset, addr[1], addr[0], bg_wea, dina[1], dina[0]); 89 | 90 | assign bam_data = game_begin ? bg_data : splash_data; 91 | assign layer_on[0] = y > 32 & game_begin; 92 | always @ (posedge clk) 93 | if (clr) begin 94 | game_begin <= 0; 95 | splash_timer <= 0; 96 | end else 97 | begin 98 | if (~game_begin & splash_timer < GAME_BEGIN_DELAY) 99 | splash_timer <= splash_timer + 1; 100 | else if (splash_timer == GAME_BEGIN_DELAY) game_begin <= 1; 101 | for (z_index = 0; z_index < LAYERS; z_index = z_index + 1) begin 102 | if (layer_on[z_index]) 103 | rgb_reg <= rgb_pic[z_index]; 104 | end 105 | end 106 | always @ (posedge bg_x_offset[0]) begin 107 | if (cloud_x_offset == 639) cloud_x_offset <= 0; 108 | else cloud_x_offset <= cloud_x_offset + 1; 109 | end 110 | assign dp = 1; 111 | assign rgb = (video_on & (layer_on[0] | layer_on[1] | layer_on[2])) ? rgb_reg : 12'b0; 112 | 113 | endmodule -------------------------------------------------------------------------------- /src/mario.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module mario( 3 | input wire clk, reset, 4 | input wire up, down, left, right, 5 | input wire game_over, 6 | output reg [9:0] pos_x_reg = 80, 7 | output reg [9:0] pos_y_reg = 64, 8 | output wire [31:0] dina, 9 | output wire [2:0] addr 10 | ); 11 | 12 | reg [2:0] rom_col, rom_row; 13 | reg [9:0] pos_x_next, pos_y_next; 14 | 15 | assign dina = {5'b10000, 1'b0, pos_x_reg, pos_y_reg, rom_row, rom_col}; 16 | assign addr = 0; 17 | 18 | localparam TIME_START_Y = 100000; 19 | localparam TIME_STEP_Y = 10000; 20 | localparam TIME_MAX_Y = 800000; 21 | localparam TIME_TERM_Y = 250000; 22 | 23 | localparam [2:0] jump_down = 3'b000, 24 | jump_up = 3'b100; 25 | 26 | reg [2:0] state_reg_y, state_next_y; 27 | 28 | reg [19:0] jump_t_reg, jump_t_next; 29 | reg [19:0] start_reg_y, start_next_y; 30 | reg [25:0] extra_up_reg, extra_up_next; 31 | 32 | // signals for up-button positive edge signal 33 | reg [7:0] up_reg; 34 | wire up_edge; 35 | assign up_edge = ~(&up_reg) & up; 36 | parameter MIN_Y = 32; 37 | 38 | always @(posedge clk) 39 | begin 40 | if (reset) begin 41 | pos_y_reg <= 64; 42 | end else begin 43 | state_reg_y <= state_next_y; 44 | jump_t_reg <= jump_t_next; 45 | start_reg_y <= start_next_y; 46 | extra_up_reg <= extra_up_next; 47 | pos_y_reg <= pos_y_next; 48 | up_reg <= {up_reg[6:0], up}; 49 | end 50 | end 51 | 52 | always @ * begin 53 | if (game_over) begin 54 | rom_row <= 1; 55 | rom_col <= 0; 56 | end else 57 | if (state_next_y == jump_up) begin 58 | rom_row <= start_next_y > 100000 & start_next_y < 600000; 59 | rom_col <= 3'b001; 60 | end else begin 61 | rom_row <= start_next_y > 550000 & start_next_y <= 800000; 62 | rom_col <= start_next_y > 550000 & start_next_y <= 800000; 63 | end 64 | end 65 | 66 | always @ * begin 67 | state_next_y = state_reg_y; 68 | jump_t_next = jump_t_reg; 69 | start_next_y = start_reg_y; 70 | extra_up_next = extra_up_reg; 71 | pos_y_next = pos_y_reg; 72 | 73 | if(up_edge & ~game_over) begin 74 | state_next_y = jump_up; 75 | start_next_y = TIME_START_Y; 76 | jump_t_next = TIME_START_Y; 77 | extra_up_next = 0; 78 | end 79 | 80 | case (state_reg_y) 81 | jump_up: begin 82 | 83 | if(jump_t_reg > 0) begin 84 | jump_t_next = jump_t_reg - 1; 85 | end 86 | 87 | if(jump_t_reg == 0) begin 88 | 89 | if( pos_y_next > MIN_Y) 90 | pos_y_next = pos_y_reg - 1; 91 | 92 | if(start_reg_y <= TIME_MAX_Y) begin 93 | start_next_y = start_reg_y + TIME_STEP_Y; 94 | jump_t_next = start_reg_y + TIME_STEP_Y; 95 | end 96 | else 97 | begin 98 | state_next_y = jump_down; 99 | start_next_y = TIME_MAX_Y; 100 | jump_t_next = TIME_MAX_Y; 101 | end 102 | end 103 | 104 | end 105 | 106 | jump_down: begin 107 | if(jump_t_reg > 0) 108 | begin 109 | jump_t_next = jump_t_reg - 1; 110 | end 111 | if(jump_t_reg == 0) 112 | begin 113 | begin 114 | if (pos_y_next <= 480) 115 | pos_y_next = pos_y_reg + 1; 116 | if(start_reg_y > TIME_TERM_Y) 117 | begin 118 | start_next_y = start_reg_y - TIME_STEP_Y; 119 | jump_t_next = start_reg_y - TIME_STEP_Y; 120 | end 121 | else 122 | begin 123 | jump_t_next = TIME_TERM_Y; 124 | end 125 | end 126 | end 127 | end 128 | endcase 129 | end 130 | endmodule 131 | -------------------------------------------------------------------------------- /src/vga_cons.xdc: -------------------------------------------------------------------------------- 1 | # Clock signal 2 | set_property PACKAGE_PIN W5 [get_ports clk] 3 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] 5 | 6 | # Switches 7 | set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 9 | set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 10 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 11 | set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 13 | set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 15 | set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 17 | set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 19 | set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 20 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 21 | set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 22 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 23 | set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 24 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 25 | set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 26 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 27 | set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 28 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 29 | set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 30 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 31 | set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 32 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 33 | set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 34 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 35 | set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 36 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 37 | set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 38 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 39 | #VGA Connector 40 | set_property PACKAGE_PIN G19 [get_ports {rgb[8]}] 41 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[8]}] 42 | set_property PACKAGE_PIN H19 [get_ports {rgb[9]}] 43 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[9]}] 44 | set_property PACKAGE_PIN J19 [get_ports {rgb[10]}] 45 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[10]}] 46 | set_property PACKAGE_PIN N19 [get_ports {rgb[11]}] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[11]}] 48 | set_property PACKAGE_PIN N18 [get_ports {rgb[0]}] 49 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] 50 | set_property PACKAGE_PIN L18 [get_ports {rgb[1]}] 51 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] 52 | set_property PACKAGE_PIN K18 [get_ports {rgb[2]}] 53 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] 54 | set_property PACKAGE_PIN J18 [get_ports {rgb[3]}] 55 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[3]}] 56 | set_property PACKAGE_PIN J17 [get_ports {rgb[4]}] 57 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[4]}] 58 | set_property PACKAGE_PIN H17 [get_ports {rgb[5]}] 59 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[5]}] 60 | set_property PACKAGE_PIN G17 [get_ports {rgb[6]}] 61 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[6]}] 62 | set_property PACKAGE_PIN D17 [get_ports {rgb[7]}] 63 | set_property IOSTANDARD LVCMOS33 [get_ports {rgb[7]}] 64 | set_property PACKAGE_PIN P19 [get_ports hsync] 65 | set_property IOSTANDARD LVCMOS33 [get_ports hsync] 66 | set_property PACKAGE_PIN R19 [get_ports vsync] 67 | set_property IOSTANDARD LVCMOS33 [get_ports vsync] 68 | 69 | set_property PACKAGE_PIN U18 [get_ports clr] 70 | set_property IOSTANDARD LVCMOS33 [get_ports clr] 71 | 72 | set_property PACKAGE_PIN T18 [get_ports up] 73 | set_property IOSTANDARD LVCMOS33 [get_ports up] 74 | 75 | set_property PACKAGE_PIN U17 [get_ports down] 76 | set_property IOSTANDARD LVCMOS33 [get_ports down] 77 | 78 | set_property PACKAGE_PIN W19 [get_ports left] 79 | set_property IOSTANDARD LVCMOS33 [get_ports left] 80 | 81 | set_property PACKAGE_PIN T17 [get_ports right] 82 | set_property IOSTANDARD LVCMOS33 [get_ports right] 83 | 84 | 85 | set_property PACKAGE_PIN U7 [get_ports seg[0]] 86 | set_property IOSTANDARD LVCMOS33 [get_ports seg[0]] 87 | set_property PACKAGE_PIN V5 [get_ports seg[1]] 88 | set_property IOSTANDARD LVCMOS33 [get_ports seg[1]] 89 | set_property PACKAGE_PIN U5 [get_ports seg[2]] 90 | set_property IOSTANDARD LVCMOS33 [get_ports seg[2]] 91 | set_property PACKAGE_PIN V8 [get_ports seg[3]] 92 | set_property IOSTANDARD LVCMOS33 [get_ports seg[3]] 93 | set_property PACKAGE_PIN U8 [get_ports seg[4]] 94 | set_property IOSTANDARD LVCMOS33 [get_ports seg[4]] 95 | set_property PACKAGE_PIN W6 [get_ports seg[5]] 96 | set_property IOSTANDARD LVCMOS33 [get_ports seg[5]] 97 | set_property PACKAGE_PIN W7 [get_ports seg[6]] 98 | set_property IOSTANDARD LVCMOS33 [get_ports seg[6]] 99 | set_property PACKAGE_PIN V7 [get_ports dp] 100 | set_property IOSTANDARD LVCMOS33 [get_ports dp] 101 | 102 | 103 | set_property PACKAGE_PIN U2 [get_ports ano[0]] 104 | set_property IOSTANDARD LVCMOS33 [get_ports ano[0]] 105 | set_property PACKAGE_PIN U4 [get_ports ano[1]] 106 | set_property IOSTANDARD LVCMOS33 [get_ports ano[1]] 107 | set_property PACKAGE_PIN V4 [get_ports ano[2]] 108 | set_property IOSTANDARD LVCMOS33 [get_ports ano[2]] 109 | set_property PACKAGE_PIN W4 [get_ports ano[3]] 110 | set_property IOSTANDARD LVCMOS33 [get_ports ano[3]] 111 | 112 | set_property PACKAGE_PIN J3 [get_ports {out}] 113 | set_property IOSTANDARD LVCMOS33 [get_ports {out}] 114 | -------------------------------------------------------------------------------- /src/text.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | module text_ram # ( 4 | parameter RAM_WIDTH = 39, 5 | parameter RAM_DEPTH = 128 6 | )( 7 | input [clogb2(RAM_DEPTH-1)-1:0] addra, // Address bus, width determined from RAM_DEPTH 8 | input [RAM_WIDTH-1:0] dina, // RAM input data 9 | input clka, // Clock 10 | input wea, // Write enable 11 | input ena, // RAM Enable, for additional power savings, disable port when not in use 12 | input rsta, // Output reset (does not affect memory contents) 13 | input regcea, // Output register enable 14 | output [RAM_WIDTH-1:0] douta 15 | ); 16 | (* ram_style="block" *) 17 | reg [RAM_WIDTH - 1:0] data = {RAM_WIDTH{1'b0}}; 18 | reg [RAM_WIDTH - 1:0] tam [RAM_DEPTH-1:0]; 19 | 20 | 21 | always @(posedge clka) 22 | if (ena) 23 | if (wea) 24 | tam[addra] <= dina; 25 | else 26 | data <= tam[addra]; 27 | reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}}; 28 | 29 | always @(posedge clka) 30 | if (rsta) 31 | douta_reg <= {RAM_WIDTH{1'b0}}; 32 | else if (regcea) 33 | douta_reg <= data; 34 | 35 | assign douta = douta_reg; 36 | function integer clogb2; 37 | input integer depth; 38 | for (clogb2=0; depth>0; clogb2=clogb2+1) 39 | depth = depth >> 1; 40 | endfunction 41 | 42 | endmodule 43 | */ 44 | 45 | // Xilinx Simple Dual Port Single Clock RAM 46 | // This code implements a parameterizable SDP single clock memory. 47 | // If a reset or enable is not necessary, it may be tied off or removed from the code. 48 | 49 | module text_ram #( 50 | parameter RAM_WIDTH = 39, // Specify RAM data width 51 | parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries) 52 | parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 53 | parameter INIT_FILE = "hello.hex" // Specify name/location of RAM initialization file if using one (leave blank if not) 54 | ) ( 55 | input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH 56 | input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH 57 | input [RAM_WIDTH-1:0] dina, // RAM input data 58 | input clka, // Clock 59 | input wea, // Write enable 60 | input enb, // Read Enable, for additional power savings, disable when not in use 61 | input rstb, // Output reset (does not affect memory contents) 62 | input regceb, // Output register enable 63 | output [RAM_WIDTH-1:0] doutb // RAM output data 64 | ); 65 | (* ram_style="block" *) 66 | reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0]; 67 | reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}}; 68 | 69 | // The following code either initializes the memory values to a specified file or to all zeros to match hardware 70 | generate 71 | if (INIT_FILE != "") begin: use_init_file 72 | initial 73 | $readmemb(INIT_FILE, BRAM); 74 | end else begin: init_bram_to_zero 75 | integer ram_index; 76 | initial 77 | for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) 78 | BRAM[ram_index] = {RAM_WIDTH{1'b0}}; 79 | end 80 | endgenerate 81 | 82 | always @(posedge clka) begin 83 | if (wea) 84 | BRAM[addra] <= dina; 85 | if (enb) 86 | ram_data <= BRAM[addrb]; 87 | end 88 | 89 | // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) 90 | generate 91 | if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register 92 | 93 | // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing 94 | assign doutb = ram_data; 95 | 96 | end else begin: output_register 97 | 98 | // The following is a 2 clock cycle read latency with improve clock-to-out timing 99 | 100 | reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; 101 | 102 | always @(posedge clka) 103 | if (rstb) 104 | doutb_reg <= {RAM_WIDTH{1'b0}}; 105 | else if (regceb) 106 | doutb_reg <= ram_data; 107 | 108 | assign doutb = doutb_reg; 109 | 110 | end 111 | endgenerate 112 | 113 | // The following function calculates the address width based on specified RAM depth 114 | function integer clogb2; 115 | input integer depth; 116 | for (clogb2=0; depth>0; clogb2=clogb2+1) 117 | depth = depth >> 1; 118 | endfunction 119 | 120 | endmodule 121 | 122 | // The following is an instantiation template for xilinx_simple_dual_port_1_clock_ram 123 | /* 124 | // Xilinx Simple Dual Port Single Clock RAM 125 | xilinx_simple_dual_port_1_clock_ram #( 126 | .RAM_WIDTH(18), // Specify RAM data width 127 | .RAM_DEPTH(1024), // Specify RAM depth (number of entries) 128 | .RAM_PERFORMANCE("HIGH_PERFORMANCE"), // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 129 | .INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not) 130 | ) your_instance_name ( 131 | .addra(addra), // Write address bus, width determined from RAM_DEPTH 132 | .addrb(addrb), // Read address bus, width determined from RAM_DEPTH 133 | .dina(dina), // RAM input data, width determined from RAM_WIDTH 134 | .clka(clka), // Clock 135 | .wea(wea), // Write enable 136 | .enb(enb), // Read Enable, for additional power savings, disable when not in use 137 | .rstb(rstb), // Output reset (does not affect memory contents) 138 | .regceb(regceb), // Output register enable 139 | .doutb(doutb) // RAM output data, width determined from RAM_WIDTH 140 | ); 141 | */ 142 | 143 | 144 | -------------------------------------------------------------------------------- /src/game_engine.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module game_engine( 3 | input wire clk, reset, 4 | input wire video_on, game_on, 5 | input wire up, down, left, right, 6 | input wire f_tick, 7 | input wire [9:0] x, y, 8 | output reg [3:0] bg_x_offset, 9 | output wire [7:0] obj_ram_addr, 10 | output wire [15:0] bg_ram_addr, 11 | output reg bg_wea = 0, 12 | output wire [31:0] obj_ram_data, 13 | output wire [31:0] bg_ram_data 14 | ); 15 | // Multiplexers 16 | reg [15:0] bam_addr [4:0]; 17 | reg [15:0] bam_data [4:0]; 18 | wire [15:0] score_addr, score_data, text_addr, text_data; 19 | reg [15:0] score = 0; 20 | reg [2:0] bam_select; 21 | reg [15:0] bam_counter; 22 | reg [3:0] real_bg_x_offset; 23 | 24 | // pipes 25 | reg [2:0] gap_end_osc; 26 | reg [2:0] up_end_osc; 27 | reg [15:0] pipe_pos_x[2:0]; 28 | reg [15:0] pipe_up_end[2:0]; 29 | reg [15:0] pipe_gap_end[2:0]; 30 | reg [15:0] pipe_y[2:0]; 31 | reg [15:0] pipe_x[2:0]; 32 | reg [2:0] pipe_data_col, pipe_data_row, pipe_data_props; 33 | reg [1:0] pipe_count; 34 | 35 | // coins 36 | reg [15:0] coin_x = 38, coin_y = 16; 37 | reg [15:0] coin_counter; 38 | reg [2:0] coin_data_col; 39 | reg [7:0] coin_y_osc; 40 | reg [31:0] scroll_counter, scroll_delay = 1_000_000; 41 | reg [31:0] coin_animate_counter; 42 | reg [1:0] coin_frame; 43 | reg coin_eaten; 44 | 45 | // Mario 46 | wire wlk; 47 | wire [9:0] mario_x, mario_y; 48 | reg game_over = 0; 49 | mario mario(.clk(game_on ? clk : 0), .reset(reset), .up(up), .left(left), .right(right), .down(down), .pos_x_reg(mario_x), .pos_y_reg(mario_y), 50 | .game_over(game_over), .dina(obj_ram_data), .addr(obj_ram_addr)); 51 | 52 | // game status 53 | vga_num vga_num(clk, 1, score, score_addr, score_data); 54 | game_over_text text(clk, game_over, text_addr, text_data); 55 | 56 | integer i; 57 | reg clear_bg = 0; 58 | parameter TILE_WIDTH = 16; 59 | parameter TILE_HEIGHT = 16; 60 | parameter TILE_COLS = 640 / TILE_WIDTH; 61 | parameter TILE_ROWS = 480 / TILE_HEIGHT; 62 | parameter MAX_SCROLL_DELAY = 1_000_000; 63 | parameter MIN_SCROLL_DELAY = 200_000; 64 | parameter COIN_ANIMATE_DELAY = 15_000_000; 65 | parameter COIN_SCORE = 10; 66 | parameter SPEED_UP_STEP = 100_000; 67 | 68 | // 400 clocks for pipes and 10 clocks for score 69 | // clear background 70 | 71 | initial begin 72 | score <= 0; 73 | game_over <= 0; 74 | scroll_delay <= 1_000_000; 75 | pipe_pos_x[0] <= 39; 76 | pipe_up_end[0] <= 10; 77 | pipe_gap_end[0] <= 22; 78 | pipe_y[0] <= 2; 79 | pipe_x[0] <= 39; 80 | pipe_pos_x[1] <= 26; 81 | pipe_up_end[1] <= 11; 82 | pipe_gap_end[1] <= 24; 83 | pipe_y[1] <= 2; 84 | pipe_x[1] <= 39; 85 | pipe_pos_x[2] <= 13; 86 | pipe_up_end[2] <= 14; 87 | pipe_gap_end[2] <= 24; 88 | pipe_y[2] <= 2; 89 | pipe_x[2] <= 39; 90 | end 91 | 92 | always @ (posedge clk) begin 93 | 94 | if (reset) begin 95 | score <= 0; 96 | bg_wea <= 0; 97 | game_over <= 0; 98 | scroll_delay <= 1_000_000; 99 | pipe_pos_x[0] <= 39; 100 | pipe_up_end[0] <= 10; 101 | pipe_gap_end[0] <= 22; 102 | pipe_y[0] <= 1; 103 | pipe_x[0] <= 39; 104 | pipe_pos_x[1] <= 26; 105 | pipe_up_end[1] <= 11; 106 | pipe_gap_end[1] <= 24; 107 | pipe_y[1] <= 1; 108 | pipe_x[1] <= 39; 109 | pipe_pos_x[2] <= 13; 110 | pipe_up_end[2] <= 3; 111 | pipe_gap_end[2] <= 28; 112 | pipe_y[2] <= 1; 113 | pipe_x[2] <= 39; 114 | end 115 | 116 | if (game_on) begin 117 | if (clear_bg) begin 118 | bg_wea <= 1; 119 | if (bam_addr[2] == TILE_COLS * TILE_ROWS) clear_bg <= 0; 120 | bam_select <= 2; 121 | bam_addr[2] <= bam_addr[2] + 1; 122 | bam_data[2] <= 0; 123 | end 124 | else begin 125 | if (bam_counter < 2050) begin bam_select <= 1; bam_counter <= bam_counter + 1; bg_wea <= pipe_y[pipe_count] >= 2 ;end 126 | else if (bam_counter >= 2050 & bam_counter < 2064) begin bam_select <= 0; bam_counter <= bam_counter + 1; bg_wea <= 1; end 127 | else if (bam_counter >= 2064 & bam_counter < 2100) begin bam_select <= 3; bam_counter <= bam_counter + 1; bg_wea <= 1; end 128 | else if (bam_counter >= 2100 & bam_counter < 2300) begin bam_select <= 4; bam_counter <= bam_counter + 1; bg_wea <= 1; end 129 | else begin bam_counter <= 0; pipe_count <= 0; end 130 | 131 | bam_addr[0] <= score_addr; 132 | bam_data[0] <= score_data; 133 | bam_addr[4] <= text_addr; 134 | bam_data[4] <= text_data; 135 | 136 | if (pipe_y[pipe_count] < pipe_up_end[pipe_count] | pipe_y[pipe_count] > pipe_gap_end[pipe_count]) 137 | begin 138 | pipe_data_col <= 3'd2 + pipe_x[pipe_count] - pipe_pos_x[pipe_count]; 139 | pipe_data_props <= 3'b100; 140 | end 141 | else if (pipe_y[pipe_count] == pipe_up_end[pipe_count]) 142 | begin 143 | pipe_data_col <= 3'd0 + pipe_x[pipe_count] - pipe_pos_x[pipe_count]; 144 | pipe_data_props <= 3'b110; 145 | 146 | end 147 | else if (pipe_y[pipe_count] == pipe_gap_end[pipe_count]) 148 | begin 149 | pipe_data_col <= 3'd0 + pipe_x[pipe_count] - pipe_pos_x[pipe_count]; 150 | pipe_data_props <= 3'b100; 151 | end 152 | else if (pipe_y[pipe_count] > pipe_up_end[pipe_count] + 1 & pipe_y[pipe_count] < pipe_gap_end[pipe_count] - 1) 153 | begin 154 | bg_wea <= 0; 155 | pipe_data_props <= 3'b000; 156 | end 157 | 158 | if (pipe_y[pipe_count] == 39) begin 159 | pipe_y[pipe_count] <= 1; 160 | if (pipe_x[pipe_count] != pipe_pos_x[pipe_count] + 1) 161 | pipe_x[pipe_count] <= pipe_pos_x[pipe_count] + 1; 162 | else 163 | begin 164 | pipe_count <= pipe_count + 1; 165 | pipe_y[pipe_count + 1] <= 1; end 166 | 167 | end else 168 | pipe_y[pipe_count] <= pipe_y[pipe_count] + 1; 169 | 170 | bam_addr[1] <= pipe_x[pipe_count] + pipe_y[pipe_count] * TILE_COLS; 171 | bam_data[1] <= {pipe_data_props, 3'd5, pipe_data_col}; 172 | // coin 173 | coin_data_col <= coin_frame + 4; 174 | bam_addr[3] <= coin_x + coin_y * TILE_COLS; 175 | bam_data[3] <= {~coin_eaten , 2'b00, 3'd7, coin_data_col}; 176 | end 177 | bg_x_offset <= (y < 32) ? 0 : real_bg_x_offset; 178 | if (scroll_counter == scroll_delay) begin 179 | if (real_bg_x_offset == 15) begin 180 | if (coin_x > 0) begin 181 | coin_x <= coin_x - 1; 182 | end else begin 183 | coin_eaten <= 0; 184 | coin_x <= 39 - coin_y_osc % 6; 185 | coin_y <= coin_y_osc % (TILE_ROWS - 2) + 2; 186 | end 187 | for (i = 0; i < 3; i = i + 1) 188 | if (pipe_pos_x[i] > 0) begin 189 | pipe_pos_x[i] <= pipe_pos_x[i] - 1; 190 | pipe_x[i] <= pipe_pos_x[i] - 1; 191 | pipe_y[i] <= 1; 192 | if (pipe_pos_x[i] == 2 && ~game_over) begin 193 | if (scroll_delay > MIN_SCROLL_DELAY & (score + 1) % 10 == 0) scroll_delay <= scroll_delay - SPEED_UP_STEP; 194 | score <= score + 1; 195 | end 196 | end 197 | else begin 198 | 199 | pipe_pos_x[i] <= 39; 200 | pipe_x[i] <= 39; 201 | pipe_up_end[i] <= up_end_osc + 6; 202 | pipe_gap_end[i] <= up_end_osc + 14 + gap_end_osc; 203 | pipe_y[i] <= 1; 204 | end 205 | clear_bg <= 1; bam_addr[2] <= 0; 206 | end 207 | real_bg_x_offset <= real_bg_x_offset + 1; 208 | scroll_counter <= 0; 209 | end else 210 | scroll_counter <= scroll_counter + 1; 211 | 212 | if (coin_animate_counter == COIN_ANIMATE_DELAY) begin coin_frame <= coin_frame + 1; coin_animate_counter <= 0; end 213 | else coin_animate_counter <= coin_animate_counter + 1; 214 | 215 | if (((mario_x + 28 + real_bg_x_offset) >= (pipe_pos_x[pipe_count] * TILE_WIDTH) & mario_x + real_bg_x_offset < (pipe_pos_x[pipe_count] + 2) * TILE_WIDTH 216 | & ((mario_y < (pipe_up_end[pipe_count] + 1) * TILE_HEIGHT) | (mario_y + 28 > pipe_gap_end[pipe_count] * TILE_HEIGHT))) | mario_y > 480) 217 | game_over <= 1; 218 | 219 | if ((mario_x + 28 + real_bg_x_offset) >= (coin_x * TILE_WIDTH) & mario_x + real_bg_x_offset < (coin_x + 1) * TILE_WIDTH 220 | & (mario_y >= (coin_y - 1) * TILE_HEIGHT) & (mario_y <= (coin_y + 1) * TILE_HEIGHT) 221 | & ~coin_eaten & ~game_over) 222 | begin coin_eaten <= 1; score <= score + COIN_SCORE; end 223 | 224 | up_end_osc <= up_end_osc + x / 2 + y + score; 225 | gap_end_osc <= gap_end_osc + y + score; 226 | coin_y_osc <= coin_y_osc + y + x; 227 | end 228 | end 229 | 230 | assign bg_ram_addr = bam_addr[bam_select]; 231 | assign bg_ram_data = bam_data[bam_select]; 232 | endmodule 233 | -------------------------------------------------------------------------------- /src/audio_unit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | module wave_generator( 4 | input wire clk, 5 | input wire [15:0] freq, 6 | output reg signed [9:0] wave_out 7 | ); 8 | reg [5:0] i; 9 | reg signed [7:0] amplitude [0:63]; 10 | reg [15:0] counter = 0; 11 | 12 | initial begin 13 | amplitude[0] = 0; 14 | amplitude[1] = 7; 15 | amplitude[2] = 13; 16 | amplitude[3] = 19; 17 | amplitude[4] = 25; 18 | amplitude[5] = 30; 19 | amplitude[6] = 35; 20 | amplitude[7] = 40; 21 | amplitude[8] = 45; 22 | amplitude[9] = 49; 23 | amplitude[10] = 52; 24 | amplitude[11] = 55; 25 | amplitude[12] = 58; 26 | amplitude[13] = 60; 27 | amplitude[14] = 62; 28 | amplitude[15] = 63; 29 | amplitude[16] = 63; 30 | amplitude[17] = 63; 31 | amplitude[18] = 62; 32 | amplitude[19] = 60; 33 | amplitude[20] = 58; 34 | amplitude[21] = 55; 35 | amplitude[22] = 52; 36 | amplitude[23] = 49; 37 | amplitude[24] = 45; 38 | amplitude[25] = 40; 39 | amplitude[26] = 35; 40 | amplitude[27] = 30; 41 | amplitude[28] = 25; 42 | amplitude[29] = 19; 43 | amplitude[30] = 13; 44 | amplitude[31] = 7; 45 | amplitude[32] = 0; 46 | amplitude[33] = -7; 47 | amplitude[34] = -13; 48 | amplitude[35] = -19; 49 | amplitude[36] = -25; 50 | amplitude[37] = -30; 51 | amplitude[38] = -35; 52 | amplitude[39] = -40; 53 | amplitude[40] = -45; 54 | amplitude[41] = -49; 55 | amplitude[42] = -52; 56 | amplitude[43] = -55; 57 | amplitude[44] = -58; 58 | amplitude[45] = -60; 59 | amplitude[46] = -62; 60 | amplitude[47] = -63; 61 | amplitude[48] = -63; 62 | amplitude[49] = -63; 63 | amplitude[50] = -62; 64 | amplitude[51] = -60; 65 | amplitude[52] = -58; 66 | amplitude[53] = -55; 67 | amplitude[54] = -52; 68 | amplitude[55] = -49; 69 | amplitude[56] = -45; 70 | amplitude[57] = -40; 71 | amplitude[58] = -35; 72 | amplitude[59] = -30; 73 | amplitude[60] = -25; 74 | amplitude[61] = -19; 75 | amplitude[62] = -13; 76 | amplitude[63] = -7; 77 | end 78 | 79 | always @ (posedge clk) begin 80 | if (freq == 0) wave_out <= 0; 81 | else 82 | if (counter == freq) begin 83 | counter <= 0; 84 | wave_out <= $signed(amplitude[i]); 85 | i <= i + 1; 86 | if (i == 63) i <= 0; else i <= i + 1; 87 | end else counter <= counter + 1; 88 | end 89 | endmodule 90 | 91 | module audio_output( 92 | input wire clk, 93 | output reg out 94 | ); 95 | wire signed [9:0] ch[0:4]; 96 | wire signed [11:0] wave_sum; 97 | wire [11:0] positive_wave_sum; 98 | wire [15:0] freq_count [0:4]; 99 | reg [9:0] PWM; 100 | reg [31:0] music_data [0:79]; 101 | reg [31:0] music_data2 [0:79]; 102 | reg [31:0] music_data3 [0:180]; 103 | reg [31:0] play_counter; 104 | reg [15:0] note_counter = 0; 105 | reg [15:0] note_counter1 = 0; 106 | reg [31:0] note_data[0:1]; 107 | reg [31:0] note_data2; 108 | wave_generator ch0(clk, freq_count[0], ch[0]); 109 | wave_generator ch1(clk, freq_count[1], ch[1]); 110 | wave_generator ch2(clk, freq_count[2], ch[2]); 111 | assign freq_count[0] = note_data[0][31:16]; 112 | assign freq_count[1] = note_data[1][31:16]; 113 | assign freq_count[2] = note_data2[31:16]; 114 | assign wave_sum = ch[2] + ch[1] + ch[0]; 115 | assign positive_wave_sum = wave_sum * 2 + 512; 116 | initial begin 117 | music_data[0] = 32'h0000010a; 118 | music_data[1] = 32'h1284010a; 119 | music_data[2] = 32'h1754010a; 120 | music_data[3] = 32'h18b7010a; 121 | music_data[4] = 32'h0ddf010a; 122 | music_data[5] = 32'h0d17010a; 123 | music_data[6] = 32'h14c80085; 124 | music_data[7] = 32'h0c5b0085; 125 | music_data[8] = 32'h14c80085; 126 | music_data[9] = 32'h00000085; 127 | music_data[10] = 32'h0c5b0085; 128 | music_data[11] = 32'h00000085; 129 | music_data[12] = 32'h0c5b0215; 130 | music_data[13] = 32'h0000010a; 131 | music_data[14] = 32'h0f91026e; 132 | music_data[15] = 32'h000000b1; 133 | music_data[16] = 32'h107f026e; 134 | music_data[17] = 32'h000000b1; 135 | music_data[18] = 32'h0f91026e; 136 | music_data[19] = 32'h00000137; 137 | music_data[20] = 32'h00000085; 138 | music_data[21] = 32'h00000085; 139 | music_data[22] = 32'h00000085; 140 | music_data[23] = 32'h00000085; 141 | music_data[24] = 32'h00000085; 142 | music_data[25] = 32'h0f91026e; 143 | music_data[26] = 32'h000000b1; 144 | music_data[27] = 32'h107f0215; 145 | music_data[28] = 32'h08bd010a; 146 | music_data[29] = 32'h0f91026e; 147 | music_data[30] = 32'h0000034c; 148 | music_data[31] = 32'h00000085; 149 | music_data[32] = 32'h117a026e; 150 | music_data[33] = 32'h000000b1; 151 | music_data[34] = 32'h0b02026e; 152 | music_data[35] = 32'h000000b1; 153 | music_data[36] = 32'h117a026e; 154 | music_data[37] = 32'h00000137; 155 | music_data[38] = 32'h00000085; 156 | music_data[39] = 32'h00000085; 157 | music_data[40] = 32'h00000085; 158 | music_data[41] = 32'h00000085; 159 | music_data[42] = 32'h00000085; 160 | music_data[43] = 32'h0a64026e; 161 | music_data[44] = 32'h000000b1; 162 | music_data[45] = 32'h0f910215; 163 | music_data[46] = 32'h0ddf010a; 164 | music_data[47] = 32'h0f91026e; 165 | music_data[48] = 32'h0000034c; 166 | music_data[49] = 32'h00000085; 167 | music_data[50] = 32'h0942026e; 168 | music_data[51] = 32'h000000b1; 169 | music_data[52] = 32'h07c8026e; 170 | music_data[53] = 32'h000000b1; 171 | music_data[54] = 32'h07c8026e; 172 | music_data[55] = 32'h000000b1; 173 | music_data[56] = 32'h0000010a; 174 | music_data[57] = 32'h00000085; 175 | music_data[58] = 32'h0000010a; 176 | music_data[59] = 32'h00000085; 177 | music_data[60] = 32'h08bd026e; 178 | music_data[61] = 32'h000000b1; 179 | music_data[62] = 32'h08bd026e; 180 | music_data[63] = 32'h000000b1; 181 | music_data[64] = 32'h0baa026e; 182 | music_data[65] = 32'h000000b1; 183 | music_data[66] = 32'h0000010a; 184 | music_data[67] = 32'h00000085; 185 | music_data[68] = 32'h0000010a; 186 | music_data[69] = 32'h00000085; 187 | music_data[70] = 32'h0942026e; 188 | music_data[71] = 32'h000000b1; 189 | music_data[72] = 32'h117a010a; 190 | music_data[73] = 32'h0c5b010a; 191 | music_data[74] = 32'h0c5b010a; 192 | music_data[75] = 32'h09420085; 193 | music_data[76] = 32'h0c5b0085; 194 | music_data[77] = 32'h0942018f; 195 | music_data[78] = 32'h117a0085; 196 | music_data[79] = 32'h1284031f; 197 | music_data2[0] = 32'h14c8010a; 198 | music_data2[1] = 32'h1605010a; 199 | music_data2[2] = 32'h107f010a; 200 | music_data2[3] = 32'h0f91010a; 201 | music_data2[4] = 32'h1754010a; 202 | music_data2[5] = 32'h1605010a; 203 | music_data2[6] = 32'h0c5b0085; 204 | music_data2[7] = 32'h14c80085; 205 | music_data2[8] = 32'h0c5b0085; 206 | music_data2[9] = 32'h00000085; 207 | music_data2[10] = 32'h12840085; 208 | music_data2[11] = 32'h00000085; 209 | music_data2[12] = 32'h117a0215; 210 | music_data2[13] = 32'h0f91010a; 211 | music_data2[14] = 32'h0942026e; 212 | music_data2[15] = 32'h000000b1; 213 | music_data2[16] = 32'h09cf026e; 214 | music_data2[17] = 32'h000000b1; 215 | music_data2[18] = 32'h0942026e; 216 | music_data2[19] = 32'h00000137; 217 | music_data2[20] = 32'h0f910085; 218 | music_data2[21] = 32'h0ddf0085; 219 | music_data2[22] = 32'h0c5b0085; 220 | music_data2[23] = 32'h0baa0085; 221 | music_data2[24] = 32'h0a640085; 222 | music_data2[25] = 32'h0942026e; 223 | music_data2[26] = 32'h000000b1; 224 | music_data2[27] = 32'h09cf0215; 225 | music_data2[28] = 32'h0ddf010a; 226 | music_data2[29] = 32'h0942026e; 227 | music_data2[30] = 32'h0000034c; 228 | music_data2[31] = 32'h0f910085; 229 | music_data2[32] = 32'h0a64026e; 230 | music_data2[33] = 32'h000000b1; 231 | music_data2[34] = 32'h1284026e; 232 | music_data2[35] = 32'h000000b1; 233 | music_data2[36] = 32'h0a64026e; 234 | music_data2[37] = 32'h00000137; 235 | music_data2[38] = 32'h0f910085; 236 | music_data2[39] = 32'h0ddf0085; 237 | music_data2[40] = 32'h0c5b0085; 238 | music_data2[41] = 32'h0baa0085; 239 | music_data2[42] = 32'h0b020085; 240 | music_data2[43] = 32'h117a026e; 241 | music_data2[44] = 32'h000000b1; 242 | music_data2[45] = 32'h18b70215; 243 | music_data2[46] = 32'h08bd010a; 244 | music_data2[47] = 32'h0942026e; 245 | music_data2[48] = 32'h0000034c; 246 | music_data2[49] = 32'h0f910085; 247 | music_data2[50] = 32'h07c8026e; 248 | music_data2[51] = 32'h000000b1; 249 | music_data2[52] = 32'h0a64026e; 250 | music_data2[53] = 32'h000000b1; 251 | music_data2[54] = 32'h0b02026e; 252 | music_data2[55] = 32'h000000b1; 253 | music_data2[56] = 32'h07c8010a; 254 | music_data2[57] = 32'h06ef0085; 255 | music_data2[58] = 32'h0000010a; 256 | music_data2[59] = 32'h07c80085; 257 | music_data2[60] = 32'h0a64026e; 258 | music_data2[61] = 32'h000000b1; 259 | music_data2[62] = 32'h0b02026e; 260 | music_data2[63] = 32'h000000b1; 261 | music_data2[64] = 32'h08bd026e; 262 | music_data2[65] = 32'h000000b1; 263 | music_data2[66] = 32'h08bd010a; 264 | music_data2[67] = 32'h07c80085; 265 | music_data2[68] = 32'h0000010a; 266 | music_data2[69] = 32'h08bd0085; 267 | music_data2[70] = 32'h1754026e; 268 | music_data2[71] = 32'h000000b1; 269 | music_data2[72] = 32'h0ddf010a; 270 | music_data2[73] = 32'h0f91010a; 271 | music_data2[74] = 32'h08bd010a; 272 | music_data2[75] = 32'h0c5b0085; 273 | music_data2[76] = 32'h09420085; 274 | music_data2[77] = 32'h0c5b018f; 275 | music_data2[78] = 32'h0c5b0085; 276 | music_data2[79] = 32'h0baa031f; 277 | music_data3[0] = 32'h00000855; 278 | music_data3[1] = 32'h1f230085; 279 | music_data3[2] = 32'h00000085; 280 | music_data3[3] = 32'h1f23031f; 281 | music_data3[4] = 32'h2ea80085; 282 | music_data3[5] = 32'h00000085; 283 | music_data3[6] = 32'h1f230085; 284 | music_data3[7] = 32'h00000085; 285 | music_data3[8] = 32'h17540085; 286 | music_data3[9] = 32'h00000085; 287 | music_data3[10] = 32'h316e0085; 288 | music_data3[11] = 32'h00000085; 289 | music_data3[12] = 32'h1f230085; 290 | music_data3[13] = 32'h00000085; 291 | music_data3[14] = 32'h18b70085; 292 | music_data3[15] = 32'h00000085; 293 | music_data3[16] = 32'h2ea80085; 294 | music_data3[17] = 32'h00000085; 295 | music_data3[18] = 32'h1f230085; 296 | music_data3[19] = 32'h00000085; 297 | music_data3[20] = 32'h17540085; 298 | music_data3[21] = 32'h00000085; 299 | music_data3[22] = 32'h25080085; 300 | music_data3[23] = 32'h00000085; 301 | music_data3[24] = 32'h1f230085; 302 | music_data3[25] = 32'h00000085; 303 | music_data3[26] = 32'h17540085; 304 | music_data3[27] = 32'h00000085; 305 | music_data3[28] = 32'h2ea80085; 306 | music_data3[29] = 32'h00000085; 307 | music_data3[30] = 32'h1f230085; 308 | music_data3[31] = 32'h00000085; 309 | music_data3[32] = 32'h17540085; 310 | music_data3[33] = 32'h00000085; 311 | music_data3[34] = 32'h316e0085; 312 | music_data3[35] = 32'h00000085; 313 | music_data3[36] = 32'h1f230085; 314 | music_data3[37] = 32'h00000085; 315 | music_data3[38] = 32'h18b70085; 316 | music_data3[39] = 32'h00000085; 317 | music_data3[40] = 32'h2ea80085; 318 | music_data3[41] = 32'h00000085; 319 | music_data3[42] = 32'h1f230085; 320 | music_data3[43] = 32'h00000085; 321 | music_data3[44] = 32'h17540085; 322 | music_data3[45] = 32'h00000085; 323 | music_data3[46] = 32'h25080085; 324 | music_data3[47] = 32'h00000085; 325 | music_data3[48] = 32'h1f230085; 326 | music_data3[49] = 32'h00000085; 327 | music_data3[50] = 32'h17540085; 328 | music_data3[51] = 32'h00000085; 329 | music_data3[52] = 32'h29910085; 330 | music_data3[53] = 32'h00000085; 331 | music_data3[54] = 32'h1f230085; 332 | music_data3[55] = 32'h00000085; 333 | music_data3[56] = 32'h18b70085; 334 | music_data3[57] = 32'h00000085; 335 | music_data3[58] = 32'h2c0a0085; 336 | music_data3[59] = 32'h00000085; 337 | music_data3[60] = 32'h20fe0085; 338 | music_data3[61] = 32'h00000085; 339 | music_data3[62] = 32'h1a2f0085; 340 | music_data3[63] = 32'h00000085; 341 | music_data3[64] = 32'h29910085; 342 | music_data3[65] = 32'h00000085; 343 | music_data3[66] = 32'h1f230085; 344 | music_data3[67] = 32'h00000085; 345 | music_data3[68] = 32'h18b70085; 346 | music_data3[69] = 32'h00000085; 347 | music_data3[70] = 32'h316e0085; 348 | music_data3[71] = 32'h00000085; 349 | music_data3[72] = 32'h1f230085; 350 | music_data3[73] = 32'h00000085; 351 | music_data3[74] = 32'h18b70085; 352 | music_data3[75] = 32'h00000085; 353 | music_data3[76] = 32'h29910085; 354 | music_data3[77] = 32'h00000085; 355 | music_data3[78] = 32'h1f230085; 356 | music_data3[79] = 32'h00000085; 357 | music_data3[80] = 32'h18b70085; 358 | music_data3[81] = 32'h00000085; 359 | music_data3[82] = 32'h316e0085; 360 | music_data3[83] = 32'h00000085; 361 | music_data3[84] = 32'h1f230085; 362 | music_data3[85] = 32'h00000085; 363 | music_data3[86] = 32'h18b70085; 364 | music_data3[87] = 32'h00000085; 365 | music_data3[88] = 32'h2ea80085; 366 | music_data3[89] = 32'h00000085; 367 | music_data3[90] = 32'h1f230085; 368 | music_data3[91] = 32'h00000085; 369 | music_data3[92] = 32'h17540085; 370 | music_data3[93] = 32'h00000085; 371 | music_data3[94] = 32'h3e470085; 372 | music_data3[95] = 32'h00000085; 373 | music_data3[96] = 32'h1f230085; 374 | music_data3[97] = 32'h00000085; 375 | music_data3[98] = 32'h17540085; 376 | music_data3[99] = 32'h00000085; 377 | music_data3[100] = 32'h2ea80085; 378 | music_data3[101] = 32'h00000085; 379 | music_data3[102] = 32'h1f230085; 380 | music_data3[103] = 32'h00000085; 381 | music_data3[104] = 32'h12840085; 382 | music_data3[105] = 32'h00000085; 383 | music_data3[106] = 32'h316e0085; 384 | music_data3[107] = 32'h00000085; 385 | music_data3[108] = 32'h1f230085; 386 | music_data3[109] = 32'h00000085; 387 | music_data3[110] = 32'h14c80085; 388 | music_data3[111] = 32'h00000085; 389 | music_data3[112] = 32'h345f0085; 390 | music_data3[113] = 32'h00000085; 391 | music_data3[114] = 32'h1f230085; 392 | music_data3[115] = 32'h00000085; 393 | music_data3[116] = 32'h16050085; 394 | music_data3[117] = 32'h00000085; 395 | music_data3[118] = 32'h2c0a0085; 396 | music_data3[119] = 32'h00000085; 397 | music_data3[120] = 32'h1f230085; 398 | music_data3[121] = 32'h00000085; 399 | music_data3[122] = 32'h12840085; 400 | music_data3[123] = 32'h00000085; 401 | music_data3[124] = 32'h29910085; 402 | music_data3[125] = 32'h00000085; 403 | music_data3[126] = 32'h1bbe0085; 404 | music_data3[127] = 32'h00000085; 405 | music_data3[128] = 32'h117a0085; 406 | music_data3[129] = 32'h00000085; 407 | music_data3[130] = 32'h2c0a0085; 408 | music_data3[131] = 32'h00000085; 409 | music_data3[132] = 32'h1bbe0085; 410 | music_data3[133] = 32'h00000085; 411 | music_data3[134] = 32'h117a0085; 412 | music_data3[135] = 32'h00000085; 413 | music_data3[136] = 32'h2ea80085; 414 | music_data3[137] = 32'h00000085; 415 | music_data3[138] = 32'h1bbe0085; 416 | music_data3[139] = 32'h00000085; 417 | music_data3[140] = 32'h117a0085; 418 | music_data3[141] = 32'h00000085; 419 | music_data3[142] = 32'h316e0085; 420 | music_data3[143] = 32'h00000085; 421 | music_data3[144] = 32'h1f230085; 422 | music_data3[145] = 32'h00000085; 423 | music_data3[146] = 32'h117a0085; 424 | music_data3[147] = 32'h00000085; 425 | music_data3[148] = 32'h2ea80085; 426 | music_data3[149] = 32'h00000085; 427 | music_data3[150] = 32'h1f230085; 428 | music_data3[151] = 32'h00000085; 429 | music_data3[152] = 32'h12840085; 430 | music_data3[153] = 32'h00000085; 431 | music_data3[154] = 32'h3e470085; 432 | music_data3[155] = 32'h00000085; 433 | music_data3[156] = 32'h1f230085; 434 | music_data3[157] = 32'h00000085; 435 | music_data3[158] = 32'h1f230085; 436 | music_data3[159] = 32'h00000085; 437 | music_data3[160] = 32'h22f40085; 438 | music_data3[161] = 32'h22f40085; 439 | music_data3[162] = 32'h22f4018f; 440 | music_data3[163] = 32'h316e0085; 441 | music_data3[164] = 32'h2ea8031f; 442 | 443 | end 444 | parameter NOTES = 80; 445 | parameter BASS = 9'd165; 446 | parameter PLAY_DELAY = 100_000 - 1; 447 | always @ (posedge clk) begin 448 | if (play_counter == PLAY_DELAY) begin 449 | play_counter <= 0; 450 | if (note_data2[15:0] == 0) begin 451 | if (note_counter1 == BASS | note_counter1 == 0) begin note_counter1 <= 1; 452 | note_data2 <= music_data3[0]; 453 | note_counter <= 1; note_data[0] <= music_data[0]; note_data[1] <= music_data2[0]; 454 | end 455 | else begin note_counter1 <= note_counter1 + 1; 456 | note_data2 <= music_data3[note_counter1]; 457 | end 458 | end else note_data2[15:0] <= note_data2[15:0] - 1; 459 | if (note_data[0][15:0] == 0) begin 460 | if (note_counter == 0) begin note_counter <= 1; note_data[0] <= music_data[0]; note_data[1] <= music_data2[0];end 461 | else if (note_counter < NOTES) begin note_counter <= note_counter + 1; note_data[0] <= music_data[note_counter]; note_data[1] <= music_data2[note_counter]; end 462 | end else note_data[0][15:0] <= note_data[0][15:0] - 1; 463 | 464 | end else play_counter <= play_counter + 1; 465 | if (PWM < $unsigned(positive_wave_sum)) out <= 1; 466 | else out <= 0; 467 | PWM <= PWM + 1; 468 | end 469 | endmodule 470 | /* 471 | set_property PACKAGE_PIN N1 [get_ports {output}] 472 | set_property IOSTANDARD LVCMOS33 [get_ports {output}] 473 | */ -------------------------------------------------------------------------------- /resource/platform.hex: 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1679 | @347 1680 | eef 1681 | @348 1682 | eef 1683 | @349 1684 | eef 1685 | @34a 1686 | eef 1687 | @34b 1688 | eef 1689 | @34c 1690 | eef 1691 | @34d 1692 | 555 1693 | @34e 1694 | 555 1695 | @34f 1696 | 000 1697 | @350 1698 | 000 1699 | @351 1700 | bbb 1701 | @352 1702 | bbb 1703 | @353 1704 | eef 1705 | @354 1706 | eef 1707 | @355 1708 | eef 1709 | @356 1710 | eef 1711 | @357 1712 | eef 1713 | @358 1714 | eef 1715 | @359 1716 | eef 1717 | @35a 1718 | eef 1719 | @35b 1720 | eef 1721 | @35c 1722 | eef 1723 | @35d 1724 | 555 1725 | @35e 1726 | 555 1727 | @35f 1728 | 000 1729 | @360 1730 | 000 1731 | @361 1732 | bbb 1733 | @362 1734 | bbb 1735 | @363 1736 | eef 1737 | @364 1738 | eef 1739 | @365 1740 | eef 1741 | @366 1742 | eef 1743 | @367 1744 | eef 1745 | @368 1746 | eef 1747 | @369 1748 | eef 1749 | @36a 1750 | eef 1751 | @36b 1752 | eef 1753 | @36c 1754 | eef 1755 | @36d 1756 | 555 1757 | @36e 1758 | 555 1759 | @36f 1760 | 000 1761 | @370 1762 | 000 1763 | @371 1764 | bbb 1765 | @372 1766 | bbb 1767 | @373 1768 | eef 1769 | @374 1770 | eef 1771 | @375 1772 | eef 1773 | @376 1774 | eef 1775 | @377 1776 | eef 1777 | @378 1778 | eef 1779 | @379 1780 | eef 1781 | @37a 1782 | eef 1783 | @37b 1784 | eef 1785 | @37c 1786 | eef 1787 | @37d 1788 | 555 1789 | @37e 1790 | 555 1791 | @37f 1792 | 000 1793 | @380 1794 | 000 1795 | @381 1796 | 000 1797 | @382 1798 | 555 1799 | @383 1800 | 555 1801 | @384 1802 | 555 1803 | @385 1804 | 555 1805 | @386 1806 | 555 1807 | @387 1808 | 555 1809 | @388 1810 | 555 1811 | @389 1812 | 555 1813 | @38a 1814 | 555 1815 | @38b 1816 | 555 1817 | @38c 1818 | 555 1819 | @38d 1820 | 555 1821 | @38e 1822 | 000 1823 | @38f 1824 | 000 1825 | @390 1826 | 000 1827 | @391 1828 | 000 1829 | @392 1830 | 555 1831 | @393 1832 | 555 1833 | @394 1834 | 555 1835 | @395 1836 | 555 1837 | @396 1838 | 555 1839 | @397 1840 | 555 1841 | @398 1842 | 555 1843 | @399 1844 | 555 1845 | @39a 1846 | 555 1847 | @39b 1848 | 555 1849 | @39c 1850 | 555 1851 | @39d 1852 | 555 1853 | @39e 1854 | 000 1855 | @39f 1856 | 000 1857 | @3a0 1858 | 000 1859 | @3a1 1860 | 000 1861 | @3a2 1862 | 555 1863 | @3a3 1864 | 555 1865 | @3a4 1866 | 555 1867 | @3a5 1868 | 555 1869 | @3a6 1870 | 555 1871 | @3a7 1872 | 555 1873 | @3a8 1874 | 555 1875 | @3a9 1876 | 555 1877 | @3aa 1878 | 555 1879 | @3ab 1880 | 555 1881 | @3ac 1882 | 555 1883 | @3ad 1884 | 555 1885 | @3ae 1886 | 000 1887 | @3af 1888 | 000 1889 | @3b0 1890 | 000 1891 | @3b1 1892 | 000 1893 | @3b2 1894 | 555 1895 | @3b3 1896 | 555 1897 | @3b4 1898 | 555 1899 | @3b5 1900 | 555 1901 | @3b6 1902 | 555 1903 | @3b7 1904 | 555 1905 | @3b8 1906 | 555 1907 | @3b9 1908 | 555 1909 | @3ba 1910 | 555 1911 | @3bb 1912 | 555 1913 | @3bc 1914 | 555 1915 | @3bd 1916 | 555 1917 | @3be 1918 | 000 1919 | @3bf 1920 | 000 1921 | @3c0 1922 | 00f 1923 | @3c1 1924 | 000 1925 | @3c2 1926 | 000 1927 | @3c3 1928 | 000 1929 | @3c4 1930 | 000 1931 | @3c5 1932 | 000 1933 | @3c6 1934 | 000 1935 | @3c7 1936 | 000 1937 | @3c8 1938 | 000 1939 | @3c9 1940 | 000 1941 | @3ca 1942 | 000 1943 | @3cb 1944 | 000 1945 | @3cc 1946 | 000 1947 | @3cd 1948 | 000 1949 | @3ce 1950 | 000 1951 | @3cf 1952 | 00f 1953 | @3d0 1954 | 00f 1955 | @3d1 1956 | 000 1957 | @3d2 1958 | 000 1959 | @3d3 1960 | 000 1961 | @3d4 1962 | 000 1963 | @3d5 1964 | 000 1965 | @3d6 1966 | 000 1967 | @3d7 1968 | 000 1969 | @3d8 1970 | 000 1971 | @3d9 1972 | 000 1973 | @3da 1974 | 000 1975 | @3db 1976 | 000 1977 | @3dc 1978 | 000 1979 | @3dd 1980 | 000 1981 | @3de 1982 | 000 1983 | @3df 1984 | 00f 1985 | @3e0 1986 | 00f 1987 | @3e1 1988 | 000 1989 | @3e2 1990 | 000 1991 | @3e3 1992 | 000 1993 | @3e4 1994 | 000 1995 | @3e5 1996 | 000 1997 | @3e6 1998 | 000 1999 | @3e7 2000 | 000 2001 | @3e8 2002 | 000 2003 | @3e9 2004 | 000 2005 | @3ea 2006 | 000 2007 | @3eb 2008 | 000 2009 | @3ec 2010 | 000 2011 | @3ed 2012 | 000 2013 | @3ee 2014 | 000 2015 | @3ef 2016 | 00f 2017 | @3f0 2018 | 00f 2019 | @3f1 2020 | 000 2021 | @3f2 2022 | 000 2023 | @3f3 2024 | 000 2025 | @3f4 2026 | 000 2027 | @3f5 2028 | 000 2029 | @3f6 2030 | 000 2031 | @3f7 2032 | 000 2033 | @3f8 2034 | 000 2035 | @3f9 2036 | 000 2037 | @3fa 2038 | 000 2039 | @3fb 2040 | 000 2041 | @3fc 2042 | 000 2043 | @3fd 2044 | 000 2045 | @3fe 2046 | 000 2047 | @3ff 2048 | 00f 2049 | @400 2050 | 00f 2051 | @401 2052 | 00f 2053 | @402 2054 | 000 2055 | @403 2056 | 000 2057 | @404 2058 | 000 2059 | @405 2060 | 000 2061 | @406 2062 | 000 2063 | @407 2064 | 000 2065 | @408 2066 | 000 2067 | @409 2068 | 000 2069 | @40a 2070 | 000 2071 | @40b 2072 | 000 2073 | @40c 2074 | 000 2075 | @40d 2076 | 000 2077 | @40e 2078 | 00f 2079 | @40f 2080 | 00f 2081 | @410 2082 | 00f 2083 | @411 2084 | 00f 2085 | @412 2086 | 000 2087 | @413 2088 | 000 2089 | @414 2090 | 000 2091 | @415 2092 | 000 2093 | @416 2094 | 000 2095 | @417 2096 | 000 2097 | @418 2098 | 000 2099 | @419 2100 | 000 2101 | @41a 2102 | 000 2103 | @41b 2104 | 000 2105 | @41c 2106 | 000 2107 | @41d 2108 | 000 2109 | @41e 2110 | 00f 2111 | @41f 2112 | 00f 2113 | @420 2114 | 00f 2115 | @421 2116 | 00f 2117 | @422 2118 | 000 2119 | @423 2120 | 000 2121 | @424 2122 | 000 2123 | @425 2124 | 000 2125 | @426 2126 | 000 2127 | @427 2128 | 000 2129 | @428 2130 | 000 2131 | @429 2132 | 000 2133 | @42a 2134 | 000 2135 | @42b 2136 | 000 2137 | @42c 2138 | 000 2139 | @42d 2140 | 000 2141 | @42e 2142 | 00f 2143 | @42f 2144 | 00f 2145 | @430 2146 | 00f 2147 | @431 2148 | 00f 2149 | @432 2150 | 00f 2151 | @433 2152 | 000 2153 | @434 2154 | 000 2155 | @435 2156 | 000 2157 | @436 2158 | 000 2159 | @437 2160 | 000 2161 | @438 2162 | 000 2163 | @439 2164 | 000 2165 | @43a 2166 | 000 2167 | @43b 2168 | 000 2169 | @43c 2170 | 000 2171 | @43d 2172 | 00f 2173 | @43e 2174 | 00f 2175 | @43f 2176 | 00f 2177 | @440 2178 | 00f 2179 | @441 2180 | 000 2181 | @442 2182 | eef 2183 | @443 2184 | eef 2185 | @444 2186 | eef 2187 | @445 2188 | eef 2189 | @446 2190 | eef 2191 | @447 2192 | eef 2193 | @448 2194 | eef 2195 | @449 2196 | eef 2197 | @44a 2198 | eef 2199 | @44b 2200 | eef 2201 | @44c 2202 | bbb 2203 | @44d 2204 | bbb 2205 | @44e 2206 | 000 2207 | @44f 2208 | 00f 2209 | @450 2210 | 00f 2211 | @451 2212 | 000 2213 | @452 2214 | eef 2215 | @453 2216 | fc1 2217 | @454 2218 | fc1 2219 | @455 2220 | 740 2221 | @456 2222 | 740 2223 | @457 2224 | 740 2225 | @458 2226 | 740 2227 | @459 2228 | 740 2229 | @45a 2230 | 740 2231 | @45b 2232 | 740 2233 | @45c 2234 | 740 2235 | @45d 2236 | 000 2237 | @45e 2238 | 000 2239 | @45f 2240 | 00f 2241 | @460 2242 | 00f 2243 | @461 2244 | 000 2245 | @462 2246 | eef 2247 | @463 2248 | eef 2249 | @464 2250 | eef 2251 | @465 2252 | c82 2253 | @466 2254 | c82 2255 | @467 2256 | c82 2257 | @468 2258 | c82 2259 | @469 2260 | c82 2261 | @46a 2262 | c82 2263 | @46b 2264 | c82 2265 | @46c 2266 | c82 2267 | @46d 2268 | c82 2269 | @46e 2270 | 000 2271 | @46f 2272 | 00f 2273 | @470 2274 | 00f 2275 | @471 2276 | 00f 2277 | @472 2278 | 000 2279 | @473 2280 | eff 2281 | @474 2282 | eff 2283 | @475 2284 | eff 2285 | @476 2286 | eff 2287 | @477 2288 | eff 2289 | @478 2290 | eff 2291 | @479 2292 | eff 2293 | @47a 2294 | eff 2295 | @47b 2296 | eff 2297 | @47c 2298 | eff 2299 | @47d 2300 | 000 2301 | @47e 2302 | 00f 2303 | @47f 2304 | 00f 2305 | @480 2306 | 00f 2307 | @481 2308 | 000 2309 | @482 2310 | eef 2311 | @483 2312 | eef 2313 | @484 2314 | eef 2315 | @485 2316 | eef 2317 | @486 2318 | eef 2319 | @487 2320 | eef 2321 | @488 2322 | eef 2323 | @489 2324 | bbb 2325 | @48a 2326 | bbb 2327 | @48b 2328 | bbb 2329 | @48c 2330 | bbb 2331 | @48d 2332 | bbb 2333 | @48e 2334 | bbb 2335 | @48f 2336 | 000 2337 | @490 2338 | 000 2339 | @491 2340 | eef 2341 | @492 2342 | fc1 2343 | @493 2344 | 740 2345 | @494 2346 | 740 2347 | @495 2348 | 740 2349 | @496 2350 | 740 2351 | @497 2352 | 740 2353 | @498 2354 | 740 2355 | @499 2356 | 740 2357 | @49a 2358 | 740 2359 | @49b 2360 | 740 2361 | @49c 2362 | 740 2363 | @49d 2364 | 740 2365 | @49e 2366 | 000 2367 | @49f 2368 | 000 2369 | @4a0 2370 | 000 2371 | @4a1 2372 | eef 2373 | @4a2 2374 | eef 2375 | @4a3 2376 | fc1 2377 | @4a4 2378 | fc1 2379 | @4a5 2380 | fc1 2381 | @4a6 2382 | fc1 2383 | @4a7 2384 | fc1 2385 | @4a8 2386 | fc1 2387 | @4a9 2388 | fc1 2389 | @4aa 2390 | fc1 2391 | @4ab 2392 | fc1 2393 | @4ac 2394 | c82 2395 | @4ad 2396 | c82 2397 | @4ae 2398 | c82 2399 | @4af 2400 | 000 2401 | @4b0 2402 | 00f 2403 | @4b1 2404 | 000 2405 | @4b2 2406 | eff 2407 | @4b3 2408 | eff 2409 | @4b4 2410 | eff 2411 | @4b5 2412 | eff 2413 | @4b6 2414 | eff 2415 | @4b7 2416 | eff 2417 | @4b8 2418 | eff 2419 | @4b9 2420 | eff 2421 | @4ba 2422 | eff 2423 | @4bb 2424 | eff 2425 | @4bc 2426 | eff 2427 | @4bd 2428 | eff 2429 | @4be 2430 | 000 2431 | @4bf 2432 | 00f 2433 | @4c0 2434 | 000 2435 | @4c1 2436 | eef 2437 | @4c2 2438 | eef 2439 | @4c3 2440 | eef 2441 | @4c4 2442 | bbb 2443 | @4c5 2444 | bbb 2445 | @4c6 2446 | eef 2447 | @4c7 2448 | eef 2449 | @4c8 2450 | eef 2451 | @4c9 2452 | bbb 2453 | @4ca 2454 | bbb 2455 | @4cb 2456 | bbb 2457 | @4cc 2458 | bbb 2459 | @4cd 2460 | bbb 2461 | @4ce 2462 | 555 2463 | @4cf 2464 | 000 2465 | @4d0 2466 | 000 2467 | @4d1 2468 | fc1 2469 | @4d2 2470 | 740 2471 | @4d3 2472 | 740 2473 | @4d4 2474 | 740 2475 | @4d5 2476 | 740 2477 | @4d6 2478 | 740 2479 | @4d7 2480 | 740 2481 | @4d8 2482 | 740 2483 | @4d9 2484 | 740 2485 | @4da 2486 | 740 2487 | @4db 2488 | 740 2489 | @4dc 2490 | 740 2491 | @4dd 2492 | 740 2493 | @4de 2494 | 000 2495 | @4df 2496 | 000 2497 | @4e0 2498 | 000 2499 | @4e1 2500 | eef 2501 | @4e2 2502 | fc1 2503 | @4e3 2504 | fc1 2505 | @4e4 2506 | fc1 2507 | @4e5 2508 | fc1 2509 | @4e6 2510 | fc1 2511 | @4e7 2512 | fc1 2513 | @4e8 2514 | fc1 2515 | @4e9 2516 | fc1 2517 | @4ea 2518 | fc1 2519 | @4eb 2520 | fc1 2521 | @4ec 2522 | fc1 2523 | @4ed 2524 | c82 2525 | @4ee 2526 | c82 2527 | @4ef 2528 | 000 2529 | @4f0 2530 | 00f 2531 | @4f1 2532 | 000 2533 | @4f2 2534 | eff 2535 | @4f3 2536 | eff 2537 | @4f4 2538 | eff 2539 | @4f5 2540 | eff 2541 | @4f6 2542 | eff 2543 | @4f7 2544 | eff 2545 | @4f8 2546 | eff 2547 | @4f9 2548 | eff 2549 | @4fa 2550 | eff 2551 | @4fb 2552 | eff 2553 | @4fc 2554 | eff 2555 | @4fd 2556 | eff 2557 | @4fe 2558 | 000 2559 | @4ff 2560 | 00f 2561 | @500 2562 | 000 2563 | @501 2564 | eef 2565 | @502 2566 | eef 2567 | @503 2568 | eef 2569 | @504 2570 | bbb 2571 | @505 2572 | bbb 2573 | @506 2574 | eef 2575 | @507 2576 | eef 2577 | @508 2578 | eef 2579 | @509 2580 | bbb 2581 | @50a 2582 | bbb 2583 | @50b 2584 | bbb 2585 | @50c 2586 | bbb 2587 | @50d 2588 | bbb 2589 | @50e 2590 | 555 2591 | @50f 2592 | 000 2593 | @510 2594 | 000 2595 | @511 2596 | fc1 2597 | @512 2598 | 740 2599 | @513 2600 | 740 2601 | @514 2602 | 740 2603 | @515 2604 | 740 2605 | @516 2606 | 740 2607 | @517 2608 | 740 2609 | @518 2610 | 740 2611 | @519 2612 | 740 2613 | @51a 2614 | 740 2615 | @51b 2616 | 740 2617 | @51c 2618 | 740 2619 | @51d 2620 | 740 2621 | @51e 2622 | 000 2623 | @51f 2624 | 000 2625 | @520 2626 | 000 2627 | @521 2628 | eef 2629 | @522 2630 | fc1 2631 | @523 2632 | fc1 2633 | @524 2634 | fc1 2635 | @525 2636 | fc1 2637 | @526 2638 | fc1 2639 | @527 2640 | fc1 2641 | @528 2642 | fc1 2643 | @529 2644 | fc1 2645 | @52a 2646 | fc1 2647 | @52b 2648 | fc1 2649 | @52c 2650 | fc1 2651 | @52d 2652 | c82 2653 | @52e 2654 | c82 2655 | @52f 2656 | 000 2657 | @530 2658 | 000 2659 | @531 2660 | eff 2661 | @532 2662 | eff 2663 | @533 2664 | eff 2665 | @534 2666 | eff 2667 | @535 2668 | eff 2669 | @536 2670 | eff 2671 | @537 2672 | eff 2673 | @538 2674 | eff 2675 | @539 2676 | eff 2677 | @53a 2678 | eff 2679 | @53b 2680 | eff 2681 | @53c 2682 | eff 2683 | @53d 2684 | eff 2685 | @53e 2686 | eff 2687 | @53f 2688 | 000 2689 | @540 2690 | 000 2691 | @541 2692 | eef 2693 | @542 2694 | eef 2695 | @543 2696 | bbb 2697 | @544 2698 | bbb 2699 | @545 2700 | bbb 2701 | @546 2702 | bbb 2703 | @547 2704 | bbb 2705 | @548 2706 | bbb 2707 | @549 2708 | bbb 2709 | @54a 2710 | bbb 2711 | @54b 2712 | bbb 2713 | @54c 2714 | bbb 2715 | @54d 2716 | bbb 2717 | @54e 2718 | 555 2719 | @54f 2720 | 000 2721 | @550 2722 | 000 2723 | @551 2724 | 740 2725 | @552 2726 | 740 2727 | @553 2728 | 740 2729 | @554 2730 | 740 2731 | @555 2732 | 740 2733 | @556 2734 | 740 2735 | @557 2736 | 740 2737 | @558 2738 | 740 2739 | @559 2740 | 740 2741 | @55a 2742 | 740 2743 | @55b 2744 | 740 2745 | @55c 2746 | 740 2747 | @55d 2748 | 740 2749 | @55e 2750 | 000 2751 | @55f 2752 | 000 2753 | @560 2754 | 000 2755 | @561 2756 | c82 2757 | @562 2758 | fc1 2759 | @563 2760 | fc1 2761 | @564 2762 | fc1 2763 | @565 2764 | 000 2765 | @566 2766 | fc1 2767 | @567 2768 | fc1 2769 | @568 2770 | fc1 2771 | @569 2772 | fc1 2773 | @56a 2774 | 000 2775 | @56b 2776 | fc1 2777 | @56c 2778 | fc1 2779 | @56d 2780 | c82 2781 | @56e 2782 | c82 2783 | @56f 2784 | 000 2785 | @570 2786 | 000 2787 | @571 2788 | eff 2789 | @572 2790 | eff 2791 | @573 2792 | eff 2793 | @574 2794 | eff 2795 | @575 2796 | eff 2797 | @576 2798 | 000 2799 | @577 2800 | eff 2801 | @578 2802 | eff 2803 | @579 2804 | 000 2805 | @57a 2806 | eff 2807 | @57b 2808 | eff 2809 | @57c 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eef 315 | @9d 316 | bbb 317 | @9e 318 | 555 319 | @9f 320 | 000 321 | @a0 322 | 000 323 | @a1 324 | bbb 325 | @a2 326 | bbb 327 | @a3 328 | eef 329 | @a4 330 | eef 331 | @a5 332 | eef 333 | @a6 334 | eef 335 | @a7 336 | eef 337 | @a8 338 | eef 339 | @a9 340 | eef 341 | @aa 342 | 000 343 | @ab 344 | eef 345 | @ac 346 | eef 347 | @ad 348 | bbb 349 | @ae 350 | 555 351 | @af 352 | 000 353 | @b0 354 | 000 355 | @b1 356 | bbb 357 | @b2 358 | bbb 359 | @b3 360 | eef 361 | @b4 362 | eef 363 | @b5 364 | eef 365 | @b6 366 | eef 367 | @b7 368 | eef 369 | @b8 370 | eef 371 | @b9 372 | eef 373 | @ba 374 | 000 375 | @bb 376 | eef 377 | @bc 378 | eef 379 | @bd 380 | bbb 381 | @be 382 | 555 383 | @bf 384 | 000 385 | @c0 386 | 000 387 | @c1 388 | bbb 389 | @c2 390 | eef 391 | @c3 392 | eef 393 | @c4 394 | eef 395 | @c5 396 | eef 397 | @c6 398 | eef 399 | @c7 400 | eef 401 | @c8 402 | eef 403 | @c9 404 | eef 405 | @ca 406 | eef 407 | @cb 408 | 000 409 | @cc 410 | eef 411 | @cd 412 | eef 413 | @ce 414 | 555 415 | @cf 416 | 000 417 | @d0 418 | 000 419 | @d1 420 | bbb 421 | @d2 422 | eef 423 | @d3 424 | eef 425 | @d4 426 | eef 427 | @d5 428 | eef 429 | @d6 430 | eef 431 | @d7 432 | eef 433 | @d8 434 | 000 435 | @d9 436 | eef 437 | @da 438 | eef 439 | @db 440 | eef 441 | @dc 442 | eef 443 | @dd 444 | eef 445 | @de 446 | 555 447 | @df 448 | 000 449 | @e0 450 | 000 451 | @e1 452 | bbb 453 | @e2 454 | eef 455 | @e3 456 | eef 457 | @e4 458 | eef 459 | @e5 460 | eef 461 | @e6 462 | eef 463 | @e7 464 | eef 465 | @e8 466 | eef 467 | @e9 468 | eef 469 | @ea 470 | 000 471 | @eb 472 | eef 473 | @ec 474 | eef 475 | @ed 476 | eef 477 | @ee 478 | 555 479 | @ef 480 | 000 481 | @f0 482 | 000 483 | @f1 484 | bbb 485 | @f2 486 | eef 487 | @f3 488 | eef 489 | @f4 490 | eef 491 | @f5 492 | eef 493 | @f6 494 | eef 495 | @f7 496 | eef 497 | @f8 498 | eef 499 | @f9 500 | eef 501 | @fa 502 | 000 503 | @fb 504 | eef 505 | @fc 506 | eef 507 | @fd 508 | eef 509 | @fe 510 | 555 511 | @ff 512 | 000 513 | @100 514 | 000 515 | @101 516 | bbb 517 | @102 518 | eef 519 | @103 520 | eef 521 | @104 522 | eef 523 | @105 524 | eef 525 | @106 526 | eef 527 | @107 528 | eef 529 | @108 530 | eef 531 | @109 532 | eef 533 | @10a 534 | eef 535 | @10b 536 | 000 537 | @10c 538 | eef 539 | @10d 540 | eef 541 | @10e 542 | 555 543 | @10f 544 | 000 545 | @110 546 | 000 547 | @111 548 | bbb 549 | @112 550 | eef 551 | @113 552 | eef 553 | @114 554 | eef 555 | @115 556 | eef 557 | @116 558 | eef 559 | @117 560 | eef 561 | @118 562 | 000 563 | @119 564 | eef 565 | @11a 566 | eef 567 | @11b 568 | eef 569 | @11c 570 | eef 571 | @11d 572 | eef 573 | @11e 574 | 555 575 | @11f 576 | 000 577 | @120 578 | 000 579 | @121 580 | bbb 581 | @122 582 | eef 583 | @123 584 | eef 585 | @124 586 | eef 587 | @125 588 | eef 589 | @126 590 | eef 591 | @127 592 | eef 593 | @128 594 | eef 595 | @129 596 | eef 597 | @12a 598 | 000 599 | @12b 600 | eef 601 | @12c 602 | eef 603 | @12d 604 | eef 605 | @12e 606 | 555 607 | @12f 608 | 000 609 | @130 610 | 000 611 | @131 612 | bbb 613 | @132 614 | eef 615 | @133 616 | eef 617 | @134 618 | eef 619 | @135 620 | eef 621 | @136 622 | eef 623 | @137 624 | eef 625 | @138 626 | eef 627 | @139 628 | eef 629 | @13a 630 | 000 631 | @13b 632 | eef 633 | @13c 634 | eef 635 | @13d 636 | eef 637 | @13e 638 | 555 639 | @13f 640 | 000 641 | @140 642 | 000 643 | @141 644 | bbb 645 | @142 646 | eef 647 | @143 648 | eef 649 | @144 650 | eef 651 | @145 652 | eef 653 | @146 654 | eef 655 | @147 656 | eef 657 | @148 658 | eef 659 | @149 660 | eef 661 | @14a 662 | eef 663 | @14b 664 | 000 665 | @14c 666 | eef 667 | @14d 668 | eef 669 | @14e 670 | 555 671 | @14f 672 | 000 673 | @150 674 | 000 675 | @151 676 | bbb 677 | @152 678 | eef 679 | @153 680 | eef 681 | @154 682 | eef 683 | @155 684 | eef 685 | @156 686 | eef 687 | @157 688 | eef 689 | @158 690 | 000 691 | @159 692 | eef 693 | @15a 694 | eef 695 | @15b 696 | eef 697 | @15c 698 | eef 699 | @15d 700 | eef 701 | @15e 702 | 555 703 | @15f 704 | 000 705 | @160 706 | 000 707 | @161 708 | bbb 709 | @162 710 | eef 711 | @163 712 | eef 713 | @164 714 | eef 715 | @165 716 | eef 717 | @166 718 | eef 719 | @167 720 | eef 721 | @168 722 | eef 723 | @169 724 | eef 725 | @16a 726 | 000 727 | @16b 728 | eef 729 | @16c 730 | eef 731 | @16d 732 | eef 733 | @16e 734 | 555 735 | @16f 736 | 000 737 | @170 738 | 000 739 | @171 740 | bbb 741 | @172 742 | eef 743 | @173 744 | eef 745 | @174 746 | eef 747 | @175 748 | eef 749 | @176 750 | eef 751 | @177 752 | eef 753 | @178 754 | eef 755 | @179 756 | eef 757 | @17a 758 | 000 759 | @17b 760 | eef 761 | @17c 762 | eef 763 | @17d 764 | eef 765 | @17e 766 | 555 767 | @17f 768 | 000 769 | @180 770 | 000 771 | @181 772 | bbb 773 | @182 774 | eef 775 | @183 776 | eef 777 | @184 778 | eef 779 | @185 780 | eef 781 | @186 782 | eef 783 | @187 784 | eef 785 | @188 786 | eef 787 | @189 788 | eef 789 | @18a 790 | eef 791 | @18b 792 | 000 793 | @18c 794 | eef 795 | @18d 796 | eef 797 | @18e 798 | 555 799 | @18f 800 | 000 801 | @190 802 | 000 803 | @191 804 | bbb 805 | @192 806 | eef 807 | @193 808 | eef 809 | @194 810 | eef 811 | @195 812 | eef 813 | @196 814 | eef 815 | @197 816 | eef 817 | @198 818 | 000 819 | @199 820 | eef 821 | @19a 822 | eef 823 | @19b 824 | eef 825 | @19c 826 | eef 827 | @19d 828 | eef 829 | @19e 830 | 555 831 | @19f 832 | 000 833 | @1a0 834 | 000 835 | @1a1 836 | bbb 837 | @1a2 838 | eef 839 | @1a3 840 | eef 841 | @1a4 842 | eef 843 | @1a5 844 | eef 845 | @1a6 846 | eef 847 | @1a7 848 | eef 849 | @1a8 850 | eef 851 | @1a9 852 | eef 853 | @1aa 854 | 000 855 | @1ab 856 | eef 857 | @1ac 858 | eef 859 | @1ad 860 | eef 861 | @1ae 862 | 555 863 | @1af 864 | 000 865 | @1b0 866 | 000 867 | @1b1 868 | bbb 869 | @1b2 870 | eef 871 | @1b3 872 | eef 873 | @1b4 874 | eef 875 | @1b5 876 | eef 877 | @1b6 878 | eef 879 | @1b7 880 | eef 881 | @1b8 882 | eef 883 | @1b9 884 | eef 885 | @1ba 886 | 000 887 | @1bb 888 | eef 889 | @1bc 890 | eef 891 | @1bd 892 | eef 893 | @1be 894 | 555 895 | @1bf 896 | 000 897 | @1c0 898 | 000 899 | @1c1 900 | bbb 901 | @1c2 902 | eef 903 | @1c3 904 | eef 905 | @1c4 906 | eef 907 | @1c5 908 | eef 909 | @1c6 910 | eef 911 | @1c7 912 | eef 913 | @1c8 914 | eef 915 | @1c9 916 | eef 917 | @1ca 918 | eef 919 | @1cb 920 | 000 921 | @1cc 922 | eef 923 | @1cd 924 | eef 925 | @1ce 926 | 555 927 | @1cf 928 | 000 929 | @1d0 930 | 000 931 | @1d1 932 | bbb 933 | @1d2 934 | eef 935 | @1d3 936 | eef 937 | @1d4 938 | eef 939 | @1d5 940 | eef 941 | @1d6 942 | eef 943 | @1d7 944 | eef 945 | @1d8 946 | 000 947 | @1d9 948 | eef 949 | @1da 950 | eef 951 | @1db 952 | eef 953 | @1dc 954 | eef 955 | @1dd 956 | eef 957 | @1de 958 | 555 959 | @1df 960 | 000 961 | @1e0 962 | 000 963 | @1e1 964 | bbb 965 | @1e2 966 | eef 967 | @1e3 968 | eef 969 | @1e4 970 | eef 971 | @1e5 972 | eef 973 | @1e6 974 | eef 975 | @1e7 976 | 000 977 | @1e8 978 | 000 979 | @1e9 980 | 000 981 | @1ea 982 | 000 983 | @1eb 984 | eef 985 | @1ec 986 | eef 987 | @1ed 988 | eef 989 | @1ee 990 | 555 991 | @1ef 992 | 000 993 | @1f0 994 | 000 995 | @1f1 996 | bbb 997 | @1f2 998 | eef 999 | @1f3 1000 | eef 1001 | @1f4 1002 | eef 1003 | @1f5 1004 | eef 1005 | @1f6 1006 | eef 1007 | @1f7 1008 | 000 1009 | @1f8 1010 | 000 1011 | @1f9 1012 | 000 1013 | @1fa 1014 | 000 1015 | @1fb 1016 | eef 1017 | @1fc 1018 | eef 1019 | @1fd 1020 | eef 1021 | @1fe 1022 | 555 1023 | @1ff 1024 | 000 1025 | @200 1026 | 000 1027 | @201 1028 | bbb 1029 | @202 1030 | eef 1031 | @203 1032 | eef 1033 | @204 1034 | eef 1035 | @205 1036 | eef 1037 | @206 1038 | eef 1039 | @207 1040 | eef 1041 | @208 1042 | 000 1043 | @209 1044 | 000 1045 | @20a 1046 | 000 1047 | @20b 1048 | 000 1049 | @20c 1050 | eef 1051 | @20d 1052 | eef 1053 | @20e 1054 | 555 1055 | @20f 1056 | 000 1057 | @210 1058 | 000 1059 | @211 1060 | bbb 1061 | @212 1062 | eef 1063 | @213 1064 | eef 1065 | @214 1066 | eef 1067 | @215 1068 | 000 1069 | @216 1070 | 000 1071 | @217 1072 | 000 1073 | @218 1074 | 000 1075 | @219 1076 | eef 1077 | @21a 1078 | eef 1079 | @21b 1080 | eef 1081 | @21c 1082 | eef 1083 | @21d 1084 | eef 1085 | @21e 1086 | 555 1087 | @21f 1088 | 000 1089 | @220 1090 | 000 1091 | @221 1092 | bbb 1093 | @222 1094 | eef 1095 | @223 1096 | eef 1097 | @224 1098 | eef 1099 | @225 1100 | 000 1101 | @226 1102 | bbb 1103 | @227 1104 | 555 1105 | @228 1106 | 000 1107 | @229 1108 | 000 1109 | @22a 1110 | 000 1111 | @22b 1112 | eef 1113 | @22c 1114 | eef 1115 | @22d 1116 | eef 1117 | @22e 1118 | 555 1119 | @22f 1120 | 000 1121 | @230 1122 | 000 1123 | @231 1124 | bbb 1125 | @232 1126 | eef 1127 | @233 1128 | eef 1129 | @234 1130 | eef 1131 | @235 1132 | 000 1133 | @236 1134 | bbb 1135 | @237 1136 | 555 1137 | @238 1138 | 000 1139 | @239 1140 | 000 1141 | @23a 1142 | 000 1143 | @23b 1144 | eef 1145 | @23c 1146 | eef 1147 | @23d 1148 | eef 1149 | @23e 1150 | 555 1151 | @23f 1152 | 000 1153 | @240 1154 | 000 1155 | @241 1156 | bbb 1157 | @242 1158 | eef 1159 | @243 1160 | eef 1161 | @244 1162 | eef 1163 | @245 1164 | eef 1165 | @246 1166 | 000 1167 | @247 1168 | bbb 1169 | @248 1170 | 555 1171 | @249 1172 | 000 1173 | @24a 1174 | 000 1175 | @24b 1176 | 000 1177 | @24c 1178 | eef 1179 | @24d 1180 | eef 1181 | @24e 1182 | 555 1183 | @24f 1184 | 000 1185 | @250 1186 | 000 1187 | @251 1188 | bbb 1189 | @252 1190 | eef 1191 | @253 1192 | 000 1193 | @254 1194 | bbb 1195 | @255 1196 | 555 1197 | @256 1198 | 000 1199 | @257 1200 | 000 1201 | @258 1202 | 000 1203 | @259 1204 | eef 1205 | @25a 1206 | eef 1207 | @25b 1208 | eef 1209 | @25c 1210 | eef 1211 | @25d 1212 | eef 1213 | @25e 1214 | 555 1215 | @25f 1216 | 000 1217 | @260 1218 | 000 1219 | @261 1220 | bbb 1221 | @262 1222 | eef 1223 | @263 1224 | eef 1225 | @264 1226 | 000 1227 | @265 1228 | bbb 1229 | @266 1230 | eef 1231 | @267 1232 | bbb 1233 | @268 1234 | 000 1235 | @269 1236 | 000 1237 | @26a 1238 | 000 1239 | @26b 1240 | eef 1241 | @26c 1242 | eef 1243 | @26d 1244 | eef 1245 | @26e 1246 | 555 1247 | @26f 1248 | 000 1249 | @270 1250 | 000 1251 | @271 1252 | bbb 1253 | @272 1254 | eef 1255 | @273 1256 | eef 1257 | @274 1258 | 000 1259 | @275 1260 | bbb 1261 | @276 1262 | eef 1263 | @277 1264 | bbb 1265 | @278 1266 | 000 1267 | @279 1268 | 000 1269 | @27a 1270 | 000 1271 | @27b 1272 | eef 1273 | @27c 1274 | eef 1275 | @27d 1276 | eef 1277 | @27e 1278 | 555 1279 | @27f 1280 | 000 1281 | @280 1282 | 000 1283 | @281 1284 | bbb 1285 | @282 1286 | eef 1287 | @283 1288 | eef 1289 | @284 1290 | eef 1291 | @285 1292 | 000 1293 | @286 1294 | bbb 1295 | @287 1296 | eef 1297 | @288 1298 | bbb 1299 | @289 1300 | 000 1301 | @28a 1302 | 000 1303 | @28b 1304 | 000 1305 | @28c 1306 | eef 1307 | @28d 1308 | eef 1309 | @28e 1310 | 555 1311 | @28f 1312 | 000 1313 | @290 1314 | 000 1315 | @291 1316 | bbb 1317 | @292 1318 | 000 1319 | @293 1320 | bbb 1321 | @294 1322 | eef 1323 | @295 1324 | bbb 1325 | @296 1326 | 000 1327 | @297 1328 | 000 1329 | @298 1330 | 000 1331 | @299 1332 | eef 1333 | @29a 1334 | eef 1335 | @29b 1336 | eef 1337 | @29c 1338 | eef 1339 | @29d 1340 | eef 1341 | @29e 1342 | 555 1343 | @29f 1344 | 000 1345 | @2a0 1346 | 000 1347 | @2a1 1348 | bbb 1349 | @2a2 1350 | eef 1351 | @2a3 1352 | eef 1353 | @2a4 1354 | 000 1355 | @2a5 1356 | 555 1357 | @2a6 1358 | bbb 1359 | @2a7 1360 | 000 1361 | @2a8 1362 | 000 1363 | @2a9 1364 | 000 1365 | @2aa 1366 | eef 1367 | @2ab 1368 | eef 1369 | @2ac 1370 | eef 1371 | @2ad 1372 | eef 1373 | @2ae 1374 | 555 1375 | @2af 1376 | 000 1377 | @2b0 1378 | 000 1379 | @2b1 1380 | bbb 1381 | @2b2 1382 | eef 1383 | @2b3 1384 | eef 1385 | @2b4 1386 | 000 1387 | @2b5 1388 | 555 1389 | @2b6 1390 | bbb 1391 | @2b7 1392 | 000 1393 | @2b8 1394 | 000 1395 | @2b9 1396 | 000 1397 | @2ba 1398 | eef 1399 | @2bb 1400 | eef 1401 | @2bc 1402 | eef 1403 | @2bd 1404 | eef 1405 | @2be 1406 | 555 1407 | @2bf 1408 | 000 1409 | @2c0 1410 | 000 1411 | @2c1 1412 | bbb 1413 | @2c2 1414 | eef 1415 | @2c3 1416 | eef 1417 | @2c4 1418 | eef 1419 | @2c5 1420 | 000 1421 | @2c6 1422 | 555 1423 | @2c7 1424 | bbb 1425 | @2c8 1426 | 000 1427 | @2c9 1428 | 000 1429 | @2ca 1430 | 000 1431 | @2cb 1432 | eef 1433 | @2cc 1434 | eef 1435 | @2cd 1436 | eef 1437 | @2ce 1438 | 555 1439 | @2cf 1440 | 000 1441 | @2d0 1442 | 000 1443 | @2d1 1444 | bbb 1445 | @2d2 1446 | 000 1447 | @2d3 1448 | 555 1449 | @2d4 1450 | bbb 1451 | @2d5 1452 | 000 1453 | @2d6 1454 | 000 1455 | @2d7 1456 | 000 1457 | @2d8 1458 | eef 1459 | @2d9 1460 | eef 1461 | @2da 1462 | eef 1463 | @2db 1464 | eef 1465 | @2dc 1466 | eef 1467 | @2dd 1468 | eef 1469 | @2de 1470 | 555 1471 | @2df 1472 | 000 1473 | @2e0 1474 | 000 1475 | @2e1 1476 | bbb 1477 | @2e2 1478 | eef 1479 | @2e3 1480 | eef 1481 | @2e4 1482 | eef 1483 | @2e5 1484 | 000 1485 | @2e6 1486 | 000 1487 | @2e7 1488 | 000 1489 | @2e8 1490 | eef 1491 | @2e9 1492 | eef 1493 | @2ea 1494 | eef 1495 | @2eb 1496 | eef 1497 | @2ec 1498 | eef 1499 | @2ed 1500 | eef 1501 | @2ee 1502 | 555 1503 | @2ef 1504 | 000 1505 | @2f0 1506 | 000 1507 | @2f1 1508 | bbb 1509 | @2f2 1510 | eef 1511 | @2f3 1512 | eef 1513 | @2f4 1514 | eef 1515 | @2f5 1516 | 000 1517 | @2f6 1518 | 000 1519 | @2f7 1520 | 000 1521 | @2f8 1522 | eef 1523 | @2f9 1524 | eef 1525 | @2fa 1526 | eef 1527 | @2fb 1528 | eef 1529 | @2fc 1530 | eef 1531 | @2fd 1532 | eef 1533 | @2fe 1534 | 555 1535 | @2ff 1536 | 000 1537 | @300 1538 | 000 1539 | @301 1540 | bbb 1541 | @302 1542 | eef 1543 | @303 1544 | eef 1545 | @304 1546 | eef 1547 | @305 1548 | eef 1549 | @306 1550 | 000 1551 | @307 1552 | 000 1553 | @308 1554 | 000 1555 | @309 1556 | eef 1557 | @30a 1558 | eef 1559 | @30b 1560 | eef 1561 | @30c 1562 | eef 1563 | @30d 1564 | eef 1565 | @30e 1566 | 555 1567 | @30f 1568 | 000 1569 | @310 1570 | 000 1571 | @311 1572 | bbb 1573 | @312 1574 | eef 1575 | @313 1576 | 000 1577 | @314 1578 | 000 1579 | @315 1580 | 000 1581 | @316 1582 | eef 1583 | @317 1584 | eef 1585 | @318 1586 | eef 1587 | @319 1588 | eef 1589 | @31a 1590 | eef 1591 | @31b 1592 | eef 1593 | @31c 1594 | eef 1595 | @31d 1596 | eef 1597 | @31e 1598 | 555 1599 | @31f 1600 | 000 1601 | @320 1602 | 000 1603 | @321 1604 | bbb 1605 | @322 1606 | eef 1607 | @323 1608 | eef 1609 | @324 1610 | eef 1611 | @325 1612 | eef 1613 | @326 1614 | eef 1615 | @327 1616 | eef 1617 | @328 1618 | eef 1619 | @329 1620 | eef 1621 | @32a 1622 | eef 1623 | @32b 1624 | eef 1625 | @32c 1626 | eef 1627 | @32d 1628 | eef 1629 | @32e 1630 | 555 1631 | @32f 1632 | 000 1633 | @330 1634 | 000 1635 | @331 1636 | bbb 1637 | @332 1638 | eef 1639 | @333 1640 | eef 1641 | @334 1642 | eef 1643 | @335 1644 | eef 1645 | @336 1646 | eef 1647 | @337 1648 | eef 1649 | @338 1650 | eef 1651 | @339 1652 | eef 1653 | @33a 1654 | eef 1655 | @33b 1656 | eef 1657 | @33c 1658 | eef 1659 | @33d 1660 | eef 1661 | @33e 1662 | 555 1663 | @33f 1664 | 000 1665 | @340 1666 | 000 1667 | @341 1668 | bbb 1669 | @342 1670 | bbb 1671 | @343 1672 | eef 1673 | @344 1674 | eef 1675 | @345 1676 | eef 1677 | @346 1678 | eef 1679 | @347 1680 | eef 1681 | @348 1682 | eef 1683 | @349 1684 | eef 1685 | @34a 1686 | eef 1687 | @34b 1688 | eef 1689 | @34c 1690 | eef 1691 | @34d 1692 | 555 1693 | @34e 1694 | 555 1695 | @34f 1696 | 000 1697 | @350 1698 | 000 1699 | @351 1700 | bbb 1701 | @352 1702 | bbb 1703 | @353 1704 | eef 1705 | @354 1706 | eef 1707 | @355 1708 | eef 1709 | @356 1710 | eef 1711 | @357 1712 | eef 1713 | @358 1714 | eef 1715 | @359 1716 | eef 1717 | @35a 1718 | eef 1719 | @35b 1720 | eef 1721 | @35c 1722 | eef 1723 | @35d 1724 | 555 1725 | @35e 1726 | 555 1727 | @35f 1728 | 000 1729 | @360 1730 | 000 1731 | @361 1732 | bbb 1733 | @362 1734 | bbb 1735 | @363 1736 | eef 1737 | @364 1738 | eef 1739 | @365 1740 | eef 1741 | @366 1742 | eef 1743 | @367 1744 | eef 1745 | @368 1746 | eef 1747 | @369 1748 | eef 1749 | @36a 1750 | eef 1751 | @36b 1752 | eef 1753 | @36c 1754 | eef 1755 | @36d 1756 | 555 1757 | @36e 1758 | 555 1759 | @36f 1760 | 000 1761 | @370 1762 | 000 1763 | @371 1764 | bbb 1765 | @372 1766 | bbb 1767 | @373 1768 | eef 1769 | @374 1770 | eef 1771 | @375 1772 | eef 1773 | @376 1774 | eef 1775 | @377 1776 | eef 1777 | @378 1778 | eef 1779 | @379 1780 | eef 1781 | @37a 1782 | eef 1783 | @37b 1784 | eef 1785 | @37c 1786 | eef 1787 | @37d 1788 | 555 1789 | @37e 1790 | 555 1791 | @37f 1792 | 000 1793 | @380 1794 | 000 1795 | @381 1796 | 000 1797 | @382 1798 | 555 1799 | @383 1800 | 555 1801 | @384 1802 | 555 1803 | @385 1804 | 555 1805 | @386 1806 | 555 1807 | @387 1808 | 555 1809 | @388 1810 | 555 1811 | @389 1812 | 555 1813 | @38a 1814 | 555 1815 | @38b 1816 | 555 1817 | @38c 1818 | 555 1819 | @38d 1820 | 555 1821 | @38e 1822 | 000 1823 | @38f 1824 | 000 1825 | @390 1826 | 000 1827 | @391 1828 | 000 1829 | @392 1830 | 555 1831 | @393 1832 | 555 1833 | @394 1834 | 555 1835 | @395 1836 | 555 1837 | @396 1838 | 555 1839 | @397 1840 | 555 1841 | @398 1842 | 555 1843 | @399 1844 | 555 1845 | @39a 1846 | 555 1847 | @39b 1848 | 555 1849 | @39c 1850 | 555 1851 | @39d 1852 | 555 1853 | @39e 1854 | 000 1855 | @39f 1856 | 000 1857 | @3a0 1858 | 000 1859 | @3a1 1860 | 000 1861 | @3a2 1862 | 555 1863 | @3a3 1864 | 555 1865 | @3a4 1866 | 555 1867 | @3a5 1868 | 555 1869 | @3a6 1870 | 555 1871 | @3a7 1872 | 555 1873 | @3a8 1874 | 555 1875 | @3a9 1876 | 555 1877 | @3aa 1878 | 555 1879 | @3ab 1880 | 555 1881 | @3ac 1882 | 555 1883 | @3ad 1884 | 555 1885 | @3ae 1886 | 000 1887 | @3af 1888 | 000 1889 | @3b0 1890 | 000 1891 | @3b1 1892 | 000 1893 | @3b2 1894 | 555 1895 | @3b3 1896 | 555 1897 | @3b4 1898 | 555 1899 | @3b5 1900 | 555 1901 | @3b6 1902 | 555 1903 | @3b7 1904 | 555 1905 | @3b8 1906 | 555 1907 | @3b9 1908 | 555 1909 | @3ba 1910 | 555 1911 | @3bb 1912 | 555 1913 | @3bc 1914 | 555 1915 | @3bd 1916 | 555 1917 | @3be 1918 | 000 1919 | @3bf 1920 | 000 1921 | @3c0 1922 | 00f 1923 | @3c1 1924 | 000 1925 | @3c2 1926 | 000 1927 | @3c3 1928 | 000 1929 | @3c4 1930 | 000 1931 | @3c5 1932 | 000 1933 | @3c6 1934 | 000 1935 | @3c7 1936 | 000 1937 | @3c8 1938 | 000 1939 | @3c9 1940 | 000 1941 | @3ca 1942 | 000 1943 | @3cb 1944 | 000 1945 | @3cc 1946 | 000 1947 | @3cd 1948 | 000 1949 | @3ce 1950 | 000 1951 | @3cf 1952 | 00f 1953 | @3d0 1954 | 00f 1955 | @3d1 1956 | 000 1957 | @3d2 1958 | 000 1959 | @3d3 1960 | 000 1961 | @3d4 1962 | 000 1963 | @3d5 1964 | 000 1965 | @3d6 1966 | 000 1967 | @3d7 1968 | 000 1969 | @3d8 1970 | 000 1971 | @3d9 1972 | 000 1973 | @3da 1974 | 000 1975 | @3db 1976 | 000 1977 | @3dc 1978 | 000 1979 | @3dd 1980 | 000 1981 | @3de 1982 | 000 1983 | @3df 1984 | 00f 1985 | @3e0 1986 | 00f 1987 | @3e1 1988 | 000 1989 | @3e2 1990 | 000 1991 | @3e3 1992 | 000 1993 | @3e4 1994 | 000 1995 | @3e5 1996 | 000 1997 | @3e6 1998 | 000 1999 | @3e7 2000 | 000 2001 | @3e8 2002 | 000 2003 | @3e9 2004 | 000 2005 | @3ea 2006 | 000 2007 | @3eb 2008 | 000 2009 | @3ec 2010 | 000 2011 | @3ed 2012 | 000 2013 | @3ee 2014 | 000 2015 | @3ef 2016 | 00f 2017 | @3f0 2018 | 00f 2019 | @3f1 2020 | 000 2021 | @3f2 2022 | 000 2023 | @3f3 2024 | 000 2025 | @3f4 2026 | 000 2027 | @3f5 2028 | 000 2029 | @3f6 2030 | 000 2031 | @3f7 2032 | 000 2033 | @3f8 2034 | 000 2035 | @3f9 2036 | 000 2037 | @3fa 2038 | 000 2039 | @3fb 2040 | 000 2041 | @3fc 2042 | 000 2043 | @3fd 2044 | 000 2045 | @3fe 2046 | 000 2047 | @3ff 2048 | 00f 2049 | @400 2050 | 00f 2051 | @401 2052 | 00f 2053 | @402 2054 | 000 2055 | @403 2056 | 000 2057 | @404 2058 | 000 2059 | @405 2060 | 000 2061 | @406 2062 | 000 2063 | @407 2064 | 000 2065 | @408 2066 | 000 2067 | @409 2068 | 000 2069 | @40a 2070 | 000 2071 | @40b 2072 | 000 2073 | @40c 2074 | 000 2075 | @40d 2076 | 000 2077 | @40e 2078 | 00f 2079 | @40f 2080 | 00f 2081 | @410 2082 | 00f 2083 | @411 2084 | 00f 2085 | @412 2086 | 000 2087 | @413 2088 | 000 2089 | @414 2090 | 000 2091 | @415 2092 | 000 2093 | @416 2094 | 000 2095 | @417 2096 | 000 2097 | @418 2098 | 000 2099 | @419 2100 | 000 2101 | @41a 2102 | 000 2103 | @41b 2104 | 000 2105 | @41c 2106 | 000 2107 | @41d 2108 | 000 2109 | @41e 2110 | 00f 2111 | @41f 2112 | 00f 2113 | @420 2114 | 00f 2115 | @421 2116 | 00f 2117 | @422 2118 | 000 2119 | @423 2120 | 000 2121 | @424 2122 | 000 2123 | @425 2124 | 000 2125 | @426 2126 | 000 2127 | @427 2128 | 000 2129 | @428 2130 | 000 2131 | @429 2132 | 000 2133 | @42a 2134 | 000 2135 | @42b 2136 | 000 2137 | @42c 2138 | 000 2139 | @42d 2140 | 000 2141 | @42e 2142 | 00f 2143 | @42f 2144 | 00f 2145 | @430 2146 | 00f 2147 | @431 2148 | 00f 2149 | @432 2150 | 00f 2151 | @433 2152 | 000 2153 | @434 2154 | 000 2155 | @435 2156 | 000 2157 | @436 2158 | 000 2159 | @437 2160 | 000 2161 | @438 2162 | 000 2163 | @439 2164 | 000 2165 | @43a 2166 | 000 2167 | @43b 2168 | 000 2169 | @43c 2170 | 000 2171 | @43d 2172 | 00f 2173 | @43e 2174 | 00f 2175 | @43f 2176 | 00f 2177 | @440 2178 | 00f 2179 | @441 2180 | 000 2181 | @442 2182 | eef 2183 | @443 2184 | eef 2185 | @444 2186 | eef 2187 | @445 2188 | eef 2189 | @446 2190 | eef 2191 | @447 2192 | eef 2193 | @448 2194 | eef 2195 | @449 2196 | eef 2197 | @44a 2198 | eef 2199 | @44b 2200 | eef 2201 | @44c 2202 | bbb 2203 | @44d 2204 | bbb 2205 | @44e 2206 | 000 2207 | @44f 2208 | 00f 2209 | @450 2210 | 00f 2211 | @451 2212 | 000 2213 | @452 2214 | eef 2215 | @453 2216 | fc1 2217 | @454 2218 | fc1 2219 | @455 2220 | 740 2221 | @456 2222 | 740 2223 | @457 2224 | 740 2225 | @458 2226 | 740 2227 | @459 2228 | 740 2229 | @45a 2230 | 740 2231 | @45b 2232 | 740 2233 | @45c 2234 | 740 2235 | @45d 2236 | 000 2237 | @45e 2238 | 000 2239 | @45f 2240 | 00f 2241 | @460 2242 | 00f 2243 | @461 2244 | 000 2245 | @462 2246 | eef 2247 | @463 2248 | eef 2249 | @464 2250 | eef 2251 | @465 2252 | c82 2253 | @466 2254 | c82 2255 | @467 2256 | c82 2257 | @468 2258 | c82 2259 | @469 2260 | c82 2261 | @46a 2262 | c82 2263 | @46b 2264 | c82 2265 | @46c 2266 | c82 2267 | @46d 2268 | c82 2269 | @46e 2270 | 000 2271 | @46f 2272 | 00f 2273 | @470 2274 | 00f 2275 | @471 2276 | 00f 2277 | @472 2278 | 000 2279 | @473 2280 | eff 2281 | @474 2282 | eff 2283 | @475 2284 | eff 2285 | @476 2286 | eff 2287 | @477 2288 | eff 2289 | @478 2290 | eff 2291 | @479 2292 | eff 2293 | @47a 2294 | eff 2295 | @47b 2296 | eff 2297 | @47c 2298 | eff 2299 | @47d 2300 | 000 2301 | @47e 2302 | 00f 2303 | @47f 2304 | 00f 2305 | @480 2306 | 00f 2307 | @481 2308 | 000 2309 | @482 2310 | eef 2311 | @483 2312 | eef 2313 | @484 2314 | eef 2315 | @485 2316 | eef 2317 | @486 2318 | eef 2319 | @487 2320 | eef 2321 | @488 2322 | eef 2323 | @489 2324 | bbb 2325 | @48a 2326 | bbb 2327 | @48b 2328 | bbb 2329 | @48c 2330 | bbb 2331 | @48d 2332 | bbb 2333 | @48e 2334 | bbb 2335 | @48f 2336 | 000 2337 | @490 2338 | 000 2339 | @491 2340 | eef 2341 | @492 2342 | fc1 2343 | @493 2344 | 740 2345 | @494 2346 | 740 2347 | @495 2348 | 740 2349 | @496 2350 | 740 2351 | @497 2352 | 740 2353 | @498 2354 | 740 2355 | @499 2356 | 740 2357 | @49a 2358 | 740 2359 | @49b 2360 | 740 2361 | @49c 2362 | 740 2363 | @49d 2364 | 740 2365 | @49e 2366 | 000 2367 | @49f 2368 | 000 2369 | @4a0 2370 | 000 2371 | @4a1 2372 | eef 2373 | @4a2 2374 | eef 2375 | @4a3 2376 | fc1 2377 | @4a4 2378 | fc1 2379 | @4a5 2380 | fc1 2381 | @4a6 2382 | fc1 2383 | @4a7 2384 | fc1 2385 | @4a8 2386 | fc1 2387 | @4a9 2388 | fc1 2389 | @4aa 2390 | fc1 2391 | @4ab 2392 | fc1 2393 | @4ac 2394 | c82 2395 | @4ad 2396 | c82 2397 | @4ae 2398 | c82 2399 | @4af 2400 | 000 2401 | @4b0 2402 | 00f 2403 | @4b1 2404 | 000 2405 | @4b2 2406 | eff 2407 | @4b3 2408 | eff 2409 | @4b4 2410 | eff 2411 | @4b5 2412 | eff 2413 | @4b6 2414 | eff 2415 | @4b7 2416 | eff 2417 | @4b8 2418 | eff 2419 | @4b9 2420 | eff 2421 | @4ba 2422 | eff 2423 | @4bb 2424 | eff 2425 | @4bc 2426 | eff 2427 | @4bd 2428 | eff 2429 | @4be 2430 | 000 2431 | @4bf 2432 | 00f 2433 | @4c0 2434 | 000 2435 | @4c1 2436 | eef 2437 | @4c2 2438 | eef 2439 | @4c3 2440 | eef 2441 | @4c4 2442 | bbb 2443 | @4c5 2444 | bbb 2445 | @4c6 2446 | eef 2447 | @4c7 2448 | eef 2449 | @4c8 2450 | eef 2451 | @4c9 2452 | bbb 2453 | @4ca 2454 | bbb 2455 | @4cb 2456 | bbb 2457 | @4cc 2458 | bbb 2459 | @4cd 2460 | bbb 2461 | @4ce 2462 | 555 2463 | @4cf 2464 | 000 2465 | @4d0 2466 | 000 2467 | @4d1 2468 | fc1 2469 | @4d2 2470 | 740 2471 | @4d3 2472 | 740 2473 | @4d4 2474 | 740 2475 | @4d5 2476 | 740 2477 | @4d6 2478 | 740 2479 | @4d7 2480 | 740 2481 | @4d8 2482 | 740 2483 | @4d9 2484 | 740 2485 | @4da 2486 | 740 2487 | @4db 2488 | 740 2489 | @4dc 2490 | 740 2491 | @4dd 2492 | 740 2493 | @4de 2494 | 000 2495 | @4df 2496 | 000 2497 | @4e0 2498 | 000 2499 | @4e1 2500 | eef 2501 | @4e2 2502 | fc1 2503 | @4e3 2504 | fc1 2505 | @4e4 2506 | fc1 2507 | @4e5 2508 | fc1 2509 | @4e6 2510 | fc1 2511 | @4e7 2512 | fc1 2513 | @4e8 2514 | fc1 2515 | @4e9 2516 | fc1 2517 | @4ea 2518 | fc1 2519 | @4eb 2520 | fc1 2521 | @4ec 2522 | fc1 2523 | @4ed 2524 | c82 2525 | @4ee 2526 | c82 2527 | @4ef 2528 | 000 2529 | @4f0 2530 | 00f 2531 | @4f1 2532 | 000 2533 | @4f2 2534 | eff 2535 | @4f3 2536 | eff 2537 | @4f4 2538 | eff 2539 | @4f5 2540 | eff 2541 | @4f6 2542 | eff 2543 | @4f7 2544 | eff 2545 | @4f8 2546 | eff 2547 | @4f9 2548 | eff 2549 | @4fa 2550 | eff 2551 | @4fb 2552 | eff 2553 | @4fc 2554 | eff 2555 | @4fd 2556 | eff 2557 | @4fe 2558 | 000 2559 | @4ff 2560 | 00f 2561 | @500 2562 | 000 2563 | @501 2564 | eef 2565 | @502 2566 | eef 2567 | @503 2568 | eef 2569 | @504 2570 | bbb 2571 | @505 2572 | bbb 2573 | @506 2574 | eef 2575 | @507 2576 | eef 2577 | @508 2578 | eef 2579 | @509 2580 | bbb 2581 | @50a 2582 | bbb 2583 | @50b 2584 | bbb 2585 | @50c 2586 | bbb 2587 | @50d 2588 | bbb 2589 | @50e 2590 | 555 2591 | @50f 2592 | 000 2593 | @510 2594 | 000 2595 | @511 2596 | fc1 2597 | @512 2598 | 740 2599 | @513 2600 | 740 2601 | @514 2602 | 740 2603 | @515 2604 | 740 2605 | @516 2606 | 740 2607 | @517 2608 | 740 2609 | @518 2610 | 740 2611 | @519 2612 | 740 2613 | @51a 2614 | 740 2615 | @51b 2616 | 740 2617 | @51c 2618 | 740 2619 | @51d 2620 | 740 2621 | @51e 2622 | 000 2623 | @51f 2624 | 000 2625 | @520 2626 | 000 2627 | @521 2628 | eef 2629 | @522 2630 | fc1 2631 | @523 2632 | fc1 2633 | @524 2634 | fc1 2635 | @525 2636 | fc1 2637 | @526 2638 | fc1 2639 | @527 2640 | fc1 2641 | @528 2642 | fc1 2643 | @529 2644 | fc1 2645 | @52a 2646 | fc1 2647 | @52b 2648 | fc1 2649 | @52c 2650 | fc1 2651 | @52d 2652 | c82 2653 | @52e 2654 | c82 2655 | @52f 2656 | 000 2657 | @530 2658 | 000 2659 | @531 2660 | eff 2661 | @532 2662 | eff 2663 | @533 2664 | eff 2665 | @534 2666 | eff 2667 | @535 2668 | eff 2669 | @536 2670 | eff 2671 | @537 2672 | eff 2673 | @538 2674 | eff 2675 | @539 2676 | eff 2677 | @53a 2678 | eff 2679 | @53b 2680 | eff 2681 | @53c 2682 | eff 2683 | @53d 2684 | eff 2685 | @53e 2686 | eff 2687 | @53f 2688 | 000 2689 | @540 2690 | 000 2691 | @541 2692 | eef 2693 | @542 2694 | eef 2695 | @543 2696 | bbb 2697 | @544 2698 | bbb 2699 | @545 2700 | bbb 2701 | @546 2702 | bbb 2703 | @547 2704 | bbb 2705 | @548 2706 | bbb 2707 | @549 2708 | bbb 2709 | @54a 2710 | bbb 2711 | @54b 2712 | bbb 2713 | @54c 2714 | bbb 2715 | @54d 2716 | bbb 2717 | @54e 2718 | 555 2719 | @54f 2720 | 000 2721 | @550 2722 | 000 2723 | @551 2724 | 740 2725 | @552 2726 | 740 2727 | @553 2728 | 740 2729 | @554 2730 | 740 2731 | @555 2732 | 740 2733 | @556 2734 | 740 2735 | @557 2736 | 740 2737 | @558 2738 | 740 2739 | @559 2740 | 740 2741 | @55a 2742 | 740 2743 | @55b 2744 | 740 2745 | @55c 2746 | 740 2747 | @55d 2748 | 740 2749 | @55e 2750 | 000 2751 | @55f 2752 | 000 2753 | @560 2754 | 000 2755 | @561 2756 | c82 2757 | @562 2758 | fc1 2759 | @563 2760 | fc1 2761 | @564 2762 | fc1 2763 | @565 2764 | 000 2765 | @566 2766 | fc1 2767 | @567 2768 | fc1 2769 | @568 2770 | fc1 2771 | @569 2772 | fc1 2773 | @56a 2774 | 000 2775 | @56b 2776 | fc1 2777 | @56c 2778 | fc1 2779 | @56d 2780 | c82 2781 | @56e 2782 | c82 2783 | @56f 2784 | 000 2785 | @570 2786 | 000 2787 | @571 2788 | eff 2789 | @572 2790 | eff 2791 | @573 2792 | eff 2793 | @574 2794 | eff 2795 | @575 2796 | eff 2797 | @576 2798 | 000 2799 | @577 2800 | eff 2801 | @578 2802 | eff 2803 | @579 2804 | 000 2805 | @57a 2806 | eff 2807 | @57b 2808 | eff 2809 | @57c 2810 | eff 2811 | @57d 2812 | eff 2813 | @57e 2814 | eff 2815 | @57f 2816 | 000 2817 | @580 2818 | 000 2819 | @581 2820 | eef 2821 | @582 2822 | eef 2823 | @583 2824 | bbb 2825 | @584 2826 | bbb 2827 | @585 2828 | bbb 2829 | @586 2830 | eef 2831 | @587 2832 | eef 2833 | @588 2834 | bbb 2835 | @589 2836 | bbb 2837 | @58a 2838 | bbb 2839 | @58b 2840 | bbb 2841 | @58c 2842 | 555 2843 | @58d 2844 | 555 2845 | @58e 2846 | 555 2847 | @58f 2848 | 000 2849 | @590 2850 | 000 2851 | @591 2852 | fc1 2853 | @592 2854 | 740 2855 | @593 2856 | 740 2857 | @594 2858 | 000 2859 | @595 2860 | 740 2861 | @596 2862 | 740 2863 | @597 2864 | 740 2865 | @598 2866 | 740 2867 | @599 2868 | 740 2869 | @59a 2870 | 740 2871 | @59b 2872 | 000 2873 | @59c 2874 | 740 2875 | @59d 2876 | 740 2877 | @59e 2878 | 000 2879 | @59f 2880 | 000 2881 | @5a0 2882 | 000 2883 | @5a1 2884 | eef 2885 | @5a2 2886 | fc1 2887 | @5a3 2888 | fc1 2889 | @5a4 2890 | fc1 2891 | @5a5 2892 | 000 2893 | @5a6 2894 | fc1 2895 | @5a7 2896 | fc1 2897 | @5a8 2898 | fc1 2899 | @5a9 2900 | fc1 2901 | @5aa 2902 | 000 2903 | @5ab 2904 | fc1 2905 | @5ac 2906 | fc1 2907 | @5ad 2908 | c82 2909 | @5ae 2910 | c82 2911 | @5af 2912 | 000 2913 | @5b0 2914 | 000 2915 | @5b1 2916 | eff 2917 | @5b2 2918 | eff 2919 | @5b3 2920 | eff 2921 | @5b4 2922 | eff 2923 | @5b5 2924 | eff 2925 | @5b6 2926 | 000 2927 | @5b7 2928 | eff 2929 | @5b8 2930 | eff 2931 | @5b9 2932 | 000 2933 | @5ba 2934 | eff 2935 | @5bb 2936 | eff 2937 | @5bc 2938 | eff 2939 | @5bd 2940 | eff 2941 | @5be 2942 | eff 2943 | @5bf 2944 | 000 2945 | @5c0 2946 | 000 2947 | @5c1 2948 | eef 2949 | @5c2 2950 | eef 2951 | @5c3 2952 | bbb 2953 | @5c4 2954 | bbb 2955 | @5c5 2956 | bbb 2957 | @5c6 2958 | eef 2959 | @5c7 2960 | eef 2961 | @5c8 2962 | bbb 2963 | @5c9 2964 | bbb 2965 | @5ca 2966 | 555 2967 | @5cb 2968 | 555 2969 | @5cc 2970 | bbb 2971 | @5cd 2972 | 555 2973 | @5ce 2974 | 555 2975 | @5cf 2976 | 000 2977 | @5d0 2978 | 000 2979 | @5d1 2980 | 740 2981 | @5d2 2982 | 740 2983 | @5d3 2984 | 740 2985 | @5d4 2986 | 740 2987 | @5d5 2988 | 000 2989 | @5d6 2990 | 740 2991 | @5d7 2992 | 740 2993 | @5d8 2994 | 740 2995 | @5d9 2996 | 740 2997 | @5da 2998 | 000 2999 | @5db 3000 | 740 3001 | @5dc 3002 | 740 3003 | @5dd 3004 | 740 3005 | @5de 3006 | 000 3007 | @5df 3008 | 000 3009 | @5e0 3010 | 000 3011 | @5e1 3012 | c82 3013 | @5e2 3014 | fc1 3015 | @5e3 3016 | fc1 3017 | @5e4 3018 | fc1 3019 | @5e5 3020 | 000 3021 | @5e6 3022 | fc1 3023 | @5e7 3024 | fc1 3025 | @5e8 3026 | fc1 3027 | @5e9 3028 | fc1 3029 | @5ea 3030 | 000 3031 | @5eb 3032 | fc1 3033 | @5ec 3034 | fc1 3035 | @5ed 3036 | c82 3037 | @5ee 3038 | c82 3039 | @5ef 3040 | 000 3041 | @5f0 3042 | 000 3043 | @5f1 3044 | eff 3045 | @5f2 3046 | eff 3047 | @5f3 3048 | eff 3049 | @5f4 3050 | eff 3051 | @5f5 3052 | eff 3053 | @5f6 3054 | 000 3055 | @5f7 3056 | eff 3057 | @5f8 3058 | eff 3059 | @5f9 3060 | 000 3061 | @5fa 3062 | eff 3063 | @5fb 3064 | eff 3065 | @5fc 3066 | eff 3067 | @5fd 3068 | eff 3069 | @5fe 3070 | eff 3071 | @5ff 3072 | 000 3073 | @600 3074 | 000 3075 | @601 3076 | bbb 3077 | @602 3078 | bbb 3079 | @603 3080 | bbb 3081 | @604 3082 | bbb 3083 | @605 3084 | bbb 3085 | @606 3086 | eef 3087 | @607 3088 | eef 3089 | @608 3090 | bbb 3091 | @609 3092 | bbb 3093 | @60a 3094 | 555 3095 | @60b 3096 | 555 3097 | @60c 3098 | bbb 3099 | @60d 3100 | 555 3101 | @60e 3102 | 555 3103 | @60f 3104 | 000 3105 | @610 3106 | 000 3107 | @611 3108 | 740 3109 | @612 3110 | 740 3111 | @613 3112 | 740 3113 | @614 3114 | 740 3115 | @615 3116 | 740 3117 | @616 3118 | 000 3119 | @617 3120 | 740 3121 | @618 3122 | 740 3123 | @619 3124 | 000 3125 | @61a 3126 | 740 3127 | @61b 3128 | 740 3129 | @61c 3130 | 740 3131 | @61d 3132 | 740 3133 | @61e 3134 | 000 3135 | @61f 3136 | 000 3137 | @620 3138 | 000 3139 | @621 3140 | c82 3141 | @622 3142 | fc1 3143 | @623 3144 | fc1 3145 | @624 3146 | fc1 3147 | @625 3148 | 000 3149 | @626 3150 | fc1 3151 | @627 3152 | fc1 3153 | @628 3154 | fc1 3155 | @629 3156 | fc1 3157 | @62a 3158 | 000 3159 | @62b 3160 | fc1 3161 | @62c 3162 | fc1 3163 | @62d 3164 | c82 3165 | @62e 3166 | c82 3167 | @62f 3168 | 000 3169 | @630 3170 | 000 3171 | @631 3172 | eff 3173 | @632 3174 | eff 3175 | @633 3176 | eff 3177 | @634 3178 | eff 3179 | @635 3180 | eff 3181 | @636 3182 | eff 3183 | @637 3184 | eff 3185 | @638 3186 | eff 3187 | @639 3188 | eff 3189 | @63a 3190 | eff 3191 | @63b 3192 | eff 3193 | @63c 3194 | eff 3195 | @63d 3196 | eff 3197 | @63e 3198 | eff 3199 | @63f 3200 | 000 3201 | @640 3202 | 000 3203 | @641 3204 | bbb 3205 | @642 3206 | bbb 3207 | @643 3208 | 555 3209 | @644 3210 | bbb 3211 | @645 3212 | bbb 3213 | @646 3214 | bbb 3215 | @647 3216 | bbb 3217 | @648 3218 | bbb 3219 | @649 3220 | bbb 3221 | @64a 3222 | 555 3223 | @64b 3224 | 555 3225 | @64c 3226 | 555 3227 | @64d 3228 | 555 3229 | @64e 3230 | 555 3231 | @64f 3232 | 000 3233 | @650 3234 | 000 3235 | @651 3236 | 740 3237 | @652 3238 | 740 3239 | @653 3240 | 740 3241 | @654 3242 | 740 3243 | @655 3244 | 740 3245 | @656 3246 | 740 3247 | @657 3248 | 740 3249 | @658 3250 | 740 3251 | @659 3252 | 740 3253 | @65a 3254 | 740 3255 | @65b 3256 | 740 3257 | @65c 3258 | 740 3259 | @65d 3260 | 740 3261 | @65e 3262 | 000 3263 | @65f 3264 | 000 3265 | @660 3266 | 000 3267 | @661 3268 | c82 3269 | @662 3270 | fc1 3271 | @663 3272 | fc1 3273 | @664 3274 | fc1 3275 | @665 3276 | fc1 3277 | @666 3278 | fc1 3279 | @667 3280 | fc1 3281 | @668 3282 | fc1 3283 | @669 3284 | fc1 3285 | @66a 3286 | fc1 3287 | @66b 3288 | fc1 3289 | @66c 3290 | fc1 3291 | @66d 3292 | c82 3293 | @66e 3294 | c82 3295 | @66f 3296 | 000 3297 | @670 3298 | 000 3299 | @671 3300 | eff 3301 | @672 3302 | eff 3303 | @673 3304 | eff 3305 | @674 3306 | f08 3307 | @675 3308 | eff 3309 | @676 3310 | eff 3311 | @677 3312 | eff 3313 | @678 3314 | eff 3315 | @679 3316 | eff 3317 | @67a 3318 | eff 3319 | @67b 3320 | f08 3321 | @67c 3322 | eff 3323 | @67d 3324 | eff 3325 | @67e 3326 | eff 3327 | @67f 3328 | 000 3329 | @680 3330 | 000 3331 | @681 3332 | bbb 3333 | @682 3334 | bbb 3335 | @683 3336 | bbb 3337 | @684 3338 | bbb 3339 | @685 3340 | bbb 3341 | @686 3342 | bbb 3343 | @687 3344 | bbb 3345 | @688 3346 | 555 3347 | @689 3348 | 555 3349 | @68a 3350 | 555 3351 | @68b 3352 | 555 3353 | @68c 3354 | 555 3355 | @68d 3356 | 555 3357 | @68e 3358 | 555 3359 | @68f 3360 | 000 3361 | @690 3362 | 000 3363 | @691 3364 | 740 3365 | @692 3366 | 740 3367 | @693 3368 | 740 3369 | @694 3370 | 740 3371 | @695 3372 | 740 3373 | @696 3374 | 740 3375 | @697 3376 | 740 3377 | @698 3378 | 740 3379 | @699 3380 | 740 3381 | @69a 3382 | 740 3383 | @69b 3384 | 740 3385 | @69c 3386 | 740 3387 | @69d 3388 | 740 3389 | @69e 3390 | 000 3391 | @69f 3392 | 000 3393 | @6a0 3394 | 000 3395 | @6a1 3396 | c82 3397 | @6a2 3398 | fc1 3399 | @6a3 3400 | fc1 3401 | @6a4 3402 | fc1 3403 | @6a5 3404 | fc1 3405 | @6a6 3406 | fc1 3407 | @6a7 3408 | fc1 3409 | @6a8 3410 | fc1 3411 | @6a9 3412 | fc1 3413 | @6aa 3414 | fc1 3415 | @6ab 3416 | fc1 3417 | @6ac 3418 | fc1 3419 | @6ad 3420 | c82 3421 | @6ae 3422 | c82 3423 | @6af 3424 | 000 3425 | @6b0 3426 | 000 3427 | @6b1 3428 | eff 3429 | @6b2 3430 | eff 3431 | @6b3 3432 | f08 3433 | @6b4 3434 | f08 3435 | @6b5 3436 | eff 3437 | @6b6 3438 | eff 3439 | @6b7 3440 | eff 3441 | @6b8 3442 | eff 3443 | @6b9 3444 | eff 3445 | @6ba 3446 | eff 3447 | @6bb 3448 | f08 3449 | @6bc 3450 | f08 3451 | @6bd 3452 | eff 3453 | @6be 3454 | eff 3455 | @6bf 3456 | 000 3457 | @6c0 3458 | 000 3459 | @6c1 3460 | bbb 3461 | @6c2 3462 | bbb 3463 | @6c3 3464 | 555 3465 | @6c4 3466 | eef 3467 | @6c5 3468 | eef 3469 | @6c6 3470 | 555 3471 | @6c7 3472 | 555 3473 | @6c8 3474 | 555 3475 | @6c9 3476 | 555 3477 | @6ca 3478 | 555 3479 | @6cb 3480 | bbb 3481 | @6cc 3482 | bbb 3483 | @6cd 3484 | 555 3485 | @6ce 3486 | 555 3487 | @6cf 3488 | 000 3489 | @6d0 3490 | 000 3491 | @6d1 3492 | 740 3493 | @6d2 3494 | 740 3495 | @6d3 3496 | 740 3497 | @6d4 3498 | 740 3499 | @6d5 3500 | 740 3501 | @6d6 3502 | 740 3503 | @6d7 3504 | 740 3505 | @6d8 3506 | 740 3507 | @6d9 3508 | 740 3509 | @6da 3510 | 740 3511 | @6db 3512 | 740 3513 | @6dc 3514 | 740 3515 | @6dd 3516 | 740 3517 | @6de 3518 | 000 3519 | @6df 3520 | 000 3521 | @6e0 3522 | 000 3523 | @6e1 3524 | c82 3525 | @6e2 3526 | fc1 3527 | @6e3 3528 | fc1 3529 | @6e4 3530 | fc1 3531 | @6e5 3532 | fc1 3533 | @6e6 3534 | fc1 3535 | @6e7 3536 | fc1 3537 | @6e8 3538 | fc1 3539 | @6e9 3540 | fc1 3541 | @6ea 3542 | fc1 3543 | @6eb 3544 | fc1 3545 | @6ec 3546 | fc1 3547 | @6ed 3548 | c82 3549 | @6ee 3550 | c82 3551 | @6ef 3552 | 000 3553 | @6f0 3554 | 00f 3555 | @6f1 3556 | 000 3557 | @6f2 3558 | eff 3559 | @6f3 3560 | eff 3561 | @6f4 3562 | eff 3563 | @6f5 3564 | f08 3565 | @6f6 3566 | f08 3567 | @6f7 3568 | f08 3569 | @6f8 3570 | f08 3571 | @6f9 3572 | f08 3573 | @6fa 3574 | f08 3575 | @6fb 3576 | eff 3577 | @6fc 3578 | eff 3579 | @6fd 3580 | eff 3581 | @6fe 3582 | 000 3583 | @6ff 3584 | 00f 3585 | @700 3586 | 000 3587 | @701 3588 | 555 3589 | @702 3590 | 555 3591 | @703 3592 | 555 3593 | @704 3594 | eef 3595 | @705 3596 | eef 3597 | @706 3598 | 555 3599 | @707 3600 | 555 3601 | @708 3602 | 555 3603 | @709 3604 | 555 3605 | @70a 3606 | 555 3607 | @70b 3608 | bbb 3609 | @70c 3610 | bbb 3611 | @70d 3612 | 555 3613 | @70e 3614 | 555 3615 | @70f 3616 | 000 3617 | @710 3618 | 000 3619 | @711 3620 | 740 3621 | @712 3622 | 740 3623 | @713 3624 | 740 3625 | @714 3626 | 740 3627 | @715 3628 | 740 3629 | @716 3630 | 740 3631 | @717 3632 | 740 3633 | @718 3634 | 740 3635 | @719 3636 | 740 3637 | @71a 3638 | 740 3639 | @71b 3640 | 740 3641 | @71c 3642 | 740 3643 | @71d 3644 | 740 3645 | @71e 3646 | 000 3647 | @71f 3648 | 000 3649 | @720 3650 | 000 3651 | @721 3652 | c82 3653 | @722 3654 | c82 3655 | @723 3656 | fc1 3657 | @724 3658 | fc1 3659 | @725 3660 | fc1 3661 | @726 3662 | fc1 3663 | @727 3664 | fc1 3665 | @728 3666 | fc1 3667 | @729 3668 | fc1 3669 | @72a 3670 | fc1 3671 | @72b 3672 | fc1 3673 | @72c 3674 | c82 3675 | @72d 3676 | c82 3677 | @72e 3678 | c82 3679 | @72f 3680 | 000 3681 | @730 3682 | 00f 3683 | @731 3684 | 000 3685 | @732 3686 | eff 3687 | @733 3688 | eff 3689 | @734 3690 | eff 3691 | @735 3692 | eff 3693 | @736 3694 | eff 3695 | @737 3696 | eff 3697 | @738 3698 | eff 3699 | @739 3700 | eff 3701 | @73a 3702 | eff 3703 | @73b 3704 | eff 3705 | @73c 3706 | eff 3707 | @73d 3708 | eff 3709 | @73e 3710 | 000 3711 | @73f 3712 | 00f 3713 | @740 3714 | 000 3715 | @741 3716 | 555 3717 | @742 3718 | 555 3719 | @743 3720 | 555 3721 | @744 3722 | 555 3723 | @745 3724 | 555 3725 | @746 3726 | 555 3727 | @747 3728 | 555 3729 | @748 3730 | 555 3731 | @749 3732 | 555 3733 | @74a 3734 | 555 3735 | @74b 3736 | 555 3737 | @74c 3738 | 555 3739 | @74d 3740 | 555 3741 | @74e 3742 | 000 3743 | @74f 3744 | 000 3745 | @750 3746 | 000 3747 | @751 3748 | 000 3749 | @752 3750 | 740 3751 | @753 3752 | 740 3753 | @754 3754 | 740 3755 | @755 3756 | 740 3757 | @756 3758 | 740 3759 | @757 3760 | 740 3761 | @758 3762 | 740 3763 | @759 3764 | 740 3765 | @75a 3766 | 740 3767 | @75b 3768 | 740 3769 | @75c 3770 | 740 3771 | @75d 3772 | 000 3773 | @75e 3774 | 000 3775 | @75f 3776 | 000 3777 | @760 3778 | 000 3779 | @761 3780 | c82 3781 | @762 3782 | c82 3783 | @763 3784 | c82 3785 | @764 3786 | c82 3787 | @765 3788 | c82 3789 | @766 3790 | c82 3791 | @767 3792 | c82 3793 | @768 3794 | c82 3795 | @769 3796 | c82 3797 | @76a 3798 | c82 3799 | @76b 3800 | c82 3801 | @76c 3802 | c82 3803 | @76d 3804 | c82 3805 | @76e 3806 | c82 3807 | @76f 3808 | 000 3809 | @770 3810 | 00f 3811 | @771 3812 | 000 3813 | @772 3814 | eff 3815 | @773 3816 | eff 3817 | @774 3818 | eff 3819 | @775 3820 | eff 3821 | @776 3822 | eff 3823 | @777 3824 | eff 3825 | @778 3826 | eff 3827 | @779 3828 | eff 3829 | @77a 3830 | eff 3831 | @77b 3832 | eff 3833 | @77c 3834 | eff 3835 | @77d 3836 | eff 3837 | @77e 3838 | 000 3839 | @77f 3840 | 00f 3841 | @780 3842 | 000 3843 | @781 3844 | 000 3845 | @782 3846 | 555 3847 | @783 3848 | 555 3849 | @784 3850 | 555 3851 | @785 3852 | 555 3853 | @786 3854 | 555 3855 | @787 3856 | 555 3857 | @788 3858 | 555 3859 | @789 3860 | 555 3861 | @78a 3862 | 555 3863 | @78b 3864 | 555 3865 | @78c 3866 | 555 3867 | @78d 3868 | 000 3869 | @78e 3870 | 000 3871 | @78f 3872 | 000 3873 | @790 3874 | 00f 3875 | @791 3876 | 000 3877 | @792 3878 | 000 3879 | @793 3880 | 000 3881 | @794 3882 | 000 3883 | @795 3884 | 000 3885 | @796 3886 | 000 3887 | @797 3888 | 000 3889 | @798 3890 | 000 3891 | @799 3892 | 000 3893 | @79a 3894 | 000 3895 | @79b 3896 | 000 3897 | @79c 3898 | 000 3899 | @79d 3900 | 000 3901 | @79e 3902 | 000 3903 | @79f 3904 | 00f 3905 | @7a0 3906 | 00f 3907 | @7a1 3908 | 000 3909 | @7a2 3910 | c82 3911 | @7a3 3912 | c82 3913 | @7a4 3914 | c82 3915 | @7a5 3916 | c82 3917 | @7a6 3918 | c82 3919 | @7a7 3920 | c82 3921 | @7a8 3922 | c82 3923 | @7a9 3924 | c82 3925 | @7aa 3926 | c82 3927 | @7ab 3928 | c82 3929 | @7ac 3930 | c82 3931 | @7ad 3932 | c82 3933 | @7ae 3934 | 000 3935 | @7af 3936 | 00f 3937 | @7b0 3938 | 00f 3939 | @7b1 3940 | 00f 3941 | @7b2 3942 | 000 3943 | @7b3 3944 | eff 3945 | @7b4 3946 | eff 3947 | @7b5 3948 | eff 3949 | @7b6 3950 | eff 3951 | @7b7 3952 | 000 3953 | @7b8 3954 | 000 3955 | @7b9 3956 | eff 3957 | @7ba 3958 | eff 3959 | @7bb 3960 | eff 3961 | @7bc 3962 | eff 3963 | @7bd 3964 | 000 3965 | @7be 3966 | 00f 3967 | @7bf 3968 | 00f 3969 | @7c0 3970 | 00f 3971 | @7c1 3972 | 000 3973 | @7c2 3974 | 000 3975 | @7c3 3976 | 000 3977 | @7c4 3978 | 000 3979 | @7c5 3980 | 000 3981 | @7c6 3982 | 000 3983 | @7c7 3984 | 000 3985 | @7c8 3986 | 000 3987 | @7c9 3988 | 000 3989 | @7ca 3990 | 000 3991 | @7cb 3992 | 000 3993 | @7cc 3994 | 000 3995 | @7cd 3996 | 000 3997 | @7ce 3998 | 000 3999 | @7cf 4000 | 00f 4001 | @7d0 4002 | 00f 4003 | @7d1 4004 | 00f 4005 | @7d2 4006 | 000 4007 | @7d3 4008 | 000 4009 | @7d4 4010 | 000 4011 | @7d5 4012 | 000 4013 | @7d6 4014 | 000 4015 | @7d7 4016 | 000 4017 | @7d8 4018 | 000 4019 | @7d9 4020 | 000 4021 | @7da 4022 | 000 4023 | @7db 4024 | 000 4025 | @7dc 4026 | 000 4027 | @7dd 4028 | 000 4029 | @7de 4030 | 00f 4031 | @7df 4032 | 00f 4033 | @7e0 4034 | 00f 4035 | @7e1 4036 | 00f 4037 | @7e2 4038 | 000 4039 | @7e3 4040 | 000 4041 | @7e4 4042 | 000 4043 | @7e5 4044 | 000 4045 | @7e6 4046 | 000 4047 | @7e7 4048 | 000 4049 | @7e8 4050 | 000 4051 | @7e9 4052 | 000 4053 | @7ea 4054 | 000 4055 | @7eb 4056 | 000 4057 | @7ec 4058 | 000 4059 | @7ed 4060 | 000 4061 | @7ee 4062 | 00f 4063 | @7ef 4064 | 00f 4065 | @7f0 4066 | 00f 4067 | @7f1 4068 | 00f 4069 | @7f2 4070 | 00f 4071 | @7f3 4072 | 000 4073 | @7f4 4074 | 000 4075 | @7f5 4076 | 000 4077 | @7f6 4078 | 000 4079 | @7f7 4080 | 00f 4081 | @7f8 4082 | 00f 4083 | @7f9 4084 | 000 4085 | @7fa 4086 | 000 4087 | @7fb 4088 | 000 4089 | @7fc 4090 | 000 4091 | @7fd 4092 | 00f 4093 | @7fe 4094 | 00f 4095 | @7ff 4096 | 00f 4097 | --------------------------------------------------------------------------------