├── .gitattributes ├── keywords.txt ├── README.md ├── examples ├── i2s_tx_wm8731 │ └── i2s_tx_wm8731.ino ├── i2s_tx_dma_wm8731 │ └── i2s_tx_dma_wm8731.ino ├── i2s_thru_wm8731 │ └── i2s_thru_wm8731.ino └── i2s_thru_dma_wm8731 │ └── i2s_thru_dma_wm8731.ino ├── i2s.h ├── i2s.cpp └── mk20dx128.h /.gitattributes: -------------------------------------------------------------------------------- 1 | *.ino binary 2 | *.asc binary 3 | -------------------------------------------------------------------------------- /keywords.txt: -------------------------------------------------------------------------------- 1 | ####################################### 2 | # Syntax Coloring Map For I2S 3 | ####################################### 4 | 5 | ####################################### 6 | # Datatypes (KEYWORD1) 7 | ####################################### 8 | 9 | ####################################### 10 | # Methods and Functions (KEYWORD2) 11 | ####################################### 12 | 13 | begin KEYWORD2 14 | start KEYWORD2 15 | stop KEYWORD2 16 | 17 | ####################################### 18 | # Instances (KEYWORD2) 19 | ####################################### 20 | 21 | ####################################### 22 | # Constants (LITERAL1) 23 | ####################################### 24 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # I2S for Teensy3 2 | 3 | The I2S protocol is designed for high-quality digital audio between devices. 4 | 5 | [Teensy3](http://www.pjrc.com/teensy/), programmed with Arduino, uses a Kinetis K20 processor (ARM Cortex M4) with hardware support for one I2S channel. 6 | This library can drive the I2S either directly or using DMA. DMA is much preferred, because the CPU isn't kept busy dealing with the I/O. 7 | It can transmit and receive simultaneously. It should be able to drive a multi-channel codec using "DSP"-mode (not yet implemented). 8 | 9 | The example sketches use the WM8731 stereo codec with [this library](https://github.com/hughpyle/machinesalem-arduino-libs/tree/master/WM8731). 10 | Examples show configuration for two different boards using this codec: the [MikroE proto board](http://www.mikroe.com/add-on-boards/audio-voice/audio-codec-proto/) (48kHz, master) and for the [Open Music Labs codec shield](http://www.openmusiclabs.com/projects/codec-shield/) (44.1kHz, slave). 11 | 12 | Current status: 13 | 14 | * Stereo Transmit and Receive implemented with and without DMA. 15 | * Current examples are tested with 16-bit audio and the Open Codec Labs shield. 16 | * Receive is synchronized to Transmit, so may not actually work if Transmit is not running. Change I2S_RCR2_SYNC(1) to I2S_RCR2_SYNC(0) to work around this. Later I'll make it switchable. 17 | * Patches and suggestions please! 18 | 19 | For more status, see the [forum](http://forum.pjrc.com/threads/15748-Teensy3-I2S-with-DMA). 20 | -------------------------------------------------------------------------------- /examples/i2s_tx_wm8731/i2s_tx_wm8731.ino: -------------------------------------------------------------------------------- 1 | /* 2 | I2S & DMA digital audio demonstrator for Teensy 3.0 3 | Interfaces using Wolfson WM8731 codec. 4 | 5 | To use the Mikro proto board (as master): set clock type to I2S_CLOCK_EXTERNAL 6 | Note: this board doesn't have line-in connections. 7 | SCK -> Teensy 9 (I2S0_TX_BCLK) 8 | MISO -> not connected for this transmit-only example 9 | MOSI -> Teensy 3 (I2S0_TXD0). Can also be switched to pin 22. 10 | ADCL -> not connected for this transmit-only example 11 | DACL -> Teensy 4 (I2S0_TX_FS). Can also be switched to pin 23 or 25 12 | SDA -> Teensy 18 (I2C0_SDA) 13 | SCL -> Teensy 19 (I2C0_SCL) 14 | 3.3V -> Teensy 3.3v 15 | GND -> Teensy GND 16 | 17 | To use the openmusiclabs audio codec shield (as slave): set clock type to I2S_CLOCK_44K_INTERNAL 18 | Note: this board cannot be used as master, only as slave. 19 | J1#2 GND 20 | J1#4 3.3v (or 5V, but then you must NOT connect the analog pots A0/A1 to teensy pins directly) 21 | J1#5 3.3v 22 | J2#1 SCL(A5) -> Teensy 19 (I2C0_SCL) 23 | J2#2 SDA(A4) -> Teensy 18 (I2C0_SDA) 24 | J3#3 SCK(D13) -> Teensy 9 (I2S0_TX_BCLK) 25 | J3#4 MISO(D12) not connected for this transmit-only example 26 | J3#5 MOSI(D11) -> Teensy 3 (I2S0_TXD0) 27 | J3#6 SS(D10) -> Teensy 4 (I2S0_TX_FS) 28 | J4#3 CLKOUT(D5) -> Teensy 11 (I2S0_MCLK) 29 | */ 30 | 31 | #if 0 32 | 33 | // Settings for MikroE prototype board 34 | #define clock_per_sec 48000 35 | #define CLOCK_TYPE (I2S_CLOCK_EXTERNAL) 36 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) | WM8731_INTERFACE_MASTER) 37 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz48000)) 38 | 39 | #else 40 | 41 | // Settings for OML audio codec shield 42 | #define clock_per_sec 44100 43 | #define CLOCK_TYPE (I2S_CLOCK_44K_INTERNAL) 44 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) ) 45 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz44100)) 46 | 47 | #endif 48 | 49 | 50 | /* Wolfson audio codec controlled by I2C */ 51 | /* Library here: https://github.com/hughpyle/machinesalem-arduino-libs/tree/master/WM8731 */ 52 | #include 53 | #include 54 | 55 | 56 | /* I2S digital audio */ 57 | #include 58 | 59 | 60 | // audio data 61 | int16_t audf, audx, audy, audd; 62 | int32_t nnn=0; 63 | 64 | void initsinevalue() 65 | { 66 | audf = 45 + (rand() % 48); // midi note number 67 | float f = (440.0 / 32) * pow(2, ((float)audf - 9) / 12); // Hz. For realz, use a lookup table. 68 | audd = 2.0 * sin(PI*f/clock_per_sec) * 32767; // delta (q15_t) 69 | audx = 0; 70 | audy = 0.9 * 32767; // start somewhere near full-scale 71 | } 72 | 73 | void nextsinevalue() 74 | { 75 | nnn++; 76 | if(nnn>(clock_per_sec)) {nnn=0;initsinevalue();}; // reset every second 77 | // if(nnn>24000){nnn=0;audx=audx<<1;if(audx==0)audx=1;b=audx;};return; // marching blip 78 | // audx+=4;if(nnn>512){nnn=0;audx=-2048;};b=audx;return; // stair 79 | // b = 0xACCF0010; audx=0xACCF; return; // const pattern 80 | audx+=((audd*audy)>>15)&0xFFFFu; audy-=((audd*audx)>>15)&0xFFFFu; // sinewaves http://cabezal.com/misc/minsky-circles.html 81 | } 82 | 83 | 84 | /* --------------------- Direct I2S data transfer, we get callback to put 2 words into the FIFO ----- */ 85 | 86 | void i2s_tx_callback( int16_t *pBuf ) 87 | { 88 | pBuf[0] = audx; 89 | pBuf[1] = audy; 90 | nextsinevalue(); 91 | } 92 | 93 | 94 | /* ----------------------- begin -------------------- */ 95 | 96 | void setup() 97 | { 98 | initsinevalue(); 99 | Serial.println( "Initializing" ); 100 | 101 | delay(2000); 102 | Serial.println( "Initializing." ); 103 | 104 | delay(1000); 105 | WM8731.begin( low, CODEC_BITRATE, CODEC_INTERFACE_FLAGS ); 106 | WM8731.setActive(); 107 | WM8731.setOutputVolume( 127 ); 108 | Serial.println( "Initialized I2C" ); 109 | 110 | delay(1000); 111 | I2STx0.stop(); 112 | I2STx0.begin( CLOCK_TYPE, i2s_tx_callback ); 113 | Serial.println( "Initialized I2S without DMA" ); 114 | 115 | I2STx0.start(); 116 | } 117 | 118 | 119 | /* --------------------- main loop ------------------ */ 120 | void loop() 121 | { 122 | } 123 | 124 | -------------------------------------------------------------------------------- /examples/i2s_tx_dma_wm8731/i2s_tx_dma_wm8731.ino: -------------------------------------------------------------------------------- 1 | /* 2 | I2S & DMA digital audio demonstrator for Teensy 3.0 3 | Interfaces using Wolfson WM8731 codec. 4 | 5 | To use the Mikro proto board (as master): set clock type to I2S_CLOCK_EXTERNAL 6 | Note: this board doesn't have line-in connections. 7 | SCK -> Teensy 9 (I2S0_TX_BCLK) 8 | MISO -> not connected for this transmit-only example 9 | MOSI -> Teensy 3 (I2S0_TXD0). Can also be switched to pin 22. 10 | ADCL -> not connected for this transmit-only example 11 | DACL -> Teensy 4 (I2S0_TX_FS). Can also be switched to pin 23 or 25 12 | SDA -> Teensy 18 (I2C0_SDA) 13 | SCL -> Teensy 19 (I2C0_SCL) 14 | 3.3V -> Teensy 3.3v 15 | GND -> Teensy GND 16 | 17 | To use the openmusiclabs audio codec shield (as slave): set clock type to I2S_CLOCK_44K_INTERNAL 18 | Note: this board cannot be used as master, only as slave. 19 | J1#2 GND 20 | J1#4 3.3v (or 5V, but then you must NOT connect the analog pots A0/A1 to teensy pins directly) 21 | J1#5 3.3v 22 | J2#1 SCL(A5) -> Teensy 19 (I2C0_SCL) 23 | J2#2 SDA(A4) -> Teensy 18 (I2C0_SDA) 24 | J3#3 SCK(D13) -> Teensy 9 (I2S0_TX_BCLK) 25 | J3#4 MISO(D12) not connected for this transmit-only example 26 | J3#5 MOSI(D11) -> Teensy 3 (I2S0_TXD0) 27 | J3#6 SS(D10) -> Teensy 4 (I2S0_TX_FS) 28 | J4#3 CLKOUT(D5) -> Teensy 11 (I2S0_MCLK) 29 | */ 30 | 31 | #if 0 32 | 33 | // Settings for MikroE prototype board 34 | #define clock_per_sec 48000 35 | #define CLOCK_TYPE (I2S_CLOCK_EXTERNAL) 36 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) | WM8731_INTERFACE_MASTER) 37 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz48000)) 38 | 39 | #else 40 | 41 | // Settings for OML audio codec shield 42 | #define clock_per_sec 44100 43 | #define CLOCK_TYPE (I2S_CLOCK_44K_INTERNAL) 44 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) ) 45 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz44100)) 46 | 47 | #endif 48 | 49 | 50 | /* Wolfson audio codec controlled by I2C */ 51 | /* Library here: https://github.com/hughpyle/machinesalem-arduino-libs/tree/master/WM8731 */ 52 | #include 53 | #include 54 | 55 | 56 | /* I2S digital audio */ 57 | #include 58 | 59 | 60 | // audio data 61 | int16_t audf, audx, audy, audd; 62 | int32_t nnn=0; 63 | 64 | void initsinevalue() 65 | { 66 | audf = 45 + (rand() % 48); // midi note number 67 | float f = (440.0 / 32) * pow(2, ((float)audf - 9) / 12); // Hz. For realz, use a lookup table. 68 | audd = 2.0 * sin(PI*f/clock_per_sec) * 32767; // delta (q15_t) 69 | audx = 0; 70 | audy = 0.9 * 32767; // start somewhere near full-scale 71 | } 72 | 73 | void nextsinevalue() 74 | { 75 | nnn++; 76 | if(nnn>(clock_per_sec)) {nnn=0;initsinevalue();}; // reset every second 77 | // if(nnn>24000){nnn=0;audx=audx<<1;if(audx==0)audx=1;b=audx;};return; // marching blip 78 | // audx+=4;if(nnn>512){nnn=0;audx=-2048;};b=audx;return; // stair 79 | // b = 0xACCF0010; audx=0xACCF; return; // const pattern 80 | audx+=((audd*audy)>>15)&0xFFFFu; audy-=((audd*audx)>>15)&0xFFFFu; // sinewaves http://cabezal.com/misc/minsky-circles.html 81 | } 82 | 83 | 84 | /* ----------------------- DMA transfer, we get callback to fill one of the ping-pong buffers ------ */ 85 | void dma_tx_callback( int16_t *pBuf, uint16_t len ) 86 | { 87 | while( len>0 ) 88 | { 89 | *pBuf++ = audx; 90 | *pBuf++ = audy; 91 | nextsinevalue(); 92 | len--; 93 | len--; 94 | } 95 | // Serial.println(audf,DEC); 96 | } 97 | 98 | 99 | /* ----------------------- begin -------------------- */ 100 | 101 | void setup() 102 | { 103 | initsinevalue(); 104 | Serial.println( "Initializing" ); 105 | 106 | delay(2000); 107 | Serial.println( "Initializing." ); 108 | 109 | delay(1000); 110 | WM8731.begin( low, CODEC_BITRATE, CODEC_INTERFACE_FLAGS ); 111 | WM8731.setActive(); 112 | WM8731.setOutputVolume( 127 ); 113 | Serial.println( "Initialized I2C" ); 114 | 115 | delay(1000); 116 | I2STx0.stop(); 117 | I2STx0.begin( CLOCK_TYPE, dma_tx_callback ); 118 | Serial.println( "Initialized I2S with DMA" ); 119 | 120 | I2STx0.start(); 121 | } 122 | 123 | 124 | /* --------------------- main loop ------------------ */ 125 | void loop() 126 | { 127 | } 128 | 129 | -------------------------------------------------------------------------------- /examples/i2s_thru_wm8731/i2s_thru_wm8731.ino: -------------------------------------------------------------------------------- 1 | /* TODO synchronous receive only if we choose it explicitly */ 2 | 3 | /* 4 | I2S digital audio demonstrator for Teensy 3.0 5 | Interfaces using Wolfson WM8731 codec. 6 | 7 | This example is a "play through delay" test, using I2S (not DMA). 8 | Reads input into a circular buffer, writes output from the same buffer, 9 | If the buffer size is 2, this is "straight through". 10 | */ 11 | 12 | /* 13 | To use the Mikro proto board (as master): set clock type to I2S_CLOCK_EXTERNAL 14 | Note: this board doesn't have line-in connections. 15 | SCK -> Teensy 9 (I2S0_TX_BCLK) 16 | MISO -> not connected for this transmit-only example 17 | MOSI -> Teensy 3 (I2S0_TXD0). Can also be switched to pin 22. 18 | ADCL -> not connected for this transmit-only example 19 | DACL -> Teensy 4 (I2S0_TX_FS). Can also be switched to pin 23 or 25 20 | SDA -> Teensy 18 (I2C0_SDA) 21 | SCL -> Teensy 19 (I2C0_SCL) 22 | 3.3V -> Teensy 3.3v 23 | GND -> Teensy GND 24 | */ 25 | 26 | /* 27 | To use the openmusiclabs audio codec shield (as slave): set clock type to I2S_CLOCK_44K_INTERNAL. 28 | Note: this board cannot be used as master, only as slave. 29 | J1#2 GND 30 | J1#4 3.3v (or 5V, but then you must NOT connect the analog pots A0/A1 to teensy pins directly) 31 | J1#5 3.3v 32 | J2#1 SCL(A5) -> Teensy 19 (I2C0_SCL) 33 | J2#2 SDA(A4) -> Teensy 18 (I2C0_SDA) 34 | J3#3 SCK(D13) -> Teensy 9 (I2S0_TX_BCLK) 35 | J3#4 MISO(D12) -> Teensy 13 (I2S0_RXD0) 36 | J3#5 MOSI(D11) -> Teensy 3 (I2S0_TXD0) 37 | J3#6 SS(D10) -> Teensy 4 (I2S0_TX_FS) 38 | J4#3 CLKOUT(D5) -> Teensy 11 (I2S0_MCLK) 39 | 40 | Receive pins 11, 12, 13 (no MCLK) 41 | Rx pin 12 // I2S0_RX_FS 42 | Rx pin 11 // I2S0_RX_BCLK 43 | 44 | */ 45 | 46 | #if 0 47 | 48 | // Settings for MikroE prototype board 49 | #define CLOCK_TYPE (I2S_CLOCK_EXTERNAL) 50 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) | WM8731_INTERFACE_MASTER) 51 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz48000)) 52 | #define CODEC_ANALOG_FLAGS (WM8731_ANALOG_DACSEL | WM8731_ANALOG_MICBOOST | WM8731_ANALOG_INSEL) 53 | 54 | #else 55 | 56 | // Settings for OML audio codec shield 57 | #define CLOCK_TYPE (I2S_CLOCK_44K_INTERNAL) 58 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) ) 59 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz44100)) 60 | #define CODEC_ANALOG_FLAGS (WM8731_ANALOG_DACSEL) 61 | 62 | #endif 63 | 64 | 65 | /* Wolfson audio codec controlled by I2C */ 66 | /* Library here: https://github.com/hughpyle/machinesalem-arduino-libs/tree/master/WM8731 */ 67 | #include 68 | #include 69 | 70 | 71 | /* I2S digital audio */ 72 | #include 73 | 74 | 75 | /* Circular buffer for audio samples, interleaved left & right channel */ 76 | const uint16_t buffersize = 2; // 2048; 77 | volatile int16_t buffer[buffersize]; 78 | uint16_t nTX = 0; 79 | uint16_t nRX = 0; 80 | 81 | 82 | /* --------------------- Direct I2S Receive, we get callback to read 2 words from the FIFO ----- */ 83 | 84 | void i2s_rx_callback( int16_t *pBuf ) 85 | { 86 | // Read the data 87 | buffer[nRX++] = pBuf[0]; 88 | buffer[nRX++] = pBuf[1]; 89 | if( nRX>=buffersize ) nRX=0; 90 | } 91 | 92 | 93 | /* --------------------- Direct I2S Transmit, we get callback to put 2 words into the FIFO ----- */ 94 | 95 | void i2s_tx_callback( int16_t *pBuf ) 96 | { 97 | // Send the data 98 | pBuf[0] = buffer[nTX++]; 99 | pBuf[1] = buffer[nTX++]; 100 | if( nTX>=buffersize ) nTX=0; 101 | } 102 | 103 | 104 | /* ----------------------- begin -------------------- */ 105 | 106 | void setup() 107 | { 108 | Serial.println( "Initializing" ); 109 | 110 | delay(2000); 111 | Serial.println( "Initializing." ); 112 | 113 | delay(1000); 114 | WM8731.begin( low, CODEC_BITRATE, CODEC_INTERFACE_FLAGS ); 115 | WM8731.setActive(); 116 | WM8731.setInputVolume( 63 ); 117 | WM8731.setOutputVolume( 127 ); 118 | WM8731.set( WM8731_ANALOG, CODEC_ANALOG_FLAGS ); 119 | Serial.println( "Initialized I2C Codec" ); 120 | 121 | delay(1000); 122 | I2SRx0.begin( CLOCK_TYPE, i2s_rx_callback ); 123 | Serial.println( "Initialized I2S RX without DMA" ); 124 | 125 | I2STx0.begin( CLOCK_TYPE, i2s_tx_callback ); 126 | Serial.println( "Initialized I2S TX without DMA" ); 127 | 128 | // Before starting tx/rx, set the buffer pointers 129 | // Receiver gets data just behind the transmit pointer (i.e. buffersize-2 "ahead") 130 | nRX = 0; 131 | nTX = 2; 132 | 133 | I2STx0.start(); 134 | I2SRx0.start(); 135 | } 136 | 137 | 138 | /* --------------------- main loop ------------------ */ 139 | void loop() 140 | { 141 | /* do nothing */ 142 | } 143 | 144 | -------------------------------------------------------------------------------- /examples/i2s_thru_dma_wm8731/i2s_thru_dma_wm8731.ino: -------------------------------------------------------------------------------- 1 | /* TODO synchronous receive only if we choose it explicitly */ 2 | 3 | /* 4 | I2S digital audio demonstrator for Teensy 3.0 5 | Interfaces using Wolfson WM8731 codec. 6 | 7 | This example is a "play through delay" test, using I2S with DMA. 8 | Reads input into a circular buffer, writes output from the same buffer, 9 | If the buffer size is DMA_BUFFER_SIZE (128 by default), this is "straight through". 10 | */ 11 | 12 | /* 13 | To use the Mikro proto board (as master): set clock type to I2S_CLOCK_EXTERNAL 14 | Note: this board doesn't have line-in connections. 15 | SCK -> Teensy 9 (I2S0_TX_BCLK) 16 | MISO -> not connected for this transmit-only example 17 | MOSI -> Teensy 3 (I2S0_TXD0). Can also be switched to pin 22. 18 | ADCL -> not connected for this transmit-only example 19 | DACL -> Teensy 4 (I2S0_TX_FS). Can also be switched to pin 23 or 25 20 | SDA -> Teensy 18 (I2C0_SDA) 21 | SCL -> Teensy 19 (I2C0_SCL) 22 | 3.3V -> Teensy 3.3v 23 | GND -> Teensy GND 24 | */ 25 | 26 | /* 27 | To use the openmusiclabs audio codec shield (as slave): set clock type to I2S_CLOCK_44K_INTERNAL. 28 | Note: this board cannot be used as master, only as slave. 29 | J1#2 GND 30 | J1#4 3.3v (or 5V, but then you must NOT connect the analog pots A0/A1 to teensy pins directly) 31 | J1#5 3.3v 32 | J2#1 SCL(A5) -> Teensy 19 (I2C0_SCL) 33 | J2#2 SDA(A4) -> Teensy 18 (I2C0_SDA) 34 | J3#3 SCK(D13) -> Teensy 9 (I2S0_TX_BCLK) 35 | J3#4 MISO(D12) -> Teensy 13 (I2S0_RXD0) 36 | J3#5 MOSI(D11) -> Teensy 3 (I2S0_TXD0) 37 | J3#6 SS(D10) -> Teensy 4 (I2S0_TX_FS) 38 | J4#3 CLKOUT(D5) -> Teensy 11 (I2S0_MCLK) 39 | 40 | Receive pins 11, 12, 13 (no MCLK) 41 | Rx pin 12 // I2S0_RX_FS 42 | Rx pin 11 // I2S0_RX_BCLK 43 | 44 | */ 45 | 46 | #if 0 47 | 48 | // Settings for MikroE prototype board 49 | #define CLOCK_TYPE (I2S_CLOCK_EXTERNAL) 50 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) | WM8731_INTERFACE_MASTER) 51 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz48000)) 52 | #define CODEC_ANALOG_FLAGS (WM8731_ANALOG_DACSEL | WM8731_ANALOG_MICBOOST | WM8731_ANALOG_INSEL) 53 | 54 | #else 55 | 56 | // Settings for OML audio codec shield 57 | #define CLOCK_TYPE (I2S_CLOCK_44K_INTERNAL) 58 | #define CODEC_INTERFACE_FLAGS (WM8731_INTERFACE_FORMAT(I2S) | WM8731_INTERFACE_WORDLEN(bits16) ) 59 | #define CODEC_BITRATE (WM8731_SAMPLING_RATE(hz44100)) 60 | #define CODEC_ANALOG_FLAGS (WM8731_ANALOG_DACSEL) 61 | 62 | #endif 63 | 64 | 65 | /* Wolfson audio codec controlled by I2C */ 66 | /* Library here: https://github.com/hughpyle/machinesalem-arduino-libs/tree/master/WM8731 */ 67 | #include 68 | #include 69 | 70 | 71 | /* I2S digital audio */ 72 | #include 73 | 74 | 75 | /* Circular buffer for audio samples, interleaved left & right channel */ 76 | const uint16_t buffersize = DMA_BUFFER_SIZE; // must be a multiple of DMA_BUFFER_SIZE 77 | volatile int16_t buffer[buffersize]; 78 | uint16_t nTX = 0; 79 | uint16_t nRX = 0; 80 | 81 | 82 | /* --------------------- DMA I2S Receive, we get callback to read 2 words from the FIFO ----- */ 83 | 84 | void dma_rx_callback( int16_t *pBuf, uint16_t len ) 85 | { 86 | while( len>0 ) 87 | { 88 | buffer[nRX++] = *pBuf++; 89 | buffer[nRX++] = *pBuf++; 90 | len--; 91 | len--; 92 | } 93 | if( nRX>=buffersize ) nRX=0; 94 | } 95 | 96 | /* --------------------- DMA I2S Transmit, we get callback to put 2 words into the FIFO ----- */ 97 | 98 | void dma_tx_callback( int16_t *pBuf, uint16_t len ) 99 | { 100 | while( len>0 ) 101 | { 102 | *pBuf++ = buffer[nTX++]; 103 | *pBuf++ = buffer[nTX++]; 104 | len--; 105 | len--; 106 | } 107 | if( nTX>=buffersize ) nTX=0; 108 | } 109 | 110 | 111 | /* ----------------------- begin -------------------- */ 112 | 113 | void setup() 114 | { 115 | Serial.println( "Initializing" ); 116 | 117 | delay(2000); 118 | Serial.println( "Initializing." ); 119 | 120 | delay(1000); 121 | WM8731.begin( low, CODEC_BITRATE, CODEC_INTERFACE_FLAGS ); 122 | WM8731.setActive(); 123 | WM8731.setInputVolume( 63 ); 124 | WM8731.setOutputVolume( 127 ); 125 | WM8731.set( WM8731_ANALOG, CODEC_ANALOG_FLAGS ); 126 | Serial.println( "Initialized I2C Codec" ); 127 | 128 | delay(1000); 129 | I2SRx0.begin( CLOCK_TYPE, dma_rx_callback ); 130 | Serial.println( "Initialized I2S RX with DMA" ); 131 | 132 | I2STx0.begin( CLOCK_TYPE, dma_tx_callback ); 133 | Serial.println( "Initialized I2S TX with DMA" ); 134 | 135 | // Before starting tx/rx, set the buffer pointers 136 | nRX = 0; 137 | nTX = 0; 138 | 139 | I2STx0.start(); 140 | I2SRx0.start(); 141 | } 142 | 143 | 144 | 145 | /* --------------------- main loop ------------------ */ 146 | void loop() 147 | { 148 | /* do nothing */ 149 | } 150 | 151 | -------------------------------------------------------------------------------- /i2s.h: -------------------------------------------------------------------------------- 1 | /* 2 | * I2S interface for Teensy 3.0 3 | * Fork this on github https://github.com/hughpyle/teensy-i2s 4 | * 5 | * Copyright (c) 2013 by Hugh Pyle and contributors. 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy 8 | * of this software and associated documentation files (the "Software"), to deal 9 | * in the Software without restriction, including without limitation the rights 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | * copies of the Software, and to permit persons to whom the Software is 12 | * furnished to do so, subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in 15 | * all copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 | * THE SOFTWARE. 24 | * 25 | */ 26 | 27 | #ifndef __I2S_H__ 28 | #define __I2S_H__ 29 | 30 | #include 31 | #include 32 | 33 | // Audio configuration. Edit these here if you need to. 34 | #define I2S_FRAME_SIZE 2 // Number of frames, 2=stereo 35 | #define I2S_IO_BIT_DEPTH 16 // Number of bits per sample in the physical data (8, 16 or 32) 36 | #define I2S_BUFFER_BIT_DEPTH 16 // Number of bits per sample in the DMA buffer (8, 16 or 32) 37 | 38 | // Clock type constants 39 | #define I2S_CLOCK_EXTERNAL 0 // The bit clock is provided by an external device (e.g. the codec) 40 | #define I2S_CLOCK_8K_INTERNAL 1 // The bit clock is 8kHz, internally generated 41 | #define I2S_CLOCK_32K_INTERNAL 2 // The bit clock is 32kHz, internally generated 42 | #define I2S_CLOCK_44K_INTERNAL 3 // The bit clock is 44.1kHz, internally generated 43 | #define I2S_CLOCK_48K_INTERNAL 4 // The bit clock is 48kHz, internally generated 44 | 45 | 46 | // Pin patterns 47 | // Teensy 3.0 hardware has several ways to configure its I2S pins: 48 | // pin alt4 alt6 49 | // 3 I2S0_TXD0 (transmit data, also on 22) 50 | // 4 I2S0_TX_FS (transmit word clock, also on 23, 25) 51 | // 9 I2S0_TX_BCLK (transmit bit clock, also on 24, 32) 52 | // 11 I2S0_RX_BCLK I2S0_MCLK (receive bit clock, also on 27; or master clock, also on 28) 53 | // 12 I2S0_RX_FS (receive word clock, also on 29) 54 | // 13 I2S0_RXD0 (receive data) 55 | // 22 I2S0_TXD0 (transmit data, also on 22) 56 | // 23 I2S0_TX_FS (also on 4, 25) 57 | // 24 I2S0_TX_BCLK (also on 9, 32) 58 | // 25 I2S0_TX_FS (also on 4, 23) 59 | // 27 I2S0_RX_BCLK (also on 11) 60 | // 28 I2S0_MCLK (also on 11) 61 | // 29 I2S0_RX_FS (also on 12) 62 | // 32 I2S0_TX_BCLK (also on 9, 24) 63 | // Pins 24 onward are pads on the bottom of the board, not pins on the edges. 64 | // 65 | // Some combinations of these are defined in the macros I2S_PIN_PATTERN_. 66 | // Not all combinations of TX and RX can be used together (you need to decide which role for pin 11). 67 | #define I2S_TX_PIN_PATTERN_1 0x01 // Transmit pins 3, 4, 9 (no MCLK) 68 | #define I2S_TX_PIN_PATTERN_2 0x02 // Transmit pins 3, 4, 9, 11 (MCLK on 11) 69 | #define I2S_TX_PIN_PATTERN_3 0x03 // Transmit pins 22, 23, 9 (no MCLK) 70 | #define I2S_TX_PIN_PATTERN_4 0x04 // Transmit pins 22, 23, 9, 11 (MCLK on 11) 71 | #define I2S_TX_PIN_PATTERN_5 0x05 // Transmit pins 3, 4, 24 (no MCLK) 72 | #define I2S_TX_PIN_PATTERN_6 0x06 // Transmit pins 3, 4, 24, 28 (MCLK on 28) 73 | 74 | #define I2S_RX_PIN_PATTERN_1 0x10 // Receive pins 11, 12, 13 (no MCLK) 75 | #define I2S_RX_PIN_PATTERN_2 0x20 // Receive pins 11, 12, 13, 28 (MCLK on 28) 76 | #define I2S_RX_PIN_PATTERN_3 0x30 // Receive pins 11, 12, 13, 27 (MCLK on 11) 77 | #define I2S_RX_PIN_PATTERN_4 0x40 // Receive pins 27, 29, 13 (no MCLK) 78 | #define I2S_RX_PIN_PATTERN_5 0x50 // Receive pins 27, 29, 13, 28 (MCLK on 28) 79 | #define I2S_RX_PIN_PATTERN_6 0x60 // Receive pins 27, 29, 13, 11 (MCLK on 11) 80 | 81 | // You should define I2S_PIN_PATTERN to be the appropriate pin pattern for your hardware setup. 82 | // Otherwise the default is this 83 | #define I2S_PIN_PATTERN I2S_TX_PIN_PATTERN_1 + I2S_RX_PIN_PATTERN_1 84 | 85 | 86 | // DMA buffer size (in samples). 87 | // Using ping-pong DMA, this determines your latency. 88 | // If you need super-low latency, set this smaller (or use I2S without DMA). 89 | #define DMA_BUFFER_SIZE 128 90 | 91 | // Use round-robin DMA channel priorities? If not, they're explicitly set 92 | #define ROUNDROBIN 93 | 94 | // Data type for the API 95 | #if I2S_BUFFER_BIT_DEPTH==8 96 | #define _I2S_SAMPLE_T int8_t 97 | #elif I2S_BUFFER_BIT_DEPTH==16 98 | #define _I2S_SAMPLE_T int16_t 99 | #else 100 | #define _I2S_SAMPLE_T int32_t 101 | #endif 102 | 103 | 104 | class I2S_class 105 | { 106 | private: 107 | // Flags 108 | uint8_t clock; /* one of I2S_CLOCK_xxx */ 109 | uint8_t receive; /* 1 or 0 */ 110 | bool useDMA; 111 | volatile bool _dma_using_Buffer_A; 112 | void (*fnI2SCallback)( _I2S_SAMPLE_T *pBuf ); // the I2S callback (buffer size = I2S_FRAME_SIZE) 113 | void (*fnDMACallback)( _I2S_SAMPLE_T *pBuf, uint16_t numSamples ); // the DMA callback (buffer size = DMA_BUFFER_SIZE) 114 | 115 | void init(); 116 | void io_init(); 117 | void clock_init(); 118 | void i2s_transmit_init(); 119 | void i2s_receive_init(); 120 | void dma_buffer_init(); 121 | void dma_transmit_init(); 122 | void dma_receive_init(); 123 | void dma_start(); 124 | void dma_stop(); 125 | 126 | public: 127 | /* Don't construct your own, there are two ready-made instances, one for receive and one for transmit */ 128 | I2S_class(uint8_t isRx); 129 | 130 | /* 131 | * @brief Initialize the I2S interface for use without DMA. 132 | * 133 | * @param[in] clk The clock type and speed, one of I2S_CLOCK_xxx 134 | * @param[in] fptr The callback function that your sketch implements. 135 | * This will be called with a pointer to a buffer 136 | * where you will read or write I2S_FRAME_SIZE of _I2S_SAMPLE_T audio data. 137 | * @return none. 138 | */ 139 | void begin(uint8_t clk, void (*fptr)( _I2S_SAMPLE_T *pBuf )); 140 | 141 | /* 142 | * @brief Initialize the I2S interface for use with DMA. 143 | * 144 | * @param[in] clk The clock type and speed, one of I2S_CLOCK_xxx 145 | * @param[in] fptr The callback function that your sketch implements. 146 | * This will be called with a pointer to a buffer 147 | * where you will read or write numSamples of _I2S_SAMPLE_T audio data. 148 | * @return none. 149 | * 150 | * TODO !!!receive with DMA is not yet implemented!!! (transmit is ok) 151 | */ 152 | void begin(uint8_t clk, void (*fptr)( _I2S_SAMPLE_T *pBuf, uint16_t numSamples )); 153 | 154 | /* 155 | * @brief Start the I2S interface. (You must have initialized first). 156 | * @return none. 157 | */ 158 | void start(); 159 | 160 | /* 161 | * @brief Stop the I2S interface. (You must have initialized first). 162 | * @return none. 163 | */ 164 | void stop(); 165 | 166 | /* internal */ 167 | inline void i2s_tx_callback(void); 168 | inline void i2s_rx_callback(void); 169 | inline void dma_tx_callback(void); 170 | inline void dma_rx_callback(void); 171 | }; 172 | 173 | 174 | extern I2S_class I2STx0; 175 | extern I2S_class I2SRx0; 176 | 177 | #endif 178 | -------------------------------------------------------------------------------- /i2s.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * I2S interface for Teensy 3.0 3 | * Fork this on github https://github.com/hughpyle/teensy-i2s 4 | * 5 | * Copyright (c) 2013 by Hugh Pyle and contributors. 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy 8 | * of this software and associated documentation files (the "Software"), to deal 9 | * in the Software without restriction, including without limitation the rights 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | * copies of the Software, and to permit persons to whom the Software is 12 | * furnished to do so, subject to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be included in 15 | * all copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 | * THE SOFTWARE. 24 | * 25 | */ 26 | 27 | #include 28 | #include 29 | #include "core_pins.h" 30 | 31 | // There's one instance of the class for Tx, another for Rx 32 | I2S_class I2STx0(0); 33 | I2S_class I2SRx0(1); 34 | 35 | // Buffers for 16 bit audio samples. 36 | // Static (not class members) because we want to put them in the DMAMEM area. 37 | // DMA: 38 | static _I2S_SAMPLE_T DMAMEM _dma_Rx_Buffer_A[DMA_BUFFER_SIZE]; 39 | static _I2S_SAMPLE_T DMAMEM _dma_Rx_Buffer_B[DMA_BUFFER_SIZE]; 40 | static _I2S_SAMPLE_T DMAMEM _dma_Tx_Buffer_A[DMA_BUFFER_SIZE]; 41 | static _I2S_SAMPLE_T DMAMEM _dma_Tx_Buffer_B[DMA_BUFFER_SIZE]; 42 | // I2S: 43 | static _I2S_SAMPLE_T _i2s_Rx_Buffer[I2S_FRAME_SIZE]; 44 | static _I2S_SAMPLE_T _i2s_Tx_Buffer[I2S_FRAME_SIZE]; 45 | 46 | 47 | 48 | I2S_class::I2S_class(uint8_t isRx) 49 | { 50 | receive = isRx; 51 | } 52 | 53 | /* Initialize the I2S interface for use without DMA. */ 54 | void I2S_class::begin(uint8_t clk, void (*fptr)( _I2S_SAMPLE_T *pBuf)) 55 | { 56 | clock = clk; 57 | useDMA = false; 58 | fnI2SCallback = fptr; 59 | init(); 60 | } 61 | 62 | /* Initialize the I2S interface for use with DMA. */ 63 | void I2S_class::begin(uint8_t clk, void (*fptr)( _I2S_SAMPLE_T *pBuf, uint16_t numSamples )) 64 | { 65 | clock = clk; 66 | useDMA = true; 67 | fnDMACallback = fptr; 68 | init(); 69 | } 70 | 71 | 72 | void I2S_class::start() 73 | { 74 | if( useDMA ) 75 | { 76 | // When FIFO needs data it generates a DMA request. 77 | if( receive ) 78 | { 79 | // Receive enable 80 | I2S0_RCSR |= I2S_RCSR_RE // Receive Enable 81 | | I2S_RCSR_BCE // Bit Clock Enable 82 | | I2S_RCSR_FRDE // FIFO Request DMA Enable 83 | | I2S_RCSR_FR // FIFO Reset 84 | ; 85 | } 86 | else 87 | { 88 | // Transmit enable 89 | I2S0_TCSR |= I2S_TCSR_TE // Transmit Enable 90 | | I2S_TCSR_BCE // Bit Clock Enable 91 | | I2S_TCSR_FRDE // FIFO Request DMA Enable 92 | | I2S_TCSR_FR // FIFO Reset 93 | ; 94 | } 95 | } 96 | else 97 | { 98 | // When FIFO needs data it generates an interrupt. 99 | if( receive ) 100 | { 101 | // Receive enable 102 | NVIC_ENABLE_IRQ(IRQ_I2S0_RX); 103 | I2S0_RCSR |= I2S_RCSR_RE // Receive Enable 104 | | I2S_RCSR_BCE // Bit Clock Enable 105 | | I2S_RCSR_FRIE // FIFO Request Interrupt Enable 106 | | I2S_RCSR_FR // FIFO Reset 107 | ; 108 | } 109 | else 110 | { 111 | // Transmit enable 112 | NVIC_ENABLE_IRQ(IRQ_I2S0_TX); 113 | I2S0_TCSR |= I2S_TCSR_TE // Transmit Enable 114 | | I2S_TCSR_BCE // Bit Clock Enable 115 | | I2S_TCSR_FRIE // FIFO Request Interrupt Enable 116 | | I2S_TCSR_FR // FIFO Reset 117 | ; 118 | } 119 | } 120 | } 121 | 122 | void I2S_class::stop() 123 | { 124 | if( useDMA ) 125 | { 126 | if( receive ) 127 | { 128 | NVIC_DISABLE_IRQ(IRQ_DMA_CH1); 129 | } 130 | else 131 | { 132 | NVIC_DISABLE_IRQ(IRQ_DMA_CH0); 133 | } 134 | } 135 | else 136 | { 137 | if( receive ) 138 | { 139 | NVIC_DISABLE_IRQ(IRQ_I2S0_RX); 140 | } 141 | else 142 | { 143 | NVIC_DISABLE_IRQ(IRQ_I2S0_TX); 144 | } 145 | } 146 | } 147 | 148 | 149 | 150 | void I2S_class::io_init(void) 151 | { 152 | // Pins for transmit 153 | switch( ( I2S_PIN_PATTERN) & 0x0F ) 154 | { 155 | case I2S_TX_PIN_PATTERN_1: 156 | CORE_PIN3_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TXD0 157 | CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_FS 158 | CORE_PIN9_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_BCLK 159 | break; 160 | case I2S_TX_PIN_PATTERN_2: 161 | CORE_PIN3_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TXD0 162 | CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_FS 163 | CORE_PIN9_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_BCLK 164 | CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_MCLK 165 | break; 166 | case I2S_TX_PIN_PATTERN_3: 167 | CORE_PIN22_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TXD0 168 | CORE_PIN23_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_FS 169 | CORE_PIN9_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_BCLK 170 | break; 171 | case I2S_TX_PIN_PATTERN_4: 172 | CORE_PIN22_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TXD0 173 | CORE_PIN23_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_FS 174 | CORE_PIN9_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_BCLK 175 | CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_MCLK 176 | break; 177 | case I2S_TX_PIN_PATTERN_5: 178 | CORE_PIN3_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TXD0 179 | CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_FS 180 | CORE_PIN24_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_BCLK 181 | break; 182 | case I2S_TX_PIN_PATTERN_6: 183 | CORE_PIN3_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TXD0 184 | CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_FS 185 | CORE_PIN24_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_TX_BCLK 186 | CORE_PIN28_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_MCLK 187 | break; 188 | default: 189 | break; 190 | } 191 | 192 | // Pins for receive 193 | switch( (I2S_PIN_PATTERN) & 0xF0 ) 194 | { 195 | case I2S_RX_PIN_PATTERN_1: 196 | CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_BCLK 197 | CORE_PIN12_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_FS 198 | CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RXD0 199 | break; 200 | case I2S_RX_PIN_PATTERN_2: 201 | CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_BCLK 202 | CORE_PIN12_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_FS 203 | CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RXD0 204 | CORE_PIN28_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_MCLK 205 | break; 206 | case I2S_RX_PIN_PATTERN_3: 207 | CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_MCLK 208 | CORE_PIN12_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_FS 209 | CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RXD0 210 | CORE_PIN27_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_BCLK 211 | break; 212 | case I2S_RX_PIN_PATTERN_4: 213 | CORE_PIN27_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_BCLK 214 | CORE_PIN29_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_FS 215 | CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RXD0 216 | break; 217 | case I2S_RX_PIN_PATTERN_5: 218 | CORE_PIN27_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_BCLK 219 | CORE_PIN29_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_FS 220 | CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RXD0 221 | CORE_PIN28_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_MCLK 222 | break; 223 | case I2S_RX_PIN_PATTERN_6: 224 | CORE_PIN27_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_BCLK 225 | CORE_PIN29_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RX_FS 226 | CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(4); // I2S0_RXD0 227 | CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(6); // I2S0_MCLK 228 | break; 229 | default: 230 | break; 231 | } 232 | } 233 | 234 | 235 | void I2S_class::clock_init() 236 | { 237 | // Disable system clock to the I2S module 238 | //SIM_SCGC6 &= ~(SIM_SCGC6_I2S); 239 | SIM_SCGC6 |= SIM_SCGC6_I2S; 240 | 241 | if(clock==I2S_CLOCK_EXTERNAL) 242 | { 243 | // Select input clock 0 244 | // Configure to input the bit-clock from pin, bypasses the MCLK divider 245 | I2S0_MCR = I2S_MCR_MICS(0); 246 | I2S0_MDR = 0; 247 | } 248 | else 249 | { 250 | // Select input clock 0 and output enable 251 | I2S0_MCR = I2S_MCR_MICS(0) | I2S_MCR_MOE; 252 | 253 | // 8k, 12k, 16k, 32k, etc all clock the I2S module at 12.288 MHz 254 | // 11025Hz, 22050, 44100 clock the I2S module at 11.2896 MHz 255 | switch( clock ) 256 | { 257 | case I2S_CLOCK_44K_INTERNAL: 258 | // Divide to get the 11.2896 MHz from 96MHz (96* (2/17)) 259 | I2S0_MDR = I2S_MDR_FRACT(1) | I2S_MDR_DIVIDE(16); 260 | break; 261 | case I2S_CLOCK_8K_INTERNAL: 262 | case I2S_CLOCK_32K_INTERNAL: 263 | case I2S_CLOCK_48K_INTERNAL: 264 | default: 265 | // Divide to get the 12.2880 MHz from 96MHz (96* (16/125)) 266 | I2S0_MDR = I2S_MDR_FRACT(15) | I2S_MDR_DIVIDE(124); 267 | break; 268 | } 269 | } 270 | 271 | // re-enable system clock to the I2S module 272 | SIM_SCGC6 |= SIM_SCGC6_I2S; 273 | } 274 | 275 | 276 | 277 | void I2S_class::init() 278 | { 279 | io_init(); 280 | clock_init(); 281 | 282 | if( receive ) 283 | i2s_receive_init(); 284 | else 285 | i2s_transmit_init(); 286 | 287 | if( useDMA ) 288 | { 289 | dma_buffer_init(); 290 | if( receive ) 291 | dma_receive_init(); 292 | else 293 | dma_transmit_init(); 294 | } 295 | 296 | } 297 | 298 | // Configures the number of words in each frame. The value written should be one less than the number of 299 | // words in the frame (for example, write 0 for one word per frame). The maximum supported frame size is 300 | // 16 words. 301 | #define FRSZ (I2S_FRAME_SIZE-1) 302 | 303 | // Configures the length of the frame sync in number of bit clocks. The value written must be one less than 304 | // the number of bit clocks. For example, write 0 for the frame sync to assert for one bit clock only. The sync 305 | // width cannot be configured longer than the first word of the frame. 306 | #define SYWD (I2S_IO_BIT_DEPTH-1) 307 | 308 | 309 | void I2S_class::i2s_transmit_init() 310 | { 311 | // transmit disable while we configure everything 312 | I2S0_TCSR &= ~(I2S_TCSR_TE); 313 | 314 | // Transmitter remains enabled until (and TE set) the end of the current frame 315 | for( int i=0; i<1000 && (I2S0_TCSR & I2S_TCSR_TE); i++ ); 316 | if( I2S0_TCSR & I2S_TCSR_TE ) 317 | return; 318 | 319 | I2S0_TMR = 0; // No word mask 320 | // -------------------------------------------------------------------------------- 321 | I2S0_TCR1 = I2S_TCR1_TFW(FRSZ); // set FIFO watermark 322 | // -------------------------------------------------------------------------------- 323 | I2S0_TCR2 = I2S_TCR2_SYNC(0); // use asynchronous mode 324 | I2S0_TCR2 |= I2S_TCR2_BCP; // BCLK polarity: active low 325 | if( clock != I2S_CLOCK_EXTERNAL ) 326 | { 327 | I2S0_TCR2 |= I2S_TCR2_MSEL(1); // use mc1 (notbus clock as BCLK source 328 | I2S0_TCR2 |= I2S_TCR2_DIV(3); // divide internal master clock to generate bit clock 329 | I2S0_TCR2 |= I2S_TCR2_BCD; // BCLK is generated internally (master mode) 330 | } 331 | // -------------------------------------------------------------------------------- 332 | I2S0_TCR3 = I2S_TCR3_TCE; // transmit data channel is enabled 333 | // -------------------------------------------------------------------------------- 334 | I2S0_TCR4 = I2S_TCR4_FRSZ(FRSZ); // frame size in words (plus one) 335 | I2S0_TCR4 |= I2S_TCR4_SYWD(SYWD); // number of bits in frame sync (plus one) 336 | I2S0_TCR4 |= I2S_TCR4_MF; // MSB (most significant bit) first 337 | I2S0_TCR4 |= I2S_TCR4_FSE; // Frame sync one bit before the frame 338 | if( clock != I2S_CLOCK_EXTERNAL ) 339 | { 340 | I2S0_TCR4 |= I2S_TCR4_FSD; // WCLK is generated internally (master mode) 341 | } 342 | // -------------------------------------------------------------------------------- 343 | I2S0_TCR5 = I2S_TCR5_W0W(SYWD); // bits per word, first frame 344 | I2S0_TCR5 |= I2S_TCR5_WNW(SYWD); // bits per word, nth frame 345 | I2S0_TCR5 |= I2S_TCR5_FBT(0x0f); // index shifted for FIFO (TODO depend on I2S_BUFFER_BIT_DEPTH) 346 | } 347 | 348 | void I2S_class::i2s_receive_init() 349 | { 350 | // receive disable while we configure everything 351 | I2S0_RCSR &= ~(I2S_RCSR_RE); 352 | 353 | // Receiver remains enabled until (and TE set) the end of the current frame 354 | for( int i=0; i<1000 && (I2S0_RCSR & I2S_RCSR_RE); i++ ); 355 | if( I2S0_RCSR & I2S_RCSR_RE ) 356 | return; 357 | 358 | I2S0_RMR = 0; // No word mask 359 | // -------------------------------------------------------------------------------- 360 | I2S0_RCR1 = I2S_RCR1_RFW(FRSZ); // set FIFO watermark 361 | // -------------------------------------------------------------------------------- 362 | I2S0_RCR2 = I2S_RCR2_SYNC(1); // synchronous with the transmitter 363 | I2S0_RCR2 |= I2S_RCR2_BCP; // BCLK polarity: active low 364 | if( clock != I2S_CLOCK_EXTERNAL ) 365 | { 366 | I2S0_RCR2 |= I2S_RCR2_MSEL(0); // use MCLK as BCLK source 367 | I2S0_RCR2 |= I2S_RCR2_DIV(7); // (DIV + 1) * 2, 12.288 MHz / 4 = 3.072 MHz 368 | I2S0_RCR2 |= I2S_RCR2_BCD; // BCLK is generated internally in Master mode 369 | } 370 | // -------------------------------------------------------------------------------- 371 | I2S0_RCR3 = I2S_RCR3_RCE; // receive data channel is enabled 372 | // -------------------------------------------------------------------------------- 373 | I2S0_RCR4 = I2S_RCR4_FRSZ(FRSZ); // frame size in words (plus one) 374 | I2S0_RCR4 |= I2S_RCR4_SYWD(SYWD); // bit width of a word (plus one) 375 | I2S0_RCR4 |= I2S_RCR4_MF; // MSB (most significant bit) first 376 | I2S0_RCR4 |= I2S_RCR4_FSE; // Frame sync one bit before the frame 377 | if( clock != I2S_CLOCK_EXTERNAL ) 378 | { 379 | I2S0_RCR4 |= I2S_RCR4_FSD; // WCLK is generated internally (master mode) 380 | } 381 | // -------------------------------------------------------------------------------- 382 | I2S0_RCR5 = I2S_RCR5_W0W(SYWD); // bits per word, first frame 383 | I2S0_RCR5 |= I2S_RCR5_WNW(SYWD); // bits per word, nth frame 384 | I2S0_RCR5 |= I2S_RCR5_FBT(0x0f); // index shifted for FIFO (TODO depend on I2S_BUFFER_BIT_DEPTH) 385 | } 386 | 387 | 388 | /* I2S class-instance callbacks */ 389 | 390 | void I2S_class::i2s_tx_callback(void) 391 | { 392 | if(!(I2S0_TCSR & I2S_TCSR_FRF)) return; 393 | 394 | // Call your function to get the data into our buffer 395 | fnI2SCallback( _i2s_Tx_Buffer ); 396 | 397 | // Copy the data from our buffer into FIFO 398 | if( I2S_FRAME_SIZE>0 ) I2S0_TDR0 = (uint32_t)(_i2s_Tx_Buffer[0]); 399 | if( I2S_FRAME_SIZE>1 ) I2S0_TDR0 = (uint32_t)(_i2s_Tx_Buffer[1]); 400 | if( I2S_FRAME_SIZE>2 ) I2S0_TDR0 = (uint32_t)(_i2s_Tx_Buffer[2]); 401 | if( I2S_FRAME_SIZE>3 ) I2S0_TDR0 = (uint32_t)(_i2s_Tx_Buffer[3]); 402 | 403 | //for( uint8_t i=0; i0 ) _i2s_Rx_Buffer[0] = (_I2S_SAMPLE_T)I2S0_RDR0; 416 | if( I2S_FRAME_SIZE>1 ) _i2s_Rx_Buffer[1] = (_I2S_SAMPLE_T)I2S0_RDR0; 417 | if( I2S_FRAME_SIZE>2 ) _i2s_Rx_Buffer[2] = (_I2S_SAMPLE_T)I2S0_RDR0; 418 | if( I2S_FRAME_SIZE>3 ) _i2s_Rx_Buffer[3] = (_I2S_SAMPLE_T)I2S0_RDR0; 419 | 420 | // Call your function to handle the data 421 | fnI2SCallback( _i2s_Rx_Buffer ); 422 | 423 | if(I2S0_RCSR & I2S_RCSR_FEF) I2S0_RCSR |= I2S_RCSR_FEF; // clear if underrun 424 | if(I2S0_RCSR & I2S_RCSR_SEF) I2S0_RCSR |= I2S_RCSR_SEF; // clear if frame sync error 425 | } 426 | 427 | 428 | /* I2S ISR (used when you're not using DMA) */ 429 | 430 | void i2s0_tx_isr(void) 431 | { 432 | I2STx0.i2s_tx_callback(); 433 | } 434 | 435 | void i2s0_rx_isr(void) 436 | { 437 | I2SRx0.i2s_rx_callback(); 438 | } 439 | 440 | 441 | 442 | /* 443 | * DMA 444 | * DMA channel 0 is used for transmit, and channel 1 for receive. 445 | */ 446 | 447 | void I2S_class::dma_buffer_init(void) 448 | { 449 | if(receive) 450 | { 451 | memset( _dma_Rx_Buffer_A, 0, DMA_BUFFER_SIZE * sizeof(_I2S_SAMPLE_T) ); 452 | memset( _dma_Rx_Buffer_B, 0, DMA_BUFFER_SIZE * sizeof(_I2S_SAMPLE_T) ); 453 | } 454 | else 455 | { 456 | memset( _dma_Tx_Buffer_A, 0, DMA_BUFFER_SIZE * sizeof(_I2S_SAMPLE_T) ); 457 | memset( _dma_Tx_Buffer_B, 0, DMA_BUFFER_SIZE * sizeof(_I2S_SAMPLE_T) ); 458 | } 459 | _dma_using_Buffer_A = 1; 460 | } 461 | 462 | 463 | 464 | void I2S_class::dma_transmit_init(void) 465 | { 466 | // Enable clock to the DMAMUX module 467 | SIM_SCGC6 |= SIM_SCGC6_DMAMUX; 468 | // And clock to the DMA module 469 | SIM_SCGC7 |= SIM_SCGC7_DMA; 470 | 471 | // configure DMA_MUX 472 | // DMAMUX0_CHCFG0 = 0; 473 | DMAMUX0_CHCFG0 = DMAMUX_SOURCE_I2S0_TX; 474 | 475 | // Enable IRQ on the DMA channel 0 476 | NVIC_ENABLE_IRQ(IRQ_DMA_CH0); 477 | 478 | // Set inactive 479 | DMA_TCD0_CSR &= ~(DMA_CSR_ACTIVE); 480 | 481 | #ifndef ROUNDROBIN 482 | // Set channel priorities (each must be unique) 483 | DMA_DCHPRI3 = 0; 484 | DMA_DCHPRI2 = 1; 485 | DMA_DCHPRI1 = 2; 486 | DMA_DCHPRI0 = 3; // cannot be pre-empted, can pre-empt, highest priority 487 | #endif 488 | 489 | // Control register 490 | DMA_CR = 0 // Normal 491 | | DMA_CR_EMLM // Enable minor looping 492 | #ifdef ROUNDROBIN 493 | | DMA_CR_ERCA // Enable round-robin channel arbitration 494 | #endif 495 | ; 496 | 497 | // fill the TCD regs 498 | DMA_TCD0_SADDR = (const volatile void *) _dma_Tx_Buffer_A ; // alternated with _dma_Buffer_B by our interrupt handler 499 | DMA_TCD0_SOFF = 2; // 2 byte source offset after each transfer 500 | DMA_TCD0_ATTR = DMA_ATTR_SMOD(0) // No source modulo 501 | | DMA_ATTR_SSIZE(DMA_ATTR_SIZE_16BIT) // Source data 16 bit 502 | | DMA_ATTR_DMOD(2) // Destination modulo 2 503 | | DMA_ATTR_DSIZE(DMA_ATTR_SIZE_16BIT); // Destination 16 bit 504 | DMA_TCD0_NBYTES_MLNO = 2; // Transfer two bytes in each service request 505 | DMA_TCD0_SLAST = 0;//-(DMA_BUFFER_SIZE*2); // Source address will always be newly written before each new start 506 | DMA_TCD0_DADDR = (volatile void *) &I2S0_TDR0; // Destination is the I2S data register 507 | DMA_TCD0_DOFF = 0; // No destination offset after each transfer 508 | DMA_TCD0_DLASTSGA = 0; // No scatter/gather 509 | DMA_TCD0_CITER_ELINKNO = DMA_BUFFER_SIZE & DMA_CITER_MASK; // Major loop iteration count = total samples (128) 510 | DMA_TCD0_BITER_ELINKNO = DMA_BUFFER_SIZE & DMA_BITER_MASK; // Major loop iteration count = total samples (128), no channel links 511 | DMA_TCD0_CSR = DMA_CSR_INTMAJOR // Interrupt on major loop completion 512 | | DMA_CSR_BWC(3); // DMA bandwidth control 513 | 514 | // enable DMA channel 0 requests 515 | // DMA_ERQ = DMA_ERQ_ERQ0; 516 | DMA_SERQ = DMA_SERQ_SERQ(0); 517 | 518 | // enable DMAMUX 519 | DMAMUX0_CHCFG0 |= DMAMUX_ENABLE /* | DMAMUX_TRIG */; 520 | 521 | // Set active 522 | DMA_TCD0_CSR |= DMA_CSR_ACTIVE; 523 | 524 | // To initiate from software, set DMA_CSR[start] 525 | //DMA_TCD0_CSR |= DMA_CSR_START; 526 | } 527 | 528 | void I2S_class::dma_receive_init(void) 529 | { 530 | // Enable clock to the DMAMUX module 531 | SIM_SCGC6 |= SIM_SCGC6_DMAMUX; 532 | // And clock to the DMA module 533 | SIM_SCGC7 |= SIM_SCGC7_DMA; 534 | 535 | // configure DMA_MUX 536 | // DMAMUX0_CHCFG1 = 0; 537 | DMAMUX0_CHCFG1 = DMAMUX_SOURCE_I2S0_RX; 538 | 539 | // Enable IRQ on the DMA channel 1 540 | NVIC_ENABLE_IRQ(IRQ_DMA_CH1); 541 | 542 | // Set inactive 543 | DMA_TCD1_CSR &= ~(DMA_CSR_ACTIVE); 544 | 545 | #ifndef ROUNDROBIN 546 | // Set channel priorities (each must be unique) 547 | DMA_DCHPRI3 = 0; 548 | DMA_DCHPRI2 = 1; 549 | DMA_DCHPRI1 = 2; 550 | DMA_DCHPRI0 = 3; // cannot be pre-empted, can pre-empt, highest priority 551 | #endif 552 | 553 | // Control register 554 | DMA_CR = 0 // Normal 555 | | DMA_CR_EMLM // Enable minor looping 556 | #ifdef ROUNDROBIN 557 | | DMA_CR_ERCA // Enable round-robin channel arbitration 558 | #endif 559 | ; 560 | 561 | // fill the TCD regs 562 | DMA_TCD1_SADDR = (const volatile void *) &I2S0_RDR0; // Source is the I2S data register 563 | DMA_TCD1_SOFF = 0; // No source offset after each transfer 564 | DMA_TCD1_ATTR = DMA_ATTR_SMOD(2) // No source modulo 565 | | DMA_ATTR_SSIZE(DMA_ATTR_SIZE_16BIT) // Source data 16 bit 566 | | DMA_ATTR_DMOD(0) // No destination modulo 567 | | DMA_ATTR_DSIZE(DMA_ATTR_SIZE_16BIT); // Destination 16 bit 568 | DMA_TCD1_NBYTES_MLNO = 2; // Transfer two bytes in each service request 569 | DMA_TCD1_SLAST = 0;//-(DMA_BUFFER_SIZE*2); // Source address will always be newly written before each new start 570 | DMA_TCD1_DADDR = (volatile void *) _dma_Rx_Buffer_A ; // Alternated with _dma_Buffer_B by our interrupt handler 571 | DMA_TCD1_DOFF = 2; // 2 bytes destination offset after each transfer 572 | DMA_TCD1_DLASTSGA = 0; // No scatter/gather 573 | DMA_TCD1_CITER_ELINKNO = DMA_BUFFER_SIZE & DMA_CITER_MASK; // Major loop iteration count = total samples (128) 574 | DMA_TCD1_BITER_ELINKNO = DMA_BUFFER_SIZE & DMA_BITER_MASK; // Major loop iteration count = total samples (128), no channel links 575 | DMA_TCD1_CSR = DMA_CSR_INTMAJOR // Interrupt on major loop completion 576 | | DMA_CSR_BWC(3); // DMA bandwidth control 577 | 578 | // enable DMA channel 1 requests 579 | // DMA_ERQ = DMA_ERQ_ERQ1; 580 | DMA_SERQ = DMA_SERQ_SERQ(1); 581 | 582 | // enable DMAMUX 583 | DMAMUX0_CHCFG1 |= DMAMUX_ENABLE /* | DMAMUX_TRIG */; 584 | 585 | // Set active 586 | DMA_TCD1_CSR |= DMA_CSR_ACTIVE; 587 | 588 | // To initiate from software, set DMA_CSR[start] 589 | //DMA_TCD1_CSR |= DMA_CSR_START; 590 | } 591 | 592 | 593 | 594 | void I2S_class::dma_start(void) 595 | { 596 | // Enable the appropriate channel 597 | DMA_SERQ = DMA_SERQ_SERQ( receive ); 598 | } 599 | 600 | void I2S_class::dma_stop(void) 601 | { 602 | // Clear Enable-flag of the appropriate channel 603 | DMA_CERQ = DMA_CERQ_CERQ( receive ); 604 | } 605 | 606 | 607 | /* DMA class-instance callbacks */ 608 | 609 | void I2S_class::dma_tx_callback(void) 610 | { 611 | _I2S_SAMPLE_T *dmaBuf; 612 | _I2S_SAMPLE_T *yourBuf; 613 | if (_dma_using_Buffer_A) 614 | { 615 | _dma_using_Buffer_A = 0; 616 | dmaBuf = _dma_Tx_Buffer_B; 617 | yourBuf = _dma_Tx_Buffer_A; 618 | } 619 | else 620 | { 621 | _dma_using_Buffer_A = 1; 622 | dmaBuf = _dma_Tx_Buffer_A; 623 | yourBuf = _dma_Tx_Buffer_B; 624 | } 625 | // DMA will play from one buffer 626 | DMA_TCD0_SADDR = (const volatile void *)dmaBuf; 627 | // while you fill the other 628 | fnDMACallback( yourBuf, DMA_BUFFER_SIZE ); 629 | } 630 | 631 | void I2S_class::dma_rx_callback(void) 632 | { 633 | _I2S_SAMPLE_T *dmaBuf; 634 | _I2S_SAMPLE_T *yourBuf; 635 | if (_dma_using_Buffer_A) 636 | { 637 | _dma_using_Buffer_A = 0; 638 | dmaBuf = _dma_Rx_Buffer_B; 639 | yourBuf = _dma_Rx_Buffer_A; 640 | } 641 | else 642 | { 643 | _dma_using_Buffer_A = 1; 644 | dmaBuf = _dma_Rx_Buffer_A; 645 | yourBuf = _dma_Rx_Buffer_B; 646 | } 647 | // DMA will read into one buffer 648 | DMA_TCD1_DADDR = (volatile void *)dmaBuf; 649 | // while you read the other 650 | fnDMACallback( yourBuf, DMA_BUFFER_SIZE ); 651 | } 652 | 653 | 654 | /* DMA ISR */ 655 | 656 | void dma_ch0_isr(void) // DMA channel 0 for Tx 657 | { 658 | I2STx0.dma_tx_callback(); 659 | DMA_CINT = DMA_CINT_CINT(0); // Clear the interrupt 660 | } 661 | 662 | void dma_ch1_isr(void) // DMA channel 1 for Rx 663 | { 664 | I2SRx0.dma_rx_callback(); 665 | DMA_CINT = DMA_CINT_CINT(1); // Clear the interrupt 666 | } 667 | -------------------------------------------------------------------------------- /mk20dx128.h: -------------------------------------------------------------------------------- 1 | /* Modifications for I2S based on teensy 1.15 rc2, see https://github.com/hughpyle/teensy-i2s */ 2 | 3 | /* Teensyduino Core Library 4 | * http://www.pjrc.com/teensy/ 5 | * Copyright (c) 2013 PJRC.COM, LLC. and contributors. 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining 8 | * a copy of this software and associated documentation files (the 9 | * "Software"), to deal in the Software without restriction, including 10 | * without limitation the rights to use, copy, modify, merge, publish, 11 | * distribute, sublicense, and/or sell copies of the Software, and to 12 | * permit persons to whom the Software is furnished to do so, subject to 13 | * the following conditions: 14 | * 15 | * 1. The above copyright notice and this permission notice shall be 16 | * included in all copies or substantial portions of the Software. 17 | * 18 | * 2. If the Software is incorporated into a build system that allows 19 | * selection among a list of target devices, then similar target 20 | * devices manufactured by PJRC.COM must be included in the list of 21 | * target devices and selectable in the same manner. 22 | * 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 | * SOFTWARE. 31 | */ 32 | 33 | #ifndef _mk20dx128_h_ 34 | #define _mk20dx128_h_ 35 | 36 | //#define F_CPU 96000000 37 | //#define F_CPU 48000000 38 | //#define F_CPU 24000000 39 | //#define F_BUS 48000000 40 | //#define F_BUS 24000000 41 | //#define F_MEM 24000000 42 | 43 | #if (F_CPU == 96000000) 44 | #define F_BUS 48000000 45 | #define F_MEM 24000000 46 | #elif (F_CPU == 48000000) 47 | #define F_BUS 48000000 48 | #define F_MEM 24000000 49 | #elif (F_CPU == 24000000) 50 | #define F_BUS 24000000 51 | #define F_MEM 24000000 52 | #endif 53 | 54 | 55 | #ifndef NULL 56 | #define NULL ((void *)0) 57 | #endif 58 | 59 | #include 60 | #ifdef __cplusplus 61 | extern "C" { 62 | #endif 63 | 64 | // chapter 11: Port control and interrupts (PORT) 65 | #define PORTA_PCR0 *(volatile uint32_t *)0x40049000 // Pin Control Register n 66 | #define PORT_PCR_ISF (uint32_t)0x01000000 // Interrupt Status Flag 67 | #define PORT_PCR_IRQC(n) (uint32_t)(((n) & 15) << 16) // Interrupt Configuration 68 | #define PORT_PCR_IRQC_MASK (uint32_t)0x000F0000 69 | #define PORT_PCR_LK (uint32_t)0x00008000 // Lock Register 70 | #define PORT_PCR_MUX(n) (uint32_t)(((n) & 7) << 8) // Pin Mux Control 71 | #define PORT_PCR_MUX_MASK (uint32_t)0x00000700 72 | #define PORT_PCR_DSE (uint32_t)0x00000040 // Drive Strength Enable 73 | #define PORT_PCR_ODE (uint32_t)0x00000020 // Open Drain Enable 74 | #define PORT_PCR_PFE (uint32_t)0x00000010 // Passive Filter Enable 75 | #define PORT_PCR_SRE (uint32_t)0x00000004 // Slew Rate Enable 76 | #define PORT_PCR_PE (uint32_t)0x00000002 // Pull Enable 77 | #define PORT_PCR_PS (uint32_t)0x00000001 // Pull Select 78 | #define PORTA_PCR1 *(volatile uint32_t *)0x40049004 // Pin Control Register n 79 | #define PORTA_PCR2 *(volatile uint32_t *)0x40049008 // Pin Control Register n 80 | #define PORTA_PCR3 *(volatile uint32_t *)0x4004900C // Pin Control Register n 81 | #define PORTA_PCR4 *(volatile uint32_t *)0x40049010 // Pin Control Register n 82 | #define PORTA_PCR5 *(volatile uint32_t *)0x40049014 // Pin Control Register n 83 | #define PORTA_PCR6 *(volatile uint32_t *)0x40049018 // Pin Control Register n 84 | #define PORTA_PCR7 *(volatile uint32_t *)0x4004901C // Pin Control Register n 85 | #define PORTA_PCR8 *(volatile uint32_t *)0x40049020 // Pin Control Register n 86 | #define PORTA_PCR9 *(volatile uint32_t *)0x40049024 // Pin Control Register n 87 | #define PORTA_PCR10 *(volatile uint32_t *)0x40049028 // Pin Control Register n 88 | #define PORTA_PCR11 *(volatile uint32_t *)0x4004902C // Pin Control Register n 89 | #define PORTA_PCR12 *(volatile uint32_t *)0x40049030 // Pin Control Register n 90 | #define PORTA_PCR13 *(volatile uint32_t *)0x40049034 // Pin Control Register n 91 | #define PORTA_PCR14 *(volatile uint32_t *)0x40049038 // Pin Control Register n 92 | #define PORTA_PCR15 *(volatile uint32_t *)0x4004903C // Pin Control Register n 93 | #define PORTA_PCR16 *(volatile uint32_t *)0x40049040 // Pin Control Register n 94 | #define PORTA_PCR17 *(volatile uint32_t *)0x40049044 // Pin Control Register n 95 | #define PORTA_PCR18 *(volatile uint32_t *)0x40049048 // Pin Control Register n 96 | #define PORTA_PCR19 *(volatile uint32_t *)0x4004904C // Pin Control Register n 97 | #define PORTA_PCR20 *(volatile uint32_t *)0x40049050 // Pin Control Register n 98 | #define PORTA_PCR21 *(volatile uint32_t *)0x40049054 // Pin Control Register n 99 | #define PORTA_PCR22 *(volatile uint32_t *)0x40049058 // Pin Control Register n 100 | #define PORTA_PCR23 *(volatile uint32_t *)0x4004905C // Pin Control Register n 101 | #define PORTA_PCR24 *(volatile uint32_t *)0x40049060 // Pin Control Register n 102 | #define PORTA_PCR25 *(volatile uint32_t *)0x40049064 // Pin Control Register n 103 | #define PORTA_PCR26 *(volatile uint32_t *)0x40049068 // Pin Control Register n 104 | #define PORTA_PCR27 *(volatile uint32_t *)0x4004906C // Pin Control Register n 105 | #define PORTA_PCR28 *(volatile uint32_t *)0x40049070 // Pin Control Register n 106 | #define PORTA_PCR29 *(volatile uint32_t *)0x40049074 // Pin Control Register n 107 | #define PORTA_PCR30 *(volatile uint32_t *)0x40049078 // Pin Control Register n 108 | #define PORTA_PCR31 *(volatile uint32_t *)0x4004907C // Pin Control Register n 109 | #define PORTA_GPCLR *(volatile uint32_t *)0x40049080 // Global Pin Control Low Register 110 | #define PORTA_GPCHR *(volatile uint32_t *)0x40049084 // Global Pin Control High Register 111 | #define PORTA_ISFR *(volatile uint32_t *)0x400490A0 // Interrupt Status Flag Register 112 | #define PORTB_PCR0 *(volatile uint32_t *)0x4004A000 // Pin Control Register n 113 | #define PORTB_PCR1 *(volatile uint32_t *)0x4004A004 // Pin Control Register n 114 | #define PORTB_PCR2 *(volatile uint32_t *)0x4004A008 // Pin Control Register n 115 | #define PORTB_PCR3 *(volatile uint32_t *)0x4004A00C // Pin Control Register n 116 | #define PORTB_PCR4 *(volatile uint32_t *)0x4004A010 // Pin Control Register n 117 | #define PORTB_PCR5 *(volatile uint32_t *)0x4004A014 // Pin Control Register n 118 | #define PORTB_PCR6 *(volatile uint32_t *)0x4004A018 // Pin Control Register n 119 | #define PORTB_PCR7 *(volatile uint32_t *)0x4004A01C // Pin Control Register n 120 | #define PORTB_PCR8 *(volatile uint32_t *)0x4004A020 // Pin Control Register n 121 | #define PORTB_PCR9 *(volatile uint32_t *)0x4004A024 // Pin Control Register n 122 | #define PORTB_PCR10 *(volatile uint32_t *)0x4004A028 // Pin Control Register n 123 | #define PORTB_PCR11 *(volatile uint32_t *)0x4004A02C // Pin Control Register n 124 | #define PORTB_PCR12 *(volatile uint32_t *)0x4004A030 // Pin Control Register n 125 | #define PORTB_PCR13 *(volatile uint32_t *)0x4004A034 // Pin Control Register n 126 | #define PORTB_PCR14 *(volatile uint32_t *)0x4004A038 // Pin Control Register n 127 | #define PORTB_PCR15 *(volatile uint32_t *)0x4004A03C // Pin Control Register n 128 | #define PORTB_PCR16 *(volatile uint32_t *)0x4004A040 // Pin Control Register n 129 | #define PORTB_PCR17 *(volatile uint32_t *)0x4004A044 // Pin Control Register n 130 | #define PORTB_PCR18 *(volatile uint32_t *)0x4004A048 // Pin Control Register n 131 | #define PORTB_PCR19 *(volatile uint32_t *)0x4004A04C // Pin Control Register n 132 | #define PORTB_PCR20 *(volatile uint32_t *)0x4004A050 // Pin Control Register n 133 | #define PORTB_PCR21 *(volatile uint32_t *)0x4004A054 // Pin Control Register n 134 | #define PORTB_PCR22 *(volatile uint32_t *)0x4004A058 // Pin Control Register n 135 | #define PORTB_PCR23 *(volatile uint32_t *)0x4004A05C // Pin Control Register n 136 | #define PORTB_PCR24 *(volatile uint32_t *)0x4004A060 // Pin Control Register n 137 | #define PORTB_PCR25 *(volatile uint32_t *)0x4004A064 // Pin Control Register n 138 | #define PORTB_PCR26 *(volatile uint32_t *)0x4004A068 // Pin Control Register n 139 | #define PORTB_PCR27 *(volatile uint32_t *)0x4004A06C // Pin Control Register n 140 | #define PORTB_PCR28 *(volatile uint32_t *)0x4004A070 // Pin Control Register n 141 | #define PORTB_PCR29 *(volatile uint32_t *)0x4004A074 // Pin Control Register n 142 | #define PORTB_PCR30 *(volatile uint32_t *)0x4004A078 // Pin Control Register n 143 | #define PORTB_PCR31 *(volatile uint32_t *)0x4004A07C // Pin Control Register n 144 | #define PORTB_GPCLR *(volatile uint32_t *)0x4004A080 // Global Pin Control Low Register 145 | #define PORTB_GPCHR *(volatile uint32_t *)0x4004A084 // Global Pin Control High Register 146 | #define PORTB_ISFR *(volatile uint32_t *)0x4004A0A0 // Interrupt Status Flag Register 147 | #define PORTC_PCR0 *(volatile uint32_t *)0x4004B000 // Pin Control Register n 148 | #define PORTC_PCR1 *(volatile uint32_t *)0x4004B004 // Pin Control Register n 149 | #define PORTC_PCR2 *(volatile uint32_t *)0x4004B008 // Pin Control Register n 150 | #define PORTC_PCR3 *(volatile uint32_t *)0x4004B00C // Pin Control Register n 151 | #define PORTC_PCR4 *(volatile uint32_t *)0x4004B010 // Pin Control Register n 152 | #define PORTC_PCR5 *(volatile uint32_t *)0x4004B014 // Pin Control Register n 153 | #define PORTC_PCR6 *(volatile uint32_t *)0x4004B018 // Pin Control Register n 154 | #define PORTC_PCR7 *(volatile uint32_t *)0x4004B01C // Pin Control Register n 155 | #define PORTC_PCR8 *(volatile uint32_t *)0x4004B020 // Pin Control Register n 156 | #define PORTC_PCR9 *(volatile uint32_t *)0x4004B024 // Pin Control Register n 157 | #define PORTC_PCR10 *(volatile uint32_t *)0x4004B028 // Pin Control Register n 158 | #define PORTC_PCR11 *(volatile uint32_t *)0x4004B02C // Pin Control Register n 159 | #define PORTC_PCR12 *(volatile uint32_t *)0x4004B030 // Pin Control Register n 160 | #define PORTC_PCR13 *(volatile uint32_t *)0x4004B034 // Pin Control Register n 161 | #define PORTC_PCR14 *(volatile uint32_t *)0x4004B038 // Pin Control Register n 162 | #define PORTC_PCR15 *(volatile uint32_t *)0x4004B03C // Pin Control Register n 163 | #define PORTC_PCR16 *(volatile uint32_t *)0x4004B040 // Pin Control Register n 164 | #define PORTC_PCR17 *(volatile uint32_t *)0x4004B044 // Pin Control Register n 165 | #define PORTC_PCR18 *(volatile uint32_t *)0x4004B048 // Pin Control Register n 166 | #define PORTC_PCR19 *(volatile uint32_t *)0x4004B04C // Pin Control Register n 167 | #define PORTC_PCR20 *(volatile uint32_t *)0x4004B050 // Pin Control Register n 168 | #define PORTC_PCR21 *(volatile uint32_t *)0x4004B054 // Pin Control Register n 169 | #define PORTC_PCR22 *(volatile uint32_t *)0x4004B058 // Pin Control Register n 170 | #define PORTC_PCR23 *(volatile uint32_t *)0x4004B05C // Pin Control Register n 171 | #define PORTC_PCR24 *(volatile uint32_t *)0x4004B060 // Pin Control Register n 172 | #define PORTC_PCR25 *(volatile uint32_t *)0x4004B064 // Pin Control Register n 173 | #define PORTC_PCR26 *(volatile uint32_t *)0x4004B068 // Pin Control Register n 174 | #define PORTC_PCR27 *(volatile uint32_t *)0x4004B06C // Pin Control Register n 175 | #define PORTC_PCR28 *(volatile uint32_t *)0x4004B070 // Pin Control Register n 176 | #define PORTC_PCR29 *(volatile uint32_t *)0x4004B074 // Pin Control Register n 177 | #define PORTC_PCR30 *(volatile uint32_t *)0x4004B078 // Pin Control Register n 178 | #define PORTC_PCR31 *(volatile uint32_t *)0x4004B07C // Pin Control Register n 179 | #define PORTC_GPCLR *(volatile uint32_t *)0x4004B080 // Global Pin Control Low Register 180 | #define PORTC_GPCHR *(volatile uint32_t *)0x4004B084 // Global Pin Control High Register 181 | #define PORTC_ISFR *(volatile uint32_t *)0x4004B0A0 // Interrupt Status Flag Register 182 | #define PORTD_PCR0 *(volatile uint32_t *)0x4004C000 // Pin Control Register n 183 | #define PORTD_PCR1 *(volatile uint32_t *)0x4004C004 // Pin Control Register n 184 | #define PORTD_PCR2 *(volatile uint32_t *)0x4004C008 // Pin Control Register n 185 | #define PORTD_PCR3 *(volatile uint32_t *)0x4004C00C // Pin Control Register n 186 | #define PORTD_PCR4 *(volatile uint32_t *)0x4004C010 // Pin Control Register n 187 | #define PORTD_PCR5 *(volatile uint32_t *)0x4004C014 // Pin Control Register n 188 | #define PORTD_PCR6 *(volatile uint32_t *)0x4004C018 // Pin Control Register n 189 | #define PORTD_PCR7 *(volatile uint32_t *)0x4004C01C // Pin Control Register n 190 | #define PORTD_PCR8 *(volatile uint32_t *)0x4004C020 // Pin Control Register n 191 | #define PORTD_PCR9 *(volatile uint32_t *)0x4004C024 // Pin Control Register n 192 | #define PORTD_PCR10 *(volatile uint32_t *)0x4004C028 // Pin Control Register n 193 | #define PORTD_PCR11 *(volatile uint32_t *)0x4004C02C // Pin Control Register n 194 | #define PORTD_PCR12 *(volatile uint32_t *)0x4004C030 // Pin Control Register n 195 | #define PORTD_PCR13 *(volatile uint32_t *)0x4004C034 // Pin Control Register n 196 | #define PORTD_PCR14 *(volatile uint32_t *)0x4004C038 // Pin Control Register n 197 | #define PORTD_PCR15 *(volatile uint32_t *)0x4004C03C // Pin Control Register n 198 | #define PORTD_PCR16 *(volatile uint32_t *)0x4004C040 // Pin Control Register n 199 | #define PORTD_PCR17 *(volatile uint32_t *)0x4004C044 // Pin Control Register n 200 | #define PORTD_PCR18 *(volatile uint32_t *)0x4004C048 // Pin Control Register n 201 | #define PORTD_PCR19 *(volatile uint32_t *)0x4004C04C // Pin Control Register n 202 | #define PORTD_PCR20 *(volatile uint32_t *)0x4004C050 // Pin Control Register n 203 | #define PORTD_PCR21 *(volatile uint32_t *)0x4004C054 // Pin Control Register n 204 | #define PORTD_PCR22 *(volatile uint32_t *)0x4004C058 // Pin Control Register n 205 | #define PORTD_PCR23 *(volatile uint32_t *)0x4004C05C // Pin Control Register n 206 | #define PORTD_PCR24 *(volatile uint32_t *)0x4004C060 // Pin Control Register n 207 | #define PORTD_PCR25 *(volatile uint32_t *)0x4004C064 // Pin Control Register n 208 | #define PORTD_PCR26 *(volatile uint32_t *)0x4004C068 // Pin Control Register n 209 | #define PORTD_PCR27 *(volatile uint32_t *)0x4004C06C // Pin Control Register n 210 | #define PORTD_PCR28 *(volatile uint32_t *)0x4004C070 // Pin Control Register n 211 | #define PORTD_PCR29 *(volatile uint32_t *)0x4004C074 // Pin Control Register n 212 | #define PORTD_PCR30 *(volatile uint32_t *)0x4004C078 // Pin Control Register n 213 | #define PORTD_PCR31 *(volatile uint32_t *)0x4004C07C // Pin Control Register n 214 | #define PORTD_GPCLR *(volatile uint32_t *)0x4004C080 // Global Pin Control Low Register 215 | #define PORTD_GPCHR *(volatile uint32_t *)0x4004C084 // Global Pin Control High Register 216 | #define PORTD_ISFR *(volatile uint32_t *)0x4004C0A0 // Interrupt Status Flag Register 217 | #define PORTE_PCR0 *(volatile uint32_t *)0x4004D000 // Pin Control Register n 218 | #define PORTE_PCR1 *(volatile uint32_t *)0x4004D004 // Pin Control Register n 219 | #define PORTE_PCR2 *(volatile uint32_t *)0x4004D008 // Pin Control Register n 220 | #define PORTE_PCR3 *(volatile uint32_t *)0x4004D00C // Pin Control Register n 221 | #define PORTE_PCR4 *(volatile uint32_t *)0x4004D010 // Pin Control Register n 222 | #define PORTE_PCR5 *(volatile uint32_t *)0x4004D014 // Pin Control Register n 223 | #define PORTE_PCR6 *(volatile uint32_t *)0x4004D018 // Pin Control Register n 224 | #define PORTE_PCR7 *(volatile uint32_t *)0x4004D01C // Pin Control Register n 225 | #define PORTE_PCR8 *(volatile uint32_t *)0x4004D020 // Pin Control Register n 226 | #define PORTE_PCR9 *(volatile uint32_t *)0x4004D024 // Pin Control Register n 227 | #define PORTE_PCR10 *(volatile uint32_t *)0x4004D028 // Pin Control Register n 228 | #define PORTE_PCR11 *(volatile uint32_t *)0x4004D02C // Pin Control Register n 229 | #define PORTE_PCR12 *(volatile uint32_t *)0x4004D030 // Pin Control Register n 230 | #define PORTE_PCR13 *(volatile uint32_t *)0x4004D034 // Pin Control Register n 231 | #define PORTE_PCR14 *(volatile uint32_t *)0x4004D038 // Pin Control Register n 232 | #define PORTE_PCR15 *(volatile uint32_t *)0x4004D03C // Pin Control Register n 233 | #define PORTE_PCR16 *(volatile uint32_t *)0x4004D040 // Pin Control Register n 234 | #define PORTE_PCR17 *(volatile uint32_t *)0x4004D044 // Pin Control Register n 235 | #define PORTE_PCR18 *(volatile uint32_t *)0x4004D048 // Pin Control Register n 236 | #define PORTE_PCR19 *(volatile uint32_t *)0x4004D04C // Pin Control Register n 237 | #define PORTE_PCR20 *(volatile uint32_t *)0x4004D050 // Pin Control Register n 238 | #define PORTE_PCR21 *(volatile uint32_t *)0x4004D054 // Pin Control Register n 239 | #define PORTE_PCR22 *(volatile uint32_t *)0x4004D058 // Pin Control Register n 240 | #define PORTE_PCR23 *(volatile uint32_t *)0x4004D05C // Pin Control Register n 241 | #define PORTE_PCR24 *(volatile uint32_t *)0x4004D060 // Pin Control Register n 242 | #define PORTE_PCR25 *(volatile uint32_t *)0x4004D064 // Pin Control Register n 243 | #define PORTE_PCR26 *(volatile uint32_t *)0x4004D068 // Pin Control Register n 244 | #define PORTE_PCR27 *(volatile uint32_t *)0x4004D06C // Pin Control Register n 245 | #define PORTE_PCR28 *(volatile uint32_t *)0x4004D070 // Pin Control Register n 246 | #define PORTE_PCR29 *(volatile uint32_t *)0x4004D074 // Pin Control Register n 247 | #define PORTE_PCR30 *(volatile uint32_t *)0x4004D078 // Pin Control Register n 248 | #define PORTE_PCR31 *(volatile uint32_t *)0x4004D07C // Pin Control Register n 249 | #define PORTE_GPCLR *(volatile uint32_t *)0x4004D080 // Global Pin Control Low Register 250 | #define PORTE_GPCHR *(volatile uint32_t *)0x4004D084 // Global Pin Control High Register 251 | #define PORTE_ISFR *(volatile uint32_t *)0x4004D0A0 // Interrupt Status Flag Register 252 | 253 | // Chapter 12: System Integration Module (SIM) 254 | #define SIM_SOPT1 *(volatile uint32_t *)0x40047000 // System Options Register 1 255 | #define SIM_SOPT1CFG *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register 256 | #define SIM_SOPT2 *(volatile uint32_t *)0x40048004 // System Options Register 2 257 | #define SIM_SOPT2_USBSRC (uint32_t)0x00040000 // 0=USB_CLKIN, 1=FFL/PLL 258 | #define SIM_SOPT2_PLLFLLSEL (uint32_t)0x00010000 // 0=FLL, 1=PLL 259 | #define SIM_SOPT2_TRACECLKSEL (uint32_t)0x00001000 // 0=MCGOUTCLK, 1=CPU 260 | #define SIM_SOPT2_PTD7PAD (uint32_t)0x00000800 // 0=normal, 1=double drive PTD7 261 | #define SIM_SOPT2_CLKOUTSEL(n) (uint32_t)(((n) & 7) << 5) // Selects the clock to output on the CLKOUT pin. 262 | #define SIM_SOPT2_RTCCLKOUTSEL (uint32_t)0x00000010 // RTC clock out select 263 | #define SIM_SOPT4 *(volatile uint32_t *)0x4004800C // System Options Register 4 264 | #define SIM_SOPT5 *(volatile uint32_t *)0x40048010 // System Options Register 5 265 | #define SIM_SOPT7 *(volatile uint32_t *)0x40048018 // System Options Register 7 266 | #define SIM_SDID *(const uint32_t *)0x40048024 // System Device Identification Register 267 | #define SIM_SCGC4 *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4 268 | #define SIM_SCGC4_VREF (uint32_t)0x00100000 // VREF Clock Gate Control 269 | #define SIM_SCGC4_CMP (uint32_t)0x00080000 // Comparator Clock Gate Control 270 | #define SIM_SCGC4_USBOTG (uint32_t)0x00040000 // USB Clock Gate Control 271 | #define SIM_SCGC4_UART2 (uint32_t)0x00001000 // UART2 Clock Gate Control 272 | #define SIM_SCGC4_UART1 (uint32_t)0x00000800 // UART1 Clock Gate Control 273 | #define SIM_SCGC4_UART0 (uint32_t)0x00000400 // UART0 Clock Gate Control 274 | #define SIM_SCGC4_I2C0 (uint32_t)0x00000040 // I2C0 Clock Gate Control 275 | #define SIM_SCGC4_CMT (uint32_t)0x00000004 // CMT Clock Gate Control 276 | #define SIM_SCGC4_EWM (uint32_t)0x00000002 // EWM Clock Gate Control 277 | #define SIM_SCGC5 *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5 278 | #define SIM_SCGC5_PORTE (uint32_t)0x00002000 // Port E Clock Gate Control 279 | #define SIM_SCGC5_PORTD (uint32_t)0x00001000 // Port D Clock Gate Control 280 | #define SIM_SCGC5_PORTC (uint32_t)0x00000800 // Port C Clock Gate Control 281 | #define SIM_SCGC5_PORTB (uint32_t)0x00000400 // Port B Clock Gate Control 282 | #define SIM_SCGC5_PORTA (uint32_t)0x00000200 // Port A Clock Gate Control 283 | #define SIM_SCGC5_TSI (uint32_t)0x00000020 // Touch Sense Input TSI Clock Gate Control 284 | #define SIM_SCGC5_LPTIMER (uint32_t)0x00000001 // Low Power Timer Access Control 285 | #define SIM_SCGC6 *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6 286 | #define SIM_SCGC6_RTC (uint32_t)0x20000000 // RTC Access 287 | #define SIM_SCGC6_ADC0 (uint32_t)0x08000000 // ADC0 Clock Gate Control 288 | #define SIM_SCGC6_FTM1 (uint32_t)0x02000000 // FTM1 Clock Gate Control 289 | #define SIM_SCGC6_FTM0 (uint32_t)0x01000000 // FTM0 Clock Gate Control 290 | #define SIM_SCGC6_PIT (uint32_t)0x00800000 // PIT Clock Gate Control 291 | #define SIM_SCGC6_PDB (uint32_t)0x00400000 // PDB Clock Gate Control 292 | #define SIM_SCGC6_USBDCD (uint32_t)0x00200000 // USB DCD Clock Gate Control 293 | #define SIM_SCGC6_CRC (uint32_t)0x00040000 // CRC Clock Gate Control 294 | #define SIM_SCGC6_I2S (uint32_t)0x00008000 // I2S Clock Gate Control 295 | #define SIM_SCGC6_SPI0 (uint32_t)0x00001000 // SPI0 Clock Gate Control 296 | #define SIM_SCGC6_DMAMUX (uint32_t)0x00000002 // DMA Mux Clock Gate Control 297 | #define SIM_SCGC6_FTFL (uint32_t)0x00000001 // Flash Memory Clock Gate Control 298 | #define SIM_SCGC7 *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7 299 | #define SIM_SCGC7_DMA (uint32_t)0x00000020 // DMA Clock Gate Control 300 | #define SIM_CLKDIV1 *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1 301 | #define SIM_CLKDIV1_OUTDIV1(n) (uint32_t)(((n) & 0x0F) << 28) // divide value for the core/system clock 302 | #define SIM_CLKDIV1_OUTDIV2(n) (uint32_t)(((n) & 0x0F) << 24) // divide value for the peripheral clock 303 | #define SIM_CLKDIV1_OUTDIV4(n) (uint32_t)(((n) & 0x0F) << 16) // divide value for the flash clock 304 | #define SIM_CLKDIV2 *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2 305 | #define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) 306 | #define SIM_CLKDIV2_USBFRAC (uint32_t)0x01 307 | #define SIM_FCFG1 *(const uint32_t *)0x4004804C // Flash Configuration Register 1 308 | #define SIM_FCFG2 *(const uint32_t *)0x40048050 // Flash Configuration Register 2 309 | #define SIM_UIDH *(const uint32_t *)0x40048054 // Unique Identification Register High 310 | #define SIM_UIDMH *(const uint32_t *)0x40048058 // Unique Identification Register Mid-High 311 | #define SIM_UIDML *(const uint32_t *)0x4004805C // Unique Identification Register Mid Low 312 | #define SIM_UIDL *(const uint32_t *)0x40048060 // Unique Identification Register Low 313 | 314 | // Chapter 13: Reset Control Module (RCM) 315 | #define RCM_SRS0 *(volatile uint8_t *)0x4007F000 // System Reset Status Register 0 316 | #define RCM_SRS1 *(volatile uint8_t *)0x4007F001 // System Reset Status Register 1 317 | #define RCM_RPFC *(volatile uint8_t *)0x4007F004 // Reset Pin Filter Control Register 318 | #define RCM_RPFW *(volatile uint8_t *)0x4007F005 // Reset Pin Filter Width Register 319 | #define RCM_MR *(volatile uint8_t *)0x4007F007 // Mode Register 320 | 321 | // Chapter 14: System Mode Controller 322 | #define SMC_PMPROT *(volatile uint8_t *)0x4007E000 // Power Mode Protection Register 323 | #define SMC_PMPROT_AVLP (uint8_t)0x20 // Allow very low power modes 324 | #define SMC_PMPROT_ALLS (uint8_t)0x08 // Allow low leakage stop mode 325 | #define SMC_PMPROT_AVLLS (uint8_t)0x02 // Allow very low leakage stop mode 326 | #define SMC_PMCTRL *(volatile uint8_t *)0x4007E001 // Power Mode Control Register 327 | #define SMC_PMCTRL_LPWUI (uint8_t)0x80 // Low Power Wake Up on Interrupt 328 | #define SMC_PMCTRL_RUNM(n) (uint8_t)(((n) & 0x03) << 5) // Run Mode Control 329 | #define SMC_PMCTRL_STOPA (uint8_t)0x08 // Stop Aborted 330 | #define SMC_PMCTRL_STOPM(n) (uint8_t)((n) & 0x07) // Stop Mode Control 331 | #define SMC_VLLSCTRL *(volatile uint8_t *)0x4007E002 // VLLS Control Register 332 | #define SMC_VLLSCTRL_PORPO (uint8_t)0x20 // POR Power Option 333 | #define SMC_VLLSCTRL_VLLSM(n) (uint8_t)((n) & 0x07) // VLLS Mode Control 334 | #define SMC_PMSTAT *(volatile uint8_t *)0x4007E003 // Power Mode Status Register 335 | #define SMC_PMSTAT_RUN (uint8_t)0x01 // Current power mode is RUN 336 | #define SMC_PMSTAT_STOP (uint8_t)0x02 // Current power mode is STOP 337 | #define SMC_PMSTAT_VLPR (uint8_t)0x04 // Current power mode is VLPR 338 | #define SMC_PMSTAT_VLPW (uint8_t)0x08 // Current power mode is VLPW 339 | #define SMC_PMSTAT_VLPS (uint8_t)0x10 // Current power mode is VLPS 340 | #define SMC_PMSTAT_LLS (uint8_t)0x20 // Current power mode is LLS 341 | #define SMC_PMSTAT_VLLS (uint8_t)0x40 // Current power mode is VLLS 342 | 343 | // Chapter 15: Power Management Controller 344 | #define PMC_LVDSC1 *(volatile uint8_t *)0x4007D000 // Low Voltage Detect Status And Control 1 register 345 | #define PMC_LVDSC1_LVDF (uint8_t)0x80 // Low-Voltage Detect Flag 346 | #define PMC_LVDSC1_LVDACK (uint8_t)0x40 // Low-Voltage Detect Acknowledge 347 | #define PMC_LVDSC1_LVDIE (uint8_t)0x20 // Low-Voltage Detect Interrupt Enable 348 | #define PMC_LVDSC1_LVDRE (uint8_t)0x10 // Low-Voltage Detect Reset Enable 349 | #define PMC_LVDSC1_LVDV(n) (uint8_t)((n) & 0x03) // Low-Voltage Detect Voltage Select 350 | #define PMC_LVDSC2 *(volatile uint8_t *)0x4007D001 // Low Voltage Detect Status And Control 2 register 351 | #define PMC_LVDSC2_LVWF (uint8_t)0x80 // Low-Voltage Warning Flag 352 | #define PMC_LVDSC2_LVWACK (uint8_t)0x40 // Low-Voltage Warning Acknowledge 353 | #define PMC_LVDSC2_LVWIE (uint8_t)0x20 // Low-Voltage Warning Interrupt Enable 354 | #define PMC_LVDSC2_LVWV(n) (uint8_t)((n) & 0x03) // Low-Voltage Warning Voltage Select 355 | #define PMC_REGSC *(volatile uint8_t *)0x4007D002 // Regulator Status And Control register 356 | #define PMC_REGSC_BGEN (uint8_t)0x10 // Bandgap Enable In VLPx Operation 357 | #define PMC_REGSC_ACKISO (uint8_t)0x08 // Acknowledge Isolation 358 | #define PMC_REGSC_REGONS (uint8_t)0x04 // Regulator In Run Regulation Status 359 | #define PMC_REGSC_BGBE (uint8_t)0x01 // Bandgap Buffer Enable 360 | 361 | // Chapter 16: Low-Leakage Wakeup Unit (LLWU) 362 | #define LLWU_PE1 *(volatile uint8_t *)0x4007C000 // LLWU Pin Enable 1 register 363 | #define LLWU_PE2 *(volatile uint8_t *)0x4007C001 // LLWU Pin Enable 2 register 364 | #define LLWU_PE3 *(volatile uint8_t *)0x4007C002 // LLWU Pin Enable 3 register 365 | #define LLWU_PE4 *(volatile uint8_t *)0x4007C003 // LLWU Pin Enable 4 register 366 | #define LLWU_ME *(volatile uint8_t *)0x4007C004 // LLWU Module Enable register 367 | #define LLWU_F1 *(volatile uint8_t *)0x4007C005 // LLWU Flag 1 register 368 | #define LLWU_F2 *(volatile uint8_t *)0x4007C006 // LLWU Flag 2 register 369 | #define LLWU_F3 *(volatile uint8_t *)0x4007C007 // LLWU Flag 3 register 370 | #define LLWU_FILT1 *(volatile uint8_t *)0x4007C008 // LLWU Pin Filter 1 register 371 | #define LLWU_FILT2 *(volatile uint8_t *)0x4007C009 // LLWU Pin Filter 2 register 372 | #define LLWU_RST *(volatile uint8_t *)0x4007C00A // LLWU Reset Enable register 373 | 374 | // Chapter 17: Miscellaneous Control Module (MCM) 375 | #define MCM_PLASC *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration 376 | #define MCM_PLAMC *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration 377 | #define MCM_PLACR *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register 378 | 379 | // Chapter 20: Direct Memory Access Multiplexer (DMAMUX) 380 | #define DMAMUX0_CHCFG0 *(volatile uint8_t *)0x40021000 // Channel Configuration register 381 | #define DMAMUX0_CHCFG1 *(volatile uint8_t *)0x40021001 // Channel Configuration register 382 | #define DMAMUX0_CHCFG2 *(volatile uint8_t *)0x40021002 // Channel Configuration register 383 | #define DMAMUX0_CHCFG3 *(volatile uint8_t *)0x40021003 // Channel Configuration register 384 | #define DMAMUX0_CHCFG4 *(volatile uint8_t *)0x40021004 // Channel Configuration register 385 | #define DMAMUX0_CHCFG5 *(volatile uint8_t *)0x40021005 // Channel Configuration register 386 | #define DMAMUX0_CHCFG6 *(volatile uint8_t *)0x40021006 // Channel Configuration register 387 | #define DMAMUX0_CHCFG7 *(volatile uint8_t *)0x40021007 // Channel Configuration register 388 | #define DMAMUX0_CHCFG8 *(volatile uint8_t *)0x40021008 // Channel Configuration register 389 | #define DMAMUX0_CHCFG9 *(volatile uint8_t *)0x40021009 // Channel Configuration register 390 | #define DMAMUX0_CHCFG10 *(volatile uint8_t *)0x4002100A // Channel Configuration register 391 | #define DMAMUX0_CHCFG11 *(volatile uint8_t *)0x4002100B // Channel Configuration register 392 | #define DMAMUX0_CHCFG12 *(volatile uint8_t *)0x4002100C // Channel Configuration register 393 | #define DMAMUX0_CHCFG13 *(volatile uint8_t *)0x4002100D // Channel Configuration register 394 | #define DMAMUX0_CHCFG14 *(volatile uint8_t *)0x4002100E // Channel Configuration register 395 | #define DMAMUX0_CHCFG15 *(volatile uint8_t *)0x4002100F // Channel Configuration register 396 | #define DMAMUX_DISABLE 0 397 | #define DMAMUX_TRIG 64 398 | #define DMAMUX_ENABLE 128 399 | #define DMAMUX_SOURCE_UART0_RX 2 400 | #define DMAMUX_SOURCE_UART0_TX 3 401 | #define DMAMUX_SOURCE_UART1_RX 4 402 | #define DMAMUX_SOURCE_UART1_TX 5 403 | #define DMAMUX_SOURCE_UART2_RX 6 404 | #define DMAMUX_SOURCE_UART2_TX 7 405 | #define DMAMUX_SOURCE_I2S0_RX 14 406 | #define DMAMUX_SOURCE_I2S0_TX 15 407 | #define DMAMUX_SOURCE_SPI0_RX 16 408 | #define DMAMUX_SOURCE_SPI0_TX 17 409 | #define DMAMUX_SOURCE_I2C0 22 410 | #define DMAMUX_SOURCE_FTM0_CH0 24 411 | #define DMAMUX_SOURCE_FTM0_CH1 25 412 | #define DMAMUX_SOURCE_FTM0_CH2 26 413 | #define DMAMUX_SOURCE_FTM0_CH3 27 414 | #define DMAMUX_SOURCE_FTM0_CH4 28 415 | #define DMAMUX_SOURCE_FTM0_CH5 29 416 | #define DMAMUX_SOURCE_FTM0_CH6 30 417 | #define DMAMUX_SOURCE_FTM0_CH7 31 418 | #define DMAMUX_SOURCE_FTM1_CH0 32 419 | #define DMAMUX_SOURCE_FTM1_CH1 33 420 | #define DMAMUX_SOURCE_ADC0 40 421 | #define DMAMUX_SOURCE_CMP0 42 422 | #define DMAMUX_SOURCE_CMP1 43 423 | #define DMAMUX_SOURCE_CMT 47 424 | #define DMAMUX_SOURCE_PDB 48 425 | #define DMAMUX_SOURCE_PORTA 49 426 | #define DMAMUX_SOURCE_PORTB 50 427 | #define DMAMUX_SOURCE_PORTC 51 428 | #define DMAMUX_SOURCE_PORTD 52 429 | #define DMAMUX_SOURCE_PORTE 53 430 | #define DMAMUX_SOURCE_ALWAYS0 54 431 | #define DMAMUX_SOURCE_ALWAYS1 55 432 | #define DMAMUX_SOURCE_ALWAYS2 56 433 | #define DMAMUX_SOURCE_ALWAYS3 57 434 | #define DMAMUX_SOURCE_ALWAYS4 58 435 | #define DMAMUX_SOURCE_ALWAYS5 59 436 | #define DMAMUX_SOURCE_ALWAYS6 60 437 | #define DMAMUX_SOURCE_ALWAYS7 61 438 | #define DMAMUX_SOURCE_ALWAYS8 62 439 | #define DMAMUX_SOURCE_ALWAYS9 63 440 | 441 | // Chapter 21: Direct Memory Access Controller (eDMA) 442 | #define DMA_CR *(volatile uint32_t *)0x40008000 // Control Register 443 | #define DMA_ES *(volatile uint32_t *)0x40008004 // Error Status Register 444 | #define DMA_ERQ *(volatile uint32_t *)0x4000800C // Enable Request Register 445 | #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register 446 | #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register 447 | #define DMA_SEEI *(volatile uint8_t *)0x40008019 // Set Enable Error Interrupt Register 448 | #define DMA_CERQ *(volatile uint8_t *)0x4000801A // Clear Enable Request Register 449 | #define DMA_SERQ *(volatile uint8_t *)0x4000801B // Set Enable Request Register 450 | #define DMA_CDNE *(volatile uint8_t *)0x4000801C // Clear DONE Status Bit Register 451 | #define DMA_SSRT *(volatile uint8_t *)0x4000801D // Set START Bit Register 452 | #define DMA_CERR *(volatile uint8_t *)0x4000801E // Clear Error Register 453 | #define DMA_CINT *(volatile uint8_t *)0x4000801F // Clear Interrupt Request Register 454 | #define DMA_INT *(volatile uint32_t *)0x40008024 // Interrupt Request Register 455 | #define DMA_ERR *(volatile uint32_t *)0x4000802C // Error Register 456 | #define DMA_HRS *(volatile uint32_t *)0x40008034 // Hardware Request Status Register 457 | #define DMA_DCHPRI3 *(volatile uint8_t *)0x40008100 // Channel n Priority Register 458 | #define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register 459 | #define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register 460 | #define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register 461 | 462 | #define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11) 463 | #define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8) 464 | #define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3) 465 | #define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0) 466 | #define DMA_TCD_ATTR_SIZE_8BIT 0 467 | #define DMA_TCD_ATTR_SIZE_16BIT 1 468 | #define DMA_TCD_ATTR_SIZE_32BIT 2 469 | #define DMA_TCD_ATTR_SIZE_16BYTE 4 470 | #define DMA_TCD_ATTR_SIZE_32BYTE 5 471 | #define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14) 472 | #define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0x3) << 8) 473 | #define DMA_TCD_CSR_DONE 0x0080 474 | #define DMA_TCD_CSR_ACTIVE 0x0040 475 | #define DMA_TCD_CSR_MAJORELINK 0x0020 476 | #define DMA_TCD_CSR_ESG 0x0010 477 | #define DMA_TCD_CSR_DREQ 0x0008 478 | #define DMA_TCD_CSR_INTHALF 0x0004 479 | #define DMA_TCD_CSR_INTMAJOR 0x0002 480 | #define DMA_TCD_CSR_START 0x0001 481 | 482 | #define DMA_TCD0_SADDR *(volatile const void * volatile *)0x40009000 // TCD Source Address 483 | #define DMA_TCD0_SOFF *(volatile int16_t *)0x40009004 // TCD Signed Source Address Offset 484 | #define DMA_TCD0_ATTR *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes 485 | #define DMA_TCD0_NBYTES_MLNO *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled) 486 | #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) 487 | #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) 488 | #define DMA_TCD0_SLAST *(volatile int32_t *)0x4000900C // TCD Last Source Address Adjustment 489 | #define DMA_TCD0_DADDR *(volatile void * volatile *)0x40009010 // TCD Destination Address 490 | #define DMA_TCD0_DOFF *(volatile int16_t *)0x40009014 // TCD Signed Destination Address Offset 491 | #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 492 | #define DMA_TCD0_CITER_ELINKNO *(volatile uint16_t *)0x40009016 // ?? 493 | #define DMA_TCD0_DLASTSGA *(volatile int32_t *)0x40009018 // TCD Last Destination Address Adjustment/Scatter Gather Address 494 | #define DMA_TCD0_CSR *(volatile uint16_t *)0x4000901C // TCD Control and Status 495 | #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled 496 | #define DMA_TCD0_BITER_ELINKNO *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled 497 | 498 | #define DMA_TCD1_SADDR *(volatile const void * volatile *)0x40009020 // TCD Source Address 499 | #define DMA_TCD1_SOFF *(volatile int16_t *)0x40009024 // TCD Signed Source Address Offset 500 | #define DMA_TCD1_ATTR *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes 501 | #define DMA_TCD1_NBYTES_MLNO *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled 502 | #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled 503 | #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled 504 | #define DMA_TCD1_SLAST *(volatile int32_t *)0x4000902C // TCD Last Source Address Adjustment 505 | #define DMA_TCD1_DADDR *(volatile void * volatile *)0x40009030 // TCD Destination Address 506 | #define DMA_TCD1_DOFF *(volatile int16_t *)0x40009034 // TCD Signed Destination Address Offset 507 | #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 508 | #define DMA_TCD1_CITER_ELINKNO *(volatile uint16_t *)0x40009036 // ?? 509 | #define DMA_TCD1_DLASTSGA *(volatile int32_t *)0x40009038 // TCD Last Destination Address Adjustment/Scatter Gather Address 510 | #define DMA_TCD1_CSR *(volatile uint16_t *)0x4000903C // TCD Control and Status 511 | #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled 512 | #define DMA_TCD1_BITER_ELINKNO *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled 513 | 514 | #define DMA_TCD2_SADDR *(volatile const void * volatile *)0x40009040 // TCD Source Address 515 | #define DMA_TCD2_SOFF *(volatile int16_t *)0x40009044 // TCD Signed Source Address Offset 516 | #define DMA_TCD2_ATTR *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes 517 | #define DMA_TCD2_NBYTES_MLNO *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled 518 | #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled 519 | #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled 520 | #define DMA_TCD2_SLAST *(volatile int32_t *)0x4000904C // TCD Last Source Address Adjustment 521 | #define DMA_TCD2_DADDR *(volatile void * volatile *)0x40009050 // TCD Destination Address 522 | #define DMA_TCD2_DOFF *(volatile int16_t *)0x40009054 // TCD Signed Destination Address Offset 523 | #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 524 | #define DMA_TCD2_CITER_ELINKNO *(volatile uint16_t *)0x40009056 // ?? 525 | #define DMA_TCD2_DLASTSGA *(volatile int32_t *)0x40009058 // TCD Last Destination Address Adjustment/Scatter Gather Address 526 | #define DMA_TCD2_CSR *(volatile uint16_t *)0x4000905C // TCD Control and Status 527 | #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled 528 | #define DMA_TCD2_BITER_ELINKNO *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled 529 | 530 | #define DMA_TCD3_SADDR *(volatile const void * volatile *)0x40009060 // TCD Source Address 531 | #define DMA_TCD3_SOFF *(volatile int16_t *)0x40009064 // TCD Signed Source Address Offset 532 | #define DMA_TCD3_ATTR *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes 533 | #define DMA_TCD3_NBYTES_MLNO *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled 534 | #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled 535 | #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled 536 | #define DMA_TCD3_SLAST *(volatile int32_t *)0x4000906C // TCD Last Source Address Adjustment 537 | #define DMA_TCD3_DADDR *(volatile void * volatile *)0x40009070 // TCD Destination Address 538 | #define DMA_TCD3_DOFF *(volatile int16_t *)0x40009074 // TCD Signed Destination Address Offset 539 | #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled 540 | #define DMA_TCD3_CITER_ELINKNO *(volatile uint16_t *)0x40009076 // ?? 541 | #define DMA_TCD3_DLASTSGA *(volatile int32_t *)0x40009078 // TCD Last Destination Address Adjustment/Scatter Gather Address 542 | #define DMA_TCD3_CSR *(volatile uint16_t *)0x4000907C // TCD Control and Status 543 | #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled 544 | #define DMA_TCD3_BITER_ELINKNO *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled 545 | 546 | // CR - DMA Control Register 547 | #define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer 548 | #define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer 549 | #define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping 550 | #define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode 551 | #define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations 552 | #define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error 553 | #define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration 554 | #define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug 555 | 556 | // ERQ - DMA Enable Request Register 557 | #define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0 558 | #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1 559 | #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2 560 | #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3 561 | 562 | // EEI - DMA Enable Error Interrupt Register 563 | #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0 564 | #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1 565 | #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2 566 | #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3 567 | 568 | // CEEI - DMA Clear Enable Error Interrupt Register 569 | #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt 570 | #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts 571 | #define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP 572 | 573 | // SEEI - DMA Set Enable Error Interrupt Register 574 | #define DMA_SEEI_SEEI(n) ((uint8_t)(n & 3)<<0) // Set Enable Error Interrupt 575 | #define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts 576 | #define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP 577 | 578 | // CERQ - DMA Clear Enable Request Register 579 | #define DMA_CERQ_CERQ(n) ((uint8_t)(n & 3)<<0) // Clear Enable Request 580 | #define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests 581 | #define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP 582 | 583 | // SERQ - DMA Set Enable Request Register 584 | #define DMA_SERQ_SERQ(n) ((uint8_t)(n & 3)<<0) // Set Enable Request 585 | #define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests 586 | #define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP 587 | 588 | // CDNE - DMA Clear DONE Status Bit Register 589 | #define DMA_CDNE_CDNE(n) ((uint8_t)(n & 3)<<0) // Clear Done Bit 590 | #define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits 591 | #define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP 592 | 593 | // SSRT - DMA Set START Bit Register 594 | #define DMA_SSRT_SSRT(n) ((uint8_t)(n & 3)<<0) // Set Start Bit 595 | #define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits 596 | #define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP 597 | 598 | // CERR - DMA Clear Error Register 599 | #define DMA_CERR_CERR(n) ((uint8_t)(n & 3)<<0) // Clear Error Indicator 600 | #define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators 601 | #define DMA_CERR_NOP ((uint8_t)1<<7) // NOP 602 | 603 | // CINT - DMA Clear Interrupt Request Register 604 | #define DMA_CINT_CINT(n) ((uint8_t)(n & 3)<<0) // Clear Interrupt Request 605 | #define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests 606 | #define DMA_CINT_NOP ((uint8_t)1<<7) // NOP 607 | 608 | // INT - DMA Interrupt Request Register 609 | #define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0 610 | #define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1 611 | #define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2 612 | #define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3 613 | 614 | // ERR - DMA Error Register 615 | #define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0 616 | #define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1 617 | #define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2 618 | #define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3 619 | 620 | // HRS - DMA Hardware Request Status Register 621 | #define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0 622 | #define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1 623 | #define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2 624 | #define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3 625 | 626 | // DCHPRI - DMA Channel n Priority Register 627 | #define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority 628 | #define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability 629 | #define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption 630 | 631 | // DMA TCD ATTR - Transfer Attributes 632 | #define DMA_ATTR_DSIZE(n) ((uint16_t)(n & 0x07)) // Destination Data Transfer Size 633 | #define DMA_ATTR_DMOD(n) ((uint16_t)(n & 0x1f)<<3) // Destination Address Modulo 634 | #define DMA_ATTR_SSIZE(n) ((uint16_t)(n & 0x07)<<8) // Source Data Transfer Size 635 | #define DMA_ATTR_SMOD(n) ((uint16_t)(n & 0x1f)<<11) // Source Address Modulo 636 | #define DMA_ATTR_SIZE_8BIT 0 637 | #define DMA_ATTR_SIZE_16BIT 1 638 | #define DMA_ATTR_SIZE_32BIT 2 639 | #define DMA_ATTR_SIZE_16BYTE 4 640 | #define DMA_ATTR_SIZE_32BYTE 5 641 | 642 | // DMA TCD Signed Minor Loop Offset 643 | #define DMA_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable 644 | #define DMA_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable 645 | #define DMA_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)(n)) // NBytes transfer count when minor loop disabled 646 | #define DMA_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)(n & 0x1F)) // NBytes transfer count when minor loop enabled 647 | #define DMA_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)(n & 0xFFFFF)<<10) // Offset 648 | 649 | // DMA TCD CSR flags 650 | #define DMA_CSR_START ((uint16_t)0x1) 651 | #define DMA_CSR_INTMAJOR ((uint16_t)0x2) 652 | #define DMA_CSR_INTHALF ((uint16_t)0x4) 653 | #define DMA_CSR_DREQ ((uint16_t)0x8) 654 | #define DMA_CSR_ESG ((uint16_t)0x10) 655 | #define DMA_CSR_MAJORELINK ((uint16_t)0x20) 656 | #define DMA_CSR_ACTIVE ((uint16_t)0x40) 657 | #define DMA_CSR_DONE ((uint16_t)0x80) 658 | #define DMA_CSR_MAJORLINKCH(n) ((uint16_t)(n & 3)<<8) // Link Channel Number 659 | #define DMA_CSR_BWC(n) ((uint16_t)(n & 3)<<14) // Bandwidth Control 660 | #define DMA_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask 661 | #define DMA_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete 662 | #define DMA_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask 663 | #define DMA_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete 664 | 665 | // Chapter 22: External Watchdog Monitor (EWM) 666 | #define EWM_CTRL *(volatile uint8_t *)0x40061000 // Control Register 667 | #define EWM_SERV *(volatile uint8_t *)0x40061001 // Service Register 668 | #define EWM_CMPL *(volatile uint8_t *)0x40061002 // Compare Low Register 669 | #define EWM_CMPH *(volatile uint8_t *)0x40061003 // Compare High Register 670 | 671 | // Chapter 23: Watchdog Timer (WDOG) 672 | #define WDOG_STCTRLH *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High 673 | #define WDOG_STCTRLH_DISTESTWDOG (uint16_t)0x4000 // Allows the WDOG's functional test mode to be disabled permanently. 674 | #define WDOG_STCTRLH_BYTESEL(n) (uint16_t)(((n) & 3) << 12) // selects the byte to be tested when the watchdog is in the byte test mode. 675 | #define WDOG_STCTRLH_TESTSEL (uint16_t)0x0800 676 | #define WDOG_STCTRLH_TESTWDOG (uint16_t)0x0400 677 | #define WDOG_STCTRLH_WAITEN (uint16_t)0x0080 678 | #define WDOG_STCTRLH_STOPEN (uint16_t)0x0040 679 | #define WDOG_STCTRLH_DBGEN (uint16_t)0x0020 680 | #define WDOG_STCTRLH_ALLOWUPDATE (uint16_t)0x0010 681 | #define WDOG_STCTRLH_WINEN (uint16_t)0x0008 682 | #define WDOG_STCTRLH_IRQRSTEN (uint16_t)0x0004 683 | #define WDOG_STCTRLH_CLKSRC (uint16_t)0x0002 684 | #define WDOG_STCTRLH_WDOGEN (uint16_t)0x0001 685 | #define WDOG_STCTRLL *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low 686 | #define WDOG_TOVALH *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High 687 | #define WDOG_TOVALL *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low 688 | #define WDOG_WINH *(volatile uint16_t *)0x40052008 // Watchdog Window Register High 689 | #define WDOG_WINL *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low 690 | #define WDOG_REFRESH *(volatile uint16_t *)0x4005200C // Watchdog Refresh register 691 | #define WDOG_UNLOCK *(volatile uint16_t *)0x4005200E // Watchdog Unlock register 692 | #define WDOG_UNLOCK_SEQ1 (uint16_t)0xC520 693 | #define WDOG_UNLOCK_SEQ2 (uint16_t)0xD928 694 | #define WDOG_TMROUTH *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High 695 | #define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low 696 | #define WDOG_RSTCNT *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register 697 | #define WDOG_PRESC *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register 698 | 699 | // Chapter 24: Multipurpose Clock Generator (MCG) 700 | #define MCG_C1 *(volatile uint8_t *)0x40064000 // MCG Control 1 Register 701 | #define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 702 | #define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK. 703 | #define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL. 704 | #define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL 705 | #define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK 706 | #define MCG_C2 *(volatile uint8_t *)0x40064001 // MCG Control 2 Register 707 | #define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source. 708 | #define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. 709 | #define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock. 710 | #define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation 711 | #define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator 712 | #define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 713 | #define MCG_C3 *(volatile uint8_t *)0x40064002 // MCG Control 3 Register 714 | #define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting 715 | #define MCG_C4 *(volatile uint8_t *)0x40064003 // MCG Control 4 Register 716 | #define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim 717 | #define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting 718 | #define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select 719 | #define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed 720 | #define MCG_C5 *(volatile uint8_t *)0x40064004 // MCG Control 5 Register 721 | #define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider 722 | #define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable 723 | #define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable 724 | #define MCG_C6 *(volatile uint8_t *)0x40064005 // MCG Control 6 Register 725 | #define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider 726 | #define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable 727 | #define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. 728 | #define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable 729 | #define MCG_S *(volatile uint8_t *)0x40064006 // MCG Status Register 730 | #define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status 731 | #define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator 732 | #define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL 733 | #define MCG_S_CLKST_MASK (uint8_t)0x0C 734 | #define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status 735 | #define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status 736 | #define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked 737 | #define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status 738 | #define MCG_SC *(volatile uint8_t *)0x40064008 // MCG Status and Control Register 739 | #define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status 740 | #define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider 741 | #define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable 742 | #define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag 743 | #define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine Select 744 | #define MCG_SC_ATME (uint8_t)0x80 // Automatic Trim Machine Enable 745 | #define MCG_ATCVH *(volatile uint8_t *)0x4006400A // MCG Auto Trim Compare Value High Register 746 | #define MCG_ATCVL *(volatile uint8_t *)0x4006400B // MCG Auto Trim Compare Value Low Register 747 | #define MCG_C7 *(volatile uint8_t *)0x4006400C // MCG Control 7 Register 748 | #define MCG_C8 *(volatile uint8_t *)0x4006400D // MCG Control 8 Register 749 | 750 | // Chapter 25: Oscillator (OSC) 751 | #define OSC0_CR *(volatile uint8_t *)0x40065000 // OSC Control Register 752 | #define OSC_SC16P (uint8_t)0x01 // Oscillator 16 pF Capacitor Load Configure 753 | #define OSC_SC8P (uint8_t)0x02 // Oscillator 8 pF Capacitor Load Configure 754 | #define OSC_SC4P (uint8_t)0x04 // Oscillator 4 pF Capacitor Load Configure 755 | #define OSC_SC2P (uint8_t)0x08 // Oscillator 2 pF Capacitor Load Configure 756 | #define OSC_EREFSTEN (uint8_t)0x20 // External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 757 | #define OSC_ERCLKEN (uint8_t)0x80 // External Reference Enable, Enables external reference clock (OSCERCLK). 758 | 759 | // Chapter 27: Flash Memory Controller (FMC) 760 | #define FMC_PFAPR *(volatile uint32_t *)0x4001F000 // Flash Access Protection 761 | #define FMC_PFB0CR *(volatile uint32_t *)0x4001F004 // Flash Control 762 | #define FMC_TAGVDW0S0 *(volatile uint32_t *)0x4001F100 // Cache Tag Storage 763 | #define FMC_TAGVDW0S1 *(volatile uint32_t *)0x4001F104 // Cache Tag Storage 764 | #define FMC_TAGVDW1S0 *(volatile uint32_t *)0x4001F108 // Cache Tag Storage 765 | #define FMC_TAGVDW1S1 *(volatile uint32_t *)0x4001F10C // Cache Tag Storage 766 | #define FMC_TAGVDW2S0 *(volatile uint32_t *)0x4001F110 // Cache Tag Storage 767 | #define FMC_TAGVDW2S1 *(volatile uint32_t *)0x4001F114 // Cache Tag Storage 768 | #define FMC_TAGVDW3S0 *(volatile uint32_t *)0x4001F118 // Cache Tag Storage 769 | #define FMC_TAGVDW3S1 *(volatile uint32_t *)0x4001F11C // Cache Tag Storage 770 | #define FMC_DATAW0S0 *(volatile uint32_t *)0x4001F200 // Cache Data Storage 771 | #define FMC_DATAW0S1 *(volatile uint32_t *)0x4001F204 // Cache Data Storage 772 | #define FMC_DATAW1S0 *(volatile uint32_t *)0x4001F208 // Cache Data Storage 773 | #define FMC_DATAW1S1 *(volatile uint32_t *)0x4001F20C // Cache Data Storage 774 | #define FMC_DATAW2S0 *(volatile uint32_t *)0x4001F210 // Cache Data Storage 775 | #define FMC_DATAW2S1 *(volatile uint32_t *)0x4001F214 // Cache Data Storage 776 | #define FMC_DATAW3S0 *(volatile uint32_t *)0x4001F218 // Cache Data Storage 777 | #define FMC_DATAW3S1 *(volatile uint32_t *)0x4001F21C // Cache Data Storage 778 | 779 | // Chapter 28: Flash Memory Module (FTFL) 780 | #define FTFL_FSTAT *(volatile uint8_t *)0x40020000 // Flash Status Register 781 | #define FTFL_FSTAT_CCIF (uint8_t)0x80 // Command Complete Interrupt Flag 782 | #define FTFL_FSTAT_RDCOLERR (uint8_t)0x40 // Flash Read Collision Error Flag 783 | #define FTFL_FSTAT_ACCERR (uint8_t)0x20 // Flash Access Error Flag 784 | #define FTFL_FSTAT_FPVIOL (uint8_t)0x10 // Flash Protection Violation Flag 785 | #define FTFL_FSTAT_MGSTAT0 (uint8_t)0x01 // Memory Controller Command Completion Status Flag 786 | #define FTFL_FCNFG *(volatile uint8_t *)0x40020001 // Flash Configuration Register 787 | #define FTFL_FCNFG_CCIE (uint8_t)0x80 // Command Complete Interrupt Enable 788 | #define FTFL_FCNFG_RDCOLLIE (uint8_t)0x40 // Read Collision Error Interrupt Enable 789 | #define FTFL_FCNFG_ERSAREQ (uint8_t)0x20 // Erase All Request 790 | #define FTFL_FCNFG_ERSSUSP (uint8_t)0x10 // Erase Suspend 791 | #define FTFL_FCNFG_PFLSH (uint8_t)0x04 // Flash memory configuration 792 | #define FTFL_FCNFG_RAMRDY (uint8_t)0x02 // RAM Ready 793 | #define FTFL_FCNFG_EEERDY (uint8_t)0x01 // EEPROM Ready 794 | #define FTFL_FSEC *(const uint8_t *)0x40020002 // Flash Security Register 795 | #define FTFL_FOPT *(const uint8_t *)0x40020003 // Flash Option Register 796 | #define FTFL_FCCOB3 *(volatile uint8_t *)0x40020004 // Flash Common Command Object Registers 797 | #define FTFL_FCCOB2 *(volatile uint8_t *)0x40020005 798 | #define FTFL_FCCOB1 *(volatile uint8_t *)0x40020006 799 | #define FTFL_FCCOB0 *(volatile uint8_t *)0x40020007 800 | #define FTFL_FCCOB7 *(volatile uint8_t *)0x40020008 801 | #define FTFL_FCCOB6 *(volatile uint8_t *)0x40020009 802 | #define FTFL_FCCOB5 *(volatile uint8_t *)0x4002000A 803 | #define FTFL_FCCOB4 *(volatile uint8_t *)0x4002000B 804 | #define FTFL_FCCOBB *(volatile uint8_t *)0x4002000C 805 | #define FTFL_FCCOBA *(volatile uint8_t *)0x4002000D 806 | #define FTFL_FCCOB9 *(volatile uint8_t *)0x4002000E 807 | #define FTFL_FCCOB8 *(volatile uint8_t *)0x4002000F 808 | #define FTFL_FPROT3 *(volatile uint8_t *)0x40020010 // Program Flash Protection Registers 809 | #define FTFL_FPROT2 *(volatile uint8_t *)0x40020011 // Program Flash Protection Registers 810 | #define FTFL_FPROT1 *(volatile uint8_t *)0x40020012 // Program Flash Protection Registers 811 | #define FTFL_FPROT0 *(volatile uint8_t *)0x40020013 // Program Flash Protection Registers 812 | #define FTFL_FEPROT *(volatile uint8_t *)0x40020016 // EEPROM Protection Register 813 | #define FTFL_FDPROT *(volatile uint8_t *)0x40020017 // Data Flash Protection Register 814 | 815 | // Chapter 30: Cyclic Redundancy Check (CRC) 816 | #define CRC_CRC *(volatile uint32_t *)0x40032000 // CRC Data register 817 | #define CRC_GPOLY *(volatile uint32_t *)0x40032004 // CRC Polynomial register 818 | #define CRC_CTRL *(volatile uint32_t *)0x40032008 // CRC Control register 819 | 820 | // Chapter 31: Analog-to-Digital Converter (ADC) 821 | #define ADC0_SC1A *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1 822 | #define ADC0_SC1B *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1 823 | #define ADC_SC1_COCO (uint32_t)0x80 // Conversion complete flag 824 | #define ADC_SC1_AIEN (uint32_t)0x40 // Interrupt enable 825 | #define ADC_SC1_DIFF (uint32_t)0x20 // Differential mode enable 826 | #define ADC_SC1_ADCH(n) (uint32_t)((n) & 0x1F) // Input channel select 827 | #define ADC0_CFG1 *(volatile uint32_t *)0x4003B008 // ADC configuration register 1 828 | #define ADC_CFG1_ADLPC (uint32_t)0x80 // Low-power configuration 829 | #define ADC_CFG1_ADIV(n) (uint32_t)(((n) & 3) << 5) // Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8 830 | #define ADC_CFG1_ADLSMP (uint32_t)0x10 // Sample time configuration, 0=Short, 1=Long 831 | #define ADC_CFG1_MODE(n) (uint32_t)(((n) & 3) << 2) // Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit 832 | #define ADC_CFG1_ADICLK(n) (uint32_t)(((n) & 3) << 0) // Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async 833 | #define ADC0_CFG2 *(volatile uint32_t *)0x4003B00C // Configuration register 2 834 | #define ADC_CFG2_MUXSEL (uint32_t)0x10 // 0=a channels, 1=b channels 835 | #define ADC_CFG2_ADACKEN (uint32_t)0x08 // async clock enable 836 | #define ADC_CFG2_ADHSC (uint32_t)0x04 // High speed configuration 837 | #define ADC_CFG2_ADLSTS(n) (uint32_t)(((n) & 3) << 0) // Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles 838 | #define ADC0_RA *(volatile uint32_t *)0x4003B010 // ADC data result register 839 | #define ADC0_RB *(volatile uint32_t *)0x4003B014 // ADC data result register 840 | #define ADC0_CV1 *(volatile uint32_t *)0x4003B018 // Compare value registers 841 | #define ADC0_CV2 *(volatile uint32_t *)0x4003B01C // Compare value registers 842 | #define ADC0_SC2 *(volatile uint32_t *)0x4003B020 // Status and control register 2 843 | #define ADC_SC2_ADACT (uint32_t)0x80 // Conversion active 844 | #define ADC_SC2_ADTRG (uint32_t)0x40 // Conversion trigger select, 0=software, 1=hardware 845 | #define ADC_SC2_ACFE (uint32_t)0x20 // Compare function enable 846 | #define ADC_SC2_ACFGT (uint32_t)0x10 // Compare function greater than enable 847 | #define ADC_SC2_ACREN (uint32_t)0x08 // Compare function range enable 848 | #define ADC_SC2_DMAEN (uint32_t)0x04 // DMA enable 849 | #define ADC_SC2_REFSEL(n) (uint32_t)(((n) & 3) << 0) // Voltage reference, 0=vcc/external, 1=1.2 volts 850 | #define ADC0_SC3 *(volatile uint32_t *)0x4003B024 // Status and control register 3 851 | #define ADC_SC3_CAL (uint32_t)0x80 // Calibration, 1=begin, stays set while cal in progress 852 | #define ADC_SC3_CALF (uint32_t)0x40 // Calibration failed flag 853 | #define ADC_SC3_ADCO (uint32_t)0x08 // Continuous conversion enable 854 | #define ADC_SC3_AVGE (uint32_t)0x04 // Hardware average enable 855 | #define ADC_SC3_AVGS(n) (uint32_t)(((n) & 3) << 0) // avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples 856 | #define ADC0_OFS *(volatile uint32_t *)0x4003B028 // ADC offset correction register 857 | #define ADC0_PG *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register 858 | #define ADC0_MG *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register 859 | #define ADC0_CLPD *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register 860 | #define ADC0_CLPS *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register 861 | #define ADC0_CLP4 *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register 862 | #define ADC0_CLP3 *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register 863 | #define ADC0_CLP2 *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register 864 | #define ADC0_CLP1 *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register 865 | #define ADC0_CLP0 *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register 866 | #define ADC0_CLMD *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register 867 | #define ADC0_CLMS *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register 868 | #define ADC0_CLM4 *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register 869 | #define ADC0_CLM3 *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register 870 | #define ADC0_CLM2 *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register 871 | #define ADC0_CLM1 *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register 872 | #define ADC0_CLM0 *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register 873 | //#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator 874 | //#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 875 | 876 | // Chapter 32: Comparator (CMP) 877 | #define CMP0_CR0 *(volatile uint8_t *)0x40073000 // CMP Control Register 0 878 | #define CMP0_CR1 *(volatile uint8_t *)0x40073001 // CMP Control Register 1 879 | #define CMP0_FPR *(volatile uint8_t *)0x40073002 // CMP Filter Period Register 880 | #define CMP0_SCR *(volatile uint8_t *)0x40073003 // CMP Status and Control Register 881 | #define CMP0_DACCR *(volatile uint8_t *)0x40073004 // DAC Control Register 882 | #define CMP0_MUXCR *(volatile uint8_t *)0x40073005 // MUX Control Register 883 | #define CMP1_CR0 *(volatile uint8_t *)0x40073008 // CMP Control Register 0 884 | #define CMP1_CR1 *(volatile uint8_t *)0x40073009 // CMP Control Register 1 885 | #define CMP1_FPR *(volatile uint8_t *)0x4007300A // CMP Filter Period Register 886 | #define CMP1_SCR *(volatile uint8_t *)0x4007300B // CMP Status and Control Register 887 | #define CMP1_DACCR *(volatile uint8_t *)0x4007300C // DAC Control Register 888 | #define CMP1_MUXCR *(volatile uint8_t *)0x4007300D // MUX Control Register 889 | 890 | // Chapter 33: Voltage Reference (VREFV1) 891 | #define VREF_TRM *(volatile uint8_t *)0x40074000 // VREF Trim Register 892 | #define VREF_SC *(volatile uint8_t *)0x40074001 // VREF Status and Control Register 893 | 894 | // Chapter 34: Programmable Delay Block (PDB) 895 | #define PDB0_SC *(volatile uint32_t *)0x40036000 // Status and Control Register 896 | #define PDB_SC_LDMOD(n) (((n) & 3) << 18) // Load Mode Select 897 | #define PDB_SC_PDBEIE 0x00020000 // Sequence Error Interrupt Enable 898 | #define PDB_SC_SWTRIG 0x00010000 // Software Trigger 899 | #define PDB_SC_DMAEN 0x00008000 // DMA Enable 900 | #define PDB_SC_PRESCALER(n) (((n) & 7) << 12) // Prescaler Divider Select 901 | #define PDB_SC_TRGSEL(n) (((n) & 15) << 8) // Trigger Input Source Select 902 | #define PDB_SC_PDBEN 0x00000080 // PDB Enable 903 | #define PDB_SC_PDBIF 0x00000040 // PDB Interrupt Flag 904 | #define PDB_SC_PDBIE 0x00000020 // PDB Interrupt Enable. 905 | #define PDB_SC_MULT(n) (((n) & 3) << 2) // Multiplication Factor 906 | #define PDB_SC_CONT 0x00000002 // Continuous Mode Enable 907 | #define PDB_SC_LDOK 0x00000001 // Load OK 908 | #define PDB0_MOD *(volatile uint32_t *)0x40036004 // Modulus Register 909 | #define PDB0_CNT *(volatile uint32_t *)0x40036008 // Counter Register 910 | #define PDB0_IDLY *(volatile uint32_t *)0x4003600C // Interrupt Delay Register 911 | #define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel n Control Register 1 912 | #define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel n Status Register 913 | #define PDB0_CH0DLY0 *(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register 914 | #define PDB0_CH0DLY1 *(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register 915 | #define PDB0_POEN *(volatile uint32_t *)0x40036190 // Pulse-Out n Enable Register 916 | #define PDB0_PO0DLY *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register 917 | #define PDB0_PO1DLY *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register 918 | 919 | // Chapter 35: FlexTimer Module (FTM) 920 | #define FTM0_SC *(volatile uint32_t *)0x40038000 // Status And Control 921 | #define FTM_SC_TOF 0x80 // Timer Overflow Flag 922 | #define FTM_SC_TOIE 0x40 // Timer Overflow Interrupt Enable 923 | #define FTM_SC_CPWMS 0x20 // Center-Aligned PWM Select 924 | #define FTM_SC_CLKS(n) (((n) & 3) << 3) // Clock Source Selection 925 | #define FTM_SC_PS(n) (((n) & 7) << 0) // Prescale Factor Selection 926 | #define FTM0_CNT *(volatile uint32_t *)0x40038004 // Counter 927 | #define FTM0_MOD *(volatile uint32_t *)0x40038008 // Modulo 928 | #define FTM0_C0SC *(volatile uint32_t *)0x4003800C // Channel 0 Status And Control 929 | #define FTM0_C0V *(volatile uint32_t *)0x40038010 // Channel 0 Value 930 | #define FTM0_C1SC *(volatile uint32_t *)0x40038014 // Channel 1 Status And Control 931 | #define FTM0_C1V *(volatile uint32_t *)0x40038018 // Channel 1 Value 932 | #define FTM0_C2SC *(volatile uint32_t *)0x4003801C // Channel 2 Status And Control 933 | #define FTM0_C2V *(volatile uint32_t *)0x40038020 // Channel 2 Value 934 | #define FTM0_C3SC *(volatile uint32_t *)0x40038024 // Channel 3 Status And Control 935 | #define FTM0_C3V *(volatile uint32_t *)0x40038028 // Channel 3 Value 936 | #define FTM0_C4SC *(volatile uint32_t *)0x4003802C // Channel 4 Status And Control 937 | #define FTM0_C4V *(volatile uint32_t *)0x40038030 // Channel 4 Value 938 | #define FTM0_C5SC *(volatile uint32_t *)0x40038034 // Channel 5 Status And Control 939 | #define FTM0_C5V *(volatile uint32_t *)0x40038038 // Channel 5 Value 940 | #define FTM0_C6SC *(volatile uint32_t *)0x4003803C // Channel 6 Status And Control 941 | #define FTM0_C6V *(volatile uint32_t *)0x40038040 // Channel 6 Value 942 | #define FTM0_C7SC *(volatile uint32_t *)0x40038044 // Channel 7 Status And Control 943 | #define FTM0_C7V *(volatile uint32_t *)0x40038048 // Channel 7 Value 944 | #define FTM0_CNTIN *(volatile uint32_t *)0x4003804C // Counter Initial Value 945 | #define FTM0_STATUS *(volatile uint32_t *)0x40038050 // Capture And Compare Status 946 | #define FTM0_MODE *(volatile uint32_t *)0x40038054 // Features Mode Selection 947 | #define FTM_MODE_FAULTIE 0x80 // Fault Interrupt Enable 948 | #define FTM_MODE_FAULTM(n) (((n) & 3) << 5) // Fault Control Mode 949 | #define FTM_MODE_CAPTEST 0x10 // Capture Test Mode Enable 950 | #define FTM_MODE_PWMSYNC 0x08 // PWM Synchronization Mode 951 | #define FTM_MODE_WPDIS 0x04 // Write Protection Disable 952 | #define FTM_MODE_INIT 0x02 // Initialize The Channels Output 953 | #define FTM_MODE_FTMEN 0x01 // FTM Enable 954 | #define FTM0_SYNC *(volatile uint32_t *)0x40038058 // Synchronization 955 | #define FTM_SYNC_SWSYNC 0x80 // 956 | #define FTM_SYNC_TRIG2 0x40 // 957 | #define FTM_SYNC_TRIG1 0x20 // 958 | #define FTM_SYNC_TRIG0 0x10 // 959 | #define FTM_SYNC_SYNCHOM 0x08 // 960 | #define FTM_SYNC_REINIT 0x04 // 961 | #define FTM_SYNC_CNTMAX 0x02 // 962 | #define FTM_SYNC_CNTMIN 0x01 // 963 | #define FTM0_OUTINIT *(volatile uint32_t *)0x4003805C // Initial State For Channels Output 964 | #define FTM0_OUTMASK *(volatile uint32_t *)0x40038060 // Output Mask 965 | #define FTM0_COMBINE *(volatile uint32_t *)0x40038064 // Function For Linked Channels 966 | #define FTM0_DEADTIME *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control 967 | #define FTM0_EXTTRIG *(volatile uint32_t *)0x4003806C // FTM External Trigger 968 | #define FTM0_POL *(volatile uint32_t *)0x40038070 // Channels Polarity 969 | #define FTM0_FMS *(volatile uint32_t *)0x40038074 // Fault Mode Status 970 | #define FTM0_FILTER *(volatile uint32_t *)0x40038078 // Input Capture Filter Control 971 | #define FTM0_FLTCTRL *(volatile uint32_t *)0x4003807C // Fault Control 972 | #define FTM0_QDCTRL *(volatile uint32_t *)0x40038080 // Quadrature Decoder Control And Status 973 | #define FTM0_CONF *(volatile uint32_t *)0x40038084 // Configuration 974 | #define FTM0_FLTPOL *(volatile uint32_t *)0x40038088 // FTM Fault Input Polarity 975 | #define FTM0_SYNCONF *(volatile uint32_t *)0x4003808C // Synchronization Configuration 976 | #define FTM0_INVCTRL *(volatile uint32_t *)0x40038090 // FTM Inverting Control 977 | #define FTM0_SWOCTRL *(volatile uint32_t *)0x40038094 // FTM Software Output Control 978 | #define FTM0_PWMLOAD *(volatile uint32_t *)0x40038098 // FTM PWM Load 979 | #define FTM1_SC *(volatile uint32_t *)0x40039000 // Status And Control 980 | #define FTM1_CNT *(volatile uint32_t *)0x40039004 // Counter 981 | #define FTM1_MOD *(volatile uint32_t *)0x40039008 // Modulo 982 | #define FTM1_C0SC *(volatile uint32_t *)0x4003900C // Channel 0 Status And Control 983 | #define FTM1_C0V *(volatile uint32_t *)0x40039010 // Channel 0 Value 984 | #define FTM1_C1SC *(volatile uint32_t *)0x40039014 // Channel 1 Status And Control 985 | #define FTM1_C1V *(volatile uint32_t *)0x40039018 // Channel 1 Value 986 | #define FTM1_CNTIN *(volatile uint32_t *)0x4003904C // Counter Initial Value 987 | #define FTM1_STATUS *(volatile uint32_t *)0x40039050 // Capture And Compare Status 988 | #define FTM1_MODE *(volatile uint32_t *)0x40039054 // Features Mode Selection 989 | #define FTM1_SYNC *(volatile uint32_t *)0x40039058 // Synchronization 990 | #define FTM1_OUTINIT *(volatile uint32_t *)0x4003905C // Initial State For Channels Output 991 | #define FTM1_OUTMASK *(volatile uint32_t *)0x40039060 // Output Mask 992 | #define FTM1_COMBINE *(volatile uint32_t *)0x40039064 // Function For Linked Channels 993 | #define FTM1_DEADTIME *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control 994 | #define FTM1_EXTTRIG *(volatile uint32_t *)0x4003906C // FTM External Trigger 995 | #define FTM1_POL *(volatile uint32_t *)0x40039070 // Channels Polarity 996 | #define FTM1_FMS *(volatile uint32_t *)0x40039074 // Fault Mode Status 997 | #define FTM1_FILTER *(volatile uint32_t *)0x40039078 // Input Capture Filter Control 998 | #define FTM1_FLTCTRL *(volatile uint32_t *)0x4003907C // Fault Control 999 | #define FTM1_QDCTRL *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status 1000 | #define FTM1_CONF *(volatile uint32_t *)0x40039084 // Configuration 1001 | #define FTM1_FLTPOL *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity 1002 | #define FTM1_SYNCONF *(volatile uint32_t *)0x4003908C // Synchronization Configuration 1003 | #define FTM1_INVCTRL *(volatile uint32_t *)0x40039090 // FTM Inverting Control 1004 | #define FTM1_SWOCTRL *(volatile uint32_t *)0x40039094 // FTM Software Output Control 1005 | #define FTM1_PWMLOAD *(volatile uint32_t *)0x40039098 // FTM PWM Load 1006 | 1007 | // Chapter 36: Periodic Interrupt Timer (PIT) 1008 | #define PIT_MCR *(volatile uint32_t *)0x40037000 // PIT Module Control Register 1009 | #define PIT_LDVAL0 *(volatile uint32_t *)0x40037100 // Timer Load Value Register 1010 | #define PIT_CVAL0 *(volatile uint32_t *)0x40037104 // Current Timer Value Register 1011 | #define PIT_TCTRL0 *(volatile uint32_t *)0x40037108 // Timer Control Register 1012 | #define PIT_TFLG0 *(volatile uint32_t *)0x4003710C // Timer Flag Register 1013 | #define PIT_LDVAL1 *(volatile uint32_t *)0x40037110 // Timer Load Value Register 1014 | #define PIT_CVAL1 *(volatile uint32_t *)0x40037114 // Current Timer Value Register 1015 | #define PIT_TCTRL1 *(volatile uint32_t *)0x40037118 // Timer Control Register 1016 | #define PIT_TFLG1 *(volatile uint32_t *)0x4003711C // Timer Flag Register 1017 | #define PIT_LDVAL2 *(volatile uint32_t *)0x40037120 // Timer Load Value Register 1018 | #define PIT_CVAL2 *(volatile uint32_t *)0x40037124 // Current Timer Value Register 1019 | #define PIT_TCTRL2 *(volatile uint32_t *)0x40037128 // Timer Control Register 1020 | #define PIT_TFLG2 *(volatile uint32_t *)0x4003712C // Timer Flag Register 1021 | #define PIT_LDVAL3 *(volatile uint32_t *)0x40037130 // Timer Load Value Register 1022 | #define PIT_CVAL3 *(volatile uint32_t *)0x40037134 // Current Timer Value Register 1023 | #define PIT_TCTRL3 *(volatile uint32_t *)0x40037138 // Timer Control Register 1024 | #define PIT_TFLG3 *(volatile uint32_t *)0x4003713C // Timer Flag Register 1025 | 1026 | // Chapter 37: Low-Power Timer (LPTMR) 1027 | #define LPTMR0_CSR *(volatile uint32_t *)0x40040000 // Low Power Timer Control Status Register 1028 | #define LPTMR0_PSR *(volatile uint32_t *)0x40040004 // Low Power Timer Prescale Register 1029 | #define LPTMR0_CMR *(volatile uint32_t *)0x40040008 // Low Power Timer Compare Register 1030 | #define LPTMR0_CNR *(volatile uint32_t *)0x4004000C // Low Power Timer Counter Register 1031 | 1032 | // Chapter 38: Carrier Modulator Transmitter (CMT) 1033 | #define CMT_CGH1 *(volatile uint8_t *)0x40062000 // CMT Carrier Generator High Data Register 1 1034 | #define CMT_CGL1 *(volatile uint8_t *)0x40062001 // CMT Carrier Generator Low Data Register 1 1035 | #define CMT_CGH2 *(volatile uint8_t *)0x40062002 // CMT Carrier Generator High Data Register 2 1036 | #define CMT_CGL2 *(volatile uint8_t *)0x40062003 // CMT Carrier Generator Low Data Register 2 1037 | #define CMT_OC *(volatile uint8_t *)0x40062004 // CMT Output Control Register 1038 | #define CMT_MSC *(volatile uint8_t *)0x40062005 // CMT Modulator Status and Control Register 1039 | #define CMT_CMD1 *(volatile uint8_t *)0x40062006 // CMT Modulator Data Register Mark High 1040 | #define CMT_CMD2 *(volatile uint8_t *)0x40062007 // CMT Modulator Data Register Mark Low 1041 | #define CMT_CMD3 *(volatile uint8_t *)0x40062008 // CMT Modulator Data Register Space High 1042 | #define CMT_CMD4 *(volatile uint8_t *)0x40062009 // CMT Modulator Data Register Space Low 1043 | #define CMT_PPS *(volatile uint8_t *)0x4006200A // CMT Primary Prescaler Register 1044 | #define CMT_DMA *(volatile uint8_t *)0x4006200B // CMT Direct Memory Access Register 1045 | 1046 | // Chapter 39: Real Time Clock (RTC) 1047 | #define RTC_TSR *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register 1048 | #define RTC_TPR *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register 1049 | #define RTC_TAR *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register 1050 | #define RTC_TCR *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register 1051 | #define RTC_TCR_CIC(n) (((n) & 255) << 24) // Compensation Interval Counter 1052 | #define RTC_TCR_TCV(n) (((n) & 255) << 16) // Time Compensation Value 1053 | #define RTC_TCR_CIR(n) (((n) & 255) << 8) // Compensation Interval Register 1054 | #define RTC_TCR_TCR(n) (((n) & 255) << 0) // Time Compensation Register 1055 | #define RTC_CR *(volatile uint32_t *)0x4003D010 // RTC Control Register 1056 | #define RTC_CR_SC2P (uint32_t)0x00002000 // 1057 | #define RTC_CR_SC4P (uint32_t)0x00001000 // 1058 | #define RTC_CR_SC8P (uint32_t)0x00000800 // 1059 | #define RTC_CR_SC16P (uint32_t)0x00000400 // 1060 | #define RTC_CR_CLKO (uint32_t)0x00000200 // 1061 | #define RTC_CR_OSCE (uint32_t)0x00000100 // 1062 | #define RTC_CR_UM (uint32_t)0x00000008 // 1063 | #define RTC_CR_SUP (uint32_t)0x00000004 // 1064 | #define RTC_CR_WPE (uint32_t)0x00000002 // 1065 | #define RTC_CR_SWR (uint32_t)0x00000001 // 1066 | #define RTC_SR *(volatile uint32_t *)0x4003D014 // RTC Status Register 1067 | #define RTC_SR_TCE (uint32_t)0x00000010 // 1068 | #define RTC_SR_TAF (uint32_t)0x00000004 // 1069 | #define RTC_SR_TOF (uint32_t)0x00000002 // 1070 | #define RTC_SR_TIF (uint32_t)0x00000001 // 1071 | #define RTC_LR *(volatile uint32_t *)0x4003D018 // RTC Lock Register 1072 | #define RTC_IER *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register 1073 | #define RTC_WAR *(volatile uint32_t *)0x4003D800 // RTC Write Access Register 1074 | #define RTC_RAR *(volatile uint32_t *)0x4003D804 // RTC Read Access Register 1075 | 1076 | // Chapter 40: Universal Serial Bus OTG Controller (USBOTG) 1077 | #define USB0_PERID *(const uint8_t *)0x40072000 // Peripheral ID register 1078 | #define USB0_IDCOMP *(const uint8_t *)0x40072004 // Peripheral ID Complement register 1079 | #define USB0_REV *(const uint8_t *)0x40072008 // Peripheral Revision register 1080 | #define USB0_ADDINFO *(volatile uint8_t *)0x4007200C // Peripheral Additional Info register 1081 | #define USB0_OTGISTAT *(volatile uint8_t *)0x40072010 // OTG Interrupt Status register 1082 | #define USB_OTGISTAT_IDCHG (uint8_t)0x80 // 1083 | #define USB_OTGISTAT_ONEMSEC (uint8_t)0x40 // 1084 | #define USB_OTGISTAT_LINE_STATE_CHG (uint8_t)0x20 // 1085 | #define USB_OTGISTAT_SESSVLDCHG (uint8_t)0x08 // 1086 | #define USB_OTGISTAT_B_SESS_CHG (uint8_t)0x04 // 1087 | #define USB_OTGISTAT_AVBUSCHG (uint8_t)0x01 // 1088 | #define USB0_OTGICR *(volatile uint8_t *)0x40072014 // OTG Interrupt Control Register 1089 | #define USB_OTGICR_IDEN (uint8_t)0x80 // 1090 | #define USB_OTGICR_ONEMSECEN (uint8_t)0x40 // 1091 | #define USB_OTGICR_LINESTATEEN (uint8_t)0x20 // 1092 | #define USB_OTGICR_SESSVLDEN (uint8_t)0x08 // 1093 | #define USB_OTGICR_BSESSEN (uint8_t)0x04 // 1094 | #define USB_OTGICR_AVBUSEN (uint8_t)0x01 // 1095 | #define USB0_OTGSTAT *(volatile uint8_t *)0x40072018 // OTG Status register 1096 | #define USB_OTGSTAT_ID (uint8_t)0x80 // 1097 | #define USB_OTGSTAT_ONEMSECEN (uint8_t)0x40 // 1098 | #define USB_OTGSTAT_LINESTATESTABLE (uint8_t)0x20 // 1099 | #define USB_OTGSTAT_SESS_VLD (uint8_t)0x08 // 1100 | #define USB_OTGSTAT_BSESSEND (uint8_t)0x04 // 1101 | #define USB_OTGSTAT_AVBUSVLD (uint8_t)0x01 // 1102 | #define USB0_OTGCTL *(volatile uint8_t *)0x4007201C // OTG Control Register 1103 | #define USB_OTGCTL_DPHIGH (uint8_t)0x80 // 1104 | #define USB_OTGCTL_DPLOW (uint8_t)0x20 // 1105 | #define USB_OTGCTL_DMLOW (uint8_t)0x10 // 1106 | #define USB_OTGCTL_OTGEN (uint8_t)0x04 // 1107 | #define USB0_ISTAT *(volatile uint8_t *)0x40072080 // Interrupt Status Register 1108 | #define USB_ISTAT_STALL (uint8_t)0x80 // 1109 | #define USB_ISTAT_ATTACH (uint8_t)0x40 // 1110 | #define USB_ISTAT_RESUME (uint8_t)0x20 // 1111 | #define USB_ISTAT_SLEEP (uint8_t)0x10 // 1112 | #define USB_ISTAT_TOKDNE (uint8_t)0x08 // 1113 | #define USB_ISTAT_SOFTOK (uint8_t)0x04 // 1114 | #define USB_ISTAT_ERROR (uint8_t)0x02 // 1115 | #define USB_ISTAT_USBRST (uint8_t)0x01 // 1116 | #define USB0_INTEN *(volatile uint8_t *)0x40072084 // Interrupt Enable Register 1117 | #define USB_INTEN_STALLEN (uint8_t)0x80 // 1118 | #define USB_INTEN_ATTACHEN (uint8_t)0x40 // 1119 | #define USB_INTEN_RESUMEEN (uint8_t)0x20 // 1120 | #define USB_INTEN_SLEEPEN (uint8_t)0x10 // 1121 | #define USB_INTEN_TOKDNEEN (uint8_t)0x08 // 1122 | #define USB_INTEN_SOFTOKEN (uint8_t)0x04 // 1123 | #define USB_INTEN_ERROREN (uint8_t)0x02 // 1124 | #define USB_INTEN_USBRSTEN (uint8_t)0x01 // 1125 | #define USB0_ERRSTAT *(volatile uint8_t *)0x40072088 // Error Interrupt Status Register 1126 | #define USB_ERRSTAT_BTSERR (uint8_t)0x80 // 1127 | #define USB_ERRSTAT_DMAERR (uint8_t)0x20 // 1128 | #define USB_ERRSTAT_BTOERR (uint8_t)0x10 // 1129 | #define USB_ERRSTAT_DFN8 (uint8_t)0x08 // 1130 | #define USB_ERRSTAT_CRC16 (uint8_t)0x04 // 1131 | #define USB_ERRSTAT_CRC5EOF (uint8_t)0x02 // 1132 | #define USB_ERRSTAT_PIDERR (uint8_t)0x01 // 1133 | #define USB0_ERREN *(volatile uint8_t *)0x4007208C // Error Interrupt Enable Register 1134 | #define USB_ERREN_BTSERREN (uint8_t)0x80 // 1135 | #define USB_ERREN_DMAERREN (uint8_t)0x20 // 1136 | #define USB_ERREN_BTOERREN (uint8_t)0x10 // 1137 | #define USB_ERREN_DFN8EN (uint8_t)0x08 // 1138 | #define USB_ERREN_CRC16EN (uint8_t)0x04 // 1139 | #define USB_ERREN_CRC5EOFEN (uint8_t)0x02 // 1140 | #define USB_ERREN_PIDERREN (uint8_t)0x01 // 1141 | #define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register 1142 | #define USB_STAT_TX (uint8_t)0x08 // 1143 | #define USB_STAT_ODD (uint8_t)0x04 // 1144 | #define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) // 1145 | #define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register 1146 | #define USB_CTL_JSTATE (uint8_t)0x80 // 1147 | #define USB_CTL_SE0 (uint8_t)0x40 // 1148 | #define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 // 1149 | #define USB_CTL_RESET (uint8_t)0x10 // 1150 | #define USB_CTL_HOSTMODEEN (uint8_t)0x08 // 1151 | #define USB_CTL_RESUME (uint8_t)0x04 // 1152 | #define USB_CTL_ODDRST (uint8_t)0x02 // 1153 | #define USB_CTL_USBENSOFEN (uint8_t)0x01 // 1154 | #define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register 1155 | #define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1 1156 | #define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low 1157 | #define USB0_FRMNUMH *(volatile uint8_t *)0x400720A4 // Frame Number Register High 1158 | #define USB0_TOKEN *(volatile uint8_t *)0x400720A8 // Token Register 1159 | #define USB0_SOFTHLD *(volatile uint8_t *)0x400720AC // SOF Threshold Register 1160 | #define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2 1161 | #define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3 1162 | #define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register 1163 | #define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed 1164 | #define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry 1165 | #define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync 1166 | #define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers. 1167 | #define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers. 1168 | #define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint 1169 | #define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous 1170 | #define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register 1171 | #define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register 1172 | #define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register 1173 | #define USB0_ENDPT4 *(volatile uint8_t *)0x400720D0 // Endpoint Control Register 1174 | #define USB0_ENDPT5 *(volatile uint8_t *)0x400720D4 // Endpoint Control Register 1175 | #define USB0_ENDPT6 *(volatile uint8_t *)0x400720D8 // Endpoint Control Register 1176 | #define USB0_ENDPT7 *(volatile uint8_t *)0x400720DC // Endpoint Control Register 1177 | #define USB0_ENDPT8 *(volatile uint8_t *)0x400720E0 // Endpoint Control Register 1178 | #define USB0_ENDPT9 *(volatile uint8_t *)0x400720E4 // Endpoint Control Register 1179 | #define USB0_ENDPT10 *(volatile uint8_t *)0x400720E8 // Endpoint Control Register 1180 | #define USB0_ENDPT11 *(volatile uint8_t *)0x400720EC // Endpoint Control Register 1181 | #define USB0_ENDPT12 *(volatile uint8_t *)0x400720F0 // Endpoint Control Register 1182 | #define USB0_ENDPT13 *(volatile uint8_t *)0x400720F4 // Endpoint Control Register 1183 | #define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register 1184 | #define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register 1185 | #define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register 1186 | #define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state. 1187 | #define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver. 1188 | #define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register 1189 | #define USB_OBSERVE_DPPU (uint8_t)0x80 // 1190 | #define USB_OBSERVE_DPPD (uint8_t)0x40 // 1191 | #define USB_OBSERVE_DMPD (uint8_t)0x10 // 1192 | #define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register 1193 | #define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode. 1194 | #define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0 1195 | #define USB_USBTRC_USBRESET (uint8_t)0x80 // 1196 | #define USB_USBTRC_USBRESMEN (uint8_t)0x20 // 1197 | #define USB_USBTRC_SYNC_DET (uint8_t)0x02 // 1198 | #define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 // 1199 | #define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register 1200 | 1201 | // Chapter 41: USB Device Charger Detection Module (USBDCD) 1202 | #define USBDCD_CONTROL *(volatile uint32_t *)0x40035000 // Control register 1203 | #define USBDCD_CLOCK *(volatile uint32_t *)0x40035004 // Clock register 1204 | #define USBDCD_STATUS *(volatile uint32_t *)0x40035008 // Status register 1205 | #define USBDCD_TIMER0 *(volatile uint32_t *)0x40035010 // TIMER0 register 1206 | #define USBDCD_TIMER1 *(volatile uint32_t *)0x40035014 // TIMER1 register 1207 | #define USBDCD_TIMER2 *(volatile uint32_t *)0x40035018 // TIMER2 register 1208 | 1209 | // Chapter 43: SPI (DSPI) 1210 | #define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register 1211 | #define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select 1212 | #define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 // 1213 | #define SPI_MCR_DCONF(n) (((n) & 3) << 28) // 1214 | #define SPI_MCR_FRZ (uint32_t)0x08000000 // 1215 | #define SPI_MCR_MTFE (uint32_t)0x04000000 // 1216 | #define SPI_MCR_ROOE (uint32_t)0x01000000 // 1217 | #define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) // 1218 | #define SPI_MCR_DOZE (uint32_t)0x00008000 // 1219 | #define SPI_MCR_MDIS (uint32_t)0x00004000 // 1220 | #define SPI_MCR_DIS_TXF (uint32_t)0x00002000 // 1221 | #define SPI_MCR_DIS_RXF (uint32_t)0x00001000 // 1222 | #define SPI_MCR_CLR_TXF (uint32_t)0x00000800 // 1223 | #define SPI_MCR_CLR_RXF (uint32_t)0x00000400 // 1224 | #define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) // 1225 | #define SPI_MCR_HALT (uint32_t)0x00000001 // 1226 | #define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register 1227 | #define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode 1228 | #define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate 1229 | #define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) 1230 | #define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity 1231 | #define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase 1232 | #define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First 1233 | #define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler 1234 | #define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler 1235 | #define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler 1236 | #define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler 1237 | #define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler 1238 | #define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler 1239 | #define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler 1240 | #define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler 1241 | #define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode 1242 | #define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode 1243 | #define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register 1244 | #define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag 1245 | #define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status 1246 | #define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag 1247 | #define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag 1248 | #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag 1249 | #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag 1250 | #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag 1251 | #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register 1252 | #define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode 1253 | #define SPI_PUSHR_CONT (uint32_t)0x80000000 // 1254 | #define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) // 1255 | #define SPI_PUSHR_EOQ (uint32_t)0x08000000 // 1256 | #define SPI_PUSHR_CTCNT (uint32_t)0x04000000 // 1257 | #define SPI_PUSHR_PCS(n) (((n) & 31) << 16) // 1258 | #define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode 1259 | #define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register 1260 | #define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers 1261 | #define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers 1262 | #define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers 1263 | #define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers 1264 | #define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers 1265 | #define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers 1266 | #define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers 1267 | #define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers 1268 | 1269 | // Chapter 44: Inter-Integrated Circuit (I2C) 1270 | #define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1 1271 | #define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register 1272 | #define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1 1273 | #define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable 1274 | #define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable 1275 | #define I2C_C1_MST (uint8_t)0x20 // Master Mode Select 1276 | #define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select 1277 | #define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable 1278 | #define I2C_C1_RSTA (uint8_t)0x04 // Repeat START 1279 | #define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable 1280 | #define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable 1281 | #define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register 1282 | #define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag 1283 | #define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave 1284 | #define I2C_S_BUSY (uint8_t)0x20 // Bus Busy 1285 | #define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost 1286 | #define I2C_S_RAM (uint8_t)0x08 // Range Address Match 1287 | #define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write 1288 | #define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag 1289 | #define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge 1290 | #define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register 1291 | #define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2 1292 | #define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable 1293 | #define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension 1294 | #define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select 1295 | #define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control 1296 | #define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable 1297 | #define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits 1298 | #define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register 1299 | #define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register 1300 | #define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register 1301 | #define I2C0_A2 *(volatile uint8_t *)0x40066009 // I2C Address Register 2 1302 | #define I2C0_SLTH *(volatile uint8_t *)0x4006600A // I2C SCL Low Timeout Register High 1303 | #define I2C0_SLTL *(volatile uint8_t *)0x4006600B // I2C SCL Low Timeout Register Low 1304 | 1305 | // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART) 1306 | #define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High 1307 | #define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low 1308 | #define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1 1309 | #define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input 1310 | #define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode 1311 | #define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input 1312 | #define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select 1313 | #define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART 1314 | #define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select 1315 | #define UART_C1_PE (uint8_t)0x02 // Parity Enable 1316 | #define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd 1317 | #define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2 1318 | #define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable. 1319 | #define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable 1320 | #define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable 1321 | #define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable 1322 | #define UART_C2_TE (uint8_t)0x08 // Transmitter Enable 1323 | #define UART_C2_RE (uint8_t)0x04 // Receiver Enable 1324 | #define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control 1325 | #define UART_C2_SBK (uint8_t)0x01 // Send Break 1326 | #define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1 1327 | #define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag 1328 | #define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag 1329 | #define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag 1330 | #define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag 1331 | #define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag 1332 | #define UART_S1_NF (uint8_t)0x04 // Noise Flag 1333 | #define UART_S1_FE (uint8_t)0x02 // Framing Error Flag 1334 | #define UART_S1_PF (uint8_t)0x01 // Parity Error Flag 1335 | #define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2 1336 | #define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3 1337 | #define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register 1338 | #define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1 1339 | #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2 1340 | #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4 1341 | #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5 1342 | #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register 1343 | #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register 1344 | #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register 1345 | #define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters 1346 | #define UART_PFIFO_TXFE (uint8_t)0x80 1347 | #define UART_PFIFO_RXFE (uint8_t)0x08 1348 | #define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register 1349 | #define UART_CFIFO_TXFLUSH (uint8_t)0x80 // 1350 | #define UART_CFIFO_RXFLUSH (uint8_t)0x40 // 1351 | #define UART_CFIFO_RXOFE (uint8_t)0x04 // 1352 | #define UART_CFIFO_TXOFE (uint8_t)0x02 // 1353 | #define UART_CFIFO_RXUFE (uint8_t)0x01 // 1354 | #define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register 1355 | #define UART_SFIFO_TXEMPT (uint8_t)0x80 1356 | #define UART_SFIFO_RXEMPT (uint8_t)0x40 1357 | #define UART_SFIFO_RXOF (uint8_t)0x04 1358 | #define UART_SFIFO_TXOF (uint8_t)0x02 1359 | #define UART_SFIFO_RXUF (uint8_t)0x01 1360 | #define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark 1361 | #define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count 1362 | #define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark 1363 | #define UART0_RCFIFO *(volatile uint8_t *)0x4006A016 // UART FIFO Receive Count 1364 | #define UART0_C7816 *(volatile uint8_t *)0x4006A018 // UART 7816 Control Register 1365 | #define UART0_IE7816 *(volatile uint8_t *)0x4006A019 // UART 7816 Interrupt Enable Register 1366 | #define UART0_IS7816 *(volatile uint8_t *)0x4006A01A // UART 7816 Interrupt Status Register 1367 | #define UART0_WP7816T0 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register 1368 | #define UART0_WP7816T1 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register 1369 | #define UART0_WN7816 *(volatile uint8_t *)0x4006A01C // UART 7816 Wait N Register 1370 | #define UART0_WF7816 *(volatile uint8_t *)0x4006A01D // UART 7816 Wait FD Register 1371 | #define UART0_ET7816 *(volatile uint8_t *)0x4006A01E // UART 7816 Error Threshold Register 1372 | #define UART0_TL7816 *(volatile uint8_t *)0x4006A01F // UART 7816 Transmit Length Register 1373 | #define UART0_C6 *(volatile uint8_t *)0x4006A021 // UART CEA709.1-B Control Register 6 1374 | #define UART0_PCTH *(volatile uint8_t *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High 1375 | #define UART0_PCTL *(volatile uint8_t *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low 1376 | #define UART0_B1T *(volatile uint8_t *)0x4006A024 // UART CEA709.1-B Beta1 Timer 1377 | #define UART0_SDTH *(volatile uint8_t *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High 1378 | #define UART0_SDTL *(volatile uint8_t *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low 1379 | #define UART0_PRE *(volatile uint8_t *)0x4006A027 // UART CEA709.1-B Preamble 1380 | #define UART0_TPL *(volatile uint8_t *)0x4006A028 // UART CEA709.1-B Transmit Packet Length 1381 | #define UART0_IE *(volatile uint8_t *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register 1382 | #define UART0_WB *(volatile uint8_t *)0x4006A02A // UART CEA709.1-B WBASE 1383 | #define UART0_S3 *(volatile uint8_t *)0x4006A02B // UART CEA709.1-B Status Register 1384 | #define UART0_S4 *(volatile uint8_t *)0x4006A02C // UART CEA709.1-B Status Register 1385 | #define UART0_RPL *(volatile uint8_t *)0x4006A02D // UART CEA709.1-B Received Packet Length 1386 | #define UART0_RPREL *(volatile uint8_t *)0x4006A02E // UART CEA709.1-B Received Preamble Length 1387 | #define UART0_CPW *(volatile uint8_t *)0x4006A02F // UART CEA709.1-B Collision Pulse Width 1388 | #define UART0_RIDT *(volatile uint8_t *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time 1389 | #define UART0_TIDT *(volatile uint8_t *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time 1390 | #define UART1_BDH *(volatile uint8_t *)0x4006B000 // UART Baud Rate Registers: High 1391 | #define UART1_BDL *(volatile uint8_t *)0x4006B001 // UART Baud Rate Registers: Low 1392 | #define UART1_C1 *(volatile uint8_t *)0x4006B002 // UART Control Register 1 1393 | #define UART1_C2 *(volatile uint8_t *)0x4006B003 // UART Control Register 2 1394 | #define UART1_S1 *(volatile uint8_t *)0x4006B004 // UART Status Register 1 1395 | #define UART1_S2 *(volatile uint8_t *)0x4006B005 // UART Status Register 2 1396 | #define UART1_C3 *(volatile uint8_t *)0x4006B006 // UART Control Register 3 1397 | #define UART1_D *(volatile uint8_t *)0x4006B007 // UART Data Register 1398 | #define UART1_MA1 *(volatile uint8_t *)0x4006B008 // UART Match Address Registers 1 1399 | #define UART1_MA2 *(volatile uint8_t *)0x4006B009 // UART Match Address Registers 2 1400 | #define UART1_C4 *(volatile uint8_t *)0x4006B00A // UART Control Register 4 1401 | #define UART1_C5 *(volatile uint8_t *)0x4006B00B // UART Control Register 5 1402 | #define UART1_ED *(volatile uint8_t *)0x4006B00C // UART Extended Data Register 1403 | #define UART1_MODEM *(volatile uint8_t *)0x4006B00D // UART Modem Register 1404 | #define UART1_IR *(volatile uint8_t *)0x4006B00E // UART Infrared Register 1405 | #define UART1_PFIFO *(volatile uint8_t *)0x4006B010 // UART FIFO Parameters 1406 | #define UART1_CFIFO *(volatile uint8_t *)0x4006B011 // UART FIFO Control Register 1407 | #define UART1_SFIFO *(volatile uint8_t *)0x4006B012 // UART FIFO Status Register 1408 | #define UART1_TWFIFO *(volatile uint8_t *)0x4006B013 // UART FIFO Transmit Watermark 1409 | #define UART1_TCFIFO *(volatile uint8_t *)0x4006B014 // UART FIFO Transmit Count 1410 | #define UART1_RWFIFO *(volatile uint8_t *)0x4006B015 // UART FIFO Receive Watermark 1411 | #define UART1_RCFIFO *(volatile uint8_t *)0x4006B016 // UART FIFO Receive Count 1412 | #define UART1_C7816 *(volatile uint8_t *)0x4006B018 // UART 7816 Control Register 1413 | #define UART1_IE7816 *(volatile uint8_t *)0x4006B019 // UART 7816 Interrupt Enable Register 1414 | #define UART1_IS7816 *(volatile uint8_t *)0x4006B01A // UART 7816 Interrupt Status Register 1415 | #define UART1_WP7816T0 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register 1416 | #define UART1_WP7816T1 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register 1417 | #define UART1_WN7816 *(volatile uint8_t *)0x4006B01C // UART 7816 Wait N Register 1418 | #define UART1_WF7816 *(volatile uint8_t *)0x4006B01D // UART 7816 Wait FD Register 1419 | #define UART1_ET7816 *(volatile uint8_t *)0x4006B01E // UART 7816 Error Threshold Register 1420 | #define UART1_TL7816 *(volatile uint8_t *)0x4006B01F // UART 7816 Transmit Length Register 1421 | #define UART1_C6 *(volatile uint8_t *)0x4006B021 // UART CEA709.1-B Control Register 6 1422 | #define UART1_PCTH *(volatile uint8_t *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High 1423 | #define UART1_PCTL *(volatile uint8_t *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low 1424 | #define UART1_B1T *(volatile uint8_t *)0x4006B024 // UART CEA709.1-B Beta1 Timer 1425 | #define UART1_SDTH *(volatile uint8_t *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High 1426 | #define UART1_SDTL *(volatile uint8_t *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low 1427 | #define UART1_PRE *(volatile uint8_t *)0x4006B027 // UART CEA709.1-B Preamble 1428 | #define UART1_TPL *(volatile uint8_t *)0x4006B028 // UART CEA709.1-B Transmit Packet Length 1429 | #define UART1_IE *(volatile uint8_t *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register 1430 | #define UART1_WB *(volatile uint8_t *)0x4006B02A // UART CEA709.1-B WBASE 1431 | #define UART1_S3 *(volatile uint8_t *)0x4006B02B // UART CEA709.1-B Status Register 1432 | #define UART1_S4 *(volatile uint8_t *)0x4006B02C // UART CEA709.1-B Status Register 1433 | #define UART1_RPL *(volatile uint8_t *)0x4006B02D // UART CEA709.1-B Received Packet Length 1434 | #define UART1_RPREL *(volatile uint8_t *)0x4006B02E // UART CEA709.1-B Received Preamble Length 1435 | #define UART1_CPW *(volatile uint8_t *)0x4006B02F // UART CEA709.1-B Collision Pulse Width 1436 | #define UART1_RIDT *(volatile uint8_t *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time 1437 | #define UART1_TIDT *(volatile uint8_t *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time 1438 | #define UART2_BDH *(volatile uint8_t *)0x4006C000 // UART Baud Rate Registers: High 1439 | #define UART2_BDL *(volatile uint8_t *)0x4006C001 // UART Baud Rate Registers: Low 1440 | #define UART2_C1 *(volatile uint8_t *)0x4006C002 // UART Control Register 1 1441 | #define UART2_C2 *(volatile uint8_t *)0x4006C003 // UART Control Register 2 1442 | #define UART2_S1 *(volatile uint8_t *)0x4006C004 // UART Status Register 1 1443 | #define UART2_S2 *(volatile uint8_t *)0x4006C005 // UART Status Register 2 1444 | #define UART2_C3 *(volatile uint8_t *)0x4006C006 // UART Control Register 3 1445 | #define UART2_D *(volatile uint8_t *)0x4006C007 // UART Data Register 1446 | #define UART2_MA1 *(volatile uint8_t *)0x4006C008 // UART Match Address Registers 1 1447 | #define UART2_MA2 *(volatile uint8_t *)0x4006C009 // UART Match Address Registers 2 1448 | #define UART2_C4 *(volatile uint8_t *)0x4006C00A // UART Control Register 4 1449 | #define UART2_C5 *(volatile uint8_t *)0x4006C00B // UART Control Register 5 1450 | #define UART2_ED *(volatile uint8_t *)0x4006C00C // UART Extended Data Register 1451 | #define UART2_MODEM *(volatile uint8_t *)0x4006C00D // UART Modem Register 1452 | #define UART2_IR *(volatile uint8_t *)0x4006C00E // UART Infrared Register 1453 | #define UART2_PFIFO *(volatile uint8_t *)0x4006C010 // UART FIFO Parameters 1454 | #define UART2_CFIFO *(volatile uint8_t *)0x4006C011 // UART FIFO Control Register 1455 | #define UART2_SFIFO *(volatile uint8_t *)0x4006C012 // UART FIFO Status Register 1456 | #define UART2_TWFIFO *(volatile uint8_t *)0x4006C013 // UART FIFO Transmit Watermark 1457 | #define UART2_TCFIFO *(volatile uint8_t *)0x4006C014 // UART FIFO Transmit Count 1458 | #define UART2_RWFIFO *(volatile uint8_t *)0x4006C015 // UART FIFO Receive Watermark 1459 | #define UART2_RCFIFO *(volatile uint8_t *)0x4006C016 // UART FIFO Receive Count 1460 | #define UART2_C7816 *(volatile uint8_t *)0x4006C018 // UART 7816 Control Register 1461 | #define UART2_IE7816 *(volatile uint8_t *)0x4006C019 // UART 7816 Interrupt Enable Register 1462 | #define UART2_IS7816 *(volatile uint8_t *)0x4006C01A // UART 7816 Interrupt Status Register 1463 | #define UART2_WP7816T0 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register 1464 | #define UART2_WP7816T1 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register 1465 | #define UART2_WN7816 *(volatile uint8_t *)0x4006C01C // UART 7816 Wait N Register 1466 | #define UART2_WF7816 *(volatile uint8_t *)0x4006C01D // UART 7816 Wait FD Register 1467 | #define UART2_ET7816 *(volatile uint8_t *)0x4006C01E // UART 7816 Error Threshold Register 1468 | #define UART2_TL7816 *(volatile uint8_t *)0x4006C01F // UART 7816 Transmit Length Register 1469 | #define UART2_C6 *(volatile uint8_t *)0x4006C021 // UART CEA709.1-B Control Register 6 1470 | #define UART2_PCTH *(volatile uint8_t *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High 1471 | #define UART2_PCTL *(volatile uint8_t *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low 1472 | #define UART2_B1T *(volatile uint8_t *)0x4006C024 // UART CEA709.1-B Beta1 Timer 1473 | #define UART2_SDTH *(volatile uint8_t *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High 1474 | #define UART2_SDTL *(volatile uint8_t *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low 1475 | #define UART2_PRE *(volatile uint8_t *)0x4006C027 // UART CEA709.1-B Preamble 1476 | #define UART2_TPL *(volatile uint8_t *)0x4006C028 // UART CEA709.1-B Transmit Packet Length 1477 | #define UART2_IE *(volatile uint8_t *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register 1478 | #define UART2_WB *(volatile uint8_t *)0x4006C02A // UART CEA709.1-B WBASE 1479 | #define UART2_S3 *(volatile uint8_t *)0x4006C02B // UART CEA709.1-B Status Register 1480 | #define UART2_S4 *(volatile uint8_t *)0x4006C02C // UART CEA709.1-B Status Register 1481 | #define UART2_RPL *(volatile uint8_t *)0x4006C02D // UART CEA709.1-B Received Packet Length 1482 | #define UART2_RPREL *(volatile uint8_t *)0x4006C02E // UART CEA709.1-B Received Preamble Length 1483 | #define UART2_CPW *(volatile uint8_t *)0x4006C02F // UART CEA709.1-B Collision Pulse Width 1484 | #define UART2_RIDT *(volatile uint8_t *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time 1485 | #define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time 1486 | 1487 | // Chapter 46: Synchronous Audio Interface (SAI) 1488 | #define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register 1489 | #define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register 1490 | #define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register 1491 | #define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register 1492 | #define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register 1493 | #define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register 1494 | #define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register 1495 | #define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register 1496 | #define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register 1497 | #define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register 1498 | #define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register 1499 | #define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register 1500 | #define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register 1501 | #define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register 1502 | #define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register 1503 | #define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register 1504 | #define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register 1505 | #define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register 1506 | #define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register 1507 | #define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register 1508 | 1509 | // I2S (SAI) Transmit Control Registers 1510 | 1511 | // I2Sx_TCSR flags 1512 | #define I2S_TCSR_TE (uint32_t)0x80000000 // Transmitter Enable 1513 | #define I2S_TCSR_STOPE (uint32_t)0x40000000 // Transmitter Enable in Stop mode 1514 | #define I2S_TCSR_DBGE (uint32_t)0x20000000 // Transmitter Enable in Debug mode 1515 | #define I2S_TCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable 1516 | #define I2S_TCSR_FR (uint32_t)0x02000000 // FIFO Reset 1517 | #define I2S_TCSR_SR (uint32_t)0x01000000 // Software Reset 1518 | #define I2S_TCSR_WSF (uint32_t)0x00100000 // Word Start Flag 1519 | #define I2S_TCSR_SEF (uint32_t)0x00080000 // Sync Error Flag 1520 | #define I2S_TCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) 1521 | #define I2S_TCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) 1522 | #define I2S_TCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) 1523 | #define I2S_TCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable 1524 | #define I2S_TCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable 1525 | #define I2S_TCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable 1526 | #define I2S_TCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable 1527 | #define I2S_TCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable 1528 | #define I2S_TCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable 1529 | #define I2S_TCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable 1530 | 1531 | // I2Sx_TCR1 flags 1532 | #define I2S_TCR1_TFW(n) ((uint32_t)n & 0x03) // Transmit FIFO watermark 1533 | 1534 | // I2Sx_TCR2 flags 1535 | #define I2S_TCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 1536 | #define I2S_TCR2_BCD ((uint32_t)1<<24) // Bit clock direction 1537 | #define I2S_TCR2_BCP ((uint32_t)1<<25) // Bit clock polarity 1538 | #define I2S_TCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK 1539 | #define I2S_TCR2_BCI ((uint32_t)1<<28) // Bit clock input 1540 | #define I2S_TCR2_BCS ((uint32_t)1<<29) // Bit clock swap 1541 | #define I2S_TCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver 1542 | 1543 | // I2Sx_TCR3 flags 1544 | #define I2S_TCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration 1545 | #define I2S_TCR3_TCE ((uint32_t)0x10000) // transmit channel enable 1546 | 1547 | // I2Sx_TCR4 flags 1548 | #define I2S_TCR4_FSD ((uint32_t)1) // Frame Sync Direction 1549 | #define I2S_TCR4_FSP ((uint32_t)2) // Frame Sync Polarity 1550 | #define I2S_TCR4_FSE ((uint32_t)8) // Frame Sync Early 1551 | #define I2S_TCR4_MF ((uint32_t)0x10) // MSB First 1552 | #define I2S_TCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width 1553 | #define I2S_TCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size 1554 | 1555 | // I2Sx_TCR5 flags 1556 | #define I2S_TCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted 1557 | #define I2S_TCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width 1558 | #define I2S_TCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width 1559 | 1560 | // I2Sx_TFRn flags 1561 | #define I2S_TFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer 1562 | #define I2S_TFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer 1563 | 1564 | // I2Sx_TMR flags 1565 | #define I2S_TMR_TWM(n) ((uint32_t)n & 0xFFFFFFFF) 1566 | 1567 | // I2S (SAI) Receive Control Registers 1568 | 1569 | // I2Sx_RCSR flags 1570 | #define I2S_RCSR_RE (uint32_t)0x80000000 // Receiver Enable 1571 | #define I2S_RCSR_STOPE (uint32_t)0x40000000 // Receiver Enable in Stop mode 1572 | #define I2S_RCSR_DBGE (uint32_t)0x20000000 // Receiver Enable in Debug mode 1573 | #define I2S_RCSR_BCE (uint32_t)0x10000000 // Bit Clock Enable 1574 | #define I2S_RCSR_FR (uint32_t)0x02000000 // FIFO Reset 1575 | #define I2S_RCSR_SR (uint32_t)0x01000000 // Software Reset 1576 | #define I2S_RCSR_WSF (uint32_t)0x00100000 // Word Start Flag 1577 | #define I2S_RCSR_SEF (uint32_t)0x00080000 // Sync Error Flag 1578 | #define I2S_RCSR_FEF (uint32_t)0x00040000 // FIFO Error Flag (underrun) 1579 | #define I2S_RCSR_FWF (uint32_t)0x00020000 // FIFO Warning Flag (empty) 1580 | #define I2S_RCSR_FRF (uint32_t)0x00010000 // FIFO Request Flag (Data Ready) 1581 | #define I2S_RCSR_WSIE (uint32_t)0x00001000 // Word Start Interrupt Enable 1582 | #define I2S_RCSR_SEIE (uint32_t)0x00000800 // Sync Error Interrupt Enable 1583 | #define I2S_RCSR_FEIE (uint32_t)0x00000400 // FIFO Error Interrupt Enable 1584 | #define I2S_RCSR_FWIE (uint32_t)0x00000200 // FIFO Warning Interrupt Enable 1585 | #define I2S_RCSR_FRIE (uint32_t)0x00000100 // FIFO Request Interrupt Enable 1586 | #define I2S_RCSR_FWDE (uint32_t)0x00000002 // FIFO Warning DMA Enable 1587 | #define I2S_RCSR_FRDE (uint32_t)0x00000001 // FIFO Request DMA Enable 1588 | 1589 | // I2Sx_RCR1 flags 1590 | #define I2S_RCR1_RFW(n) ((uint32_t)n & 0x03) // Receive FIFO watermark 1591 | 1592 | // I2Sx_RCR2 flags 1593 | #define I2S_RCR2_DIV(n) ((uint32_t)n & 0xff) // Bit clock divide by (DIV+1)*2 1594 | #define I2S_RCR2_BCD ((uint32_t)1<<24) // Bit clock direction 1595 | #define I2S_RCR2_BCP ((uint32_t)1<<25) // Bit clock polarity 1596 | #define I2S_RCR2_MSEL(n) ((uint32_t)(n & 3)<<26) // MCLK select, 0=bus clock, 1=I2S0_MCLK 1597 | #define I2S_RCR2_BCI ((uint32_t)1<<28) // Bit clock input 1598 | #define I2S_RCR2_BCS ((uint32_t)1<<29) // Bit clock swap 1599 | #define I2S_RCR2_SYNC(n) ((uint32_t)(n & 3)<<30) // 0=async 1=sync with receiver 1600 | 1601 | // I2Sx_RCR3 flags 1602 | #define I2S_RCR3_WDFL(n) ((uint32_t)n & 0x0f) // word flag configuration 1603 | #define I2S_RCR3_RCE ((uint32_t)0x10000) // receive channel enable 1604 | 1605 | // I2Sx_RCR4 flags 1606 | #define I2S_RCR4_FSD ((uint32_t)1) // Frame Sync Direction 1607 | #define I2S_RCR4_FSP ((uint32_t)2) // Frame Sync Polarity 1608 | #define I2S_RCR4_FSE ((uint32_t)8) // Frame Sync Early 1609 | #define I2S_RCR4_MF ((uint32_t)0x10) // MSB First 1610 | #define I2S_RCR4_SYWD(n) ((uint32_t)(n & 0x1f)<<8) // Sync Width 1611 | #define I2S_RCR4_FRSZ(n) ((uint32_t)(n & 0x0f)<<16) // Frame Size 1612 | 1613 | // I2Sx_RCR5 flags 1614 | #define I2S_RCR5_FBT(n) ((uint32_t)(n & 0x1f)<<8) // First Bit Shifted 1615 | #define I2S_RCR5_W0W(n) ((uint32_t)(n & 0x1f)<<16) // Word 0 Width 1616 | #define I2S_RCR5_WNW(n) ((uint32_t)(n & 0x1f)<<24) // Word N Width 1617 | 1618 | // I2Sx_RFRn flags 1619 | #define I2S_RFR_RFP(n) ((uint32_t)n & 7) // read FIFO pointer 1620 | #define I2S_RFR_WFP(n) ((uint32_t)(n & 7)<<16) // write FIFO pointer 1621 | 1622 | // I2Sx_RMR flags 1623 | #define I2S_RMR_RWM(n) ((uint32_t)n & 0xFFFFFFFF) 1624 | 1625 | // I2S (SAI) MCLK Registers 1626 | 1627 | // I2Sx_MCR flags 1628 | #define I2S_MCR_DUF ((uint32_t)1<<31) // Divider Update Flag 1629 | #define I2S_MCR_MOE ((uint32_t)1<<30) // MCLK Output Enable 1630 | #define I2S_MCR_MICS(n) ((uint32_t)(n & 3)<<24) // MCLK Input Clock Select 1631 | 1632 | // I2Sx_MDR flags 1633 | #define I2S_MDR_FRACT(n) ((uint32_t)(n & 0xff)<<12) // MCLK Fraction 1634 | #define I2S_MDR_DIVIDE(n) ((uint32_t)(n & 0xfff)) // MCLK Divide 1635 | 1636 | 1637 | // Chapter 47: General-Purpose Input/Output (GPIO) 1638 | #define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register 1639 | #define GPIOA_PSOR *(volatile uint32_t *)0x400FF004 // Port Set Output Register 1640 | #define GPIOA_PCOR *(volatile uint32_t *)0x400FF008 // Port Clear Output Register 1641 | #define GPIOA_PTOR *(volatile uint32_t *)0x400FF00C // Port Toggle Output Register 1642 | #define GPIOA_PDIR *(volatile uint32_t *)0x400FF010 // Port Data Input Register 1643 | #define GPIOA_PDDR *(volatile uint32_t *)0x400FF014 // Port Data Direction Register 1644 | #define GPIOB_PDOR *(volatile uint32_t *)0x400FF040 // Port Data Output Register 1645 | #define GPIOB_PSOR *(volatile uint32_t *)0x400FF044 // Port Set Output Register 1646 | #define GPIOB_PCOR *(volatile uint32_t *)0x400FF048 // Port Clear Output Register 1647 | #define GPIOB_PTOR *(volatile uint32_t *)0x400FF04C // Port Toggle Output Register 1648 | #define GPIOB_PDIR *(volatile uint32_t *)0x400FF050 // Port Data Input Register 1649 | #define GPIOB_PDDR *(volatile uint32_t *)0x400FF054 // Port Data Direction Register 1650 | #define GPIOC_PDOR *(volatile uint32_t *)0x400FF080 // Port Data Output Register 1651 | #define GPIOC_PSOR *(volatile uint32_t *)0x400FF084 // Port Set Output Register 1652 | #define GPIOC_PCOR *(volatile uint32_t *)0x400FF088 // Port Clear Output Register 1653 | #define GPIOC_PTOR *(volatile uint32_t *)0x400FF08C // Port Toggle Output Register 1654 | #define GPIOC_PDIR *(volatile uint32_t *)0x400FF090 // Port Data Input Register 1655 | #define GPIOC_PDDR *(volatile uint32_t *)0x400FF094 // Port Data Direction Register 1656 | #define GPIOD_PDOR *(volatile uint32_t *)0x400FF0C0 // Port Data Output Register 1657 | #define GPIOD_PSOR *(volatile uint32_t *)0x400FF0C4 // Port Set Output Register 1658 | #define GPIOD_PCOR *(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register 1659 | #define GPIOD_PTOR *(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register 1660 | #define GPIOD_PDIR *(volatile uint32_t *)0x400FF0D0 // Port Data Input Register 1661 | #define GPIOD_PDDR *(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register 1662 | #define GPIOE_PDOR *(volatile uint32_t *)0x400FF100 // Port Data Output Register 1663 | #define GPIOE_PSOR *(volatile uint32_t *)0x400FF104 // Port Set Output Register 1664 | #define GPIOE_PCOR *(volatile uint32_t *)0x400FF108 // Port Clear Output Register 1665 | #define GPIOE_PTOR *(volatile uint32_t *)0x400FF10C // Port Toggle Output Register 1666 | #define GPIOE_PDIR *(volatile uint32_t *)0x400FF110 // Port Data Input Register 1667 | #define GPIOE_PDDR *(volatile uint32_t *)0x400FF114 // Port Data Direction Register 1668 | 1669 | // Chapter 48: Touch sense input (TSI) 1670 | #define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register 1671 | #define TSI_GENCS_LPCLKS (uint32_t)0x10000000 // 1672 | #define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) // 1673 | #define TSI_GENCS_NSCN(n) (((n) & 31) << 19) // 1674 | #define TSI_GENCS_PS(n) (((n) & 7) << 16) // 1675 | #define TSI_GENCS_EOSF (uint32_t)0x00008000 // 1676 | #define TSI_GENCS_OUTRGF (uint32_t)0x00004000 // 1677 | #define TSI_GENCS_EXTERF (uint32_t)0x00002000 // 1678 | #define TSI_GENCS_OVRF (uint32_t)0x00001000 // 1679 | #define TSI_GENCS_SCNIP (uint32_t)0x00000200 // 1680 | #define TSI_GENCS_SWTS (uint32_t)0x00000100 // 1681 | #define TSI_GENCS_TSIEN (uint32_t)0x00000080 // 1682 | #define TSI_GENCS_TSIIE (uint32_t)0x00000040 // 1683 | #define TSI_GENCS_ERIE (uint32_t)0x00000020 // 1684 | #define TSI_GENCS_ESOR (uint32_t)0x00000010 // 1685 | #define TSI_GENCS_STM (uint32_t)0x00000002 // 1686 | #define TSI_GENCS_STPE (uint32_t)0x00000001 // 1687 | #define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register 1688 | #define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) // 1689 | #define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) // 1690 | #define TSI_SCANC_SMOD(n) (((n) & 255) << 8) // 1691 | #define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) // 1692 | #define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) // 1693 | #define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register 1694 | #define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register 1695 | #define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register 1696 | #define TSI0_CNTR3 *(volatile uint32_t *)0x40045104 // Counter Register 1697 | #define TSI0_CNTR5 *(volatile uint32_t *)0x40045108 // Counter Register 1698 | #define TSI0_CNTR7 *(volatile uint32_t *)0x4004510C // Counter Register 1699 | #define TSI0_CNTR9 *(volatile uint32_t *)0x40045110 // Counter Register 1700 | #define TSI0_CNTR11 *(volatile uint32_t *)0x40045114 // Counter Register 1701 | #define TSI0_CNTR13 *(volatile uint32_t *)0x40045118 // Counter Register 1702 | #define TSI0_CNTR15 *(volatile uint32_t *)0x4004511C // Counter Register 1703 | #define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register 1704 | 1705 | // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750) 1706 | #define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31))) 1707 | #define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31))) 1708 | #define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31))) 1709 | #define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31))) 1710 | 1711 | #define NVIC_ISER0 *(volatile uint32_t *)0xE000E100 1712 | #define NVIC_ISER1 *(volatile uint32_t *)0xE000E104 1713 | #define NVIC_ICER0 *(volatile uint32_t *)0xE000E180 1714 | #define NVIC_ICER1 *(volatile uint32_t *)0xE000E184 1715 | 1716 | //#define NVIC_SET_PRIORITY(n, p) 1717 | #define IRQ_DMA_CH0 0 1718 | #define IRQ_DMA_CH1 1 1719 | #define IRQ_DMA_CH2 2 1720 | #define IRQ_DMA_CH3 3 1721 | #define IRQ_DMA_ERROR 4 1722 | #define IRQ_FTFL_COMPLETE 6 1723 | #define IRQ_FTFL_COLLISION 7 1724 | #define IRQ_LOW_VOLTAGE 8 1725 | #define IRQ_LLWU 9 1726 | #define IRQ_WDOG 10 1727 | #define IRQ_I2C0 11 1728 | #define IRQ_SPI0 12 1729 | #define IRQ_I2S0_TX 13 1730 | #define IRQ_I2S0_RX 14 1731 | #define IRQ_UART0_LON 15 1732 | #define IRQ_UART0_STATUS 16 1733 | #define IRQ_UART0_ERROR 17 1734 | #define IRQ_UART1_STATUS 18 1735 | #define IRQ_UART1_ERROR 19 1736 | #define IRQ_UART2_STATUS 20 1737 | #define IRQ_UART2_ERROR 21 1738 | #define IRQ_ADC0 22 1739 | #define IRQ_CMP0 23 1740 | #define IRQ_CMP1 24 1741 | #define IRQ_FTM0 25 1742 | #define IRQ_FTM1 26 1743 | #define IRQ_CMT 27 1744 | #define IRQ_RTC_ALARM 28 1745 | #define IRQ_RTC_SECOND 29 1746 | #define IRQ_PIT_CH0 30 1747 | #define IRQ_PIT_CH1 31 1748 | #define IRQ_PIT_CH2 32 1749 | #define IRQ_PIT_CH3 33 1750 | #define IRQ_PDB 34 1751 | #define IRQ_USBOTG 35 1752 | #define IRQ_USBDCD 36 1753 | #define IRQ_TSI 37 1754 | #define IRQ_MCG 38 1755 | #define IRQ_LPTMR 39 1756 | #define IRQ_PORTA 40 1757 | #define IRQ_PORTB 41 1758 | #define IRQ_PORTC 42 1759 | #define IRQ_PORTD 43 1760 | #define IRQ_PORTE 44 1761 | #define IRQ_SOFTWARE 45 1762 | 1763 | 1764 | #define __disable_irq() asm volatile("CPSID i"); 1765 | #define __enable_irq() asm volatile("CPSIE i"); 1766 | 1767 | // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708 1768 | #define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register 1769 | #define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State 1770 | #define SCB_ICSR_PENDSTSET (uint32_t)0x04000000 1771 | #define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset 1772 | #define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control 1773 | #define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register 1774 | #define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control 1775 | #define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1 1776 | #define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2 1777 | #define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3 1778 | #define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State 1779 | #define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register 1780 | #define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status 1781 | #define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status 1782 | #define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address 1783 | 1784 | #define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status 1785 | #define SYST_CSR_COUNTFLAG (uint32_t)0x00010000 1786 | #define SYST_CSR_CLKSOURCE (uint32_t)0x00000004 1787 | #define SYST_CSR_TICKINT (uint32_t)0x00000002 1788 | #define SYST_CSR_ENABLE (uint32_t)0x00000001 1789 | #define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register 1790 | #define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register 1791 | #define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value 1792 | 1793 | 1794 | #define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control 1795 | #define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks 1796 | #define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register 1797 | #define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count 1798 | #define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register 1799 | 1800 | 1801 | extern void nmi_isr(void); 1802 | extern void hard_fault_isr(void); 1803 | extern void memmanage_fault_isr(void); 1804 | extern void bus_fault_isr(void); 1805 | extern void usage_fault_isr(void); 1806 | extern void svcall_isr(void); 1807 | extern void debugmonitor_isr(void); 1808 | extern void pendablesrvreq_isr(void); 1809 | extern void systick_isr(void); 1810 | extern void dma_ch0_isr(void); 1811 | extern void dma_ch1_isr(void); 1812 | extern void dma_ch2_isr(void); 1813 | extern void dma_ch3_isr(void); 1814 | extern void dma_error_isr(void); 1815 | extern void flash_cmd_isr(void); 1816 | extern void flash_error_isr(void); 1817 | extern void low_voltage_isr(void); 1818 | extern void wakeup_isr(void); 1819 | extern void watchdog_isr(void); 1820 | extern void i2c0_isr(void); 1821 | extern void spi0_isr(void); 1822 | extern void i2s0_tx_isr(void); 1823 | extern void i2s0_rx_isr(void); 1824 | extern void uart0_lon_isr(void); 1825 | extern void uart0_status_isr(void); 1826 | extern void uart0_error_isr(void); 1827 | extern void uart1_status_isr(void); 1828 | extern void uart1_error_isr(void); 1829 | extern void uart2_status_isr(void); 1830 | extern void uart2_error_isr(void); 1831 | extern void adc0_isr(void); 1832 | extern void cmp0_isr(void); 1833 | extern void cmp1_isr(void); 1834 | extern void ftm0_isr(void); 1835 | extern void ftm1_isr(void); 1836 | extern void cmt_isr(void); 1837 | extern void rtc_alarm_isr(void); 1838 | extern void rtc_seconds_isr(void); 1839 | extern void pit0_isr(void); 1840 | extern void pit1_isr(void); 1841 | extern void pit2_isr(void); 1842 | extern void pit3_isr(void); 1843 | extern void pdb_isr(void); 1844 | extern void usb_isr(void); 1845 | extern void usb_charge_isr(void); 1846 | extern void tsi0_isr(void); 1847 | extern void mcg_isr(void); 1848 | extern void lptmr_isr(void); 1849 | extern void porta_isr(void); 1850 | extern void portb_isr(void); 1851 | extern void portc_isr(void); 1852 | extern void portd_isr(void); 1853 | extern void porte_isr(void); 1854 | extern void software_isr(void); 1855 | 1856 | 1857 | 1858 | 1859 | #ifdef __cplusplus 1860 | } 1861 | #endif 1862 | #endif 1863 | --------------------------------------------------------------------------------