├── report_hu.pdf ├── README.md └── fft_git ├── top.v ├── but64.v ├── tf1.coe ├── tf2.coe ├── tf3.coe └── fft.v /report_hu.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/hxfycy/1024-point-fft/HEAD/report_hu.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 1024-point-fft 2 | This is a Radix-4 1024 point fft module in verilog designed by xiaofeng hu in Hust,Dec.,2018. 3 | 4 | This design uses Vivado 2017.4 IP Core- BRAM Generator to generate BRAM and BROM, The BROM initialization file is included in the root directory. 5 | 6 | Test.ram: This package include the whole test project in Vivado 2017.4 7 | but there still exist some test module I didn't delete, reader can refer to this module for BRAM configuration. 8 | 9 | I also include this design's report in Chinese. 2019.1.16 10 | 11 | -------------------------------------------------------------------------------- /fft_git/top.v: -------------------------------------------------------------------------------- 1 | module top 2 | ( 3 | input clk, 4 | input rxd, 5 | (*mark_debug="true"*)input sdi, 6 | output txd, 7 | (*mark_debug="true"*)output din,sck,cs, 8 | //test 9 | //input nrst, 10 | (*mark_debug="true"*)input start_key 11 | // output reg fft_busy 12 | ); 13 | 14 | //whole module rst 15 | // reg nrst; 16 | reg fft_busy; 17 | wire start_en; 18 | wire start_sync; 19 | wire nrst; 20 | wire rsten; 21 | assign nrst=!rsten; 22 | Falling2En#( 23 | 16 24 | )_en( 25 | clk,start_key, 26 | start_en, start_sync 27 | ); 28 | Rising2En#( 29 | 16 30 | ) 31 | _rst( 32 | clk,start_key, 33 | rsten, 34 | ); 35 | initial fft_busy=1'b0; 36 | 37 | //uart receive 38 | wire [63:0]dout; 39 | wire dout_valid,busy; 40 | //reg start; 41 | 42 | //uart send 43 | wire [63:0]uart_din; 44 | reg uart_start; 45 | wire send_busy; 46 | 47 | //fft_out 48 | wire [9:0]out_cnt; 49 | wire out_avail; 50 | wire [31:0]out_RE; 51 | wire [31:0]out_IM; 52 | 53 | 54 | 55 | UartRx _rx( 56 | clk,nrst,rxd, 57 | dout, 58 | dout_valid, ,busy 59 | ); 60 | 61 | fft_top _top 62 | ( 63 | din,sck,cs, 64 | sdi, 65 | clk, 66 | nrst, 67 | , 68 | start_en&(!fft_busy), 69 | out_cnt, 70 | out_avail, 71 | out_RE, 72 | out_IM 73 | ); 74 | wire ubuf_we; 75 | reg [9:0]ubuf_addr; 76 | wire [63:0]ubuf_data; 77 | reg usend_en; 78 | reg [9:0]usend_addr; 79 | wire [63:0]usend_data; 80 | reg send_ready; 81 | wire cnt_co,cnt0_co,cnt1_co; 82 | wire [9:0] uart_cnt; 83 | counterM 84 | # ( 1024) 85 | cnt2( 86 | clk,!nrst, 87 | uart_cnt, 88 | cnt0_co, 89 | cnt1_co //co-->new enable en-->old enable 90 | ); 91 | counterM 92 | # ( 67) 93 | cnt1( 94 | clk,!nrst, 95 | , 96 | cnt_co, 97 | cnt0_co //co-->new enable en-->old enable 98 | ); 99 | counterM 100 | # (10) 101 | cnt( 102 | clk,!nrst, 103 | , 104 | send_ready, 105 | cnt_co //co-->new enable en-->old enable 106 | ); 107 | always@(posedge clk) 108 | begin 109 | if(start_en) 110 | fft_busy<=1'b1; 111 | else if(cnt1_co) //send finished 112 | fft_busy<=1'b0; 113 | end 114 | 115 | initial send_ready=1'b0; 116 | assign ubuf_we=out_avail; 117 | assign ubuf_data={out_RE,out_IM}; 118 | //assign usend_addr=uart_cnt; 119 | always@(posedge clk) 120 | begin 121 | usend_addr<=uart_cnt; 122 | end 123 | always@(posedge clk) 124 | begin 125 | ubuf_addr<=out_cnt; 126 | if(ubuf_addr==10'd1023) 127 | begin 128 | send_ready<=1'b1; 129 | end 130 | if(cnt1_co) 131 | begin 132 | send_ready<=1'b0; 133 | end 134 | end 135 | 136 | uart_buffer _uart 137 | ( 138 | clk, 139 | ubuf_we, 140 | ubuf_addr, 141 | ubuf_data, 142 | clk, 143 | 1'b1, 144 | usend_addr, 145 | usend_data 146 | ); 147 | 148 | always@(posedge clk) 149 | begin 150 | uart_start<=cnt0_co; 151 | end 152 | assign uart_din=usend_data; 153 | UartTx _tx 154 | ( 155 | clk,nrst, 156 | uart_din, 157 | uart_start, 158 | send_busy,txd 159 | ); 160 | endmodule 161 | 162 | module fft_top 163 | ( 164 | output wire din,sck,cs, 165 | input wire sdi, 166 | input clk, 167 | input nrst, 168 | input enable,//always enable 169 | //input data_ok, 170 | input start, 171 | output [9:0]out_cnt, 172 | output wire out_avail, 173 | output wire [31:0] serialout_RE, 174 | output wire [31:0] serialout_IM 175 | ); 176 | //reg start; 177 | reg data_ok; 178 | initial data_ok=0; 179 | reg[31:0]datain; 180 | initial datain=32'b1; 181 | /* 182 | always@(posedge clk)begin 183 | if(data_ok) 184 | begin 185 | if(datain<32'd256) 186 | datain<=datain+1'b1; 187 | else 188 | datain<=32'b1; 189 | end 190 | end 191 | */ 192 | 193 | wire [63:0]data; 194 | wire [63:0]ram_indata; 195 | 196 | fft _f 197 | ( 198 | clk, 199 | nrst, 200 | 1'b1,//whole module enable signal 201 | data_ok,//indicate data is ready to input 202 | data, 203 | serialout_RE, 204 | serialout_IM, 205 | out_cnt, 206 | out_avail//output data available 207 | ); 208 | //dram instantiation 209 | wire ram_inwe; 210 | wire [9:0]ram_inaddr; 211 | wire ram_inok; 212 | reg ram_outen; 213 | wire [9:0]ram_outaddr; 214 | wire [63:0]ram_outdata; 215 | reg [9:0]ram_outcnt; 216 | reg [9:0]ram_outcntd1; 217 | assign ram_outaddr=ram_outcnt; 218 | assign data=ram_outdata; 219 | initial ram_outcnt<=10'b0; 220 | initial ram_outcntd1<=10'b0; 221 | initial ram_outen<=1'b0; 222 | always@(posedge clk) 223 | begin 224 | ram_outcntd1<=ram_outcnt; 225 | end 226 | 227 | reg buffer_enable; 228 | initial buffer_enable=1'b0; 229 | always@(posedge clk) 230 | begin 231 | data_ok<=buffer_enable; 232 | end 233 | always@(posedge clk) 234 | begin 235 | if(ram_inok) 236 | begin 237 | buffer_enable<=1'b1; 238 | ram_outen<=1'b1; 239 | end 240 | else if(ram_outcnt==10'd1023) 241 | begin 242 | buffer_enable<=1'b0; 243 | ram_outen<=1'b0; 244 | end 245 | end 246 | 247 | always@(posedge clk) 248 | begin 249 | if(buffer_enable) 250 | begin 251 | if(ram_outcnt<10'd1023) 252 | begin 253 | ram_outcnt<=ram_outcnt+1'b1; 254 | end 255 | else 256 | begin 257 | ram_outcnt<=1'b0; 258 | end 259 | end 260 | else 261 | begin 262 | ram_outcnt<=10'b0; 263 | end 264 | end 265 | sb8865 _8865 266 | ( 267 | din,sck,cs, 268 | sdi, 269 | clk, 270 | , 271 | ram_indata, 272 | start, 273 | ram_inwe, 274 | ram_inaddr, 275 | ram_inok 276 | //output reg signed [15:0]shiftr, 277 | //output integer i 278 | ); 279 | 280 | adbuffer _buffer 281 | ( 282 | clk, 283 | ram_inwe, 284 | ram_inaddr, 285 | ram_indata, 286 | clk, 287 | ram_outen, 288 | ram_outaddr, 289 | ram_outdata 290 | ); 291 | 292 | endmodule -------------------------------------------------------------------------------- /fft_git/but64.v: -------------------------------------------------------------------------------- 1 | module but64 2 | ( 3 | input [63:0] Y0,Y1,Y2,Y3, 4 | input [2:0] state, //calculation state 5 | input [63:0] TF1,TF2,TF3, //rotation factor 6 | input clk, //posedge clk to latch output data after 1 period, 7 | input nrst, //negedge rst to clr 8 | output reg[63:0] X0,X1,X2,X3 , 9 | input enable, 10 | output reg fft_available 11 | //test 12 | // output wire signed[10:0] O1R,O2R,O3R,O1I,O2I,O3I, 13 | // output wire signed[11:0] U0R,U1R,U0I,U1I, 14 | // output wire signed[11:0] V0R,V1R,V0I,V1I, 15 | // output wire signed[12:0] Z0R,Z1R,Z2R,Z3R,Z0I,Z1I,Z2I,Z3I, 16 | // output reg [7:0]cnto; 17 | 18 | ); 19 | reg enabled1;reg enabled2;reg enabled3; 20 | wire [63:0] O1,O2,O3; //mult output 21 | reg [63:0] Y0d1,Y0d2,Y0d3; 22 | /* 23 | wire [23:0] U0,U1; //12bit 24 | wire [23:0] V0,V1; // 25 | wire [25:0] Z0,Z1,Z2,Z3; //extend one bit to avoid overflow 26 | */ 27 | booth64_cpx _m1(Y1,TF1,O1,clk); 28 | booth64_cpx _m2(Y2,TF2,O2,clk); 29 | booth64_cpx _m3(Y3,TF3,O3,clk); 30 | 31 | wire signed[31:0]Y0R,Y0I,Y1R,Y1I,Y2R,Y2I,Y3R,Y3I; 32 | assign Y0R=Y0d3[63:32];assign Y0I=Y0d3[31:0];assign Y1R=Y1[63:32];assign Y1I=Y1[31:0]; 33 | assign Y2R=Y2[63:32];assign Y2I=Y2[31:0];assign Y3R=Y3[63:32];assign Y3I=Y3[31:0]; 34 | 35 | wire signed[31:0] O1R,O2R,O3R,O1I,O2I,O3I; //b30.8*b32.0 output>>8 cut off first 32 bits, no overflow will happen 36 | wire signed[23:0] O1RR,O2RR,O3RR,O1II,O2II,O3II; 37 | assign O1RR=O1[63:40];assign O1II=O1[31:8];assign O2RR=O2[63:40];assign O2II=O2[31:8];assign O3RR=O3[63:40];assign O3II=O3[31:8]; 38 | assign O1R=O1RR;assign O1I=O1II;assign O2R=O2RR;assign O2I=O2II;assign O3R=O3RR;assign O3I=O3II; 39 | wire signed[31:0] U0R,U1R,U0I,U1I; 40 | assign U0R=Y0R+O2R;//U0=Y0+O2 41 | assign U0I=Y0I+O2I; 42 | assign U1R=Y0R-O2R;//U1=Y0-O2 43 | assign U1I=Y0I-O2I; 44 | 45 | wire signed[31:0] V0R,V1R,V0I,V1I; 46 | assign V0R=O1R+O3R;//V0=O1+O3 47 | assign V0I=O1I+O3I; 48 | assign V1R=O1R-O3R;//V1=O1-O3 49 | assign V1I=O1I-O3I; 50 | 51 | wire signed[31:0] Z0R,Z1R,Z2R,Z3R,Z0I,Z1I,Z2I,Z3I; 52 | assign Z0R=U0R+V0R;assign Z0I=U0I+V0I;//Z0=U0+V0 53 | assign Z1R=U1R+V1I;assign Z1I=U1I-V1R;//Z1=U1-jV1 54 | assign Z2R=U0R-V0R;assign Z2I=U0I-V0I;//Z2=U0-V0 55 | assign Z3R=U1R-V1I;assign Z3I=U1I+V1R;//Z3=U1+jV1 56 | 57 | always@(posedge clk or negedge nrst)begin 58 | if(!nrst) 59 | begin 60 | X0<=64'b0;X1<=64'b0;X2<=64'b0;X3<=64'b0; 61 | fft_available<=1'b0; 62 | enabled1<=1'b0; 63 | enabled2<=1'b0; 64 | enabled3<=1'b0; 65 | Y0d1<=64'b0; 66 | Y0d2<=64'b0; 67 | Y0d3<=64'b0; 68 | end 69 | else if(enable||enabled1||enabled2||enabled3)begin 70 | Y0d1<=Y0; 71 | Y0d2<=Y0d1; 72 | Y0d3<=Y0d2; 73 | X0<={Z0R,Z0I}; 74 | X1<={Z1R,Z1I}; 75 | X2<={Z2R,Z2I}; 76 | X3<={Z3R,Z3I}; 77 | enabled1<=enable; 78 | enabled2<=enabled1; 79 | enabled3<=enabled2; 80 | fft_available<=enabled3; 81 | end 82 | else begin 83 | enabled1<=enable; 84 | enabled2<=enabled1; 85 | enabled3<=enabled2; 86 | fft_available<=enabled3; 87 | X0<=64'b0; 88 | X1<=64'b0; 89 | X2<=64'b0; 90 | X3<=64'b0; 91 | end 92 | end 93 | 94 | endmodule 95 | 96 | module booth64_cpx( 97 | input signed [63:0]mult1,mult2,//a+bi;c+di; 98 | output reg signed [63:0]result,//ac-bd+(ad+bc)i=(A-B)+(B-C)i no overflow wil happen 99 | input clk 100 | ); 101 | wire signed [31:0]a,b,c,d; 102 | assign a=mult1[63:32]; 103 | assign b=mult1[31:0]; 104 | assign c=mult2[63:32]; 105 | assign d=mult2[31:0]; 106 | 107 | wire signed [31:0]tmp_A,tmp_B,tmp_C; //A=a+b, B=c+d, C=b-a 108 | wire signed [31:0]prod_A,prod_B,prod_C;//A=(a+b)c;B=(c+d)b;C=(b-a)d 109 | wire signed [31:0]result_high,result_low; 110 | assign tmp_A=a+b; 111 | assign tmp_B=c+d; 112 | assign tmp_C=b-a; 113 | 114 | booth64 _A(tmp_A,c,clk,prod_A); 115 | booth64 _B(tmp_B,b,clk,prod_B); 116 | booth64 _C(tmp_C,d,clk,prod_C); 117 | 118 | assign result_high=prod_A-prod_B; 119 | assign result_low=prod_B-prod_C; 120 | //assign result={result_high,result_low}; 121 | always@(*) 122 | begin 123 | result<={result_high,result_low}; 124 | end 125 | endmodule 126 | module booth64( 127 | input signed [31:0] mult1,mult2, 128 | input clk, 129 | output reg signed [31:0] part_prod 130 | ); 131 | //reg signed [31:0] part_prod; 132 | //assign result=part_prod; 133 | reg signed[31:0] part_prodA,part_prodB,part_prodC,part_prodD,part_prodE,part_prodF,part_prodG,part_prodH; 134 | reg signed[31:0] part_prod1,part_prod2; 135 | 136 | reg signed[32:0] part_A1,part_A2,part_A3,part_A4,part_A5,part_A6,part_A7,part_A8; 137 | reg signed[32:0] part_A9,part_AA,part_AB,part_AC,part_AD,part_AE,part_AF,part_A0; 138 | 139 | wire signed a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aa,ab,ac,ad,ae,af; 140 | 141 | 142 | assign a0=part_A1[32]; 143 | assign a1=part_A2[32]; 144 | assign a2=part_A3[32]; 145 | assign a3=part_A4[32]; 146 | assign a4=part_A5[32]; 147 | assign a5=part_A6[32]; 148 | assign a6=part_A7[32]; 149 | assign a7=part_A8[32]; 150 | assign a8=part_A9[32]; 151 | assign a9=part_AA[32]; 152 | assign aa=part_AB[32]; 153 | assign ab=part_AC[32]; 154 | assign ac=part_AD[32]; 155 | assign ad=part_AE[32]; 156 | assign ae=part_AF[32]; 157 | assign af=part_A0[32]; 158 | 159 | 160 | always@(posedge clk) 161 | begin //1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 162 | part_prodA<=part_A1[31:0]+ 163 | {part_A2[29:0],2'sb0}; 164 | 165 | part_prodE<={part_A3[27:0],4'sb0}+ 166 | {part_A4[25:0],6'sb0}; 167 | 168 | part_prodB<={part_A5[23:0],8'sb0}+ 169 | {part_A6[21:0],10'sb0}; 170 | part_prodF<={part_A7[19:0],12'sb0}+ 171 | {part_A8[17:0],14'sb0}; 172 | 173 | part_prodC<={part_A9[15:0],16'sb0}+ 174 | {part_AA[13:0],18'sb0}; 175 | part_prodG<={part_AB[11:0],20'sb0}+ 176 | {part_AC[9:0],22'sb0}; 177 | 178 | part_prodD<={part_AD[7:0],24'sb0}+ 179 | {part_AE[5:0],26'sb0}; 180 | part_prodH<={part_AF[3:0],28'sb0}+ 181 | {part_A0[1:0],30'sb0}; 182 | 183 | part_prod1<=part_prodA+part_prodB+part_prodC+part_prodD; 184 | part_prod2<=part_prodE+part_prodF+part_prodG+part_prodH; 185 | 186 | part_prod<=part_prod1+part_prod2; 187 | end 188 | 189 | always@(*) 190 | begin 191 | case(mult1[1:0]) 192 | 2'b00:part_A1=33'b0; 193 | 2'b01:part_A1={mult2[31],mult2}; 194 | 2'b10:part_A1=-{mult2,1'b0}; 195 | 2'b11:part_A1=-{mult2[31],mult2}; 196 | default:part_A1=33'b0; 197 | endcase 198 | 199 | case(mult1[3:1]) 200 | 3'b000:part_A2= 33'b0; 201 | 3'b001:part_A2= {mult2[31],mult2}; 202 | 3'b010:part_A2= {mult2[31],mult2}; 203 | 3'b011:part_A2= {mult2,1'b0}; 204 | 3'b100:part_A2=-{mult2,1'b0}; 205 | 3'b101:part_A2=-{mult2[31],mult2}; 206 | 3'b110:part_A2=-{mult2[31],mult2}; 207 | 3'b111:part_A2= 33'b0; 208 | default:part_A2= 33'b0; 209 | endcase 210 | 211 | 212 | case(mult1[5:3]) 213 | 3'b000:part_A3= 33'b0; 214 | 3'b001:part_A3= {mult2[31],mult2}; 215 | 3'b010:part_A3= {mult2[31],mult2}; 216 | 3'b011:part_A3= {mult2,1'b0}; 217 | 3'b100:part_A3=-{mult2,1'b0}; 218 | 3'b101:part_A3=-{mult2[31],mult2}; 219 | 3'b110:part_A3=-{mult2[31],mult2}; 220 | 3'b111:part_A3= 33'b0; 221 | default:part_A3= 33'b0; 222 | endcase 223 | 224 | case(mult1[7:5]) 225 | 3'b000:part_A4= 33'b0; 226 | 3'b001:part_A4= {mult2[31],mult2}; 227 | 3'b010:part_A4= {mult2[31],mult2}; 228 | 3'b011:part_A4= {mult2,1'b0}; 229 | 3'b100:part_A4=-{mult2,1'b0}; 230 | 3'b101:part_A4=-{mult2[31],mult2}; 231 | 3'b110:part_A4=-{mult2[31],mult2}; 232 | 3'b111:part_A4= 33'b0; 233 | default:part_A4= 33'b0; 234 | endcase 235 | 236 | case(mult1[9:7]) 237 | 3'b000:part_A5= 33'b0; 238 | 3'b001:part_A5= {mult2[31],mult2}; 239 | 3'b010:part_A5= {mult2[31],mult2}; 240 | 3'b011:part_A5= {mult2,1'b0}; 241 | 3'b100:part_A5=-{mult2,1'b0}; 242 | 3'b101:part_A5=-{mult2[31],mult2}; 243 | 3'b110:part_A5=-{mult2[31],mult2}; 244 | 3'b111:part_A5= 33'b0; 245 | default:part_A5= 33'b0; 246 | endcase 247 | 248 | 249 | case(mult1[11:9]) 250 | 3'b000:part_A6= 33'b0; 251 | 3'b001:part_A6= {mult2[31],mult2}; 252 | 3'b010:part_A6= {mult2[31],mult2}; 253 | 3'b011:part_A6= {mult2,1'b0}; 254 | 3'b100:part_A6=-{mult2,1'b0}; 255 | 3'b101:part_A6=-{mult2[31],mult2}; 256 | 3'b110:part_A6=-{mult2[31],mult2}; 257 | 3'b111:part_A6= 33'b0; 258 | default:part_A6= 33'b0; 259 | endcase 260 | 261 | case(mult1[13:11]) 262 | 3'b000:part_A7= 33'b0; 263 | 3'b001:part_A7= {mult2[31],mult2}; 264 | 3'b010:part_A7= {mult2[31],mult2}; 265 | 3'b011:part_A7= {mult2,1'b0}; 266 | 3'b100:part_A7=-{mult2,1'b0}; 267 | 3'b101:part_A7=-{mult2[31],mult2}; 268 | 3'b110:part_A7=-{mult2[31],mult2}; 269 | 3'b111:part_A7= 33'b0; 270 | default:part_A7= 33'b0; 271 | endcase 272 | 273 | case(mult1[15:13]) 274 | 3'b000:part_A8= 33'b0; 275 | 3'b001:part_A8= {mult2[31],mult2}; 276 | 3'b010:part_A8= {mult2[31],mult2}; 277 | 3'b011:part_A8= {mult2,1'b0}; 278 | 3'b100:part_A8=-{mult2,1'b0}; 279 | 3'b101:part_A8=-{mult2[31],mult2}; 280 | 3'b110:part_A8=-{mult2[31],mult2}; 281 | 3'b111:part_A8= 33'b0; 282 | default:part_A8= 33'b0; 283 | endcase 284 | 285 | case(mult1[17:15]) 286 | 3'b000:part_A9= 33'b0; 287 | 3'b001:part_A9= {mult2[31],mult2}; 288 | 3'b010:part_A9= {mult2[31],mult2}; 289 | 3'b011:part_A9= {mult2,1'b0}; 290 | 3'b100:part_A9=-{mult2,1'b0}; 291 | 3'b101:part_A9=-{mult2[31],mult2}; 292 | 3'b110:part_A9=-{mult2[31],mult2}; 293 | 3'b111:part_A9= 33'b0; 294 | default:part_A9= 33'b0; 295 | endcase 296 | 297 | case(mult1[19:17]) 298 | 3'b000:part_AA= 33'b0; 299 | 3'b001:part_AA= {mult2[31],mult2}; 300 | 3'b010:part_AA= {mult2[31],mult2}; 301 | 3'b011:part_AA= {mult2,1'b0}; 302 | 3'b100:part_AA=-{mult2,1'b0}; 303 | 3'b101:part_AA=-{mult2[31],mult2}; 304 | 3'b110:part_AA=-{mult2[31],mult2}; 305 | 3'b111:part_AA= 33'b0; 306 | default:part_AA= 33'b0; 307 | endcase 308 | case(mult1[21:19]) 309 | 3'b000:part_AB= 33'b0; 310 | 3'b001:part_AB= {mult2[31],mult2}; 311 | 3'b010:part_AB= {mult2[31],mult2}; 312 | 3'b011:part_AB= {mult2,1'b0}; 313 | 3'b100:part_AB=-{mult2,1'b0}; 314 | 3'b101:part_AB=-{mult2[31],mult2}; 315 | 3'b110:part_AB=-{mult2[31],mult2}; 316 | 3'b111:part_AB= 33'b0; 317 | default:part_AB= 33'b0; 318 | endcase 319 | 320 | case(mult1[23:21]) 321 | 3'b000:part_AC= 33'b0; 322 | 3'b001:part_AC= {mult2[31],mult2}; 323 | 3'b010:part_AC= {mult2[31],mult2}; 324 | 3'b011:part_AC= {mult2,1'b0}; 325 | 3'b100:part_AC=-{mult2,1'b0}; 326 | 3'b101:part_AC=-{mult2[31],mult2}; 327 | 3'b110:part_AC=-{mult2[31],mult2}; 328 | 3'b111:part_AC= 33'b0; 329 | default:part_AC= 33'b0; 330 | endcase 331 | 332 | case(mult1[25:23]) 333 | 3'b000:part_AD= 33'b0; 334 | 3'b001:part_AD= {mult2[31],mult2}; 335 | 3'b010:part_AD= {mult2[31],mult2}; 336 | 3'b011:part_AD= {mult2,1'b0}; 337 | 3'b100:part_AD=-{mult2,1'b0}; 338 | 3'b101:part_AD=-{mult2[31],mult2}; 339 | 3'b110:part_AD=-{mult2[31],mult2}; 340 | 3'b111:part_AD= 33'b0; 341 | default:part_AD= 33'b0; 342 | endcase 343 | 344 | case(mult1[27:25]) 345 | 3'b000:part_AE= 33'b0; 346 | 3'b001:part_AE= {mult2[31],mult2}; 347 | 3'b010:part_AE= {mult2[31],mult2}; 348 | 3'b011:part_AE= {mult2,1'b0}; 349 | 3'b100:part_AE=-{mult2,1'b0}; 350 | 3'b101:part_AE=-{mult2[31],mult2}; 351 | 3'b110:part_AE=-{mult2[31],mult2}; 352 | 3'b111:part_AE= 33'b0; 353 | default:part_AE= 33'b0; 354 | endcase 355 | 356 | case(mult1[29:27]) 357 | 3'b000:part_AF= 33'b0; 358 | 3'b001:part_AF= {mult2[31],mult2}; 359 | 3'b010:part_AF= {mult2[31],mult2}; 360 | 3'b011:part_AF= {mult2,1'b0}; 361 | 3'b100:part_AF=-{mult2,1'b0}; 362 | 3'b101:part_AF=-{mult2[31],mult2}; 363 | 3'b110:part_AF=-{mult2[31],mult2}; 364 | 3'b111:part_AF= 33'b0; 365 | default:part_AF= 33'b0; 366 | endcase 367 | 368 | 369 | case(mult1[31:29]) 370 | 3'b000:part_A0= 33'b0; 371 | 3'b001:part_A0= {mult2[31],mult2}; 372 | 3'b010:part_A0= {mult2[31],mult2}; 373 | 3'b011:part_A0= {mult2,1'b0}; 374 | 3'b100:part_A0=-{mult2,1'b0}; 375 | 3'b101:part_A0=-{mult2[31],mult2}; 376 | 3'b110:part_A0=-{mult2[31],mult2}; 377 | 3'b111:part_A0= 33'b0; 378 | default:part_A0= 33'b0; 379 | endcase 380 | end 381 | 382 | 383 | endmodule -------------------------------------------------------------------------------- /fft_git/tf1.coe: -------------------------------------------------------------------------------- 1 | MEMORY_INITIALIZATION_RADIX=2; 2 | MEMORY_INITIALIZATION_VECTOR= 3 | 0000000000000000000000010000000000000000000000000000000000000000, 4 | 0000000000000000000000010000000011111111111111111111111111111110, 5 | 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1111111111111111111111111101000100000000000000000000000011111100, 250 | 1111111111111111111111111101011000000000000000000000000011111100, 251 | 1111111111111111111111111101101000000000000000000000000011111101, 252 | 1111111111111111111111111101111100000000000000000000000011111110, 253 | 1111111111111111111111111110010000000000000000000000000011111110, 254 | 1111111111111111111111111110100000000000000000000000000011111111, 255 | 1111111111111111111111111110110100000000000000000000000011111111, 256 | 1111111111111111111111111111001000000000000000000000000100000000, 257 | 1111111111111111111111111111011100000000000000000000000100000000, 258 | 1111111111111111111111111111101100000000000000000000000100000000; 259 | -------------------------------------------------------------------------------- /fft_git/fft.v: -------------------------------------------------------------------------------- 1 | module fft 2 | ( 3 | input clk, 4 | input nrst, 5 | input enable,//whole module enable signal 6 | input data_ok,//indicate data is ready to input 7 | input [63:0] serialin, 8 | output wire [31:0] serialout_RE, 9 | output wire [31:0] serialout_IM, 10 | output reg [9:0] out_cnt, 11 | output out_avail//output data available 12 | ); 13 | 14 | 15 | 16 | //input timing: clk __/^^^^\____/^^^^ 17 | // data_ok__/^^^^^^^^^^^^^ 18 | // data ____data0-----data1----- 19 | 20 | //output timing: clk __/^^^^\____/^^^ 21 | // out_avail __/--------------------^^\______ 22 | // out_data___data0-----data1-data3ff\-----not care------- 23 | localparam IDLE=3'b0; 24 | localparam CT0=3'b1; 25 | localparam CT1=3'd2; 26 | localparam CT2=3'd3; 27 | localparam CT3=3'd4; 28 | localparam CT4=3'd5; 29 | localparam OUT=3'd6; 30 | 31 | //output 32 | reg [63:0] serialout; 33 | reg out_delayen; 34 | reg out_available; 35 | assign serialout_RE=serialout[63:32]; 36 | assign serialout_IM=serialout[31:0]; 37 | assign out_avail=out_available|out_delayen; 38 | 39 | //flag and enable 40 | reg input_ok; //input data storage finished 41 | reg out_ok; //data is ready for output 42 | reg out_do; //ram busy in output 43 | reg buten; //butterfly enable signal 44 | reg [2:0] state;//fft state register 45 | 46 | 47 | //buffer 48 | reg [63:0] buf_wdata0; //buffer to ram data 49 | reg [7:0] buf_waddr0; //buffer to ram address 50 | reg [63:0] buf_0[2:0]; //block buffer 51 | reg [1:0] buf_cnt0; //block buffer counter 52 | reg buf_full0; //buffer full flag 53 | reg buf_we0; 54 | 55 | reg [63:0] buf_wdata1; 56 | reg [7:0] buf_waddr1; 57 | reg [63:0] buf_1[2:0]; 58 | reg [1:0] buf_cnt1; 59 | reg buf_full1; 60 | reg buf_we1; 61 | 62 | reg [63:0] buf_wdata2; 63 | reg [7:0] buf_waddr2; 64 | reg [63:0] buf_2[2:0]; 65 | reg [1:0] buf_cnt2; 66 | reg buf_full2; 67 | reg buf_we2; 68 | 69 | reg [63:0] buf_wdata3; 70 | reg [7:0] buf_waddr3; 71 | reg [63:0] buf_3[2:0]; 72 | reg [1:0] buf_cnt3; 73 | reg buf_full3; 74 | reg buf_we3; 75 | 76 | wire buf_clear; 77 | assign buf_clear=(!buf_full0)&&(!buf_full1)&&(!buf_full2)&&(!buf_full3); 78 | 79 | //ram behavior module 80 | reg ram0en; //block enable 81 | reg ram0we; //write enable 82 | reg [7:0] ram0_waddr; // block0 write address 83 | reg [7:0] ram0_raddr; // block0 read address 84 | reg [63:0] ram0_wdata; // block write data 85 | wire[63:0] ram0_rdata; // block read data 86 | reg ram1en; 87 | reg ram1we; 88 | reg [7:0] ram1_waddr; 89 | reg [7:0] ram1_raddr; 90 | reg [63:0] ram1_wdata; 91 | wire[63:0] ram1_rdata; 92 | reg ram2en; 93 | reg ram2we; 94 | reg [7:0] ram2_waddr; 95 | reg [7:0] ram2_raddr; 96 | reg [63:0] ram2_wdata; 97 | wire[63:0] ram2_rdata; 98 | reg ram3en; 99 | reg ram3we; 100 | reg [7:0] ram3_waddr; 101 | reg [7:0] ram3_raddr; 102 | reg [63:0] ram3_wdata; 103 | wire[63:0] ram3_rdata; 104 | 105 | //rom instantiation 106 | reg romen; 107 | reg [7:0]rom_addr; 108 | wire [63:0]TF1,TF2,TF3; 109 | 110 | //ram instantiation 111 | reg ram00en,ram01en,ram02en,ram03en,ram10en,ram11en,ram12en,ram13en; 112 | reg ram00we,ram01we,ram02we,ram03we,ram10we,ram11we,ram12we,ram13we; 113 | reg [7:0]addr00,addr01,addr02,addr03,addr10,addr11,addr12,addr13; 114 | reg [63:0]ram00_wdata,ram01_wdata,ram02_wdata,ram03_wdata,ram10_wdata,ram11_wdata,ram12_wdata,ram13_wdata; 115 | wire [63:0]ram00_rdata,ram01_rdata,ram02_rdata,ram03_rdata,ram10_rdata,ram11_rdata,ram12_rdata,ram13_rdata; 116 | 117 | //butterfly_instantiation 118 | reg [63:0]Y0,Y1,Y2,Y3; 119 | wire [63:0] X0,X1,X2,X3; 120 | wire fft_available;// indicate that FFT_OUT is available 121 | 122 | //pointer and counter 123 | reg [1:0]ram_index;//read ram choose 124 | reg [7:0] cnt; //fft_cnt 125 | reg [7:0] cntd1; //fft_cnt delay 1 T 126 | reg [7:0] cntd2; //fft_cnt delay 2 T 127 | reg [7:0] cntd3; //fft_cnt delay 3 T for adder buffer 128 | reg [7:0] cntd4; //fft_cnt deay 4 T for adder buffer 129 | reg [7:0] cntd5; 130 | reg [9:0] outcnt;//output data counter ,test only 131 | reg [9:0] outcntd1;//output counter delay 1 t 132 | reg [9:0] outcntd2;//output counter delay 2 t 133 | reg [9:0] incnt;//input data counter 134 | 135 | //ram_waddr generation 136 | always@(posedge clk or negedge nrst)begin 137 | if(!nrst) 138 | begin 139 | ram_index<=2'b0; 140 | ram0_waddr<=8'b0;ram1_waddr<=8'b0;ram2_waddr<=8'b0;ram3_waddr<=8'b0; 141 | ram0we<=1'b0;ram1we<=1'b0;ram2we<=1'b0;ram3we<=1'b0; 142 | incnt<=10'b0; 143 | input_ok<=1'b0; 144 | end 145 | else begin 146 | case(state) 147 | IDLE: 148 | begin 149 | if(data_ok&&!input_ok&&enable) 150 | begin 151 | incnt<=incnt+1; 152 | ram0_waddr<=incnt[7:0];ram1_waddr<=incnt[7:0];ram2_waddr<=incnt[7:0];ram3_waddr<=incnt[7:0]; 153 | case(incnt[9:8]) 154 | 2'b00:begin ram0we<=1'b1;ram1we<=1'b0;ram2we<=1'b0;ram3we<=1'b0;ram0_wdata<=serialin; end 155 | 2'b01:begin ram0we<=1'b0;ram1we<=1'b1;ram2we<=1'b0;ram3we<=1'b0;ram1_wdata<=serialin; end 156 | 2'b10:begin ram0we<=1'b0;ram1we<=1'b0;ram2we<=1'b1;ram3we<=1'b0;ram2_wdata<=serialin; end 157 | 2'b11:begin ram0we<=1'b0;ram1we<=1'b0;ram2we<=1'b0;ram3we<=1'b1;ram3_wdata<=serialin; end 158 | default:begin ram0we<=1'b0;ram1we<=1'b0;ram2we<=1'b0;ram3we<=1'b0; end 159 | endcase 160 | if(incnt==10'd1023) 161 | begin 162 | input_ok<=1'b1; //data_input is ok 163 | ram_index<=2'b0; 164 | end 165 | else input_ok<=1'b0; 166 | end 167 | end 168 | CT0: 169 | begin 170 | ram0we<=fft_available;ram1we<=ram0we;ram2we<=ram1we;ram3we<=ram2we; 171 | ram0_waddr<={cntd2[1:0],cntd2[7:2]};ram1_waddr<=ram0_waddr;ram2_waddr<=ram1_waddr; 172 | end 173 | CT1,CT2,CT3:// same as CT0 174 | begin 175 | ram0we<=fft_available;ram1we<=ram0we;ram2we<=ram1we;ram3we<=ram2we; 176 | ram0_waddr<={cntd5[1:0],cntd5[7:2]};ram1_waddr<=ram0_waddr;ram2_waddr<=ram1_waddr; 177 | end 178 | endcase 179 | end 180 | end 181 | 182 | //rom_addr generation 183 | always@(*) 184 | begin 185 | if(!nrst) 186 | begin 187 | romen<=1'b0; 188 | rom_addr<=8'b0; 189 | end 190 | else 191 | begin 192 | case(state) 193 | IDLE: 194 | begin 195 | romen=1'b0; 196 | end 197 | 198 | CT0: 199 | begin 200 | rom_addr=8'b0; 201 | end 202 | 203 | CT1: 204 | begin 205 | rom_addr={cnt[7:6],6'b0}; 206 | end 207 | 208 | CT2: 209 | begin 210 | rom_addr={cnt[7:4],4'b0}; 211 | end 212 | 213 | CT3: 214 | begin 215 | rom_addr={cnt[7:2],2'b0}; 216 | end 217 | 218 | CT4: 219 | begin 220 | rom_addr=cnt; 221 | end 222 | 223 | default: 224 | begin 225 | romen<=1'b0; 226 | rom_addr<=8'b0; 227 | end 228 | endcase 229 | end 230 | end 231 | 232 | //ram_raddr generation 233 | always@(posedge clk or negedge nrst) 234 | begin 235 | if(!nrst) 236 | begin 237 | out_cnt<=10'b0; 238 | outcnt<=10'b0; 239 | outcntd1<=10'b0; 240 | outcntd2<=10'b0; 241 | out_available<=1'b0; 242 | out_delayen<=1'b0; 243 | out_do<=1'b0; 244 | ram0_raddr<=8'b0;ram1_raddr<=8'b0;ram2_raddr<=8'b0;ram3_raddr<=8'b0; 245 | end 246 | else 247 | case(state) 248 | OUT: 249 | begin 250 | if(!out_do) 251 | begin 252 | if(out_ok==1) 253 | begin 254 | out_do<=1'b1; 255 | ram0_raddr<=8'b0;ram1_raddr<=8'b0;ram2_raddr<=8'b0;ram3_raddr<=8'b0; 256 | end 257 | else 258 | begin 259 | ram0_raddr<=8'b0;ram1_raddr<=8'b0;ram2_raddr<=8'b0;ram3_raddr<=8'b0; 260 | ram0en<=1'b1;ram1en<=1'b1;ram2en<=1'b1;ram3en<=1'b1; 261 | end 262 | end 263 | else if(out_do) 264 | begin 265 | outcnt<=outcnt+1'b1; 266 | ram0_raddr<=outcnt[7:0];ram1_raddr<=outcnt[7:0];ram2_raddr<=outcnt[7:0];ram3_raddr<=outcnt[7:0]; 267 | case(outcnt[9:8]) 268 | 2'b00:begin ram0en<=1'b1;ram1en<=1'b0;ram2en<=1'b0;ram3en<=1'b0; end 269 | 2'b01:begin ram0en<=1'b0;ram1en<=1'b1;ram2en<=1'b0;ram3en<=1'b0; end 270 | 2'b10:begin ram0en<=1'b0;ram1en<=1'b0;ram2en<=1'b1;ram3en<=1'b0; end 271 | 2'b11:begin ram0en<=1'b0;ram1en<=1'b0;ram2en<=1'b0;ram3en<=1'b1; end 272 | default:begin ram0en<=1'b0;ram1en<=1'b0;ram2en<=1'b0;ram3en<=1'b0; end 273 | endcase 274 | if(outcnt==10'd1023) 275 | begin 276 | outcnt<=10'b0; 277 | out_do<=1'b0; 278 | //ram0en<=1'b1;ram1en<=1'b1;ram2en<=1'b1;ram3en<=1'b1; 279 | end 280 | end 281 | outcntd1<=outcnt; 282 | outcntd2<=outcntd1; 283 | out_delayen<=out_available; 284 | out_cnt<=outcntd1; 285 | if(outcntd1==10'b1) 286 | begin out_available<=1'b1; end 287 | else if(outcntd2==10'd1023) 288 | begin out_available<=1'b0; end 289 | 290 | case(outcntd2[9:8]) 291 | 2'b00:begin serialout<=ram10_rdata; end 292 | 2'b01:begin serialout<=ram11_rdata; end 293 | 2'b10:begin serialout<=ram12_rdata; end 294 | 2'b11:begin serialout<=ram13_rdata; end 295 | default:serialout<=64'b0; 296 | endcase 297 | end 298 | endcase 299 | end 300 | 301 | //state transition 302 | always@(posedge clk or negedge nrst) 303 | begin 304 | if(!nrst) 305 | begin 306 | state<=IDLE; 307 | ram0en<=0; 308 | ram1en<=0; 309 | ram2en<=0; 310 | ram3en<=0; 311 | ram_index<=1'b0; 312 | out_ok<=1'b0; 313 | cnt<=0; 314 | cntd1<=0; 315 | cntd2<=0; 316 | cntd3<=0; 317 | cntd4<=0; 318 | cntd5<=0; 319 | end 320 | 321 | else case(state) 322 | IDLE: 323 | begin 324 | if(enable&&input_ok&&(incnt==10'b0)) 325 | begin 326 | cnt<=0; 327 | ram_index=1'b0; 328 | state<=CT0; 329 | //buten<=1'b1; 330 | end 331 | else begin 332 | cnt<=8'b0; 333 | cntd1<=8'b0; 334 | cntd2<=8'b0; 335 | cntd3<=8'b0; 336 | cntd4<=8'b0; 337 | cntd5<=8'b0; 338 | ram_index=1'b0; 339 | buten<=1'b0; 340 | //input_ok<=1'b0; 341 | end 342 | end 343 | CT0: 344 | begin 345 | if(cnt==8'b0&&cntd5==8'b0) 346 | begin 347 | buten<=1'b1; 348 | end 349 | if(cntd1==8'd255) 350 | begin 351 | buten<=1'b0; 352 | end 353 | if(cntd5==8'd255) 354 | begin 355 | cnt<=8'd0; 356 | cntd1<=8'd0; 357 | cntd2<=8'd0; 358 | cntd3<=8'd0; 359 | cntd4<=8'b0; 360 | if(buf_clear&&(!ram13we)) 361 | begin 362 | state<=CT1; 363 | cntd5<=8'd0; 364 | end 365 | end 366 | else 367 | begin 368 | cnt<=cnt+1'b1; 369 | cntd1<=cnt; 370 | cntd2<=cntd1; 371 | cntd3<=cntd2; 372 | cntd4<=cntd3; 373 | cntd5<=cntd4; 374 | end 375 | end 376 | 377 | CT1: // same as CT0 378 | begin 379 | if(cnt==8'b0&&cntd5==8'b0) 380 | begin 381 | buten<=1'b1; 382 | end 383 | if(cntd1==8'd255) 384 | begin 385 | buten<=1'b0; 386 | end 387 | if(cntd5==8'd255) 388 | begin 389 | cnt<=8'd0; 390 | cntd1<=8'd0; 391 | cntd2<=8'd0; 392 | cntd3<=8'd0; 393 | cntd4<=8'd0; 394 | if(buf_clear&&(!ram13we)) 395 | begin 396 | state<=CT2; 397 | cntd5<=8'd0; 398 | end 399 | end 400 | else 401 | begin 402 | cnt<=cnt+1'b1; 403 | cntd1<=cnt; 404 | cntd2<=cntd1; 405 | cntd3<=cntd2; 406 | cntd4<=cntd3; 407 | cntd5<=cntd4; 408 | end 409 | 410 | end 411 | CT2: // same as CT0 412 | begin 413 | if(cnt==8'b0&&cntd5==8'b0) 414 | begin 415 | buten<=1'b1; 416 | end 417 | if(cntd1==8'd255) 418 | begin 419 | buten<=1'b0; 420 | end 421 | if(cntd5==8'd255) 422 | begin 423 | cnt<=8'd0; 424 | cntd1<=8'd0; 425 | cntd2<=8'd0; 426 | cntd3<=8'd0; 427 | cntd4<=8'd0; 428 | if(buf_clear&&(!ram13we)) 429 | begin 430 | state<=CT3; 431 | cntd5<=8'd0; 432 | end 433 | end 434 | else 435 | begin 436 | cnt<=cnt+1'b1; 437 | cntd1<=cnt; 438 | cntd2<=cntd1; 439 | cntd3<=cntd2; 440 | cntd4<=cntd3; 441 | cntd5<=cntd4; 442 | end 443 | end 444 | 445 | CT3: // same as CT0 446 | begin 447 | if(cnt==8'b0&&cntd5==8'b0) 448 | begin 449 | buten<=1'b1; 450 | end 451 | if(cntd1==8'd255) 452 | begin 453 | buten<=1'b0; 454 | end 455 | if(cntd5==8'd255) 456 | begin 457 | cnt<=8'd0; 458 | cntd1<=8'd0; 459 | cntd2<=8'b0; 460 | cntd3<=8'b0; 461 | cntd4<=8'b0; 462 | if(buf_clear&&(!ram13we)) 463 | begin 464 | state<=CT4; 465 | cntd5<=8'd0; 466 | end 467 | end 468 | else 469 | begin 470 | cnt<=cnt+1'b1; 471 | cntd1<=cnt; 472 | cntd2<=cntd1; 473 | cntd3<=cntd2; 474 | cntd4<=cntd3; 475 | cntd5<=cntd4; 476 | end 477 | end 478 | 479 | CT4: // same as CT0 480 | begin 481 | 482 | if(cnt==8'b0&&cntd5==8'b0) 483 | begin 484 | buten<=1'b1; 485 | end 486 | if(cntd1==8'd255) 487 | begin 488 | buten<=1'b0; 489 | end 490 | if(cntd5==8'd255) 491 | begin 492 | cnt<=8'd0; 493 | cntd1<=8'd0; 494 | cntd2<=8'b0; 495 | cntd3<=8'b0; 496 | cntd4<=8'b0; 497 | if(buf_clear&&!fft_available) 498 | begin 499 | state<=OUT; 500 | out_ok<=1'b1; 501 | end 502 | end 503 | else 504 | begin 505 | cnt<=cnt+1'b1; 506 | cntd1<=cnt; 507 | cntd2<=cntd1; 508 | cntd3<=cntd2; 509 | cntd4<=cntd3; 510 | cntd5<=cntd4; 511 | end 512 | 513 | end 514 | 515 | OUT: 516 | begin 517 | out_ok<=1'b0; 518 | end 519 | endcase 520 | end 521 | 522 | //buffer behavioral model 523 | always@(posedge clk or negedge nrst) 524 | begin 525 | if(!nrst) 526 | begin 527 | buf_wdata0<=64'b0; 528 | buf_waddr0<=8'b0; 529 | buf_0[0]<=64'b0; 530 | buf_0[1]<=64'b0; 531 | buf_0[2]<=64'b0; 532 | buf_cnt0<=2'b0; 533 | buf_full0<=1'b0; 534 | buf_we0<=1'b0; 535 | 536 | buf_wdata1<=64'b0; 537 | buf_waddr1<=8'b0; 538 | buf_1[0]<=64'b0; 539 | buf_1[1]<=64'b0; 540 | buf_1[2]<=64'b0; 541 | buf_cnt1<=2'b0; 542 | buf_full1<=1'b0; 543 | buf_we1<=1'b0; 544 | 545 | buf_wdata2<=64'b0; 546 | buf_waddr2<=8'b0; 547 | buf_2[0]<=64'b0; 548 | buf_2[1]<=64'b0; 549 | buf_2[2]<=64'b0; 550 | buf_cnt2<=2'b0; 551 | buf_full2<=1'b0; 552 | buf_we2<=1'b0; 553 | 554 | buf_wdata3<=64'b0; 555 | buf_waddr3<=8'b0; 556 | buf_3[0]<=64'b0; 557 | buf_3[1]<=64'b0; 558 | buf_3[2]<=64'b0; 559 | buf_cnt3<=2'b0; 560 | buf_full3<=1'b0; 561 | buf_we3<=1'b0; 562 | 563 | end 564 | 565 | else 566 | begin 567 | if(buf_full0)//buff0 568 | begin 569 | case(state) 570 | CT0: 571 | begin 572 | buf_wdata0<=buf_0[buf_cnt0]; 573 | buf_waddr0<={cntd5[1:0],cntd5[7:2]}; 574 | buf_we0<=1'b1; 575 | if(buf_cnt0==2'd2) 576 | begin 577 | buf_cnt0<=2'b0; 578 | buf_full0<=1'b0; 579 | end 580 | 581 | else buf_cnt0<=buf_cnt0+1'b1; 582 | end 583 | CT1,CT2,CT3://same as CT0, Don't use buffer in CT4 584 | begin 585 | buf_wdata0<=buf_0[buf_cnt0]; 586 | buf_waddr0<={cntd5[1:0],cntd5[7:2]}; 587 | buf_we0<=1'b1; 588 | if(buf_cnt0==2'd2) 589 | begin 590 | buf_cnt0<=2'b0; 591 | buf_full0<=1'b0; 592 | end 593 | else buf_cnt0<=buf_cnt0+1'b1; 594 | end 595 | 596 | default: 597 | begin 598 | buf_wdata0<=64'b0; 599 | buf_waddr0<=8'b0; 600 | buf_we0<=1'b0; 601 | buf_cnt0<=2'b0; 602 | buf_full0<=1'b0; 603 | end 604 | endcase 605 | end 606 | else 607 | begin 608 | case(state) 609 | CT0:if(cntd5[1:0]==2'b0&&fft_available) 610 | begin 611 | buf_wdata0<=X0; 612 | buf_waddr0<={cntd5[1:0],cntd5[7:2]}; 613 | buf_we0<=1'b1; 614 | buf_0[0]<=X1; 615 | buf_0[1]<=X2; 616 | buf_0[2]<=X3; 617 | buf_full0<=1'b1; 618 | end 619 | CT1,CT2,CT3:if(cntd5[1:0]==2'b0&&fft_available) 620 | begin 621 | buf_wdata0<=X0; 622 | buf_waddr0<={cntd5[1:0],cntd5[7:2]}; 623 | buf_we0<=1'b1; 624 | buf_0[0]<=X1; 625 | buf_0[1]<=X2; 626 | buf_0[2]<=X3; 627 | buf_full0<=1'b1; 628 | end 629 | default: 630 | begin 631 | buf_wdata0<=64'b0; 632 | buf_waddr0<=8'b0; 633 | buf_we0<=1'b0; 634 | buf_0[0]<=64'b0; 635 | buf_0[1]<=64'b0; 636 | buf_0[2]<=64'b0; 637 | buf_full0<=1'b0; 638 | end 639 | endcase 640 | end 641 | 642 | 643 | if(buf_full1)//buff1 644 | begin 645 | case(state) 646 | CT0: 647 | begin 648 | buf_wdata1<=buf_1[buf_cnt1]; 649 | buf_waddr1<=buf_waddr0; 650 | buf_we1<=1'b1; 651 | if(buf_cnt1==2'd2) 652 | begin 653 | buf_cnt1<=2'b0; 654 | buf_full1<=1'b0; 655 | end 656 | else buf_cnt1<=buf_cnt1+1'b1; 657 | end 658 | CT1,CT2,CT3: 659 | begin 660 | buf_wdata1<=buf_1[buf_cnt1]; 661 | buf_waddr1<=buf_waddr0; 662 | buf_we1<=1'b1; 663 | if(buf_cnt1==2'd2) 664 | begin 665 | buf_cnt1<=2'b0; 666 | buf_full1<=1'b0; 667 | end 668 | else buf_cnt1<=buf_cnt1+1'b1; 669 | end 670 | default: 671 | begin 672 | buf_wdata1<=64'b0; 673 | buf_waddr1<=8'b0; 674 | buf_we1<=1'b0; 675 | buf_cnt1<=2'b0; 676 | buf_full1<=1'b0; 677 | end 678 | endcase 679 | 680 | end 681 | else begin 682 | case(state) 683 | CT0:if(cntd5[1:0]==2'b1&&fft_available) 684 | begin 685 | buf_wdata1<=X0; 686 | buf_waddr1<=buf_waddr0; 687 | buf_we1<=1'b1; 688 | buf_1[0]<=X1; 689 | buf_1[1]<=X2; 690 | buf_1[2]<=X3; 691 | buf_full1<=1'b1; 692 | end 693 | CT1,CT2,CT3:// 694 | begin 695 | if(cntd5[1:0]==2'b1&&fft_available) 696 | begin 697 | buf_wdata1<=X0; 698 | buf_waddr1<=buf_waddr0; 699 | buf_we1<=1'b1; 700 | buf_1[0]<=X1; 701 | buf_1[1]<=X2; 702 | buf_1[2]<=X3; 703 | buf_full1<=1'b1; 704 | end 705 | end 706 | default: 707 | begin 708 | buf_wdata1<=64'b0; 709 | buf_waddr1<=8'b0; 710 | buf_we1<=1'b0; 711 | buf_1[0]<=64'b0; 712 | buf_1[1]<=64'b0; 713 | buf_1[2]<=64'b0; 714 | buf_full1<=1'b0; 715 | end 716 | endcase 717 | end 718 | 719 | if(buf_full2)//buff2 720 | begin 721 | case(state) 722 | CT0: 723 | begin 724 | buf_wdata2<=buf_2[buf_cnt2]; 725 | buf_waddr2<=buf_waddr1; 726 | buf_we2<=1'b1; 727 | if(buf_cnt2==2'd2) 728 | begin 729 | buf_cnt2<=2'b0; 730 | buf_full2<=1'b0; 731 | end 732 | else buf_cnt2<=buf_cnt2+1'b1; 733 | end 734 | CT1,CT2,CT3: 735 | begin 736 | buf_wdata2<=buf_2[buf_cnt2]; 737 | buf_waddr2<=buf_waddr1; 738 | buf_we2<=1'b1; 739 | if(buf_cnt2==2'd2) 740 | begin 741 | buf_cnt2<=2'b0; 742 | buf_full2<=1'b0; 743 | end 744 | else buf_cnt2<=buf_cnt2+1'b1; 745 | end 746 | default: 747 | begin 748 | buf_wdata2<=64'b0; 749 | buf_waddr2<=8'b0; 750 | buf_we2<=1'b0; 751 | buf_cnt2<=2'b0; 752 | buf_full2<=1'b0; 753 | end 754 | endcase 755 | 756 | end 757 | else 758 | begin 759 | case(state) 760 | CT0:if(cntd5[1:0]==2'b10&&fft_available) 761 | begin 762 | buf_wdata2<=X0; 763 | buf_waddr2<=buf_waddr1; 764 | buf_we2<=1'b1; 765 | buf_2[0]<=X1; 766 | buf_2[1]<=X2; 767 | buf_2[2]<=X3; 768 | buf_full2<=1'b1; 769 | end 770 | CT1,CT2,CT3:if(cntd5[1:0]==2'b10&&fft_available) 771 | begin 772 | buf_wdata2<=X0; 773 | buf_waddr2<=buf_waddr1; 774 | buf_we2<=1'b1; 775 | buf_2[0]<=X1; 776 | buf_2[1]<=X2; 777 | buf_2[2]<=X3; 778 | buf_full2<=1'b1; 779 | end 780 | default: 781 | begin 782 | buf_wdata2<=64'b0; 783 | buf_waddr2<=8'b0; 784 | buf_we2<=1'b0; 785 | buf_2[0]<=64'b0; 786 | buf_2[1]<=64'b0; 787 | buf_2[2]<=64'b0; 788 | buf_full2<=1'b0; 789 | end 790 | endcase 791 | end 792 | 793 | if(buf_full3)//buff3 794 | begin 795 | case(state) 796 | CT0: 797 | begin 798 | buf_wdata3<=buf_3[buf_cnt3]; 799 | buf_waddr3<=buf_waddr2; 800 | buf_we3<=1'b1; 801 | if(buf_cnt3==2'd2) 802 | begin 803 | buf_cnt3<=2'b0; 804 | buf_full3<=1'b0; 805 | end 806 | else buf_cnt3<=buf_cnt3+1'b1; 807 | end 808 | CT1,CT2,CT3: 809 | begin 810 | buf_wdata3<=buf_3[buf_cnt3]; 811 | buf_waddr3<=buf_waddr2; 812 | buf_we3<=1'b1; 813 | if(buf_cnt3==2'd2) 814 | begin 815 | buf_cnt3<=2'b0; 816 | buf_full3<=1'b0; 817 | end 818 | else buf_cnt3<=buf_cnt3+1'b1; 819 | end 820 | default: 821 | begin 822 | buf_wdata3<=64'b0; 823 | buf_waddr3<=64'b0; 824 | buf_we3<=1'b0; 825 | buf_cnt3<=2'b0; 826 | buf_full3<=1'b0; 827 | end 828 | endcase 829 | 830 | end 831 | else 832 | begin 833 | case(state) 834 | CT0:if(cntd5[1:0]==2'd3&&fft_available) 835 | begin 836 | buf_wdata3<=X0; 837 | buf_waddr3<=buf_waddr2; 838 | buf_we3<=1'b1; 839 | buf_3[0]<=X1; 840 | buf_3[1]<=X2; 841 | buf_3[2]<=X3; 842 | buf_full3<=1'b1; 843 | end 844 | CT1,CT2,CT3:if(cntd5[1:0]==2'd3&&fft_available) 845 | begin 846 | buf_wdata3<=X0; 847 | buf_waddr3<=buf_waddr2; 848 | buf_we3<=1'b1; 849 | buf_3[0]<=X1; 850 | buf_3[1]<=X2; 851 | buf_3[2]<=X3; 852 | buf_full3<=1'b1; 853 | end 854 | default: 855 | begin 856 | buf_wdata3<=64'b0; 857 | buf_waddr3<=64'b0; 858 | buf_we3<=1'b0; 859 | buf_3[0]<=64'b0; 860 | buf_3[1]<=64'b0; 861 | buf_3[2]<=64'b0; 862 | buf_full3<=1'b0; 863 | end 864 | endcase 865 | end 866 | 867 | end 868 | end 869 | 870 | 871 | //ram instantiation and MUX 872 | always@(*) 873 | begin 874 | case(state) 875 | IDLE: 876 | begin 877 | ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b0;ram11en=1'b0;ram12en=1'b0;ram13en=1'b0; 878 | ram00we=ram0we; ram01we=ram1we; ram02we=ram2we; ram03we=ram3we;ram10we=0;ram11we=0;ram12we=0;ram13we=0; 879 | addr00=ram0_waddr; addr01=ram1_waddr; addr02=ram2_waddr; addr03=ram3_waddr; 880 | ram00_wdata=ram0_wdata; ram01_wdata=ram1_wdata; ram02_wdata=ram2_wdata; ram03_wdata=ram3_wdata; 881 | end 882 | 883 | CT0: 884 | begin 885 | ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b1;ram11en=1'b1;ram12en=1'b1;ram13en=1'b1; 886 | ram00we=1'b0;ram01we=1'b0;ram02we=1'b0;ram03we=1'b0;ram10we=ram0we;ram11we=ram1we;ram12we=ram2we;ram13we=ram3we; 887 | addr00={cnt[1:0],cnt[7:2]};addr01={cnt[1:0],cnt[7:2]};addr02={cnt[1:0],cnt[7:2]};addr03={cnt[1:0],cnt[7:2]};addr10=buf_waddr0;addr11=buf_waddr1;addr12=buf_waddr2;addr13=buf_waddr3; 888 | ram10_wdata=buf_wdata0;ram11_wdata=buf_wdata1;ram12_wdata=buf_wdata2;ram13_wdata=buf_wdata3; 889 | end 890 | 891 | CT1: 892 | begin 893 | ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b1;ram11en=1'b1;ram12en=1'b1;ram13en=1'b1; 894 | ram00we=ram0we;ram01we=ram1we;ram02we=ram2we;ram03we=ram3we;ram10we=1'b0;ram11we=1'b0;ram12we=1'b0;ram13we=1'b0; 895 | addr00=buf_waddr0;addr01=buf_waddr1;addr02=buf_waddr2;addr03=buf_waddr3;addr10={cnt[7:6],cnt[1:0],cnt[5:2]};addr11=addr10;addr12=addr11;addr13=addr12; 896 | ram00_wdata=buf_wdata0;ram01_wdata=buf_wdata1;ram02_wdata=buf_wdata2;ram03_wdata=buf_wdata3; 897 | end 898 | 899 | CT2: 900 | begin 901 | ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b1;ram11en=1'b1;ram12en=1'b1;ram13en=1'b1; 902 | ram00we=1'b0;ram01we=1'b0;ram02we=1'b0;ram03we=1'b0;ram10we=ram0we;ram11we=ram1we;ram12we=ram2we;ram13we=ram3we; 903 | addr00={cnt[7:4],cnt[1:0],cnt[3:2]};addr01=addr00;addr02=addr00;addr03=addr00;addr10=buf_waddr0;addr11=buf_waddr1;addr12=buf_waddr2;addr13=buf_waddr3; 904 | ram10_wdata=buf_wdata0;ram11_wdata=buf_wdata1;ram12_wdata=buf_wdata2;ram13_wdata=buf_wdata3; 905 | end 906 | 907 | CT3: 908 | begin 909 | ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b1;ram11en=1'b1;ram12en=1'b1;ram13en=1'b1; 910 | ram00we=ram0we;ram01we=ram1we;ram02we=ram2we;ram03we=ram3we;ram10we=1'b0;ram11we=1'b0;ram12we=1'b0;ram13we=1'b0; 911 | addr00=buf_waddr0;addr01=buf_waddr1;addr02=buf_waddr2;addr03=buf_waddr3;addr10=cnt;addr11=addr10;addr12=addr11;addr13=addr12; 912 | ram00_wdata=buf_wdata0;ram01_wdata=buf_wdata1;ram02_wdata=buf_wdata2;ram03_wdata=buf_wdata3; 913 | end 914 | CT4: 915 | begin 916 | ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b1;ram11en=1'b1;ram12en=1'b1;ram13en=1'b1; 917 | ram00we=1'b0;ram01we=1'b0;ram02we=1'b0;ram03we=1'b0;ram10we=fft_available;ram11we=ram10we;ram12we=ram10we;ram13we=ram10we; 918 | addr00=cnt;addr01=addr00;addr02=addr00;addr03=addr00;addr10=cntd5;addr11=addr10;addr12=addr10;addr13=addr10; 919 | ram10_wdata=X0;ram11_wdata=X1;ram12_wdata=X2;ram13_wdata=X3; 920 | end 921 | 922 | OUT: 923 | begin 924 | ram00en=1'b0;ram01en=1'b0;ram02en=1'b0;ram03en=1'b0;ram10en=1'b1;ram11en=1'b1;ram12en=1'b1;ram13en=1'b1; 925 | //test 926 | //ram00en=1'b1;ram01en=1'b1;ram02en=1'b1;ram03en=1'b1;ram10en=1'b0;ram11en=1'b0;ram12en=1'b0;ram13en=1'b0; 927 | //testend 928 | ram00we=0; ram01we=0; ram02we=0; ram03we=0; 929 | ram10we=0; ram11we=0; ram12we=0; ram13we=0; 930 | 931 | addr10=ram0_raddr; addr11=ram1_raddr; addr12=ram2_raddr; addr13=ram3_raddr; 932 | 933 | end 934 | endcase 935 | end 936 | bram_00 _ram00(.clka(clk),.ena(ram00en),.wea(ram00we),.addra(addr00), .dina(ram00_wdata), .douta(ram00_rdata)); 937 | bram_01 _ram01(.clka(clk),.ena(ram01en),.wea(ram01we),.addra(addr01), .dina(ram01_wdata), .douta(ram01_rdata)); 938 | bram_02 _ram02(.clka(clk),.ena(ram02en),.wea(ram02we),.addra(addr02), .dina(ram02_wdata), .douta(ram02_rdata)); 939 | bram_03 _ram03(.clka(clk),.ena(ram03en),.wea(ram03we),.addra(addr03), .dina(ram03_wdata), .douta(ram03_rdata)); 940 | bram_10 _ram10(.clka(clk),.ena(ram10en),.wea(ram10we),.addra(addr10), .dina(ram10_wdata), .douta(ram10_rdata)); 941 | bram_11 _ram11(.clka(clk),.ena(ram11en),.wea(ram11we),.addra(addr11), .dina(ram11_wdata), .douta(ram11_rdata)); 942 | bram_12 _ram12(.clka(clk),.ena(ram12en),.wea(ram12we),.addra(addr12), .dina(ram12_wdata), .douta(ram12_rdata)); 943 | bram_13 _ram13(.clka(clk),.ena(ram13en),.wea(ram13we),.addra(addr13), .dina(ram13_wdata), .douta(ram13_rdata)); 944 | 945 | //rom instantiation 946 | 947 | tf1 _tf1(clk,1'b1,rom_addr,TF1); 948 | tf2 _tf2(clk,1'b1,rom_addr,TF2); 949 | tf3 _tf3(clk,1'b1,rom_addr,TF3); 950 | 951 | 952 | //buterfly unit instantiation and MUX 953 | 954 | always@(*) 955 | begin 956 | case(state) 957 | IDLE: 958 | begin 959 | 960 | end 961 | CT0,CT2,CT4: 962 | begin 963 | Y0=ram00_rdata;Y1=ram01_rdata;Y2=ram02_rdata;Y3=ram03_rdata; 964 | end 965 | CT1,CT3: 966 | begin 967 | Y0=ram10_rdata;Y1=ram11_rdata;Y2=ram12_rdata;Y3=ram13_rdata; 968 | end 969 | 970 | default: 971 | begin 972 | Y0=64'b0;Y1=64'b0;Y2=64'b0;Y3=64'b0; 973 | end 974 | endcase 975 | end 976 | 977 | but64 _but 978 | ( 979 | Y0,Y1,Y2,Y3, 980 | state, //calculation state 981 | TF1,TF2,TF3, //rotation factor 982 | clk, //posedge clk to latch output data after 1 period, 983 | nrst, //negedge rst to clr 984 | X0,X1,X2,X3, 985 | buten, 986 | fft_available 987 | //test 988 | // output wire signed[10:0] O1R,O2R,O3R,O1I,O2I,O3I, 989 | // output wire signed[11:0] U0R,U1R,U0I,U1I, 990 | // output wire signed[11:0] V0R,V1R,V0I,V1I, 991 | // output wire signed[12:0] Z0R,Z1R,Z2R,Z3R,Z0I,Z1I,Z2I,Z3I, 992 | // output reg [7:0]cnto; 993 | 994 | ); 995 | endmodule --------------------------------------------------------------------------------